--- /dev/null
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+\r
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+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>32.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>22</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>20</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>5.10.0.159</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>6.70.1.5793</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>STM32L152xB ST STM32L152xB</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>20</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>20</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibThreads</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>29</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCOptimizationNoSizeConstraints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>STM32L1XX_MD</state>\r
+ <state>USE_STDPERIPH_DRIVER</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
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+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_dxs.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_ecs.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_filter.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_globals.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_linrot.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_object.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_time.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_time_stm32l1xx.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_touchkey.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>System</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\System\startup_stm32l1xx_md.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\System\system_stm32l1xx.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\discover_functions.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\icc_measure.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\icc_measure_Ram.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\stm32l1xx_it.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\tsl_user.c</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 09-March-2012\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
+ * This file contains all the peripheral register's definitions, bits \r
+ * definitions and memory mapping for STM32L1xx High-, Medium-density\r
+ * and Medium-density Plus devices.\r
+ *\r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The device used in the target application\r
+ * - To use or not the peripheral\92s drivers in application code(i.e. \r
+ * code will be based on direct access to peripheral\92s registers \r
+ * rather than drivers API), this option is controlled by \r
+ * "#define USE_STDPERIPH_DRIVER"\r
+ * - To change few application-specific parameters such as the HSE \r
+ * crystal frequency\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral\92s registers hardware\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32L1XX_H\r
+#define __STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM32L device used in your \r
+ application \r
+ */\r
+\r
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)\r
+ /* #define STM32L1XX_MD */ /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */\r
+ /* #define STM32L1XX_MDP */ /*!< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices */\r
+ #define STM32L1XX_HD /*!< STM32L1XX_HD: STM32L Ultra Low Power High-density devices */\r
+#endif\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+\r
+ - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx \r
+ microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\r
+ - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and \r
+ STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.\r
+ - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx \r
+ microcontrollers where the Flash memory density is 384 Kbytes.\r
+ */\r
+\r
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)\r
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"\r
+#endif\r
+\r
+#if !defined USE_STDPERIPH_DRIVER\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_STDPERIPH_DRIVER*/\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application \r
+ \r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */\r
+#if !defined (HSE_VALUE)\r
+#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+ Timeout value \r
+ */\r
+#if !defined (HSE_STARTUP_TIMEOUT)\r
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup \r
+ Timeout value \r
+ */\r
+#if !defined (HSI_STARTUP_TIMEOUT)\r
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */\r
+#endif\r
+\r
+#if !defined (HSI_VALUE)\r
+#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#endif\r
+\r
+#if !defined (LSI_VALUE)\r
+#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#endif\r
+\r
+#if !defined (LSE_VALUE)\r
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */\r
+#endif\r
+\r
+/**\r
+ * @brief STM32L1xx Standard Peripheral Library version number V1.1.1\r
+ */\r
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */\r
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */\r
+#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_RC))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */\r
+#define __MPU_PRESENT 1 /*!< STM32L provides MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+ \r
+/*!< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** STM32L specific Interrupt Numbers ***********************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */\r
+ USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */\r
+ DAC_IRQn = 21, /*!< DAC Interrupt */\r
+ COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ LCD_IRQn = 24, /*!< LCD Interrupt */\r
+ TIM9_IRQn = 25, /*!< TIM9 global Interrupt */\r
+ TIM10_IRQn = 26, /*!< TIM10 global Interrupt */\r
+ TIM11_IRQn = 27, /*!< TIM11 global Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM6_IRQn = 43, /*!< TIM6 global Interrupt */\r
+#ifdef STM32L1XX_MD\r
+ TIM7_IRQn = 44 /*!< TIM7 global Interrupt */\r
+#endif\r
+\r
+#ifdef STM32L1XX_MDP\r
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */\r
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */\r
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */\r
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */\r
+ AES_IRQn = 55, /*!< AES global Interrupt */\r
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */\r
+#endif\r
+\r
+#ifdef STM32L1XX_HD\r
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */\r
+ SDIO_IRQn = 45, /*!< SDIO global Interrupt */\r
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 48, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 49, /*!< UART5 global Interrupt */\r
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */\r
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */\r
+ AES_IRQn = 55, /*!< AES global Interrupt */\r
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */\r
+#endif\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm3.h"\r
+#include "system_stm32l1xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/** \r
+ * @brief __RAM_FUNC definition\r
+ */ \r
+#if defined ( __CC_ARM )\r
+/* ARM Compiler\r
+ ------------\r
+ RAM functions are defined using the toolchain options. \r
+ Functions that are executed in RAM should reside in a separate source \r
+ module. Using the 'Options for File' dialog you can simply change the \r
+ 'Code / Const' area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the \r
+ 'Options for Target' dialog. \r
+*/\r
+ #define __RAM_FUNC FLASH_Status \r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+ RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
+*/\r
+ #define __RAM_FUNC __ramfunc FLASH_Status\r
+\r
+#elif defined ( __GNUC__ )\r
+/* GNU Compiler\r
+ ------------\r
+ RAM functions are defined using a specific toolchain attribute \r
+ "__attribute__((section(".data")))". \r
+*/\r
+ #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))\r
+\r
+#elif defined ( __TASKING__ )\r
+/* TASKING Compiler\r
+ ----------------\r
+ RAM functions are defined using a specific toolchain pragma. This pragma is \r
+ defined in the stm32l1xx_flash_ramfunc.c \r
+*/\r
+ #define __RAM_FUNC FLASH_Status\r
+\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */\r
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */\r
+ __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */\r
+ __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief AES hardware accelerator\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */\r
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */\r
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */\r
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */\r
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */\r
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */\r
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */\r
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */\r
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */\r
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */\r
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */\r
+} AES_TypeDef;\r
+\r
+/** \r
+ * @brief Comparator \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */\r
+} COMP_TypeDef;\r
+\r
+/** \r
+ * @brief CRC calculation unit\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ \r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */\r
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */\r
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */\r
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */\r
+} DMA_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!< EXTI interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!< EXTI event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!< EXTI rising edge trigger selection register, Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!< EXTI software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!< EXTI pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */\r
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */\r
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */\r
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */\r
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */\r
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */\r
+ __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */\r
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */\r
+ uint32_t RESERVED[23]; /*!< Reserved, 0x24 */\r
+ __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */\r
+ __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */\r
+} FLASH_TypeDef;\r
+\r
+/** \r
+ * @brief Option Bytes Registers\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */\r
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */\r
+ __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */\r
+ __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */\r
+ __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */\r
+ __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */\r
+ __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */\r
+ __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */\r
+} OB_TypeDef;\r
+\r
+/** \r
+ * @brief Operational Amplifier (OPAMP)\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */\r
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ \r
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */\r
+} OPAMP_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r
+} FSMC_Bank1_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank1E\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FSMC_Bank1E_TypeDef; \r
+\r
+/** \r
+ * @brief General Purpose IO\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x12 */\r
+ __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x16 */\r
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */\r
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */\r
+ __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x2A */\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief SysTem Configuration\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */\r
+} IWDG_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief LCD\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */\r
+ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */\r
+ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */\r
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */\r
+ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */\r
+} LCD_TypeDef;\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */\r
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */\r
+} PWR_TypeDef;\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */\r
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */\r
+ __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */\r
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */\r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Routing Interface \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */\r
+ __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */\r
+ __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */\r
+ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */\r
+ __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */\r
+ __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */\r
+ __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */\r
+} RI_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ \r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */\r
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */\r
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */\r
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */\r
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */\r
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */\r
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */\r
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */\r
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */\r
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */\r
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */\r
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+/** \r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */\r
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */\r
+} SDIO_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ uint16_t RESERVED10; /*!< Reserved, 0x2A */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ uint32_t RESERVED12; /*!< Reserved, 0x30 */ \r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ \r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ \r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ uint32_t RESERVED17; /*!< Reserved, 0x44 */ \r
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ uint16_t RESERVED18; /*!< Reserved, 0x4A */ \r
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ uint16_t RESERVED19; /*!< Reserved, 0x4E */ \r
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ uint16_t RESERVED20; /*!< Reserved, 0x52 */\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+} USART_TypeDef;\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+\r
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\r
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
+\r
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */\r
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
+\r
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\r
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\r
+\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define LCD_BASE (APB1PERIPH_BASE + 0x2400)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)\r
+#define RI_BASE (APB1PERIPH_BASE + 0x7C04)\r
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)\r
+\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2700)\r
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
+\r
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)\r
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)\r
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800)\r
+#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)\r
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)\r
+#define RCC_BASE (AHBPERIPH_BASE + 0x3800)\r
+\r
+\r
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */\r
+#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */\r
+\r
+#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)\r
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)\r
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)\r
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)\r
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)\r
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)\r
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)\r
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)\r
+\r
+#define DMA2_BASE (AHBPERIPH_BASE + 0x6400)\r
+#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)\r
+#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)\r
+#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)\r
+#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)\r
+#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)\r
+\r
+#define AES_BASE ((uint32_t)0x50060000)\r
+\r
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */\r
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */\r
+\r
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define LCD ((LCD_TypeDef *) LCD_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define COMP ((COMP_TypeDef *) COMP_BASE)\r
+#define RI ((RI_TypeDef *) RI_BASE)\r
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
+\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\r
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\r
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\r
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\r
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\r
+\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define OB ((OB_TypeDef *) OB_BASE) \r
+\r
+#define AES ((AES_TypeDef *) AES_BASE)\r
+\r
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r
+\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers Bits Definition */\r
+/******************************************************************************/\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter (ADC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */\r
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */\r
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */\r
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */\r
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */\r
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */\r
+#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */\r
+#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */\r
+#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */\r
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */\r
+\r
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */\r
+#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */\r
+\r
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */\r
+\r
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+\r
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */\r
+#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */\r
+\r
+#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */\r
+#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+\r
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */\r
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */\r
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */\r
+\r
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+\r
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */\r
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+\r
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */\r
+\r
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */\r
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */\r
+#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */\r
+#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */\r
+#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */\r
+#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */\r
+#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */\r
+#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */\r
+#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */\r
+#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */\r
+#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */\r
+#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */\r
+#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR3 register *******************/\r
+#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+ \r
+#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR4 register *******************/\r
+#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR5 register *******************/\r
+#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */\r
+\r
+/****************** Bit definition for ADC_SMPR0 register *******************/\r
+#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */\r
+#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+ \r
+#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */\r
+#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */\r
+#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */\r
+#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/\r
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ \r
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Advanced Encryption Standard (AES) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for AES_CR register *********************/\r
+#define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */\r
+#define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */\r
+#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */\r
+#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */\r
+\r
+#define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */\r
+#define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+\r
+#define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */\r
+#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+\r
+#define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */\r
+#define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */\r
+#define AES_CR_CCIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */\r
+#define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */\r
+#define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */\r
+#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */\r
+\r
+/******************* Bit definition for AES_SR register *********************/\r
+#define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */\r
+#define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */\r
+#define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */\r
+\r
+/******************* Bit definition for AES_DINR register *******************/\r
+#define AES_DINR ((uint32_t)0x0000FFFF) /*!< AES Data Input Register */\r
+\r
+/******************* Bit definition for AES_DOUTR register ******************/\r
+#define AES_DOUTR ((uint32_t)0x0000FFFF) /*!< AES Data Output Register */\r
+\r
+/******************* Bit definition for AES_KEYR0 register ******************/\r
+#define AES_KEYR0 ((uint32_t)0x0000FFFF) /*!< AES Key Register 0 */\r
+\r
+/******************* Bit definition for AES_KEYR1 register ******************/\r
+#define AES_KEYR1 ((uint32_t)0x0000FFFF) /*!< AES Key Register 1 */\r
+\r
+/******************* Bit definition for AES_KEYR2 register ******************/\r
+#define AES_KEYR2 ((uint32_t)0x0000FFFF) /*!< AES Key Register 2 */\r
+\r
+/******************* Bit definition for AES_KEYR3 register ******************/\r
+#define AES_KEYR3 ((uint32_t)0x0000FFFF) /*!< AES Key Register 3 */\r
+\r
+/******************* Bit definition for AES_IVR0 register *******************/\r
+#define AES_IVR0 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 0 */\r
+\r
+/******************* Bit definition for AES_IVR1 register *******************/\r
+#define AES_IVR1 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 1 */\r
+\r
+/******************* Bit definition for AES_IVR2 register *******************/\r
+#define AES_IVR2 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 2 */\r
+\r
+/******************* Bit definition for AES_IVR3 register *******************/\r
+#define AES_IVR3 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 3 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog Comparators (COMP) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for COMP_CSR register ********************/\r
+#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */\r
+#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */\r
+#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */\r
+#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */\r
+\r
+#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */\r
+#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */\r
+#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */\r
+\r
+#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */\r
+#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */\r
+\r
+#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */\r
+#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */\r
+\r
+#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */\r
+#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */\r
+#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */\r
+#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */\r
+#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */\r
+\r
+#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */\r
+#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */\r
+#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Operational Amplifier (OPAMP) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for OPAMP_CSR register ******************/\r
+#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */\r
+#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */\r
+#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */\r
+#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */\r
+#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */\r
+#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */\r
+#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */\r
+#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */\r
+#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */\r
+#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */\r
+#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */\r
+#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */\r
+#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */\r
+#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */\r
+#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */\r
+#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */\r
+#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /*!< OPAMP3 disable */\r
+#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /*!< Switch 3 for OPAMP3 Enable */\r
+#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /*!< Switch 4 for OPAMP3 Enable */\r
+#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /*!< Switch 5 for OPAMP3 Enable */\r
+#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /*!< Switch 6 for OPAMP3 Enable */\r
+#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /*!< OPAMP3 Offset calibration for P differential pair */\r
+#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /*!< OPAMP3 Offset calibration for N differential pair */\r
+#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /*!< OPAMP3 Low power enable */\r
+#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ \r
+#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */\r
+#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /*!< Switch ANA Enable for OPAMP3 */\r
+#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */\r
+#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */\r
+#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */\r
+#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */\r
+#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /*!< OPAMP3 calibration output */\r
+\r
+/******************* Bit definition for OPAMP_OTR register ******************/\r
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /*!< Offset trim for OPAMP1 */\r
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /*!< Offset trim for OPAMP2 */\r
+#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /*!< Offset trim for OPAMP2 */\r
+#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */\r
+\r
+/******************* Bit definition for OPAMP_LPOTR register ****************/\r
+#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /*!< Offset trim in low power for OPAMP1 */\r
+#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /*!< Offset trim in low power for OPAMP2 */\r
+#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /*!< Offset trim in low power for OPAMP3 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit (CRC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter (DAC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun interrupt enable */\r
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU (DBGMCU) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */\r
+\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */\r
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/****************** Bit definition for DBGMCU_CR register *******************/\r
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */\r
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */\r
+\r
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/\r
+\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */\r
+\r
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/\r
+\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller (DMA) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for DMA_ISR register ********************/\r
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */\r
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */\r
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */\r
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */\r
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */\r
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */\r
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */\r
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */\r
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */\r
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */\r
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */\r
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */\r
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */\r
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */\r
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */\r
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */\r
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */\r
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */\r
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */\r
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */\r
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */\r
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */\r
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */\r
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */\r
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */\r
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */\r
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */\r
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */\r
+\r
+/******************* Bit definition for DMA_IFCR register *******************/\r
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */\r
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */\r
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */\r
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */\r
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */\r
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */\r
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */\r
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */\r
+\r
+/******************* Bit definition for DMA_CCR1 register *******************/\r
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/\r
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */\r
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR2 register *******************/\r
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */\r
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR3 register *******************/\r
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/*!<****************** Bit definition for DMA_CCR4 register *******************/\r
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/****************** Bit definition for DMA_CCR5 register *******************/\r
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */\r
+\r
+/******************* Bit definition for DMA_CCR6 register *******************/\r
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR7 register *******************/\r
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */\r
+\r
+/****************** Bit definition for DMA_CNDTR1 register ******************/\r
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR2 register ******************/\r
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR3 register ******************/\r
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR4 register ******************/\r
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR5 register ******************/\r
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR6 register ******************/\r
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR7 register ******************/\r
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CPAR1 register *******************/\r
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR2 register *******************/\r
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR3 register *******************/\r
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR4 register *******************/\r
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR5 register *******************/\r
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR6 register *******************/\r
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR7 register *******************/\r
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CMAR1 register *******************/\r
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR2 register *******************/\r
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR3 register *******************/\r
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CMAR4 register *******************/\r
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR5 register *******************/\r
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR6 register *******************/\r
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR7 register *******************/\r
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller (EXTI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */\r
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */\r
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */\r
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */\r
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */\r
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */\r
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */\r
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */\r
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */\r
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH, DATA EEPROM and Option Bytes Registers */\r
+/* (FLASH, DATA_EEPROM, OB) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for FLASH_ACR register ******************/\r
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */\r
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */\r
+#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */\r
+#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */\r
+#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */\r
+\r
+/******************* Bit definition for FLASH_PECR register ******************/\r
+#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */\r
+#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */\r
+#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */\r
+#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */\r
+#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */\r
+#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */\r
+#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */\r
+#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */\r
+#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */\r
+#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */ \r
+#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */ \r
+#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */ \r
+\r
+/****************** Bit definition for FLASH_PDKEYR register ******************/\r
+#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */\r
+\r
+/****************** Bit definition for FLASH_PEKEYR register ******************/\r
+#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */\r
+\r
+/****************** Bit definition for FLASH_PRGKEYR register ******************/\r
+#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */\r
+\r
+/****************** Bit definition for FLASH_OPTKEYR register ******************/\r
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */\r
+\r
+/****************** Bit definition for FLASH_SR register *******************/\r
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */\r
+#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/\r
+#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */\r
+#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */\r
+\r
+#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */\r
+#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */\r
+#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */\r
+#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */\r
+#define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */\r
+\r
+/****************** Bit definition for FLASH_OBR register *******************/\r
+#define FLASH_OBR_RDPRT ((uint16_t)0x000000AA) /*!< Read Protection */\r
+#define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/\r
+#define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */\r
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */\r
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */\r
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */\r
+#define FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000) /*!< BFB2 */\r
+\r
+/****************** Bit definition for FLASH_WRPR register ******************/\r
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */\r
+\r
+/****************** Bit definition for FLASH_WRPR1 register *****************/\r
+#define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */\r
+\r
+/****************** Bit definition for FLASH_WRPR2 register *****************/\r
+#define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Static Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FSMC_BCR1 register *******************/\r
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */\r
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+\r
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */\r
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */\r
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */\r
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */\r
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */\r
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */\r
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */\r
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */\r
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */\r
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR2 register *******************/\r
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */\r
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+\r
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */\r
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */\r
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */\r
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */\r
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */\r
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */\r
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */\r
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */\r
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */\r
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR3 register *******************/\r
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */\r
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+\r
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */\r
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */\r
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */\r
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */\r
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */\r
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */\r
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */\r
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */\r
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */\r
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR4 register *******************/\r
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */\r
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+\r
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */\r
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */\r
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */\r
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */\r
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */\r
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */\r
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */\r
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */\r
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */\r
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BTR1 register ******************/\r
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BTR2 register *******************/\r
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+/******************* Bit definition for FSMC_BTR3 register *******************/\r
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BTR4 register *******************/\r
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR1 register ******************/\r
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR2 register ******************/\r
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/\r
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR3 register ******************/\r
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR4 register ******************/\r
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose IOs (GPIO) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for GPIO_MODER register *****************/ \r
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_OTYPER register ****************/ \r
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
+\r
+/******************* Bit definition for GPIO_OSPEEDR register ***************/ \r
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_PUPDR register *****************/ \r
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)\r
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)\r
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)\r
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)\r
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)\r
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)\r
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)\r
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)\r
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)\r
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)\r
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)\r
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)\r
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)\r
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)\r
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)\r
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)\r
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0\r
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1\r
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2\r
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3\r
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4\r
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5\r
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6\r
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7\r
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8\r
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9\r
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10\r
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11\r
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12\r
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13\r
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14\r
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15\r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)\r
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)\r
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)\r
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)\r
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)\r
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)\r
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)\r
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)\r
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)\r
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)\r
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)\r
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)\r
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)\r
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)\r
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)\r
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)\r
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0\r
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1\r
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2\r
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3\r
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4\r
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5\r
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6\r
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7\r
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8\r
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9\r
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10\r
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11\r
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12\r
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13\r
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14\r
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15\r
+\r
+/******************* Bit definition for GPIO_BSRR register ******************/ \r
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_LCKR register ******************/\r
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)\r
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)\r
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)\r
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)\r
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)\r
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)\r
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)\r
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)\r
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)\r
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)\r
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)\r
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)\r
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)\r
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)\r
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)\r
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)\r
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)\r
+\r
+/******************* Bit definition for GPIO_AFRL register ******************/\r
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)\r
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)\r
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)\r
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)\r
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)\r
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)\r
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)\r
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)\r
+\r
+/******************* Bit definition for GPIO_AFRH register ******************/\r
+#define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)\r
+#define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)\r
+#define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)\r
+#define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)\r
+#define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)\r
+#define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)\r
+#define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)\r
+#define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for I2C_CR1 register ********************/\r
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */\r
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */\r
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */\r
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */\r
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */\r
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */\r
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */\r
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */\r
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */\r
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */\r
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */\r
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */\r
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */\r
+\r
+/******************* Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\r
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+\r
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */\r
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */\r
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */\r
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */\r
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */\r
+\r
+/******************* Bit definition for I2C_OAR1 register *******************/\r
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */\r
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */\r
+\r
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */\r
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */\r
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */\r
+\r
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */\r
+\r
+/******************* Bit definition for I2C_OAR2 register *******************/\r
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */\r
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */\r
+\r
+/******************** Bit definition for I2C_DR register ********************/\r
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */\r
+\r
+/******************* Bit definition for I2C_SR1 register ********************/\r
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */\r
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */\r
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */\r
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */\r
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */\r
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */\r
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */\r
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */\r
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */\r
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */\r
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */\r
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */\r
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */\r
+\r
+/******************* Bit definition for I2C_SR2 register ********************/\r
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */\r
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */\r
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */\r
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */\r
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */\r
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */\r
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */\r
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */\r
+\r
+/******************* Bit definition for I2C_CCR register ********************/\r
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */\r
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */\r
+\r
+/****************** Bit definition for I2C_TRISE register *******************/\r
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG (IWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD Controller (LCD) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for LCD_CR register *********************/\r
+#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */\r
+#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */\r
+\r
+#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */\r
+#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */\r
+#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */\r
+#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */\r
+\r
+#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */\r
+#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */\r
+#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */\r
+\r
+#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */\r
+\r
+/******************* Bit definition for LCD_FCR register ********************/\r
+#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */\r
+#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */\r
+#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */\r
+\r
+#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */\r
+#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */\r
+#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */\r
+#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */\r
+#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */\r
+#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */\r
+#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */\r
+#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */\r
+#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */\r
+\r
+/******************* Bit definition for LCD_SR register *********************/\r
+#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */\r
+#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */\r
+#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */\r
+#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */\r
+#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */\r
+#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */\r
+\r
+/******************* Bit definition for LCD_CLR register ********************/\r
+#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */\r
+#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */\r
+\r
+/******************* Bit definition for LCD_RAM register ********************/\r
+#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control (PWR) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for PWR_CR register ********************/\r
+#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */\r
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */\r
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */\r
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */\r
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */\r
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */\r
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */\r
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */\r
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */\r
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */\r
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */\r
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */\r
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */\r
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */\r
+\r
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */\r
+#define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */\r
+#define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */\r
+\r
+#define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */\r
+#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */\r
+#define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */\r
+#define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */\r
+\r
+/******************* Bit definition for PWR_CSR register ********************/\r
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */\r
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */\r
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */\r
+#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */\r
+#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */\r
+#define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */\r
+\r
+#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */\r
+#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */\r
+#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control (RCC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */\r
+\r
+#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */\r
+#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */\r
+\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */\r
+\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */\r
+#define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */\r
+\r
+#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */\r
+#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */\r
+#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */\r
+\r
+/******************** Bit definition for RCC_ICSCR register *****************/\r
+#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */\r
+#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */\r
+\r
+#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */\r
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */\r
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */\r
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */\r
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */\r
+#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */\r
+#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */\r
+#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */\r
+#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */\r
+#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */\r
+\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */\r
+\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */\r
+\r
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */\r
+\r
+/*!< PLL entry clock source*/\r
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */\r
+\r
+#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */\r
+#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */\r
+\r
+\r
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
+\r
+/*!< PLLMUL configuration */\r
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */\r
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */\r
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */\r
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */\r
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */\r
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */\r
+#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */\r
+#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */\r
+#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */\r
+\r
+/*!< PLLDIV configuration */\r
+#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */\r
+#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */\r
+#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */\r
+\r
+\r
+/*!< PLLDIV configuration */\r
+#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */\r
+#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */\r
+#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */\r
+#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */\r
+\r
+\r
+#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+/*!< MCO configuration */\r
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */\r
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */\r
+#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */\r
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */\r
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */\r
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */\r
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */\r
+\r
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */\r
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */\r
+\r
+/*!< MCO Prescaler configuration */\r
+#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */\r
+#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */\r
+#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */\r
+#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */\r
+#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */\r
+\r
+/*!<****************** Bit definition for RCC_CIR register ********************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */\r
+#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */\r
+#define RCC_CIR_LSECSS ((uint32_t)0x00000040) /*!< LSE CSS Interrupt flag */\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */\r
+\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */\r
+#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */\r
+#define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /*!< LSE CSS Interrupt Enable */\r
+\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */\r
+#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */\r
+#define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /*!< LSE CSS Interrupt Clear */\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */\r
+\r
+\r
+/***************** Bit definition for RCC_AHBRSTR register ******************/\r
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */\r
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */\r
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */\r
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */\r
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */\r
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */\r
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) /*!< GPIO port F reset */\r
+#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) /*!< GPIO port G reset */\r
+#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */\r
+#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */\r
+#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */\r
+#define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /*!< DMA2 reset */\r
+#define RCC_AHBRSTR_AESRST ((uint32_t)0x08000000) /*!< AES reset */\r
+#define RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000) /*!< FSMC reset */\r
+ \r
+/***************** Bit definition for RCC_APB2RSTR register *****************/\r
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */\r
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */\r
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */\r
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */\r
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */\r
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) /*!< SDIO reset */\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */\r
+\r
+/***************** Bit definition for RCC_APB1RSTR register *****************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */\r
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */\r
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */\r
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
+#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */\r
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */\r
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */\r
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */\r
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */\r
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */\r
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */\r
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */\r
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */\r
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
+#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */\r
+\r
+/****************** Bit definition for RCC_AHBENR register ******************/\r
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */\r
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */\r
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */\r
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */\r
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */\r
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */\r
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) /*!< GPIO port F clock enable */\r
+#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) /*!< GPIO port G clock enable */\r
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */\r
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when\r
+ the Flash memory is in power down mode) */\r
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */\r
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /*!< DMA2 clock enable */\r
+#define RCC_AHBENR_AESEN ((uint32_t)0x08000000) /*!< AES clock enable */\r
+#define RCC_AHBENR_FSMCEN ((uint32_t)0x40000000) /*!< FSMC clock enable */\r
+\r
+\r
+/****************** Bit definition for RCC_APB2ENR register *****************/\r
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */\r
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */\r
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */\r
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */\r
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) /*!< SDIO clock enable */\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */\r
+\r
+\r
+/***************** Bit definition for RCC_APB1ENR register ******************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */\r
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */\r
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */\r
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
+#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */\r
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */\r
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */\r
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */\r
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */\r
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */\r
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */\r
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
+#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */\r
+\r
+/****************** Bit definition for RCC_AHBLPENR register ****************/\r
+#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) /*!< GPIO port F clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) /*!< GPIO port G clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode\r
+ (has effect only when the Flash memory is\r
+ in power down mode) */\r
+#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /*!< DMA2 clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000) /*!< AES clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000) /*!< FSMC clock enabled in sleep mode */\r
+\r
+/****************** Bit definition for RCC_APB2LPENR register ***************/\r
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) /*!< SDIO clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */\r
+\r
+/***************** Bit definition for RCC_APB1LPENR register ****************/\r
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /*!< Timer 5 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /*!< SPI 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) /*!< UART 4 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) /*!< UART 5 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/\r
+\r
+/******************* Bit definition for RCC_CSR register ********************/\r
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */\r
+\r
+#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */\r
+#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */\r
+#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */\r
+#define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /*!< External Low Speed oscillator CSS Enable */\r
+#define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /*!< External Low Speed oscillator CSS Detected */\r
+\r
+#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
+#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+/*!< RTC congiguration */\r
+#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */\r
+#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */\r
+#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */\r
+\r
+#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */\r
+#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */\r
+ \r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */\r
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */\r
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */\r
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM ((uint32_t)0x00400000)\r
+#define RTC_TR_HT ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TR_ST ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
+#define RTC_DR_YU ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_DR_MT ((uint32_t)0x00001000)\r
+#define RTC_DR_MU ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_DR_DT ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_DR_DU ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_COE ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
+#define RTC_CR_POL ((uint32_t)0x00100000)\r
+#define RTC_CR_COSEL ((uint32_t)0x00080000)\r
+#define RTC_CR_BCK ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
+#define RTC_CR_DCE ((uint32_t)0x00000080)\r
+#define RTC_CR_FMT ((uint32_t)0x00000040)\r
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)\r
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)\r
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)\r
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)\r
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)\r
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CALIBR register ***************/\r
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)\r
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)\r
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP ((uint32_t)0x00008000)\r
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)\r
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)\r
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)\r
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)\r
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)\r
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)\r
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)\r
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)\r
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)\r
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)\r
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)\r
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)\r
+\r
+/******************** Bits definition for RTC_TAFCR register ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)\r
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)\r
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)\r
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)\r
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)\r
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)\r
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)\r
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)\r
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)\r
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)\r
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)\r
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)\r
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)\r
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)\r
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)\r
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)\r
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)\r
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)\r
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)\r
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP20R register ***************/\r
+#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP21R register ***************/\r
+#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP22R register ***************/\r
+#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP23R register ***************/\r
+#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP24R register ***************/\r
+#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP25R register ***************/\r
+#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP26R register ***************/\r
+#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP27R register ***************/\r
+#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP28R register ***************/\r
+#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP29R register ***************/\r
+#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP30R register ***************/\r
+#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP31R register ***************/\r
+#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for SDIO_POWER register ******************/\r
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for SDIO_CLKCR register ******************/\r
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */\r
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */\r
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */\r
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */\r
+\r
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */\r
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */\r
+\r
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */\r
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDIO_ARG register *******************/\r
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */\r
+\r
+/******************* Bit definition for SDIO_CMD register *******************/\r
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */\r
+\r
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */\r
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */\r
+\r
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */\r
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */\r
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */\r
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */\r
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */\r
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */\r
+\r
+/***************** Bit definition for SDIO_RESPCMD register *****************/\r
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */\r
+\r
+/****************** Bit definition for SDIO_RESP0 register ******************/\r
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP1 register ******************/\r
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP2 register ******************/\r
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP3 register ******************/\r
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP4 register ******************/\r
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */\r
+\r
+/****************** Bit definition for SDIO_DTIMER register *****************/\r
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */\r
+\r
+/****************** Bit definition for SDIO_DLEN register *******************/\r
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */\r
+\r
+/****************** Bit definition for SDIO_DCTRL register ******************/\r
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */\r
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */\r
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */\r
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */\r
+\r
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */\r
+\r
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */\r
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */\r
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */\r
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDIO_DCOUNT register *****************/\r
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */\r
+\r
+/****************** Bit definition for SDIO_STA register ********************/\r
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */\r
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */\r
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */\r
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */\r
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */\r
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */\r
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */\r
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */\r
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */\r
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */\r
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */\r
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */\r
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */\r
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */\r
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */\r
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */\r
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */\r
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */\r
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */\r
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */\r
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */\r
+\r
+/******************* Bit definition for SDIO_ICR register *******************/\r
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */\r
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */\r
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */\r
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */\r
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */\r
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */\r
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */\r
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */\r
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */\r
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */\r
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */\r
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */\r
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */\r
+\r
+/****************** Bit definition for SDIO_MASK register *******************/\r
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */\r
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */\r
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */\r
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */\r
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */\r
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */\r
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */\r
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */\r
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */\r
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */\r
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */\r
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */\r
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */\r
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */\r
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */\r
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */\r
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */\r
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */\r
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */\r
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */\r
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */\r
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */\r
+\r
+/***************** Bit definition for SDIO_FIFOCNT register *****************/\r
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDIO_FIFO register *******************/\r
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */\r
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */\r
+\r
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */\r
+\r
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */\r
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */\r
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */\r
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */\r
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */\r
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */\r
+#define SPI_CR2_FRF ((uint8_t)0x08) /*!< Frame format */\r
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */\r
+#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */\r
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */\r
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */\r
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */\r
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */\r
+\r
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */\r
+\r
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */\r
+\r
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* System Configuration (SYSCFG) */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for SYSCFG_MEMRMP register ****************/\r
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /*!< Boot mode Config */\r
+#define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+\r
+/***************** Bit definition for SYSCFG_PMC register *******************/\r
+#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */\r
+\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006) /*!< PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007) /*!< PG[0] pin */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060) /*!< PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070) /*!< PG[1] pin */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600) /*!< PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700) /*!< PG[2] pin */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000) /*!< PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000) /*!< PG[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/\r
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */\r
+\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006) /*!< PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007) /*!< PG[4] pin */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060) /*!< PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070) /*!< PG[5] pin */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600) /*!< PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700) /*!< PG[6] pin */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000) /*!< PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000) /*!< PG[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/\r
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */\r
+\r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006) /*!< PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007) /*!< PG[8] pin */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060) /*!< PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070) /*!< PG[9] pin */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600) /*!< PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700) /*!< PG[10] pin */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000) /*!< PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000) /*!< PG[11] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/\r
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */\r
+\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006) /*!< PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007) /*!< PG[12] pin */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060) /*!< PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070) /*!< PG[13] pin */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600) /*!< PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700) /*!< PG[14] pin */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000) /*!< PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000) /*!< PG[15] pin */\r
+ \r
+/******************************************************************************/\r
+/* */\r
+/* Routing Interface (RI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for RI_ICR register ********************/\r
+#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */\r
+#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */\r
+#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */\r
+#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */\r
+#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */\r
+\r
+#define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */\r
+#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */\r
+#define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */\r
+#define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */\r
+#define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */\r
+\r
+/******************** Bit definition for RI_ASCR1 register ********************/\r
+#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */\r
+#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+#define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /*!< Bit 16 */\r
+#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */\r
+#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */\r
+#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */\r
+#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */\r
+#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */\r
+#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */\r
+#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */\r
+#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */\r
+#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */\r
+#define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /*!< Bit 27 */\r
+#define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /*!< Bit 28 */\r
+#define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /*!< Bit 29 */\r
+#define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /*!< Bit 30 */\r
+#define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */\r
+\r
+/******************** Bit definition for RI_ASCR2 register ********************/\r
+#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */\r
+#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */\r
+#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */\r
+#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */\r
+#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */\r
+#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */\r
+#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */\r
+#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */\r
+#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */\r
+#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */\r
+#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */\r
+#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */\r
+#define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */\r
+#define RI_ASCR2_CH0b ((uint32_t)0x00010000) /*!< CH0b selection bit */\r
+#define RI_ASCR2_CH1b ((uint32_t)0x00020000) /*!< CH1b selection bit */\r
+#define RI_ASCR2_CH2b ((uint32_t)0x00040000) /*!< CH2b selection bit */\r
+#define RI_ASCR2_CH3b ((uint32_t)0x00080000) /*!< CH3b selection bit */\r
+#define RI_ASCR2_CH6b ((uint32_t)0x00100000) /*!< CH6b selection bit */\r
+#define RI_ASCR2_CH7b ((uint32_t)0x00200000) /*!< CH7b selection bit */\r
+#define RI_ASCR2_CH8b ((uint32_t)0x00400000) /*!< CH8b selection bit */\r
+#define RI_ASCR2_CH9b ((uint32_t)0x00800000) /*!< CH9b selection bit */\r
+#define RI_ASCR2_CH10b ((uint32_t)0x01000000) /*!< CH10b selection bit */\r
+#define RI_ASCR2_CH11b ((uint32_t)0x02000000) /*!< CH11b selection bit */\r
+#define RI_ASCR2_CH12b ((uint32_t)0x04000000) /*!< CH12b selection bit */\r
+#define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */\r
+#define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */\r
+#define RI_ASCR2_GR5_4 ((uint32_t)0x20000000) /*!< GR5-4 selection bit */\r
+\r
+/******************** Bit definition for RI_HYSCR1 register ********************/\r
+#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */\r
+#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */\r
+#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/******************** Bit definition for RI_HYSCR2 register ********************/\r
+#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */\r
+#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */\r
+#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/******************** Bit definition for RI_HYSCR3 register ********************/\r
+#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */\r
+#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */\r
+#define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/******************** Bit definition for RI_HYSCR4 register ********************/\r
+#define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */\r
+#define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Timers (TIM) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */\r
+\r
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
+ \r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
+ \r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */\r
+#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for USART_SR register *******************/\r
+#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */\r
+#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */\r
+#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */\r
+#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */\r
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */\r
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */\r
+#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */\r
+#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */\r
+#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */\r
+#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */\r
+\r
+/******************* Bit definition for USART_DR register *******************/\r
+#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */\r
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */\r
+#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */\r
+#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */\r
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */\r
+#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */\r
+#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */\r
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling by 8-bit mode */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */\r
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */\r
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */\r
+\r
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */\r
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */\r
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */\r
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */\r
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */\r
+\r
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Serial Bus (USB) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/*!<Endpoint-specific registers */\r
+/******************* Bit definition for USB_EP0R register *******************/\r
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP1R register *******************/\r
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP2R register *******************/\r
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP3R register *******************/\r
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP4R register *******************/\r
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP5R register *******************/\r
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP6R register *******************/\r
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP7R register *******************/\r
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/*!<Common registers */\r
+/******************* Bit definition for USB_CNTR register *******************/\r
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */\r
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */\r
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */\r
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */\r
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */\r
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */\r
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */\r
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */\r
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */\r
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */\r
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */\r
+\r
+/******************* Bit definition for USB_ISTR register *******************/\r
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */\r
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */\r
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */\r
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */\r
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */\r
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */\r
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */\r
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */\r
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */\r
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */\r
+\r
+/******************* Bit definition for USB_FNR register ********************/\r
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */\r
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */\r
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */\r
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */\r
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */\r
+\r
+/****************** Bit definition for USB_DADDR register *******************/\r
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */\r
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */\r
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */\r
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */\r
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */\r
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */\r
+\r
+#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */\r
+\r
+/****************** Bit definition for USB_BTABLE register ******************/ \r
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */\r
+\r
+/*!< Buffer descriptor table */\r
+/***************** Bit definition for USB_ADDR0_TX register *****************/\r
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_TX register *****************/\r
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_TX register *****************/\r
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_TX register *****************/\r
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_TX register *****************/\r
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_TX register *****************/\r
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_TX register *****************/\r
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_TX register *****************/\r
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_TX register ****************/\r
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */\r
+\r
+/***************** Bit definition for USB_COUNT1_TX register ****************/\r
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */\r
+\r
+/***************** Bit definition for USB_COUNT2_TX register ****************/\r
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */\r
+\r
+/***************** Bit definition for USB_COUNT3_TX register ****************/\r
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */\r
+\r
+/***************** Bit definition for USB_COUNT4_TX register ****************/\r
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */\r
+\r
+/***************** Bit definition for USB_COUNT5_TX register ****************/\r
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */\r
+\r
+/***************** Bit definition for USB_COUNT6_TX register ****************/\r
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */\r
+\r
+/***************** Bit definition for USB_COUNT7_TX register ****************/\r
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/\r
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/\r
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/\r
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/\r
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/\r
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/\r
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/\r
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/\r
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/\r
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/\r
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/\r
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/\r
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/\r
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/\r
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/\r
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/\r
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_ADDR0_RX register *****************/\r
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_RX register *****************/\r
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_RX register *****************/\r
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_RX register *****************/\r
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_RX register *****************/\r
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_RX register *****************/\r
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_RX register *****************/\r
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_RX register *****************/\r
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_RX register ****************/\r
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT1_RX register ****************/\r
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT2_RX register ****************/\r
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT3_RX register ****************/\r
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT4_RX register ****************/\r
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT5_RX register ****************/\r
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT6_RX register ****************/\r
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT7_RX register ****************/\r
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/\r
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/\r
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/\r
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/\r
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/\r
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/\r
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/\r
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/\r
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/\r
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/\r
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/\r
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/\r
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/\r
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/\r
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/\r
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/\r
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG (WWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */\r
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */\r
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */\r
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SystemTick (SysTick) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/***************** Bit definition for SysTick_CTRL register *****************/\r
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */\r
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */\r
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */\r
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */\r
+\r
+/***************** Bit definition for SysTick_LOAD register *****************/\r
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
+\r
+/***************** Bit definition for SysTick_VAL register ******************/\r
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */\r
+\r
+/***************** Bit definition for SysTick_CALIB register ****************/\r
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */\r
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */\r
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Nested Vectored Interrupt Controller (NVIC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for NVIC_ISER register *******************/\r
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */\r
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ICER register *******************/\r
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */\r
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ISPR register *******************/\r
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */\r
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ICPR register *******************/\r
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */\r
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_IABR register *******************/\r
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */\r
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_PRI0 register *******************/\r
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */\r
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */\r
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */\r
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */\r
+\r
+/****************** Bit definition for NVIC_PRI1 register *******************/\r
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */\r
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */\r
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */\r
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */\r
+\r
+/****************** Bit definition for NVIC_PRI2 register *******************/\r
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */\r
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */\r
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */\r
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */\r
+\r
+/****************** Bit definition for NVIC_PRI3 register *******************/\r
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */\r
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */\r
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */\r
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */\r
+\r
+/****************** Bit definition for NVIC_PRI4 register *******************/\r
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */\r
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */\r
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */\r
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */\r
+\r
+/****************** Bit definition for NVIC_PRI5 register *******************/\r
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */\r
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */\r
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */\r
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */\r
+\r
+/****************** Bit definition for NVIC_PRI6 register *******************/\r
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */\r
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */\r
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */\r
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */\r
+\r
+/****************** Bit definition for NVIC_PRI7 register *******************/\r
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */\r
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */\r
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */\r
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */\r
+\r
+/****************** Bit definition for SCB_CPUID register *******************/\r
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */\r
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */\r
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */\r
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */\r
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */\r
+\r
+/******************* Bit definition for SCB_ICSR register *******************/\r
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */\r
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\r
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */\r
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */\r
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */\r
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */\r
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */\r
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */\r
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */\r
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */\r
+\r
+/******************* Bit definition for SCB_VTOR register *******************/\r
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */\r
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */\r
+\r
+/*!<***************** Bit definition for SCB_AIRCR register *******************/\r
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */\r
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */\r
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */\r
+\r
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */\r
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+/* prority group configuration */\r
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\r
+\r
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */\r
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\r
+\r
+/******************* Bit definition for SCB_SCR register ********************/\r
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */\r
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */\r
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */\r
+\r
+/******************** Bit definition for SCB_CCR register *******************/\r
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\r
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\r
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */\r
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */\r
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */\r
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\r
+\r
+/******************* Bit definition for SCB_SHPR register ********************/\r
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\r
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\r
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\r
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\r
+\r
+/****************** Bit definition for SCB_SHCSR register *******************/\r
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */\r
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */\r
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */\r
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */\r
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */\r
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */\r
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */\r
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */\r
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */\r
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */\r
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */\r
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */\r
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */\r
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */\r
+\r
+/******************* Bit definition for SCB_CFSR register *******************/\r
+/*!< MFSR */\r
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */\r
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */\r
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */\r
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */\r
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */\r
+/*!< BFSR */\r
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */\r
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */\r
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */\r
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */\r
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */\r
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */\r
+/*!< UFSR */\r
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */\r
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */\r
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */\r
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */\r
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */\r
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\r
+\r
+/******************* Bit definition for SCB_HFSR register *******************/\r
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */\r
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\r
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */\r
+\r
+/******************* Bit definition for SCB_DFSR register *******************/\r
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */\r
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */\r
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */\r
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */\r
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */\r
+\r
+/******************* Bit definition for SCB_MMFAR register ******************/\r
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */\r
+\r
+/******************* Bit definition for SCB_BFAR register *******************/\r
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */\r
+\r
+/******************* Bit definition for SCB_afsr register *******************/\r
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm32l1xx_conf.h"\r
+#endif\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 09-March-2012\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32L1XX_H\r
+#define __SYSTEM_STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32L1xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_types\r
+ * @{\r
+ */\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32L1XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* ---------------------------------------------------------------------- \r
+* Copyright (C) 2010 ARM Limited. All rights reserved. \r
+* \r
+* $Date: 11. November 2010 \r
+* $Revision: V1.0.2 \r
+* \r
+* Project: CMSIS DSP Library \r
+* Title: arm_common_tables.h \r
+* \r
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions \r
+* \r
+* Target Processor: Cortex-M4/Cortex-M3\r
+* \r
+* Version 1.0.2 2010/11/11 \r
+* Documentation updated. \r
+* \r
+* Version 1.0.1 2010/10/05 \r
+* Production release and review comments incorporated. \r
+* \r
+* Version 1.0.0 2010/09/20 \r
+* Production release and review comments incorporated. \r
+* -------------------------------------------------------------------- */\r
+\r
+#ifndef _ARM_COMMON_TABLES_H\r
+#define _ARM_COMMON_TABLES_H\r
+\r
+#include "arm_math.h"\r
+\r
+extern const uint16_t armBitRevTable[1024];\r
+extern const q15_t armRecipTableQ15[64];\r
+extern const q31_t armRecipTableQ31[64];\r
+extern const q31_t realCoefAQ31[1024];\r
+extern const q31_t realCoefBQ31[1024];\r
+extern const float32_t twiddleCoef[6144];\r
+extern const q31_t twiddleCoefQ31[6144];\r
+extern const q15_t twiddleCoefQ15[6144];\r
+\r
+#endif /* ARM_COMMON_TABLES_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V3.01\r
+ * @date 22. March 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M3\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M3 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if (__CM3_REV < 0x0201) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V3.01\r
+ * @date 06. March 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V3.01\r
+ * @date 06. March 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+\r
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );\r
+ return(op1);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc000.h\r
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
+ * @version V3.01\r
+ * @date 22. March 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_SC000_H_GENERIC\r
+#define __CORE_SC000_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup SC000\r
+ @{\r
+ */\r
+\r
+/* CMSIS SC000 definitions */\r
+#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __SC000_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */\r
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \\r
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (0) /*!< Cortex secure core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_SC000_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC000_H_DEPENDANT\r
+#define __CORE_SC000_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC000_REV\r
+ #define __SC000_REV 0x0000\r
+ #warning "__SC000_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group SC000 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ uint32_t RESERVED1[154];\r
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/* SCB Security Features Register Definitions */\r
+#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */\r
+#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */\r
+\r
+#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */\r
+#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of SC000 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */\r
+ else {\r
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_SC000_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc300.h\r
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
+ * @version V3.01\r
+ * @date 22. March 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_SC300_H_GENERIC\r
+#define __CORE_SC300_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup SC3000\r
+ @{\r
+ */\r
+\r
+/* CMSIS SC300 definitions */\r
+#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __SC300_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */\r
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \\r
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (300) /*!< Cortex secure core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_SC300_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC300_H_DEPENDANT\r
+#define __CORE_SC300_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC300_REV\r
+ #define __SC300_REV 0x0000\r
+ #warning "__SC300_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group SC300 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ uint32_t RESERVED1[1];\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_SC300_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
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+\r
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release\r
+Notes for<o:p></o:p> </span><span style="font-size: 20pt; color: rgb(51, 102, 255); font-family: Verdana;">STM32L1xx Standard Peripherals Library Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span><br>\r
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+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright\r
+© 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp"></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
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+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
+<tbody>\r
+<tr style="">\r
+<td style="padding: 0cm;" valign="top">\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
+<ol style="margin-top: 0cm;" start="1" type="1">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32L1xx Standard Peripherals Library Drivers update history</a><o:p></o:p></span></li>\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>\r
+</ol>\r
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32L1xx Standard Peripherals Library Drivers update history<o:p></o:p></span></h2>\r
+\r
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 05-March-2012<o:p></o:p></span></h3>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+\r
+ <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 24-January-2012<o:p></o:p></span></h3>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+\r
+ <ul style="margin-top: 0cm;" type="square">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version for <span style="font-weight: bold; font-style: italic;">STM32L1xx High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density Plus</span> devices.</span><br>\r
+ <span style="font-size: 10pt; font-family: Verdana;"></span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new drivers for new peripherals on </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32L1xx High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density Plus</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices:</span></li>\r
+ <ul style="font-weight: bold; font-style: italic;">\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_aes.h/.c </span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_fsmc.h/.c </span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_opamp.h/.c </span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_sdio.h/.c </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_adc.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new channel for ADC Bank B</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function to select between Bank A and Bank B: void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_BankSelection);</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update ADC_InjectedChannelConfig() and ADC_RegularChannelConfig() to support new ADC channels.<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_comp.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: void COMP_SW1SwitchConfig(FunctionalState NewState);<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_dbgmcu.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new parameter for TIM5<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_dma.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add DMA2 support<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_exti.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new EXTI Line 23 connected to TS channel acquisition event<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_flash.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new pages definitions for Write protection</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flag FLASH_FLAG_OPTVERRUSR</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add\r
+new functions: FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(),\r
+FLASH_OB_BootConfig(), FLASH_OB_GetWRP1(), FLASH_OB_GetWRP2(),\r
+FLASH_EraseParallelPage() and FLASH_ProgramParallelHalfPage().</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update\r
+functions to avoid STM32L1XX_MD workaround on Data EEPROM (FAST)\r
+halfword/byte erase: DATA_EEPROM_FastProgramByte(),\r
+DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_ProgramByte() and\r
+DATA_EEPROM_ProgramHalfWord().</span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_flash_ramfunc.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: FLASH_EraseParallelPage() and FLASH_ProgramParallelHalfPage().</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update\r
+FLASH_ProgramHalfPage(), FLASH_ProgramParallelHalfPage(),\r
+DATA_EEPROM_EraseDoubleWord() and DATA_EEPROM_ProgramDoubleWord()\r
+functions.</span></li>\r
+\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_gpio.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new GPIO port definition.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new alternate functions for new peripherals.<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_i2c.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_rcc.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new interrupt for RCC_IT_LSECSS</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions for new peripherals</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: RCC_LSEClockSecuritySystemCmd()<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_rtc.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">SYNCH_PREDIV max value changed to 0x7FFF</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions for RTC Alarm Sub Second "RTC_Alarm_Sub_Seconds_Masks" and Alarm Sub Second max value (0x7FFF)</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add\r
+new definitions for: RTC_Calib_Output_selection,\r
+RTC_Smooth_calib_period, RTC_Smooth_calib_Plus_pulses,\r
+RTC_Smooth_calib_Minus_pulses.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions: RTC_TamperTrigger_LowLevel and RTC_TamperTrigger_HighLevel.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add\r
+new definitions for RTC_Tamper_Filter, RTC_Tamper_Sampling_Frequencies,\r
+RTC_Tamper_Pin_Precharge_Duration, RTC_Tamper_2 and RTC_Tamper_3.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new RTC_Add_1_Second_Parameter and RTC_Substract_Fraction_Of_Second_Value defintions.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new Backup registers definitions from RTC_BKP_DR20 to RTC_BKP_DR31.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flags: RTC_FLAG_RECALPF, RTC_FLAG_TAMP3F and RTC_FLAG_TAMP2F</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new interrupts definitions RTC_IT_TAMP2 and RTC_IT_TAMP3</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: <span style="font-style: italic;">RTC_BypassShadowCmd(),\r
+RTC_GetSubSecond(), RTC_AlarmSubSecondConfig(),\r
+RTC_GetAlarmSubSecond(), RTC_CalibOutputConfig(),\r
+RTC_SmoothCalibConfig(), RTC_GetTimeStampSubSecond(),\r
+RTC_TamperFilterConfig(), RTC_TamperSamplingFreqConfig(),\r
+RTC_TamperPinsPrechargeDuration(), RTC_TimeStampOnTamperDetectionCmd(),\r
+RTC_TamperPullUpCmd(), RTC_SynchroShiftConfig().</span><br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_spi.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for I2S</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new structure "I2S_InitTypeDef"</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new parameter: I2S_Mode, I2S_Standard, I2S_Data_Format, I2S_MCLK_Output, I2S_Audio_Frequency and I2S_Clock_Polarity.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 2 interrupts: I2S_IT_UDR and SPI_I2S_IT_FRE</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flags: I2S_FLAG_CHSIDE, I2S_FLAG_UDR and SPI_I2S_FLAG_FRE</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: I2S_Init(), I2S_StructInit() and I2S_Cmd()<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_syscfg.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"> Add support for new port: EXTI_PortSourceGPIOF and EXTI_PortSourceGPIOG</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new remap for FSMC: SYSCFG_MemoryRemap_FSMC</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new RI Channels and new RI IOSwitch</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: SYSCFG_GetBootMode() and SYSCFG_RIChannelSpeedConfig()<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_tim.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update to support TIM 32-bit</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change TIM_Period and TIM_Pulse to be declared as 32-bit</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the "TIM_DMABase_RCR": the RCR register is not present on STM32L1xx family.<br>\r
+ </span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add </span><span style="font-size: 10pt; font-family: Verdana;">new parameter: </span><span style="font-size: 10pt; font-family: Verdana;">TIM_DMABase_OR <br>\r
+ </span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change "TIM_DMABurstLength_1Byte" to "TIM_DMABurstLength_1Transfer"</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add\r
+new TIM_Remap: TIM2_TIM10_OC, TIM2_TIM5_TRGO, TIM3_TIM11_OC,\r
+TIM3_TIM5_TRGO, TIM10_ETR_LSE, TIM10_ETR_TIM9_TRGO, TIM11_ETR_LSE and\r
+TIM11_ETR_TIM9_TRGO.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update TIM_RemapConfig() function coding.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all functions header comments to support TIM5.<br>\r
+ </span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_usart.h/.c</span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update to support UART4 and UART5</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all functions header comment<br>\r
+ </span></li>\r
+ </ul>\r
+ </ul>\r
+ <p class="MsoNormal"><br>\r
+ </p>\r
+\r
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 31-December-2010<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><br><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>\r
+\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">package</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></div><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><br>Unless\r
+required by applicable law or agreed to in writing, software\r
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT\r
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See\r
+the License for the specific language governing permissions and\r
+limitations under the License.</span>\r
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+<hr align="center" size="2" width="100%"></span></div>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For\r
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers\r
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+</div>\r
+<p class="MsoNormal"><o:p> </o:p></p>\r
+</div>\r
+</body></html>
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the miscellaneous\r
+ * firmware library functions (add-on to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MISC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief NVIC Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
+ This parameter can be a value of @ref IRQn_Type \r
+ (For the complete STM32 Devices IRQ Channels list, please\r
+ refer to stm32l1xx.h file) */\r
+\r
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
+ specified in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
+ in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+ will be enabled or disabled. \r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+} NVIC_InitTypeDef;\r
+\r
+/** \r
+ *\r
+@verbatim \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ | | | 4 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ | | | 3 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ | | | 2 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ | | | 1 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ | | | 0 bits for subpriority \r
+ ============================================================================================================================\r
+@endverbatim\r
+*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Vector_Table_Base \r
+ * @{\r
+ */\r
+\r
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+ ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup System_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+ * @{\r
+ */\r
+\r
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+ ((GROUP) == NVIC_PriorityGroup_1) || \\r
+ ((GROUP) == NVIC_PriorityGroup_2) || \\r
+ ((GROUP) == NVIC_PriorityGroup_3) || \\r
+ ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SysTick_clock_source \r
+ * @{\r
+ */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_adc.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the ADC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_ADC_H\r
+#define __STM32L1xx_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief ADC Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.\r
+ This parameter can be a value of @ref ADC_Resolution */\r
+ \r
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
+ Scan (multichannel) or Single (one channel) mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+ \r
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
+ Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ \r
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the\r
+ trigger of a regular group. This parameter can be a value\r
+ of @ref ADC_external_trigger_edge_for_regular_channels_conversion */\r
+ \r
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
+ to digital conversion of regular channels. This parameter\r
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
+ \r
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
+ This parameter can be a value of @ref ADC_data_align */\r
+ \r
+ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done\r
+ using the sequencer for regular channel group.\r
+ This parameter must range from 1 to 27. */\r
+}ADC_InitTypeDef;\r
+\r
+typedef struct \r
+{ \r
+ uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.\r
+ This parameter can be a value \r
+ of @ref ADC_Prescaler */\r
+}ADC_CommonInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Constants\r
+ * @{\r
+ */ \r
+#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+\r
+/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase \r
+ * @{\r
+ */ \r
+#define ADC_PowerDown_Delay ((uint32_t)0x00010000)\r
+#define ADC_PowerDown_Idle ((uint32_t)0x00020000)\r
+#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)\r
+\r
+#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \\r
+ ((DWON) == ADC_PowerDown_Idle) || \\r
+ ((DWON) == ADC_PowerDown_Idle_Delay))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_Prescaler \r
+ * @{\r
+ */ \r
+#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)\r
+#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)\r
+#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)\r
+\r
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div2) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+\r
+/** @defgroup ADC_Resolution \r
+ * @{\r
+ */ \r
+#define ADC_Resolution_12b ((uint32_t)0x00000000)\r
+#define ADC_Resolution_10b ((uint32_t)0x01000000)\r
+#define ADC_Resolution_8b ((uint32_t)0x02000000)\r
+#define ADC_Resolution_6b ((uint32_t)0x03000000)\r
+\r
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\r
+ ((RESOLUTION) == ADC_Resolution_10b) || \\r
+ ((RESOLUTION) == ADC_Resolution_8b) || \\r
+ ((RESOLUTION) == ADC_Resolution_6b))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)\r
+#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)\r
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)\r
+\r
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion\r
+ * @{\r
+ */ \r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)\r
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)\r
+#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)\r
+#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)\r
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)\r
+\r
+/* TIM4 */\r
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)\r
+#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)\r
+\r
+/* TIM6 */\r
+#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)\r
+\r
+/* TIM9 */\r
+#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)\r
+\r
+/* EXTI */\r
+#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)\r
+\r
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_data_align \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
+\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_channels \r
+ * @{\r
+ */ \r
+/* ADC Bank A Channels -------------------------------------------------------*/ \r
+#define ADC_Channel_0 ((uint8_t)0x00)\r
+#define ADC_Channel_1 ((uint8_t)0x01)\r
+#define ADC_Channel_2 ((uint8_t)0x02)\r
+#define ADC_Channel_3 ((uint8_t)0x03)\r
+\r
+#define ADC_Channel_6 ((uint8_t)0x06)\r
+#define ADC_Channel_7 ((uint8_t)0x07)\r
+#define ADC_Channel_8 ((uint8_t)0x08)\r
+#define ADC_Channel_9 ((uint8_t)0x09)\r
+#define ADC_Channel_10 ((uint8_t)0x0A)\r
+#define ADC_Channel_11 ((uint8_t)0x0B)\r
+#define ADC_Channel_12 ((uint8_t)0x0C)\r
+\r
+\r
+/* ADC Bank B Channels -------------------------------------------------------*/ \r
+#define ADC_Channel_0b ADC_Channel_0\r
+#define ADC_Channel_1b ADC_Channel_1\r
+#define ADC_Channel_2b ADC_Channel_2\r
+#define ADC_Channel_3b ADC_Channel_3\r
+\r
+#define ADC_Channel_6b ADC_Channel_6\r
+#define ADC_Channel_7b ADC_Channel_7\r
+#define ADC_Channel_8b ADC_Channel_8\r
+#define ADC_Channel_9b ADC_Channel_9\r
+#define ADC_Channel_10b ADC_Channel_10\r
+#define ADC_Channel_11b ADC_Channel_11\r
+#define ADC_Channel_12b ADC_Channel_12\r
+\r
+/* ADC Common Channels (ADC Bank A and B) ------------------------------------*/\r
+#define ADC_Channel_4 ((uint8_t)0x04)\r
+#define ADC_Channel_5 ((uint8_t)0x05)\r
+\r
+#define ADC_Channel_13 ((uint8_t)0x0D)\r
+#define ADC_Channel_14 ((uint8_t)0x0E)\r
+#define ADC_Channel_15 ((uint8_t)0x0F)\r
+#define ADC_Channel_16 ((uint8_t)0x10)\r
+#define ADC_Channel_17 ((uint8_t)0x11)\r
+#define ADC_Channel_18 ((uint8_t)0x12)\r
+#define ADC_Channel_19 ((uint8_t)0x13)\r
+#define ADC_Channel_20 ((uint8_t)0x14)\r
+#define ADC_Channel_21 ((uint8_t)0x15)\r
+#define ADC_Channel_22 ((uint8_t)0x16)\r
+#define ADC_Channel_23 ((uint8_t)0x17)\r
+#define ADC_Channel_24 ((uint8_t)0x18)\r
+#define ADC_Channel_25 ((uint8_t)0x19)\r
+\r
+#define ADC_Channel_27 ((uint8_t)0x1B)\r
+#define ADC_Channel_28 ((uint8_t)0x1C)\r
+#define ADC_Channel_29 ((uint8_t)0x1D)\r
+#define ADC_Channel_30 ((uint8_t)0x1E)\r
+#define ADC_Channel_31 ((uint8_t)0x1F)\r
+\r
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \\r
+ ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \\r
+ ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \\r
+ ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \\r
+ ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \\r
+ ((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \\r
+ ((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \\r
+ ((CHANNEL) == ADC_Channel_31))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_sampling_times \r
+ * @{\r
+ */ \r
+\r
+#define ADC_SampleTime_4Cycles ((uint8_t)0x00)\r
+#define ADC_SampleTime_9Cycles ((uint8_t)0x01)\r
+#define ADC_SampleTime_16Cycles ((uint8_t)0x02)\r
+#define ADC_SampleTime_24Cycles ((uint8_t)0x03)\r
+#define ADC_SampleTime_48Cycles ((uint8_t)0x04)\r
+#define ADC_SampleTime_96Cycles ((uint8_t)0x05)\r
+#define ADC_SampleTime_192Cycles ((uint8_t)0x06)\r
+#define ADC_SampleTime_384Cycles ((uint8_t)0x07)\r
+\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \\r
+ ((TIME) == ADC_SampleTime_9Cycles) || \\r
+ ((TIME) == ADC_SampleTime_16Cycles) || \\r
+ ((TIME) == ADC_SampleTime_24Cycles) || \\r
+ ((TIME) == ADC_SampleTime_48Cycles) || \\r
+ ((TIME) == ADC_SampleTime_96Cycles) || \\r
+ ((TIME) == ADC_SampleTime_192Cycles) || \\r
+ ((TIME) == ADC_SampleTime_384Cycles))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Delay_length \r
+ * @{\r
+ */ \r
+\r
+#define ADC_DelayLength_None ((uint8_t)0x00)\r
+#define ADC_DelayLength_Freeze ((uint8_t)0x10)\r
+#define ADC_DelayLength_7Cycles ((uint8_t)0x20)\r
+#define ADC_DelayLength_15Cycles ((uint8_t)0x30)\r
+#define ADC_DelayLength_31Cycles ((uint8_t)0x40)\r
+#define ADC_DelayLength_63Cycles ((uint8_t)0x50)\r
+#define ADC_DelayLength_127Cycles ((uint8_t)0x60)\r
+#define ADC_DelayLength_255Cycles ((uint8_t)0x70)\r
+\r
+#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \\r
+ ((LENGTH) == ADC_DelayLength_Freeze) || \\r
+ ((LENGTH) == ADC_DelayLength_7Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_15Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_31Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_63Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_127Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_255Cycles))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)\r
+#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)\r
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+\r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)\r
+\r
+/* TIM4 */\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)\r
+\r
+/* TIM7 */\r
+#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)\r
+\r
+/* TIM9 */\r
+#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)\r
+\r
+/* TIM10 */\r
+#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)\r
+\r
+/* EXTI */\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_channel_selection \r
+ * @{\r
+ */ \r
+#define ADC_InjectedChannel_1 ((uint8_t)0x18)\r
+#define ADC_InjectedChannel_2 ((uint8_t)0x1C)\r
+#define ADC_InjectedChannel_3 ((uint8_t)0x20)\r
+#define ADC_InjectedChannel_4 ((uint8_t)0x24)\r
+\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_2) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_3) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_analog_watchdog_selection \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) \r
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_IT_AWD ((uint16_t)0x0106) \r
+#define ADC_IT_EOC ((uint16_t)0x0205) \r
+#define ADC_IT_JEOC ((uint16_t)0x0407) \r
+#define ADC_IT_OVR ((uint16_t)0x201A) \r
+ \r
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \\r
+ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_FLAG_AWD ((uint16_t)0x0001)\r
+#define ADC_FLAG_EOC ((uint16_t)0x0002)\r
+#define ADC_FLAG_JEOC ((uint16_t)0x0004)\r
+#define ADC_FLAG_JSTRT ((uint16_t)0x0008)\r
+#define ADC_FLAG_STRT ((uint16_t)0x0010)\r
+#define ADC_FLAG_OVR ((uint16_t)0x0020)\r
+#define ADC_FLAG_ADONS ((uint16_t)0x0040)\r
+#define ADC_FLAG_RCNR ((uint16_t)0x0100)\r
+#define ADC_FLAG_JCNR ((uint16_t)0x0200) \r
+ \r
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))\r
+ \r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
+ ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \\r
+ ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \\r
+ ((FLAG) == ADC_FLAG_JCNR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_thresholds \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_offset \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_length \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_rank \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_length \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_rank \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_discontinuous_mode_number \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Bank_Selection \r
+ * @{\r
+ */ \r
+#define ADC_Bank_A ((uint8_t)0x00)\r
+#define ADC_Bank_B ((uint8_t)0x01) \r
+#define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the ADC configuration to the default reset state *****/ \r
+void ADC_DeInit(ADC_TypeDef* ADCx); \r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);\r
+\r
+/* Power saving functions *****************************************************/\r
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);\r
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);\r
+\r
+/* Analog Watchdog configuration functions ************************************/\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
+\r
+/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
+\r
+/* Regular Channels Configuration functions ***********************************/\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+\r
+/* Regular Channels DMA Configuration functions *******************************/\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Injected channels Configuration functions **********************************/\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_ADC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_aes.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the AES firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_AES_H\r
+#define __STM32L1xx_AES_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup AES\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief AES Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t AES_Operation; /*!< Specifies the AES mode of operation.\r
+ This parameter can be a value of @ref AES_possible_Operation_modes */\r
+ uint32_t AES_Chaining; /*!< Specifies the AES Chaining modes: ECB, CBC or CTR.\r
+ This parameter can be a value of @ref AES_possible_chaining_modes */\r
+ uint32_t AES_DataType; /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit.\r
+ This parameter can be a value of @ref AES_Data_Types */\r
+}AES_InitTypeDef;\r
+\r
+/** \r
+ * @brief AES Key(s) structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t AES_Key0; /*!< Key[31:0] */\r
+ uint32_t AES_Key1; /*!< Key[63:32] */\r
+ uint32_t AES_Key2; /*!< Key[95:64] */\r
+ uint32_t AES_Key3; /*!< Key[127:96] */\r
+}AES_KeyInitTypeDef;\r
+\r
+/** \r
+ * @brief AES Initialization Vectors (IV) structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t AES_IV0; /*!< Init Vector IV[31:0] */\r
+ uint32_t AES_IV1; /*!< Init Vector IV[63:32] */\r
+ uint32_t AES_IV2; /*!< Init Vector IV[95:64] */\r
+ uint32_t AES_IV3; /*!< Init Vector IV[127:96] */\r
+}AES_IVInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup AES_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup AES_possible_Operation_modes\r
+ * @{\r
+ */ \r
+#define AES_Operation_Encryp ((uint32_t)0x00000000) /*!< AES in Encryption mode */\r
+#define AES_Operation_KeyDeriv AES_CR_MODE_0 /*!< AES in Key Derivation mode */\r
+#define AES_Operation_Decryp AES_CR_MODE_1 /*!< AES in Decryption mode */\r
+#define AES_Operation_KeyDerivAndDecryp AES_CR_MODE /*!< AES in Key Derivation and Decryption mode */\r
+\r
+#define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp) || \\r
+ ((OPERATION) == AES_Operation_KeyDeriv) || \\r
+ ((OPERATION) == AES_Operation_Decryp) || \\r
+ ((OPERATION) == AES_Operation_KeyDerivAndDecryp))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup AES_possible_chaining_modes\r
+ * @{\r
+ */ \r
+#define AES_Chaining_ECB ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */\r
+#define AES_Chaining_CBC AES_CR_CHMOD_0 /*!< AES in CBC chaining mode */\r
+#define AES_Chaining_CTR AES_CR_CHMOD_1 /*!< AES in CTR chaining mode */\r
+\r
+#define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \\r
+ ((CHAINING) == AES_Chaining_CBC) || \\r
+ ((CHAINING) == AES_Chaining_CTR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AES_Data_Types\r
+ * @{\r
+ */ \r
+#define AES_DataType_32b ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */\r
+#define AES_DataType_16b AES_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */\r
+#define AES_DataType_8b AES_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */\r
+#define AES_DataType_1b AES_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */\r
+\r
+#define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \\r
+ ((DATATYPE) == AES_DataType_16b)|| \\r
+ ((DATATYPE) == AES_DataType_8b) || \\r
+ ((DATATYPE) == AES_DataType_1b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AES_Flags\r
+ * @{\r
+ */ \r
+#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */\r
+#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */\r
+#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */\r
+\r
+#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \\r
+ ((FLAG) == AES_FLAG_RDERR) || \\r
+ ((FLAG) == AES_FLAG_WRERR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup AES_Interrupts\r
+ * @{\r
+ */ \r
+#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */\r
+#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */\r
+\r
+#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))\r
+#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AES_DMA_Transfer_modes\r
+ * @{\r
+ */ \r
+#define AES_DMATransfer_In AES_CR_DMAINEN /*!< DMA requests enabled for input transfer phase */\r
+#define AES_DMATransfer_Out AES_CR_DMAOUTEN /*!< DMA requests enabled for input transfer phase */\r
+#define AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */\r
+\r
+#define IS_AES_DMA_TRANSFER(TRANSFER) (((TRANSFER) == AES_DMATransfer_In) || \\r
+ ((TRANSFER) == AES_DMATransfer_Out) || \\r
+ ((TRANSFER) == AES_DMATransfer_InOut))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Initialization and configuration functions *********************************/\r
+void AES_DeInit(void);\r
+void AES_Init(AES_InitTypeDef* AES_InitStruct);\r
+void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct);\r
+void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct);\r
+void AES_Cmd(FunctionalState NewState);\r
+\r
+/* Structures initialization functions ****************************************/\r
+void AES_StructInit(AES_InitTypeDef* AES_InitStruct);\r
+void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct);\r
+void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct);\r
+\r
+/* AES Read and Write functions **********************************************/ \r
+void AES_WriteSubData(uint32_t Data);\r
+uint32_t AES_ReadSubData(void);\r
+void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct);\r
+void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct);\r
+\r
+/* DMA transfers management function ******************************************/\r
+void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState);\r
+FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG);\r
+void AES_ClearFlag(uint32_t AES_FLAG);\r
+ITStatus AES_GetITStatus(uint32_t AES_IT);\r
+void AES_ClearITPendingBit(uint32_t AES_IT);\r
+\r
+/* High Level AES functions **************************************************/\r
+ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
+ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
+ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
+ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
+ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
+ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_AES_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_comp.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the COMP firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_COMP_H\r
+#define __STM32L1xx_COMP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup COMP\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief COMP Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.\r
+ This parameter can be a value of @ref COMP_Speed */\r
+ uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.\r
+ This parameter can be a value of @ref COMP_InvertingInput */\r
+ uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.\r
+ This parameter can be a value of @ref COMP_OutputSelect */\r
+ \r
+}COMP_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup COMP_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+#define COMP_OutputLevel_High ((uint32_t)0x00000001)\r
+#define COMP_OutputLevel_Low ((uint32_t)0x00000000)\r
+\r
+/** @defgroup COMP_Selection\r
+ * @{\r
+ */\r
+\r
+#define COMP_Selection_COMP1 ((uint32_t)0x00000001)\r
+#define COMP_Selection_COMP2 ((uint32_t)0x00000002)\r
+\r
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \\r
+ ((PERIPH) == COMP_Selection_COMP2))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_InvertingInput\r
+ * @{\r
+ */\r
+\r
+#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */\r
+#define COMP_InvertingInput_IO ((uint32_t)0x00040000)\r
+#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)\r
+#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)\r
+#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)\r
+#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)\r
+#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)\r
+#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)\r
+\r
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \\r
+ ((INPUT) == COMP_InvertingInput_IO) || \\r
+ ((INPUT) == COMP_InvertingInput_VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_DAC1) || \\r
+ ((INPUT) == COMP_InvertingInput_DAC2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_OutputSelect\r
+ * @{\r
+ */\r
+\r
+#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)\r
+#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)\r
+#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)\r
+#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)\r
+#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)\r
+#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)\r
+#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)\r
+#define COMP_OutputSelect_None ((uint32_t)0x00E00000)\r
+\r
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \\r
+ ((OUTPUT) == COMP_OutputSelect_None))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup COMP_Speed\r
+ * @{\r
+ */\r
+\r
+#define COMP_Speed_Slow ((uint32_t)0x00000000)\r
+#define COMP_Speed_Fast ((uint32_t)0x00001000)\r
+\r
+#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \\r
+ ((SPEED) == COMP_Speed_Fast))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the COMP configuration to the default reset state ****/\r
+void COMP_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);\r
+void COMP_Cmd(FunctionalState NewState);\r
+uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);\r
+void COMP_SW1SwitchConfig(FunctionalState NewState);\r
+\r
+/* Window mode control function ***********************************************/\r
+void COMP_WindowCmd(FunctionalState NewState);\r
+\r
+/* Internal Reference Voltage (VREFINT) output function ***********************/\r
+void COMP_VrefintOutputCmd(FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_COMP_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_crc.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the CRC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_CRC_H\r
+#define __STM32L1xx_CRC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+void CRC_ResetDR(void);\r
+uint32_t CRC_CalcCRC(uint32_t Data);\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t CRC_GetCRC(void);\r
+void CRC_SetIDRegister(uint8_t IDValue);\r
+uint8_t CRC_GetIDRegister(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_CRC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dac.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the DAC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DAC_H\r
+#define __STM32L1xx_DAC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+ \r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DAC Init structure definition\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
+ This parameter can be a value of @ref DAC_trigger_selection */\r
+\r
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
+ are generated, or whether no wave is generated.\r
+ This parameter can be a value of @ref DAC_wave_generation */\r
+\r
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
+ the maximum amplitude triangle generation for the DAC channel. \r
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
+\r
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
+ This parameter can be a value of @ref DAC_output_buffer */\r
+}DAC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_trigger_selection \r
+ * @{\r
+ */\r
+ \r
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
+ has been loaded, and not by external trigger */\r
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T9_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
+ ((WAVE) == DAC_WaveGeneration_Noise) || \\r
+ ((WAVE) == DAC_WaveGeneration_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_lfsrunmask_triangleamplitude\r
+ * @{\r
+ */\r
+\r
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
+\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_3) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_7) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_15) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_31) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_63) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_127) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_255) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_511) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_4095))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_output_buffer \r
+ * @{\r
+ */\r
+\r
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_Channel_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Channel_1 ((uint32_t)0x00000000)\r
+#define DAC_Channel_2 ((uint32_t)0x00000010)\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
+ ((CHANNEL) == DAC_Channel_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignment \r
+ * @{\r
+ */\r
+\r
+#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
+#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
+#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
+ ((WAVE) == DAC_Wave_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data \r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DAC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
+ \r
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the DAC configuration to the default reset state *****/ \r
+void DAC_DeInit(void);\r
+\r
+/* DAC channels configuration: trigger, output buffer, data format functions */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
+\r
+/* DMA management functions ***************************************************/\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_DAC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dbgmcu.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the DBGMCU \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DBGMCU_H\r
+#define __STM32L1xx_DBGMCU_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DBGMCU\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)\r
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)\r
+#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)\r
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+uint32_t DBGMCU_GetREVID(void);\r
+uint32_t DBGMCU_GetDEVID(void);\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_DBGMCU_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dma.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the DMA firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DMA_H\r
+#define __STM32L1xx_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DMA Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
+ This parameter can be a value of @ref DMA_data_transfer_direction */\r
+\r
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
+ or DMA_MemoryDataSize members depending in the transfer direction. */\r
+\r
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
+\r
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_memory_incremented_mode */\r
+\r
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_peripheral_data_size */\r
+\r
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_memory_data_size */\r
+\r
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_circular_normal_mode\r
+ @note: The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Channel */\r
+\r
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_priority_level */\r
+\r
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
+ This parameter can be a value of @ref DMA_memory_to_memory */\r
+}DMA_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
+ ((PERIPH) == DMA1_Channel2) || \\r
+ ((PERIPH) == DMA1_Channel3) || \\r
+ ((PERIPH) == DMA1_Channel4) || \\r
+ ((PERIPH) == DMA1_Channel5) || \\r
+ ((PERIPH) == DMA1_Channel6) || \\r
+ ((PERIPH) == DMA1_Channel7) || \\r
+ ((PERIPH) == DMA2_Channel1) || \\r
+ ((PERIPH) == DMA2_Channel2) || \\r
+ ((PERIPH) == DMA2_Channel3) || \\r
+ ((PERIPH) == DMA2_Channel4) || \\r
+ ((PERIPH) == DMA2_Channel5))\r
+\r
+/** @defgroup DMA_data_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
+ ((DIR) == DMA_DIR_PeripheralSRC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
+ ((STATE) == DMA_PeripheralInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
+ ((STATE) == DMA_MemoryInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_MemoryDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_circular_normal_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
+#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_priority_level \r
+ * @{\r
+ */\r
+\r
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
+#define DMA_Priority_High ((uint32_t)0x00002000)\r
+#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
+#define DMA_Priority_Low ((uint32_t)0x00000000)\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
+ ((PRIORITY) == DMA_Priority_High) || \\r
+ ((PRIORITY) == DMA_Priority_Medium) || \\r
+ ((PRIORITY) == DMA_Priority_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_to_memory \r
+ * @{\r
+ */\r
+\r
+#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
+#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define DMA_IT_TC ((uint32_t)0x00000002)\r
+#define DMA_IT_HT ((uint32_t)0x00000004)\r
+#define DMA_IT_TE ((uint32_t)0x00000008)\r
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
+\r
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
+\r
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)\r
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)\r
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)\r
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)\r
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)\r
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)\r
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)\r
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)\r
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)\r
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)\r
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)\r
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)\r
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)\r
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)\r
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)\r
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)\r
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)\r
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)\r
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)\r
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)\r
+\r
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))\r
+\r
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \\r
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \\r
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \\r
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \\r
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \\r
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \\r
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \\r
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \\r
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \\r
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \\r
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flags_definition \r
+ * @{\r
+ */\r
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
+\r
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)\r
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)\r
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)\r
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)\r
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)\r
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)\r
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)\r
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)\r
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)\r
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)\r
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)\r
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)\r
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)\r
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)\r
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)\r
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)\r
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)\r
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)\r
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)\r
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))\r
+\r
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \\r
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \\r
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \\r
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \\r
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \\r
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \\r
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \\r
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \\r
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \\r
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \\r
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Buffer_Size \r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the DMA configuration to the default reset state *****/ \r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
+\r
+/* Data Counter functions *****************************************************/\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);\r
+void DMA_ClearFlag(uint32_t DMAy_FLAG);\r
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);\r
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_DMA_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_exti.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the EXTI firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_EXTI_H\r
+#define __STM32L1xx_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief EXTI mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+ * @brief EXTI Trigger enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C, \r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+ ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/** \r
+ * @brief EXTI Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
+ This parameter can be any combination of @ref EXTI_Lines */\r
+ \r
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+ This parameter can be a value of @ref EXTITrigger_TypeDef */\r
+\r
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+}EXTI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Lines \r
+ * @{\r
+ */\r
+\r
+#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */\r
+#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */\r
+#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */\r
+#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */\r
+#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */\r
+#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */\r
+#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */\r
+#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */\r
+#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */\r
+#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */\r
+#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */\r
+#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */\r
+#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */\r
+#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */\r
+#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */\r
+#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */\r
+#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 \r
+ Connected to the PVD Output */\r
+#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17 \r
+ Connected to the RTC Alarm \r
+ event */\r
+#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18 \r
+ Connected to the USB Device \r
+ FS Wakeup from suspend event */\r
+#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19 \r
+ Connected to the RTC Tamper \r
+ and Time Stamp events */ \r
+#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 \r
+ Connected to the RTC Wakeup \r
+ event */\r
+#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 \r
+ Connected to the Comparator 1 \r
+ event */\r
+\r
+#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 \r
+ Connected to the Comparator 2\r
+ event */\r
+\r
+#define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23 \r
+ Comparator channel acquisition event */\r
+\r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \\r
+ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \\r
+ ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the EXTI configuration to the default reset state *****/\r
+void EXTI_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_EXTI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the FLASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_FLASH_H\r
+#define __STM32L1xx_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief FLASH Status \r
+ */ \r
+typedef enum\r
+{ \r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_ERROR_PROGRAM,\r
+ FLASH_COMPLETE,\r
+ FLASH_TIMEOUT\r
+}FLASH_Status;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup FLASH_Latency \r
+ * @{\r
+ */ \r
+#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Interrupts \r
+ * @{\r
+ */\r
+ \r
+#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */\r
+#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Address \r
+ * @{\r
+ */\r
+ \r
+#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))\r
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Option_Bytes_Write_Protection \r
+ * @{\r
+ */\r
+ \r
+#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */\r
+#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */\r
+#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */\r
+#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */\r
+#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */\r
+#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */\r
+#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */\r
+#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */\r
+#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */\r
+#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */\r
+#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */\r
+#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */\r
+#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */\r
+#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */\r
+#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */\r
+#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */\r
+#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */\r
+#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */\r
+#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */\r
+#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */\r
+#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */\r
+#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */\r
+#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */\r
+#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */\r
+#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */\r
+#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */\r
+#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */\r
+#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */\r
+#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */\r
+#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */\r
+#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */\r
+#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */\r
+\r
+#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
+\r
+#define OB_WRP1_Pages512to527 ((uint32_t)0x00000001) /* Write protection of Sector32 */\r
+#define OB_WRP1_Pages528to543 ((uint32_t)0x00000002) /* Write protection of Sector33 */\r
+#define OB_WRP1_Pages544to559 ((uint32_t)0x00000004) /* Write protection of Sector34 */\r
+#define OB_WRP1_Pages560to575 ((uint32_t)0x00000008) /* Write protection of Sector35 */\r
+#define OB_WRP1_Pages576to591 ((uint32_t)0x00000010) /* Write protection of Sector36 */\r
+#define OB_WRP1_Pages592to607 ((uint32_t)0x00000020) /* Write protection of Sector37 */\r
+#define OB_WRP1_Pages608to623 ((uint32_t)0x00000040) /* Write protection of Sector38 */\r
+#define OB_WRP1_Pages624to639 ((uint32_t)0x00000080) /* Write protection of Sector39 */\r
+#define OB_WRP1_Pages640to655 ((uint32_t)0x00000100) /* Write protection of Sector40 */\r
+#define OB_WRP1_Pages656to671 ((uint32_t)0x00000200) /* Write protection of Sector41 */\r
+#define OB_WRP1_Pages672to687 ((uint32_t)0x00000400) /* Write protection of Sector42 */\r
+#define OB_WRP1_Pages688to703 ((uint32_t)0x00000800) /* Write protection of Sector43 */\r
+#define OB_WRP1_Pages704to719 ((uint32_t)0x00001000) /* Write protection of Sector44 */\r
+#define OB_WRP1_Pages720to735 ((uint32_t)0x00002000) /* Write protection of Sector45 */\r
+#define OB_WRP1_Pages736to751 ((uint32_t)0x00004000) /* Write protection of Sector46 */\r
+#define OB_WRP1_Pages752to767 ((uint32_t)0x00008000) /* Write protection of Sector47 */\r
+#define OB_WRP1_Pages768to783 ((uint32_t)0x00010000) /* Write protection of Sector48 */\r
+#define OB_WRP1_Pages784to799 ((uint32_t)0x00020000) /* Write protection of Sector49 */\r
+#define OB_WRP1_Pages800to815 ((uint32_t)0x00040000) /* Write protection of Sector50 */\r
+#define OB_WRP1_Pages816to831 ((uint32_t)0x00080000) /* Write protection of Sector51 */\r
+#define OB_WRP1_Pages832to847 ((uint32_t)0x00100000) /* Write protection of Sector52 */\r
+#define OB_WRP1_Pages848to863 ((uint32_t)0x00200000) /* Write protection of Sector53 */\r
+#define OB_WRP1_Pages864to879 ((uint32_t)0x00400000) /* Write protection of Sector54 */\r
+#define OB_WRP1_Pages880to895 ((uint32_t)0x00800000) /* Write protection of Sector55 */\r
+#define OB_WRP1_Pages896to911 ((uint32_t)0x01000000) /* Write protection of Sector56 */\r
+#define OB_WRP1_Pages912to927 ((uint32_t)0x02000000) /* Write protection of Sector57 */\r
+#define OB_WRP1_Pages928to943 ((uint32_t)0x04000000) /* Write protection of Sector58 */\r
+#define OB_WRP1_Pages944to959 ((uint32_t)0x08000000) /* Write protection of Sector59 */\r
+#define OB_WRP1_Pages960to975 ((uint32_t)0x10000000) /* Write protection of Sector60 */\r
+#define OB_WRP1_Pages976to991 ((uint32_t)0x20000000) /* Write protection of Sector61 */\r
+#define OB_WRP1_Pages992to1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */\r
+#define OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */\r
+\r
+#define OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
+\r
+#define OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */\r
+#define OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */\r
+#define OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */\r
+#define OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */\r
+#define OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */\r
+#define OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */\r
+#define OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */\r
+#define OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */\r
+#define OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */\r
+#define OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */\r
+#define OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */\r
+#define OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */\r
+#define OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */\r
+#define OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */\r
+#define OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */\r
+#define OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */\r
+#define OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */\r
+#define OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */\r
+#define OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */\r
+#define OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */\r
+#define OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */\r
+#define OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */\r
+#define OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */\r
+#define OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */\r
+#define OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */\r
+#define OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */\r
+#define OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */\r
+#define OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */\r
+#define OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */\r
+#define OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */\r
+#define OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */\r
+#define OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */\r
+\r
+#define OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
+\r
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_Read_Protection \r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Read Protection Level \r
+ */ \r
+#define OB_RDP_Level_0 ((uint8_t)0xAA)\r
+#define OB_RDP_Level_1 ((uint8_t)0xBB)\r
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 \r
+ it's no more possible to go back to level 1 or 0 */\r
+\r
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\\r
+ ((LEVEL) == OB_RDP_Level_1))/*||\\r
+ ((LEVEL) == OB_RDP_Level_2))*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Option_Bytes_IWatchdog \r
+ * @{\r
+ */\r
+\r
+#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */\r
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STOP \r
+ * @{\r
+ */\r
+\r
+#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STDBY \r
+ * @{\r
+ */\r
+\r
+#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_BOOT\r
+ * @{\r
+ */\r
+\r
+#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position\r
+ and this parameter is selected the device will boot from Bank 2 \r
+ or Bank 1, depending on the activation of the bank */\r
+#define OB_BOOT_BANK1 ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position\r
+ and this parameter is selected the device will boot from Bank1(Default) */\r
+#define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_BOR_Level \r
+ * @{\r
+ */\r
+\r
+#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD \r
+ power supply reaches the PDR(Power Down Reset) threshold (1.5V) */\r
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */\r
+#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */\r
+#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */\r
+#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */\r
+#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */\r
+\r
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \\r
+ ((LEVEL) == OB_BOR_LEVEL1) || \\r
+ ((LEVEL) == OB_BOR_LEVEL2) || \\r
+ ((LEVEL) == OB_BOR_LEVEL3) || \\r
+ ((LEVEL) == OB_BOR_LEVEL4) || \\r
+ ((LEVEL) == OB_BOR_LEVEL5))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Flags \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */\r
+#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */\r
+#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
+#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */\r
+#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */\r
+#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))\r
+\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \\r
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \\r
+ ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \\r
+ ((FLAG) == FLASH_FLAG_OPTVERRUSR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Keys \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */\r
+#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 \r
+ to unlock the RUN_PD bit in FLASH_ACR */\r
+\r
+#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */\r
+#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2\r
+ to unlock the write access to the FLASH_PECR register and\r
+ data EEPROM */\r
+\r
+#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */\r
+#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2\r
+ to unlock the program memory */\r
+\r
+#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */\r
+#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to\r
+ unlock the write access to the option byte block */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup Timeout_definition \r
+ * @{\r
+ */ \r
+#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup CMSIS_Legacy \r
+ * @{\r
+ */\r
+#if defined ( __ICCARM__ ) \r
+#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk\r
+#endif\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+ \r
+/** \r
+ * @brief FLASH memory functions that can be executed from FLASH. \r
+ */ \r
+/* FLASH Interface configuration functions ************************************/ \r
+void FLASH_SetLatency(uint32_t FLASH_Latency);\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
+\r
+/* FLASH Memory Programming functions *****************************************/ \r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
+\r
+/* DATA EEPROM Programming functions ******************************************/ \r
+void DATA_EEPROM_Unlock(void);\r
+void DATA_EEPROM_Lock(void);\r
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);\r
+FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);\r
+FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);\r
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
+\r
+/* Option Bytes Programming functions *****************************************/\r
+void FLASH_OB_Unlock(void);\r
+void FLASH_OB_Lock(void);\r
+void FLASH_OB_Launch(void);\r
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
+FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);\r
+FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);\r
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
+FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);\r
+uint8_t FLASH_OB_GetUser(void);\r
+uint32_t FLASH_OB_GetWRP(void);\r
+uint32_t FLASH_OB_GetWRP1(void);\r
+uint32_t FLASH_OB_GetWRP2(void);\r
+FlagStatus FLASH_OB_GetRDP(void);\r
+uint8_t FLASH_OB_GetBOR(void);\r
+\r
+/* Interrupts and flags management functions **********************************/ \r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
+\r
+/** \r
+ * @brief FLASH memory functions that should be executed from internal SRAM.\r
+ * These functions are defined inside the "stm32l1xx_flash_ramfunc.c"\r
+ * file.\r
+ */ \r
+__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
+__RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);\r
+__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);\r
+__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);\r
+__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address);\r
+__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_FLASH_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_fsmc.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the FSMC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_FSMC_H\r
+#define __STM32L1xx_FSMC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FSMC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief Timing parameters For NOR/SRAM Banks \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address setup time. \r
+ This parameter can be a value between 0 and 0xF.\r
+ @note It is not used with synchronous NOR Flash memories. */\r
+\r
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address hold time.\r
+ This parameter can be a value between 0 and 0xF. \r
+ @note It is not used with synchronous NOR Flash memories.*/\r
+\r
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the data setup time.\r
+ This parameter can be a value between 0 and 0xFF.\r
+ @note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */\r
+\r
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the bus turnaround.\r
+ This parameter can be a value between 0 and 0xF.\r
+ @note It is only used for multiplexed NOR Flash memories. */\r
+\r
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.\r
+ This parameter can be a value between 1 and 0xF.\r
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */\r
+\r
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue\r
+ to the memory before getting the first data.\r
+ The parameter value depends on the memory type as shown below:\r
+ - It must be set to 0 in case of a CRAM\r
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses\r
+ - It may assume a value between 0 and 0xF in NOR Flash memories\r
+ with synchronous burst mode enable */\r
+\r
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. \r
+ This parameter can be a value of @ref FSMC_Access_Mode */\r
+}FSMC_NORSRAMTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NOR/SRAM Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.\r
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */\r
+\r
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are\r
+ multiplexed on the databus or not. \r
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */\r
+\r
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to\r
+ the corresponding memory bank.\r
+ This parameter can be a value of @ref FSMC_Memory_Type */\r
+\r
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be a value of @ref FSMC_Data_Width */\r
+\r
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r
+ valid only with synchronous burst Flash memories.\r
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */\r
+ \r
+ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,\r
+ valid only with asynchronous Flash memories.\r
+ This parameter can be a value of @ref FSMC_AsynchronousWait */\r
+\r
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r
+ the Flash memory in burst mode.\r
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */\r
+\r
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash\r
+ memory, valid only when accessing Flash memories in burst mode.\r
+ This parameter can be a value of @ref FSMC_Wrap_Mode */\r
+\r
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r
+ clock cycle before the wait state or during the wait state,\r
+ valid only when accessing memories in burst mode. \r
+ This parameter can be a value of @ref FSMC_Wait_Timing */\r
+\r
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. \r
+ This parameter can be a value of @ref FSMC_Write_Operation */\r
+\r
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait\r
+ signal, valid for Flash memory access in burst mode. \r
+ This parameter can be a value of @ref FSMC_Wait_Signal */\r
+\r
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.\r
+ This parameter can be a value of @ref FSMC_Extended_Mode */\r
+\r
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.\r
+ This parameter can be a value of @ref FSMC_Write_Burst */ \r
+\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ \r
+\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ \r
+}FSMC_NORSRAMInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup FSMC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_NORSRAM_Bank \r
+ * @{\r
+ */\r
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r
+\r
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup NOR_SRAM_Controller \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
+ ((MUX) == FSMC_DataAddressMux_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Memory_Type \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
+ ((MEMORY) == FSMC_MemoryType_NOR))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Width \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Burst_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
+ ((STATE) == FSMC_BurstAccessMode_Enable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FSMC_AsynchronousWait \r
+ * @{\r
+ */\r
+#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)\r
+#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)\r
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \\r
+ ((STATE) == FSMC_AsynchronousWait_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FSMC_Wait_Signal_Polarity \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
+ ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wrap_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
+ ((MODE) == FSMC_WrapMode_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Timing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Operation \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
+ ((OPERATION) == FSMC_WriteOperation_Enable))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Signal \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
+ ((SIGNAL) == FSMC_WaitSignal_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Extended_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r
+\r
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
+ ((MODE) == FSMC_ExtendedMode_Enable)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Burst \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
+ ((BURST) == FSMC_WriteBurst_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Hold_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Bus_Turn_around_Duration \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_CLK_Division \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Latency \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r
+#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
+ ((MODE) == FSMC_AccessMode_B) || \\r
+ ((MODE) == FSMC_AccessMode_C) || \\r
+ ((MODE) == FSMC_AccessMode_D)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+/* NOR/SRAM Controller functions **********************************************/\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_FSMC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the GPIO \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_GPIO_H\r
+#define __STM32L1xx_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+ ((PERIPH) == GPIOB) || \\r
+ ((PERIPH) == GPIOC) || \\r
+ ((PERIPH) == GPIOD) || \\r
+ ((PERIPH) == GPIOE) || \\r
+ ((PERIPH) == GPIOH) || \\r
+ ((PERIPH) == GPIOF) || \\r
+ ((PERIPH) == GPIOG))\r
+\r
+/** @defgroup Configuration_Mode_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */\r
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */\r
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */\r
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */\r
+}GPIOMode_TypeDef;\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \\r
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Output_type_enumeration\r
+ * @{\r
+ */ \r
+typedef enum\r
+{ GPIO_OType_PP = 0x00,\r
+ GPIO_OType_OD = 0x01\r
+}GPIOOType_TypeDef;\r
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Output_Maximum_frequency_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */\r
+ GPIO_Speed_2MHz = 0x01, /*!< Low Speed */\r
+ GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */\r
+ GPIO_Speed_40MHz = 0x03 /*!< High Speed */\r
+}GPIOSpeed_TypeDef;\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
+ ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ GPIO_PuPd_NOPULL = 0x00,\r
+ GPIO_PuPd_UP = 0x01,\r
+ GPIO_PuPd_DOWN = 0x02\r
+}GPIOPuPd_TypeDef;\r
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\r
+ ((PUPD) == GPIO_PuPd_DOWN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration\r
+ * @{\r
+ */\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** \r
+ * @brief GPIO Init structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIOMode_TypeDef */\r
+\r
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.\r
+ This parameter can be a value of @ref GPIOOType_TypeDef */\r
+\r
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */\r
+}GPIO_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup GPIO_pins_define \r
+ * @{\r
+ */\r
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+ ((PIN) == GPIO_Pin_1) || \\r
+ ((PIN) == GPIO_Pin_2) || \\r
+ ((PIN) == GPIO_Pin_3) || \\r
+ ((PIN) == GPIO_Pin_4) || \\r
+ ((PIN) == GPIO_Pin_5) || \\r
+ ((PIN) == GPIO_Pin_6) || \\r
+ ((PIN) == GPIO_Pin_7) || \\r
+ ((PIN) == GPIO_Pin_8) || \\r
+ ((PIN) == GPIO_Pin_9) || \\r
+ ((PIN) == GPIO_Pin_10) || \\r
+ ((PIN) == GPIO_Pin_11) || \\r
+ ((PIN) == GPIO_Pin_12) || \\r
+ ((PIN) == GPIO_Pin_13) || \\r
+ ((PIN) == GPIO_Pin_14) || \\r
+ ((PIN) == GPIO_Pin_15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+ * @{\r
+ */ \r
+#define GPIO_PinSource0 ((uint8_t)0x00)\r
+#define GPIO_PinSource1 ((uint8_t)0x01)\r
+#define GPIO_PinSource2 ((uint8_t)0x02)\r
+#define GPIO_PinSource3 ((uint8_t)0x03)\r
+#define GPIO_PinSource4 ((uint8_t)0x04)\r
+#define GPIO_PinSource5 ((uint8_t)0x05)\r
+#define GPIO_PinSource6 ((uint8_t)0x06)\r
+#define GPIO_PinSource7 ((uint8_t)0x07)\r
+#define GPIO_PinSource8 ((uint8_t)0x08)\r
+#define GPIO_PinSource9 ((uint8_t)0x09)\r
+#define GPIO_PinSource10 ((uint8_t)0x0A)\r
+#define GPIO_PinSource11 ((uint8_t)0x0B)\r
+#define GPIO_PinSource12 ((uint8_t)0x0C)\r
+#define GPIO_PinSource13 ((uint8_t)0x0D)\r
+#define GPIO_PinSource14 ((uint8_t)0x0E)\r
+#define GPIO_PinSource15 ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+ ((PINSOURCE) == GPIO_PinSource1) || \\r
+ ((PINSOURCE) == GPIO_PinSource2) || \\r
+ ((PINSOURCE) == GPIO_PinSource3) || \\r
+ ((PINSOURCE) == GPIO_PinSource4) || \\r
+ ((PINSOURCE) == GPIO_PinSource5) || \\r
+ ((PINSOURCE) == GPIO_PinSource6) || \\r
+ ((PINSOURCE) == GPIO_PinSource7) || \\r
+ ((PINSOURCE) == GPIO_PinSource8) || \\r
+ ((PINSOURCE) == GPIO_PinSource9) || \\r
+ ((PINSOURCE) == GPIO_PinSource10) || \\r
+ ((PINSOURCE) == GPIO_PinSource11) || \\r
+ ((PINSOURCE) == GPIO_PinSource12) || \\r
+ ((PINSOURCE) == GPIO_PinSource13) || \\r
+ ((PINSOURCE) == GPIO_PinSource14) || \\r
+ ((PINSOURCE) == GPIO_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Alternat_function_selection_define \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief AF 0 selection \r
+ */ \r
+#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */\r
+#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */\r
+#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */\r
+#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */\r
+#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */\r
+#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 1 selection \r
+ */ \r
+#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 2 selection \r
+ */ \r
+#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */\r
+#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */\r
+#define GPIO_AF_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */\r
+/** \r
+ * @brief AF 3 selection \r
+ */ \r
+#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */\r
+#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */\r
+#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */\r
+/** \r
+ * @brief AF 4 selection \r
+ */ \r
+#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */\r
+#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 5 selection \r
+ */ \r
+#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */\r
+#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 6 selection \r
+ */ \r
+#define GPIO_AF_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */\r
+/** \r
+ * @brief AF 7 selection \r
+ */ \r
+#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */\r
+#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */\r
+#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */\r
+/** \r
+ * @brief AF 8 selection \r
+ */ \r
+#define GPIO_AF_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */\r
+#define GPIO_AF_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */\r
+/** \r
+ * @brief AF 10 selection \r
+ */ \r
+#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */\r
+/** \r
+ * @brief AF 11 selection \r
+ */ \r
+#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */\r
+/** \r
+ * @brief AF 12 selection \r
+ */ \r
+#define GPIO_AF_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */\r
+#define GPIO_AF_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */\r
+/** \r
+ * @brief AF 14 selection \r
+ */ \r
+#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 15 selection \r
+ */ \r
+#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \\r
+ ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \\r
+ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \\r
+ ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \\r
+ ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \\r
+ ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \\r
+ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \\r
+ ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \\r
+ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \\r
+ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \\r
+ ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \\r
+ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_SPI3) || \\r
+ ((AF) == GPIO_AF_UART4) || ((AF) == GPIO_AF_UART5) || \\r
+ ((AF) == GPIO_AF_FSMC) || ((AF) == GPIO_AF_SDIO) || \\r
+ ((AF) == GPIO_AF_EVENTOUT))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Legacy \r
+ * @{\r
+ */\r
+ \r
+#define GPIO_Mode_AIN GPIO_Mode_AN\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the GPIO configuration to the default reset state ****/\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+\r
+/* GPIO Read and Write functions **********************************************/\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+\r
+/* GPIO Alternate functions configuration functions ***************************/\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_GPIO_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the I2C firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_I2C_H\r
+#define __STM32L1xx_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief I2C Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
+ This parameter must be set to a value lower than 400kHz */\r
+\r
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
+ This parameter can be a value of @ref I2C_mode */\r
+\r
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
+\r
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
+ This parameter can be a value of @ref I2C_acknowledgement */\r
+\r
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
+ This parameter can be a value of @ref I2C_acknowledged_address */\r
+}I2C_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup I2C_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
+ ((PERIPH) == I2C2))\r
+/** @defgroup I2C_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_Mode_I2C ((uint16_t)0x0000)\r
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+ ((MODE) == I2C_Mode_SMBusDevice) || \\r
+ ((MODE) == I2C_Mode_SMBusHost))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_duty_cycle_in_fast_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
+ ((CYCLE) == I2C_DutyCycle_2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_acknowledgement\r
+ * @{\r
+ */\r
+\r
+#define I2C_Ack_Enable ((uint16_t)0x0400)\r
+#define I2C_Ack_Disable ((uint16_t)0x0000)\r
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
+ ((STATE) == I2C_Ack_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
+#define I2C_Direction_Receiver ((uint8_t)0x01)\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+ ((DIRECTION) == I2C_Direction_Receiver))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_acknowledged_address \r
+ * @{\r
+ */\r
+\r
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_registers \r
+ * @{\r
+ */\r
+\r
+#define I2C_Register_CR1 ((uint8_t)0x00)\r
+#define I2C_Register_CR2 ((uint8_t)0x04)\r
+#define I2C_Register_OAR1 ((uint8_t)0x08)\r
+#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
+#define I2C_Register_DR ((uint8_t)0x10)\r
+#define I2C_Register_SR1 ((uint8_t)0x14)\r
+#define I2C_Register_SR2 ((uint8_t)0x18)\r
+#define I2C_Register_CCR ((uint8_t)0x1C)\r
+#define I2C_Register_TRISE ((uint8_t)0x20)\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+ ((REGISTER) == I2C_Register_CR2) || \\r
+ ((REGISTER) == I2C_Register_OAR1) || \\r
+ ((REGISTER) == I2C_Register_OAR2) || \\r
+ ((REGISTER) == I2C_Register_DR) || \\r
+ ((REGISTER) == I2C_Register_SR1) || \\r
+ ((REGISTER) == I2C_Register_SR2) || \\r
+ ((REGISTER) == I2C_Register_CCR) || \\r
+ ((REGISTER) == I2C_Register_TRISE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_SMBus_alert_pin_level \r
+ * @{\r
+ */\r
+\r
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
+ ((ALERT) == I2C_SMBusAlert_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_PEC_position \r
+ * @{\r
+ */\r
+\r
+#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
+ ((POSITION) == I2C_PECPosition_Current))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_NACK_position \r
+ * @{\r
+ */\r
+\r
+#define I2C_NACKPosition_Next ((uint16_t)0x0800)\r
+#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)\r
+#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \\r
+ ((POSITION) == I2C_NACKPosition_Current))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_BUF ((uint16_t)0x0400)\r
+#define I2C_IT_EVT ((uint16_t)0x0200)\r
+#define I2C_IT_ERR ((uint16_t)0x0100)\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
+#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
+#define I2C_IT_OVR ((uint32_t)0x01000800)\r
+#define I2C_IT_AF ((uint32_t)0x01000400)\r
+#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
+#define I2C_IT_BERR ((uint32_t)0x01000100)\r
+#define I2C_IT_TXE ((uint32_t)0x06000080)\r
+#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
+#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
+#define I2C_IT_BTF ((uint32_t)0x02000004)\r
+#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
+#define I2C_IT_SB ((uint32_t)0x02000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_flags_definition \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SR2 register flags \r
+ */\r
+\r
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
+\r
+/** \r
+ * @brief SR1 register flags \r
+ */\r
+\r
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
+#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
+#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+ ((FLAG) == I2C_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Events \r
+ * @{\r
+ */\r
+\r
+/**\r
+ ===============================================================================\r
+ I2C Master Events (Events grouped in order of communication)\r
+ ===============================================================================\r
+ */\r
+\r
+/** \r
+ * @brief Communication start\r
+ * \r
+ * After sending the START condition (I2C_GenerateSTART() function) the master \r
+ * has to wait for this event. It means that the Start condition has been correctly \r
+ * released on the I2C bus (the bus is free, no other devices is communicating).\r
+ * \r
+ */\r
+/* --EV5 */\r
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
+\r
+/** \r
+ * @brief Address Acknowledge\r
+ * \r
+ * After checking on EV5 (start condition correctly released on the bus), the \r
+ * master sends the address of the slave(s) with which it will communicate \r
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
+ * his address. If an acknowledge is sent on the bus, one of the following events will \r
+ * be set:\r
+ * \r
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
+ * event is set.\r
+ * \r
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
+ * is set\r
+ * \r
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
+ * function). Then master should wait on EV9. It means that the 10-bit addressing \r
+ * header has been correctly sent on the bus. Then master should send the second part of \r
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
+ * should wait for event EV6. \r
+ * \r
+ */\r
+\r
+/* --EV6 */\r
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
+/* --EV9 */\r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * If a communication is established (START condition generated and slave address \r
+ * acknowledged) then the master has to check on one of the following events for \r
+ * communication procedures:\r
+ * \r
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
+ * the data received from the slave (I2C_ReceiveData() function).\r
+ * \r
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
+ * function) then to wait on event EV8 or EV8_2.\r
+ * These two events are similar: \r
+ * - EV8 means that the data has been written in the data register and is \r
+ * being shifted out.\r
+ * - EV8_2 means that the data has been physically shifted out and output \r
+ * on the bus.\r
+ * In most cases, using EV8 is sufficient for the application.\r
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
+ * (before Stop condition generation).\r
+ * \r
+ * @note In case the user software does not guarantee that this event EV7 is \r
+ * managed before the current byte end of transfer, then user may check on EV7 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ * \r
+ */\r
+\r
+/* Master RECEIVER mode -----------------------------*/ \r
+/* --EV7 */\r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
+\r
+/* Master TRANSMITTER mode --------------------------*/\r
+/* --EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
+/* --EV8_2 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
+\r
+\r
+/**\r
+ ===============================================================================\r
+ I2C Slave Events (Events grouped in order of communication)\r
+ ===============================================================================\r
+ */\r
+\r
+\r
+/** \r
+ * @brief Communication start events\r
+ * \r
+ * Wait on one of these events at the start of the communication. It means that \r
+ * the I2C peripheral detected a Start condition on the bus (generated by master \r
+ * device) followed by the peripheral address. The peripheral generates an ACK \r
+ * condition on the bus (if the acknowledge feature is enabled through function \r
+ * I2C_AcknowledgeConfig()) and the events listed above are set :\r
+ * \r
+ * 1) In normal case (only one address managed by the slave), when the address \r
+ * sent by the master matches the own address of the peripheral (configured by \r
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
+ * (where XXX could be TRANSMITTER or RECEIVER).\r
+ * \r
+ * 2) In case the address sent by the master matches the second address of the \r
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
+ * \r
+ * 3) In case the address sent by the master is General Call (address 0x00) and \r
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
+ * \r
+ */\r
+\r
+/* --EV1 (all the events below are variants of EV1) */ \r
+/* 1) Case of One Single Address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+\r
+/* 2) Case of Dual address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
+\r
+/* 3) Case of General Call enabled for the slave */\r
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * Wait on one of these events when EV1 has already been checked and: \r
+ * \r
+ * - Slave RECEIVER mode:\r
+ * - EV2: When the application is expecting a data byte to be received. \r
+ * - EV4: When the application is expecting the end of the communication: master \r
+ * sends a stop condition and data transmission is stopped.\r
+ * \r
+ * - Slave Transmitter mode:\r
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
+ * used when the user software doesn't guarantee the EV3 is managed before the\r
+ * current byte end of transfer.\r
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
+ * shall end (before sending the STOP condition). In this case slave has to stop sending \r
+ * data bytes and expect a Stop condition on the bus.\r
+ * \r
+ * @note In case the user software does not guarantee that the event EV2 is \r
+ * managed before the current byte end of transfer, then user may check on EV2 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ *\r
+ */\r
+\r
+/* Slave RECEIVER mode --------------------------*/ \r
+/* --EV2 */\r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
+/* --EV4 */\r
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
+\r
+/* Slave TRANSMITTER mode -----------------------*/\r
+/* --EV3 */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
+/* --EV3_2 */\r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
+\r
+/*\r
+ ===============================================================================\r
+ End of Events Description\r
+ ===============================================================================\r
+ */\r
+\r
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_own_address1 \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_clock_speed \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the I2C configuration to the default reset state *****/\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);\r
+\r
+/* PEC management functions ***************************************************/ \r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+\r
+\r
+/* Interrupts, events and flags management functions **************************/\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
+\r
+/*\r
+\r
+ ===============================================================================\r
+ I2C State Monitoring Functions\r
+ ===============================================================================\r
+ This I2C driver provides three different ways for I2C state monitoring\r
+ depending on the application requirements and constraints:\r
+ \r
+ \r
+ 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
+ -----------------------------------------------------------\r
+ It compares the status registers (SR1 and SR2) content to a given event\r
+ (can be the combination of one or more flags).\r
+ It returns SUCCESS if the current status includes the given flags \r
+ and returns ERROR if one or more flags are missing in the current status.\r
+\r
+ - When to use\r
+ - This function is suitable for most applications as well as for startup \r
+ activity since the events are fully described in the product reference \r
+ manual (RM0038).\r
+ - It is also suitable for users who need to define their own events.\r
+\r
+ - Limitations\r
+ - If an error occurs (ie. error flags are set besides to the monitored \r
+ flags), the I2C_CheckEvent() function may return SUCCESS despite \r
+ the communication hold or corrupted real state. \r
+ In this case, it is advised to use error interrupts to monitor \r
+ the error events and handle them in the interrupt IRQ handler.\r
+ \r
+ Note\r
+ For error management, it is advised to use the following functions:\r
+ - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
+ Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
+ I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
+ - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
+ and/or I2C_GenerateStop() in order to clear the error flag and source \r
+ and return to correct communciation status.\r
+ \r
+ \r
+ 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
+ -------------------------------------------------------------------- \r
+ Using the function I2C_GetLastEvent() which returns the image of both status \r
+ registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ by 16 bits and concatenated to Status Register 1).\r
+\r
+ - When to use\r
+ - This function is suitable for the same applications above but it \r
+ allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
+ function.\r
+ - The returned value could be compared to events already defined in \r
+ the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
+ This function is suitable when multiple flags are monitored at the \r
+ same time.\r
+ - At the opposite of I2C_CheckEvent() function, this function allows \r
+ user to choose when an event is accepted (when all events flags are \r
+ set and no other flags are set or just when the needed flags are set \r
+ like I2C_CheckEvent() function.\r
+\r
+ - Limitations\r
+ - User may need to define his own events.\r
+ - Same remark concerning the error management is applicable for this \r
+ function if user decides to check only regular communication flags \r
+ (and ignores error flags).\r
+ \r
+ \r
+ 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
+ -----------------------------------------------------------------------\r
+ \r
+ Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ one single flag (ie. I2C_FLAG_RXNE ...). \r
+\r
+ - When to use\r
+ - This function could be used for specific applications or in debug \r
+ phase.\r
+ - It is suitable when only one flag checking is needed (most I2C \r
+ events are monitored through multiple flags).\r
+ - Limitations: \r
+ - When calling this function, the Status register is accessed. \r
+ Some flags are cleared when the status register is accessed. \r
+ So checking the status of one Flag, may clear other ones.\r
+ - Function may need to be called twice or more in order to monitor \r
+ one single event.\r
+\r
+ For detailed description of Events, please refer to section I2C_Events in \r
+ stm32l1xx_i2c.h file.\r
+\r
+*/\r
+\r
+/*\r
+ ===============================================================================\r
+ 1. Basic state monitoring\r
+ ===============================================================================\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
+/*\r
+ ===============================================================================\r
+ 2. Advanced state monitoring\r
+ ===============================================================================\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+/*\r
+ ===============================================================================\r
+ 3. Flag-based state monitoring\r
+ ===============================================================================\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+\r
+\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_I2C_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the IWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_IWDG_H\r
+#define __STM32L1xx_IWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_WriteAccess\r
+ * @{\r
+ */\r
+\r
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
+ ((ACCESS) == IWDG_WriteAccess_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_prescaler \r
+ * @{\r
+ */\r
+\r
+#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
+#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
+#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
+#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
+#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
+#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
+#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
+ ((PRESCALER) == IWDG_Prescaler_8) || \\r
+ ((PRESCALER) == IWDG_Prescaler_16) || \\r
+ ((PRESCALER) == IWDG_Prescaler_32) || \\r
+ ((PRESCALER) == IWDG_Prescaler_64) || \\r
+ ((PRESCALER) == IWDG_Prescaler_128)|| \\r
+ ((PRESCALER) == IWDG_Prescaler_256))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Flag \r
+ * @{\r
+ */\r
+\r
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Prescaler and Counter configuration functions ******************************/\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
+void IWDG_SetReload(uint16_t Reload);\r
+void IWDG_ReloadCounter(void);\r
+\r
+/* IWDG activation function ***************************************************/\r
+void IWDG_Enable(void);\r
+\r
+/* Flag management function ***************************************************/\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_IWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_lcd.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the LCD firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_LCD_H\r
+#define __STM32L1xx_LCD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup LCD\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+ \r
+/** \r
+ * @brief LCD Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t LCD_Prescaler; /*!< Configures the LCD Prescaler. \r
+ This parameter can be one value of @ref LCD_Prescaler */\r
+ uint32_t LCD_Divider; /*!< Configures the LCD Divider.\r
+ This parameter can be one value of @ref LCD_Divider */\r
+ uint32_t LCD_Duty; /*!< Configures the LCD Duty.\r
+ This parameter can be one value of @ref LCD_Duty */\r
+ uint32_t LCD_Bias; /*!< Configures the LCD Bias.\r
+ This parameter can be one value of @ref LCD_Bias */ \r
+ uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source.\r
+ This parameter can be one value of @ref LCD_Voltage_Source */\r
+}LCD_InitTypeDef;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup LCD_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define LCD_Prescaler_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */\r
+#define LCD_Prescaler_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */\r
+#define LCD_Prescaler_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */\r
+#define LCD_Prescaler_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */\r
+#define LCD_Prescaler_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */\r
+#define LCD_Prescaler_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */\r
+#define LCD_Prescaler_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */\r
+#define LCD_Prescaler_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */\r
+#define LCD_Prescaler_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */\r
+#define LCD_Prescaler_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */\r
+#define LCD_Prescaler_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */\r
+#define LCD_Prescaler_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */\r
+#define LCD_Prescaler_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */\r
+#define LCD_Prescaler_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */\r
+#define LCD_Prescaler_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */\r
+#define LCD_Prescaler_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */\r
+\r
+#define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \\r
+ ((PRESCALER) == LCD_Prescaler_2) || \\r
+ ((PRESCALER) == LCD_Prescaler_4) || \\r
+ ((PRESCALER) == LCD_Prescaler_8) || \\r
+ ((PRESCALER) == LCD_Prescaler_16) || \\r
+ ((PRESCALER) == LCD_Prescaler_32) || \\r
+ ((PRESCALER) == LCD_Prescaler_64) || \\r
+ ((PRESCALER) == LCD_Prescaler_128) || \\r
+ ((PRESCALER) == LCD_Prescaler_256) || \\r
+ ((PRESCALER) == LCD_Prescaler_512) || \\r
+ ((PRESCALER) == LCD_Prescaler_1024) || \\r
+ ((PRESCALER) == LCD_Prescaler_2048) || \\r
+ ((PRESCALER) == LCD_Prescaler_4096) || \\r
+ ((PRESCALER) == LCD_Prescaler_8192) || \\r
+ ((PRESCALER) == LCD_Prescaler_16384) || \\r
+ ((PRESCALER) == LCD_Prescaler_32768))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LCD_Divider \r
+ * @{\r
+ */\r
+\r
+#define LCD_Divider_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */\r
+#define LCD_Divider_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */\r
+#define LCD_Divider_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */\r
+#define LCD_Divider_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */\r
+#define LCD_Divider_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */\r
+#define LCD_Divider_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */\r
+#define LCD_Divider_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */\r
+#define LCD_Divider_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */\r
+#define LCD_Divider_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */\r
+#define LCD_Divider_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */\r
+#define LCD_Divider_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */\r
+#define LCD_Divider_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */\r
+#define LCD_Divider_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */\r
+#define LCD_Divider_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */\r
+#define LCD_Divider_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */\r
+#define LCD_Divider_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */\r
+\r
+#define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \\r
+ ((DIVIDER) == LCD_Divider_17) || \\r
+ ((DIVIDER) == LCD_Divider_18) || \\r
+ ((DIVIDER) == LCD_Divider_19) || \\r
+ ((DIVIDER) == LCD_Divider_20) || \\r
+ ((DIVIDER) == LCD_Divider_21) || \\r
+ ((DIVIDER) == LCD_Divider_22) || \\r
+ ((DIVIDER) == LCD_Divider_23) || \\r
+ ((DIVIDER) == LCD_Divider_24) || \\r
+ ((DIVIDER) == LCD_Divider_25) || \\r
+ ((DIVIDER) == LCD_Divider_26) || \\r
+ ((DIVIDER) == LCD_Divider_27) || \\r
+ ((DIVIDER) == LCD_Divider_28) || \\r
+ ((DIVIDER) == LCD_Divider_29) || \\r
+ ((DIVIDER) == LCD_Divider_30) || \\r
+ ((DIVIDER) == LCD_Divider_31))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup LCD_Duty \r
+ * @{\r
+ */\r
+ \r
+#define LCD_Duty_Static ((uint32_t)0x00000000) /*!< Static duty */\r
+#define LCD_Duty_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */\r
+#define LCD_Duty_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */\r
+#define LCD_Duty_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */\r
+#define LCD_Duty_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */\r
+\r
+#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \\r
+ ((DUTY) == LCD_Duty_1_2) || \\r
+ ((DUTY) == LCD_Duty_1_3) || \\r
+ ((DUTY) == LCD_Duty_1_4) || \\r
+ ((DUTY) == LCD_Duty_1_8))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+\r
+/** @defgroup LCD_Bias \r
+ * @{\r
+ */\r
+ \r
+#define LCD_Bias_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */\r
+#define LCD_Bias_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */\r
+#define LCD_Bias_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */\r
+\r
+#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \\r
+ ((BIAS) == LCD_Bias_1_2) || \\r
+ ((BIAS) == LCD_Bias_1_3))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup LCD_Voltage_Source \r
+ * @{\r
+ */\r
+ \r
+#define LCD_VoltageSource_Internal ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */\r
+#define LCD_VoltageSource_External LCD_CR_VSEL /*!< External voltage source for the LCD */\r
+\r
+#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \\r
+ ((SOURCE) == LCD_VoltageSource_External))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_Interrupts \r
+ * @{\r
+ */\r
+#define LCD_IT_SOF LCD_FCR_SOFIE\r
+#define LCD_IT_UDD LCD_FCR_UDDIE\r
+\r
+#define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_PulseOnDuration \r
+ * @{\r
+ */\r
+\r
+#define LCD_PulseOnDuration_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */\r
+#define LCD_PulseOnDuration_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */\r
+#define LCD_PulseOnDuration_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */\r
+#define LCD_PulseOnDuration_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */\r
+#define LCD_PulseOnDuration_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */\r
+#define LCD_PulseOnDuration_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */\r
+#define LCD_PulseOnDuration_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */\r
+#define LCD_PulseOnDuration_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */\r
+\r
+#define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \\r
+ ((DURATION) == LCD_PulseOnDuration_1) || \\r
+ ((DURATION) == LCD_PulseOnDuration_2) || \\r
+ ((DURATION) == LCD_PulseOnDuration_3) || \\r
+ ((DURATION) == LCD_PulseOnDuration_4) || \\r
+ ((DURATION) == LCD_PulseOnDuration_5) || \\r
+ ((DURATION) == LCD_PulseOnDuration_6) || \\r
+ ((DURATION) == LCD_PulseOnDuration_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup LCD_DeadTime \r
+ * @{\r
+ */\r
+\r
+#define LCD_DeadTime_0 ((uint32_t)0x00000000) /*!< No dead Time */\r
+#define LCD_DeadTime_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */\r
+#define LCD_DeadTime_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */\r
+#define LCD_DeadTime_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */\r
+#define LCD_DeadTime_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */\r
+#define LCD_DeadTime_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */\r
+#define LCD_DeadTime_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */\r
+#define LCD_DeadTime_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */\r
+\r
+#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \\r
+ ((TIME) == LCD_DeadTime_1) || \\r
+ ((TIME) == LCD_DeadTime_2) || \\r
+ ((TIME) == LCD_DeadTime_3) || \\r
+ ((TIME) == LCD_DeadTime_4) || \\r
+ ((TIME) == LCD_DeadTime_5) || \\r
+ ((TIME) == LCD_DeadTime_6) || \\r
+ ((TIME) == LCD_DeadTime_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_BlinkMode \r
+ * @{\r
+ */\r
+\r
+#define LCD_BlinkMode_Off ((uint32_t)0x00000000) /*!< Blink disabled */\r
+#define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */\r
+#define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to \r
+ 8 pixels according to the programmed duty) */\r
+#define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */\r
+\r
+#define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \\r
+ ((MODE) == LCD_BlinkMode_SEG0_COM0) || \\r
+ ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \\r
+ ((MODE) == LCD_BlinkMode_AllSEG_AllCOM))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_BlinkFrequency \r
+ * @{\r
+ */\r
+\r
+#define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */\r
+#define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */\r
+#define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */\r
+#define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */\r
+#define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */\r
+#define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */\r
+#define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */\r
+#define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */\r
+\r
+#define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div1024))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Contrast \r
+ * @{\r
+ */\r
+\r
+#define LCD_Contrast_Level_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */\r
+#define LCD_Contrast_Level_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */\r
+#define LCD_Contrast_Level_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */\r
+#define LCD_Contrast_Level_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */\r
+#define LCD_Contrast_Level_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */\r
+#define LCD_Contrast_Level_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */\r
+#define LCD_Contrast_Level_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */\r
+#define LCD_Contrast_Level_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */\r
+\r
+#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_1) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_2) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_3) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_4) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_5) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_6) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_7))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LCD_Flag \r
+ * @{\r
+ */\r
+\r
+#define LCD_FLAG_ENS LCD_SR_ENS\r
+#define LCD_FLAG_SOF LCD_SR_SOF\r
+#define LCD_FLAG_UDR LCD_SR_UDR\r
+#define LCD_FLAG_UDD LCD_SR_UDD\r
+#define LCD_FLAG_RDY LCD_SR_RDY\r
+#define LCD_FLAG_FCRSF LCD_SR_FCRSR\r
+\r
+#define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \\r
+ ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \\r
+ ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF))\r
+\r
+#define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_RAMRegister \r
+ * @{\r
+ */\r
+\r
+#define LCD_RAMRegister_0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */\r
+#define LCD_RAMRegister_1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */\r
+#define LCD_RAMRegister_2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */\r
+#define LCD_RAMRegister_3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */\r
+#define LCD_RAMRegister_4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */\r
+#define LCD_RAMRegister_5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */\r
+#define LCD_RAMRegister_6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */\r
+#define LCD_RAMRegister_7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */\r
+#define LCD_RAMRegister_8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */\r
+#define LCD_RAMRegister_9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */\r
+#define LCD_RAMRegister_10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */\r
+#define LCD_RAMRegister_11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */\r
+#define LCD_RAMRegister_12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */\r
+#define LCD_RAMRegister_13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */\r
+#define LCD_RAMRegister_14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */\r
+#define LCD_RAMRegister_15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */\r
+\r
+#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \\r
+ ((REGISTER) == LCD_RAMRegister_1) || \\r
+ ((REGISTER) == LCD_RAMRegister_2) || \\r
+ ((REGISTER) == LCD_RAMRegister_3) || \\r
+ ((REGISTER) == LCD_RAMRegister_4) || \\r
+ ((REGISTER) == LCD_RAMRegister_5) || \\r
+ ((REGISTER) == LCD_RAMRegister_6) || \\r
+ ((REGISTER) == LCD_RAMRegister_7) || \\r
+ ((REGISTER) == LCD_RAMRegister_8) || \\r
+ ((REGISTER) == LCD_RAMRegister_9) || \\r
+ ((REGISTER) == LCD_RAMRegister_10) || \\r
+ ((REGISTER) == LCD_RAMRegister_11) || \\r
+ ((REGISTER) == LCD_RAMRegister_12) || \\r
+ ((REGISTER) == LCD_RAMRegister_13) || \\r
+ ((REGISTER) == LCD_RAMRegister_14) || \\r
+ ((REGISTER) == LCD_RAMRegister_15))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the LCD configuration to the default reset state *****/\r
+void LCD_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void LCD_Init(LCD_InitTypeDef* LCD_InitStruct);\r
+void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct);\r
+void LCD_Cmd(FunctionalState NewState);\r
+void LCD_WaitForSynchro(void);\r
+void LCD_HighDriveCmd(FunctionalState NewState);\r
+void LCD_MuxSegmentCmd(FunctionalState NewState);\r
+void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration);\r
+void LCD_DeadTimeConfig(uint32_t LCD_DeadTime);\r
+void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency);\r
+void LCD_ContrastConfig(uint32_t LCD_Contrast);\r
+\r
+/* LCD RAM memory write functions *********************************************/\r
+void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data);\r
+void LCD_UpdateDisplayRequest(void);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState);\r
+FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG);\r
+void LCD_ClearFlag(uint32_t LCD_FLAG);\r
+ITStatus LCD_GetITStatus(uint32_t LCD_IT);\r
+void LCD_ClearITPendingBit(uint32_t LCD_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_LCD_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_opamp.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the operational\r
+ * amplifiers (opamp) firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_OPAMP_H\r
+#define __STM32L1xx_OPAMP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup OPAMP\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup OPAMP_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup OPAMP_Selection\r
+ * @{\r
+ */\r
+\r
+#define OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD\r
+#define OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD\r
+#define OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD\r
+\r
+#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \\r
+ ((PERIPH) == OPAMP_Selection_OPAMP2) || \\r
+ ((PERIPH) == OPAMP_Selection_OPAMP3))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup OPAMP_Switches\r
+ * @{\r
+ */\r
+\r
+/* OPAMP1 Switches */\r
+#define OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1 /*!< OPAMP1 Switch 3 */\r
+#define OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1 /*!< OPAMP1 Switch 4 */\r
+#define OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1 /*!< OPAMP1 Switch 5 */\r
+#define OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1 /*!< OPAMP1 Switch 6 */\r
+#define OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1 /*!< OPAMP1 Switch ANA */\r
+\r
+/* OPAMP2 Switches */\r
+#define OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2 /*!< OPAMP2 Switch 3 */\r
+#define OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2 /*!< OPAMP2 Switch 4 */\r
+#define OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2 /*!< OPAMP2 Switch 5 */\r
+#define OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2 /*!< OPAMP2 Switch 6 */\r
+#define OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2 /*!< OPAMP2 Switch 7 */\r
+#define OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2 /*!< OPAMP2 Switch ANA */\r
+\r
+/* OPAMP3 Switches */\r
+#define OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3 /*!< OPAMP3 Switch 3 */\r
+#define OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3 /*!< OPAMP3 Switch 4 */\r
+#define OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3 /*!< OPAMP3 Switch 5 */\r
+#define OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3 /*!< OPAMP3 Switch 6 */\r
+#define OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3 /*!< OPAMP3 Switch ANA */\r
+\r
+#define IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup OPAMP_Trimming\r
+ * @{\r
+ */\r
+\r
+#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */\r
+#define OPAMP_Trimming_User OPAMP_OTR_OT_USER /*!< User trimming */\r
+\r
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \\r
+ ((TRIMMING) == OPAMP_Trimming_User))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup OPAMP_Input\r
+ * @{\r
+ */\r
+\r
+#define OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H /*!< NMOS input */\r
+#define OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L /*!< PMOS input */\r
+\r
+#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_NMOS) || \\r
+ ((INPUT) == OPAMP_Input_PMOS))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup OPAMP_TrimValue\r
+ * @{\r
+ */\r
+\r
+#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup OPAMP_PowerRange\r
+ * @{\r
+ */\r
+\r
+#define OPAMP_PowerRange_Low ((uint32_t)0x00000000) /*!< Low power range is selected (VDDA is lower than 2.4V) */\r
+#define OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE /*!< High power range is selected (VDDA is higher than 2.4V) */\r
+\r
+#define IS_OPAMP_RANGE(RANGE) (((RANGE) == OPAMP_PowerRange_Low) || \\r
+ ((RANGE) == OPAMP_PowerRange_High))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Initialization and Configuration functions *********************************/\r
+void OPAMP_DeInit(void);\r
+void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState);\r
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);\r
+void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState);\r
+void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange);\r
+\r
+/* Calibration functions ******************************************************/\r
+void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming);\r
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);\r
+void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);\r
+FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_OPAMP_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the PWR firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_PWR_H\r
+#define __STM32L1xx_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_PVD_detection_level \r
+ * @{\r
+ */ \r
+\r
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0\r
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1\r
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2\r
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3\r
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4\r
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5\r
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6\r
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage \r
+ (Compare internally to VREFINT) */\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_WakeUp_Pins \r
+ * @{\r
+ */\r
+\r
+#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)\r
+#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)\r
+#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \\r
+ ((PIN) == PWR_WakeUpPin_2) || \\r
+ ((PIN) == PWR_WakeUpPin_3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup PWR_Voltage_Scaling_Ranges\r
+ * @{\r
+ */\r
+\r
+#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0\r
+#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1\r
+#define PWR_VoltageScaling_Range3 PWR_CR_VOS\r
+\r
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \\r
+ ((RANGE) == PWR_VoltageScaling_Range2) || \\r
+ ((RANGE) == PWR_VoltageScaling_Range3))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower PWR_CR_LPSDSR\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_SLEEP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWR_STOP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag \r
+ * @{\r
+ */\r
+\r
+#define PWR_FLAG_WU PWR_CSR_WUF\r
+#define PWR_FLAG_SB PWR_CSR_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF\r
+#define PWR_FLAG_VOS PWR_CSR_VOSF\r
+#define PWR_FLAG_REGLP PWR_CSR_REGLPF\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \\r
+ ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the PWR configuration to the default reset state ******/ \r
+void PWR_DeInit(void);\r
+\r
+/* RTC Domain Access function *************************************************/ \r
+void PWR_RTCAccessCmd(FunctionalState NewState);\r
+\r
+/* PVD configuration functions ************************************************/ \r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+\r
+/* WakeUp pins configuration functions ****************************************/ \r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);\r
+\r
+/* Ultra Low Power mode configuration functions *******************************/ \r
+void PWR_FastWakeUpCmd(FunctionalState NewState);\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState);\r
+\r
+/* Voltage Scaling configuration functions ************************************/ \r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);\r
+\r
+/* Low Power modes configuration functions ************************************/ \r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState);\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+\r
+/* Flags management functions *************************************************/ \r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_PWR_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the RCC \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RCC_H\r
+#define __STM32L1xx_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ uint32_t SYSCLK_Frequency;\r
+ uint32_t HCLK_Frequency;\r
+ uint32_t PCLK1_Frequency;\r
+ uint32_t PCLK2_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_HSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_HSE_OFF ((uint8_t)0x00)\r
+#define RCC_HSE_ON ((uint8_t)0x01)\r
+#define RCC_HSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_MSI_Clock_Range \r
+ * @{\r
+ */\r
+\r
+#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */\r
+#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */\r
+#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */\r
+#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */\r
+#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */\r
+#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */\r
+#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */\r
+\r
+#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \\r
+ ((RANGE) == RCC_MSIRange_1) || \\r
+ ((RANGE) == RCC_MSIRange_2) || \\r
+ ((RANGE) == RCC_MSIRange_3) || \\r
+ ((RANGE) == RCC_MSIRange_4) || \\r
+ ((RANGE) == RCC_MSIRange_5) || \\r
+ ((RANGE) == RCC_MSIRange_6))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_PLL_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLSource_HSI ((uint8_t)0x00)\r
+#define RCC_PLLSource_HSE ((uint8_t)0x01)\r
+\r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_PLL_Multiplication_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLMul_3 ((uint8_t)0x00)\r
+#define RCC_PLLMul_4 ((uint8_t)0x04)\r
+#define RCC_PLLMul_6 ((uint8_t)0x08)\r
+#define RCC_PLLMul_8 ((uint8_t)0x0C)\r
+#define RCC_PLLMul_12 ((uint8_t)0x10)\r
+#define RCC_PLLMul_16 ((uint8_t)0x14)\r
+#define RCC_PLLMul_24 ((uint8_t)0x18)\r
+#define RCC_PLLMul_32 ((uint8_t)0x1C)\r
+#define RCC_PLLMul_48 ((uint8_t)0x20)\r
+\r
+\r
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \\r
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \\r
+ ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \\r
+ ((MUL) == RCC_PLLMul_48))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Divider_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLDiv_2 ((uint8_t)0x40)\r
+#define RCC_PLLDiv_3 ((uint8_t)0x80)\r
+#define RCC_PLLDiv_4 ((uint8_t)0xC0)\r
+\r
+\r
+#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \\r
+ ((DIV) == RCC_PLLDiv_4))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_System_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI\r
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_APB1_APB2_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup RCC_Interrupt_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_MSIRDY ((uint8_t)0x20)\r
+#define RCC_IT_LSECSS ((uint8_t)0x40)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+\r
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \\r
+ ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_LSECSS))\r
+\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_LSE_Configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_LSE_OFF ((uint8_t)0x00)\r
+#define RCC_LSE_ON ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_RTC_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE\r
+#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI\r
+#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE\r
+#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)\r
+#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)\r
+#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN\r
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN\r
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN\r
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN\r
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN\r
+#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN\r
+#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN\r
+#define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN\r
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN\r
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN\r
+#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN\r
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN\r
+#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN\r
+#define RCC_AHBPeriph_AES RCC_AHBENR_AESEN\r
+#define RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN\r
+#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN\r
+#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN\r
+#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN\r
+#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN\r
+#define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN\r
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN\r
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_APB1_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN\r
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN\r
+#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN\r
+#define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN\r
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN\r
+#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN\r
+#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN\r
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN\r
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN\r
+#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN\r
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN\r
+#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN\r
+#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN\r
+#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN\r
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN\r
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN\r
+#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN\r
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN\r
+#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN\r
+#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN\r
+\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)\r
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)\r
+#define RCC_MCOSource_HSI ((uint8_t)0x02)\r
+#define RCC_MCOSource_MSI ((uint8_t)0x03)\r
+#define RCC_MCOSource_HSE ((uint8_t)0x04)\r
+#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)\r
+#define RCC_MCOSource_LSI ((uint8_t)0x06)\r
+#define RCC_MCOSource_LSE ((uint8_t)0x07)\r
+\r
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \\r
+ ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \\r
+ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \\r
+ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO_Output_Divider \r
+ * @{\r
+ */\r
+\r
+#define RCC_MCODiv_1 ((uint8_t)0x00)\r
+#define RCC_MCODiv_2 ((uint8_t)0x10)\r
+#define RCC_MCODiv_4 ((uint8_t)0x20)\r
+#define RCC_MCODiv_8 ((uint8_t)0x30)\r
+#define RCC_MCODiv_16 ((uint8_t)0x40)\r
+\r
+#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \\r
+ ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \\r
+ ((DIV) == RCC_MCODiv_16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Flag \r
+ * @{\r
+ */\r
+\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
+#define RCC_FLAG_MSIRDY ((uint8_t)0x29)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x49)\r
+#define RCC_FLAG_LSECSS ((uint8_t)0x4A)\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)\r
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \\r
+ ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \\r
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LSECSS))\r
+\r
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the RCC clock configuration to the default reset state */\r
+void RCC_DeInit(void);\r
+\r
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/\r
+void RCC_HSEConfig(uint8_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);\r
+void RCC_MSICmd(FunctionalState NewState);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);\r
+\r
+/* System, AHB and APB busses clocks configuration functions ******************/\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+\r
+/* Peripheral clocks configuration functions **********************************/\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_RTCResetCmd(FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_RCC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rtc.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the RTC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RTC_H\r
+#define __STM32L1xx_RTC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief RTC Init structures definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.\r
+ This parameter can be a value of @ref RTC_Hour_Formats */\r
+ \r
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x7F */\r
+ \r
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x7FFF */ \r
+}RTC_InitTypeDef;\r
+\r
+/** \r
+ * @brief RTC Time structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.\r
+ This parameter must be set to a value in the 0-12 range\r
+ if the RTC_HourFormat_12 is selected or 0-23 range if\r
+ the RTC_HourFormat_24 is selected. */\r
+\r
+ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+ \r
+ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+\r
+ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.\r
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */\r
+}RTC_TimeTypeDef; \r
+\r
+/** \r
+ * @brief RTC Date structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+ \r
+ uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).\r
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */\r
+\r
+ uint8_t RTC_Date; /*!< Specifies the RTC Date.\r
+ This parameter must be set to a value in the 1-31 range. */\r
+ \r
+ uint8_t RTC_Year; /*!< Specifies the RTC Date Year.\r
+ This parameter must be set to a value in the 0-99 range. */\r
+}RTC_DateTypeDef;\r
+\r
+/** \r
+ * @brief RTC Alarm structure definition \r
+ */\r
+typedef struct\r
+{\r
+ RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */\r
+\r
+ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.\r
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r
+\r
+ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.\r
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r
+ \r
+ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.\r
+ If the Alarm Date is selected, this parameter\r
+ must be set to a value in the 1-31 range.\r
+ If the Alarm WeekDay is selected, this \r
+ parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+}RTC_AlarmTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Hour_Formats \r
+ * @{\r
+ */ \r
+#define RTC_HourFormat_24 ((uint32_t)0x00000000)\r
+#define RTC_HourFormat_12 ((uint32_t)0x00000040)\r
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \\r
+ ((FORMAT) == RTC_HourFormat_24))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Asynchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Synchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))\r
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)\r
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)\r
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_AM_PM_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_H12_AM ((uint8_t)0x00)\r
+#define RTC_H12_PM ((uint8_t)0x40)\r
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Year_Date_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Month_Date_Definitions \r
+ * @{\r
+ */ \r
+\r
+/* Coded in BCD format */\r
+#define RTC_Month_January ((uint8_t)0x01)\r
+#define RTC_Month_February ((uint8_t)0x02)\r
+#define RTC_Month_March ((uint8_t)0x03)\r
+#define RTC_Month_April ((uint8_t)0x04)\r
+#define RTC_Month_May ((uint8_t)0x05)\r
+#define RTC_Month_June ((uint8_t)0x06)\r
+#define RTC_Month_July ((uint8_t)0x07)\r
+#define RTC_Month_August ((uint8_t)0x08)\r
+#define RTC_Month_September ((uint8_t)0x09)\r
+#define RTC_Month_October ((uint8_t)0x10)\r
+#define RTC_Month_November ((uint8_t)0x11)\r
+#define RTC_Month_December ((uint8_t)0x12)\r
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))\r
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_WeekDay_Definitions \r
+ * @{\r
+ */ \r
+ \r
+#define RTC_Weekday_Monday ((uint8_t)0x01)\r
+#define RTC_Weekday_Tuesday ((uint8_t)0x02)\r
+#define RTC_Weekday_Wednesday ((uint8_t)0x03)\r
+#define RTC_Weekday_Thursday ((uint8_t)0x04)\r
+#define RTC_Weekday_Friday ((uint8_t)0x05)\r
+#define RTC_Weekday_Saturday ((uint8_t)0x06)\r
+#define RTC_Weekday_Sunday ((uint8_t)0x07)\r
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Alarm_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmDateWeekDay_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) \r
+#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) \r
+\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \\r
+ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmMask_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmMask_None ((uint32_t)0x00000000)\r
+#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) \r
+#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)\r
+#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)\r
+#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)\r
+#define RTC_AlarmMask_All ((uint32_t)0x80808080)\r
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarms_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Alarm_A ((uint32_t)0x00000100)\r
+#define RTC_Alarm_B ((uint32_t)0x00000200)\r
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))\r
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions\r
+ * @{\r
+ */ \r
+#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \r
+ There is no comparison on sub seconds \r
+ for Alarm */\r
+#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \r
+ comparison. Only SS[0] is compared. */\r
+#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \r
+ comparison. Only SS[1:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \r
+ comparison. Only SS[2:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \r
+ comparison. Only SS[3:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \r
+ comparison. Only SS[4:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \r
+ comparison. Only SS[5:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \r
+ comparison. Only SS[6:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \r
+ comparison. Only SS[7:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \r
+ comparison. Only SS[8:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \r
+ comparison. Only SS[9:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \r
+ comparison. Only SS[10:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \r
+ comparison.Only SS[11:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \r
+ comparison. Only SS[12:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \r
+ comparison.Only SS[13:0] are compared */\r
+#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \r
+ to activate alarm. */\r
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_None))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarm_Sub_Seconds_Value\r
+ * @{\r
+ */ \r
+\r
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Wakeup_Timer_Definitions \r
+ * @{\r
+ */\r
+#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)\r
+#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)\r
+#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)\r
+#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)\r
+#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)\r
+#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)\r
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \\r
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \\r
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))\r
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Stamp_Edges_definitions \r
+ * @{\r
+ */ \r
+#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)\r
+#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)\r
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \\r
+ ((EDGE) == RTC_TimeStampEdge_Falling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_selection_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Output_Disable ((uint32_t)0x00000000)\r
+#define RTC_Output_AlarmA ((uint32_t)0x00200000)\r
+#define RTC_Output_AlarmB ((uint32_t)0x00400000)\r
+#define RTC_Output_WakeUp ((uint32_t)0x00600000)\r
+ \r
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \\r
+ ((OUTPUT) == RTC_Output_AlarmA) || \\r
+ ((OUTPUT) == RTC_Output_AlarmB) || \\r
+ ((OUTPUT) == RTC_Output_WakeUp))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_Polarity_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_OutputPolarity_High ((uint32_t)0x00000000)\r
+#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)\r
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \\r
+ ((POL) == RTC_OutputPolarity_Low))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Coarse_Calibration_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_CalibSign_Positive ((uint32_t)0x00000000) \r
+#define RTC_CalibSign_Negative ((uint32_t)0x00000080)\r
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \\r
+ ((SIGN) == RTC_CalibSign_Negative))\r
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ /** @defgroup RTC_Calib_Output_selection_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) \r
+#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)\r
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \\r
+ ((OUTPUT) == RTC_CalibOutput_1Hz))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_period_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation\r
+ period is 32s, else 2exp20 RTCCLK seconds */\r
+#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \r
+ period is 16s, else 2exp19 RTCCLK seconds */\r
+#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \r
+ period is 8s, else 2exp18 RTCCLK seconds */\r
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \\r
+ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \\r
+ ((PERIOD) == RTC_SmoothCalibPeriod_8sec))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \r
+ during a X -second window = Y - CALM[8:0]. \r
+ with Y = 512, 256, 128 when X = 32, 16, 8 */\r
+#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited\r
+ during a 32-second window = CALM[8:0]. */\r
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \\r
+ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_DayLightSaving_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)\r
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \\r
+ ((SAVE) == RTC_DayLightSaving_ADD1H))\r
+\r
+#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)\r
+#define RTC_StoreOperation_Set ((uint32_t)0x00040000)\r
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \\r
+ ((OPERATION) == RTC_StoreOperation_Set))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Trigger_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)\r
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)\r
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)\r
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)\r
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Filter_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */\r
+\r
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 \r
+ consecutive samples at the active level */\r
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 \r
+ consecutive samples at the active level */\r
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 \r
+ consecutive samples at the active leve. */\r
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \\r
+ ((FILTER) == RTC_TamperFilter_2Sample) || \\r
+ ((FILTER) == RTC_TamperFilter_4Sample) || \\r
+ ((FILTER) == RTC_TamperFilter_8Sample))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 32768 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 16384 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 8192 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 4096 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 2048 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 1024 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 512 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 256 */\r
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before \r
+ sampling during 1 RTCCLK cycle */\r
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before \r
+ sampling during 2 RTCCLK cycles */\r
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before \r
+ sampling during 4 RTCCLK cycles */\r
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before \r
+ sampling during 8 RTCCLK cycles */\r
+\r
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Tamper_Pins_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for \r
+ input tamper 1 */\r
+#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for \r
+ input tamper 2 */\r
+#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for \r
+ input tamper 3 */\r
+\r
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Output_Type_ALARM_OUT \r
+ * @{\r
+ */ \r
+#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)\r
+#define RTC_OutputType_PushPull ((uint32_t)0x00040000)\r
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \\r
+ ((TYPE) == RTC_OutputType_PushPull))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions\r
+ * @{\r
+ */ \r
+#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)\r
+#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)\r
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \\r
+ ((SEL) == RTC_ShiftAdd1S_Set))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value\r
+ * @{\r
+ */ \r
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTC_Backup_Registers_Definitions \r
+ * @{\r
+ */\r
+\r
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)\r
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)\r
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)\r
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)\r
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)\r
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)\r
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)\r
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)\r
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)\r
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)\r
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)\r
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)\r
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)\r
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)\r
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)\r
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)\r
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)\r
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)\r
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)\r
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)\r
+#define RTC_BKP_DR20 ((uint32_t)0x00000014)\r
+#define RTC_BKP_DR21 ((uint32_t)0x00000015)\r
+#define RTC_BKP_DR22 ((uint32_t)0x00000016)\r
+#define RTC_BKP_DR23 ((uint32_t)0x00000017)\r
+#define RTC_BKP_DR24 ((uint32_t)0x00000018)\r
+#define RTC_BKP_DR25 ((uint32_t)0x00000019)\r
+#define RTC_BKP_DR26 ((uint32_t)0x0000001A)\r
+#define RTC_BKP_DR27 ((uint32_t)0x0000001B)\r
+#define RTC_BKP_DR28 ((uint32_t)0x0000001C)\r
+#define RTC_BKP_DR29 ((uint32_t)0x0000001D)\r
+#define RTC_BKP_DR30 ((uint32_t)0x0000001E)\r
+#define RTC_BKP_DR31 ((uint32_t)0x0000001F)\r
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \\r
+ ((BKP) == RTC_BKP_DR1) || \\r
+ ((BKP) == RTC_BKP_DR2) || \\r
+ ((BKP) == RTC_BKP_DR3) || \\r
+ ((BKP) == RTC_BKP_DR4) || \\r
+ ((BKP) == RTC_BKP_DR5) || \\r
+ ((BKP) == RTC_BKP_DR6) || \\r
+ ((BKP) == RTC_BKP_DR7) || \\r
+ ((BKP) == RTC_BKP_DR8) || \\r
+ ((BKP) == RTC_BKP_DR9) || \\r
+ ((BKP) == RTC_BKP_DR10) || \\r
+ ((BKP) == RTC_BKP_DR11) || \\r
+ ((BKP) == RTC_BKP_DR12) || \\r
+ ((BKP) == RTC_BKP_DR13) || \\r
+ ((BKP) == RTC_BKP_DR14) || \\r
+ ((BKP) == RTC_BKP_DR15) || \\r
+ ((BKP) == RTC_BKP_DR16) || \\r
+ ((BKP) == RTC_BKP_DR17) || \\r
+ ((BKP) == RTC_BKP_DR18) || \\r
+ ((BKP) == RTC_BKP_DR19) || \\r
+ ((BKP) == RTC_BKP_DR20) || \\r
+ ((BKP) == RTC_BKP_DR21) || \\r
+ ((BKP) == RTC_BKP_DR22) || \\r
+ ((BKP) == RTC_BKP_DR23) || \\r
+ ((BKP) == RTC_BKP_DR24) || \\r
+ ((BKP) == RTC_BKP_DR25) || \\r
+ ((BKP) == RTC_BKP_DR26) || \\r
+ ((BKP) == RTC_BKP_DR27) || \\r
+ ((BKP) == RTC_BKP_DR28) || \\r
+ ((BKP) == RTC_BKP_DR29) || \\r
+ ((BKP) == RTC_BKP_DR30) || \\r
+ ((BKP) == RTC_BKP_DR31))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Input_parameter_format_definitions \r
+ * @{\r
+ */ \r
+#define RTC_Format_BIN ((uint32_t)0x000000000)\r
+#define RTC_Format_BCD ((uint32_t)0x000000001)\r
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Flags_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)\r
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)\r
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)\r
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)\r
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)\r
+#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)\r
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)\r
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)\r
+#define RTC_FLAG_SHPF ((uint32_t)0x00000008)\r
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)\r
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \\r
+ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \\r
+ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \\r
+ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \\r
+ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \\r
+ ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \\r
+ ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \\r
+ ((FLAG) == RTC_FLAG_SHPF))\r
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Interrupts_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_IT_TS ((uint32_t)0x00008000)\r
+#define RTC_IT_WUT ((uint32_t)0x00004000)\r
+#define RTC_IT_ALRB ((uint32_t)0x00002000)\r
+#define RTC_IT_ALRA ((uint32_t)0x00001000)\r
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */\r
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)\r
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)\r
+#define RTC_IT_TAMP3 ((uint32_t)0x00080000)\r
+\r
+\r
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))\r
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \\r
+ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \\r
+ ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \\r
+ ((IT) == RTC_IT_TAMP3))\r
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Legacy \r
+ * @{\r
+ */ \r
+#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig\r
+#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the RTC configuration to the default reset state *****/ \r
+ErrorStatus RTC_DeInit(void);\r
+\r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_WriteProtectionCmd(FunctionalState NewState);\r
+ErrorStatus RTC_EnterInitMode(void);\r
+void RTC_ExitInitMode(void);\r
+ErrorStatus RTC_WaitForSynchro(void);\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);\r
+void RTC_BypassShadowCmd(FunctionalState NewState);\r
+\r
+/* Time and Date configuration functions **************************************/ \r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+uint32_t RTC_GetSubSecond(void);\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+\r
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/ \r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);\r
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);\r
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);\r
+\r
+/* WakeUp Timer configuration functions ***************************************/ \r
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);\r
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);\r
+uint32_t RTC_GetWakeUpCounter(void);\r
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);\r
+\r
+/* Daylight Saving configuration functions ************************************/ \r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);\r
+uint32_t RTC_GetStoreOperation(void);\r
+\r
+/* Output pin Configuration function ******************************************/ \r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);\r
+\r
+/* Coarse and Smooth Calibration configuration functions **********************/\r
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);\r
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);\r
+void RTC_CalibOutputCmd(FunctionalState NewState);\r
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);\r
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, \r
+ uint32_t RTC_SmoothCalibPlusPulses,\r
+ uint32_t RTC_SmouthCalibMinusPulsesValue);\r
+\r
+/* TimeStamp configuration functions ******************************************/ \r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
+ RTC_DateTypeDef* RTC_StampDateStruct);\r
+uint32_t RTC_GetTimeStampSubSecond(void);\r
+\r
+/* Tampers configuration functions ********************************************/ \r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);\r
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);\r
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);\r
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);\r
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);\r
+void RTC_TamperPullUpCmd(FunctionalState NewState);\r
+\r
+/* Backup Data Registers configuration functions ******************************/ \r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);\r
+\r
+/* Output Type Config configuration functions *********************************/ \r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);\r
+\r
+/* RTC_Shift_control_synchonisation_functions *********************************/\r
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);\r
+\r
+/* Interrupts and flags management functions **********************************/ \r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);\r
+void RTC_ClearFlag(uint32_t RTC_FLAG);\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_RTC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_sdio.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the SDIO firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SDIO_H\r
+#define __STM32L1xx_SDIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SDIO\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref SDIO_Clock_Edge */\r
+\r
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is\r
+ enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Clock_Bypass */\r
+\r
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or\r
+ disabled when the bus is idle.\r
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */\r
+\r
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.\r
+ This parameter can be a value of @ref SDIO_Bus_Wide */\r
+\r
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */\r
+\r
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.\r
+ This parameter can be a value between 0x00 and 0xFF. */\r
+\r
+} SDIO_InitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent\r
+ to a card as part of a command message. If a command\r
+ contains an argument, it must be loaded into this register\r
+ before writing the command to the command register */\r
+\r
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */\r
+\r
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.\r
+ This parameter can be a value of @ref SDIO_Response_Type */\r
+\r
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */\r
+\r
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_CPSM_State */\r
+} SDIO_CmdInitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r
+\r
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */\r
+ \r
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.\r
+ This parameter can be a value of @ref SDIO_Data_Block_Size */\r
+ \r
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r
+ is a read or write.\r
+ This parameter can be a value of @ref SDIO_Transfer_Direction */\r
+ \r
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r
+ This parameter can be a value of @ref SDIO_Transfer_Type */\r
+ \r
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_DPSM_State */\r
+} SDIO_DataInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SDIO_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Edge \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
+ ((EDGE) == SDIO_ClockEdge_Falling))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Bypass \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
+ ((BYPASS) == SDIO_ClockBypass_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Clock_Power_Save \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
+ ((SAVE) == SDIO_ClockPowerSave_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Bus_Wide \r
+ * @{\r
+ */\r
+\r
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
+ ((WIDE) == SDIO_BusWide_8b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Hardware_Flow_Control \r
+ * @{\r
+ */\r
+\r
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Power_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SDIO_Interrupt_soucres \r
+ * @{\r
+ */\r
+\r
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Command_Index\r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Response_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_Response_No ((uint32_t)0x00000000)\r
+#define SDIO_Response_Short ((uint32_t)0x00000040)\r
+#define SDIO_Response_Long ((uint32_t)0x000000C0)\r
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
+ ((RESPONSE) == SDIO_Response_Short) || \\r
+ ((RESPONSE) == SDIO_Response_Long))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Wait_Interrupt_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */\r
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */\r
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */\r
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
+ ((WAIT) == SDIO_Wait_Pend))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_CPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Response_Registers \r
+ * @{\r
+ */\r
+\r
+#define SDIO_RESP1 ((uint32_t)0x00000000)\r
+#define SDIO_RESP2 ((uint32_t)0x00000004)\r
+#define SDIO_RESP3 ((uint32_t)0x00000008)\r
+#define SDIO_RESP4 ((uint32_t)0x0000000C)\r
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Length \r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Block_Size \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_32b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_64b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_128b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_256b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_512b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16384b)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Direction \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
+ ((DIR) == SDIO_TransferDir_ToSDIO))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
+ ((MODE) == SDIO_TransferMode_Block))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_DPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Flags \r
+ * @{\r
+ */\r
+\r
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
+ ((FLAG) == SDIO_FLAG_CMDREND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
+ ((FLAG) == SDIO_FLAG_DATAEND) || \\r
+ ((FLAG) == SDIO_FLAG_STBITERR) || \\r
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXACT) || \\r
+ ((FLAG) == SDIO_FLAG_RXACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
+ ((FLAG) == SDIO_FLAG_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r
+\r
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
+ ((IT) == SDIO_IT_DCRCFAIL) || \\r
+ ((IT) == SDIO_IT_CTIMEOUT) || \\r
+ ((IT) == SDIO_IT_DTIMEOUT) || \\r
+ ((IT) == SDIO_IT_TXUNDERR) || \\r
+ ((IT) == SDIO_IT_RXOVERR) || \\r
+ ((IT) == SDIO_IT_CMDREND) || \\r
+ ((IT) == SDIO_IT_CMDSENT) || \\r
+ ((IT) == SDIO_IT_DATAEND) || \\r
+ ((IT) == SDIO_IT_STBITERR) || \\r
+ ((IT) == SDIO_IT_DBCKEND) || \\r
+ ((IT) == SDIO_IT_CMDACT) || \\r
+ ((IT) == SDIO_IT_TXACT) || \\r
+ ((IT) == SDIO_IT_RXACT) || \\r
+ ((IT) == SDIO_IT_TXFIFOHE) || \\r
+ ((IT) == SDIO_IT_RXFIFOHF) || \\r
+ ((IT) == SDIO_IT_TXFIFOF) || \\r
+ ((IT) == SDIO_IT_RXFIFOF) || \\r
+ ((IT) == SDIO_IT_TXFIFOE) || \\r
+ ((IT) == SDIO_IT_RXFIFOE) || \\r
+ ((IT) == SDIO_IT_TXDAVL) || \\r
+ ((IT) == SDIO_IT_RXDAVL) || \\r
+ ((IT) == SDIO_IT_SDIOIT) || \\r
+ ((IT) == SDIO_IT_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Read_Wait_Mode \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)\r
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)\r
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
+ ((MODE) == SDIO_ReadWaitMode_DATA2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+/* Function used to set the SDIO configuration to the default reset state ****/\r
+void SDIO_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_ClockCmd(FunctionalState NewState);\r
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);\r
+uint32_t SDIO_GetPowerState(void);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void SDIO_DMACmd(FunctionalState NewState);\r
+\r
+/* Command path state machine (CPSM) management functions *********************/\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
+uint8_t SDIO_GetCommandResponse(void);\r
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r
+\r
+/* Data path state machine (DPSM) management functions ************************/\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+uint32_t SDIO_GetDataCounter(void);\r
+uint32_t SDIO_ReadData(void);\r
+void SDIO_WriteData(uint32_t Data);\r
+uint32_t SDIO_GetFIFOCount(void);\r
+\r
+/* SDIO IO Cards mode management functions ************************************/\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r
+void SDIO_SetSDIOOperation(FunctionalState NewState);\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
+\r
+/* CE-ATA mode management functions *******************************************/\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
+void SDIO_CEATAITCmd(FunctionalState NewState);\r
+void SDIO_SendCEATACmd(FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);\r
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_SDIO_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_spi.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the SPI \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SPI_H\r
+#define __STM32L1xx_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief SPI Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
+ This parameter can be a value of @ref SPI_data_direction */\r
+\r
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
+ This parameter can be a value of @ref SPI_mode */\r
+\r
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be a value of @ref SPI_data_size */\r
+\r
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
+ This parameter can be a value of @ref SPI_Clock_Polarity */\r
+\r
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be a value of @ref SPI_Clock_Phase */\r
+\r
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be a value of @ref SPI_Slave_Select_management */\r
+ \r
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
+}SPI_InitTypeDef;\r
+\r
+/** \r
+ * @brief I2S Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r
+ This parameter can be a value of @ref SPI_I2S_Mode */\r
+\r
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r
+ This parameter can be a value of @ref SPI_I2S_Standard */\r
+\r
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r
+ This parameter can be a value of @ref SPI_I2S_Data_Format */\r
+\r
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
+ This parameter can be a value of @ref SPI_I2S_MCLK_Output */\r
+\r
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
+ This parameter can be a value of @ref SPI_I2S_Audio_Frequency */\r
+\r
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r
+ This parameter can be a value of @ref SPI_I2S_Clock_Polarity */\r
+}I2S_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
+ ((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3))\r
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3))\r
+\r
+/** @defgroup SPI_data_direction \r
+ * @{\r
+ */\r
+ \r
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+ ((MODE) == SPI_Direction_1Line_Rx) || \\r
+ ((MODE) == SPI_Direction_1Line_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_mode \r
+ * @{\r
+ */\r
+\r
+#define SPI_Mode_Master ((uint16_t)0x0104)\r
+#define SPI_Mode_Slave ((uint16_t)0x0000)\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+ ((MODE) == SPI_Mode_Slave))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_data_size \r
+ * @{\r
+ */\r
+\r
+#define SPI_DataSize_16b ((uint16_t)0x0800)\r
+#define SPI_DataSize_8b ((uint16_t)0x0000)\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
+ ((DATASIZE) == SPI_DataSize_8b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPOL_Low ((uint16_t)0x0000)\r
+#define SPI_CPOL_High ((uint16_t)0x0002)\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+ ((CPOL) == SPI_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+ ((CPHA) == SPI_CPHA_2Edge))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSS_Soft ((uint16_t)0x0200)\r
+#define SPI_NSS_Hard ((uint16_t)0x0000)\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+ ((NSS) == SPI_NSS_Hard))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_BaudRate_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_MSB_LSB_transmission \r
+ * @{\r
+ */\r
+\r
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+ ((BIT) == SPI_FirstBit_LSB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Mode \r
+ * @{\r
+ */\r
+\r
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
+ ((MODE) == I2S_Mode_SlaveRx) || \\r
+ ((MODE) == I2S_Mode_MasterTx)|| \\r
+ ((MODE) == I2S_Mode_MasterRx))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup SPI_I2S_Standard \r
+ * @{\r
+ */\r
+\r
+#define I2S_Standard_Phillips ((uint16_t)0x0000)\r
+#define I2S_Standard_MSB ((uint16_t)0x0010)\r
+#define I2S_Standard_LSB ((uint16_t)0x0020)\r
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
+ ((STANDARD) == I2S_Standard_MSB) || \\r
+ ((STANDARD) == I2S_Standard_LSB) || \\r
+ ((STANDARD) == I2S_Standard_PCMShort) || \\r
+ ((STANDARD) == I2S_Standard_PCMLong))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPI_I2S_Data_Format \r
+ * @{\r
+ */\r
+\r
+#define I2S_DataFormat_16b ((uint16_t)0x0000)\r
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r
+#define I2S_DataFormat_24b ((uint16_t)0x0003)\r
+#define I2S_DataFormat_32b ((uint16_t)0x0005)\r
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
+ ((FORMAT) == I2S_DataFormat_16bextended) || \\r
+ ((FORMAT) == I2S_DataFormat_24b) || \\r
+ ((FORMAT) == I2S_DataFormat_32b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_MCLK_Output \r
+ * @{\r
+ */\r
+\r
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)\r
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
+ ((OUTPUT) == I2S_MCLKOutput_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Audio_Frequency \r
+ * @{\r
+ */\r
+\r
+#define I2S_AudioFreq_192k ((uint32_t)192000)\r
+#define I2S_AudioFreq_96k ((uint32_t)96000)\r
+#define I2S_AudioFreq_48k ((uint32_t)48000)\r
+#define I2S_AudioFreq_44k ((uint32_t)44100)\r
+#define I2S_AudioFreq_32k ((uint32_t)32000)\r
+#define I2S_AudioFreq_22k ((uint32_t)22050)\r
+#define I2S_AudioFreq_16k ((uint32_t)16000)\r
+#define I2S_AudioFreq_11k ((uint32_t)11025)\r
+#define I2S_AudioFreq_8k ((uint32_t)8000)\r
+#define I2S_AudioFreq_Default ((uint32_t)2)\r
+\r
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \\r
+ ((FREQ) <= I2S_AudioFreq_192k)) || \\r
+ ((FREQ) == I2S_AudioFreq_Default))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPI_I2S_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define I2S_CPOL_Low ((uint16_t)0x0000)\r
+#define I2S_CPOL_High ((uint16_t)0x0008)\r
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
+ ((CPOL) == I2S_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_DMA_transfer_requests \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_NSS_internal_software_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Transmit_Receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_CRC_Tx ((uint8_t)0x00)\r
+#define SPI_CRC_Rx ((uint8_t)0x01)\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_direction_transmit_receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
+#define SPI_Direction_Tx ((uint16_t)0x4000)\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+ ((DIRECTION) == SPI_Direction_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
+#define I2S_IT_UDR ((uint8_t)0x53)\r
+#define SPI_I2S_IT_FRE ((uint8_t)0x58)\r
+\r
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_RXNE) || \\r
+ ((IT) == SPI_I2S_IT_ERR))\r
+\r
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
+#define SPI_IT_MODF ((uint8_t)0x55)\r
+#define SPI_IT_CRCERR ((uint8_t)0x54)\r
+\r
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
+\r
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \\r
+ ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\\r
+ ((IT) == SPI_I2S_IT_FRE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)\r
+#define I2S_FLAG_UDR ((uint16_t)0x0008)\r
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
+#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
+#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)\r
+\r
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\r
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \\r
+ ((FLAG) == SPI_I2S_FLAG_FRE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_polynomial \r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Legacy \r
+ * @{\r
+ */\r
+\r
+#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx\r
+#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx\r
+#define SPI_IT_TXE SPI_I2S_IT_TXE\r
+#define SPI_IT_RXNE SPI_I2S_IT_RXNE\r
+#define SPI_IT_ERR SPI_I2S_IT_ERR\r
+#define SPI_IT_OVR SPI_I2S_IT_OVR\r
+#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE\r
+#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE\r
+#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR\r
+#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY\r
+#define SPI_DeInit SPI_I2S_DeInit\r
+#define SPI_ITConfig SPI_I2S_ITConfig\r
+#define SPI_DMACmd SPI_I2S_DMACmd\r
+#define SPI_SendData SPI_I2S_SendData\r
+#define SPI_ReceiveData SPI_I2S_ReceiveData\r
+#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus\r
+#define SPI_ClearFlag SPI_I2S_ClearFlag\r
+#define SPI_GetITStatus SPI_I2S_GetITStatus\r
+#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the SPI configuration to the default reset state *****/ \r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
+\r
+/* Hardware CRC Calculation functions *****************************************/\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SPI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_syscfg.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the SYSCFG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/*!< Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SYSCFG_H\r
+#define __STM32L1xx_SYSCFG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*!< Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SYSCFG\r
+ * @{\r
+ */ \r
+ \r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup EXTI_Port_Sources \r
+ * @{\r
+ */ \r
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)\r
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)\r
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)\r
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03)\r
+#define EXTI_PortSourceGPIOE ((uint8_t)0x04)\r
+#define EXTI_PortSourceGPIOH ((uint8_t)0x05)\r
+#define EXTI_PortSourceGPIOF ((uint8_t)0x06)\r
+#define EXTI_PortSourceGPIOG ((uint8_t)0x07)\r
+ \r
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOH)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Pin_sources \r
+ * @{\r
+ */ \r
+#define EXTI_PinSource0 ((uint8_t)0x00)\r
+#define EXTI_PinSource1 ((uint8_t)0x01)\r
+#define EXTI_PinSource2 ((uint8_t)0x02)\r
+#define EXTI_PinSource3 ((uint8_t)0x03)\r
+#define EXTI_PinSource4 ((uint8_t)0x04)\r
+#define EXTI_PinSource5 ((uint8_t)0x05)\r
+#define EXTI_PinSource6 ((uint8_t)0x06)\r
+#define EXTI_PinSource7 ((uint8_t)0x07)\r
+#define EXTI_PinSource8 ((uint8_t)0x08)\r
+#define EXTI_PinSource9 ((uint8_t)0x09)\r
+#define EXTI_PinSource10 ((uint8_t)0x0A)\r
+#define EXTI_PinSource11 ((uint8_t)0x0B)\r
+#define EXTI_PinSource12 ((uint8_t)0x0C)\r
+#define EXTI_PinSource13 ((uint8_t)0x0D)\r
+#define EXTI_PinSource14 ((uint8_t)0x0E)\r
+#define EXTI_PinSource15 ((uint8_t)0x0F)\r
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
+ ((PINSOURCE) == EXTI_PinSource1) || \\r
+ ((PINSOURCE) == EXTI_PinSource2) || \\r
+ ((PINSOURCE) == EXTI_PinSource3) || \\r
+ ((PINSOURCE) == EXTI_PinSource4) || \\r
+ ((PINSOURCE) == EXTI_PinSource5) || \\r
+ ((PINSOURCE) == EXTI_PinSource6) || \\r
+ ((PINSOURCE) == EXTI_PinSource7) || \\r
+ ((PINSOURCE) == EXTI_PinSource8) || \\r
+ ((PINSOURCE) == EXTI_PinSource9) || \\r
+ ((PINSOURCE) == EXTI_PinSource10) || \\r
+ ((PINSOURCE) == EXTI_PinSource11) || \\r
+ ((PINSOURCE) == EXTI_PinSource12) || \\r
+ ((PINSOURCE) == EXTI_PinSource13) || \\r
+ ((PINSOURCE) == EXTI_PinSource14) || \\r
+ ((PINSOURCE) == EXTI_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Memory_Remap_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)\r
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r
+#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)\r
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)\r
+ \r
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_FSMC) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RI_Resistor\r
+ * @{\r
+ */\r
+\r
+#define RI_Resistor_10KPU COMP_CSR_10KPU\r
+#define RI_Resistor_400KPU COMP_CSR_400KPU\r
+#define RI_Resistor_10KPD COMP_CSR_10KPD\r
+#define RI_Resistor_400KPD COMP_CSR_400KPD\r
+\r
+#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \\r
+ ((RESISTOR) == COMP_CSR_400KPU) || \\r
+ ((RESISTOR) == COMP_CSR_10KPD) || \\r
+ ((RESISTOR) == COMP_CSR_400KPD))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_Channel\r
+ * @{\r
+ */\r
+\r
+#define RI_Channel_3 ((uint32_t)0x04000000)\r
+#define RI_Channel_8 ((uint32_t)0x08000000)\r
+#define RI_Channel_13 ((uint32_t)0x10000000)\r
+\r
+#define IS_RI_CHANNEL(CHANNEL) (((CHANNEL) == RI_Channel_3) || \\r
+ ((CHANNEL) == RI_Channel_8) || \\r
+ ((CHANNEL) == RI_Channel_13))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_ChannelSpeed\r
+ * @{\r
+ */\r
+\r
+#define RI_ChannelSpeed_Fast ((uint32_t)0x00000000)\r
+#define RI_ChannelSpeed_Slow ((uint32_t)0x00000001)\r
+\r
+#define IS_RI_CHANNELSPEED(SPEED) (((SPEED) == RI_ChannelSpeed_Fast) || \\r
+ ((SPEED) == RI_ChannelSpeed_Slow))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_InputCapture\r
+ * @{\r
+ */ \r
+ \r
+#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */\r
+#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */\r
+#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */\r
+#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */\r
+\r
+#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Select\r
+ * @{\r
+ */ \r
+ \r
+#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */\r
+#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */\r
+#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */\r
+#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */\r
+\r
+#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \\r
+ ((TIM) == TIM_Select_TIM2) || \\r
+ ((TIM) == TIM_Select_TIM3) || \\r
+ ((TIM) == TIM_Select_TIM4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RI_InputCaptureRouting\r
+ * @{\r
+ */ \r
+ /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ \r
+#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */\r
+#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */\r
+#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */\r
+#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */\r
+#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */\r
+#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */\r
+#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */\r
+#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */\r
+#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */\r
+#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */\r
+#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */\r
+#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */\r
+#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */\r
+#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */\r
+#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */\r
+#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */\r
+\r
+#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_1) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_2) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_3) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_4) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_5) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_6) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_7) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_8) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_9) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_10) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_11) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_12) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_13) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_14) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_15))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_IOSwitch\r
+ * @{\r
+ */ \r
+ \r
+/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */\r
+#define RI_IOSwitch_CH0 ((uint32_t)0x80000001)\r
+#define RI_IOSwitch_CH1 ((uint32_t)0x80000002)\r
+#define RI_IOSwitch_CH2 ((uint32_t)0x80000004)\r
+#define RI_IOSwitch_CH3 ((uint32_t)0x80000008)\r
+#define RI_IOSwitch_CH4 ((uint32_t)0x80000010)\r
+#define RI_IOSwitch_CH5 ((uint32_t)0x80000020)\r
+#define RI_IOSwitch_CH6 ((uint32_t)0x80000040)\r
+#define RI_IOSwitch_CH7 ((uint32_t)0x80000080)\r
+#define RI_IOSwitch_CH8 ((uint32_t)0x80000100)\r
+#define RI_IOSwitch_CH9 ((uint32_t)0x80000200)\r
+#define RI_IOSwitch_CH10 ((uint32_t)0x80000400)\r
+#define RI_IOSwitch_CH11 ((uint32_t)0x80000800)\r
+#define RI_IOSwitch_CH12 ((uint32_t)0x80001000)\r
+#define RI_IOSwitch_CH13 ((uint32_t)0x80002000)\r
+#define RI_IOSwitch_CH14 ((uint32_t)0x80004000)\r
+#define RI_IOSwitch_CH15 ((uint32_t)0x80008000)\r
+#define RI_IOSwitch_CH31 ((uint32_t)0x80010000)\r
+#define RI_IOSwitch_CH18 ((uint32_t)0x80040000)\r
+#define RI_IOSwitch_CH19 ((uint32_t)0x80080000)\r
+#define RI_IOSwitch_CH20 ((uint32_t)0x80100000)\r
+#define RI_IOSwitch_CH21 ((uint32_t)0x80200000)\r
+#define RI_IOSwitch_CH22 ((uint32_t)0x80400000)\r
+#define RI_IOSwitch_CH23 ((uint32_t)0x80800000)\r
+#define RI_IOSwitch_CH24 ((uint32_t)0x81000000)\r
+#define RI_IOSwitch_CH25 ((uint32_t)0x82000000)\r
+#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect \r
+ selected channel to COMP1 non inverting input */\r
+#define RI_IOSwitch_CH27 ((uint32_t)0x88000000)\r
+#define RI_IOSwitch_CH28 ((uint32_t)0x90000000)\r
+#define RI_IOSwitch_CH29 ((uint32_t)0xA0000000)\r
+#define RI_IOSwitch_CH30 ((uint32_t)0xC0000000)\r
+\r
+/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ \r
+#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)\r
+#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)\r
+#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)\r
+#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)\r
+#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)\r
+#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)\r
+#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)\r
+#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)\r
+#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)\r
+#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)\r
+#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)\r
+#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)\r
+#define RI_IOSwitch_GR4_4 ((uint32_t)0x00008000)\r
+#define RI_IOSwitch_CH0b ((uint32_t)0x00010000)\r
+#define RI_IOSwitch_CH1b ((uint32_t)0x00020000)\r
+#define RI_IOSwitch_CH2b ((uint32_t)0x00040000)\r
+#define RI_IOSwitch_CH3b ((uint32_t)0x00080000)\r
+#define RI_IOSwitch_CH6b ((uint32_t)0x00100000)\r
+#define RI_IOSwitch_CH7b ((uint32_t)0x00200000)\r
+#define RI_IOSwitch_CH8b ((uint32_t)0x00400000)\r
+#define RI_IOSwitch_CH9b ((uint32_t)0x00800000)\r
+#define RI_IOSwitch_CH10b ((uint32_t)0x01000000)\r
+#define RI_IOSwitch_CH11b ((uint32_t)0x02000000)\r
+#define RI_IOSwitch_CH12b ((uint32_t)0x04000000)\r
+#define RI_IOSwitch_GR6_3 ((uint32_t)0x08000000)\r
+#define RI_IOSwitch_GR6_4 ((uint32_t)0x10000000)\r
+#define RI_IOSwitch_GR5_4 ((uint32_t)0x20000000)\r
+\r
+\r
+#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH5) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH6) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH7) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH8) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH9) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH10) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH11) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH12) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH13) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH14) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH15) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH18) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH19) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH20) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH21) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH22) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH23) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH24) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH25) || \\r
+ ((IOSWITCH) == RI_IOSwitch_VCOMP) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH27) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH28) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH29) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH30) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH31) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH0b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH1b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH2b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH3b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH6b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH7b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH8b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH9b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH10b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH11b) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH12b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Port\r
+ * @{\r
+ */\r
+\r
+#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */\r
+#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */\r
+#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */\r
+#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */\r
+#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */\r
+#define RI_PortF ((uint8_t)0x06) /*!< GPIOF selected */\r
+#define RI_PortG ((uint8_t)0x07) /*!< GPIOG selected */\r
+\r
+#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \\r
+ ((PORT) == RI_PortB) || \\r
+ ((PORT) == RI_PortC) || \\r
+ ((PORT) == RI_PortD) || \\r
+ ((PORT) == RI_PortE) || \\r
+ ((PORT) == RI_PortF) || \\r
+ ((PORT) == RI_PortG))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Pin define \r
+ * @{\r
+ */\r
+#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the SYSCFG and RI configuration to the default reset state **/\r
+void SYSCFG_DeInit(void);\r
+void SYSCFG_RIDeInit(void);\r
+\r
+/* SYSCFG Initialization and Configuration functions **************************/ \r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r
+uint32_t SYSCFG_GetBootMode(void);\r
+void SYSCFG_USBPuCmd(FunctionalState NewState);\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
+\r
+/* RI Initialization and Configuration functions ******************************/ \r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select);\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);\r
+void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed);\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SYSCFG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_tim.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the TIM firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_TIM_H\r
+#define __STM32L1xx_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief TIM Time Base Init structure definition\r
+ * @note This structure is used with all TIMx except for TIM6 and TIM7. \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter must be a number between 0x0000 and 0xFFFF. */ \r
+\r
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+} TIM_TimeBaseInitTypeDef; \r
+\r
+/** \r
+ * @brief TIM Output Compare Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_state */\r
+\r
+ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
+ This parameter can be a value of @ref TIM_Channel */\r
+\r
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint16_t TIM_ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+ \r
+/** @defgroup TIM_Exported_constants \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11))\r
+\r
+/* LIST1: TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11 */\r
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11))\r
+\r
+/* LIST3: TIM2, TIM3, TIM4 and TIM5 */\r
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5))\r
+\r
+/* LIST2: TIM2, TIM3, TIM4, TIM5 and TIM9 */\r
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM9))\r
+\r
+/* LIST5: TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM9 */\r
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) ||\\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) ||\\r
+ ((PERIPH) == TIM9))\r
+\r
+/* LIST4: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 */\r
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) ||\\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7))\r
+\r
+/* LIST6: TIM2, TIM3, TIM9, TIM10 and TIM11 */\r
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11))\r
+\r
+\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_OPMode_Single ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Channel \r
+ * @{\r
+ */\r
+\r
+#define TIM_Channel_1 ((uint16_t)0x0000)\r
+#define TIM_Channel_2 ((uint16_t)0x0004)\r
+#define TIM_Channel_3 ((uint16_t)0x0008)\r
+#define TIM_Channel_4 ((uint16_t)0x000C)\r
+\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+ \r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+ * @{\r
+ */\r
+\r
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup TIM_Output_Compare_state\r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Capture_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCx_Enable ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
+ ((POLARITY) == TIM_ICPolarity_BothEdge))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_IT_Update ((uint16_t)0x0001)\r
+#define TIM_IT_CC1 ((uint16_t)0x0002)\r
+#define TIM_IT_CC2 ((uint16_t)0x0004)\r
+#define TIM_IT_CC3 ((uint16_t)0x0008)\r
+#define TIM_IT_CC4 ((uint16_t)0x0010)\r
+#define TIM_IT_Trigger ((uint16_t)0x0040)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_Trigger))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
+#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
+#define TIM_DMABase_OR ((uint16_t)0x0013)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_DCR) || \\r
+ ((BASE) == TIM_DMABase_OR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMA_Update ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
+#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+ * @{\r
+ */ \r
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+ * @{\r
+ */\r
+\r
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_EventSource_Update ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000)) \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Preload_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Fast_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Clear_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Flags \r
+ * @{\r
+ */\r
+\r
+#define TIM_FLAG_Update ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OCReferenceClear \r
+ * @{\r
+ */\r
+#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)\r
+#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)\r
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \\r
+ ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Remap \r
+ * @{\r
+ */\r
+\r
+#define TIM2_TIM10_OC ((uint32_t)0xFFFE0000)\r
+#define TIM2_TIM5_TRGO ((uint32_t)0xFFFE0001)\r
+\r
+#define TIM3_TIM11_OC ((uint32_t)0xFFFE0000)\r
+#define TIM3_TIM5_TRGO ((uint32_t)0xFFFE0001)\r
+\r
+#define TIM9_GPIO ((uint32_t)0xFFFC0000)\r
+#define TIM9_LSE ((uint32_t)0xFFFC0001)\r
+\r
+#define TIM9_TIM3_TRGO ((uint32_t)0xFFFB0000)\r
+#define TIM9_TS_IO ((uint32_t)0xFFFB0004)\r
+\r
+#define TIM10_GPIO ((uint32_t)0xFFF40000)\r
+#define TIM10_LSI ((uint32_t)0xFFF40001)\r
+#define TIM10_LSE ((uint32_t)0xFFF40002)\r
+#define TIM10_RTC ((uint32_t)0xFFF40003)\r
+#define TIM10_RI ((uint32_t)0xFFF40008)\r
+\r
+#define TIM10_ETR_LSE ((uint32_t)0xFFFB0000)\r
+#define TIM10_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)\r
+\r
+#define TIM11_GPIO ((uint32_t)0xFFF40000)\r
+#define TIM11_MSI ((uint32_t)0xFFF40001)\r
+#define TIM11_HSE_RTC ((uint32_t)0xFFF40002)\r
+#define TIM11_RI ((uint32_t)0xFFF40008)\r
+\r
+#define TIM11_ETR_LSE ((uint32_t)0xFFFB0000)\r
+#define TIM11_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)\r
+\r
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM10_OC)|| \\r
+ ((TIM_REMAP) == TIM2_TIM5_TRGO)|| \\r
+ ((TIM_REMAP) == TIM3_TIM11_OC)|| \\r
+ ((TIM_REMAP) == TIM3_TIM5_TRGO)|| \\r
+ ((TIM_REMAP) == TIM9_GPIO)|| \\r
+ ((TIM_REMAP) == TIM9_LSE)|| \\r
+ ((TIM_REMAP) == TIM9_TIM3_TRGO)|| \\r
+ ((TIM_REMAP) == TIM9_TS_IO)|| \\r
+ ((TIM_REMAP) == TIM10_GPIO)|| \\r
+ ((TIM_REMAP) == TIM10_LSI)|| \\r
+ ((TIM_REMAP) == TIM10_LSE)|| \\r
+ ((TIM_REMAP) == TIM10_RTC)|| \\r
+ ((TIM_REMAP) == TIM10_RI)|| \\r
+ ((TIM_REMAP) == TIM10_ETR_LSE)|| \\r
+ ((TIM_REMAP) == TIM10_ETR_TIM9_TRGO)|| \\r
+ ((TIM_REMAP) == TIM11_GPIO)|| \\r
+ ((TIM_REMAP) == TIM11_MSI)|| \\r
+ ((TIM_REMAP) == TIM11_HSE_RTC)|| \\r
+ ((TIM_REMAP) == TIM11_RI)|| \\r
+ ((TIM_REMAP) == TIM11_ETR_LSE)|| \\r
+ ((TIM_REMAP) == TIM11_ETR_TIM9_TRGO))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Legacy \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer\r
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers\r
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers\r
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers\r
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers\r
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers\r
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers\r
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers\r
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers\r
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers\r
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers\r
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers\r
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers\r
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers\r
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers\r
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers\r
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers\r
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* TimeBase management ********************************************************/\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Output Compare management **************************************************/\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+\r
+/* Input Capture management ***************************************************/\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+\r
+/* Interrupts, DMA and flags management ***************************************/\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Clocks management **********************************************************/\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+\r
+\r
+/* Synchronization management *************************************************/\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+\r
+/* Specific interface management **********************************************/ \r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Specific remapping management **********************************************/\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_TIM_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_usart.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the USART \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_USART_H\r
+#define __STM32L1xx_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** \r
+ * @brief USART Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))\r
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 \r
+ Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */\r
+\r
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USART_Word_Length */\r
+\r
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+ uint16_t USART_Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+ \r
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode */\r
+\r
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
+} USART_InitTypeDef;\r
+\r
+/** \r
+ * @brief USART Clock Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+\r
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Clock */\r
+\r
+ uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit */\r
+} USART_ClockInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3) || \\r
+ ((PERIPH) == UART4) || \\r
+ ((PERIPH) == UART5))\r
+\r
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3))\r
+\r
+/** @defgroup USART_Word_Length \r
+ * @{\r
+ */ \r
+ \r
+#define USART_WordLength_8b ((uint16_t)0x0000)\r
+#define USART_WordLength_9b ((uint16_t)0x1000)\r
+ \r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+ ((LENGTH) == USART_WordLength_9b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Stop_Bits \r
+ * @{\r
+ */ \r
+ \r
+#define USART_StopBits_1 ((uint16_t)0x0000)\r
+#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
+#define USART_StopBits_2 ((uint16_t)0x2000)\r
+#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+ ((STOPBITS) == USART_StopBits_0_5) || \\r
+ ((STOPBITS) == USART_StopBits_2) || \\r
+ ((STOPBITS) == USART_StopBits_1_5))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Parity \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Parity_No ((uint16_t)0x0000)\r
+#define USART_Parity_Even ((uint16_t)0x0400)\r
+#define USART_Parity_Odd ((uint16_t)0x0600) \r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+ ((PARITY) == USART_Parity_Even) || \\r
+ ((PARITY) == USART_Parity_Odd))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Mode \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Mode_Rx ((uint16_t)0x0004)\r
+#define USART_Mode_Tx ((uint16_t)0x0008)\r
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Hardware_Flow_Control \r
+ * @{\r
+ */ \r
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock \r
+ * @{\r
+ */ \r
+#define USART_Clock_Disable ((uint16_t)0x0000)\r
+#define USART_Clock_Enable ((uint16_t)0x0800)\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+ ((CLOCK) == USART_Clock_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define USART_CPOL_Low ((uint16_t)0x0000)\r
+#define USART_CPOL_High ((uint16_t)0x0400)\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Phase\r
+ * @{\r
+ */\r
+\r
+#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
+#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit\r
+ * @{\r
+ */\r
+\r
+#define USART_LastBit_Disable ((uint16_t)0x0000)\r
+#define USART_LastBit_Enable ((uint16_t)0x0100)\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+ ((LASTBIT) == USART_LastBit_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Interrupt_definition \r
+ * @{\r
+ */\r
+ \r
+#define USART_IT_PE ((uint16_t)0x0028)\r
+#define USART_IT_TXE ((uint16_t)0x0727)\r
+#define USART_IT_TC ((uint16_t)0x0626)\r
+#define USART_IT_RXNE ((uint16_t)0x0525)\r
+#define USART_IT_IDLE ((uint16_t)0x0424)\r
+#define USART_IT_LBD ((uint16_t)0x0846)\r
+#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */\r
+#define USART_IT_CTS ((uint16_t)0x096A)\r
+#define USART_IT_ERR ((uint16_t)0x0060)\r
+#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */\r
+#define USART_IT_NE ((uint16_t)0x0260)\r
+#define USART_IT_FE ((uint16_t)0x0160)\r
+\r
+/** @defgroup USART_Legacy \r
+ * @{\r
+ */\r
+#define USART_IT_ORE USART_IT_ORE_ER \r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \\r
+ ((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \\r
+ ((IT) == USART_IT_FE))\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_DMA_Requests \r
+ * @{\r
+ */\r
+\r
+#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
+#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_WakeUp_methods\r
+ * @{\r
+ */\r
+\r
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+ ((WAKEUP) == USART_WakeUp_AddressMark))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_LIN_Break_Detection_Length \r
+ * @{\r
+ */\r
+ \r
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+ ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IrDA_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+ ((MODE) == USART_IrDAMode_Normal))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Flags \r
+ * @{\r
+ */\r
+\r
+#define USART_FLAG_CTS ((uint16_t)0x0200)\r
+#define USART_FLAG_LBD ((uint16_t)0x0100)\r
+#define USART_FLAG_TXE ((uint16_t)0x0080)\r
+#define USART_FLAG_TC ((uint16_t)0x0040)\r
+#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
+#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
+#define USART_FLAG_ORE ((uint16_t)0x0008)\r
+#define USART_FLAG_NE ((uint16_t)0x0004)\r
+#define USART_FLAG_FE ((uint16_t)0x0002)\r
+#define USART_FLAG_PE ((uint16_t)0x0001)\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
+ \r
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))\r
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the USART configuration to the default reset state ***/ \r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
+\r
+/* Multi-Processor Communication functions ************************************/\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* LIN mode functions *********************************************************/\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+\r
+/* Half-duplex mode function **************************************************/\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Smartcard mode functions ***************************************************/\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
+\r
+/* IrDA mode functions ********************************************************/\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_USART_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file contains all the functions prototypes for the WWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_WWDG_H\r
+#define __STM32L1xx_WWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup WWDG_Prescaler \r
+ * @{\r
+ */ \r
+ \r
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
+ ((PRESCALER) == WWDG_Prescaler_2) || \\r
+ ((PRESCALER) == WWDG_Prescaler_4) || \\r
+ ((PRESCALER) == WWDG_Prescaler_8))\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the WWDG configuration to the default reset state ****/ \r
+void WWDG_DeInit(void);\r
+\r
+/* Prescaler, Refresh window and Counter configuration functions **************/\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
+void WWDG_SetWindowValue(uint8_t WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(uint8_t Counter);\r
+\r
+/* WWDG activation functions **************************************************/\r
+void WWDG_Enable(uint8_t Counter);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_WWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides all the miscellaneous firmware functions (add-on\r
+ * to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC \r
+ * @brief MISC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Private_Functions\r
+ * @{\r
+ */\r
+/**\r
+ *\r
+@verbatim\r
+ *******************************************************************************\r
+ ##### Interrupts configuration functions #####\r
+ *******************************************************************************\r
+ [..] This section provide functions allowing to configure the NVIC interrupts \r
+ (IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.\r
+ (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() \r
+ function according to the following table.\r
+ The table below gives the allowed values of the preemption priority \r
+ and subpriority according to the Priority Grouping configuration \r
+ performed by NVIC_PriorityGroupConfig function.\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for preemption priority\r
+ | | | 4 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for preemption priority\r
+ | | | 3 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for preemption priority\r
+ | | | 2 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for preemption priority\r
+ | | | 1 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for preemption priority\r
+ | | | 0 bits for subpriority\r
+ ============================================================================================================================\r
+\r
+\r
+ (#) Enable and Configure the priority of the selected IRQ Channels. \r
+\r
+ -@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,\r
+ the IRQ priority will be managed only by subpriority.\r
+ The sub-priority is only used to sort pending exception priorities, \r
+ and does not affect active exceptions.\r
+ -@- Lower priority values gives higher priority.\r
+ -@- Priority Order:\r
+ (#@) Lowest Preemption priority.\r
+ (#@) Lowest Subpriority.\r
+ (#@) Lowest hardware priority (IRQn position).\r
+ \r
+@endverbatim\r
+*/\r
+\r
+/**\r
+ * @brief Configures the priority grouping: preemption priority and subpriority.\r
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PriorityGroup_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority.\r
+ * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested \r
+ * interrupt. This interrupts priority is managed only with subpriority. \r
+ * @arg NVIC_PriorityGroup_1: 1 bits for preemption priority.\r
+ * 3 bits for subpriority.\r
+ * @arg NVIC_PriorityGroup_2: 2 bits for preemption priority.\r
+ * 2 bits for subpriority.\r
+ * @arg NVIC_PriorityGroup_3: 3 bits for preemption priority.\r
+ * 1 bits for subpriority.\r
+ * @arg NVIC_PriorityGroup_4: 4 bits for preemption priority.\r
+ * 0 bits for subpriority.\r
+ * @retval None\r
+ */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the NVIC peripheral according to the specified\r
+ * parameters in the NVIC_InitStruct.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before.\r
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+ * the configuration information for the specified NVIC peripheral.\r
+ * @retval None\r
+ */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+\r
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);\r
+ tmppriority = tmppriority << 0x04;\r
+ \r
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the vector table location and Offset.\r
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.\r
+ * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.\r
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.\r
+ * @retval None\r
+ */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert_param(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+ * @brief Selects the condition for the system to enter low power mode.\r
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.\r
+ * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.\r
+ * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.\r
+ * @param NewState: new state of LP condition. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param SysTick_CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+ \r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_adc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral:\r
+ * + Initialization and Configuration\r
+ * + Power saving\r
+ * + Analog Watchdog configuration\r
+ * + Temperature Sensor & Vrefint (Voltage Reference internal) management \r
+ * + Regular Channels Configuration\r
+ * + Regular Channels DMA Configuration\r
+ * + Injected channels Configuration\r
+ * + Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+================================================================================\r
+ ##### How to use this driver #####\r
+================================================================================\r
+ [..]\r
+ (#) Configure the ADC Prescaler, conversion resolution and data alignment \r
+ using the ADC_Init() function.\r
+ (#) Activate the ADC peripheral using ADC_Cmd() function.\r
+ \r
+ *** Regular channels group configuration ***\r
+ ============================================\r
+ [..]\r
+ (+) To configure the ADC regular channels group features, use \r
+ ADC_Init() and ADC_RegularChannelConfig() functions.\r
+ (+) To activate the continuous mode, use the ADC_continuousModeCmd()\r
+ function.\r
+ (+) To configurate and activate the Discontinuous mode, use the \r
+ ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.\r
+ (+) To read the ADC converted values, use the ADC_GetConversionValue()\r
+ function.\r
+ \r
+ *** DMA for Regular channels group features configuration ***\r
+ =============================================================\r
+ [..]\r
+ (+) To enable the DMA mode for regular channels group, use the \r
+ ADC_DMACmd() function.\r
+ (+) To enable the generation of DMA requests continuously at the end\r
+ of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() \r
+ function.\r
+ \r
+ *** Injected channels group configuration ***\r
+ =============================================\r
+ [..]\r
+ (+) To configure the ADC Injected channels group features, use \r
+ ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()\r
+ functions.\r
+ (+) To activate the continuous mode, use the ADC_continuousModeCmd()\r
+ function.\r
+ (+) To activate the Injected Discontinuous mode, use the \r
+ ADC_InjectedDiscModeCmd() function.\r
+ (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() \r
+ function.\r
+ (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() \r
+ function.\r
+\r
+ @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+ \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_adc.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC \r
+ * @brief ADC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ADC DISCNUM mask */\r
+#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)\r
+ \r
+/* ADC AWDCH mask */\r
+#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) \r
+ \r
+/* ADC Analog watchdog enable mode mask */\r
+#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)\r
+ \r
+/* CR1 register Mask */\r
+#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) \r
+ \r
+/* ADC DELAY mask */ \r
+#define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)\r
+ \r
+/* ADC JEXTEN mask */\r
+#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)\r
+ \r
+/* ADC JEXTSEL mask */\r
+#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)\r
+ \r
+/* CR2 register Mask */\r
+#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)\r
+\r
+/* ADC SQx mask */\r
+#define SQR5_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR4_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR3_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR2_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR1_SQ_SET ((uint32_t)0x0000001F)\r
+\r
+/* ADC L Mask */\r
+#define SQR1_L_RESET ((uint32_t)0xFE0FFFFF) \r
+\r
+/* ADC JSQx mask */\r
+#define JSQR_JSQ_SET ((uint32_t)0x0000001F) \r
+ \r
+/* ADC JL mask */\r
+#define JSQR_JL_SET ((uint32_t)0x00300000) \r
+#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) \r
+\r
+/* ADC SMPx mask */\r
+#define SMPR1_SMP_SET ((uint32_t)0x00000007) \r
+#define SMPR2_SMP_SET ((uint32_t)0x00000007)\r
+#define SMPR3_SMP_SET ((uint32_t)0x00000007) \r
+#define SMPR0_SMP_SET ((uint32_t)0x00000007)\r
+\r
+/* ADC JDRx registers offset */\r
+#define JDR_OFFSET ((uint8_t)0x30) \r
+ \r
+/* ADC CCR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF) \r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions.\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the ADC Prescaler.\r
+ (+) ADC Conversion Resolution (12bit..6bit).\r
+ (+) Scan Conversion Mode (multichannel or one channel) for regular group.\r
+ (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for \r
+ regular group.\r
+ (+) External trigger Edge and source of regular group.\r
+ (+) Converted data alignment (left or right).\r
+ (+) The number of ADC conversions that will be done using the sequencer \r
+ for regular channel group.\r
+ (+) Enable or disable the ADC peripheral.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes ADC1 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ADC_DeInit(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ if(ADCx == ADC1)\r
+ {\r
+ /* Enable ADC1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+ /* Release ADC1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters\r
+ * in the ADC_InitStruct.\r
+ * @note This function is used to configure the global features of the ADC ( \r
+ * Resolution and Data Alignment), however, the rest of the configuration\r
+ * parameters are specific to the regular channels group (scan mode \r
+ * activation, continuous mode activation, External trigger source and \r
+ * edge, number of conversion in the regular channels group sequencer).\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains \r
+ * the configuration information for the specified ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) \r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint8_t tmpreg2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); \r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); \r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); \r
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));\r
+ \r
+ /*---------------------------- ADCx CR1 Configuration -----------------*/\r
+ /* Get the ADCx CR1 value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear RES and SCAN bits */ \r
+ tmpreg1 &= CR1_CLEAR_MASK;\r
+ /* Configure ADCx: scan conversion mode and resolution */\r
+ /* Set SCAN bit according to ADC_ScanConvMode value */\r
+ /* Set RES bit according to ADC_Resolution value */ \r
+ tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);\r
+ /* Write to ADCx CR1 */\r
+ ADCx->CR1 = tmpreg1;\r
+ \r
+ /*---------------------------- ADCx CR2 Configuration -----------------*/\r
+ /* Get the ADCx CR2 value */\r
+ tmpreg1 = ADCx->CR2;\r
+ /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */\r
+ tmpreg1 &= CR2_CLEAR_MASK;\r
+ /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */\r
+ /* Set ALIGN bit according to ADC_DataAlign value */\r
+ /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ \r
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
+ /* Set CONT bit according to ADC_ContinuousConvMode value */\r
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | \r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
+ /* Write to ADCx CR2 */\r
+ ADCx->CR2 = tmpreg1;\r
+ \r
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
+ /* Get the ADCx SQR1 value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Clear L bits */\r
+ tmpreg1 &= SQR1_L_RESET;\r
+ /* Configure ADCx: regular channel sequence length */\r
+ /* Set L bits according to ADC_NbrOfConversion value */ \r
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);\r
+ tmpreg1 |= ((uint32_t)tmpreg2 << 20);\r
+ /* Write to ADCx SQR1 */\r
+ ADCx->SQR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_InitStruct member with its default value.\r
+ * @note This function is used to initialize the global features of the ADC ( \r
+ * Resolution and Data Alignment), however, the rest of the configuration\r
+ * parameters are specific to the regular channels group (scan mode \r
+ * activation, continuous mode activation, External trigger source and \r
+ * edge, number of conversion in the regular channels group sequencer).\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) \r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Resolution member */\r
+ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;\r
+\r
+ /* Initialize the ADC_ScanConvMode member */\r
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ContinuousConvMode member */\r
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ExternalTrigConvEdge member */\r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r
+\r
+ /* Initialize the ADC_ExternalTrigConv member */\r
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;\r
+\r
+ /* Initialize the ADC_DataAlign member */\r
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
+\r
+ /* Initialize the ADC_NbrOfConversion member */\r
+ ADC_InitStruct->ADC_NbrOfConversion = 1;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCs peripherals according to the specified parameters\r
+ * in the ADC_CommonInitStruct.\r
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure \r
+ * that contains the configuration information (Prescaler) for ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));\r
+\r
+ /*---------------------------- ADC CCR Configuration -----------------*/\r
+ /* Get the ADC CCR value */\r
+ tmpreg = ADC->CCR;\r
+\r
+ /* Clear ADCPRE bit */ \r
+ tmpreg &= CR_CLEAR_MASK;\r
+ \r
+ /* Configure ADCx: ADC prescaler according to ADC_Prescaler */ \r
+ tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler); \r
+ \r
+ /* Write to ADC CCR */\r
+ ADC->CCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_CommonInitStruct member with its default value.\r
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Prescaler member */\r
+ ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC peripheral.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the ADCx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ADON bit to wake up the ADC from power down mode */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC peripheral */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified ADC Channels Bank.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Bank: ADC Channels Bank.\r
+ * @arg ADC_Bank_A: ADC Channels Bank A.\r
+ * @arg ADC_Bank_B: ADC Channels Bank B.\r
+ * @retval None\r
+ */\r
+void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_BANK(ADC_Bank));\r
+\r
+ if (ADC_Bank != ADC_Bank_A)\r
+ {\r
+ /* Set the ADC_CFG bit to select the ADC Bank B channels */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_CFG;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the ADC_CFG bit to select the ADC Bank A channels */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CFG);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group2 Power saving functions\r
+ * @brief Power saving functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Power saving functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to reduce power consumption.\r
+ [..] The two function must be combined to get the maximal benefits:\r
+ When the ADC frequency is higher than the CPU one, it is recommended to:\r
+ (#) Insert a freeze delay :\r
+ ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze).\r
+ (#) Enable the power down in Idle and Delay phases :\r
+ ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase.\r
+ * @note ADC power-on and power-off can be managed by hardware to cut the \r
+ * consumption when the ADC is not converting.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_PowerDown: The ADC power down configuration.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase.\r
+ * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase.\r
+ * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases.\r
+ * @note The ADC can be powered down:\r
+ * @note During the hardware delay insertion (using the ADC_PowerDown_Delay\r
+ * parameter).\r
+ * => The ADC is powered up again at the end of the delay.\r
+ * @note During the ADC is waiting for a trigger event ( using the \r
+ * ADC_PowerDown_Idle parameter).\r
+ * => The ADC is powered up at the next trigger event.\r
+ * @note During the hardware delay insertion or the ADC is waiting for a \r
+ * trigger event (using the ADC_PowerDown_Idle_Delay parameter).\r
+ * => The ADC is powered up only at the end of the delay and at the\r
+ * next trigger event.\r
+ * @param NewState: new state of the ADCx power down.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC power-down during Delay and/or Idle phase */\r
+ ADCx->CR1 |= ADC_PowerDown;\r
+ }\r
+ else\r
+ {\r
+ /* Disable The ADC power-down during Delay and/or Idle phase */\r
+ ADCx->CR1 &= (uint32_t)~ADC_PowerDown;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Defines the length of the delay which is applied after a conversion \r
+ * or a sequence of conversion.\r
+ * @note When the CPU clock is not fast enough to manage the data rate, a \r
+ * Hardware delay can be introduced between ADC conversions to reduce \r
+ * this data rate.\r
+ * @note The Hardware delay is inserted after :\r
+ * - each regular conversion.\r
+ * - after each sequence of injected conversions.\r
+ * @note No Hardware delay is inserted between conversions of different groups.\r
+ * @note When the hardware delay is not enough, the Freeze Delay Mode can be \r
+ * selected and a new conversion can start only if all the previous data \r
+ * of the same group have been treated:\r
+ * - for a regular conversion: once the ADC conversion data register has \r
+ * been read (using ADC_GetConversionValue() function) or if the EOC \r
+ * Flag has been cleared (using ADC_ClearFlag() function).\r
+ * - for an injected conversion: when the JEOC bit has been cleared \r
+ * (using ADC_ClearFlag() function).\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_DelayLength: The length of delay which is applied after a \r
+ * conversion or a sequence of conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_DelayLength_None: No delay.\r
+ * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.\r
+ * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles.\r
+ * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles \r
+ * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles \r
+ * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles \r
+ * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles \r
+ * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles \r
+ * @retval None\r
+ */\r
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));\r
+\r
+ /* Get the old register value */ \r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old delay length */\r
+ tmpreg &= CR2_DELS_RESET;\r
+ /* Set the delay length */\r
+ tmpreg |= ADC_DelayLength;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group3 Analog Watchdog configuration functions\r
+ * @brief Analog Watchdog configuration functions. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Analog Watchdog configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to configure the Analog Watchdog\r
+ (AWD) feature in the ADC.\r
+ [..] A typical configuration Analog Watchdog is done following these steps :\r
+ (#) the ADC guarded channel(s) is (are) selected using the \r
+ ADC_AnalogWatchdogSingleChannelConfig() function.\r
+ (#) The Analog watchdog lower and higher threshold are configured using \r
+ the ADC_AnalogWatchdogThresholdsConfig() function.\r
+ (#) The Analog watchdog is enabled and configured to enable the check, \r
+ on one or more channels, using the ADC_AnalogWatchdogCmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the analog watchdog on single/all regular\r
+ * or injected channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single \r
+ * regular channel.\r
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single \r
+ * injected channel.\r
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a \r
+ * single regular or injected channel.\r
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular \r
+ * channel.\r
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected \r
+ * channel.\r
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all \r
+ * regular and injected channels.\r
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog.\r
+ * @retval None \r
+ */\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear AWDEN, JAWDEN and AWDSGL bits */ \r
+ tmpreg &= CR1_AWDMODE_RESET;\r
+ /* Set the analog watchdog enable mode */\r
+ tmpreg |= ADC_AnalogWatchdog;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the high and low thresholds of the analog watchdog.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param HighThreshold: the ADC analog watchdog High threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
+ uint16_t LowThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
+\r
+ /* Set the ADCx high threshold */\r
+ ADCx->HTR = HighThreshold;\r
+ /* Set the ADCx low threshold */\r
+ ADCx->LTR = LowThreshold;\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog guarded single channel.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected\r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @arg ADC_Channel_27: ADC Channel27 selected\r
+ * @arg ADC_Channel_28: ADC Channel28 selected\r
+ * @arg ADC_Channel_29: ADC Channel29 selected\r
+ * @arg ADC_Channel_30: ADC Channel30 selected\r
+ * @arg ADC_Channel_31: ADC Channel31 selected\r
+ * @arg ADC_Channel_0b: ADC Channel0b selected\r
+ * @arg ADC_Channel_1b: ADC Channel1b selected\r
+ * @arg ADC_Channel_2b: ADC Channel2b selected\r
+ * @arg ADC_Channel_3b: ADC Channel3b selected\r
+ * @arg ADC_Channel_6b: ADC Channel6b selected\r
+ * @arg ADC_Channel_7b: ADC Channel7b selected\r
+ * @arg ADC_Channel_8b: ADC Channel8b selected\r
+ * @arg ADC_Channel_9b: ADC Channel9b selected\r
+ * @arg ADC_Channel_10b: ADC Channel10b selected\r
+ * @arg ADC_Channel_11b: ADC Channel11b selected\r
+ * @arg ADC_Channel_12b: ADC Channel12b selected\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear the Analog watchdog channel select bits */\r
+ tmpreg &= CR1_AWDCH_RESET;\r
+ /* Set the Analog watchdog channel */\r
+ tmpreg |= ADC_Channel;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
+ * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function.\r
+ *\r
+@verbatim \r
+ =========================================================================================\r
+ ##### Temperature Sensor and Vrefint (Voltage Reference internal) management function #####\r
+ =========================================================================================\r
+ [..] This section provides a function allowing to enable/ disable the internal \r
+ connections between the ADC and the Temperature Sensor and the Vrefint \r
+ source.\r
+ [..] A typical configuration to get the Temperature sensor and Vrefint channels \r
+ voltages is done following these steps :\r
+ (#) Enable the internal connection of Temperature sensor and Vrefint sources \r
+ with the ADC channels using ADC_TempSensorVrefintCmd() function.\r
+ (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using \r
+ ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions.\r
+ (#) Get the voltage values, using ADC_GetConversionValue() or \r
+ ADC_GetInjectedConversionValue().\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the temperature sensor and Vrefint channel.\r
+ * @param NewState: new state of the temperature sensor and Vref int channels.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the temperature sensor and Vrefint channel*/\r
+ ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the temperature sensor and Vrefint channel*/\r
+ ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group5 Regular Channels Configuration functions\r
+ * @brief Regular Channels Configuration functions.\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Regular Channels Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to manage the ADC regular channels,\r
+ it is composed of 2 sub sections :\r
+ (#) Configuration and management functions for regular channels: This \r
+ subsection provides functions allowing to configure the ADC regular \r
+ channels :\r
+ (++) Configure the rank in the regular group sequencer for each channel.\r
+ (++) Configure the sampling time for each channel.\r
+ (++) select the conversion Trigger for regular channels.\r
+ (++) select the desired EOC event behavior configuration.\r
+ (++) Activate the continuous Mode (*).\r
+ (++) Activate the Discontinuous Mode.\r
+ -@@- Please Note that the following features for regular channels are \r
+ configurated using the ADC_Init() function : \r
+ (+@@) scan mode activation.\r
+ (+@@) continuous mode activation (**).\r
+ (+@@) External trigger source.\r
+ (+@@) External trigger edge.\r
+ (+@@) number of conversion in the regular channels group sequencer.\r
+ -@@- (*) and (**) are performing the same configuration.\r
+ (#) Get the conversion data: This subsection provides an important function \r
+ in the ADC peripheral since it returns the converted data of the current \r
+ regular channel. When the Conversion value is read, the EOC Flag is \r
+ automatically cleared.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures for the selected ADC regular channel its corresponding\r
+ * rank in the sequencer and its sampling time.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @arg ADC_Channel_27: ADC Channel27 selected\r
+ * @arg ADC_Channel_28: ADC Channel28 selected\r
+ * @arg ADC_Channel_29: ADC Channel29 selected\r
+ * @arg ADC_Channel_30: ADC Channel30 selected\r
+ * @arg ADC_Channel_31: ADC Channel31 selected \r
+ * @arg ADC_Channel_0b: ADC Channel0b selected\r
+ * @arg ADC_Channel_1b: ADC Channel1b selected\r
+ * @arg ADC_Channel_2b: ADC Channel2b selected\r
+ * @arg ADC_Channel_3b: ADC Channel3b selected\r
+ * @arg ADC_Channel_6b: ADC Channel6b selected\r
+ * @arg ADC_Channel_7b: ADC Channel7b selected\r
+ * @arg ADC_Channel_8b: ADC Channel8b selected\r
+ * @arg ADC_Channel_9b: ADC Channel9b selected\r
+ * @arg ADC_Channel_10b: ADC Channel10b selected\r
+ * @arg ADC_Channel_11b: ADC Channel11b selected\r
+ * @arg ADC_Channel_12b: ADC Channel12b selected \r
+ * @param Rank: The rank in the regular group sequencer. This parameter\r
+ * must be between 1 to 28.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles\r
+ * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
+ * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
+ * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
+ * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
+ * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
+ * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
+ * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
+ * @retval None\r
+ */\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_REGULAR_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+\r
+ /* If ADC_Channel_30 or ADC_Channel_31 is selected */\r
+ if (ADC_Channel > ADC_Channel_29)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR0;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR0 = tmpreg1;\r
+ }\r
+ /* If ADC_Channel_20 ... ADC_Channel_29 is selected */\r
+ else if (ADC_Channel > ADC_Channel_19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ /* If ADC_Channel_10 ... ADC_Channel_19 is selected */\r
+ else if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR3 = tmpreg1;\r
+ }\r
+ /* For Rank 1 to 6 */\r
+ if (Rank < 7)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR5;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR5 = tmpreg1;\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (Rank < 13)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR4;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR4 = tmpreg1;\r
+ } \r
+ /* For Rank 13 to 18 */\r
+ else if (Rank < 19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR3 = tmpreg1;\r
+ }\r
+ \r
+ /* For Rank 19 to 24 */\r
+ else if (Rank < 25)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR2 = tmpreg1;\r
+ } \r
+ \r
+ /* For Rank 25 to 28 */\r
+ else\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR1 = tmpreg1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the regular channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Enable the selected ADC conversion for regular group */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start regular conversion Status.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The new state of ADC software start conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Check the status of SWSTART bit */\r
+ if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)\r
+ {\r
+ /* SWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the EOC on each regular channel conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC EOC flag rising\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC EOC rising on each regular channel conversion */\r
+ ADCx->CR2 |= ADC_CR2_EOCS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC EOC rising on each regular channel conversion */\r
+ ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADC continuous conversion mode.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC continuous conversion mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC continuous conversion mode */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC continuous conversion mode */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the discontinuous mode for the selected ADC regular\r
+ * group channel.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param Number: specifies the discontinuous mode regular channel count value.\r
+ * This number must be between 1 and 8.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
+\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= CR1_DISCNUM_RESET;\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg2 = Number - 1;\r
+ tmpreg1 |= tmpreg2 << 13;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode on regular group\r
+ * channel for the specified ADC.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode on regular \r
+ * group channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADCx conversion result data for regular channel.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Return the selected ADC conversion value */\r
+ return (uint16_t) ADCx->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group6 Regular Channels DMA Configuration functions\r
+ * @brief Regular Channels DMA Configuration functions.\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Regular Channels DMA Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to configure the DMA for ADC regular \r
+ channels.Since converted regular channel values are stored into a unique \r
+ data register, it is useful to use DMA for conversion of more than one \r
+ regular channel. This avoids the loss of the data already stored in the \r
+ ADC Data register.\r
+ When the DMA mode is enabled (using the ADC_DMACmd() function), after each\r
+ conversion of a regular channel, a DMA request is generated.\r
+ [..] Depending on the "DMA disable selection" configuration (using the \r
+ ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA \r
+ transfer, two possibilities are allowed:\r
+ (+) No new DMA request is issued to the DMA controller (feature DISABLED).\r
+ (+) Requests can continue to be generated (feature ENABLED).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC DMA request.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode).\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC EOC flag rising\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request after last transfer */\r
+ ADCx->CR2 |= ADC_CR2_DDS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request after last transfer */\r
+ ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group7 Injected channels Configuration functions\r
+ * @brief Injected channels Configuration functions.\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Injected channels Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to configure the ADC Injected channels,\r
+ it is composed of 2 sub sections : \r
+ (#) Configuration functions for Injected channels: This subsection provides \r
+ functions allowing to configure the ADC injected channels :\r
+ (++) Configure the rank in the injected group sequencer for each channel.\r
+ (++) Configure the sampling time for each channel.\r
+ (++) Activate the Auto injected Mode.\r
+ (++) Activate the Discontinuous Mode.\r
+ (++) scan mode activation.\r
+ (++) External/software trigger source.\r
+ (++) External trigger edge.\r
+ (++) injected channels sequencer.\r
+ \r
+ (#) Get the Specified Injected channel conversion data: This subsection \r
+ provides an important function in the ADC peripheral since it returns \r
+ the converted data of the specific injected channel.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Configures for the selected ADC injected channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @arg ADC_Channel_27: ADC Channel27 selected\r
+ * @arg ADC_Channel_28: ADC Channel28 selected\r
+ * @arg ADC_Channel_29: ADC Channel29 selected\r
+ * @arg ADC_Channel_30: ADC Channel30 selected\r
+ * @arg ADC_Channel_31: ADC Channel31 selected \r
+ * @arg ADC_Channel_0b: ADC Channel0b selected\r
+ * @arg ADC_Channel_1b: ADC Channel1b selected\r
+ * @arg ADC_Channel_2b: ADC Channel2b selected\r
+ * @arg ADC_Channel_3b: ADC Channel3b selected\r
+ * @arg ADC_Channel_6b: ADC Channel6b selected\r
+ * @arg ADC_Channel_7b: ADC Channel7b selected\r
+ * @arg ADC_Channel_8b: ADC Channel8b selected\r
+ * @arg ADC_Channel_9b: ADC Channel9b selected\r
+ * @arg ADC_Channel_10b: ADC Channel10b selected\r
+ * @arg ADC_Channel_11b: ADC Channel11b selected\r
+ * @arg ADC_Channel_12b: ADC Channel12b selected \r
+ * @param Rank: The rank in the injected group sequencer. This parameter\r
+ * must be between 1 to 4.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel. This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles\r
+ * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
+ * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
+ * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
+ * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
+ * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
+ * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
+ * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
+ * @retval None\r
+ */\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_INJECTED_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+ \r
+ /* If ADC_Channel_30 or ADC_Channel_31 is selected */\r
+ if (ADC_Channel > ADC_Channel_29)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR0;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR0 = tmpreg1;\r
+ }\r
+ /* If ADC_Channel_20 ... ADC_Channel_29 is selected */\r
+ else if (ADC_Channel > ADC_Channel_19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ } \r
+ /* If ADC_Channel_10 ... ADC_Channel_19 is selected */\r
+ else if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR3 = tmpreg1;\r
+ }\r
+ \r
+ /* Rank configuration */\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Get JL value: Number = JL+1 */\r
+ tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;\r
+ /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ \r
+ tmpreg2 = (uint32_t)(JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))));\r
+ /* Clear the old JSQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ \r
+ tmpreg2 = (uint32_t)(((uint32_t)(ADC_Channel)) << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))));\r
+ /* Set the JSQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the sequencer length for injected channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param Length: The sequencer length.\r
+ * This parameter must be a number between 1 to 4.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Clear the old injected sequence length JL bits */\r
+ tmpreg1 &= JSQR_JL_RESET;\r
+ /* Set the injected sequence length JL bits */\r
+ tmpreg2 = Length - 1; \r
+ tmpreg1 |= tmpreg2 << 20;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Set the injected channels conversion value offset.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected.\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected.\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected.\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected.\r
+ * @param Offset: the offset value for the selected ADC injected channel\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+ assert_param(IS_ADC_OFFSET(Offset)); \r
+ \r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel;\r
+ \r
+ /* Set the selected injected channel data offset */\r
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger for injected channels conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected \r
+ * conversion. This parameter can be one of the following values:\r
+ * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected\r
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected\r
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external event selection for injected group */\r
+ tmpreg &= CR2_JEXTSEL_RESET;\r
+ /* Set the external event selection for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConv;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger edge for injected channels conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger\r
+ * edge to start injected conversion.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for \r
+ * injected conversion.\r
+ * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge\r
+ * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge\r
+ * @arg ADC_ExternalTrigConvEdge_RisingFalling: detection on \r
+ * both rising and falling edge\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external trigger edge for injected group */\r
+ tmpreg &= CR2_JEXTEN_RESET;\r
+ /* Set the new external trigger edge for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConvEdge;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the injected \r
+ * channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Enable the selected ADC conversion for injected group */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start injected conversion Status.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The new state of ADC software start injected conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Check the status of JSWSTART bit */\r
+ if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)\r
+ {\r
+ /* JSWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* JSWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the JSWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC automatic injected group\r
+ * conversion after regular one.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC auto injected\r
+ * conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode for injected group\r
+ * channel for the specified ADC.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode\r
+ * on injected group channel. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the ADC injected channel conversion result.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_InjectedChannel: the converted ADC injected channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+\r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel + JDR_OFFSET;\r
+ \r
+ /* Returns the selected injected channel conversion data value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group8 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions.\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to configure the ADC Interrupts \r
+ and get the status and clear flags and Interrupts pending bits.\r
+ \r
+ [..] The ADC provide 4 Interrupts sources and 9 Flags which can be divided into \r
+ 3 groups:\r
+ *** Flags and Interrupts for ADC regular channels ***\r
+ =====================================================\r
+ [..]\r
+ (+)Flags :\r
+ (##) ADC_FLAG_OVR : Overrun detection when regular converted data are \r
+ lost.\r
+ (##) ADC_FLAG_EOC : Regular channel end of conversion + to indicate \r
+ (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )\r
+ the end of :\r
+ (+++) a regular CHANNEL conversion.\r
+ (+++) sequence of regular GROUP conversions.\r
+\r
+\r
+ (##) ADC_FLAG_STRT: Regular channel start + to indicate when regular \r
+ CHANNEL conversion starts.\r
+ (##) ADC_FLAG_RCNR: Regular channel not ready + to indicate if a new \r
+ regular conversion can be launched.\r
+ (+)Interrupts :\r
+ (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection \r
+ event.\r
+ (##) ADC_IT_EOC : specifies the interrupt source for Regular channel \r
+ end of conversion event.\r
+ \r
+ *** Flags and Interrupts for ADC Injected channels ***\r
+ ======================================================\r
+ (+)Flags :\r
+ (##) ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at \r
+ the end of injected GROUP conversion.\r
+ (##) ADC_FLAG_JSTRT: Injected channel start + to indicate hardware when \r
+ injected GROUP conversion starts.\r
+ (##) ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new \r
+ injected conversion can be launched.\r
+ (+)Interrupts \r
+ (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel \r
+ end of conversion event.\r
+ *** General Flags and Interrupts for the ADC ***\r
+ ================================================\r
+ (+)Flags :\r
+ (##) ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage \r
+ crosses the programmed thresholds values.\r
+ (##) ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready \r
+ to convert.\r
+ (+)Interrupts :\r
+ (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog \r
+ event.\r
+ \r
+ [..] The user should identify which mode will be used in his application to \r
+ manage the ADC controller events: Polling mode or Interrupt mode.\r
+ \r
+ [..] In the Polling Mode it is advised to use the following functions:\r
+ (+) ADC_GetFlagStatus() : to check if flags events occur.\r
+ (+) ADC_ClearFlag() : to clear the flags events.\r
+ \r
+ [..] In the Interrupt Mode it is advised to use the following functions:\r
+ (+) ADC_ITConfig() : to enable or disable the interrupt source.\r
+ (+) ADC_GetITStatus() : to check if Interrupt occurs.\r
+ (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit \r
+ (corresponding Flag).\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC interrupts.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt\r
+ * @arg ADC_IT_OVR: overrun interrupt\r
+ * @param NewState: new state of the specified ADC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) \r
+{\r
+ uint32_t itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_IT(ADC_IT)); \r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)ADC_IT;\r
+ itmask = (uint32_t)0x01 << itmask; \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADCx->CR1 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADCx->CR1 &= (~(uint32_t)itmask);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC flag is set or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @arg ADC_FLAG_OVR: Overrun flag\r
+ * @arg ADC_FLAG_ADONS: ADC ON status\r
+ * @arg ADC_FLAG_RCNR: Regular channel not ready\r
+ * @arg ADC_FLAG_JCNR: Injected channel not ready\r
+ * @retval The new state of ADC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
+\r
+ /* Check the status of the specified ADC flag */\r
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
+ {\r
+ /* ADC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's pending flags.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @arg ADC_FLAG_OVR: overrun flag\r
+ * @retval None\r
+ */\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
+\r
+ /* Clear the selected ADC flags */\r
+ ADCx->SR = ~(uint32_t)ADC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC interrupt has occurred or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt\r
+ * @arg ADC_IT_OVR: Overrun interrupt\r
+ * @retval The new state of ADC_IT (SET or RESET).\r
+ */\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT));\r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint32_t)((uint32_t)ADC_IT >> 8);\r
+\r
+ /* Get the ADC_IT enable bit status */\r
+ enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); \r
+\r
+ /* Check the status of the specified ADC interrupt */\r
+ if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ { \r
+ /* ADC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's interrupt pending bits.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt\r
+ * @arg ADC_IT_OVR: Overrun interrupt\r
+ * @retval None\r
+ */\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ uint8_t itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT)); \r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)(ADC_IT >> 8);\r
+\r
+ /* Clear the selected ADC interrupt pending bits */\r
+ ADCx->SR = ~(uint32_t)itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_aes.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the AES peripheral: \r
+ * + Configuration\r
+ * + Read/Write operations\r
+ * + DMA transfers management \r
+ * + Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ ===============================================================================\r
+ ##### AES Peripheral features #####\r
+ ===============================================================================\r
+....[..]\r
+ (#) The Advanced Encryption Standard hardware accelerator (AES) can be used\r
+ to both encipher and decipher data using AES algorithm.\r
+ (#) The AES supports 4 operation modes:\r
+ (++) Encryption: It consumes 214 clock cycle when processing one 128-bit block\r
+ (++) Decryption: It consumes 214 clock cycle when processing one 128-bit block\r
+ (++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block\r
+ (++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk\r
+ (#) Moreover 3 chaining modes are supported:\r
+ (++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately\r
+ (++) Cipher block chaining (CBC): Each block is XORed with the previous block\r
+ (++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the\r
+ plain text to give the cipher text\r
+ (#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.\r
+ (#) The AES peripheral supports write/read error handling with interrupt capability.\r
+ (#) Automatic data flow control with support of direct memory access (DMA) using\r
+ 2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data\r
+ (DMA2 Channel3).\r
+\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (#) AES AHB clock must be enabled to get write access to AES registers \r
+ using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).\r
+ (#) Initialize the key using AES_KeyInit().\r
+ (#) Configure the AES operation mode using AES_Init().\r
+ (#) If required, enable interrupt source using AES_ITConfig() and\r
+ enable the AES interrupt vector using NVIC_Init().\r
+ (#) If required, when using the DMA mode.\r
+ (##) Configure the DMA using DMA_Init().\r
+ (##) Enable DMA requests using AES_DMAConfig().\r
+ (#) Enable the AES peripheral using AES_Cmd().\r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_aes.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup AES \r
+ * @brief AES driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define CR_CLEAR_MASK ((uint32_t)0xFFFFFF81)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup AES_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup AES_Group1 Initialization and configuration\r
+ * @brief Initialization and configuration.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and configuration #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+ /**\r
+ * @brief Deinitializes AES peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void AES_DeInit(void)\r
+{\r
+ /* Enable AES reset state */\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE);\r
+ /* Release AES from reset state */\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the AES peripheral according to the specified parameters\r
+ * in the AES_InitStruct:\r
+ * - AES_Operation: specifies the operation mode (encryption, decryption...).\r
+ * - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).\r
+ * - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.\r
+ * @note If AES is already enabled, use AES_Cmd(DISABLE) before setting the new \r
+ * configuration (When AES is enabled, setting configuration is forbidden).\r
+ * @param AES_InitStruct: pointer to an AES_InitTypeDef structure that contains \r
+ * the configuration information for AES peripheral.\r
+ * @retval None\r
+ */\r
+void AES_Init(AES_InitTypeDef* AES_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation));\r
+ assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining));\r
+ assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType));\r
+\r
+ /* Get AES CR register value */\r
+ tmpreg = AES->CR;\r
+ \r
+ /* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */\r
+ tmpreg &= (uint32_t)CR_CLEAR_MASK;\r
+ \r
+ tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType);\r
+\r
+ AES->CR = (uint32_t) tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.\r
+ * @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that\r
+ * contains the configuration information for the specified AES Keys.\r
+ * @note This function must be called while the AES is disabled.\r
+ * @note In encryption, key derivation and key derivation + decryption modes,\r
+ * AES_KeyInitStruct must contain the encryption key.\r
+ * In decryption mode, AES_KeyInitStruct must contain the decryption key.\r
+ * @retval None\r
+ */\r
+void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct)\r
+{\r
+ AES->KEYR0 = AES_KeyInitStruct->AES_Key0;\r
+ AES->KEYR1 = AES_KeyInitStruct->AES_Key1;\r
+ AES->KEYR2 = AES_KeyInitStruct->AES_Key2;\r
+ AES->KEYR3 = AES_KeyInitStruct->AES_Key3;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the AES Initialization Vector IV according to \r
+ * the specified parameters in the AES_IVInitStruct.\r
+ * @param AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that\r
+ * contains the configuration information for the specified AES IV.\r
+ * @note When ECB chaining mode is selected, Initialization Vector IV has no\r
+ * meaning.\r
+ * When CTR chaining mode is selected, AES_IV0 contains the CTR value.\r
+ * AES_IV1, AES_IV2 and AES_IV3 contains nonce value.\r
+ * @retval None\r
+ */\r
+void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct)\r
+{\r
+ AES->IVR0 = AES_IVInitStruct->AES_IV0;\r
+ AES->IVR1 = AES_IVInitStruct->AES_IV1;\r
+ AES->IVR2 = AES_IVInitStruct->AES_IV2;\r
+ AES->IVR3 = AES_IVInitStruct->AES_IV3;\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the AES peripheral.\r
+ * @param NewState: new state of the AES peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note The key must be written while AES is disabled.\r
+ * @retval None\r
+ */\r
+void AES_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the AES peripheral */\r
+ AES->CR |= (uint32_t) AES_CR_EN; /**< AES Enable */\r
+ }\r
+ else\r
+ {\r
+ /* Disable the AES peripheral */\r
+ AES->CR &= (uint32_t)(~AES_CR_EN); /**< AES Disable */\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AES_Group2 Structures initialization functions\r
+ * @brief Structures initialization.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Structures initialization functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Fills each AES_InitStruct member with its default value.\r
+ * @param AES_InitStruct: pointer to an AES_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void AES_StructInit(AES_InitTypeDef* AES_InitStruct)\r
+{\r
+ AES_InitStruct->AES_Operation = AES_Operation_Encryp;\r
+ AES_InitStruct->AES_Chaining = AES_Chaining_ECB;\r
+ AES_InitStruct->AES_DataType = AES_DataType_32b;\r
+}\r
+\r
+/**\r
+ * @brief Fills each AES_KeyInitStruct member with its default value.\r
+ * @param AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which \r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct)\r
+{\r
+ AES_KeyInitStruct->AES_Key0 = 0x00000000;\r
+ AES_KeyInitStruct->AES_Key1 = 0x00000000;\r
+ AES_KeyInitStruct->AES_Key2 = 0x00000000;\r
+ AES_KeyInitStruct->AES_Key3 = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @brief Fills each AES_IVInitStruct member with its default value.\r
+ * @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct)\r
+{\r
+ AES_IVInitStruct->AES_IV0 = 0x00000000;\r
+ AES_IVInitStruct->AES_IV1 = 0x00000000;\r
+ AES_IVInitStruct->AES_IV2 = 0x00000000;\r
+ AES_IVInitStruct->AES_IV3 = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AES_Group3 AES Read and Write\r
+ * @brief AES Read and Write.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### AES Read and Write functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Write data in DINR register to be processed by AES peripheral.\r
+ * @note To process 128-bit data (4 * 32-bit), this function must be called\r
+ * four times to write the 128-bit data in the 32-bit register DINR.\r
+ * @note When an unexpected write to DOUTR register is detected, WRERR flag is\r
+ * set.\r
+ * @param Data: The data to be processed.\r
+ * @retval None\r
+ */\r
+void AES_WriteSubData(uint32_t Data)\r
+{\r
+ /* Write Data */\r
+ AES->DINR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the data in DOUTR register processed by AES peripheral.\r
+ * @note This function must be called four times to get the 128-bit data.\r
+ * @note When an unexpected read of DINR register is detected, RDERR flag is\r
+ * set.\r
+ * @retval The processed data.\r
+ */\r
+uint32_t AES_ReadSubData(void)\r
+{\r
+ /* Read Data */\r
+ return AES->DOUTR;\r
+}\r
+\r
+/**\r
+ * @brief Read the Key value.\r
+ * @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which\r
+ * will contain the key.\r
+ * @note When the key derivation mode is selected, AES must be disabled\r
+ * (AES_Cmd(DISABLE)) before reading the decryption key.\r
+ * Reading the key while the AES is enabled will return unpredictable\r
+ * value.\r
+ * @retval None\r
+ */\r
+void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct)\r
+{\r
+ AES_KeyInitStruct->AES_Key0 = AES->KEYR0;\r
+ AES_KeyInitStruct->AES_Key1 = AES->KEYR1;\r
+ AES_KeyInitStruct->AES_Key2 = AES->KEYR2;\r
+ AES_KeyInitStruct->AES_Key3 = AES->KEYR3;\r
+}\r
+\r
+/**\r
+ * @brief Read the Initialization Vector IV value.\r
+ * @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which\r
+ * will contain the Initialization Vector IV.\r
+ * @note When the AES is enabled Reading the Initialization Vector IV value\r
+ * will return 0. The AES must be disabled using AES_Cmd(DISABLE)\r
+ * to get the right value.\r
+ * @note When ECB chaining mode is selected, Initialization Vector IV has no\r
+ * meaning.\r
+ * When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value.\r
+ * AES_IV1, AES_IV2 and AES_IV3 contains nonce value.\r
+ * @retval None\r
+ */\r
+void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct)\r
+{\r
+ AES_IVInitStruct->AES_IV0 = AES->IVR0;\r
+ AES_IVInitStruct->AES_IV1 = AES->IVR1;\r
+ AES_IVInitStruct->AES_IV2 = AES->IVR2;\r
+ AES_IVInitStruct->AES_IV3 = AES->IVR3;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AES_Group4 DMA transfers management functions\r
+ * @brief DMA transfers management function.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DMA transfers management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the AES DMA interface.\r
+ * @param AES_DMATransfer: Specifies the AES DMA transfer.\r
+ * This parameter can be one of the following values:\r
+ * @arg AES_DMATransfer_In: When selected, DMA manages the data input phase.\r
+ * @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase.\r
+ * @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.\r
+ * @param NewState Indicates the new state of the AES DMA interface.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note The DMA has no action in key derivation mode.\r
+ * @retval None\r
+ */\r
+void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer */\r
+ AES->CR |= (uint32_t) AES_DMATransfer;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer */\r
+ AES->CR &= (uint32_t)(~AES_DMATransfer);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AES_Group5 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions.\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified AES interrupt.\r
+ * @param AES_IT: Specifies the AES interrupt source to enable/disable.\r
+ * This parameter can be any combinations of the following values:\r
+ * @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF \r
+ * flag is set an interrupt is generated.\r
+ * @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error\r
+ * flags (RDERR) or write error flag (WRERR) is set,\r
+ * an interrupt is generated.\r
+ * @param NewState: The new state of the AES interrupt source.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_AES_IT(AES_IT));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ AES->CR |= (uint32_t) AES_IT; /**< AES_IT Enable */\r
+ }\r
+ else\r
+ {\r
+ AES->CR &= (uint32_t)(~AES_IT); /**< AES_IT Disable */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified AES flag is set or not.\r
+ * @param AES_FLAG specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when\r
+ * he computation phase is completed.\r
+ * @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read\r
+ * operation of DOUTR register is detected.\r
+ * @arg AES_FLAG_WRERR: Write Error Flag is set when an unexpected write\r
+ * operation in DINR is detected.\r
+ * @retval FlagStatus (SET or RESET)\r
+ */\r
+FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_AES_FLAG(AES_FLAG));\r
+\r
+ if ((AES->SR & AES_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the AES_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the AES flags.\r
+ * @param AES_FLAG: specifies the flag to clear.\r
+ * This parameter can be:\r
+ * @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC\r
+ * bit in CR register.\r
+ * @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in \r
+ * CR register.\r
+ * @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in\r
+ * CR register.\r
+ * @retval None\r
+ */\r
+void AES_ClearFlag(uint32_t AES_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_AES_FLAG(AES_FLAG));\r
+\r
+ /* Check if AES_FLAG is AES_FLAG_CCF */\r
+ if (AES_FLAG == AES_FLAG_CCF)\r
+ {\r
+ /* Clear CCF flag by setting CCFC bit */\r
+ AES->CR |= (uint32_t) AES_CR_CCFC;\r
+ }\r
+ else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */\r
+ {\r
+ /* Clear RDERR and WRERR flags by setting ERRC bit */\r
+ AES->CR |= (uint32_t) AES_CR_ERRC;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified AES interrupt has occurred or not.\r
+ * @param AES_IT: Specifies the AES interrupt pending bit to check.\r
+ * This parameter can be:\r
+ * @arg AES_IT_CC: Computation Complete Interrupt.\r
+ * @arg AES_IT_ERR: Error Interrupt.\r
+ * @retval ITStatus The new state of AES_IT (SET or RESET).\r
+ */\r
+ITStatus AES_GetITStatus(uint32_t AES_IT)\r
+{\r
+ ITStatus itstatus = RESET;\r
+ uint32_t cciebitstatus = RESET, ccfbitstatus = RESET;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_AES_GET_IT(AES_IT));\r
+\r
+ cciebitstatus = AES->CR & AES_CR_CCIE;\r
+ ccfbitstatus = AES->SR & AES_SR_CCF;\r
+\r
+ /* Check if AES_IT is AES_IT_CC */\r
+ if (AES_IT == AES_IT_CC)\r
+ {\r
+ /* Check the status of the specified AES interrupt */\r
+ if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET))\r
+ {\r
+ /* Interrupt occurred */\r
+ itstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt didn't occur */\r
+ itstatus = RESET;\r
+ }\r
+ }\r
+ else /* AES_IT is AES_IT_ERR */\r
+ {\r
+ /* Check the status of the specified AES interrupt */\r
+ if ((AES->CR & AES_CR_ERRIE) != RESET)\r
+ {\r
+ /* Check if WRERR or RDERR flags are set */\r
+ if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET)\r
+ {\r
+ /* Interrupt occurred */\r
+ itstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt didn't occur */\r
+ itstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt didn't occur */\r
+ itstatus = (ITStatus) RESET;\r
+ }\r
+ }\r
+\r
+ /* Return the AES_IT status */\r
+ return itstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the AES's interrupt pending bits.\r
+ * @param AES_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combinations of the following values:\r
+ * @arg AES_IT_CC: Computation Complete Interrupt.\r
+ * @arg AES_IT_ERR: Error Interrupt.\r
+ * @retval None\r
+ */\r
+void AES_ClearITPendingBit(uint32_t AES_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_AES_IT(AES_IT));\r
+\r
+ /* Clear the interrupt pending bit */\r
+ AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_aes_util.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides high level functions to encrypt and decrypt an \r
+ * input message using AES in ECB/CBC/CTR modes.\r
+ *\r
+ * @verbatim\r
+\r
+================================================================================\r
+ ##### How to use this driver #####\r
+================================================================================\r
+ [..]\r
+ (#) Enable The AES controller clock using \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function.\r
+\r
+ (#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode.\r
+ (#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode.\r
+\r
+ (#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode.\r
+ (#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode.\r
+\r
+ (#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode.\r
+ (#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode.\r
+\r
+ * @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_aes.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup AES \r
+ * @brief AES driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define AES_CC_TIMEOUT ((uint32_t) 0x00010000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup AES_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup AES_Group6 High Level AES functions\r
+ * @brief High Level AES functions \r
+ *\r
+@verbatim\r
+================================================================================\r
+ ##### High Level AES functions #####\r
+================================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Encrypt using AES in ECB Mode\r
+ * @param Key: Key used for AES algorithm.\r
+ * @param Input: pointer to the Input buffer.\r
+ * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
+ * @param Output: pointer to the returned buffer.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Operation done\r
+ * - ERROR: Operation failed\r
+ */\r
+ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
+{\r
+ AES_InitTypeDef AES_InitStructure;\r
+ AES_KeyInitTypeDef AES_KeyInitStructure;\r
+ ErrorStatus status = SUCCESS;\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ __IO uint32_t counter = 0;\r
+ uint32_t ccstatus = 0;\r
+ uint32_t i = 0;\r
+\r
+ /* AES Key initialisation */\r
+ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
+ AES_KeyInit(&AES_KeyInitStructure);\r
+\r
+ /* AES configuration */\r
+ AES_InitStructure.AES_Operation = AES_Operation_Encryp;\r
+ AES_InitStructure.AES_Chaining = AES_Chaining_ECB;\r
+ AES_InitStructure.AES_DataType = AES_DataType_8b;\r
+ AES_Init(&AES_InitStructure);\r
+\r
+ /* Enable AES */\r
+ AES_Cmd(ENABLE);\r
+\r
+ for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
+ {\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ \r
+ /* Wait for CCF flag to be set */\r
+ counter = 0;\r
+ do\r
+ {\r
+ ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
+ counter++;\r
+ }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
+ \r
+ if (ccstatus == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Clear CCF flag */\r
+ AES_ClearFlag(AES_FLAG_CCF);\r
+ /* Read cipher text */\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ }\r
+ }\r
+ \r
+ /* Disable AES before starting new processing */\r
+ AES_Cmd(DISABLE);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Decrypt using AES in ECB Mode\r
+ * @param Key: Key used for AES algorithm.\r
+ * @param Input: pointer to the Input buffer.\r
+ * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
+ * @param Output: pointer to the returned buffer.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Operation done\r
+ * - ERROR: Operation failed\r
+ */\r
+ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
+{\r
+ AES_InitTypeDef AES_InitStructure;\r
+ AES_KeyInitTypeDef AES_KeyInitStructure;\r
+ ErrorStatus status = SUCCESS;\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ __IO uint32_t counter = 0;\r
+ uint32_t ccstatus = 0;\r
+ uint32_t i = 0;\r
+\r
+ /* AES Key initialisation */\r
+ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
+ AES_KeyInit(&AES_KeyInitStructure);\r
+\r
+ /* AES configuration */\r
+ AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;\r
+ AES_InitStructure.AES_Chaining = AES_Chaining_ECB;\r
+ AES_InitStructure.AES_DataType = AES_DataType_8b;\r
+ AES_Init(&AES_InitStructure);\r
+\r
+ /* Enable AES */\r
+ AES_Cmd(ENABLE);\r
+\r
+ for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
+ {\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ \r
+ /* Wait for CCF flag to be set */\r
+ counter = 0;\r
+ do\r
+ {\r
+ ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
+ counter++;\r
+ }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
+ \r
+ if (ccstatus == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Clear CCF flag */\r
+ AES_ClearFlag(AES_FLAG_CCF);\r
+\r
+ /* Read cipher text */\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ }\r
+ }\r
+\r
+ /* Disable AES before starting new processing */\r
+ AES_Cmd(DISABLE);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Encrypt using AES in CBC Mode\r
+ * @param InitVectors: Initialisation Vectors used for AES algorithm.\r
+ * @param Key: Key used for AES algorithm.\r
+ * @param Input: pointer to the Input buffer.\r
+ * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
+ * @param Output: pointer to the returned buffer.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Operation done\r
+ * - ERROR: Operation failed\r
+ */\r
+ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
+{\r
+ AES_InitTypeDef AES_InitStructure;\r
+ AES_KeyInitTypeDef AES_KeyInitStructure;\r
+ AES_IVInitTypeDef AES_IVInitStructure;\r
+ ErrorStatus status = SUCCESS;\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ uint32_t ivaddr = (uint32_t)InitVectors;\r
+ __IO uint32_t counter = 0;\r
+ uint32_t ccstatus = 0;\r
+ uint32_t i = 0;\r
+\r
+ /* AES Key initialisation*/\r
+ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
+ AES_KeyInit(&AES_KeyInitStructure);\r
+\r
+ /* AES Initialization Vectors */\r
+ AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));\r
+ AES_IVInit(&AES_IVInitStructure);\r
+\r
+ /* AES configuration */\r
+ AES_InitStructure.AES_Operation = AES_Operation_Encryp;\r
+ AES_InitStructure.AES_Chaining = AES_Chaining_CBC;\r
+ AES_InitStructure.AES_DataType = AES_DataType_8b;\r
+ AES_Init(&AES_InitStructure);\r
+\r
+ /* Enable AES */\r
+ AES_Cmd(ENABLE);\r
+\r
+ for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
+ {\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ \r
+ /* Wait for CCF flag to be set */\r
+ counter = 0;\r
+ do\r
+ {\r
+ ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
+ counter++;\r
+ }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
+ \r
+ if (ccstatus == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Clear CCF flag */\r
+ AES_ClearFlag(AES_FLAG_CCF);\r
+\r
+ /* Read cipher text */\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ }\r
+ }\r
+\r
+ /* Disable AES before starting new processing */\r
+ AES_Cmd(DISABLE);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Decrypt using AES in CBC Mode\r
+ * @param InitVectors: Initialisation Vectors used for AES algorithm.\r
+ * @param Key: Key used for AES algorithm.\r
+ * @param Input: pointer to the Input buffer.\r
+ * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
+ * @param Output: pointer to the returned buffer.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Operation done\r
+ * - ERROR: Operation failed\r
+ */\r
+ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
+{\r
+ AES_InitTypeDef AES_InitStructure;\r
+ AES_KeyInitTypeDef AES_KeyInitStructure;\r
+ AES_IVInitTypeDef AES_IVInitStructure;\r
+ ErrorStatus status = SUCCESS;\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ uint32_t ivaddr = (uint32_t)InitVectors;\r
+ __IO uint32_t counter = 0;\r
+ uint32_t ccstatus = 0;\r
+ uint32_t i = 0;\r
+ \r
+ /* AES Key initialisation*/\r
+ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
+ AES_KeyInit(&AES_KeyInitStructure);\r
+\r
+ /* AES Initialization Vectors */\r
+ AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));\r
+ AES_IVInit(&AES_IVInitStructure);\r
+\r
+ /* AES configuration */\r
+ AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;\r
+ AES_InitStructure.AES_Chaining = AES_Chaining_CBC;\r
+ AES_InitStructure.AES_DataType = AES_DataType_8b;\r
+ AES_Init(&AES_InitStructure);\r
+\r
+ /* Enable AES */\r
+ AES_Cmd(ENABLE);\r
+\r
+ for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
+ {\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ \r
+ /* Wait for CCF flag to be set */\r
+ counter = 0;\r
+ do\r
+ {\r
+ ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
+ counter++;\r
+ }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
+\r
+ if (ccstatus == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Clear CCF flag */\r
+ AES_ClearFlag(AES_FLAG_CCF);\r
+\r
+ /* Read cipher text */\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ }\r
+ }\r
+\r
+ /* Disable AES before starting new processing */\r
+ AES_Cmd(DISABLE);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Encrypt using AES in CTR Mode\r
+ * @param InitVectors: Initialisation Vectors used for AES algorithm.\r
+ * @param Key: Key used for AES algorithm.\r
+ * @param Input: pointer to the Input buffer.\r
+ * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
+ * @param Output: pointer to the returned buffer.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Operation done\r
+ * - ERROR: Operation failed\r
+ */\r
+ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
+{\r
+ AES_InitTypeDef AES_InitStructure;\r
+ AES_KeyInitTypeDef AES_KeyInitStructure;\r
+ AES_IVInitTypeDef AES_IVInitStructure;\r
+\r
+ ErrorStatus status = SUCCESS;\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ uint32_t ivaddr = (uint32_t)InitVectors;\r
+ __IO uint32_t counter = 0;\r
+ uint32_t ccstatus = 0;\r
+ uint32_t i = 0;\r
+\r
+ /* AES key initialisation*/\r
+ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
+ AES_KeyInit(&AES_KeyInitStructure);\r
+\r
+ /* AES Initialization Vectors */\r
+ AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV2= __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV0= __REV(*(uint32_t*)(ivaddr));\r
+ AES_IVInit(&AES_IVInitStructure);\r
+\r
+ /* AES configuration */\r
+ AES_InitStructure.AES_Operation = AES_Operation_Encryp;\r
+ AES_InitStructure.AES_Chaining = AES_Chaining_CTR;\r
+ AES_InitStructure.AES_DataType = AES_DataType_8b;\r
+ AES_Init(&AES_InitStructure);\r
+\r
+ /* Enable AES */\r
+ AES_Cmd(ENABLE);\r
+\r
+ for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
+ {\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ \r
+ /* Wait for CCF flag to be set */\r
+ counter = 0;\r
+ do\r
+ {\r
+ ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
+ counter++;\r
+ }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
+\r
+ if (ccstatus == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Clear CCF flag */\r
+ AES_ClearFlag(AES_FLAG_CCF);\r
+\r
+ /* Read cipher text */\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ }\r
+ }\r
+\r
+ /* Disable AES before starting new processing */\r
+ AES_Cmd(DISABLE);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Decrypt using AES in CTR Mode\r
+ * @param InitVectors: Initialisation Vectors used for AES algorithm.\r
+ * @param Key: Key used for AES algorithm.\r
+ * @param Input: pointer to the Input buffer.\r
+ * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.\r
+ * @param Output: pointer to the returned buffer.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Operation done\r
+ * - ERROR: Operation failed\r
+ */\r
+ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r
+{\r
+ AES_InitTypeDef AES_InitStructure;\r
+ AES_KeyInitTypeDef AES_KeyInitStructure;\r
+ AES_IVInitTypeDef AES_IVInitStructure;\r
+\r
+ ErrorStatus status = SUCCESS;\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ uint32_t ivaddr = (uint32_t)InitVectors;\r
+ __IO uint32_t counter = 0;\r
+ uint32_t ccstatus = 0;\r
+ uint32_t i = 0;\r
+\r
+ /* AES Key initialisation*/\r
+ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr += 4;\r
+ AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));\r
+ AES_KeyInit(&AES_KeyInitStructure);\r
+\r
+ /* AES Initialization Vectors */\r
+ AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr += 4;\r
+ AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));\r
+ AES_IVInit(&AES_IVInitStructure);\r
+\r
+ /* AES configuration */\r
+ AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;\r
+ AES_InitStructure.AES_Chaining = AES_Chaining_CTR;\r
+ AES_InitStructure.AES_DataType = AES_DataType_8b;\r
+ AES_Init(&AES_InitStructure);\r
+\r
+ /* Enable AES */\r
+ AES_Cmd(ENABLE);\r
+\r
+ for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)\r
+ {\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ AES_WriteSubData(*(uint32_t*)(inputaddr));\r
+ inputaddr += 4;\r
+ \r
+ /* Wait for CCF flag to be set */\r
+ counter = 0;\r
+ do\r
+ {\r
+ ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);\r
+ counter++;\r
+ }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));\r
+\r
+ if (ccstatus == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Clear CCF flag */\r
+ AES_ClearFlag(AES_FLAG_CCF);\r
+ \r
+ /* Read cipher text */\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ *(uint32_t*)(outputaddr) = AES_ReadSubData();\r
+ outputaddr += 4;\r
+ }\r
+ }\r
+\r
+ /* Disable AES before starting new processing */\r
+ AES_Cmd(DISABLE);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_comp.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the comparators (COMP1 and COMP2) peripheral: \r
+ * + Comparators configuration\r
+ * + Window mode control\r
+ * + Internal Reference Voltage (VREFINT) output\r
+ *\r
+ * @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..] The device integrates two analog comparators COMP1 and COMP2:\r
+ (+) COMP1 is a fixed threshold (VREFINT) that shares the non inverting\r
+ input with the ADC channels.\r
+ (+) COMP2 is a rail-to-rail comparator whose the inverting input can be \r
+ selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, 1/2 VERFINT, 3/4 \r
+ VREFINT, VREFINT, PB3 and whose the output can be redirected to \r
+ embedded timers: TIM2, TIM3, TIM4, TIM10.\r
+ \r
+ (+) The two comparators COMP1 and COMP2 can be combined in window mode.\r
+\r
+ -@-\r
+ (#@) Comparator APB clock must be enabled to get write access\r
+ to comparator register using\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).\r
+ \r
+ (#@) COMP1 comparator and ADC can't be used at the same time since\r
+ they share the same ADC switch matrix (analog switches).\r
+ \r
+ (#@) When an I/O is used as comparator input, the corresponding GPIO \r
+ registers should be configured in analog mode.\r
+ \r
+ (#@) Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on\r
+ GPIO pin. They are only internal.\r
+ To get the comparator output level, use COMP_GetOutputLevel().\r
+ \r
+ (#@) COMP1 and COMP2 outputs are internally connected to EXTI Line 21\r
+ and EXTI Line 22 respectively.\r
+ Interrupts can be used by configuring the EXTI Line using the \r
+ EXTI peripheral driver.\r
+ \r
+ (#@) After enabling the comparator (COMP1 or COMP2), user should wait\r
+ for start-up time (tSTART) to get right output levels.\r
+ Please refer to product datasheet for more information on tSTART.\r
+ \r
+ (#@) Comparators cannot be used to exit the device from Sleep or Stop \r
+ mode when the internal reference voltage is switched off using \r
+ the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_comp.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup COMP \r
+ * @brief COMP driver modules.\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup COMP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup COMP_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes COMP peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void COMP_DeInit(void)\r
+{\r
+ COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */\r
+}\r
+\r
+/**\r
+ * @brief Initializes the COMP2 peripheral according to the specified parameters\r
+ * in the COMP_InitStruct.\r
+ * @note This function configures only COMP2.\r
+ * @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are \r
+ * different from "000".\r
+ * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains \r
+ * the configuration information for the specified COMP peripheral. \r
+ * @retval None\r
+ */\r
+void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));\r
+ assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));\r
+ assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));\r
+\r
+ /*!< Get the COMP CSR value */\r
+ tmpreg = COMP->CSR;\r
+\r
+ /*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */ \r
+ tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));\r
+ \r
+ /*!< Configure COMP: speed, inversion input selection and output redirection */\r
+ /*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */\r
+ /*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */ \r
+ /*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */ \r
+ tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput \r
+ | COMP_InitStruct->COMP_OutputSelect));\r
+\r
+ /*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are \r
+ different from "000" */\r
+ /*!< Write to COMP_CSR register */\r
+ COMP->CSR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the COMP1 peripheral.\r
+ * @note After enabling COMP1, the following functions should be called to \r
+ * connect the selected GPIO input to COMP1 non inverting input:\r
+ * @note Enable switch control mode using SYSCFG_RISwitchControlModeCmd()\r
+ * @note Close VCOMP switch using SYSCFG_RIIOSwitchConfig()\r
+ * @note Close the I/O switch number n corresponding to the I/O \r
+ * using SYSCFG_RIIOSwitchConfig()\r
+ * @param NewState: new state of the COMP1 peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note This function enables/disables only the COMP1.\r
+ * @retval None\r
+ */\r
+void COMP_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the COMP1 */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the COMP1 */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the output level (high or low) of the selected comparator.\r
+ * @note Comparator output is low when the noninverting input is at a lower\r
+ * voltage than the inverting input.\r
+ * @note Comparator output is high when the noninverting input is at a higher\r
+ * voltage than the inverting input.\r
+ * @note Comparators outputs aren't available on GPIO (outputs levels are \r
+ * only internal). The COMP1 and COMP2 outputs are connected internally \r
+ * to the EXTI Line 21 and Line 22 respectively.\r
+ * @param COMP_Selection: the selected comparator.\r
+ * This parameter can be one of the following values:\r
+ * @arg COMP_Selection_COMP1: COMP1 selected\r
+ * @arg COMP_Selection_COMP2: COMP2 selected\r
+ * @retval Returns the selected comparator output level.\r
+ */\r
+uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)\r
+{\r
+ uint8_t compout = 0x0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
+\r
+ /* Check if Comparator 1 is selected */\r
+ if(COMP_Selection == COMP_Selection_COMP1)\r
+ {\r
+ /* Check if comparator 1 output level is high */\r
+ if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)\r
+ {\r
+ /* Get Comparator 1 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_High;\r
+ }\r
+ /* comparator 1 output level is low */\r
+ else\r
+ {\r
+ /* Get Comparator 1 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_Low;\r
+ }\r
+ }\r
+ /* Comparator 2 is selected */\r
+ else\r
+ {\r
+ /* Check if comparator 2 output level is high */\r
+ if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)\r
+ {\r
+ /* Get Comparator output level */\r
+ compout = (uint8_t) COMP_OutputLevel_High;\r
+ }\r
+ /* comparator 2 output level is low */\r
+ else\r
+ {\r
+ /* Get Comparator 2 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_Low;\r
+ }\r
+ }\r
+ /* Return the comparator output level */\r
+ return (uint8_t)(compout);\r
+}\r
+\r
+/**\r
+ * @brief Close or Open the SW1 switch.\r
+ * @param NewState: new state of the SW1 switch.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note ENABLE to close the SW1 switch\r
+ * @note DISABLE to open the SW1 switch\r
+ * @retval None.\r
+ */\r
+void COMP_SW1SwitchConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Close SW1 switch */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_SW1;\r
+ }\r
+ else\r
+ {\r
+ /* Open SW1 switch */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_SW1);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Group2 Window mode control function\r
+ * @brief Window mode control function.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Window mode control function #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the window mode.\r
+ * In window mode:\r
+ * @note COMP1 inverting input is fixed to VREFINT defining the first\r
+ * threshold.\r
+ * @note COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT\r
+ * sub-multiples, PB3) defining the second threshold.\r
+ * @note COMP1 and COMP2 non inverting inputs are connected together.\r
+ * @note In window mode, only the Group 6 (PB4 or PB5) can be used as\r
+ * noninverting inputs.\r
+ * @param NewState: new state of the window mode. \r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void COMP_WindowCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the window mode */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the window mode */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Group3 Internal Reference Voltage output function\r
+ * @brief Internal Reference Voltage (VREFINT) output function.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Internal Reference Voltage (VREFINT) output function #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the output of internal reference voltage (VREFINT).\r
+ * The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or\r
+ * CH9 (PB1).\r
+ * To correctly use this function, the SYSCFG_RIIOSwitchConfig() function\r
+ * should be called after.\r
+ * @param NewState: new state of the Vrefint output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void COMP_VrefintOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the output of internal reference voltage */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the output of internal reference voltage */\r
+ COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_crc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides all the CRC firmware functions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_crc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC \r
+ * @brief CRC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the CRC Data register (DR).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CRC_ResetDR(void)\r
+{\r
+ /* Reset CRC generator */\r
+ CRC->CR = CRC_CR_RESET;\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
+ * @param Data: data word(32-bit) to compute its CRC.\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcCRC(uint32_t Data)\r
+{\r
+ CRC->DR = Data;\r
+ \r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
+ * @param pBuffer: pointer to the buffer containing the data to be computed.\r
+ * @param BufferLength: length of the buffer to be computed \r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0;\r
+ \r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ CRC->DR = pBuffer[index];\r
+ }\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current CRC value.\r
+ * @param None\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_GetCRC(void)\r
+{\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
+ * @param IDValue: 8-bit value to be stored in the ID register \r
+ * @retval None\r
+ */\r
+void CRC_SetIDRegister(uint8_t IDValue)\r
+{\r
+ CRC->IDR = IDValue;\r
+}\r
+\r
+/**\r
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register.\r
+ * @param None\r
+ * @retval 8-bit value of the ID register \r
+ */\r
+uint8_t CRC_GetIDRegister(void)\r
+{\r
+ return (CRC->IDR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dac.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Digital-to-Analog Converter (DAC) peripheral: \r
+ * + DAC channels configuration: trigger, output buffer, data format\r
+ * + DMA management \r
+ * + Interrupts and flags management\r
+\r
+ * @verbatim \r
+ * \r
+ ===============================================================================\r
+ ##### DAC Peripheral features #####\r
+ ===============================================================================\r
+ [..] The device integrates two 12-bit Digital Analog Converters that can \r
+ be used independently or simultaneously (dual mode):\r
+ (#) DAC channel1 with DAC_OUT1 (PA4) as output.\r
+ (#) DAC channel2 with DAC_OUT2 (PA5) as output.\r
+ \r
+ [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None\r
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using \r
+ DAC_SetChannel1Data()/DAC_SetChannel2Data.\r
+ \r
+ [..] Digital to Analog conversion can be triggered by:\r
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.\r
+ The used pin (GPIOx_Pin9) must be configured in input mode.\r
+ (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9 \r
+ (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...).\r
+ The timer TRGO event should be selected using TIM_SelectOutputTrigger()\r
+ (#) Software using DAC_Trigger_Software.\r
+ \r
+ [..] Each DAC channel integrates an output buffer that can be used to \r
+ reduce the output impedance, and to drive external loads directly\r
+ without having to add an external operational amplifier.\r
+ To enable, the output buffer use \r
+ DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+ \r
+ [..] Refer to the device datasheet for more details about output impedance\r
+ value with and without output buffer.\r
+ \r
+ [..] Both DAC channels can be used to generate:\r
+ (#) Noise wave using DAC_WaveGeneration_Noise\r
+ (#) Triangle wave using DAC_WaveGeneration_Triangle\r
+ \r
+ [..] Wave generation can be disabled using DAC_WaveGeneration_None.\r
+ \r
+ [..] The DAC data format can be:\r
+ (#) 8-bit right alignment using DAC_Align_8b_R\r
+ (#) 12-bit left alignment using DAC_Align_12b_L\r
+ (#) 12-bit right alignment using DAC_Align_12b_R\r
+ \r
+ [..] The analog output voltage on each DAC channel pin is determined\r
+ by the following equation: DAC_OUTx = VREF+ * DOR / 4095\r
+ with DOR is the Data Output Register.\r
+ VEF+ is the input voltage reference (refer to the device datasheet)\r
+ e.g. To set DAC_OUT1 to 0.7V, use\r
+ DAC_SetChannel1Data(DAC_Align_12b_R, 868);\r
+ Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V.\r
+ \r
+ [..] A DMA1 request can be generated when an external trigger (but not\r
+ a software trigger) occurs if DMA1 requests are enabled using\r
+ DAC_DMACmd()\r
+ [..] DMA1 requests are mapped as following:\r
+ (#) DAC channel1 is mapped on DMA1 channel3 which must be already \r
+ configured.\r
+ (#) DAC channel2 is mapped on DMA1 channel4 which must be already \r
+ configured.\r
+ \r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (+) DAC APB clock must be enabled to get write access to DAC registers using\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)\r
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.\r
+ (+) Configure the DAC channel using DAC_Init()\r
+ (+) Enable the DAC channel using DAC_Cmd()\r
+\r
+ @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dac.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC \r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* CR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r
+\r
+/* DAC Dual Channels SWTRIG masks */\r
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r
+\r
+/* DHR registers offsets */\r
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r
+\r
+/* DOR register offset */\r
+#define DOR_OFFSET ((uint32_t)0x0000002C)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DAC_Group1 DAC channels configuration\r
+ * @brief DAC channels configuration: trigger, output buffer, data format.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DAC channels configuration: trigger, output buffer, data format #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DAC_DeInit(void)\r
+{\r
+ /* Enable DAC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
+ /* Release DAC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified \r
+ * parameters in the DAC_InitStruct.\r
+ * @param DAC_Channel: the selected DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected.\r
+ * @arg DAC_Channel_2: DAC Channel2 selected.\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
+ * contains the configuration information for the specified DAC channel.\r
+ * @retval None\r
+ */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
+\r
+/*---------------------------- DAC CR Configuration --------------------------*/\r
+ /* Get the DAC CR value */\r
+ tmpreg1 = DAC->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,\r
+ mask/amplitude for wave generation */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set WAVEx bits according to DAC_WaveGeneration value */\r
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << DAC_Channel;\r
+ /* Write to DAC CR */\r
+ DAC->CR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DAC_InitStruct member with its default value.\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+/*--------------- Reset DAC init structure parameters values -----------------*/\r
+ /* Initialize the DAC_Trigger member */\r
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
+ /* Initialize the DAC_WaveGeneration member */\r
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
+ /* Initialize the DAC_OutputBuffer member */\r
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel.\r
+ * @param DAC_Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the DAC channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the DAC channel is enabled the trigger source can no more\r
+ * be modified.\r
+ * @retval None\r
+ */\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel */\r
+ DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel */\r
+ DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel software trigger.\r
+ * @param DAC_Channel: the selected DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel software trigger.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables simultaneously the two DAC channels software\r
+ * triggers.\r
+ * @param NewState: new state of the DAC channels software triggers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for both DAC channels */\r
+ DAC->SWTRIGR |= DUAL_SWTRIG_SET;\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for both DAC channels */\r
+ DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param DAC_Channel: the selected DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_Wave: Specifies the wave type to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Wave_Noise: noise wave generation\r
+ * @arg DAC_Wave_Triangle: triangle wave generation\r
+ * @param NewState: new state of the selected DAC channel wave generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note \r
+ * @retval None\r
+ */\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_WAVE(DAC_Wave)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ DAC->CR |= DAC_Wave << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected wave generation for the selected DAC channel */\r
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel1.\r
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE; \r
+ tmp += DHR12R1_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel2.\r
+ * @param DAC_Align: Specifies the data alignment for DAC channel2.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12R2_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel2 selected data holding register */\r
+ *(__IO uint32_t *)tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual channel DAC.\r
+ * @param DAC_Align: Specifies the data alignment for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
+ * holding register.\r
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
+ * holding register.\r
+ * @note In dual mode, a unique register access is required to write in both\r
+ * DAC channels at the same time.\r
+ * @retval None\r
+ */\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
+{\r
+ uint32_t data = 0, tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (DAC_Align == DAC_Align_8b_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12RD_OFFSET + DAC_Align;\r
+\r
+ /* Set the dual DAC selected data holding register */\r
+ *(__IO uint32_t *)tmp = data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC channel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ \r
+ tmp = (uint32_t) DAC_BASE ;\r
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Group2 DMA management functions\r
+ * @brief DMA management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DMA management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel DMA request.\r
+ * When enabled DMA1 is generated when an external trigger (EXTI Line9,\r
+ * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs.\r
+ * @param DAC_Channel: the selected DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which \r
+ * must be already configured. \r
+ * @retval None\r
+ */\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel DMA request */\r
+ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel DMA request */\r
+ DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC interrupts.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
+ * This parameter can be the following value:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @param NewState: new state of the specified DAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */ \r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC interrupts */\r
+ DAC->CR |= (DAC_IT << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC interrupts */\r
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC flag is set or not.\r
+ * @param DAC_Channel: thee selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to check. \r
+ * This parameter can be only of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @retval The new state of DAC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Check the status of the specified DAC flag */\r
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
+ {\r
+ /* DAC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channel's pending flags.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to clear. \r
+ * This parameter can be the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
+ * @retval None\r
+ */\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Clear the selected DAC flags */\r
+ DAC->SR = (DAC_FLAG << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC interrupt has occurred or not.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt source to check. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @retval The new state of DAC_IT (SET or RESET).\r
+ */\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT));\r
+\r
+ /* Get the DAC_IT enable bit status */\r
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
+ \r
+ /* Check the status of the specified DAC interrupt */\r
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* DAC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channel's interrupt pending bits.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @retval None\r
+ */\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ /* Clear the selected DAC interrupt pending bits */\r
+ DAC->SR = (DAC_IT << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dbgmcu.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides all the DBGMCU firmware functions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dbgmcu.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU \r
+ * @brief DBGMCU driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @param None\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t DBGMCU_GetREVID(void)\r
+{\r
+ return(DBGMCU->IDCODE >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @param None\r
+ * @retval Device identifier\r
+ */\r
+uint32_t DBGMCU_GetDEVID(void)\r
+{\r
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Configures low power mode behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the low power mode.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode\r
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode\r
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode\r
+ * @param NewState: new state of the specified low power mode in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->CR |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->CR &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the APB1 peripheral.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted\r
+ * @arg DBGMCU_RTC_STOP:\r
+ * + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when \r
+ * Core is halted.\r
+ * + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar \r
+ * and Wakeup counter stopped when Core is halted.\r
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted\r
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted\r
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is \r
+ * halted\r
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is \r
+ * halted\r
+ * @param NewState: new state of the specified APB1 peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->APB1FZ |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->APB1FZ &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the APB2 peripheral.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted\r
+ * @param NewState: new state of the specified APB2 peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->APB2FZ |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->APB2FZ &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dma.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Direct Memory Access controller (DMA): \r
+ * + Initialization and Configuration\r
+ * + Data Counter\r
+ * + Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Enable The DMA controller clock using \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or \r
+ using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.\r
+ (#) Enable and configure the peripheral to be connected to the DMA channel\r
+ (except for internal SRAM / FLASH memories: no initialization is \r
+ necessary).\r
+ (#) For a given Channel, program the Source and Destination addresses, \r
+ the transfer Direction, the Buffer Size, the Peripheral and Memory \r
+ Incrementation mode and Data Size, the Circular or Normal mode, \r
+ the channel transfer Priority and the Memory-to-Memory transfer \r
+ mode (if needed) using the DMA_Init() function.\r
+ (#) Enable the NVIC and the corresponding interrupt(s) using the function \r
+ DMA_ITConfig() if you need to use DMA interrupts.\r
+ (#) Enable the DMA channel using the DMA_Cmd() function.\r
+ (#) Activate the needed channel Request using PPP_DMACmd() function for \r
+ any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) \r
+ The function allowing this operation is provided in each PPP peripheral \r
+ driver (ie. SPI_DMACmd for SPI peripheral).\r
+ (#) Optionally, you can configure the number of data to be transferred\r
+ when the channel is disabled (ie. after each Transfer Complete event\r
+ or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().\r
+ And you can get the number of remaining data to be transferred using \r
+ the function DMA_GetCurrDataCounter() at run time (when the DMA channel is\r
+ enabled and running).\r
+ (#) To control DMA events you can use one of the following two methods:\r
+ (##) Check on DMA channel flags using the function DMA_GetFlagStatus().\r
+ (##) Use DMA interrupts through the function DMA_ITConfig() at initialization\r
+ phase and DMA_GetITStatus() function into interrupt routines in\r
+ communication phase.\r
+ After checking on a flag you should clear it using DMA_ClearFlag()\r
+ function. And after checking on an interrupt event you should \r
+ clear it using DMA_ClearITPendingBit() function.\r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dma.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA \r
+ * @brief DMA driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* DMA1 Channelx interrupt pending bit masks */\r
+#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
+#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
+\r
+/* DMA2 Channelx interrupt pending bit masks */\r
+#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+\r
+/* DMA FLAG mask */\r
+#define FLAG_MASK ((uint32_t)0x10000000)\r
+\r
+/* DMA registers Masks */\r
+#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides functions allowing to initialize the DMA channel \r
+ source and destination addresses, incrementation and data sizes, transfer \r
+ direction, buffer size, circular/normal mode selection, memory-to-memory \r
+ mode selection and channel priority value.\r
+ [..] The DMA_Init() function follows the DMA configuration procedures as described \r
+ in reference manual (RM0038).\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes the DMAy Channelx registers to their default reset\r
+ * values.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
+ * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+\r
+ /* Reset DMAy Channelx control register */\r
+ DMAy_Channelx->CCR = 0;\r
+ \r
+ /* Reset DMAy Channelx remaining bytes register */\r
+ DMAy_Channelx->CNDTR = 0;\r
+ \r
+ /* Reset DMAy Channelx peripheral address register */\r
+ DMAy_Channelx->CPAR = 0;\r
+ \r
+ /* Reset DMAy Channelx memory address register */\r
+ DMAy_Channelx->CMAR = 0;\r
+ \r
+ if (DMAy_Channelx == DMA1_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel1 */\r
+ DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel2 */\r
+ DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel3 */\r
+ DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel4 */\r
+ DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel5 */\r
+ DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel6)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel6 */\r
+ DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel7)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel7 */\r
+ DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel1 */\r
+ DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel2 */\r
+ DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel3 */\r
+ DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel4 */\r
+ DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;\r
+ }\r
+ else\r
+ { \r
+ if (DMAy_Channelx == DMA2_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel5 */\r
+ DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMAy Channelx according to the specified\r
+ * parameters in the DMA_InitStruct.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
+ * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
+ * contains the configuration information for the specified DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
+\r
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
+ /* Get the DMAy_Channelx CCR value */\r
+ tmpreg = DMAy_Channelx->CCR;\r
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
+ tmpreg &= CCR_CLEAR_MASK;\r
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
+ /* Set DIR bit according to DMA_DIR value */\r
+ /* Set CIRC bit according to DMA_Mode value */\r
+ /* Set PINC bit according to DMA_PeripheralInc value */\r
+ /* Set MINC bit according to DMA_MemoryInc value */\r
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
+ /* Set PL bits according to DMA_Priority value */\r
+ /* Set the MEM2MEM bit according to DMA_M2M value */\r
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
+\r
+ /* Write to DMAy Channelx CCR */\r
+ DMAy_Channelx->CCR = tmpreg;\r
+\r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
+\r
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CPAR */\r
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
+\r
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CMAR */\r
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DMA_InitStruct member with its default value.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+/*-------------- Reset DMA init structure parameters values ------------------*/\r
+ /* Initialize the DMA_PeripheralBaseAddr member */\r
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
+ /* Initialize the DMA_MemoryBaseAddr member */\r
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+ /* Initialize the DMA_PeripheralInc member */\r
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+ /* Initialize the DMA_MemoryInc member */\r
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
+ /* Initialize the DMA_PeripheralDataSize member */\r
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
+ /* Initialize the DMA_MemoryDataSize member */\r
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+ /* Initialize the DMA_Priority member */\r
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
+ * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param NewState: new state of the DMAy Channelx. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Group2 Data Counter functions\r
+ * @brief Data Counter functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Data Counter functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides function allowing to configure and read the buffer \r
+ size (number of data to be transferred).The DMA data counter can be written \r
+ only when the DMA channel is disabled (ie. after transfer complete event).\r
+ [..] The following function can be used to write the Channel data counter value:\r
+ (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t \r
+ DataNumber).\r
+ -@- It is advised to use this function rather than DMA_Init() in situations \r
+ where only the Data buffer needs to be reloaded.\r
+ [..] The DMA data counter can be read to indicate the number of remaining transfers \r
+ for the relative DMA channel. This counter is decremented at the end of each \r
+ data transfer and when the transfer is complete: \r
+ (+) If Normal mode is selected: the counter is set to 0.\r
+ (+) If Circular mode is selected: the counter is reloaded with the initial \r
+ value(configured before enabling the DMA channel).\r
+ [..] The following function can be used to read the Channel data counter value:\r
+ (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
+ * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DataNumber: The number of data units in the current DMAy Channelx\r
+ * transfer.\r
+ * @note This function can only be used when the DMAy_Channelx is disabled.\r
+ * @retval None.\r
+ */\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ \r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DataNumber; \r
+}\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current\r
+ * DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
+ * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @retval The number of remaining data units in the current DMAy Channelx\r
+ * transfer.\r
+ */\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ /* Return the number of remaining data units for DMAy Channelx */\r
+ return ((uint16_t)(DMAy_Channelx->CNDTR));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides functions allowing to configure the DMA Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the DMA controller events: Polling mode or Interrupt mode. \r
+ *** Polling Mode ***\r
+ ====================\r
+ [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller \r
+ number x : DMA channel number ).\r
+ (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.\r
+ (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.\r
+ (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.\r
+ (#) DMAy_FLAG_GLx : to indicate that at least one of the events described \r
+ above occurred.\r
+ -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the \r
+ same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).\r
+ [..]In this Mode it is advised to use the following functions:\r
+ (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+ (+) void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+\r
+ *** Interrupt Mode ***\r
+ ======================\r
+ [..] Each DMA channel can be managed through 4 Interrupts:\r
+ (+) Interrupt Source\r
+ (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete \r
+ event.\r
+ (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete \r
+ event.\r
+ (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.\r
+ (##) DMA_IT_GL : to indicate that at least one of the interrupts described \r
+ above occurred.\r
+ -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of \r
+ the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).\r
+ [..]In this Mode it is advised to use the following functions:\r
+ (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, \r
+ FunctionalState NewState);\r
+ (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+ (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx interrupts.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be \r
+ * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
+ * or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @param NewState: new state of the specified DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
+ * @param DMAy_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
+ * \r
+ * @note\r
+ * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags \r
+ * relative to the same channel is set (Transfer Complete, Half-transfer \r
+ * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or \r
+ * DMAy_FLAG_TEx). \r
+ * \r
+ * @retval The new state of DMAy_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));\r
+\r
+ /* Calculate the used DMAy */\r
+ if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR;\r
+ }\r
+ else\r
+ {\r
+ /* Get DMA2 ISR register value */\r
+ tmpreg = DMA2->ISR;\r
+ }\r
+\r
+ /* Check the status of the specified DMAy flag */\r
+ if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* DMAy_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMAy_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the DMAy_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's pending flags.\r
+ * @param DMAy_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. \r
+ * \r
+ * @note\r
+ * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags\r
+ * relative to the same channel (Transfer Complete, Half-transfer Complete and \r
+ * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). \r
+ * \r
+ * @retval None\r
+ */\r
+void DMA_ClearFlag(uint32_t DMAy_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));\r
+\r
+ if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMAy flags */\r
+ DMA1->IFCR = DMAy_FLAG;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the selected DMAy flags */\r
+ DMA2->IFCR = DMAy_FLAG;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
+ * @param DMAy_IT: specifies the DMAy interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. \r
+ * \r
+ * @note\r
+ * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other \r
+ * interrupts relative to the same channel is set (Transfer Complete, \r
+ * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, \r
+ * DMAy_IT_HTx or DMAy_IT_TEx). \r
+ * \r
+ * @retval The new state of DMAy_IT (SET or RESET).\r
+ */\r
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_IT(DMAy_IT));\r
+\r
+ /* Calculate the used DMAy */\r
+ if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR;\r
+ }\r
+ else\r
+ {\r
+ /* Get DMA2 ISR register value */\r
+ tmpreg = DMA2->ISR;\r
+ }\r
+ \r
+ /* Check the status of the specified DMAy interrupt */\r
+ if ((tmpreg & DMAy_IT) != (uint32_t)RESET)\r
+ {\r
+ /* DMAy_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMAy_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMAy_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's interrupt pending bits.\r
+ * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. \r
+ * \r
+ * @note\r
+ * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other \r
+ * interrupts relative to the same channel (Transfer Complete, Half-transfer \r
+ * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and \r
+ * DMAy_IT_TEx). \r
+ * \r
+ * @retval None\r
+ */\r
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_IT(DMAy_IT));\r
+\r
+ /* Calculate the used DMAy */\r
+ if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMAy interrupt pending bits */\r
+ DMA1->IFCR = DMAy_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the selected DMAy interrupt pending bits */\r
+ DMA2->IFCR = DMAy_IT;\r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_exti.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the EXTI peripheral: \r
+ * + Initialization and Configuration\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim \r
+ ============================================================================== \r
+ ##### EXTI features ##### \r
+ ============================================================================== \r
+ [..] External interrupt/event lines are mapped as following:\r
+ (#) All available GPIO pins are connected to the 16 external \r
+ interrupt/event lines from EXTI0 to EXTI15.\r
+ (#) EXTI line 16 is connected to the PVD output.\r
+ (#) EXTI line 17 is connected to the RTC Alarm event.\r
+ (#) EXTI line 18 is connected to the USB Device FS wakeup event.\r
+ (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.\r
+ (#) EXTI line 20 is connected to the RTC Wakeup event.\r
+ (#) EXTI line 21 is connected to the Comparator 1 wakeup event.\r
+ (#) EXTI line 22 is connected to the Comparator 2 wakeup event.\r
+ (#) EXTI line 23 is connected to the Comparator channel acquisition wakeup event.\r
+ \r
+ \r
+ ##### How to use this driver ##### \r
+ ============================================================================== \r
+ [..] In order to use an I/O pin as an external interrupt source, follow\r
+ steps below:\r
+ (#) Configure the I/O in input mode using GPIO_Init()\r
+ (#) Select the input source pin for the EXTI line using \r
+ SYSCFG_EXTILineConfig()\r
+ (#) Select the mode(interrupt, event) and configure the trigger \r
+ selection (Rising, falling or both) using EXTI_Init()\r
+ (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()\r
+ [..]\r
+ (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx\r
+ registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_exti.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI \r
+ * @brief EXTI driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->IMR = 0x00000000;\r
+ EXTI->EMR = 0x00000000;\r
+ EXTI->RTSR = 0x00000000; \r
+ EXTI->FTSR = 0x00000000; \r
+ EXTI->PR = 0x00FFFFFF;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the EXTI peripheral according to the specified\r
+ * parameters in the EXTI_InitStruct.\r
+ * EXTI_Line specifies the EXTI line (EXTI0....EXTI23).\r
+ * EXTI_Mode specifies which EXTI line is used as interrupt or an event.\r
+ * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt\r
+ * pending bit will be set.\r
+ * EXTI_LineCmd controls (Enable/Disable) the EXTI line.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+ * that contains the configuration information for the EXTI peripheral.\r
+ * @retval None\r
+ */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ \r
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ /* Disable the selected external lines */\r
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each EXTI_InitStruct member with its reset value.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param EXTI_Line: specifies the EXTI line on which the software interrupt\r
+ * will be generated.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..23).\r
+ * @retval None\r
+ */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Group2 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ============================================================================== \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param EXTI_Line: specifies the EXTI line flag to check.\r
+ * This parameter can be:\r
+ * EXTI_Linex: External interrupt line x where x(0..23).\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..23).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param EXTI_Line: specifies the EXTI line to check.\r
+ * This parameter can be:\r
+ * EXTI_Linex: External interrupt line x where x(0..23).\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ enablestatus = EXTI->IMR & EXTI_Line;\r
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param EXTI_Line: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..23).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides all the Flash firmware functions. These functions \r
+ * can be executed from Internal FLASH or Internal SRAM memories. \r
+ * The functions that should be called from SRAM are defined inside \r
+ * the "stm32l1xx_flash_ramfunc.c" file.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the FLASH peripheral:\r
+ * + FLASH Interface configuration\r
+ * + FLASH Memory Programming\r
+ * + DATA EEPROM Programming\r
+ * + Option Bytes Programming\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to configure and program the Flash \r
+ memory of all STM32L1xx devices.\r
+ [..] These functions are split in 5 groups:\r
+ (#) FLASH Interface configuration functions: this group includes \r
+ the management of following features:\r
+ (++) Set the latency.\r
+ (++) Enable/Disable the prefetch buffer.\r
+ (++) Enable/Disable the 64 bit Read Access. \r
+ (++) Enable/Disable the RUN PowerDown mode.\r
+ (++) Enable/Disable the SLEEP PowerDown mode. \r
+ \r
+ (#) FLASH Memory Programming functions: this group includes all \r
+ needed functions to erase and program the main memory:\r
+ (++) Lock and Unlock the Flash interface.\r
+ (++) Erase function: Erase Page.\r
+ (++) Program functions: Fast Word and Half Page(should be \r
+ executed from internal SRAM).\r
+ \r
+ (#) DATA EEPROM Programming functions: this group includes all \r
+ needed functions to erase and program the DATA EEPROM memory:\r
+ (++) Lock and Unlock the DATA EEPROM interface.\r
+ (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase \r
+ (++) Double Word (should be executed from internal SRAM).\r
+ (++) Program functions: Fast Program Byte, Fast Program Half-Word, \r
+ FastProgramWord, Program Byte, Program Half-Word, \r
+ Program Word and Program Double-Word (should be executed \r
+ from internal SRAM).\r
+ \r
+ (#) FLASH Option Bytes Programming functions: this group includes \r
+ all needed functions to:\r
+ (++) Lock and Unlock the Flash Option bytes.\r
+ (++) Set/Reset the write protection.\r
+ (++) Set the Read protection Level.\r
+ (++) Set the BOR level.\r
+ (++) rogram the user option Bytes.\r
+ (++) Launch the Option Bytes loader.\r
+ (++) Get the Write protection.\r
+ (++) Get the read protection status.\r
+ (++) Get the BOR level.\r
+ (++) Get the user option bytes.\r
+ \r
+ (#) FLASH Interrupts and flag management functions: this group \r
+ includes all needed functions to:\r
+ (++) Enable/Disable the flash interrupt sources.\r
+ (++) Get flags status.\r
+ (++) Clear flags.\r
+ (++) Get Flash operation status.\r
+ (++) Wait for last flash operation.\r
+\r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_flash.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+ \r
+/* FLASH Mask */\r
+#define WRP01_MASK ((uint32_t)0x0000FFFF)\r
+#define WRP23_MASK ((uint32_t)0xFFFF0000)\r
+#define WRP45_MASK ((uint32_t)0x0000FFFF)\r
+#define WRP67_MASK ((uint32_t)0xFFFF0000)\r
+#define WRP89_MASK ((uint32_t)0x0000FFFF)\r
+#define WRP1011_MASK ((uint32_t)0xFFFF0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions\r
+ * @brief FLASH Interface configuration functions \r
+ *\r
+@verbatim \r
+ ============================================================================== \r
+ ##### FLASH Interface configuration functions #####\r
+ ==============================================================================\r
+\r
+ [..] FLASH_Interface configuration_Functions, includes the following functions:\r
+ (+) void FLASH_SetLatency(uint32_t FLASH_Latency):\r
+ [..] To correctly read data from Flash memory, the number of wait states (LATENCY) \r
+ must be correctly programmed according to the frequency of the CPU clock \r
+ (HCLK) and the supply voltage of the device.\r
+ [..] \r
+ ----------------------------------------------------------------\r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------|\r
+ | (Latency) | voltage range | voltage range |\r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------|\r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |-------------- |----------------|---------------|---------------|\r
+ |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |---------------|----------------|---------------|---------------|\r
+ |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
+ ----------------------------------------------------------------\r
+ [..]\r
+ (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+ (+) void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
+ (+) void FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
+ (+) void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
+ (+) void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+ [..] \r
+ Here below the allowed configuration of Latency, 64Bit access and prefetch buffer\r
+ [..] \r
+ --------------------------------------------------------------------------------\r
+ | | ACC64 = 0 | ACC64 = 1 |\r
+ | Latency |----------------|---------------|---------------|---------------|\r
+ | | PRFTEN = 0 | PRFTEN = 1 | PRFTEN = 0 | PRFTEN = 1 |\r
+ |---------------|----------------|---------------|---------------|---------------|\r
+ |0WS(1CPU cycle)| YES | NO | YES | YES |\r
+ |---------------|----------------|---------------|---------------|---------------|\r
+ |1WS(2CPU cycle)| NO | NO | YES | YES |\r
+ --------------------------------------------------------------------------------\r
+ [..]\r
+ All these functions don't need the unlock sequence.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the code latency value.\r
+ * @param FLASH_Latency: specifies the FLASH Latency value.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle.\r
+ * @arg FLASH_Latency_1: FLASH One Latency cycle.\r
+ * @retval None\r
+ */\r
+void FLASH_SetLatency(uint32_t FLASH_Latency)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
+ \r
+ /* Read the ACR register */\r
+ tmpreg = FLASH->ACR; \r
+ \r
+ /* Sets the Latency value */\r
+ tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));\r
+ tmpreg |= FLASH_Latency;\r
+ \r
+ /* Write the ACR register */\r
+ FLASH->ACR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Prefetch Buffer.\r
+ * @param NewState: new state of the FLASH prefetch buffer.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables read access to flash by 64 bits.\r
+ * @param NewState: new state of the FLASH read access mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note If this bit is set, the Read access 64 bit is used.\r
+ * If this bit is reset, the Read access 32 bit is used.\r
+ * @note This bit cannot be written at the same time as the LATENCY and \r
+ * PRFTEN bits.\r
+ * To reset this bit, the LATENCY should be zero wait state and the \r
+ * prefetch off.\r
+ * @retval None\r
+ */\r
+void FLASH_ReadAccess64Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->ACR |= FLASH_ACR_ACC64;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the power down mode during Sleep mode.\r
+ * @note This function is used to power down the FLASH when the system is in SLEEP LP mode.\r
+ * @param NewState: new state of the power down mode during sleep mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */\r
+ FLASH->ACR |= FLASH_ACR_SLEEP_PD;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions\r
+ * @brief FLASH Memory Programming functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FLASH Memory Programming functions ##### \r
+ ==============================================================================\r
+\r
+ [..] The FLASH Memory Programming functions, includes the following functions:\r
+ (+) void FLASH_Unlock(void);\r
+ (+) void FLASH_Lock(void);\r
+ (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+ (+) FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
+ \r
+ [..] Any operation of erase or program should follow these steps:\r
+ (#) Call the FLASH_Unlock() function to enable the flash control register and \r
+ program memory access.\r
+ (#) Call the desired function to erase page or program data.\r
+ (#) Call the FLASH_Lock() to disable the flash program memory access \r
+ (recommended to protect the FLASH memory against possible unwanted operation).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the FLASH control register and program memory access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)\r
+ {\r
+ /* Unlocking the data memory and FLASH_PECR register access */\r
+ DATA_EEPROM_Unlock();\r
+ \r
+ /* Unlocking the program memory access */\r
+ FLASH->PRGKEYR = FLASH_PRGKEY1;\r
+ FLASH->PRGKEYR = FLASH_PRGKEY2; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the Program memory access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Lock(void)\r
+{\r
+ /* Set the PRGLOCK Bit to lock the program memory access */\r
+ FLASH->PECR |= FLASH_PECR_PRGLOCK;\r
+}\r
+\r
+/**\r
+ * @brief Erases a specified page in program memory.\r
+ * @note To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param Page_Address: The page address in program memory to be erased.\r
+ * @note A Page is erased in the Program memory only if the address to load \r
+ * is the start address of a page (multiple of 256 bytes).\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to erase the page */\r
+\r
+ /* Set the ERASE bit */\r
+ FLASH->PECR |= FLASH_PECR_ERASE;\r
+\r
+ /* Set PROG bit */\r
+ FLASH->PECR |= FLASH_PECR_PROG;\r
+ \r
+ /* Write 00000000h to the first word of the program page to erase */\r
+ *(__IO uint32_t *)Page_Address = 0x00000000;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ /* If the erase operation is completed, disable the ERASE and PROG bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); \r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in program memory.\r
+ * @note To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access\r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new word */ \r
+ *(__IO uint32_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Group3 DATA EEPROM Programming functions\r
+ * @brief DATA EEPROM Programming functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### DATA EEPROM Programming functions ##### \r
+ =============================================================================== \r
+ \r
+ [..] The DATA_EEPROM Programming_Functions, includes the following functions:\r
+ (+) void DATA_EEPROM_Unlock(void);\r
+ (+) void DATA_EEPROM_Lock(void);\r
+ (+) FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);\r
+ (+) FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);\r
+ (+) FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
+ (+) FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
+ (+) FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
+ (+) FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
+ (+) FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
+ (+) FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+ (+) FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
+ \r
+ [..] Any operation of erase or program should follow these steps:\r
+ (#) Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access\r
+ and Flash program erase control register access.\r
+ (#) Call the desired function to erase or program data.\r
+ (#) Call the DATA_EEPROM_Lock() to disable the data EEPROM access\r
+ and Flash program erase control register access(recommended\r
+ to protect the DATA_EEPROM against possible unwanted operation).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the data memory and FLASH_PECR register access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)\r
+ { \r
+ /* Unlocking the Data memory and FLASH_PECR register access*/\r
+ FLASH->PEKEYR = FLASH_PEKEY1;\r
+ FLASH->PEKEYR = FLASH_PEKEY2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the Data memory and FLASH_PECR register access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_Lock(void)\r
+{\r
+ /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */\r
+ FLASH->PECR |= FLASH_PECR_PELOCK;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables DATA EEPROM fixed Time programming (2*Tprog).\r
+ * @param NewState: new state of the DATA EEPROM fixed Time programming mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;\r
+ }\r
+ else\r
+ {\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Erase a byte in data memory.\r
+ * @param Address: specifies the address to be erased.\r
+ * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP \r
+ * density devices.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Write "00h" to valid address in the data memory" */\r
+ *(__IO uint8_t *) Address = (uint8_t)0x00;\r
+ }\r
+ \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erase a halfword in data memory.\r
+ * @param Address: specifies the address to be erased.\r
+ * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP \r
+ * density devices.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Write "0000h" to valid address in the data memory" */\r
+ *(__IO uint16_t *) Address = (uint16_t)0x0000;\r
+ }\r
+ \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erase a word in data memory.\r
+ * @param Address: specifies the address to be erased.\r
+ * @note For STM32L1XX_MD, A data memory word is erased in the data memory only \r
+ * if the address to load is the start address of a word (multiple of a word).\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Write "00000000h" to valid address in the data memory" */\r
+ *(__IO uint32_t *) Address = 0x00000000;\r
+ }\r
+ \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a Byte at a specified address in data memory.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased.\r
+ * @retval FLASH Status: The returned value can be:\r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+#endif\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+\r
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
+ if(Data != (uint8_t)0x00) \r
+ {\r
+ /* If the previous operation is completed, proceed to write the new Data */\r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+ else\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr;\r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);\r
+ } \r
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)\r
+ /* If the previous operation is completed, proceed to write the new Data */\r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+#endif \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a half word at a specified address in data memory.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+#endif\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+\r
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
+ if(Data != (uint16_t)0x0000) \r
+ {\r
+ /* If the previous operation is completed, proceed to write the new data */\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+ else\r
+ {\r
+ if((Address & 0x3) != 0x3)\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);\r
+ }\r
+ else\r
+ {\r
+ DATA_EEPROM_FastProgramByte(Address, 0x00);\r
+ DATA_EEPROM_FastProgramByte(Address + 1, 0x00);\r
+ }\r
+ }\r
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)\r
+ /* If the previous operation is completed, proceed to write the new data */\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+#endif\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in data memory.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to the data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */ \r
+ *(__IO uint32_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a Byte at a specified address in data memory without erase.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming.\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+#endif\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
+ if(Data != (uint8_t) 0x00)\r
+ { \r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ }\r
+ else\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);\r
+ }\r
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)\r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+#endif\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a half word at a specified address in data memory without erase.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be:\r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+#endif\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)\r
+ if(Data != (uint16_t)0x0000)\r
+ {\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+ else\r
+ {\r
+ if((Address & 0x3) != 0x3)\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);\r
+ }\r
+ else\r
+ {\r
+ DATA_EEPROM_FastProgramByte(Address, 0x00);\r
+ DATA_EEPROM_FastProgramByte(Address + 1, 0x00);\r
+ }\r
+ }\r
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+#endif\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in data memory without erase.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming.\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be:\r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ *(__IO uint32_t *)Address = Data;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group4 Option Bytes Programming functions\r
+ * @brief Option Bytes Programming functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Option Bytes Programming functions ##### \r
+ ============================================================================== \r
+\r
+ [..] The FLASH_Option Bytes Programming_functions, includes the following functions:\r
+ (+) void FLASH_OB_Unlock(void);\r
+ (+) void FLASH_OB_Lock(void);\r
+ (+) void FLASH_OB_Launch(void);\r
+ (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
+ (+) FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);\r
+ (+) FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState); \r
+ (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+ (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+ (+) FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
+ (+) uint8_t FLASH_OB_GetUser(void);\r
+ (+) uint32_t FLASH_OB_GetWRP(void);\r
+ (+) uint32_t FLASH_OB_GetWRP1(void);\r
+ (+) uint32_t FLASH_OB_GetWRP2(void); \r
+ (+) FlagStatus FLASH_OB_GetRDP(void);\r
+ (+) uint8_t FLASH_OB_GetBOR(void);\r
+ (+) FLASH_Status FLASH_OB_BootConfig(uint16_t OB_BOOT);\r
+ \r
+ [..] Any operation of erase or program should follow these steps:\r
+ (#) Call the FLASH_OB_Unlock() function to enable the Flash option control \r
+ register access.\r
+ (#) Call one or several functions to program the desired option bytes.\r
+ (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable \r
+ the desired sector write protection.\r
+ (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level.\r
+ (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure \r
+ the user option Bytes: IWDG, STOP and the Standby.\r
+ (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level.\r
+ (++) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes .\r
+ (#) Once all needed option bytes to be programmed are correctly written, call the\r
+ FLASH_OB_Launch(void) function to launch the Option Bytes programming process.\r
+ (#) Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended\r
+ to protect the option Bytes against possible unwanted operations).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the option bytes block access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)\r
+ {\r
+ /* Unlocking the data memory and FLASH_PECR register access */\r
+ DATA_EEPROM_Unlock();\r
+ \r
+ /* Unlocking the option bytes block access */\r
+ FLASH->OPTKEYR = FLASH_OPTKEY1;\r
+ FLASH->OPTKEYR = FLASH_OPTKEY2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the option bytes block access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Lock(void)\r
+{\r
+ /* Set the OPTLOCK Bit to lock the option bytes block access */\r
+ FLASH->PECR |= FLASH_PECR_OPTLOCK;\r
+}\r
+\r
+/**\r
+ * @brief Launch the option byte loading.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Launch(void)\r
+{\r
+ /* Set the OBL_Launch bit to lauch the option byte loading */\r
+ FLASH->PECR |= FLASH_PECR_OBL_LAUNCH;\r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages.\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param OB_WRP: specifies the address of the pages to be write protected.\r
+ * This parameter can be:\r
+ * @param value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511\r
+ * @param OB_WRP_AllPages\r
+ * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)\r
+{\r
+ uint32_t WRP01_Data = 0, WRP23_Data = 0;\r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(OB_WRP));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01));\r
+ WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23))); \r
+ tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);\r
+ OB->WRP01 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data);\r
+ OB->WRP23 = tmp2; \r
+ } \r
+ \r
+ else\r
+ {\r
+ WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));\r
+ WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); \r
+\r
+ tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);\r
+ OB->WRP01 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data);\r
+ OB->WRP23 = tmp2;\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+\r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages.\r
+ * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP \r
+ * density devices.\r
+ * To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param OB_WRP1: specifies the address of the pages to be write protected.\r
+ * This parameter can be:\r
+ * @arg value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023\r
+ * @arg OB_WRP_AllPages\r
+ * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState)\r
+{\r
+ uint32_t WRP45_Data = 0, WRP67_Data = 0;\r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(OB_WRP1));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ WRP45_Data = (uint16_t)(((OB_WRP1 & WRP45_MASK) | OB->WRP45));\r
+ WRP67_Data = (uint16_t)((((OB_WRP1 & WRP67_MASK)>>16 | OB->WRP67))); \r
+ tmp1 = (uint32_t)(~(WRP45_Data) << 16)|(WRP45_Data);\r
+ OB->WRP45 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)(~(WRP67_Data) << 16)|(WRP67_Data);\r
+ OB->WRP67 = tmp2; \r
+ } \r
+ \r
+ else\r
+ {\r
+ WRP45_Data = (uint16_t)(~OB_WRP1 & (WRP45_MASK & OB->WRP45));\r
+ WRP67_Data = (uint16_t)((((~OB_WRP1 & WRP67_MASK)>>16 & OB->WRP67))); \r
+\r
+ tmp1 = (uint32_t)((~WRP45_Data) << 16)|(WRP45_Data);\r
+ OB->WRP45 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)((~WRP67_Data) << 16)|(WRP67_Data);\r
+ OB->WRP67 = tmp2;\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+\r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages.\r
+ * @note This function can be used only for STM32L1XX_HD density devices.\r
+ * To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param OB_WRP2: specifies the address of the pages to be write protected.\r
+ * This parameter can be:\r
+ * @arg value between OB_WRP_Pages1024to1039 and OB_WRP_Pages1520to1535\r
+ * @arg OB_WRP_AllPages\r
+ * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState)\r
+{\r
+ uint32_t WRP89_Data = 0, WRP1011_Data = 0;\r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(OB_WRP2));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ WRP89_Data = (uint16_t)(((OB_WRP2 & WRP89_MASK) | OB->WRP89));\r
+ WRP1011_Data = (uint16_t)((((OB_WRP2 & WRP1011_MASK)>>16 | OB->WRP1011))); \r
+ tmp1 = (uint32_t)(~(WRP89_Data) << 16)|(WRP89_Data);\r
+ OB->WRP89 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)(~(WRP1011_Data) << 16)|(WRP1011_Data);\r
+ OB->WRP1011 = tmp2; \r
+ } \r
+ \r
+ else\r
+ {\r
+ WRP89_Data = (uint16_t)(~OB_WRP2 & (WRP89_MASK & OB->WRP89));\r
+ WRP1011_Data = (uint16_t)((((~OB_WRP2 & WRP1011_MASK)>>16 & OB->WRP1011))); \r
+\r
+ tmp1 = (uint32_t)((~WRP89_Data) << 16)|(WRP89_Data);\r
+ OB->WRP89 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)((~WRP1011_Data) << 16)|(WRP1011_Data);\r
+ OB->WRP1011 = tmp2;\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+\r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the read out protection.\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param FLASH_ReadProtection_Level: specifies the read protection level. \r
+ * This parameter can be:\r
+ * @arg OB_RDP_Level_0: No protection\r
+ * @arg OB_RDP_Level_1: Read protection of the memory\r
+ * @arg OB_RDP_Level_2: Chip protection\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint8_t tmp1 = 0;\r
+ uint32_t tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_RDP(OB_RDP));\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* calculate the option byte to write */\r
+ tmp1 = (uint8_t)(~(OB_RDP ));\r
+ tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP));\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* program read protection level */\r
+ OB->RDP = tmp2;\r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Read protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param OB_IWDG: Selects the WDG mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software WDG selected\r
+ * @arg OB_IWDG_HW: Hardware WDG selected\r
+ * @param OB_STOP: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param OB_STDBY: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = (FLASH->OBR & 0x000F0000) >> 16;\r
+ \r
+ /* Calculate the user option byte to write */ \r
+ tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10));\r
+ tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Write the User Option Byte */ \r
+ OB->USER = tmp; \r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH brownout reset threshold level Option Byte.\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param OB_BOR: Selects the brownout reset threshold level.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD \r
+ * power supply reaches the PDR(Power Down Reset) threshold (1.5V)\r
+ * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply\r
+ * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply\r
+ * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply\r
+ * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply\r
+ * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOR_LEVEL(OB_BOR));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = (FLASH->OBR & 0x00F00000) >> 16;\r
+ \r
+ /* Calculate the option byte to write */\r
+ tmp = (uint32_t)~(OB_BOR | tmp1)<<16;\r
+ tmp |= (OB_BOR | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Write the BOR Option Byte */ \r
+ OB->USER = tmp; \r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Configures to boot from Bank1 or Bank2.\r
+ * @note This function can be used only for STM32L1XX_HD density devices.\r
+ * To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param OB_BOOT: select the FLASH Bank to boot from.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash\r
+ * position and this parameter is selected the device will boot from Bank2 or Bank1,\r
+ * depending on the activation of the bank. The active banks are checked in\r
+ * the following order: Bank2, followed by Bank1.\r
+ * The active bank is recognized by the value programmed at the base address\r
+ * of the respective bank (corresponding to the initial stack pointer value\r
+ * in the interrupt vector table).\r
+ * @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash\r
+ * position and this parameter is selected the device will boot from Bank1(Default).\r
+ * For more information, please refer to AN2606 from www.st.com. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOOT_BANK(OB_BOOT));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = (FLASH->OBR & 0x007F0000) >> 16;\r
+ \r
+ /* Calculate the option byte to write */\r
+ tmp = (uint32_t)~(OB_BOOT | tmp1)<<16;\r
+ tmp |= (OB_BOOT | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Write the BOOT Option Byte */ \r
+ OB->USER = tmp; \r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH User Option Bytes values.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes.\r
+ */\r
+uint8_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return (uint8_t)(FLASH->OBR >> 20);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes value.\r
+ * @param None\r
+ * @retval The FLASH Write Protection Option Bytes value.\r
+ */\r
+uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes value.\r
+ * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP \r
+ * density devices.\r
+ * @param None\r
+ * @retval The FLASH Write Protection Option Bytes value.\r
+ */\r
+uint32_t FLASH_OB_GetWRP1(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR1);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes value.\r
+ * @note This function can be used only for STM32L1XX_HD density devices.\r
+ * @param None\r
+ * @retval The FLASH Write Protection Option Bytes value.\r
+ */\r
+uint32_t FLASH_OB_GetWRP2(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR2);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Read out Protection Status is set or not.\r
+ * @param None\r
+ * @retval FLASH ReadOut Protection Status(SET or RESET).\r
+ */\r
+FlagStatus FLASH_OB_GetRDP(void)\r
+{\r
+ FlagStatus readstatus = RESET;\r
+ \r
+ if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0)\r
+ {\r
+ readstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ readstatus = RESET;\r
+ }\r
+ return readstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH BOR level.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes.\r
+ */\r
+uint8_t FLASH_OB_GetBOR(void)\r
+{\r
+ /* Return the BOR level */\r
+ return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group5 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified FLASH interrupts.\r
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or \r
+ * disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP: FLASH end of programming Interrupt\r
+ * @arg FLASH_IT_ERR: FLASH Error Interrupt\r
+ * @retval None \r
+ */\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->PECR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->PECR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FLASH flag is set or not.\r
+ * @param FLASH_FLAG: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
+ * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode\r
+ * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
+ * @arg FLASH_FLAG_SIZERR: FLASH size error flag\r
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag\r
+ * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag\r
+ * @retval The new state of FLASH_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));\r
+\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the new state of FLASH_FLAG (SET or RESET) */\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the FLASH's pending flags.\r
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r
+ * @arg FLASH_FLAG_SIZERR: FLASH size error flag \r
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag\r
+ * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag\r
+ * @retval None\r
+ */\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.\r
+ */\r
+FLASH_Status FLASH_GetStatus(void)\r
+{\r
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ FLASHstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
+ { \r
+ FLASHstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)\r
+ {\r
+ FLASHstatus = FLASH_ERROR_PROGRAM; \r
+ }\r
+ else\r
+ {\r
+ FLASHstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the FLASH Status */\r
+ return FLASHstatus;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH programming Timeout.\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ __IO FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the FLASH Status */\r
+ status = FLASH_GetStatus();\r
+ \r
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetStatus();\r
+ Timeout--;\r
+ }\r
+ \r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash_ramfunc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides all the Flash firmware functions which should be\r
+ * executed from the internal SRAM. This file should be placed in \r
+ * internal SRAM. \r
+ * Other FLASH memory functions that can be used from the FLASH are \r
+ * defined in the "stm32l1xx_flash.c" file. \r
+@verbatim\r
+\r
+ *** ARM Compiler ***\r
+ --------------------\r
+ [..] RAM functions are defined using the toolchain options. \r
+ Functions that are be executed in RAM should reside in a separate\r
+ source module. Using the 'Options for File' dialog you can simply change\r
+ the 'Code / Const' area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the \r
+ Options for Target' dialog.\r
+\r
+ *** ICCARM Compiler ***\r
+ -----------------------\r
+ [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
+\r
+ *** GNU Compiler ***\r
+ --------------------\r
+ [..] RAM functions are defined using a specific toolchain attribute\r
+ "__attribute__((section(".data")))".\r
+\r
+ *** TASKING Compiler ***\r
+ ------------------------\r
+ [..] RAM functions are defined using a specific toolchain pragma. This \r
+ pragma is defined inside this file.\r
+\r
+@endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_flash.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static __RAM_FUNC GetStatus(void);\r
+static __RAM_FUNC WaitForLastOperation(uint32_t Timeout);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup FLASH_Group1\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */ \r
+#if defined ( __TASKING__ )\r
+#pragma section_code_init on\r
+#endif\r
+\r
+/**\r
+ * @brief Enable or disable the power down mode during RUN mode.\r
+ * @note This function can be used only when the user code is running from Internal SRAM.\r
+ * @param NewState: new state of the power down mode during RUN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Unlock the RUN_PD bit */\r
+ FLASH->PDKEYR = FLASH_PDKEY1;\r
+ FLASH->PDKEYR = FLASH_PDKEY2;\r
+ \r
+ /* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;\r
+\r
+ if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD)\r
+ {\r
+ status = FLASH_ERROR_PROGRAM;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */\r
+ FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);\r
+ }\r
+\r
+ /* Return the Write Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Group2\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Erases a specified 2 page in program memory in parallel.\r
+ * @note This function can be used only for STM32L1XX_HD density devices.\r
+ * To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @param Page_Address1: The page address in program memory to be erased in \r
+ * the first Bank (BANK1). This parameter should be between 0x08000000\r
+ * and 0x0802FF00.\r
+ * @param Page_Address2: The page address in program memory to be erased in \r
+ * the second Bank (BANK2). This parameter should be between 0x08030000\r
+ * and 0x0805FF00.\r
+ * @note A Page is erased in the Program memory only if the address to load \r
+ * is the start address of a page (multiple of 256 bytes).\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to erase the page */\r
+\r
+ /* Set the PARALLBANK bit */\r
+ FLASH->PECR |= FLASH_PECR_PARALLBANK;\r
+ \r
+ /* Set the ERASE bit */\r
+ FLASH->PECR |= FLASH_PECR_ERASE;\r
+\r
+ /* Set PROG bit */\r
+ FLASH->PECR |= FLASH_PECR_PROG;\r
+ \r
+ /* Write 00000000h to the first word of the first program page to erase */\r
+ *(__IO uint32_t *)Page_Address1 = 0x00000000;\r
+ /* Write 00000000h to the first word of the second program page to erase */ \r
+ *(__IO uint32_t *)Page_Address2 = 0x00000000; \r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK); \r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a half page in program memory.\r
+ * @param Address: specifies the address to be written.\r
+ * @param pBuffer: pointer to the buffer containing the data to be written to \r
+ * the half page.\r
+ * @note To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @note Half page write is possible only from SRAM.\r
+ * @note If there are more than 32 words to write, after 32 words another \r
+ * Half Page programming operation starts and has to be finished.\r
+ * @note A half page is written to the program memory only if the first \r
+ * address to load is the start address of a half page (multiple of 128 \r
+ * bytes) and the 31 remaining words to load are in the same half page.\r
+ * @note During the Program memory half page write all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.).\r
+ * @note If a PGAERR is set during a Program memory half page write, the \r
+ * complete write operation is aborted. Software should then reset the \r
+ * FPRG and PROG/DATA bits and restart the write operation from the \r
+ * beginning.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer)\r
+{\r
+ uint32_t count = 0; \r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) \r
+ This bit prevents the interruption of multicycle instructions and therefore \r
+ will increase the interrupt latency. of Cortex-M3. */\r
+ SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new \r
+ half page */\r
+ FLASH->PECR |= FLASH_PECR_FPRG;\r
+ FLASH->PECR |= FLASH_PECR_PROG;\r
+ \r
+ /* Write one half page directly with 32 different words */\r
+ while(count < 32)\r
+ {\r
+ *(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++);\r
+ count ++; \r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* if the write operation is completed, disable the PROG and FPRG bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
+ }\r
+\r
+ SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;\r
+ \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs 2 half page in program memory in parallel.\r
+ * @param Address1: specifies the first address to be written in the first bank \r
+ * (BANK1). This parameter should be between 0x08000000 and 0x0802FF80.\r
+ * @param pBuffer1: pointer to the buffer containing the data to be written \r
+ * to the first half page in the first bank.\r
+ * @param Address2: specifies the second address to be written in the second bank\r
+ * (BANK2). This parameter should be between 0x08030000 and 0x0805FF80.\r
+ * @param pBuffer2: pointer to the buffer containing the data to be written \r
+ * to the second half page in the second bank.\r
+ * @note This function can be used only for STM32L1XX_HD density devices.\r
+ * @note To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation).\r
+ * @note Half page write is possible only from SRAM.\r
+ * @note If there are more than 32 words to write, after 32 words another \r
+ * Half Page programming operation starts and has to be finished.\r
+ * @note A half page is written to the program memory only if the first \r
+ * address to load is the start address of a half page (multiple of 128 \r
+ * bytes) and the 31 remaining words to load are in the same half page.\r
+ * @note During the Program memory half page write all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.).\r
+ * @note If a PGAERR is set during a Program memory half page write, the \r
+ * complete write operation is aborted. Software should then reset the \r
+ * FPRG and PROG/DATA bits and restart the write operation from the \r
+ * beginning.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)\r
+{\r
+ uint32_t count = 0; \r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) \r
+ This bit prevents the interruption of multicycle instructions and therefore \r
+ will increase the interrupt latency. of Cortex-M3. */\r
+ SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new \r
+ half page */\r
+ FLASH->PECR |= FLASH_PECR_PARALLBANK;\r
+ FLASH->PECR |= FLASH_PECR_FPRG;\r
+ FLASH->PECR |= FLASH_PECR_PROG;\r
+ \r
+ /* Write the first half page directly with 32 different words */\r
+ while(count < 32)\r
+ {\r
+ *(__IO uint32_t*) (Address1 + (4 * count)) = *(pBuffer1++);\r
+ count ++; \r
+ }\r
+ count = 0;\r
+ /* Write the second half page directly with 32 different words */\r
+ while(count < 32)\r
+ {\r
+ *(__IO uint32_t*) (Address2 + (4 * count)) = *(pBuffer2++);\r
+ count ++; \r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);\r
+ }\r
+\r
+ SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;\r
+ \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Group3\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Erase a double word in data memory.\r
+ * @param Address: specifies the address to be erased.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @note Data memory double word erase is possible only from SRAM.\r
+ * @note A double word is erased to the data memory only if the first address \r
+ * to load is the start address of a double word (multiple of 8 bytes).\r
+ * @note During the Data memory double word erase, all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.).\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+\r
+__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) \r
+ This bit prevents the interruption of multicycle instructions and therefore \r
+ will increase the interrupt latency. of Cortex-M3. */\r
+ SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to erase the next double word */\r
+ /* Set the ERASE bit */\r
+ FLASH->PECR |= FLASH_PECR_ERASE;\r
+\r
+ /* Set DATA bit */\r
+ FLASH->PECR |= FLASH_PECR_DATA;\r
+ \r
+ /* Write 00000000h to the 2 words to erase */\r
+ *(__IO uint32_t *)Address = 0x00000000;\r
+ Address += 4;\r
+ *(__IO uint32_t *)Address = 0x00000000;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* If the erase operation is completed, disable the ERASE and DATA bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);\r
+ } \r
+ \r
+ SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;\r
+ \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a double word in data memory without erase.\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation).\r
+ * @note Data memory double word write is possible only from SRAM.\r
+ * @note A data memory double word is written to the data memory only if the \r
+ * first address to load is the start address of a double word (multiple \r
+ * of double word).\r
+ * @note During the Data memory double word write, all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.).\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */ \r
+__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) \r
+ This bit prevents the interruption of multicycle instructions and therefore \r
+ will increase the interrupt latency. of Cortex-M3. */\r
+ SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new data*/\r
+ FLASH->PECR |= FLASH_PECR_FPRG;\r
+ FLASH->PECR |= FLASH_PECR_DATA;\r
+ \r
+ /* Write the 2 words */ \r
+ *(__IO uint32_t *)Address = (uint32_t) Data;\r
+ Address += 4;\r
+ *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* If the write operation is completed, disable the FPRG and DATA bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); \r
+ }\r
+ \r
+ SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;\r
+ \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+static __RAM_FUNC GetStatus(void)\r
+{\r
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ FLASHstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
+ { \r
+ FLASHstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)\r
+ {\r
+ FLASHstatus = FLASH_ERROR_PROGRAM; \r
+ }\r
+ else\r
+ {\r
+ FLASHstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the FLASH Status */\r
+ return FLASHstatus;\r
+}\r
+\r
+/**\r
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH programming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+static __RAM_FUNC WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ __IO FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the FLASH Status */\r
+ status = GetStatus();\r
+ \r
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = GetStatus();\r
+ Timeout--;\r
+ }\r
+ \r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+#if defined ( __TASKING__ )\r
+#pragma section_code_init restore\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_fsmc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the FSMC peripheral:\r
+ * + Initialization \r
+ * + Interrupts and flags management\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_fsmc.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC \r
+ * @brief FSMC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup FSMC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Group1 NOR/SRAM Controller functions\r
+ * @brief NOR/SRAM Controller functions \r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### NOR-SRAM Controller functions #####\r
+ ==============================================================================\r
+ [..] The following sequence should be followed to configure the FSMC to \r
+ interface with SRAM, PSRAM, NOR or OneNAND memory connected to the \r
+ NOR/SRAM Bank: \r
+ (#) Enable the clock for the FSMC and associated GPIOs using the following \r
+ functions: \r
+ (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); \r
+ (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); \r
+ (#) FSMC pins configuration \r
+ (++) Connect the involved FSMC pins to AF12 using the following function \r
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);\r
+ (++) Configure these FSMC pins in alternate function mode by calling the\r
+ function GPIO_Init();\r
+ (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example: \r
+ FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the \r
+ FSMC_NORSRAMInitStructure variable with the allowed values of the \r
+ structure member.\r
+ (#) Initialize the NOR/SRAM Controller by calling the function \r
+ FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); \r
+ (#) Then enable the NOR/SRAM Bank, for example: \r
+ FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); \r
+ (#) At this stage you can read/write from/to the memory connected to the \r
+ NOR/SRAM Bank.\r
+ \r
+@endverbatim\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
+ * reset values.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
+ \r
+ /* FSMC_Bank1_NORSRAM1 */\r
+ if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
+ {\r
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; \r
+ }\r
+ /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
+ else\r
+ { \r
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
+ }\r
+ FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
+ FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC NOR/SRAM Banks according to the specified\r
+ * parameters in the FSMC_NORSRAMInitStruct.\r
+ * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
+ * structure that contains the configuration information for \r
+ * the FSMC NOR/SRAM specified Banks. \r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
+ assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
+ assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
+ assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
+ assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
+ assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));\r
+ assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
+ assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
+ assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
+ assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
+ assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
+ assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); \r
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
+ \r
+ /* Bank1 NOR/SRAM control register configuration */ \r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
+\r
+ if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
+ {\r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;\r
+ }\r
+ \r
+ /* Bank1 NOR/SRAM timing register configuration */\r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
+ \r
+ \r
+ /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
+ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
+ {\r
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.\r
+ * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
+{ \r
+ /* Reset NOR/SRAM Init structure parameters values */\r
+ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
+ FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */\r
+ FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */\r
+ FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the GPIO peripheral: \r
+ * + Initialization and Configuration\r
+ * + GPIO Read and Write\r
+ * + GPIO Alternate functions configuration\r
+ * \r
+ * @verbatim\r
+ ===========================================================================\r
+ ##### How to use this driver #####\r
+ ===========================================================================\r
+ [..]\r
+ (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()\r
+ (#) Configure the GPIO pin(s) using GPIO_Init()\r
+ Four possible configuration are available for each pin:\r
+ (++) Input: Floating, Pull-up, Pull-down.\r
+ (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ Open Drain (Pull-up, Pull-down or no Pull).\r
+ In output mode, the speed is configurable: Very Low, Low,\r
+ Medium or High.\r
+ (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ Open Drain (Pull-up, Pull-down or no Pull).\r
+ (++) Analog: required mode when a pin is to be used as ADC channel,\r
+ DAC output or comparator input.\r
+ (#) Peripherals alternate function:\r
+ (++) For ADC, DAC and comparators, configure the desired pin in \r
+ analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN\r
+ (++) For other peripherals (TIM, USART...):\r
+ (+++) Connect the pin to the desired peripherals' Alternate \r
+ Function (AF) using GPIO_PinAFConfig() function.\r
+ (+++) Configure the desired pin in alternate function mode using\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ (+++) Select the type, pull-up/pull-down and output speed via \r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
+ (+++) Call GPIO_Init() function.\r
+ (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()\r
+ (#) To set/reset the level of a pin configured in output mode use\r
+ GPIO_SetBits()/GPIO_ResetBits()\r
+ (#) During and just after reset, the alternate functions are not \r
+ active and the GPIO pins are configured in input floating mode\r
+ (except JTAG pins).\r
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as \r
+ general-purpose (PC14 and PC15, respectively) when the LSE\r
+ oscillator is off. The LSE has priority over the GPIO function.\r
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
+ general-purpose PH0 and PH1, respectively, when the HSE \r
+ oscillator is off. The HSE has priority over the GPIO function.\r
+ @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO \r
+ * @brief GPIO driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Group1 Initialization and Configuration\r
+ * @brief Initialization and Configuration\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset \r
+ * values.\r
+ * By default, The GPIO pins are configured in input floating mode\r
+ * (except JTAG pins).\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ if(GPIOx == GPIOA)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); \r
+ }\r
+ else if(GPIOx == GPIOB)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOC)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOD)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOE)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOF)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOG)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if(GPIOx == GPIOH)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified \r
+ * parameters in the GPIO_InitStruct.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that \r
+ * contains the configuration information for the specified GPIO\r
+ * peripheral.\r
+\r
+ * @retval None\r
+ */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r
+\r
+ /* -------------------------Configure the port pins---------------- */\r
+ /*-- GPIO Mode Configuration --*/\r
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r
+ {\r
+ pos = ((uint32_t)0x01) << pinpos;\r
+\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+ if (currentpin == pos)\r
+ {\r
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r
+\r
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r
+\r
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r
+ {\r
+ /* Check Speed mode parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+\r
+ /* Speed mode configuration */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r
+\r
+ /*Check Output mode parameters */\r
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r
+\r
+ /* Output mode configuration */\r
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;\r
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r
+ }\r
+\r
+ /* Pull-up Pull down resistor configuration */\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r
+ GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each GPIO_InitStruct member with its default value.\r
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;\r
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ __IO uint32_t tmp = 0x00010000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group2 GPIO Read and Write\r
+ * @brief GPIO Read and Write\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### GPIO Read and Write #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data port.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @retval GPIO input data port value.\r
+ */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified output data port bit.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The output port pin value.\r
+ */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ \r
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the selected data port bits.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @retval None\r
+ */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRRL = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected data port bits.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @retval None\r
+ */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRRH = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+ * @param BitVal: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the BitAction enum values:\r
+ * @arg Bit_RESET: to clear the port pin\r
+ * @arg Bit_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));\r
+ \r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRRL = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRRH = GPIO_Pin ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param PortVal: specifies the value to be written to the port output data \r
+ * register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @brief Toggles the specified GPIO pins..\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the pins to be toggled.\r
+ * @retval None\r
+ */\r
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ GPIOx->ODR ^= GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions\r
+ * @brief GPIO Alternate functions configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### GPIO Alternate functions configuration functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified pin.\r
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral.\r
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @param GPIO_AFSelection: selects the pin to used as Alternat function.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization\r
+ * @arg GPIO_AF_MCO: Microcontroller clock output\r
+ * @arg GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out,\r
+ * 512 Hz clock output (with an LSE oscillator of 32.768 kHz)\r
+ * @arg GPIO_AF_WKUP: wakeup\r
+ * @arg GPIO_AF_SWJ: SWJ (SW and JTAG)\r
+ * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)\r
+ * @arg GPIO_AF_TIM2c: Connect TIM2 pins to AF1\r
+ * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2\r
+ * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2\r
+ * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2\r
+ * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3\r
+ * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3\r
+ * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3\r
+ * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4\r
+ * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4\r
+ * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5\r
+ * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5\r
+ * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6\r
+ * @arg GPIO_AF_USART1: Connect USART1 pins to AF7\r
+ * @arg GPIO_AF_USART2: Connect USART2 pins to AF7\r
+ * @arg GPIO_AF_USART3: Connect USART3 pins to AF7\r
+ * @arg GPIO_AF_UART4: Connect UART4 pins to AF8\r
+ * @arg GPIO_AF_UART5: Connect UART5 pins to AF8\r
+ * @arg GPIO_AF_USB: Connect USB pins to AF10\r
+ * @arg GPIO_AF_LCD: Connect LCD pins to AF11\r
+ * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12\r
+ * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12\r
+ * @arg GPIO_AF_RI: Connect RI pins to AF14\r
+ * @arg GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal\r
+ * @note The pin should already been configured in Alternate Function mode(AF)\r
+ * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * @note Please refer to the Alternate function mapping table in the device \r
+ * datasheet for the detailed mapping of the system and peripherals'\r
+ * alternate function I/O pins. \r
+ * @note EVENTOUT is not mapped on PH0, PH1 and PH2. \r
+ * @retval None\r
+ */\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r
+{\r
+ uint32_t temp = 0x00;\r
+ uint32_t temp_2 = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ assert_param(IS_GPIO_AF(GPIO_AF));\r
+ \r
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Inter-integrated circuit (I2C)\r
+ * + Initialization and Configuration\r
+ * + Data transfers\r
+ * + PEC management\r
+ * + DMA transfers management\r
+ * + Interrupts, events and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * ============================================================================\r
+ * ##### How to use this driver #####\r
+ * ============================================================================\r
+ [..]\r
+ (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)\r
+ function for I2C1 or I2C2.\r
+ (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using \r
+ RCC_AHBPeriphClockCmd() function. \r
+ (#) Peripherals alternate function: \r
+ (++) Connect the pin to the desired peripherals' Alternate \r
+ Function (AF) using GPIO_PinAFConfig() function.\r
+ (++) Configure the desired pin in alternate function by:\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ (++) Select the type, pull-up/pull-down and output speed via \r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ (++) Call GPIO_Init() function.\r
+ (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged\r
+ Address using the I2C_Init() function.\r
+ (#) Optionally you can enable/configure the following parameters without\r
+ re-initialization (i.e there is no need to call again I2C_Init() function):\r
+ (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.\r
+ (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.\r
+ (++) Enable the general call using the I2C_GeneralCallCmd() function.\r
+ (++) Enable the clock stretching using I2C_StretchClockCmd() function.\r
+ (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()\r
+ function.\r
+ (++) Enable the PEC Calculation using I2C_CalculatePEC() function.\r
+ (++) For SMBus Mode: \r
+ (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function.\r
+ (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function.\r
+ (#) Enable the NVIC and the corresponding interrupt using the function\r
+ I2C_ITConfig() if you need to use interrupt mode.\r
+ (#) When using the DMA mode \r
+ (++) Configure the DMA using DMA_Init() function.\r
+ (++) Active the needed channel Request using I2C_DMACmd() or\r
+ I2C_DMALastTransferCmd() function.\r
+ (#) Enable the I2C using the I2C_Cmd() function.\r
+ (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the \r
+ transfers. \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_i2c.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C \r
+ * @brief I2C driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*<! I2C registers Masks */\r
+#define FLAG_MASK ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */\r
+#define ITEN_MASK ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_DeInit(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ if (I2Cx == I2C1)\r
+ {\r
+ /* Enable I2C1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
+ /* Release I2C1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ /* Enable I2C2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
+ /* Release I2C2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the I2Cx peripheral according to the specified \r
+ * parameters in the I2C_InitStruct.\r
+ * @note To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency \r
+ * (I2C peripheral input clock) must be a multiple of 10 MHz. \r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+ * contains the configuration information for the specified I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, freqrange = 0;\r
+ uint16_t result = 0x04;\r
+ uint32_t pclk1 = 8000000;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
+\r
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
+ /* Get the I2Cx CR2 value */\r
+ tmpreg = I2Cx->CR2;\r
+ /* Clear frequency FREQ[5:0] bits */\r
+ tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);\r
+ /* Get pclk1 frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ pclk1 = rcc_clocks.PCLK1_Frequency;\r
+ /* Set frequency bits depending on pclk1 value */\r
+ freqrange = (uint16_t)(pclk1 / 1000000);\r
+ tmpreg |= freqrange;\r
+ /* Write to I2Cx CR2 */\r
+ I2Cx->CR2 = tmpreg;\r
+\r
+/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
+ /* Disable the selected I2C peripheral to configure TRISE */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
+ /* Reset tmpreg value */\r
+ /* Clear F/S, DUTY and CCR[11:0] bits */\r
+ tmpreg = 0;\r
+\r
+ /* Configure speed in standard mode */\r
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
+ {\r
+ /* Standard mode speed calculate */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
+ /* Test if CCR value is under 0x4*/\r
+ if (result < 0x04)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result = 0x04; \r
+ }\r
+ /* Set speed value for standard mode */\r
+ tmpreg |= result; \r
+ /* Set Maximum Rise Time for standard mode */\r
+ I2Cx->TRISE = freqrange + 1; \r
+ }\r
+ /* Configure speed in fast mode */\r
+ /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral\r
+ input clock) must be a multiple of 10 MHz */\r
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
+ {\r
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
+ }\r
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
+ /* Set DUTY bit */\r
+ result |= I2C_DutyCycle_16_9;\r
+ }\r
+\r
+ /* Test if CCR value is under 0x1*/\r
+ if ((result & I2C_CCR_CCR) == 0)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result |= (uint16_t)0x0001; \r
+ }\r
+ /* Set speed value and set F/S bit for fast mode */\r
+ tmpreg |= (uint16_t)(result | I2C_CCR_FS);\r
+ /* Set Maximum Rise Time for fast mode */\r
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
+ }\r
+\r
+ /* Write to I2Cx CCR */\r
+ I2Cx->CCR = tmpreg;\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= I2C_CR1_PE;\r
+\r
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
+ /* Get the I2Cx CR1 value */\r
+ tmpreg = I2Cx->CR1;\r
+ /* Clear ACK, SMBTYPE and SMBUS bits */\r
+ tmpreg &= CR1_CLEAR_MASK;\r
+ /* Configure I2Cx: mode and acknowledgement */\r
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
+ /* Set ACK bit according to I2C_Ack value */\r
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 = tmpreg;\r
+\r
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
+ /* Set I2Cx Own Address1 and acknowledged address */\r
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2C_InitStruct member with its default value.\r
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+/*---------------- Reset I2C init structure parameters values ----------------*/\r
+ /* initialize the I2C_ClockSpeed member */\r
+ I2C_InitStruct->I2C_ClockSpeed = 5000;\r
+ /* Initialize the I2C_Mode member */\r
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
+ /* Initialize the I2C_DutyCycle member */\r
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
+ /* Initialize the I2C_OwnAddress1 member */\r
+ I2C_InitStruct->I2C_OwnAddress1 = 0;\r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+ /* Initialize the I2C_AcknowledgedAddress member */\r
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= I2C_CR1_PE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C peripheral */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication START condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C START condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2Cx->CR1 |= I2C_CR1_START;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication STOP condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C STOP condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2Cx->CR1 |= I2C_CR1_STOP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C acknowledge feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C Acknowledgement.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2Cx->CR1 |= I2C_CR1_ACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified I2C own address2.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the 7bit I2C own address2.\r
+ * @retval None.\r
+ */\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
+{\r
+ uint16_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->OAR2;\r
+\r
+ /* Reset I2Cx Own address2 bit [7:1] */\r
+ tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);\r
+\r
+ /* Set I2Cx Own address2 */\r
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
+\r
+ /* Store the new register value */\r
+ I2Cx->OAR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C dual addressing mode.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C dual addressing mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable dual addressing mode */\r
+ I2Cx->OAR2 |= I2C_OAR2_ENDUAL;\r
+ }\r
+ else\r
+ {\r
+ /* Disable dual addressing mode */\r
+ I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C general call feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C General call.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable generall call */\r
+ I2Cx->CR1 |= I2C_CR1_ENGC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable generall call */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C software reset.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C software reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2Cx->CR1 |= I2C_CR1_SWRST;\r
+ }\r
+ else\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
+ * @retval None\r
+ */\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
+ {\r
+ /* Drive the SMBusAlert pin Low */\r
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
+ }\r
+ else\r
+ {\r
+ /* Drive the SMBusAlert pin High */\r
+ I2Cx->CR1 &= I2C_SMBusAlert_High;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C ARP.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx ARP. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C ARP */\r
+ I2Cx->CR1 |= I2C_CR1_ENARP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C ARP */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C Clock stretching.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx Clock stretching.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState == DISABLE)\r
+ {\r
+ /* Enable the selected I2C Clock stretching */\r
+ I2Cx->CR1 |= I2C_CR1_NOSTRETCH;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C Clock stretching */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C fast mode duty cycle.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
+ * @retval None\r
+ */\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=2 */\r
+ I2Cx->CCR &= I2C_DutyCycle_2;\r
+ }\r
+ else\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=16/9 */\r
+ I2Cx->CCR |= I2C_DutyCycle_16_9;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits the address byte to select the slave device.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the slave address which will be transmitted.\r
+ * @param I2C_Direction: specifies whether the I2C device will be a\r
+ * Transmitter or a Receiver. This parameter can be one of the following values:\r
+ * @arg I2C_Direction_Transmitter: Transmitter mode\r
+ * @arg I2C_Direction_Receiver: Receiver mode\r
+ * @retval None.\r
+ */\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
+ /* Test on the direction to set/reset the read/write bit */\r
+ if (I2C_Direction != I2C_Direction_Transmitter)\r
+ {\r
+ /* Set the address bit0 for read */\r
+ Address |= I2C_OAR1_ADD0;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the address bit0 for write */\r
+ Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);\r
+ }\r
+ /* Send the address */\r
+ I2Cx->DR = Address;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group2 Data transfers functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Data transfers functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends a data byte through the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Data: Byte to be transmitted.\r
+ * @retval None\r
+ */\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Write in the DR register the data to be sent */\r
+ I2Cx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The value of the received data.\r
+ */\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the data in the DR register */\r
+ return (uint8_t)I2Cx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C NACK position in master receiver mode.\r
+ * This function is useful in I2C Master Receiver mode when the number\r
+ * of data to be received is equal to 2. In this case, this function \r
+ * should be called (with parameter I2C_NACKPosition_Next) before data \r
+ * reception starts,as described in the 2-byte reception procedure \r
+ * recommended in Reference Manual in Section: Master receiver.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_NACKPosition: specifies the NACK position. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last\r
+ * received byte.\r
+ * @arg I2C_NACKPosition_Current: indicates that current byte is the last \r
+ * received byte.\r
+ * @note This function configures the same bit (POS) as I2C_PECPositionConfig() \r
+ * but is intended to be used in I2C mode while I2C_PECPositionConfig() \r
+ * is intended to used in SMBUS mode.\r
+ * \r
+ * @retval None\r
+ */\r
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));\r
+ \r
+ /* Check the input parameter */\r
+ if (I2C_NACKPosition == I2C_NACKPosition_Next)\r
+ {\r
+ /* Next byte in shift register is the last received byte */\r
+ I2Cx->CR1 |= I2C_NACKPosition_Next;\r
+ }\r
+ else\r
+ {\r
+ /* Current byte in shift register is the last received byte */\r
+ I2Cx->CR1 &= I2C_NACKPosition_Current;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group3 PEC management functions\r
+ * @brief PEC management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### PEC management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C PEC transfer.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C PEC transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC transmission */\r
+ I2Cx->CR1 |= I2C_CR1_PEC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC transmission */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C PEC position.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_PECPosition: specifies the PEC position. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
+ * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()\r
+ * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() \r
+ * is intended to used in I2C mode.\r
+ * @retval None\r
+ */\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
+ if (I2C_PECPosition == I2C_PECPosition_Next)\r
+ {\r
+ /* Next byte in shift register is PEC */\r
+ I2Cx->CR1 |= I2C_PECPosition_Next;\r
+ }\r
+ else\r
+ {\r
+ /* Current byte in shift register is PEC */\r
+ I2Cx->CR1 &= I2C_PECPosition_Current;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx PEC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC calculation */\r
+ I2Cx->CR1 |= I2C_CR1_ENPEC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC calculation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the PEC value for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The PEC value.\r
+ */\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the selected I2C PEC value */\r
+ return ((I2Cx->SR2) >> 8);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group4 DMA transfers management functions\r
+ * @brief DMA transfers management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DMA transfers management functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to configure the I2C DMA channels \r
+ requests.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C DMA requests.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C DMA requests */\r
+ I2Cx->CR2 |= I2C_CR2_DMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C DMA requests */\r
+ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Specifies that the next DMA transfer is the last one.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA last transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Next DMA transfer is the last transfer */\r
+ I2Cx->CR2 |= I2C_CR2_LAST;\r
+ }\r
+ else\r
+ {\r
+ /* Next DMA transfer is not the last transfer */\r
+ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group5 Interrupts events and flags management functions\r
+ * @brief Interrupts, events and flags management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts, events and flags management functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to configure the I2C Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode. \r
+\r
+\r
+ ##### I2C State Monitoring Functions #####\r
+ =============================================================================== \r
+ [..]This I2C driver provides three different ways for I2C state monitoring\r
+ depending on the application requirements and constraints:\r
+ \r
+ \r
+ ***. Basic state monitoring (Using I2C_CheckEvent() function) ***\r
+ -----------------------------------------------------------------\r
+ [..]It compares the status registers (SR1 and SR2) content to a given event\r
+ (can be the combination of one or more flags).\r
+ It returns SUCCESS if the current status includes the given flags \r
+ and returns ERROR if one or more flags are missing in the current status.\r
+\r
+ (+) When to use\r
+ (++) This function is suitable for most applications as well as for \r
+ startup activity since the events are fully described in the product \r
+ reference manual (RM0038).\r
+ (++) It is also suitable for users who need to define their own events.\r
+ (+) Limitations\r
+ (++) If an error occurs (ie. error flags are set besides to the monitored \r
+ flags), the I2C_CheckEvent() function may return SUCCESS despite \r
+ the communication hold or corrupted real state. \r
+ In this case, it is advised to use error interrupts to monitor \r
+ the error events and handle them in the interrupt IRQ handler.\r
+ -@@- For error management, it is advised to use the following functions:\r
+ (+@@) I2C_ITConfig() to configure and enable the error interrupts \r
+ (I2C_IT_ERR).\r
+ (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
+ Where x is the peripheral instance (I2C1, I2C2 ...).\r
+ (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the\r
+ I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
+ (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
+ and/or I2C_GenerateStop() in order to clear the error flag and source\r
+ and return to correct communication status.\r
+\r
+ *** Advanced state monitoring (Using the function I2C_GetLastEvent()) ***\r
+ ------------------------------------------------------------------------- \r
+ [..] Using the function I2C_GetLastEvent() which returns the image of both status \r
+ registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ by 16 bits and concatenated to Status Register 1).\r
+\r
+ (+) When to use\r
+ (++) This function is suitable for the same applications above but it \r
+ allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
+ function.\r
+ (++) The returned value could be compared to events already defined in \r
+ the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
+ This function is suitable when multiple flags are monitored at the \r
+ same time.\r
+ (++) At the opposite of I2C_CheckEvent() function, this function allows \r
+ user to choose when an event is accepted (when all events flags are \r
+ set and no other flags are set or just when the needed flags are set \r
+ like I2C_CheckEvent() function.\r
+\r
+ (+) Limitations\r
+ (++) User may need to define his own events.\r
+ (++) Same remark concerning the error management is applicable for this \r
+ function if user decides to check only regular communication flags \r
+ (and ignores error flags).\r
+ \r
+ \r
+ *** Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ***\r
+ ----------------------------------------------------------------------------\r
+ [..] Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ one single flag (ie. I2C_FLAG_RXNE ...).\r
+ (+) When to use\r
+ (++) This function could be used for specific applications or in debug \r
+ phase.\r
+ (++) It is suitable when only one flag checking is needed (most I2C \r
+ events are monitored through multiple flags).\r
+ (+) Limitations: \r
+ (++) When calling this function, the Status register is accessed. \r
+ Some flags are cleared when the status register is accessed. \r
+ So checking the status of one Flag, may clear other ones.\r
+ (++) Function may need to be called twice or more in order to monitor \r
+ one single event.\r
+ \r
+ [..] For detailed description of Events, please refer to section I2C_Events in \r
+ stm32l1xx_i2c.h file.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Reads the specified I2C register and returns its value.\r
+ * @param I2C_Register: specifies the register to read.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Register_CR1: CR1 register.\r
+ * @arg I2C_Register_CR2: CR2 register.\r
+ * @arg I2C_Register_OAR1: OAR1 register.\r
+ * @arg I2C_Register_OAR2: OAR2 register.\r
+ * @arg I2C_Register_DR: DR register.\r
+ * @arg I2C_Register_SR1: SR1 register.\r
+ * @arg I2C_Register_SR2: SR2 register.\r
+ * @arg I2C_Register_CCR: CCR register.\r
+ * @arg I2C_Register_TRISE: TRISE register.\r
+ * @retval The value of the read register.\r
+ */\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_REGISTER(I2C_Register));\r
+\r
+ tmp = (uint32_t) I2Cx;\r
+ tmp += I2C_Register;\r
+\r
+ /* Return the selected register value */\r
+ return (*(__IO uint16_t *) tmp);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C interrupts.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_BUF: Buffer interrupt mask\r
+ * @arg I2C_IT_EVT: Event interrupt mask\r
+ * @arg I2C_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified I2C interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2Cx->CR2 |= I2C_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
+ }\r
+}\r
+\r
+/*\r
+ ===============================================================================\r
+ 1. Basic state monitoring \r
+ ===============================================================================\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the last I2Cx Event is equal to the one passed\r
+ * as parameter.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_EVENT: specifies the event to be checked. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1\r
+ * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1\r
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2\r
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3\r
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2\r
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4\r
+ * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5\r
+ * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6\r
+ * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6\r
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2\r
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9\r
+ * @note For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32l1xx_i2c.h file.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Last event is equal to the I2C_EVENT\r
+ * - ERROR: Last event is different from the I2C_EVENT\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_EVENT(I2C_EVENT));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_MASK;\r
+\r
+ /* Check whether the last event contains the I2C_EVENT */\r
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
+ {\r
+ /* SUCCESS: last event is equal to I2C_EVENT */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: last event is different from I2C_EVENT */\r
+ status = ERROR;\r
+ }\r
+ /* Return status */\r
+ return status;\r
+}\r
+\r
+/*\r
+ ===============================================================================\r
+ 2. Advanced state monitoring \r
+ =============================================================================== \r
+ */\r
+\r
+/**\r
+ * @brief Returns the last I2Cx Event.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * \r
+ * @note For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32l1xx_i2c.h file.\r
+ * \r
+ * @retval The last event\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_MASK;\r
+\r
+ /* Return status */\r
+ return lastevent;\r
+}\r
+\r
+/*\r
+ ===============================================================================\r
+ 3. Flag-based state monitoring \r
+ =============================================================================== \r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C flag is set or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
+ * @arg I2C_FLAG_BUSY: Bus busy flag\r
+ * @arg I2C_FLAG_MSL: Master/Slave flag\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"\r
+ * Address matched flag (Slave mode)"ENDAD"\r
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_FLAG (SET or RESET).\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ __IO uint32_t i2creg = 0, i2cxbase = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
+\r
+ /* Get the I2Cx peripheral base address */\r
+ i2cxbase = (uint32_t)I2Cx;\r
+ \r
+ /* Read flag register index */\r
+ i2creg = I2C_FLAG >> 28;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_FLAG &= FLAG_MASK;\r
+ \r
+ if(i2creg != 0)\r
+ {\r
+ /* Get the I2Cx SR1 register address */\r
+ i2cxbase += 0x14;\r
+ }\r
+ else\r
+ {\r
+ /* Flag in I2Cx SR2 Register */\r
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
+ /* Get the I2Cx SR2 register address */\r
+ i2cxbase += 0x18;\r
+ }\r
+ \r
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* I2C_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the I2C_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the I2Cx's pending flags.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * \r
+\r
+ *@note STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ *@note ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
+ * second byte of the address in DR register.\r
+ *@note BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ *@note ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ *@note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
+ * register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_FLAG & FLAG_MASK;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C interrupt has occurred or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_IT_PECERR: PEC error in reception flag\r
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure flag\r
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error flag\r
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_IT_BTF: Byte transfer finished flag\r
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"\r
+ * Address matched flag (Slave mode)"ENDAD"\r
+ * @arg I2C_IT_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_IT (SET or RESET).\r
+ */\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_IT(I2C_IT));\r
+\r
+ /* Check if the interrupt source is enabled or not */\r
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_IT &= FLAG_MASK;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the I2Cx's interrupt pending bits.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt pending bit to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure interrupt\r
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error interrupt\r
+ * \r
+\r
+ * @note STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * @note ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
+ * byte of the address in I2C_DR register.\r
+ * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * @note ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * @note SB (Start Bit) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_DR register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_IT & FLAG_MASK;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Independent watchdog (IWDG) peripheral: \r
+ * + Prescaler and Counter configuration\r
+ * + IWDG activation\r
+ * + Flag management\r
+ *\r
+ * @verbatim \r
+ * \r
+ ============================================================================== \r
+ ##### IWDG features #####\r
+ ============================================================================== \r
+ [..] The IWDG can be started by either software or hardware (configurable\r
+ through option byte).\r
+ \r
+ [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and\r
+ thus stays active even if the main clock fails.\r
+ Once the IWDG is started, the LSI is forced ON and cannot be disabled\r
+ (LSI cannot be disabled too), and the counter starts counting down from \r
+ the reset value of 0xFFF. When it reaches the end of count value (0x000)\r
+ a system reset is generated.\r
+ The IWDG counter should be reloaded at regular intervals to prevent\r
+ an MCU reset.\r
+ \r
+ [..] The IWDG is implemented in the VDD voltage domain that is still functional\r
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).\r
+ \r
+ [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG\r
+ reset occurs.\r
+ \r
+ [..] Min-max timeout value @37KHz (LSI): ~108us / ~28.3s\r
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx\r
+ devices provide the capability to measure the LSI frequency (LSI clock\r
+ connected internally to TIM10 CH1 input capture). The measured value\r
+ can be used to have an IWDG timeout with an acceptable accuracy. \r
+ For more information, please refer to the STM32L1xx Reference manual.\r
+ \r
+ ##### How to use this driver ##### \r
+ ============================================================================== \r
+ [..]\r
+ (#) Enable write access to IWDG_PR and IWDG_RLR registers using\r
+ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.\r
+ (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function.\r
+\r
+ (#) Configure the IWDG counter value using IWDG_SetReload() function.\r
+ This value will be loaded in the IWDG counter each time the counter\r
+ is reloaded, then the IWDG will start counting down from this value.\r
+\r
+ (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used\r
+ in software mode (no need to enable the LSI, it will be enabled\r
+ by hardware).\r
+\r
+ (#) Then the application program must reload the IWDG counter at regular\r
+ intervals during normal operation to prevent an MCU reset, using\r
+ IWDG_ReloadCounter() function.\r
+\r
+ @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_iwdg.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG \r
+ * @brief IWDG driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ---------------------- IWDG registers bit mask ----------------------------*/\r
+/* KR register bit mask */\r
+#define KR_KEY_RELOAD ((uint16_t)0xAAAA)\r
+#define KR_KEY_ENABLE ((uint16_t)0xCCCC)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions\r
+ * @brief Prescaler and Counter configuration functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Prescaler and Counter configuration functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
+ * @retval None\r
+ */\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
+ IWDG->KR = IWDG_WriteAccess;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Prescaler value.\r
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
+ * @retval None\r
+ */\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
+ IWDG->PR = IWDG_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Reload value.\r
+ * @param Reload: specifies the IWDG Reload value.\r
+ * This parameter must be a number between 0 and 0x0FFF.\r
+ * @retval None\r
+ */\r
+void IWDG_SetReload(uint16_t Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_RELOAD(Reload));\r
+ IWDG->RLR = Reload;\r
+}\r
+\r
+/**\r
+ * @brief Reloads IWDG counter with value defined in the reload register\r
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_ReloadCounter(void)\r
+{\r
+ IWDG->KR = KR_KEY_RELOAD;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Group2 IWDG activation function\r
+ * @brief IWDG activation function \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IWDG activation function #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None.\r
+ * @retval None.\r
+ */\r
+void IWDG_Enable(void)\r
+{\r
+ IWDG->KR = KR_KEY_ENABLE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Group3 Flag management function \r
+ * @brief Flag management function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Flag management function ##### \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified IWDG flag is set or not.\r
+ * @param IWDG_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
+ * @retval The new state of IWDG_FLAG (SET or RESET).\r
+ */\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_lcd.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the LCD controller (LCD) peripheral:\r
+ * + Initialization and configuration\r
+ * + LCD RAM memory write\r
+ * + Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ \r
+ ===============================================================================\r
+ ##### LCD Clock #####\r
+ ===============================================================================\r
+ [..] LCDCLK is the same as RTCCLK. \r
+ [..] To configure the RTCCLK/LCDCLK, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ RCC_APB1PeriphClockCmd() function.\r
+ (+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.\r
+ (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.\r
+ \r
+ [..] The frequency generator allows you to achieve various LCD frame rates\r
+ starting from an LCD input clock frequency (LCDCLK) which can vary \r
+ from 32 kHz up to 1 MHz.\r
+ \r
+ ##### LCD and low power modes #####\r
+ ===============================================================================\r
+ [..] The LCD still active during STOP mode.\r
+ \r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (#) Enable LCD clock using \r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function.\r
+ (#) Configure the LCD prescaler, divider, duty, bias and voltage source\r
+ using LCD_Init() function.\r
+ (#) Optionally you can enable/configure:\r
+ (++) LCD High Drive using the LCD_HighDriveCmd() function.\r
+ (++) LCD COM/SEG Mux using the LCD_MuxSegmentCmd() function.\r
+ (++) LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function.\r
+ (++) LCD Dead Time using the LCD_DeadTimeConfig() function \r
+ (++) The LCD Blink mode and frequency using the LCD_BlinkConfig() function.\r
+ (++) The LCD Contrast using the LCD_ContrastConfig() function.\r
+ (#) Call the LCD_WaitForSynchro() function to wait for LCD_FCR register\r
+ synchronization.\r
+ (#) Call the LCD_Cmd() to enable the LCD controller.\r
+ (#) Wait until the LCD Controller status is enabled and the step-up\r
+ converter is ready using the LCD_GetFlagStatus() and\r
+ LCD_FLAG_ENS and LCD_FLAG_RDY flags.\r
+ (#) Write to the LCD RAM memory using the LCD_Write() function.\r
+ (#) Request an update display using the LCD_UpdateDisplayRequest()\r
+ function.\r
+ (#) Wait until the update display is finished by checking the UDD\r
+ flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD).\r
+ \r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_lcd.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD \r
+ * @brief LCD driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ LCD registers bit address in the alias region --------------- */\r
+#define LCD_OFFSET (LCD_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of LCDEN bit */\r
+#define CR_OFFSET (LCD_OFFSET + 0x00)\r
+#define LCDEN_BitNumber 0x00\r
+#define CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))\r
+\r
+/* Alias word address of MUX_SEG bit */\r
+#define MUX_SEG_BitNumber 0x07\r
+#define CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))\r
+\r
+\r
+/* --- FCR Register ---*/\r
+\r
+/* Alias word address of HD bit */\r
+#define FCR_OFFSET (LCD_OFFSET + 0x04)\r
+#define HD_BitNumber 0x00\r
+#define FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))\r
+\r
+/* --- SR Register ---*/\r
+\r
+/* Alias word address of UDR bit */\r
+#define SR_OFFSET (LCD_OFFSET + 0x08)\r
+#define UDR_BitNumber 0x02\r
+#define SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))\r
+\r
+#define FCR_MASK ((uint32_t)0xFC03FFFF) /* LCD FCR Mask */\r
+#define CR_MASK ((uint32_t)0xFFFFFF81) /* LCD CR Mask */\r
+#define PON_MASK ((uint32_t)0xFFFFFF8F) /* LCD PON Mask */\r
+#define DEAD_MASK ((uint32_t)0xFFFFFC7F) /* LCD DEAD Mask */\r
+#define BLINK_MASK ((uint32_t)0xFFFC1FFF) /* LCD BLINK Mask */\r
+#define CONTRAST_MASK ((uint32_t)0xFFFFE3FF) /* LCD CONTRAST Mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup LCD_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the LCD peripheral registers to their default reset\r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_DeInit(void)\r
+{\r
+ /* Enable LCD reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, ENABLE);\r
+ /* Release LCD from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LCD peripheral according to the specified parameters\r
+ * in the LCD_InitStruct.\r
+ * @note This function can be used only when the LCD is disabled.\r
+ * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure that contains\r
+ * the configuration information for the specified LCD peripheral.\r
+ * @retval None\r
+ */\r
+void LCD_Init(LCD_InitTypeDef* LCD_InitStruct)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_LCD_PRESCALER(LCD_InitStruct->LCD_Prescaler));\r
+ assert_param(IS_LCD_DIVIDER(LCD_InitStruct->LCD_Divider));\r
+ assert_param(IS_LCD_DUTY(LCD_InitStruct->LCD_Duty));\r
+ assert_param(IS_LCD_BIAS(LCD_InitStruct->LCD_Bias));\r
+ assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_InitStruct->LCD_VoltageSource));\r
+\r
+ LCD->FCR &= (uint32_t)FCR_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_InitStruct->LCD_Prescaler | LCD_InitStruct->LCD_Divider);\r
+\r
+ LCD_WaitForSynchro();\r
+\r
+ LCD->CR &= (uint32_t)CR_MASK;\r
+ LCD->CR |= (uint32_t)(LCD_InitStruct->LCD_Duty | LCD_InitStruct->LCD_Bias | \\r
+ LCD_InitStruct->LCD_VoltageSource);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Fills each LCD_InitStruct member with its default value.\r
+ * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct)\r
+{\r
+/*--------------- Reset LCD init structure parameters values -----------------*/\r
+ LCD_InitStruct->LCD_Prescaler = LCD_Prescaler_1; /*!< Initialize the LCD_Prescaler member */\r
+ \r
+ LCD_InitStruct->LCD_Divider = LCD_Divider_16; /*!< Initialize the LCD_Divider member */\r
+ \r
+ LCD_InitStruct->LCD_Duty = LCD_Duty_Static; /*!< Initialize the LCD_Duty member */\r
+ \r
+ LCD_InitStruct->LCD_Bias = LCD_Bias_1_4; /*!< Initialize the LCD_Bias member */\r
+ \r
+ LCD_InitStruct->LCD_VoltageSource = LCD_VoltageSource_Internal; /*!< Initialize the LCD_VoltageSource member */\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the LCD Controller.\r
+ * @param NewState: new state of the LCD peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_Cmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_LCDEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain.\r
+ * This function must be called after any write operation to LCD_FCR register.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_WaitForSynchro(void)\r
+{\r
+ /* Loop until FCRSF flag is set */\r
+ while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the low resistance divider. Displays with high\r
+ * internal resistance may need a longer drive time to achieve\r
+ * satisfactory contrast. This function is useful in this case if some\r
+ * additional power consumption can be tolerated.\r
+ * @note When this mode is enabled, the PulseOn Duration (PON) have to be \r
+ * programmed to 1/CK_PS (LCD_PulseOnDuration_1).\r
+ * @param NewState: new state of the low resistance divider.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_HighDriveCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) FCR_HD_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Mux Segment.\r
+ * @note This function can be used only when the LCD is disabled.\r
+ * @param NewState: new state of the Mux Segment.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_MuxSegmentCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_MUX_SEG_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD pulses on duration.\r
+ * @param LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of\r
+ * CK_PS (prescaled LCD clock period) pulses.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_PulseOnDuration_0: 0 pulse\r
+ * @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS\r
+ * @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS\r
+ * @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS\r
+ * @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS\r
+ * @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS\r
+ * @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS\r
+ * @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS\r
+ * @retval None\r
+ */\r
+void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_PULSE_ON_DURATION(LCD_PulseOnDuration));\r
+\r
+ LCD->FCR &= (uint32_t)PON_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_PulseOnDuration);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD dead time.\r
+ * @param LCD_DeadTime: specifies the LCD dead time.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_DeadTime_0: No dead Time\r
+ * @arg LCD_DeadTime_1: One Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_2: Two Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_3: Three Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_4: Four Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_5: Five Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_6: Six Phase between different couple of Frame \r
+ * @arg LCD_DeadTime_7: Seven Phase between different couple of Frame\r
+ * @retval None\r
+ */\r
+void LCD_DeadTimeConfig(uint32_t LCD_DeadTime)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));\r
+\r
+ LCD->FCR &= (uint32_t)DEAD_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_DeadTime);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD Blink mode and Blink frequency.\r
+ * @param LCD_BlinkMode: specifies the LCD blink mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_BlinkMode_Off: Blink disabled\r
+ * @arg LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)\r
+ * @arg LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8\r
+ * pixels according to the programmed duty)\r
+ * @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM \r
+ * (all pixels)\r
+ * @param LCD_BlinkFrequency: specifies the LCD blink frequency.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8\r
+ * @arg LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16\r
+ * @arg LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32\r
+ * @arg LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64\r
+ * @arg LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128\r
+ * @arg LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256\r
+ * @arg LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512\r
+ * @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024\r
+ * @retval None\r
+ */\r
+void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));\r
+ assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));\r
+ \r
+ LCD->FCR &= (uint32_t)BLINK_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_BlinkMode | LCD_BlinkFrequency);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD Contrast.\r
+ * @param LCD_Contrast: specifies the LCD Contrast.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_Contrast_Level_0: Maximum Voltage = 2.60V\r
+ * @arg LCD_Contrast_Level_1: Maximum Voltage = 2.73V\r
+ * @arg LCD_Contrast_Level_2: Maximum Voltage = 2.86V\r
+ * @arg LCD_Contrast_Level_3: Maximum Voltage = 2.99V\r
+ * @arg LCD_Contrast_Level_4: Maximum Voltage = 3.12V\r
+ * @arg LCD_Contrast_Level_5: Maximum Voltage = 3.25V\r
+ * @arg LCD_Contrast_Level_6: Maximum Voltage = 3.38V\r
+ * @arg LCD_Contrast_Level_7: Maximum Voltage = 3.51V\r
+ * @retval None\r
+ */\r
+void LCD_ContrastConfig(uint32_t LCD_Contrast)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_CONTRAST(LCD_Contrast));\r
+\r
+ LCD->FCR &= (uint32_t)CONTRAST_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_Contrast);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Group2 LCD RAM memory write functions\r
+ * @brief LCD RAM memory write functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### LCD RAM memory write functions #####\r
+ ===============================================================================\r
+ [..] Using its double buffer memory the LCD controller ensures the coherency \r
+ of the displayed information without having to use interrupts to control \r
+ LCD_RAM modification.\r
+\r
+ [..] The application software can access the first buffer level (LCD_RAM) through\r
+ the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag \r
+ in the LCD_SR register using the LCD_UpdateDisplayRequest() function.\r
+\r
+ [..] This UDR flag (update display request) requests the updated information \r
+ to be moved into the second buffer level (LCD_DISPLAY).\r
+\r
+ [..] This operation is done synchronously with the frame (at the beginning of \r
+ the next frame), until the update is completed, the LCD_RAM is write \r
+ protected and the UDR flag stays high.\r
+\r
+ [..] Once the update is completed another flag (UDD - Update Display Done) is \r
+ set and generates an interrupt if the UDDIE bit in the LCD_FCR register \r
+ is set.\r
+\r
+ [..] The time it takes to update LCD_DISPLAY is, in the worst case, one odd \r
+ and one even frame.\r
+\r
+ [..] The update will not occur (UDR = 1 and UDD = 0) until the display is\r
+ enabled (LCDEN = 1).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a word in the specific LCD RAM.\r
+ * @param LCD_RAMRegister: specifies the LCD Contrast.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_RAMRegister_0: LCD RAM Register 0\r
+ * @arg LCD_RAMRegister_1: LCD RAM Register 1\r
+ * @arg LCD_RAMRegister_2: LCD RAM Register 2\r
+ * @arg LCD_RAMRegister_3: LCD RAM Register 3\r
+ * @arg LCD_RAMRegister_4: LCD RAM Register 4\r
+ * @arg LCD_RAMRegister_5: LCD RAM Register 5\r
+ * @arg LCD_RAMRegister_6: LCD RAM Register 6\r
+ * @arg LCD_RAMRegister_7: LCD RAM Register 7\r
+ * @arg LCD_RAMRegister_8: LCD RAM Register 8\r
+ * @arg LCD_RAMRegister_9: LCD RAM Register 9\r
+ * @arg LCD_RAMRegister_10: LCD RAM Register 10\r
+ * @arg LCD_RAMRegister_11: LCD RAM Register 11\r
+ * @arg LCD_RAMRegister_12: LCD RAM Register 12\r
+ * @arg LCD_RAMRegister_13: LCD RAM Register 13\r
+ * @arg LCD_RAMRegister_14: LCD RAM Register 14\r
+ * @arg LCD_RAMRegister_15: LCD RAM Register 15\r
+ * @param LCD_Data: specifies LCD Data Value to be written.\r
+ * @retval None\r
+ */\r
+void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));\r
+\r
+ /* Copy data bytes to RAM register */\r
+ LCD->RAM[LCD_RAMRegister] = (uint32_t)LCD_Data;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Update Display Request.\r
+ * @note Each time software modifies the LCD_RAM it must set the UDR bit to\r
+ * transfer the updated data to the second level buffer.\r
+ * The UDR bit stays set until the end of the update and during this\r
+ * time the LCD_RAM is write protected.\r
+ * @note When the display is disabled, the update is performed for all\r
+ * LCD_DISPLAY locations.\r
+ * When the display is enabled, the update is performed only for locations\r
+ * for which commons are active (depending on DUTY). For example if\r
+ * DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_UpdateDisplayRequest(void)\r
+{\r
+ *(__IO uint32_t *) SR_UDR_BB = (uint32_t)0x01;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified LCD interrupts.\r
+ * @param LCD_IT: specifies the LCD interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt\r
+ * @param NewState: new state of the specified LCD interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_IT(LCD_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ LCD->FCR |= LCD_IT;\r
+ }\r
+ else\r
+ {\r
+ LCD->FCR &= (uint32_t)~LCD_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified LCD flag is set or not.\r
+ * @param LCD_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.\r
+ * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR\r
+ * goes from 0 to 1. On deactivation it reflects the real status of\r
+ * LCD so it becomes 0 at the end of the last displayed frame.\r
+ * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at\r
+ * the beginning of a new frame, at the same time as the display data is\r
+ * updated.\r
+ * @arg LCD_FLAG_UDR: Update Display Request flag.\r
+ * @arg LCD_FLAG_UDD: Update Display Done flag.\r
+ * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status\r
+ * of the step-up converter.\r
+ * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.\r
+ * This flag is set by hardware each time the LCD_FCR register is updated\r
+ * in the LCDCLK domain.\r
+ * @retval The new state of LCD_FLAG (SET or RESET).\r
+ */\r
+FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_GET_FLAG(LCD_FLAG));\r
+ \r
+ if ((LCD->SR & LCD_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the LCD's pending flags.\r
+ * @param LCD_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_FLAG_SOF: Start of Frame Interrupt\r
+ * @arg LCD_FLAG_UDD: Update Display Done Interrupt\r
+ * @retval None\r
+ */\r
+void LCD_ClearFlag(uint32_t LCD_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_CLEAR_FLAG(LCD_FLAG));\r
+ \r
+ /* Clear the corresponding LCD flag */\r
+ LCD->CLR = (uint32_t)LCD_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occurred or not.\r
+ * @param LCD_IT: specifies the LCD interrupts sources to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt.\r
+ * @note If the device is in STOP mode (PCLK not provided) UDD will not \r
+ * generate an interrupt even if UDDIE = 1. \r
+ * If the display is not enabled the UDD interrupt will never occur.\r
+ * @retval The new state of the LCD_IT (SET or RESET).\r
+ */\r
+ITStatus LCD_GetITStatus(uint32_t LCD_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_GET_IT(LCD_IT));\r
+ \r
+ if ((LCD->SR & LCD_IT) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ if (((LCD->FCR & LCD_IT) != (uint16_t)RESET) && (bitstatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the LCD's interrupt pending bits.\r
+ * @param LCD_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt\r
+ * @retval None\r
+ */\r
+void LCD_ClearITPendingBit(uint32_t LCD_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_IT(LCD_IT));\r
+ \r
+ /* Clear the corresponding LCD pending bit */\r
+ LCD->CLR = (uint32_t)LCD_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_opamp.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following\r
+ * functionalities of the operational amplifiers (opamp) peripheral:\r
+ * + Initialization and configuration\r
+ * + Calibration management\r
+ * \r
+ * @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] The device integrates three independent rail-to-rail operational amplifiers\r
+ OPAMP1, OPAMP2 and OPAMP3:\r
+ (+) Internal connections to the ADC.\r
+ (+) Internal connections to the DAC.\r
+ (+) Internal connection to COMP1 (only OPAMP3).\r
+ (+) Internal connection for unity gain (voltage follower) configuration.\r
+ (+) Calibration capability.\r
+ (+) Selectable gain-bandwidth (2MHz in normal mode, 500KHz in low power mode).\r
+ [..] \r
+ (#) COMP AHB clock must be enabled to get write access\r
+ to OPAMP registers using\r
+ (#) RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE)\r
+ \r
+ (#) Configure the corresponding GPIO to OPAMPx INP, OPAMPx_INN (if used)\r
+ and OPAMPx_OUT in analog mode.\r
+ \r
+ (#) Configure (close/open) the OPAMP switches using OPAMP_SwitchCmd()\r
+\r
+ (#) Enable the OPAMP peripheral using OPAMP_Cmd()\r
+\r
+ -@- In order to use OPAMP outputs as ADC inputs, the opamps must be enabled\r
+ and the ADC must use the OPAMP output channel number:\r
+ (+@) OPAMP1 output is connected to ADC channel 3.\r
+ (+@) OPAMP2 output is connected to ADC channel 8.\r
+ (+@) OPAMP3 output is connected to ADC channel 13 (SW1 switch must be closed).\r
+\r
+ * @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_opamp.h"\r
+\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup OPAMP \r
+ * @brief OPAMP driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup OPAMP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup OPAMP_Group1 Initialization and configuration\r
+ * @brief Initialization and configuration\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and configuration #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Deinitialize the OPAMPs register to its default reset value.\r
+ * @note At startup, OTR and LPOTR registers are set to factory programmed values.\r
+ * @param None.\r
+ * @retval None.\r
+ */\r
+void OPAMP_DeInit(void)\r
+{\r
+ /*!< Set OPAMP_CSR register to reset value */\r
+ OPAMP->CSR = 0x00010101;\r
+ /*!< Set OPAMP_OTR register to reset value */\r
+ OPAMP->OTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x00000038);\r
+ /*!< Set OPAMP_LPOTR register to reset value */\r
+ OPAMP->LPOTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x0000003C);\r
+}\r
+\r
+/**\r
+ * @brief Close or Open the OPAMP switches.\r
+ * @param OPAMP_OPAMPxSwitchy: selects the OPAMPx switch.\r
+ * This parameter can be any combinations of the following values:\r
+ * @arg OPAMP_OPAMP1Switch3: used to connect internally OPAMP1 output to \r
+ * OPAMP1 negative input (internal follower)\r
+ * @arg OPAMP_OPAMP1Switch4: used to connect PA2 to OPAMP1 negative input\r
+ * @arg OPAMP_OPAMP1Switch5: used to connect PA1 to OPAMP1 positive input\r
+ * @arg OPAMP_OPAMP1Switch6: used to connect DAC_OUT1 to OPAMP1 positive input\r
+ * @arg OPAMP_OPAMP1SwitchANA: used to meet 1 nA input leakage\r
+ * @arg OPAMP_OPAMP2Switch3: used to connect internally OPAMP2 output to \r
+ * OPAMP2 negative input (internal follower)\r
+ * @arg OPAMP_OPAMP2Switch4: used to connect PA7 to OPAMP2 negative input\r
+ * @arg OPAMP_OPAMP2Switch5: used to connect PA6 to OPAMP2 positive input\r
+ * @arg OPAMP_OPAMP2Switch6: used to connect DAC_OUT1 to OPAMP2 positive input\r
+ * @arg OPAMP_OPAMP2Switch7: used to connect DAC_OUT2 to OPAMP2 positive input\r
+ * @arg OPAMP_OPAMP2SwitchANA: used to meet 1 nA input leakage\r
+ * @arg OPAMP_OPAMP3Switch3: used to connect internally OPAMP3 output to \r
+ * OPAMP3 negative input (internal follower)\r
+ * @arg OPAMP_OPAMP3Switch4: used to connect PC2 to OPAMP3 negative input\r
+ * @arg OPAMP_OPAMP3Switch5: used to connect PC1 to OPAMP3 positive input\r
+ * @arg OPAMP_OPAMP3Switch6: used to connect DAC_OUT1 to OPAMP3 positive input\r
+ * @arg OPAMP_OPAMP3SwitchANA: used to meet 1 nA input leakage on negative input\r
+ *\r
+ * @param NewState: New state of the OPAMP switch. \r
+ * This parameter can be:\r
+ * ENABLE to close the OPAMP switch\r
+ * or DISABLE to open the OPAMP switch\r
+ * @note OPAMP_OPAMP2Switch6 and OPAMP_OPAMP2Switch7 mustn't be closed together.\r
+ * @retval None\r
+ */\r
+void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_OPAMP_SWITCH(OPAMP_OPAMPxSwitchy));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Close the selected switches */\r
+ OPAMP->CSR |= (uint32_t) OPAMP_OPAMPxSwitchy;\r
+ }\r
+ else\r
+ {\r
+ /* Open the selected switches */\r
+ OPAMP->CSR &= (~(uint32_t)OPAMP_OPAMPxSwitchy);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the OPAMP peripheral.\r
+ * @param OPAMP_Selection: the selected OPAMP. \r
+ * This parameter can be one of the following values:\r
+ * @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected\r
+ * @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected\r
+ * @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected\r
+ * @param NewState: new state of the selected OPAMP peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected OPAMP */\r
+ OPAMP->CSR &= (~(uint32_t) OPAMP_Selection);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected OPAMP */\r
+ OPAMP->CSR |= (uint32_t) OPAMP_Selection;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the low power mode for OPAMP peripheral.\r
+ * @param OPAMP_Selection: the selected OPAMP. \r
+ * This parameter can be one of the following values:\r
+ * @arg OPAMP_Selection_OPAMP1: OPAMP1 selected\r
+ * @arg OPAMP_Selection_OPAMP2: OPAMP2 selected\r
+ * @arg OPAMP_Selection_OPAMP3: OPAMP3 selected\r
+ * @param NewState: new low power state of the selected OPAMP peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the selected OPAMP in low power mode */\r
+ OPAMP->CSR |= (uint32_t) (OPAMP_Selection << 7);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the low power mode for the selected OPAMP */\r
+ OPAMP->CSR &= (~(uint32_t) (OPAMP_Selection << 7));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Select the OPAMP power range.\r
+ * @note The OPAMP power range selection must be performed while OPAMPs are powered down.\r
+ * @param OPAMP_Range: the selected OPAMP power range. \r
+ * This parameter can be one of the following values:\r
+ * @arg OPAMP_PowerRange_Low: Low power range is selected (VDDA is lower than 2.4V).\r
+ * @arg OPAMP_PowerRange_High: High power range is selected (VDDA is higher than 2.4V).\r
+ * @retval None\r
+ */\r
+void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_OPAMP_RANGE(OPAMP_PowerRange));\r
+\r
+ /* Reset the OPAMP range bit */\r
+ OPAMP->CSR &= (~(uint32_t) (OPAMP_CSR_AOP_RANGE));\r
+\r
+ /* Select the OPAMP power range */\r
+ OPAMP->CSR |= OPAMP_PowerRange;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup OPAMP_Group2 Calibration functions\r
+ * @brief Calibration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Calibration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Select the trimming mode.\r
+ * @param OffsetTrimming: the selected offset trimming mode. \r
+ * This parameter can be one of the following values:\r
+ * @arg OffsetTrimming_Factory: factory trimming values are used for offset\r
+ * calibration.\r
+ * @arg OffsetTrimming_User: user trimming values are used for offset\r
+ * calibration.\r
+ * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()\r
+ * function or OPAMP_OffsetTrimLowPowerConfig() function to adjust \r
+ * trimming value.\r
+ * @retval None\r
+ */\r
+void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));\r
+\r
+ /* Reset the OPAMP_OTR range bit */\r
+ OPAMP->CSR &= (~(uint32_t) (OPAMP_OTR_OT_USER));\r
+\r
+ /* Select the OPAMP offset trimming */\r
+ OPAMP->CSR |= OPAMP_Trimming;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configure the trimming value of OPAMPs in normal mode.\r
+ * @param OPAMP_Selection: the selected OPAMP. \r
+ * This parameter can be one of the following values:\r
+ * @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.\r
+ * @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.\r
+ * @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.\r
+ * @param OPAMP_Input: the selected OPAMP input. \r
+ * This parameter can be one of the following values:\r
+ * @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.\r
+ * @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.\r
+ * @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower\r
+ * or equal to 0x0000001F. \r
+ * @retval None\r
+ */\r
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
+ assert_param(IS_OPAMP_INPUT(OPAMP_Input));\r
+ assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));\r
+\r
+ /* Get the OPAMP_OTR value */\r
+ tmpreg = OPAMP->OTR;\r
+\r
+ if(OPAMP_Selection == OPAMP_Selection_OPAMP1)\r
+ {\r
+ /* Reset the OPAMP inputs selection */\r
+ tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);\r
+ /* Select the OPAMP input */\r
+ tmpreg |= OPAMP_Input;\r
+\r
+ if(OPAMP_Input == OPAMP_Input_PMOS)\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP1 PMOS input */\r
+ tmpreg &= (0xFFFFFFE0);\r
+ /* Set the new trimming value corresponding to OPAMP1 PMOS input */\r
+ tmpreg |= (OPAMP_TrimValue);\r
+ }\r
+ else\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP1 NMOS input */\r
+ tmpreg &= (0xFFFFFC1F);\r
+ /* Set the new trimming value corresponding to OPAMP1 NMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<5);\r
+ }\r
+ }\r
+ else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)\r
+ {\r
+ /* Reset the OPAMP inputs selection */\r
+ tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);\r
+ /* Select the OPAMP input */\r
+ tmpreg |= (uint32_t)(OPAMP_Input<<8);\r
+\r
+ if(OPAMP_Input == OPAMP_Input_PMOS)\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP2 PMOS input */\r
+ tmpreg &= (0xFFFF83FF);\r
+ /* Set the new trimming value corresponding to OPAMP2 PMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<10);\r
+ }\r
+ else\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP2 NMOS input */\r
+ tmpreg &= (0xFFF07FFF);\r
+ /* Set the new trimming value corresponding to OPAMP2 NMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<15);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset the OPAMP inputs selection */\r
+ tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);\r
+ /* Select the OPAMP input */\r
+ tmpreg |= (uint32_t)(OPAMP_Input<<16);\r
+\r
+ if(OPAMP_Input == OPAMP_Input_PMOS)\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP3 PMOS input */\r
+ tmpreg &= (0xFE0FFFFF);\r
+ /* Set the new trimming value corresponding to OPAMP3 PMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<20);\r
+ }\r
+ else\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP3 NMOS input */\r
+ tmpreg &= (0xC1FFFFFF);\r
+ /* Set the new trimming value corresponding to OPAMP3 NMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<25);\r
+ }\r
+ }\r
+\r
+ /* Set the OPAMP_OTR register */\r
+ OPAMP->OTR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configure the trimming value of OPAMPs in low power mode.\r
+ * @param OPAMP_Selection: the selected OPAMP. \r
+ * This parameter can be one of the following values:\r
+ * @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.\r
+ * @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.\r
+ * @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.\r
+ * @param OPAMP_Input: the selected OPAMP input. \r
+ * This parameter can be one of the following values:\r
+ * @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.\r
+ * @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.\r
+ * @param OPAMP_TrimValue: the trimming value. \r
+ * This parameter can be any value lower or equal to 0x0000001F. \r
+ * @retval None\r
+ */\r
+void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
+ assert_param(IS_OPAMP_INPUT(OPAMP_Input));\r
+ assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));\r
+\r
+ /* Get the OPAMP_LPOTR value */\r
+ tmpreg = OPAMP->LPOTR;\r
+\r
+ if(OPAMP_Selection == OPAMP_Selection_OPAMP1)\r
+ {\r
+ /* Reset the OPAMP inputs selection */\r
+ tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);\r
+ /* Select the OPAMP input */\r
+ tmpreg |= OPAMP_Input;\r
+\r
+ if(OPAMP_Input == OPAMP_Input_PMOS)\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP1 PMOS input */\r
+ tmpreg &= (0xFFFFFFE0);\r
+ /* Set the new trimming value corresponding to OPAMP1 PMOS input */\r
+ tmpreg |= (OPAMP_TrimValue);\r
+ }\r
+ else\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP1 NMOS input */\r
+ tmpreg &= (0xFFFFFC1F);\r
+ /* Set the new trimming value corresponding to OPAMP1 NMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<5);\r
+ }\r
+ }\r
+ else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)\r
+ {\r
+ /* Reset the OPAMP inputs selection */\r
+ tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);\r
+ /* Select the OPAMP input */\r
+ tmpreg |= (uint32_t)(OPAMP_Input<<8);\r
+\r
+ if(OPAMP_Input == OPAMP_Input_PMOS)\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP2 PMOS input */\r
+ tmpreg &= (0xFFFF83FF);\r
+ /* Set the new trimming value corresponding to OPAMP2 PMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<10);\r
+ }\r
+ else\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP2 NMOS input */\r
+ tmpreg &= (0xFFF07FFF);\r
+ /* Set the new trimming value corresponding to OPAMP2 NMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<15);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset the OPAMP inputs selection */\r
+ tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);\r
+ /* Select the OPAMP input */\r
+ tmpreg |= (uint32_t)(OPAMP_Input<<16);\r
+\r
+ if(OPAMP_Input == OPAMP_Input_PMOS)\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP3 PMOS input */\r
+ tmpreg &= (0xFE0FFFFF);\r
+ /* Set the new trimming value corresponding to OPAMP3 PMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<20);\r
+ }\r
+ else\r
+ {\r
+ /* Reset the trimming value corresponding to OPAMP3 NMOS input */\r
+ tmpreg &= (0xC1FFFFFF);\r
+ /* Set the new trimming value corresponding to OPAMP3 NMOS input */\r
+ tmpreg |= (OPAMP_TrimValue<<25);\r
+ }\r
+ }\r
+\r
+ /* Set the OPAMP_LPOTR register */\r
+ OPAMP->LPOTR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified OPAMP calibration flag is set or not.\r
+ * @note User should wait until calibration flag change the value when changing\r
+ * the trimming value.\r
+ * @param OPAMP_Selection: the selected OPAMP. \r
+ * This parameter can be one of the following values:\r
+ * @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected.\r
+ * @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected.\r
+ * @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected.\r
+ * @retval The new state of the OPAMP calibration flag (SET or RESET).\r
+ */\r
+FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));\r
+ \r
+ /* Get the CSR register value */\r
+ tmpreg = OPAMP->CSR;\r
+\r
+ /* Check if OPAMP1 is selected */\r
+ if(OPAMP_Selection == OPAMP_Selection_OPAMP1)\r
+ {\r
+ /* Check OPAMP1 CAL bit status */\r
+ if ((tmpreg & OPAMP_CSR_OPA1CALOUT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ /* Check if OPAMP2 is selected */\r
+ else if(OPAMP_Selection == OPAMP_Selection_OPAMP2)\r
+ {\r
+ /* Check OPAMP2 CAL bit status */\r
+ if ((tmpreg & OPAMP_CSR_OPA2CALOUT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ } \r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check OPAMP3 CAL bit status */\r
+ if ((tmpreg & OPAMP_CSR_OPA3CALOUT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Power Controller (PWR) peripheral: \r
+ * + RTC Domain Access\r
+ * + PVD configuration\r
+ * + WakeUp pins configuration\r
+ * + Ultra Low Power mode configuration\r
+ * + Voltage Scaling configuration\r
+ * + Low Power modes configuration\r
+ * + Flags management\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR \r
+ * @brief PWR driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* --------- PWR registers bit address in the alias region ---------- */\r
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of DBP bit */\r
+#define CR_OFFSET (PWR_OFFSET + 0x00)\r
+#define DBP_BitNumber 0x08\r
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BitNumber 0x04\r
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
+\r
+/* Alias word address of ULP bit */\r
+#define ULP_BitNumber 0x09\r
+#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))\r
+\r
+/* Alias word address of FWU bit */\r
+#define FWU_BitNumber 0x0A\r
+#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of EWUP bit */\r
+#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
+#define EWUP_BitNumber 0x08\r
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
+#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Group1 RTC Domain Access function \r
+ * @brief RTC Domain Access function \r
+ *\r
+@verbatim \r
+ ============================================================================== \r
+ ##### RTC Domain Access function #####\r
+ ============================================================================== \r
+\r
+ [..] After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup \r
+ registers) are protected against possible stray write accesses.\r
+ [..] To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
+ * @note Before calling this function, the VOS[1:0] bits should be configured \r
+ * to "10" and the system frequency has to be configured accordingly. \r
+ * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()\r
+ * function.\r
+ * @note ULP and FWU bits are not reset by this function. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables access to the RTC and backup registers.\r
+ * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the \r
+ * RTC Domain Access should be kept enabled.\r
+ * @param NewState: new state of the access to the RTC and backup registers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_RTCAccessCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group2 PVD configuration functions\r
+ * @brief PVD configuration functions \r
+ *\r
+@verbatim \r
+ ============================================================================== \r
+ ##### PVD configuration functions #####\r
+ ============================================================================== \r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold\r
+ selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ (+) The PVD can use an external input analog voltage (PVD_IN) which is compared \r
+ internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode \r
+ when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).\r
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the \r
+ PVD threshold. This event is internally connected to the EXTI line16\r
+ and can generate an interrupt if enabled through the EXTI registers.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param PWR_PVDLevel: specifies the PVD detection level.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V.\r
+ * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V.\r
+ * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V.\r
+ * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V.\r
+ * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V.\r
+ * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V.\r
+ * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V.\r
+ * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT).\r
+ * @retval None\r
+ */\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+ \r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PLS[7:5] bits */\r
+ tmpreg &= CR_PLS_MASK;\r
+ \r
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+ tmpreg |= PWR_PVDLevel;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Power Voltage Detector(PVD).\r
+ * @param NewState: new state of the PVD.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group3 WakeUp pins configuration functions\r
+ * @brief WakeUp pins configuration functions \r
+ *\r
+@verbatim \r
+ ============================================================================== \r
+ ##### WakeUp pin configuration functions #####\r
+ ============================================================================== \r
+\r
+ (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are \r
+ forced in input pull down configuration and are active on rising edges.\r
+ (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and\r
+ WakeUp Pin 3 on PE.06.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the WakeUp Pin functionality.\r
+ * @param PWR_WakeUpPin: specifies the WakeUpPin.\r
+ * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.\r
+ * @param NewState: new state of the WakeUp Pin functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));\r
+ \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ tmp = CSR_EWUP_BB + PWR_WakeUpPin;\r
+ \r
+ *(__IO uint32_t *) (tmp) = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group4 Ultra Low Power mode configuration functions\r
+ * @brief Ultra Low Power mode configuration functions \r
+ *\r
+@verbatim \r
+ ============================================================================== \r
+ ##### Ultra Low Power mode configuration functions #####\r
+ ============================================================================== \r
+ [..]\r
+ (+) The internal voltage reference consumption is not negligible, in particular \r
+ in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()\r
+ function (ULP bit (Ultra low power) in the PWR_CR register) to disable the \r
+ internal voltage reference. However, in this case, when exiting from the \r
+ Stop/Standby mode, the functions managed through the internal voltage reference \r
+ are not reliable during the internal voltage reference startup time (up to 3 ms).\r
+ To reduce the wakeup time, the device can exit from Stop/Standby mode without \r
+ waiting for the internal voltage reference startup time. This is performed \r
+ by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast\r
+ wakeup) in the PWR_CR register) before entering Stop/Standby mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.\r
+ * @param NewState: new state of the Fast WakeUp functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_FastWakeUpCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Ultra Low Power mode.\r
+ * @param NewState: new state of the Ultra Low Power mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group5 Voltage Scaling configuration functions\r
+ * @brief Voltage Scaling configuration functions \r
+ *\r
+@verbatim \r
+ ============================================================================== \r
+ ##### Voltage Scaling configuration functions #####\r
+ ============================================================================== \r
+\r
+ (+) The dynamic voltage scaling is a power management technique which consists in \r
+ increasing or decreasing the voltage used for the digital peripherals (VCORE), \r
+ according to the circumstances.\r
+ \r
+ [..] Depending on the device voltage range, the maximum frequency and FLASH wait\r
+ state should be adapted accordingly:\r
+ [..] \r
+ +------------------------------------------------------------------+ \r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------| \r
+ | (Latency) | voltage range | voltage range | \r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------|\r
+ | | Range 3 | Range 2 | Range 1 |\r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |---------------- |----------------|---------------|---------------| \r
+ | 0WS(1CPU cycle) |0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |-----------------|----------------|---------------|---------------| \r
+ | 1WS(2CPU cycle) |2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
+ |-----------------|----------------|---------------|---------------| \r
+ | CPU Performance | Low | Medium | High |\r
+ |-----__----------|----------------|---------------|---------------| \r
+ |Power Performance| High | Medium | Low | \r
+ +------------------------------------------------------------------+ \r
+\r
+ (+) To modify the Product voltage range, user application has to:\r
+ (++) Check VDD to identify which ranges are allowed (see table above).\r
+ (++) Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus() \r
+ function and wait until it is reset.\r
+ (++) Configure the Voltage range using the PWR_VoltageScalingConfig() function.\r
+\r
+ (+) When VCORE range 1 is selected and VDD drops below 2.0 V, the application must\r
+ reconfigure the system:\r
+ (++) Detect that VDD drops below 2.0 V using the PVD Level 1.\r
+ (++) Adapt the clock frequency to the voltage range that will be selected at next step.\r
+ (++) Select the required voltage range.\r
+ (++) When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system\r
+ reconfiguration is required.\r
+ \r
+ (+) When VDD is above 2.0 V, any of the 3 voltage ranges can be selected.\r
+ (++) When the voltage range is above the targeted voltage range (e.g. from range \r
+ 1 to 2).\r
+ (++) Adapt the clock frequency to the lower voltage range that will be selected \r
+ at next step.\r
+ (++) Select the required voltage range.\r
+ (++) When the voltage range is below the targeted voltage range (e.g. from range \r
+ 3 to 1).\r
+ (++) Select the required voltage range.\r
+ (++) Tune the clock frequency if needed.\r
+ \r
+ (+) When VDD is below 2.0 V, only range 2 and 3 can be selected:\r
+ (++) From range 2 to range 3.\r
+ (+++) Adapt the clock frequency to voltage range 3.\r
+ (+++) Select voltage range 3.\r
+ (++) From range 3 to range 2.\r
+ (+++) Select the voltage range 2.\r
+ (+++) Tune the clock frequency if needed.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage scaling range.\r
+ * @note During voltage scaling configuration, the system clock is stopped \r
+ * until the regulator is stabilized (VOSF = 0). This must be taken \r
+ * into account during application developement, in case a critical \r
+ * reaction time to interrupt is needed, and depending on peripheral \r
+ * used (timer, communication,...).\r
+ * \r
+ * @param PWR_VoltageScaling: specifies the voltage scaling range.\r
+ * This parameter can be:\r
+ * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V).\r
+ * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V).\r
+ * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V) \r
+ * @retval None\r
+ */\r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));\r
+ \r
+ tmp = PWR->CR;\r
+\r
+ tmp &= CR_VOS_MASK;\r
+ tmp |= PWR_VoltageScaling;\r
+ \r
+ PWR->CR = tmp & 0xFFFFFFF3;\r
+\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group6 Low Power modes configuration functions\r
+ * @brief Low Power modes configuration functions \r
+ *\r
+@verbatim \r
+ ============================================================================== \r
+ ##### Low Power modes configuration functions #####\r
+ ============================================================================== \r
+\r
+ [..] The devices feature five low-power modes:\r
+ (+) Low power run mode: regulator in low power mode, limited clock frequency, \r
+ limited number of peripherals running.\r
+ (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.\r
+ (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, \r
+ limited number of peripherals running, regulator in low power mode.\r
+ (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode.\r
+ (+) Standby mode: VCORE domain powered off.\r
+ \r
+ *** Low power run mode (LP run) *** \r
+ ===================================\r
+ [..]\r
+ (+) Entry:\r
+ (++) Decrease the system frequency.\r
+ (++) The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()\r
+ function.\r
+ (+) Exit:\r
+ (++) The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()\r
+ function.\r
+ (++) Increase the system frequency if needed.\r
+\r
+ *** Sleep mode *** \r
+ ==================\r
+ [..] \r
+ (+) Entry:\r
+ (++) The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,) \r
+ function with regulator ON.\r
+ (+) Exit:\r
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ *** Low power sleep mode (LP sleep) *** \r
+ =======================================\r
+ [..] \r
+ (+) Entry:\r
+ (++) The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()\r
+ function.\r
+ (++) Decrease the system frequency.\r
+ (++) The regulator is forced in low power mode and the WFI or WFE instructions\r
+ are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function \r
+ with regulator in LowPower.\r
+ (+) Exit:\r
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep LP mode.\r
+\r
+ *** Stop mode *** \r
+ =================\r
+ [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,\r
+ the HSI and the HSE RC oscillators are disabled. Internal SRAM and register \r
+ contents are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+ To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature\r
+ sensor can be switched off before entering the Stop mode. They can be switched \r
+ on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()\r
+ function. \r
+ \r
+ (+) Entry:\r
+ (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) \r
+ function with regulator in LowPower or with Regulator ON.\r
+ (+) Exit:\r
+ (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+ \r
+ *** Standby mode *** \r
+ ====================\r
+ [..] The Standby mode allows to achieve the lowest power consumption. It is based \r
+ on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. \r
+ The VCORE domain is consequently powered off. The PLL, the MSI, the HSI \r
+ oscillator and the HSE oscillator are also switched off. SRAM and register \r
+ contents are lost except for the RTC registers, RTC backup registers and \r
+ Standby circuitry.\r
+ \r
+ [..] The voltage regulator is OFF.\r
+ \r
+ [..] To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature\r
+ sensor can be switched off before entering the Standby mode. They can be switched \r
+ on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()\r
+ function. \r
+ \r
+ (+) Entry:\r
+ (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.\r
+ (+) Exit:\r
+ (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,\r
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode *** \r
+ =============================================\r
+ [..]The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
+ Wakeup event, a tamper event, a time-stamp event, or a comparator event, \r
+ without depending on an external interrupt (Auto-wakeup mode).\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Stop mode\r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:\r
+ (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
+ (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
+ and RTC_AlarmCmd() functions.\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
+ is necessary to:\r
+ (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
+ function.\r
+ (+++) Configure the RTC to detect the tamper or time stamp event using the\r
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
+ functions.\r
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:\r
+ (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.\r
+ (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
+ RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Standby mode\r
+ (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:\r
+ (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.\r
+ (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
+ and RTC_AlarmCmd() functions.\r
+ (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it \r
+ is necessary to:\r
+ (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
+ function.\r
+ (+++) Configure the RTC to detect the tamper or time stamp event using the\r
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
+ functions.\r
+ (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:\r
+ (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
+ (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
+ RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
+\r
+ (+) Comparator auto-wakeup (AWU) from the Stop mode\r
+ (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup\r
+ event, it is necessary to:\r
+ (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 \r
+ to be sensitive to to the selected edges (falling, rising or falling \r
+ and rising) (Interrupt or Event modes) using the EXTI_Init() function.\r
+ (+++) Configure the comparator to generate the event.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enters/Exits the Low Power Run mode.\r
+ * @note Low power run mode can only be entered when VCORE is in range 2.\r
+ * In addition, the dynamic voltage scaling must not be used when Low \r
+ * power run mode is selected. Only Stop and Sleep modes with regulator \r
+ * configured in Low power mode is allowed when Low power run mode is \r
+ * selected. \r
+ * @note In Low power run mode, all I/O pins keep the same state as in Run mode.\r
+ * @param NewState: new state of the Low Power Run mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ PWR->CR |= PWR_CR_LPSDSR;\r
+ PWR->CR |= PWR_CR_LPRUN; \r
+ }\r
+ else\r
+ {\r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); \r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode. \r
+ * @param PWR_Regulator: specifies the regulator state in Sleep mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: Sleep mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode\r
+ * @note Low power sleep mode can only be entered when VCORE is in range 2.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Low power sleep mode.\r
+ * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+\r
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));\r
+ \r
+ /* Select the regulator state in Sleep mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
+ \r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters STOP mode.\r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the MSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced.\r
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON.\r
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode.\r
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction.\r
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction.\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
+}\r
+\r
+/**\r
+ * @brief Enters STANDBY mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * Reset pad (still available) \r
+ * RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, \r
+ * time-stamp, RTC Alarm out, or RTC clock calibration out.\r
+ * WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Clear Wakeup flag */\r
+ PWR->CR |= PWR_CR_CWUF;\r
+ \r
+ /* Select STANDBY mode */\r
+ PWR->CR |= PWR_CR_PDDS;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM )\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group7 Flags management functions\r
+ * @brief Flags management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Flags management functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified PWR flag is set or not.\r
+ * @param PWR_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r
+ * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), \r
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.\r
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
+ * resumed from StandBy mode. \r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r
+ * by the PWR_PVDCmd() function.\r
+ * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This \r
+ * flag indicates the state of the internal voltage reference, VREFINT.\r
+ * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for \r
+ * the internal regulator to be ready after the voltage range is changed.\r
+ * The VOSF flag indicates that the regulator has reached the voltage level \r
+ * defined with bits VOS[1:0] of PWR_CR register.\r
+ * @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware \r
+ * when the MCU is in Low power run mode.\r
+ * When the MCU exits from Low power run mode, this flag stays SET until \r
+ * the regulator is ready in main mode. A polling on this flag is \r
+ * recommended to wait for the regulator main mode. \r
+ * This flag is RESET by hardware when the regulator is ready. \r
+ * @retval The new state of PWR_FLAG (SET or RESET).\r
+ */\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
+ \r
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the PWR's pending flags.\r
+ * @param PWR_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @retval None\r
+ */\r
+void PWR_ClearFlag(uint32_t PWR_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+ \r
+ PWR->CR |= PWR_FLAG << 2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Reset and clock control (RCC) peripheral: \r
+ * + Internal/external clocks, PLL, CSS and MCO configuration\r
+ * + System, AHB and APB busses clocks configuration\r
+ * + Peripheral clocks configuration\r
+ * + Interrupts and flags management\r
+ *\r
+ @verbatim\r
+\r
+ ===============================================================================\r
+ ##### RCC specific features #####\r
+ ===============================================================================\r
+ [..] After reset the device is running from MSI (2 MHz) with Flash 0 WS, \r
+ all peripherals are off except internal SRAM, Flash and JTAG.\r
+ (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
+ all peripherals mapped on these busses are running at MSI speed.\r
+ (#) The clock for all peripherals is switched off, except the SRAM and \r
+ FLASH.\r
+ (#) All GPIOs are in input floating state, except the JTAG pins which\r
+ are assigned to be used for debug purpose.\r
+ [..] Once the device started from reset, the user application has to:\r
+ (#) Configure the clock source to be used to drive the System clock\r
+ (if the application needs higher frequency/performance)\r
+ (#) Configure the System clock frequency and Flash settings\r
+ (#) Configure the AHB and APB busses prescalers\r
+ (#) Enable the clock for the peripheral(s) to be used\r
+ (#) Configure the clock source(s) for peripherals whose clocks are not\r
+ derived from the System clock (ADC, RTC/LCD and IWDG)\r
+\r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC \r
+ * @brief RCC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of MSION bit */\r
+#define MSION_BitNumber 0x08\r
+#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x1C\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x34)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+/* Alias word address of LSECSSON bit */\r
+#define LSECSSON_BitNumber 0x0B\r
+#define CSR_LSECSSON_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSECSSON_BitNumber * 4))\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define RTCEN_BitNumber 0x16\r
+#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of RTCRST bit */\r
+#define RTCRST_BitNumber 0x17\r
+#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))\r
+\r
+\r
+/* ---------------------- RCC registers mask -------------------------------- */\r
+/* RCC Flag Mask */\r
+#define FLAG_MASK ((uint8_t)0x1F)\r
+\r
+/* CR register byte 3 (Bits[23:16]) base address */\r
+#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)\r
+\r
+/* ICSCR register byte 4 (Bits[31:24]) base address */\r
+#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)\r
+\r
+/* CFGR register byte 3 (Bits[23:16]) base address */\r
+#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)\r
+\r
+/* CSR register byte 2 (Bits[15:8]) base address */\r
+#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to configure the internal/external \r
+ clocks, PLL, CSS and MCO.\r
+ (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly \r
+ or through the PLL as System clock source.\r
+ (#) MSI (multi-speed internal), multispeed low power RC \r
+ (65.536 KHz to 4.194 MHz) MHz used as System clock source.\r
+ (#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG \r
+ and/or RTC clock source.\r
+ (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used \r
+ directly or through the PLL as System clock source. Can be used \r
+ also as RTC clock source.\r
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.\r
+ (#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).\r
+ (#) CSS (Clock security system), once enable and if a HSE clock failure \r
+ occurs (HSE used directly or through PLL as System clock source), \r
+ the System clock is automatically switched to MSI and an interrupt \r
+ is generated if enabled. \r
+ The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) \r
+ exception vector.\r
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI, \r
+ HSE, PLL, LSI or LSE clock (through a configurable prescaler) on \r
+ PA8 pin.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note The default reset state of the clock configuration is given below:\r
+ * @note MSI ON and used as system clock source (MSI range is not modified\r
+ * by this function, it keep the value configured by user application)\r
+ * @note HSI, HSE and PLL OFF\r
+ * @note AHB, APB1 and APB2 prescaler set to 1.\r
+ * @note CSS and MCO OFF\r
+ * @note All interrupts disabled\r
+ * @note However, this function doesn't modify the configuration of the\r
+ * @note Peripheral clocks\r
+ * @note LSI, LSE and RTC clocks \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_DeInit(void)\r
+{\r
+ \r
+ /* Set MSION bit */\r
+ RCC->CR |= (uint32_t)0x00000100;\r
+\r
+ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+ RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+ \r
+ /* Reset HSION, HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External High Speed oscillator (HSE).\r
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * @note HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @note This function reset the CSSON bit, so if the Clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function.\r
+ * @param RCC_HSE: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator\r
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_HSEConfig(uint8_t RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r
+\r
+ /* Set the new HSE configuration -------------------------------------------*/\r
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Waits for HSE start-up.\r
+ * @note This functions waits on HSERDY flag to be set and return SUCCESS if \r
+ * this flag is set, otherwise returns ERROR if the timeout is reached \r
+ * and this flag is not set. The timeout value is defined by the constant\r
+ * HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending\r
+ * on the HSE crystal used in your application. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: HSE oscillator is stable and ready to use\r
+ * - ERROR: HSE oscillator not yet ready\r
+ */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ FlagStatus HSEStatus = RESET;\r
+ \r
+ /* Wait till HSE is ready and if timeout is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ StartUpCounter++; \r
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
+ \r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal MSI RC.\r
+ * Refer to the Application Note AN3300 for more details on how to \r
+ * calibrate the MSI.\r
+ * @param MSICalibrationValue: specifies the MSI calibration trimming value.\r
+ * This parameter must be a number between 0 and 0xFF.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)\r
+{\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));\r
+\r
+ *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue; \r
+}\r
+\r
+/**\r
+ * @brief Configures the Internal Multi Speed oscillator (MSI) clock range.\r
+ * @note After restart from Reset or wakeup from STANDBY, the MSI clock is \r
+ * around 2.097 MHz. The MSI clock does not change after wake-up from\r
+ * STOP mode.\r
+ * @note The MSI clock range can be modified on the fly. \r
+ * @param RCC_MSIRange: specifies the MSI Clock range.\r
+ * This parameter must be one of the following values:\r
+ * @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz\r
+ * @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz\r
+ * @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz\r
+ * @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz\r
+ * @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz\r
+ * @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)\r
+ * @arg RCC_MSIRange_6: MSI clock is around 4.194 MHz\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));\r
+ \r
+ tmpreg = RCC->ICSCR;\r
+ \r
+ /* Clear MSIRANGE[2:0] bits */\r
+ tmpreg &= ~RCC_ICSCR_MSIRANGE;\r
+ \r
+ /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */\r
+ tmpreg |= (uint32_t)RCC_MSIRange;\r
+\r
+ /* Store the new value */\r
+ RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Multi Speed oscillator (MSI).\r
+ * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled). \r
+ * @note MSI can not be stopped if it is used as system clock source.\r
+ * In this case, you have to select another source of the system\r
+ * clock then stop the MSI. \r
+ * @note After enabling the MSI, the application software should wait on\r
+ * MSIRDY flag to be set indicating that MSI clock is stable and can\r
+ * be used as system clock source. \r
+ * @param NewState: new state of the MSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_MSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * Refer to the Application Note AN3300 for more details on how to \r
+ * calibrate the HSI.\r
+ * @param HSICalibrationValue: specifies the HSI calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
+ \r
+ tmpreg = RCC->ICSCR;\r
+ \r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= ~RCC_ICSCR_HSITRIM;\r
+ \r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (uint32_t)HSICalibrationValue << 8;\r
+\r
+ /* Store the new value */\r
+ RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @note After enabling the HSI, the application software should wait on \r
+ * HSIRDY flag to be set indicating that HSI clock is stable and can\r
+ * be used to clock the PLL and/or system clock.\r
+ * @note HSI can not be stopped if it is used directly or through the PLL\r
+ * as system clock. In this case, you have to select another source \r
+ * of the system clock then stop the HSI.\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @param NewState: new state of the HSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE).\r
+ * @note As the LSE is in the RTC domain and write access is denied to this\r
+ * domain after reset, you have to enable write access using \r
+ * PWR_RTCAccessCmd(ENABLE) function before to configure the LSE\r
+ * (to be done once after reset). \r
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param RCC_LSE: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator\r
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+ \r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;\r
+\r
+ /* Set the new LSE configuration -------------------------------------------*/\r
+ *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI). \r
+ * @note After enabling the LSI, the application software should wait on \r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * @note LSI can not be disabled if the IWDG is running. \r
+ * @param NewState: new state of the LSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL clock source and multiplication factor.\r
+ * @note This function must be used only when the PLL is disabled.\r
+ * \r
+ * @param RCC_PLLSource: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source\r
+ * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source\r
+ * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as\r
+ * PLL source).\r
+ * \r
+ * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock\r
+ * This parameter can be:\r
+ * @arg RCC_PLLMul_3: PLL clock source multiplied by 3\r
+ * @arg RCC_PLLMul_4: PLL clock source multiplied by 4\r
+ * @arg RCC_PLLMul_6: PLL clock source multiplied by 6\r
+ * @arg RCC_PLLMul_8: PLL clock source multiplied by 8\r
+ * @arg RCC_PLLMul_12: PLL clock source multiplied by 12\r
+ * @arg RCC_PLLMul_16: PLL clock source multiplied by 16 \r
+ * @arg RCC_PLLMul_24: PLL clock source multiplied by 24\r
+ * @arg RCC_PLLMul_32: PLL clock source multiplied by 32\r
+ * @arg RCC_PLLMul_48: PLL clock source multiplied by 48\r
+ * @note The application software must set correctly the PLL multiplication\r
+ * factor to avoid exceeding:\r
+ * - 96 MHz as PLLVCO when the product is in range 1\r
+ * - 48 MHz as PLLVCO when the product is in range 2\r
+ * - 24 MHz when the product is in range 3\r
+ * @note When using the USB the PLLVCO should be 96MHz\r
+ * \r
+ * @param RCC_PLLDiv: specifies the PLL division factor.\r
+ * This parameter can be:\r
+ * @arg RCC_PLLDiv_2: PLL Clock output divided by 2 \r
+ * @arg RCC_PLLDiv_3: PLL Clock output divided by 3 \r
+ * @arg RCC_PLLDiv_4: PLL Clock output divided by 4 \r
+ * @note The application software must set correctly the output division to avoid\r
+ * exceeding 32 MHz as SYSCLK.\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+ assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));\r
+ \r
+ *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PLL.\r
+ * @note After enabling the PLL, the application software should wait on \r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * @note The PLL can not be disabled if it is used as system clock source\r
+ * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. \r
+ * @param NewState: new state of the PLL.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to \r
+ * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. \r
+ * @param NewState: new state of the Clock Security System.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the LSE Clock Security System.\r
+ * @param NewState: new state of the Clock Security System.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO pin (PA8).\r
+ * @note PA8 should be configured in alternate function mode. \r
+ * @param RCC_MCOSource: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCOSource_NoClock: No clock selected\r
+ * @arg RCC_MCOSource_SYSCLK: System clock selected\r
+ * @arg RCC_MCOSource_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCOSource_MSI: MSI oscillator clock selected \r
+ * @arg RCC_MCOSource_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCOSource_PLLCLK: PLL clock selected\r
+ * @arg RCC_MCOSource_LSI: LSI clock selected\r
+ * @arg RCC_MCOSource_LSE: LSE clock selected \r
+ * @param RCC_MCODiv: specifies the MCO prescaler.\r
+ * This parameter can be one of the following values: \r
+ * @arg RCC_MCODiv_1: no division applied to MCO clock \r
+ * @arg RCC_MCODiv_2: division by 2 applied to MCO clock\r
+ * @arg RCC_MCODiv_4: division by 4 applied to MCO clock\r
+ * @arg RCC_MCODiv_8: division by 8 applied to MCO clock\r
+ * @arg RCC_MCODiv_16: division by 16 applied to MCO clock \r
+ * @retval None\r
+ */\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
+ assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));\r
+ \r
+ /* Select MCO clock source and prescaler */\r
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions\r
+ * @brief System, AHB and APB busses clocks configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### System, AHB and APB busses clocks configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to configure the System, AHB, \r
+ APB1 and APB2 busses clocks.\r
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): \r
+ MSI, HSI, HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable \r
+ prescaler and used to clock the CPU, memory and peripherals mapped \r
+ on AHB bus (DMA and GPIO).APB1 (PCLK1) and APB2 (PCLK2) clocks are \r
+ derived from AHB clock through configurable prescalers and used to \r
+ clock the peripherals mapped on these busses. You can use \r
+ "RCC_GetClocksFreq()" function to retrieve the frequencies of these \r
+ clocks. \r
+\r
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) \r
+ except:\r
+ (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.\r
+ (+@) The ADC clock which is always the HSI clock. A divider by 1, 2 \r
+ or 4 allows to adapt the clock frequency to the device operating \r
+ conditions. \r
+ (+@) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz \r
+ HSE_RTC (HSE divided by a programmable prescaler).\r
+ The System clock (SYSCLK) frequency must be higher or equal to \r
+ the RTC/LCD clock frequency.\r
+ (+@) IWDG clock which is always the LSI clock.\r
+ \r
+ (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.\r
+ Depending on the device voltage range, the maximum frequency should \r
+ be adapted accordingly:\r
+\r
+ +----------------------------------------------------------------+\r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------|\r
+ | (Latency) | voltage range | voltage range |\r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------|\r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |-------------- |----------------|---------------|---------------|\r
+ |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |---------------|----------------|---------------|---------------|\r
+ |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
+ +----------------------------------------------------------------+\r
+\r
+ (#) After reset, the System clock source is the MSI (2 MHz) with 0 WS, \r
+ Flash 32-bit access is enabled and prefetch is disabled.\r
+ [..] It is recommended to use the following software sequences to tune the \r
+ number of wait states needed to access the Flash memory with the CPU \r
+ frequency (HCLK).\r
+ (+) Increasing the CPU frequency (in the same voltage range)\r
+ (+) Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)" \r
+ function\r
+ (+) Check that 64-bit access is taken into account by reading FLASH_ACR\r
+ (+) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" \r
+ function\r
+ (+) Check that the new number of WS is taken into account by reading \r
+ FLASH_ACR\r
+ (+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
+ (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" \r
+ function\r
+ (+) Check that the new CPU clock source is taken into account by reading \r
+ the clock source status, using "RCC_GetSYSCLKSource()" function \r
+ (+) Decreasing the CPU frequency (in the same voltage range)\r
+ (+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
+ (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" \r
+ function\r
+ (+) Check that the new CPU clock source is taken into account by reading \r
+ the clock source status, using "RCC_GetSYSCLKSource()" function\r
+ (+) Program the new number of WS, using "FLASH_SetLatency()" function\r
+ (+) Check that the new number of WS is taken into account by reading \r
+ FLASH_ACR\r
+ (+) Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)" \r
+ function\r
+ (+) Check that 32-bit access is taken into account by reading FLASH_ACR\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the system clock (SYSCLK).\r
+ * @note The MSI is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ * @note A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after startup delay or PLL locked). \r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready. \r
+ * You can use RCC_GetSYSCLKSource() function to know which clock is\r
+ * currently used as system clock source. \r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock source \r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source\r
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source\r
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source\r
+ * @retval None\r
+ */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= ~RCC_CFGR_SW;\r
+ \r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval The clock source used as system clock. The returned value can be one \r
+ * of the following values:\r
+ * - 0x00: MSI used as system clock\r
+ * - 0x04: HSI used as system clock \r
+ * - 0x08: HSE used as system clock\r
+ * - 0x0C: PLL used as system clock\r
+ */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the AHB clock (HCLK).\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * these bits to ensure that the system frequency does not exceed the\r
+ * maximum allowed frequency (for more details refer to section above\r
+ * "CPU, AHB and APB busses clocks configuration functions")\r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * the system clock (SYSCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+ * @retval None\r
+ */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= ~RCC_CFGR_HPRE;\r
+ \r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Low Speed APB clock (PCLK1).\r
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear PPRE1[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE1;\r
+ \r
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the High Speed APB clock (PCLK2).\r
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear PPRE2[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE2;\r
+ \r
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK << 3;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the frequencies of the System, AHB and APB busses clocks.\r
+ * @note The frequency returned by this function is not the real frequency\r
+ * in the chip. It is calculated based on the predefined constant and\r
+ * the source selected by RCC_SYSCLKConfig():\r
+ * \r
+ * @note If SYSCLK source is MSI, function returns values based on MSI\r
+ * Value as defined by the MSI range, refer to RCC_MSIRangeConfig()\r
+ * \r
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
+ * \r
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
+ * \r
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * return wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal. \r
+ * \r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
+ * the clocks frequencies. \r
+ * \r
+ * @note This function can be used by the user application to compute the \r
+ * baudrate for the communication peripherals or configure other parameters.\r
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function\r
+ * must be called to update the structure's field. Otherwise, any\r
+ * configuration based on this function will be incorrect.\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
+ RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ case 0x04: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ case 0x08: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+ break;\r
+ case 0x0C: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+ pllmul = PLLMulTable[(pllmul >> 18)];\r
+ plldiv = (plldiv >> 22) + 1;\r
+ \r
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+ if (pllsource == 0x00)\r
+ {\r
+ /* HSI oscillator clock selected as PLL clock source */\r
+ RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);\r
+ }\r
+ else\r
+ {\r
+ /* HSE selected as PLL clock source */\r
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);\r
+ }\r
+ break;\r
+ default: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
+ RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ }\r
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp]; \r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r
+ tmp = tmp >> 11;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r
+ * @brief Peripheral clocks configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral clocks configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to configure the Peripheral clocks. \r
+ (#) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC \r
+ (HSE divided by a programmable prescaler).\r
+ (#) After restart from Reset or wakeup from STANDBY, all peripherals are \r
+ off except internal SRAM, Flash and JTAG. Before to start using a \r
+ peripheral you have to enable its interface clock. You can do this \r
+ using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and \r
+ RCC_APB1PeriphClockCmd() functions.\r
+\r
+ (#) To reset the peripherals configuration (to the default state after \r
+ device reset) you can use RCC_AHBPeriphResetCmd(), \r
+ RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions.\r
+ (#) To further reduce power consumption in SLEEP mode the peripheral \r
+ clocks can be disabled prior to executing the WFI or WFE instructions.\r
+ You can do this using RCC_AHBPeriphClockLPModeCmd(), \r
+ RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() \r
+ functions.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).\r
+ * @note As the RTC clock configuration bits are in the RTC domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using PWR_RTCAccessCmd(ENABLE) function before to configure\r
+ * the RTC clock source (to be done once after reset). \r
+ * @note Once the RTC clock is configured it can't be changed unless the RTC\r
+ * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)\r
+ * @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).\r
+ * \r
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock\r
+ * \r
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes.\r
+ * \r
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+ \r
+ if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)\r
+ { \r
+ /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
+ tmpreg = RCC->CR;\r
+\r
+ /* Clear RTCPRE[1:0] bits */\r
+ tmpreg &= ~RCC_CR_RTCPRE;\r
+\r
+ /* Configure HSE division factor for RTC clock */\r
+ tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);\r
+\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+ }\r
+ \r
+ RCC->CSR &= ~RCC_CSR_RTCSEL;\r
+ \r
+ /* Select the RTC clock source */\r
+ RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock.\r
+ * @note This function must be used only after the RTC clock source was selected\r
+ * using the RCC_RTCCLKConfig function.\r
+ * @param NewState: new state of the RTC clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases the RTC peripheral and associated resources reset.\r
+ * @note This function resets the RTC peripheral, RTC clock source selection\r
+ * (in RCC_CSR) and the backup registers.\r
+ * @param NewState: new state of the RTC reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA: GPIOA clock\r
+ * @arg RCC_AHBPeriph_GPIOB: GPIOB clock\r
+ * @arg RCC_AHBPeriph_GPIOC: GPIOC clock\r
+ * @arg RCC_AHBPeriph_GPIOD: GPIOD clock\r
+ * @arg RCC_AHBPeriph_GPIOE: GPIOE clock\r
+ * @arg RCC_AHBPeriph_GPIOH: GPIOH clock\r
+ * @arg RCC_AHBPeriph_GPIOF: GPIOF clock\r
+ * @arg RCC_AHBPeriph_GPIOG: GPIOG clock\r
+ * @arg RCC_AHBPeriph_CRC: CRC clock\r
+ * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_DMA1: DMA1 clock\r
+ * @arg RCC_AHBPeriph_DMA2: DMA2 clock\r
+ * @arg RCC_AHBPeriph_AES: AES clock\r
+ * @arg RCC_AHBPeriph_FSMC: FSMC clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG APB2 Clock.\r
+ * @arg RCC_APB2Periph_TIM9: TIM9 APB2 Clock.\r
+ * @arg RCC_APB2Periph_TIM10: TIM10 APB2 Clock.\r
+ * @arg RCC_APB2Periph_TIM11: TIM11 APB2 Clock.\r
+ * @arg RCC_APB2Periph_ADC1: ADC1 APB2 Clock.\r
+ * @arg RCC_APB2Periph_SDIO: SDIO APB2 Clock.\r
+ * @arg RCC_APB2Periph_SPI1: SPI1 APB2 Clock.\r
+ * @arg RCC_APB2Periph_USART1: USART1 APB2 Clock.\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock\r
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock\r
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock\r
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock \r
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock\r
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock\r
+ * @arg RCC_APB1Periph_LCD: LCD clock\r
+ * @arg RCC_APB1Periph_WWDG: WWDG clock\r
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock\r
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock\r
+ * @arg RCC_APB1Periph_USART2: USART2 clock\r
+ * @arg RCC_APB1Periph_USART3: USART3 clock\r
+ * @arg RCC_APB1Periph_UART4: UART4 clock\r
+ * @arg RCC_APB1Periph_UART5: UART5 clock \r
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock\r
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock\r
+ * @arg RCC_APB1Periph_USB: USB clock\r
+ * @arg RCC_APB1Periph_PWR: PWR clock\r
+ * @arg RCC_APB1Periph_DAC: DAC clock\r
+ * @arg RCC_APB1Periph_COMP COMP clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases AHB peripheral reset.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA: GPIOA clock\r
+ * @arg RCC_AHBPeriph_GPIOB: GPIOB clock\r
+ * @arg RCC_AHBPeriph_GPIOC: GPIOC clock \r
+ * @arg RCC_AHBPeriph_GPIOD: GPIOD clock\r
+ * @arg RCC_AHBPeriph_GPIOE: GPIOE clock\r
+ * @arg RCC_AHBPeriph_GPIOH: GPIOH clock\r
+ * @arg RCC_AHBPeriph_GPIOF: GPIOF clock\r
+ * @arg RCC_AHBPeriph_GPIOG: GPIOG clock \r
+ * @arg RCC_AHBPeriph_CRC: CRC clock\r
+ * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_DMA1: DMA1 clock\r
+ * @arg RCC_AHBPeriph_DMA2: DMA2 clock\r
+ * @arg RCC_AHBPeriph_AES: AES clock\r
+ * @arg RCC_AHBPeriph_FSMC: FSMC clock \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBRSTR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock \r
+ * @arg RCC_APB2Periph_TIM10: TIM10 clock\r
+ * @arg RCC_APB2Periph_TIM11: TIM11 clock\r
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock\r
+ * @arg RCC_APB2Periph_SDIO: SDIO clock\r
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock\r
+ * @arg RCC_APB2Periph_USART1: USART1 clock\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock\r
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock\r
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock\r
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock \r
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock\r
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock\r
+ * @arg RCC_APB1Periph_LCD: LCD clock\r
+ * @arg RCC_APB1Periph_WWDG: WWDG clock\r
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock\r
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock \r
+ * @arg RCC_APB1Periph_USART2: USART2 clock\r
+ * @arg RCC_APB1Periph_USART3: USART3 clock\r
+ * @arg RCC_APB1Periph_UART4: UART4 clock\r
+ * @arg RCC_APB1Periph_UART5: UART5 clock \r
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock\r
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock\r
+ * @arg RCC_APB1Periph_USB: USB clock\r
+ * @arg RCC_APB1Periph_PWR: PWR clock\r
+ * @arg RCC_APB1Periph_DAC: DAC clock\r
+ * @arg RCC_APB1Periph_COMP \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock during SLEEP mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * - By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA: GPIOA clock\r
+ * @arg RCC_AHBPeriph_GPIOB: GPIOB clock\r
+ * @arg RCC_AHBPeriph_GPIOC: GPIOC clock \r
+ * @arg RCC_AHBPeriph_GPIOD: GPIOD clock\r
+ * @arg RCC_AHBPeriph_GPIOE: GPIOE clock\r
+ * @arg RCC_AHBPeriph_GPIOH: GPIOH clock\r
+ * @arg RCC_AHBPeriph_GPIOF: GPIOF clock\r
+ * @arg RCC_AHBPeriph_GPIOG: GPIOG clock \r
+ * @arg RCC_AHBPeriph_CRC: CRC clock\r
+ * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_SRAM: SRAM clock \r
+ * @arg RCC_AHBPeriph_DMA1: DMA1 clock\r
+ * @arg RCC_AHBPeriph_DMA2: DMA2 clock\r
+ * @arg RCC_AHBPeriph_AES: AES clock\r
+ * @arg RCC_AHBPeriph_FSMC: FSMC clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBLPENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBLPENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the APB2 peripheral clock during SLEEP mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock\r
+ * @arg RCC_APB2Periph_TIM10: TIM10 clock\r
+ * @arg RCC_APB2Periph_TIM11: TIM11 clock\r
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock\r
+ * @arg RCC_APB2Periph_SDIO: SDIO clock \r
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock\r
+ * @arg RCC_APB2Periph_USART1: USART1 clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2LPENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2LPENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the APB1 peripheral clock during SLEEP mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock\r
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock\r
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock\r
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock\r
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock\r
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock\r
+ * @arg RCC_APB1Periph_LCD: LCD clock\r
+ * @arg RCC_APB1Periph_WWDG: WWDG clock\r
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock\r
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock\r
+ * @arg RCC_APB1Periph_USART2: USART2 clock\r
+ * @arg RCC_APB1Periph_USART3: USART3 clock\r
+ * @arg RCC_APB1Periph_UART4: UART4 clock\r
+ * @arg RCC_APB1Periph_UART5: UART5 clock \r
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock\r
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock\r
+ * @arg RCC_APB1Periph_USB: USB clock\r
+ * @arg RCC_APB1Periph_PWR: PWR clock\r
+ * @arg RCC_APB1Periph_DAC: DAC clock\r
+ * @arg RCC_APB1Periph_COMP: COMP clock\r
+ * @param NewState: new state \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1LPENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1LPENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group4 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RCC interrupts.\r
+ * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled\r
+ * and if the HSE clock fails, the CSS interrupt occurs and an NMI is\r
+ * automatically generated. The NMI will be executed indefinitely, and \r
+ * since NMI has higher priority than any other IRQ (and main program)\r
+ * the application will be stacked in the NMI ISR unless the CSS interrupt\r
+ * pending bit is cleared.\r
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt\r
+ * @arg RCC_IT_LSECSS: LSE CSS interrupt \r
+ * @param NewState: new state of the specified RCC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC flag is set or not.\r
+ * @param RCC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready \r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected \r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * @retval The new state of RCC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else /* The flag to check is in CSR register (tmp == 2) */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_MASK;\r
+\r
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC reset flags.\r
+ * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= RCC_CSR_RMVF;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC interrupt has occurred or not.\r
+ * @param RCC_IT: specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt \r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt\r
+ * @arg RCC_IT_LSECSS: LSE CSS interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval The new state of RCC_IT (SET or RESET).\r
+ */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+ \r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC's interrupt pending bits.\r
+ * @param RCC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
+ * @arg RCC_IT_LSECSS: LSE CSS interrupt\r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval None\r
+ */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+ \r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rtc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Real-Time Clock (RTC) peripheral:\r
+ * + Initialization\r
+ * + Calendar (Time and Date) configuration\r
+ * + Alarms (Alarm A and Alarm B) configuration\r
+ * + WakeUp Timer configuration\r
+ * + Daylight Saving configuration\r
+ * + Output pin Configuration\r
+ * + Coarse digital Calibration configuration\r
+ * + Smooth digital Calibration configuration\r
+ * + TimeStamp configuration\r
+ * + Tampers configuration\r
+ * + Backup Data Registers configuration\r
+ * + Output Type Config configuration\r
+ * + Shift control synchronisation \r
+ * + Interrupts and flags management \r
+ * \r
+ @verbatim\r
+\r
+ ===============================================================================\r
+ ##### RTC Domain Reset #####\r
+ ===============================================================================\r
+ [..] After power-on reset, the RTC domain (RTC clock source configuration,\r
+ RTC registers and RTC Backup data registers) is reset. You can also\r
+ reset this domain by software using the RCC_RTCResetCmd() function.\r
+\r
+ ##### RTC Operating Condition #####\r
+ ===============================================================================\r
+ [..] As long as the supply voltage remains in the operating range, \r
+ the RTC never stops, regardless of the device status (Run mode, \r
+ low power modes or under reset).\r
+\r
+ ##### RTC Domain Access #####\r
+ ===============================================================================\r
+ [..] After reset, the RTC domain (RTC clock source configuration,\r
+ RTC registers and RTC Backup data registers) are protected against \r
+ possible stray write accesses. \r
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ RCC_APB1PeriphClockCmd() function.\r
+ (+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.\r
+ (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.\r
+ (+) Enable RTC Clock using the RCC_RTCCLKCmd() function.\r
+\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (+) Enable the RTC domain access (see description in the section above)\r
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and\r
+ RTC hour format using the RTC_Init() function.\r
+ ***Time and Date configuration ***\r
+ ==================================\r
+ [..]\r
+ (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()\r
+ and RTC_SetDate() functions.\r
+ (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()\r
+ functions.\r
+ (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.\r
+ (+) Use the RTC_DayLightSavingConfig() function to add or sub one\r
+ hour to the RTC Calendar. \r
+\r
+ ***Alarm configuration ***\r
+ ==========================\r
+ [..]\r
+ (+) To configure the RTC Alarm use the RTC_SetAlarm() function.\r
+ (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function\r
+ (+) To read the RTC Alarm, use the RTC_GetAlarm() function.\r
+ (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.\r
+\r
+ ***RTC Wakeup configuration ***\r
+ ===============================\r
+ [..]\r
+ (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()\r
+ function.\r
+ (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() \r
+ function.\r
+ (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function \r
+ (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() \r
+ function.\r
+\r
+ ***Outputs configuration ***\r
+ ============================\r
+ [..] The RTC has 2 different outputs:\r
+ (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B\r
+ and WaKeUp signals.\r
+ To output the selected RTC signal on RTC_AF1 pin, use the \r
+ RTC_OutputConfig() function.\r
+ (+) AFO_CALIB: this output is 512Hz signal or 1Hz.\r
+ To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()\r
+ function.\r
+\r
+ ***Smooth digital Calibration configuration ***\r
+ ===============================================\r
+ [..]\r
+ (+) Configure the RTC Original Digital Calibration Value and the corresponding\r
+ calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() \r
+ function.\r
+\r
+ ***Coarse digital Calibration configuration ***\r
+ ===============================================\r
+ [..]\r
+ (+) Configure the RTC Coarse Calibration Value and the corresponding\r
+ sign using the RTC_CoarseCalibConfig() function.\r
+ (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() \r
+ function.\r
+\r
+ ***TimeStamp configuration ***\r
+ ==============================\r
+ [..]\r
+ (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp \r
+ using the RTC_TimeStampCmd() function.\r
+ (+) To read the RTC TimeStamp Time and Date register, use the \r
+ RTC_GetTimeStamp() function.\r
+ (+) To read the RTC TimeStamp SubSecond register, use the \r
+ RTC_GetTimeStampSubSecond() function.\r
+\r
+ ***Tamper configuration ***\r
+ ===========================\r
+ [..]\r
+ (+) Configure the Tamper filter count using RTC_TamperFilterConfig()\r
+ function. \r
+ (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper \r
+ filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() \r
+ function.\r
+ (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()\r
+ function.\r
+ (+) Configure the Tamper precharge or discharge duration using \r
+ RTC_TamperPinsPrechargeDuration() function.\r
+ (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.\r
+ (+) Enable the RTC Tamper using the RTC_TamperCmd() function.\r
+ (+) Enable the Time stamp on Tamper detection event using \r
+ RTC_TSOnTamperDetecCmd() function. \r
+\r
+ ***Backup Data Registers configuration ***\r
+ ==========================================\r
+ [..]\r
+ (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()\r
+ function. \r
+ (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()\r
+ function. \r
+\r
+ ##### RTC and low power modes #####\r
+ ===============================================================================\r
+ [..] The MCU can be woken up from a low power mode by an RTC alternate \r
+ function.\r
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r
+ RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r
+ These RTC alternate functions can wake up the system from the Stop \r
+ and Standby lowpower modes.\r
+ The system can also wake up from low power modes without depending \r
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r
+ or the RTC wakeup events.\r
+ [..] The RTC provides a programmable time base for waking up from the \r
+ Stop or Standby mode at regular intervals.\r
+ Wakeup from STOP and Standby modes is possible only when the RTC \r
+ clock source is LSE or LSI.\r
+\r
+ ##### Selection of RTC_AF1 alternate functions #####\r
+ ===============================================================================\r
+ [..] The RTC_AF1 pin (PC13) can be used for the following purposes:\r
+ (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.\r
+ (+) AFO_ALARM output.\r
+ (+) AFO_CALIB output.\r
+ (+) AFI_TAMPER.\r
+ (+) AFI_TIMESTAMP.\r
+\r
+ +------------------------------------------------------------------------------------------+\r
+ | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE |\r
+ | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM |\r
+ | and function | | | | | |Configuration |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Alarm out | | | | | Don't | |\r
+ | output OD | 1 | 0 |Don't care | Don't care | care | 0 |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Alarm out | | | | | Don't | |\r
+ | output PP | 1 | 0 |Don't care | Don't care | care | 1 |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Calibration out | | | | | Don't | |\r
+ | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | TAMPER input | | | | | Don't | |\r
+ | floating | 0 | 0 | 1 | 0 | care | Don't care |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | TIMESTAMP and | | | | | Don't | |\r
+ | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |\r
+ | floating | | | | | | |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | TIMESTAMP input | | | | | Don't | |\r
+ | floating | 0 | 0 | 0 | 1 | care | Don't care |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care |\r
+ +------------------------------------------------------------------------------------------+\r
+\r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_rtc.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC \r
+ * @brief RTC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* Masks Definition */\r
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)\r
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) \r
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) \r
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)\r
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \\r
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \\r
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \\r
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \\r
+ RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \\r
+ RTC_FLAG_SHPF))\r
+\r
+#define INITMODE_TIMEOUT ((uint32_t) 0x00002000)\r
+#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)\r
+#define RECALPF_TIMEOUT ((uint32_t) 0x00001000)\r
+#define SHPF_TIMEOUT ((uint32_t) 0x00002000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static uint8_t RTC_ByteToBcd2(uint8_t Value);\r
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RTC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to initialize and configure the \r
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable \r
+ RTC registers Write protection, enter and exit the RTC initialization mode, \r
+ RTC registers synchronization check and reference clock detection enable.\r
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. \r
+ It is split into 2 programmable prescalers to minimize power consumption.\r
+ (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.\r
+ (++) When both prescalers are used, it is recommended to configure the \r
+ asynchronous prescaler to a high value to minimize consumption.\r
+ (#) All RTC registers are Write protected. Writing to the RTC registers\r
+ is enabled by writing a key into the Write Protection register, RTC_WPR.\r
+ (#) To Configure the RTC Calendar, user application should enter \r
+ initialization mode. In this mode, the calendar counter is stopped \r
+ and its value can be updated. When the initialization sequence is \r
+ complete, the calendar restarts counting after 4 RTCCLK cycles.\r
+ (#) To read the calendar through the shadow registers after Calendar \r
+ initialization, calendar update or after wakeup from low power modes \r
+ the software must first clear the RSF flag. The software must then \r
+ wait until it is set again before reading the calendar, which means \r
+ that the calendar registers have been correctly copied into the \r
+ RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function \r
+ implements the above software sequence (RSF clear and RSF check).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the RTC registers to their default reset values.\r
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data\r
+ * registers. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are deinitialized\r
+ * - ERROR: RTC registers are not deinitialized\r
+ */\r
+ErrorStatus RTC_DeInit(void)\r
+{\r
+ __IO uint32_t wutcounter = 0x00;\r
+ uint32_t wutwfstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Reset TR, DR and CR registers */\r
+ RTC->TR = (uint32_t)0x00000000;\r
+ RTC->DR = (uint32_t)0x00002101;\r
+ \r
+ /* Reset All CR bits except CR[2:0] */\r
+ RTC->CR &= (uint32_t)0x00000007;\r
+ \r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r
+ wutcounter++; \r
+ } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Reset all RTC CR register bits */\r
+ RTC->CR &= (uint32_t)0x00000000;\r
+ RTC->WUTR = (uint32_t)0x0000FFFF;\r
+ RTC->PRER = (uint32_t)0x007F00FF;\r
+ RTC->CALIBR = (uint32_t)0x00000000;\r
+ RTC->ALRMAR = (uint32_t)0x00000000;\r
+ RTC->ALRMBR = (uint32_t)0x00000000;\r
+ RTC->SHIFTR = (uint32_t)0x00000000;\r
+ RTC->CALR = (uint32_t)0x00000000;\r
+ RTC->ALRMASSR = (uint32_t)0x00000000;\r
+ RTC->ALRMBSSR = (uint32_t)0x00000000;\r
+\r
+ /* Reset ISR register and exit initialization mode */\r
+ RTC->ISR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset Tamper and alternate functions configuration register */\r
+ RTC->TAFCR = 0x00000000;\r
+ \r
+ /* Wait till the RTC RSF flag is set */\r
+ if (RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RTC registers according to the specified parameters \r
+ * in RTC_InitStruct.\r
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains \r
+ * the configuration information for the RTC peripheral.\r
+ * @note The RTC Prescaler register is write protected and can be written in \r
+ * initialization mode only. \r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are initialized\r
+ * - ERROR: RTC registers are not initialized \r
+ */\r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));\r
+ assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));\r
+ assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Clear RTC CR FMT Bit */\r
+ RTC->CR &= ((uint32_t)~(RTC_CR_FMT));\r
+ /* Set RTC_CR register */\r
+ RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));\r
+ \r
+ /* Configure the RTC PRER */\r
+ RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);\r
+ RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+\r
+ status = SUCCESS; \r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_InitStruct member with its default value.\r
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)\r
+{\r
+ /* Initialize the RTC_HourFormat member */\r
+ RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;\r
+ \r
+ /* Initialize the RTC_AsynchPrediv member */\r
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;\r
+\r
+ /* Initialize the RTC_SynchPrediv member */\r
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC registers write protection.\r
+ * @note All the RTC registers are write protected except for RTC_ISR[13:8], \r
+ * RTC_TAFCR and RTC_BKPxR.\r
+ * @note Writing a wrong key reactivates the write protection.\r
+ * @note The protection mechanism is not affected by system reset. \r
+ * @param NewState: new state of the write protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_WriteProtectionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the RTC Initialization mode.\r
+ * @note The RTC Initialization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC is in Init mode\r
+ * - ERROR: RTC is not in Init mode \r
+ */\r
+ErrorStatus RTC_EnterInitMode(void)\r
+{\r
+ __IO uint32_t initcounter = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ uint32_t initstatus = 0x00;\r
+ \r
+ /* Check if the Initialization mode is set */\r
+ if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
+ {\r
+ /* Set the Initialization mode */\r
+ RTC->ISR = (uint32_t)RTC_INIT_MASK;\r
+ \r
+ /* Wait till RTC is in INIT state and if Time out is reached exit */\r
+ do\r
+ {\r
+ initstatus = RTC->ISR & RTC_ISR_INITF;\r
+ initcounter++; \r
+ } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_INITF) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS; \r
+ } \r
+ \r
+ return (status); \r
+}\r
+\r
+/**\r
+ * @brief Exits the RTC Initialization mode.\r
+ * @note When the initialization sequence is complete, the calendar restarts \r
+ * counting after 4 RTCCLK cycles. \r
+ * @note The RTC Initialization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_ExitInitMode(void)\r
+{\r
+ /* Exit Initialization mode */\r
+ RTC->ISR &= (uint32_t)~RTC_ISR_INIT;\r
+}\r
+\r
+/**\r
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r
+ * synchronized with RTC APB clock.\r
+ * @note The RTC Resynchronization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @note To read the calendar through the shadow registers after Calendar \r
+ * initialization, calendar update or after wakeup from low power modes \r
+ * the software must first clear the RSF flag. \r
+ * The software must then wait until it is set again before reading \r
+ * the calendar, which means that the calendar registers have been \r
+ * correctly copied into the RTC_TR and RTC_DR shadow registers. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are synchronised\r
+ * - ERROR: RTC registers are not synchronised\r
+ */\r
+ErrorStatus RTC_WaitForSynchro(void)\r
+{\r
+ __IO uint32_t synchrocounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ uint32_t synchrostatus = 0x00;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Clear RSF flag */\r
+ RTC->ISR &= (uint32_t)RTC_RSF_MASK;\r
+ \r
+ /* Wait the registers to be synchronised */\r
+ do\r
+ {\r
+ synchrostatus = RTC->ISR & RTC_ISR_RSF;\r
+ synchrocounter++; \r
+ } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_RSF) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC reference clock detection.\r
+ * @param NewState: new state of the RTC reference clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC reference clock detection is enabled\r
+ * - ERROR: RTC reference clock detection is disabled \r
+ */\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)\r
+{\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the RTC reference clock detection */\r
+ RTC->CR |= RTC_CR_REFCKON; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the RTC reference clock detection */\r
+ RTC->CR &= ~RTC_CR_REFCKON; \r
+ }\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+\r
+ status = SUCCESS;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Bypass Shadow feature.\r
+ * @note When the Bypass Shadow is enabled the calendar value are taken \r
+ * directly from the Calendar counter.\r
+ * @param NewState: new state of the Bypass Shadow feature.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+*/\r
+void RTC_BypassShadowCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the BYPSHAD bit */\r
+ RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the BYPSHAD bit */\r
+ RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group2 Time and Date configuration functions\r
+ * @brief Time and Date configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Time and Date configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to program and read the RTC \r
+ Calendar (Time and Date).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the RTC current time.\r
+ * @param RTC_Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format.\r
+ * @arg RTC_Format_BCD: BCD data format.\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains \r
+ * the time configuration information for the RTC.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Time register is configured\r
+ * - ERROR: RTC Time register is not configured\r
+ */\r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ \r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));\r
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_TimeStruct->RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));\r
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));\r
+ }\r
+ else\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); \r
+ } \r
+ else\r
+ {\r
+ RTC_TimeStruct->RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));\r
+ }\r
+ \r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \\r
+ ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \\r
+ ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \\r
+ (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));\r
+ } \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_TR register */\r
+ RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode(); \r
+\r
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if (RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ \r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_TimeStruct member with its default value\r
+ * (Time = 00h:00min:00sec).\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ /* Time = 00h:00min:00sec */\r
+ RTC_TimeStruct->RTC_H12 = RTC_H12_AM;\r
+ RTC_TimeStruct->RTC_Hours = 0;\r
+ RTC_TimeStruct->RTC_Minutes = 0;\r
+ RTC_TimeStruct->RTC_Seconds = 0; \r
+}\r
+\r
+/**\r
+ * @brief Get the RTC current Time.\r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format.\r
+ * @arg RTC_Format_BCD: BCD data format.\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
+ * contain the returned current time configuration.\r
+ * @retval None\r
+ */\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ /* Get the RTC_TR register */\r
+ tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); \r
+ \r
+ /* Fill the structure fields with the read parameters */\r
+ RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r
+ RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the structure parameters to Binary format */\r
+ RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);\r
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC current Calendar Subseconds value.\r
+ * @note This function freeze the Time and Date registers after reading the \r
+ * SSR register.\r
+ * @param None\r
+ * @retval RTC current Calendar Subseconds value.\r
+ */\r
+uint32_t RTC_GetSubSecond(void)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Get subseconds values from the correspondent registers*/\r
+ tmpreg = (uint32_t)(RTC->SSR);\r
+ \r
+ /* Read DR register to unfroze calendar registers */\r
+ (void) (RTC->DR);\r
+ \r
+ return (tmpreg);\r
+}\r
+\r
+/**\r
+ * @brief Set the RTC current date.\r
+ * @param RTC_Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format.\r
+ * @arg RTC_Format_BCD: BCD data format.\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains \r
+ * the date configuration information for the RTC.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Date register is configured\r
+ * - ERROR: RTC Date register is not configured\r
+ */\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))\r
+ {\r
+ RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;\r
+ } \r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));\r
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));\r
+ assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));\r
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
+ assert_param(IS_RTC_MONTH(tmpreg));\r
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
+ assert_param(IS_RTC_DATE(tmpreg));\r
+ }\r
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \\r
+ (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \\r
+ ((uint32_t)RTC_DateStruct->RTC_Date) | \\r
+ (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \\r
+ ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));\r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_DR register */\r
+ RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode(); \r
+\r
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if (RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_DateStruct member with its default value\r
+ * (Monday, January 01 xx00).\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ /* Monday, January 01 xx00 */\r
+ RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;\r
+ RTC_DateStruct->RTC_Date = 1;\r
+ RTC_DateStruct->RTC_Month = RTC_Month_January;\r
+ RTC_DateStruct->RTC_Year = 0;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC current date.\r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format.\r
+ * @arg RTC_Format_BCD: BCD data format.\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will \r
+ * contain the returned current date configuration.\r
+ * @retval None\r
+ */\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ \r
+ /* Get the RTC_TR register */\r
+ tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); \r
+\r
+ /* Fill the structure fields with the read parameters */\r
+ RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r
+ RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));\r
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); \r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the structure parameters to Binary format */\r
+ RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);\r
+ RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
+ RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group3 Alarms configuration functions\r
+ * @brief Alarms (Alarm A and Alarm B) configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Alarms (Alarm A and Alarm B) configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to program and read the RTC \r
+ Alarms.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the specified RTC Alarm.\r
+ * @note The Alarm register can only be written when the corresponding Alarm\r
+ * is disabled (Use the RTC_AlarmCmd(DISABLE)). \r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format.\r
+ * @arg RTC_Format_BCD: BCD data format.\r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A.\r
+ * @arg RTC_Alarm_B: to select Alarm B.\r
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that \r
+ * contains the alarm configuration parameters.\r
+ * @retval None\r
+ */\r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm));\r
+ assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));\r
+\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));\r
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));\r
+ \r
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));\r
+ }\r
+ \r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));\r
+ \r
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
+ } \r
+ }\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
+ } \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Alarm register */\r
+ if (RTC_Alarm == RTC_Alarm_A)\r
+ {\r
+ RTC->ALRMAR = (uint32_t)tmpreg;\r
+ }\r
+ else\r
+ {\r
+ RTC->ALRMBR = (uint32_t)tmpreg;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_AlarmStruct member with its default value\r
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =\r
+ * all fields are masked).\r
+ * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;\r
+\r
+ /* Alarm Date Settings : Date = 1st day of the month */\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;\r
+\r
+ /* Alarm Masks Settings : Mask = all fields are not masked */\r
+ RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC Alarm value and masks.\r
+ * @param RTC_Format: specifies the format of the output parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format.\r
+ * @arg RTC_Format_BCD: BCD data format.\r
+ * @param RTC_Alarm: specifies the alarm to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A.\r
+ * @arg RTC_Alarm_B: to select Alarm B.\r
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will \r
+ * contains the output alarm configuration values. \r
+ * @retval None\r
+ */\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm)); \r
+\r
+ /* Get the RTC_ALRMxR register */\r
+ if (RTC_Alarm == RTC_Alarm_A)\r
+ {\r
+ tmpreg = (uint32_t)(RTC->ALRMAR);\r
+ }\r
+ else\r
+ {\r
+ tmpreg = (uint32_t)(RTC->ALRMBR);\r
+ }\r
+\r
+ /* Fill the structure with the read parameters */\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \\r
+ RTC_ALRMAR_HU)) >> 16);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \\r
+ RTC_ALRMAR_MNU)) >> 8);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \\r
+ RTC_ALRMAR_SU));\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r
+ RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);\r
+\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Hours);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Minutes);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Seconds);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC Alarm.\r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A.\r
+ * @arg RTC_Alarm_B: to select Alarm B.\r
+ * @param NewState: new state of the specified alarm.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Alarm is enabled/disabled\r
+ * - ERROR: RTC Alarm is not enabled/disabled \r
+ */\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)\r
+{\r
+ __IO uint32_t alarmcounter = 0x00;\r
+ uint32_t alarmstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Alarm state */\r
+ if (NewState != DISABLE)\r
+ {\r
+ RTC->CR |= (uint32_t)RTC_Alarm;\r
+\r
+ status = SUCCESS; \r
+ }\r
+ else\r
+ { \r
+ /* Disable the Alarm in RTC_CR register */\r
+ RTC->CR &= (uint32_t)~RTC_Alarm;\r
+ \r
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ alarmstatus = RTC->ISR & (RTC_Alarm >> 8);\r
+ alarmcounter++; \r
+ } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ } \r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Configure the RTC AlarmA/B Subseconds value and mask.*\r
+ * @note This function is performed only when the Alarm is disabled. \r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A.\r
+ * @arg RTC_Alarm_B: to select Alarm B.\r
+ * @param RTC_AlarmSubSecondValue: specifies the Subseconds value.\r
+ * This parameter can be a value from 0 to 0x00007FFF.\r
+ * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.\r
+ * There is no comparison on sub seconds for Alarm.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.\r
+ * Only SS[0] is compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.\r
+ * Only SS[1:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.\r
+ * Only SS[2:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.\r
+ * Only SS[3:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.\r
+ * Only SS[4:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.\r
+ * Only SS[5:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.\r
+ * Only SS[6:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.\r
+ * Only SS[7:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.\r
+ * Only SS[8:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.\r
+ * Only SS[9:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.\r
+ * Only SS[10:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.\r
+ * Only SS[11:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.\r
+ * Only SS[12:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.\r
+ * Only SS[13:0] are compared.\r
+ * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match\r
+ * to activate alarm.\r
+ * @retval None\r
+ */\r
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Configure the Alarm A or Alarm B SubSecond registers */\r
+ tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);\r
+ \r
+ if (RTC_Alarm == RTC_Alarm_A)\r
+ {\r
+ /* Configure the AlarmA SubSecond register */\r
+ RTC->ALRMASSR = tmpreg;\r
+ }\r
+ else\r
+ {\r
+ /* Configure the Alarm B SubSecond register */\r
+ RTC->ALRMBSSR = tmpreg;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC Alarm Subseconds value.\r
+ * @param RTC_Alarm: specifies the alarm to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A.\r
+ * @arg RTC_Alarm_B: to select Alarm B.\r
+ * @param None\r
+ * @retval RTC Alarm Subseconds value.\r
+ */\r
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Get the RTC_ALRMxR register */\r
+ if (RTC_Alarm == RTC_Alarm_A)\r
+ {\r
+ tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);\r
+ }\r
+ else\r
+ {\r
+ tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);\r
+ } \r
+ \r
+ return (tmpreg);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions\r
+ * @brief WakeUp Timer configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### WakeUp Timer configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to program and read the RTC WakeUp.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC Wakeup clock source.\r
+ * @note The WakeUp Clock source can only be changed when the RTC WakeUp\r
+ * is disabled (Use the RTC_WakeUpCmd(DISABLE)).\r
+ * @param RTC_WakeUpClock: Wakeup Clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16.\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8.\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4.\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2.\r
+ * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE.\r
+ * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE.\r
+ * @retval None\r
+ */\r
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the Wakeup Timer clock source bits in CR register */\r
+ RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r
+\r
+ /* Configure the clock source */\r
+ RTC->CR |= (uint32_t)RTC_WakeUpClock;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Configures the RTC Wakeup counter.\r
+ * @note The RTC WakeUp counter can only be written when the RTC WakeUp.\r
+ * is disabled (Use the RTC_WakeUpCmd(DISABLE)).\r
+ * @param RTC_WakeUpCounter: specifies the WakeUp counter.\r
+ * This parameter can be a value from 0x0000 to 0xFFFF. \r
+ * @retval None\r
+ */\r
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Configure the Wakeup Timer counter */\r
+ RTC->WUTR = (uint32_t)RTC_WakeUpCounter;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Returns the RTC WakeUp timer counter value.\r
+ * @param None\r
+ * @retval The RTC WakeUp Counter value.\r
+ */\r
+uint32_t RTC_GetWakeUpCounter(void)\r
+{\r
+ /* Get the counter value */\r
+ return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the RTC WakeUp timer.\r
+ * @param NewState: new state of the WakeUp timer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)\r
+{\r
+ __IO uint32_t wutcounter = 0x00;\r
+ uint32_t wutwfstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Wakeup Timer */\r
+ RTC->CR |= (uint32_t)RTC_CR_WUTE;\r
+ status = SUCCESS; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the Wakeup Timer */\r
+ RTC->CR &= (uint32_t)~RTC_CR_WUTE;\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r
+ wutcounter++; \r
+ } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ } \r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group5 Daylight Saving configuration functions\r
+ * @brief Daylight Saving configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Daylight Saving configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to configure the RTC DayLight Saving.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Adds or substract one hour from the current time.\r
+ * @param RTC_DayLightSaveOperation: the value of hour adjustment. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time).\r
+ * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time).\r
+ * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit \r
+ * in CR register to store the operation.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_StoreOperation_Reset: BCK Bit Reset.\r
+ * @arg RTC_StoreOperation_Set: BCK Bit Set.\r
+ * @retval None\r
+ */\r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));\r
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the bits to be configured */\r
+ RTC->CR &= (uint32_t)~(RTC_CR_BCK);\r
+\r
+ /* Configure the RTC_CR register */\r
+ RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Returns the RTC Day Light Saving stored operation.\r
+ * @param None\r
+ * @retval RTC Day Light Saving stored operation.\r
+ * - RTC_StoreOperation_Reset\r
+ * - RTC_StoreOperation_Set\r
+ */\r
+uint32_t RTC_GetStoreOperation(void)\r
+{\r
+ return (RTC->CR & RTC_CR_BCK);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group6 Output pin Configuration function\r
+ * @brief Output pin Configuration function \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Output pin Configuration function #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to configure the RTC Output source.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC output source (AFO_ALARM).\r
+ * @param RTC_Output: Specifies which signal will be routed to the RTC output. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Output_Disable: No output selected\r
+ * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output.\r
+ * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output.\r
+ * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output.\r
+ * @param RTC_OutputPolarity: Specifies the polarity of the output signal.\r
+ * This parameter can be one of the following:\r
+ * @arg RTC_OutputPolarity_High: The output pin is high when the \r
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).\r
+ * @arg RTC_OutputPolarity_Low: The output pin is low when the \r
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).\r
+ * @retval None\r
+ */\r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_OUTPUT(RTC_Output));\r
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the bits to be configured */\r
+ RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);\r
+\r
+ /* Configure the output selection and polarity */\r
+ RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group7 Coarse and Smooth Calibrations configuration functions\r
+ * @brief Coarse and Smooth Calibrations configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Coarse and Smooth Calibrations configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the Coarse Calibration parameters.\r
+ * @param RTC_CalibSign: specifies the sign of the calibration value.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_CalibSign_Positive: The value sign is positive.\r
+ * @arg RTC_CalibSign_Negative: The value sign is negative.\r
+ * @param Value: value of calibration expressed in ppm (coded on 5 bits) \r
+ * This value should be between 0 and 63 when using negative sign\r
+ * with a 2-ppm step.\r
+ * This value should be between 0 and 126 when using positive sign\r
+ * with a 4-ppm step.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Coarse calibration are initialized\r
+ * - ERROR: RTC Coarse calibration are not initialized \r
+ */\r
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));\r
+ assert_param(IS_RTC_CALIB_VALUE(Value)); \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the coarse calibration value */\r
+ RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+ \r
+ status = SUCCESS;\r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+* @brief Enables or disables the Coarse calibration process.\r
+ * @param NewState: new state of the Coarse calibration.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Coarse calibration are enabled/disabled\r
+ * - ERROR: RTC Coarse calibration are not enabled/disabled \r
+ */\r
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Coarse Calibration */\r
+ RTC->CR |= (uint32_t)RTC_CR_DCE;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the Coarse Calibration */\r
+ RTC->CR &= (uint32_t)~RTC_CR_DCE;\r
+ }\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+ \r
+ status = SUCCESS;\r
+ } \r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock to be output through the relative \r
+ * pin.\r
+ * @param NewState: new state of the coarse calibration Output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_CalibOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the RTC clock output */\r
+ RTC->CR |= (uint32_t)RTC_CR_COE;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the RTC clock output */\r
+ RTC->CR &= (uint32_t)~RTC_CR_COE;\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ * @param RTC_CalibOutput : Select the Calibration output Selection .\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. \r
+ * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.\r
+ * @retval None\r
+*/\r
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /*clear flags before config*/\r
+ RTC->CR &= (uint32_t)~(RTC_CR_COSEL);\r
+\r
+ /* Configure the RTC_CR register */\r
+ RTC->CR |= (uint32_t)RTC_CalibOutput;\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Smooth Calibration Settings.\r
+ * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.\r
+ * This parameter can be can be one of the following values:\r
+ * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.\r
+ * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.\r
+ * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.\r
+ * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.\r
+ * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.\r
+ * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.\r
+ * This parameter can be one any value from 0 to 0x000001FF.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Calib registers are configured\r
+ * - ERROR: RTC Calib registers are not configured\r
+*/\r
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,\r
+ uint32_t RTC_SmoothCalibPlusPulses,\r
+ uint32_t RTC_SmouthCalibMinusPulsesValue)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ uint32_t recalpfcount = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));\r
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));\r
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* check if a calibration is pending*/\r
+ if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)\r
+ {\r
+ /* wait until the Calibration is completed*/\r
+ while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))\r
+ {\r
+ recalpfcount++;\r
+ }\r
+ }\r
+\r
+ /* check if the calibration pending is completed or if there is no calibration operation at all*/\r
+ if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)\r
+ {\r
+ /* Configure the Smooth calibration settings */\r
+ RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);\r
+\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return (ErrorStatus)(status);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RTC_Group8 TimeStamp configuration functions\r
+ * @brief TimeStamp configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### TimeStamp configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or Disables the RTC TimeStamp functionality with the \r
+ * specified time stamp pin stimulating edge.\r
+ * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
+ * activated.\r
+ * This parameter can be one of the following:\r
+ * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising \r
+ * edge of the related pin.\r
+ * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the \r
+ * falling edge of the related pin.\r
+ * @param NewState: new state of the TimeStamp.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+\r
+ /* Get the new configuration */\r
+ if (NewState != DISABLE)\r
+ {\r
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);\r
+ }\r
+ else\r
+ {\r
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge);\r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ RTC->CR = (uint32_t)tmpreg;\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC TimeStamp value and masks.\r
+ * @param RTC_Format: specifies the format of the output parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
+ * contains the TimeStamp time values. \r
+ * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will \r
+ * contains the TimeStamp date values. \r
+ * @retval None\r
+ */\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
+ RTC_DateTypeDef* RTC_StampDateStruct)\r
+{\r
+ uint32_t tmptime = 0, tmpdate = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ /* Get the TimeStamp time and date registers values */\r
+ tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);\r
+ tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Fill the Time structure fields with the read parameters */\r
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r
+ RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); \r
+\r
+ /* Fill the Date structure fields with the read parameters */\r
+ RTC_StampDateStruct->RTC_Year = 0;\r
+ RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the Time structure parameters to Binary format */\r
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);\r
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);\r
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);\r
+\r
+ /* Convert the Date structure parameters to Binary format */\r
+ RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);\r
+ RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);\r
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC timestamp Subseconds value.\r
+ * @param None\r
+ * @retval RTC current timestamp Subseconds value.\r
+ */\r
+uint32_t RTC_GetTimeStampSubSecond(void)\r
+{\r
+ /* Get timestamp subseconds values from the correspondent registers */\r
+ return (uint32_t)(RTC->TSSSR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group9 Tampers configuration functions\r
+ * @brief Tampers configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Tampers configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the select Tamper pin edge.\r
+ * @param RTC_Tamper: Selected tamper pin.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_Tamper_1: Select Tamper 1.\r
+ * @arg RTC_Tamper_2: Select Tamper 2.\r
+ * @arg RTC_Tamper_3: Select Tamper 3.\r
+ * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that \r
+ * stimulates tamper event. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.\r
+ * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.\r
+ * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.\r
+ * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.\r
+ * @retval None\r
+ */\r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
+ assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));\r
+ \r
+ /* Check if the active level for Tamper is rising edge (Low level)*/\r
+ if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)\r
+ { \r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); \r
+ }\r
+ else\r
+ { \r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Tamper detection.\r
+ * @param RTC_Tamper: Selected tamper pin.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_Tamper_1: Select Tamper 1.\r
+ * @arg RTC_Tamper_2: Select Tamper 2.\r
+ * @arg RTC_Tamper_3: Select Tamper 3.\r
+ * @param NewState: new state of the tamper pin.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected Tamper pin */\r
+ RTC->TAFCR |= (uint32_t)RTC_Tamper;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected Tamper pin */\r
+ RTC->TAFCR &= (uint32_t)~RTC_Tamper; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Configures the Tampers Filter.\r
+ * @param RTC_TamperFilter: Specifies the tampers filter.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.\r
+ * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive \r
+ * samples at the active level.\r
+ * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive \r
+ * samples at the active level.\r
+ * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive \r
+ * samples at the active level.\r
+ * @retval None\r
+ */\r
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));\r
+ \r
+ /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);\r
+\r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)RTC_TamperFilter;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Tampers Sampling Frequency.\r
+ * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 32768\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 16384\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 8192\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 4096\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 2048\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 1024\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 512 \r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 256 \r
+ * @retval None\r
+ */\r
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));\r
+ \r
+ /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);\r
+\r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Tampers Pins input Precharge Duration.\r
+ * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input\r
+ * Precharge Duration.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.\r
+ * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.\r
+ * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.\r
+ * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.\r
+ * @retval None\r
+ */\r
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));\r
+ \r
+ /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);\r
+\r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TimeStamp on Tamper Detection Event.\r
+ * @note The timestamp is valid even the TSE bit in tamper control register \r
+ * is reset. \r
+ * @param NewState: new state of the timestamp on tamper event.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Save timestamp on tamper detection event */\r
+ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;\r
+ }\r
+ else\r
+ {\r
+ /* Tamper detection does not cause a timestamp to be saved */\r
+ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Precharge of Tamper pin.\r
+ * @param NewState: new state of tamper pull up.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void RTC_TamperPullUpCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable precharge of the selected Tamper pin */\r
+ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; \r
+ }\r
+ else\r
+ {\r
+ /* Disable precharge of the selected Tamper pin */\r
+ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; \r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions\r
+ * @brief Backup Data Registers configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Backup Data Registers configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a data in a specified RTC Backup data register.\r
+ * @param RTC_BKP_DR: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register.\r
+ * @param Data: Data to be written in the specified RTC Backup data register. \r
+ * @retval None\r
+ */\r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
+\r
+ tmp = RTC_BASE + 0x50;\r
+ tmp += (RTC_BKP_DR * 4);\r
+\r
+ /* Write the specified register */\r
+ *(__IO uint32_t *)tmp = (uint32_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads data from the specified RTC Backup data Register.\r
+ * @param RTC_BKP_DR: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register. \r
+ * @retval None\r
+ */\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
+\r
+ tmp = RTC_BASE + 0x50;\r
+ tmp += (RTC_BKP_DR * 4);\r
+ \r
+ /* Read the specified register */\r
+ return (*(__IO uint32_t *)tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group11 Output Type Config configuration functions\r
+ * @brief Output Type Config configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Output Type Config configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC Output Pin mode. \r
+ * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in \r
+ * Open Drain mode.\r
+ * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in \r
+ * Push Pull mode. \r
+ * @retval None\r
+ */\r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));\r
+ \r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);\r
+ RTC->TAFCR |= (uint32_t)(RTC_OutputType); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group12 Shift control synchronisation functions\r
+ * @brief Shift control synchronisation functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Shift control synchronisation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the Synchronization Shift Control Settings.\r
+ * @note When REFCKON is set, firmware must not write to Shift control register \r
+ * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.\r
+ * This parameter can be one of the following values :\r
+ * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. \r
+ * @arg RTC_ShiftAdd1S_Reset: No effect.\r
+ * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.\r
+ * This parameter can be one any value from 0 to 0x7FFF.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Shift registers are configured\r
+ * - ERROR: RTC Shift registers are not configured\r
+*/\r
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ uint32_t shpfcount = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));\r
+ assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Check if a Shift is pending*/\r
+ if ((RTC->ISR & RTC_ISR_SHPF) != RESET)\r
+ {\r
+ /* Wait until the shift is completed*/\r
+ while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))\r
+ {\r
+ shpfcount++;\r
+ }\r
+ }\r
+\r
+ /* Check if the Shift pending is completed or if there is no Shift operation at all*/\r
+ if ((RTC->ISR & RTC_ISR_SHPF) == RESET)\r
+ {\r
+ /* check if the reference clock detection is disabled */\r
+ if((RTC->CR & RTC_CR_REFCKON) == RESET)\r
+ {\r
+ /* Configure the Shift settings */\r
+ RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);\r
+ \r
+ if(RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return (ErrorStatus)(status);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group13 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] All RTC interrupts are connected to the EXTI controller.\r
+ (+) To enable the RTC Alarm interrupt, the following sequence is required:\r
+ (+) Configure and enable the EXTI Line 17 in interrupt mode and select \r
+ the rising edge sensitivity using the EXTI_Init() function.\r
+ (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using \r
+ the NVIC_Init() function.\r
+ (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) \r
+ using the RTC_SetAlarm() and RTC_AlarmCmd() functions.\r
+\r
+ (+) To enable the RTC Wakeup interrupt, the following sequence is required:\r
+ (+) Configure and enable the EXTI Line 20 in interrupt mode and select \r
+ the rising edge sensitivity using the EXTI_Init() function.\r
+ (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the \r
+ NVIC_Init() function.\r
+ (+) Configure the RTC to generate the RTC wakeup timer event using the \r
+ RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() \r
+ functions.\r
+\r
+ (+) To enable the RTC Tamper interrupt, the following sequence is required:\r
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select \r
+ the rising edge sensitivity using the EXTI_Init() function.\r
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using \r
+ the NVIC_Init() function.\r
+ (+) Configure the RTC to detect the RTC tamper event using the \r
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.\r
+\r
+ (+) To enable the RTC TimeStamp interrupt, the following sequence is \r
+ required:\r
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select \r
+ the rising edge sensitivity using the EXTI_Init() function.\r
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using \r
+ the NVIC_Init() function.\r
+ (+) Configure the RTC to detect the RTC time-stamp event using the \r
+ RTC_TimeStampCmd() functions.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC interrupts.\r
+ * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt mask.\r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt mask.\r
+ * @arg RTC_IT_ALRB: Alarm B interrupt mask.\r
+ * @arg RTC_IT_ALRA: Alarm A interrupt mask.\r
+ * @arg RTC_IT_TAMP: Tamper event interrupt mask.\r
+ * @param NewState: new state of the specified RTC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CONFIG_IT(RTC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Configure the Interrupts in the RTC_CR register */\r
+ RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);\r
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
+ RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);\r
+ }\r
+ else\r
+ {\r
+ /* Configure the Interrupts in the RTC_CR register */\r
+ RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);\r
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC flag is set or not.\r
+ * @param RTC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_FLAG_RECALPF: RECALPF event flag.\r
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.\r
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.\r
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.\r
+ * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag.\r
+ * @arg RTC_FLAG_TSF: Time Stamp event flag.\r
+ * @arg RTC_FLAG_WUTF: WakeUp Timer flag.\r
+ * @arg RTC_FLAG_ALRBF: Alarm B flag.\r
+ * @arg RTC_FLAG_ALRAF: Alarm A flag.\r
+ * @arg RTC_FLAG_INITF: Initialization mode flag.\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag.\r
+ * @arg RTC_FLAG_INITS: Registers Configured flag.\r
+ * @argRTC_FLAG_SHPF: Shift operation pending flag.\r
+ * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag.\r
+ * @arg RTC_FLAG_ALRBWF: Alarm B Write flag.\r
+ * @arg RTC_FLAG_ALRAWF: Alarm A write flag.\r
+ * @retval The new state of RTC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));\r
+ \r
+ /* Get all the flags */\r
+ tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);\r
+ \r
+ /* Return the status of the flag */\r
+ if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC's pending flags.\r
+ * @param RTC_FLAG: specifies the RTC flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.\r
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.\r
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.\r
+ * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag.\r
+ * @arg RTC_FLAG_TSF: Time Stamp event flag.\r
+ * @arg RTC_FLAG_WUTF: WakeUp Timer flag.\r
+ * @arg RTC_FLAG_ALRBF: Alarm B flag.\r
+ * @arg RTC_FLAG_ALRAF: Alarm A flag.\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag.\r
+ * @retval None\r
+ */\r
+void RTC_ClearFlag(uint32_t RTC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));\r
+\r
+ /* Clear the Flags in the RTC_ISR register */\r
+ RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occurred or not.\r
+ * @param RTC_IT: specifies the RTC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt.\r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt.\r
+ * @arg RTC_IT_ALRB: Alarm B interrupt. \r
+ * @arg RTC_IT_ALRA: Alarm A interrupt. \r
+ * @arg RTC_IT_TAMP1: Tamper1 event interrupt. \r
+ * @arg RTC_IT_TAMP2: Tamper2 event interrupt. \r
+ * @arg RTC_IT_TAMP3: Tamper3 event interrupt.\r
+ * @retval The new state of RTC_IT (SET or RESET).\r
+ */\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0, enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_IT(RTC_IT));\r
+ \r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));\r
+ \r
+ /* Get the Interrupt enable Status */\r
+ enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));\r
+ \r
+ /* Get the Interrupt pending bit */\r
+ tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));\r
+ \r
+ /* Get the status of the Interrupt */\r
+ if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC's interrupt pending bits.\r
+ * @param RTC_IT: specifies the RTC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt \r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt \r
+ * @arg RTC_IT_ALRB: Alarm B interrupt \r
+ * @arg RTC_IT_ALRA: Alarm A interrupt \r
+ * @arg RTC_IT_TAMP1: Tamper1 event interrupt\r
+ * @arg RTC_IT_TAMP2: Tamper2 event interrupt\r
+ * @arg RTC_IT_TAMP3: Tamper3 event interrupt \r
+ * @retval None\r
+ */\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_IT(RTC_IT));\r
+\r
+ /* Get the RTC_ISR Interrupt pending bits mask */\r
+ tmpreg = (uint32_t)(RTC_IT >> 4);\r
+\r
+ /* Clear the interrupt pending bits in the RTC_ISR register */\r
+ RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Converts a 2 digit decimal to BCD format.\r
+ * @param Value: Byte to be converted.\r
+ * @retval Converted byte\r
+ */\r
+static uint8_t RTC_ByteToBcd2(uint8_t Value)\r
+{\r
+ uint8_t bcdhigh = 0;\r
+ \r
+ while (Value >= 10)\r
+ {\r
+ bcdhigh++;\r
+ Value -= 10;\r
+ }\r
+ \r
+ return ((uint8_t)(bcdhigh << 4) | Value);\r
+}\r
+\r
+/**\r
+ * @brief Convert from 2 digit BCD to Binary.\r
+ * @param Value: BCD value to be converted.\r
+ * @retval Converted word\r
+ */\r
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)\r
+{\r
+ uint8_t tmp = 0;\r
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r
+ return (tmp + (Value & (uint8_t)0x0F));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_sdio.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the SDIO peripheral:\r
+ * + Initialization \r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL\r
+ (PLLVCO) througth a fixed divider by 2.\r
+ Before to start working with SDIO peripheral make sure that the PLLVCO is \r
+ well configured to 96MHz. \r
+ The SDIO peripheral uses two clock signals: \r
+ (++) SDIO adapter clock (SDIOCLK = 48 MHz).\r
+ (++) APB2 bus clock (PCLK2).\r
+ PCLK2 and SDIO_CK clock frequencies must respect the following \r
+ condition: Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)).\r
+ (#) Enable peripheral clock using \r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). \r
+ (#) According to the SDIO mode, enable the GPIO clocks using\r
+ RCC_AHBPeriphClockCmd() function.\r
+ The I/O can be one of the following configurations: \r
+ (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. \r
+ (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. \r
+ (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].\r
+\r
+ (#) Peripheral's alternate function: \r
+ (++) Connect the pin to the desired peripherals' Alternate \r
+ Function (AF) using GPIO_PinAFConfig() function.\r
+ (++) Configure the desired pin in alternate function by: \r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
+ (++) Select the type, pull-up/pull-down and output speed via \r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
+ (++) Call GPIO_Init() function.\r
+\r
+ (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, \r
+ hardware, flow control and the Clock Divider using the SDIO_Init() \r
+ function. \r
+ (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) \r
+ function. \r
+ (#) Enable the clock using the SDIO_ClockCmd() function. \r
+ (#) Enable the NVIC and the corresponding interrupt using the function \r
+ SDIO_ITConfig() if you need to use interrupt mode. \r
+ (#) When using the DMA mode\r
+ (++) Configure the DMA using DMA_Init() function.\r
+ (++) Active the needed channel Request using SDIO_DMACmd() function.\r
+ (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.\r
+ (#) To control the CPSM (Command Path State Machine) and send commands to the\r
+ card use the SDIO_SendCommand(), SDIO_GetCommandResponse() and \r
+ SDIO_GetResponse() functions. First, user has to fill the command \r
+ structure (pointer to SDIO_CmdInitTypeDef) according to the selected \r
+ command to be sent. The parameters that should be filled are: \r
+ (++) Command Argument.\r
+ (++) Command Index.\r
+ (++) Command Response type.\r
+ (++) Command Wait.\r
+ (++) CPSM Status (Enable or Disable).\r
+ To check if the command is well received, read the SDIO_CMDRESP register \r
+ using the SDIO_GetCommandResponse(). The SDIO responses registers \r
+ (SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function. \r
+ (#) To control the DPSM (Data Path State Machine) and send/receive \r
+ data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),\r
+ SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.\r
+\r
+ *** Read Operations *** \r
+ ----------------------- \r
+ [..]\r
+ (#) First, user has to fill the data structure (pointer to \r
+ SDIO_DataInitTypeDef) according to the selected data type to be received. \r
+ The parameters that should be filled are:\r
+ (++) Data TimeOut.\r
+ (++) Data Length.\r
+ (++) Data Block size.\r
+ (++) Data Transfer direction: should be from card (To SDIO).\r
+ (++) Data Transfer mode.\r
+ (++) DPSM Status (Enable or Disable).\r
+ (#) Configure the SDIO resources to receive the data from the card \r
+ according to selected transfer mode (Refer to Step 8, 9 and 10).\r
+ (#) Send the selected Read command (refer to step 11).\r
+ (#) Use the SDIO flags/interrupts to check the transfer status.\r
+ \r
+ *** Write Operations *** \r
+ ------------------------ \r
+ [..]\r
+ (#) First, user has to fill the data structure (pointer to\r
+ SDIO_DataInitTypeDef) according to the selected data type to be received. \r
+ The parameters that should be filled are: \r
+ (++) Data TimeOut.\r
+ (++) Data Length.\r
+ (++) Data Block size.\r
+ (++) Data Transfer direction: should be to card (To CARD).\r
+ (++) Data Transfer mode.\r
+ (++) DPSM Status (Enable or Disable).\r
+ (#) Configure the SDIO resources to send the data to the card \r
+ according to selected transfer mode (Refer to Step 8, 9 and 10).\r
+ (#) Send the selected Write command (refer to step 11).\r
+ (#) Use the SDIO flags/interrupts to check the transfer status.\r
+\r
+ @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_sdio.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO \r
+ * @brief SDIO driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/ \r
+\r
+/* ------------ SDIO registers bit address in the alias region ----------- */\r
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)\r
+\r
+/* --- CLKCR Register ---*/\r
+\r
+/* Alias word address of CLKEN bit */\r
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)\r
+#define CLKEN_BitNumber 0x08\r
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))\r
+\r
+/* --- CMD Register ---*/\r
+\r
+/* Alias word address of SDIOSUSPEND bit */\r
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)\r
+#define SDIOSUSPEND_BitNumber 0x0B\r
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))\r
+\r
+/* Alias word address of ENCMDCOMPL bit */\r
+#define ENCMDCOMPL_BitNumber 0x0C\r
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))\r
+\r
+/* Alias word address of NIEN bit */\r
+#define NIEN_BitNumber 0x0D\r
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))\r
+\r
+/* Alias word address of ATACMD bit */\r
+#define ATACMD_BitNumber 0x0E\r
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))\r
+\r
+/* --- DCTRL Register ---*/\r
+\r
+/* Alias word address of DMAEN bit */\r
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)\r
+#define DMAEN_BitNumber 0x03\r
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))\r
+\r
+/* Alias word address of RWSTART bit */\r
+#define RWSTART_BitNumber 0x08\r
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))\r
+\r
+/* Alias word address of RWSTOP bit */\r
+#define RWSTOP_BitNumber 0x09\r
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))\r
+\r
+/* Alias word address of RWMOD bit */\r
+#define RWMOD_BitNumber 0x0A\r
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))\r
+\r
+/* Alias word address of SDIOEN bit */\r
+#define SDIOEN_BitNumber 0x0B\r
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))\r
+\r
+/* ---------------------- SDIO registers bit mask ------------------------ */\r
+\r
+/* --- CLKCR Register ---*/\r
+\r
+/* CLKCR register clear mask */\r
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) \r
+\r
+/* --- PWRCTRL Register ---*/\r
+\r
+/* SDIO PWRCTRL Mask */\r
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)\r
+\r
+/* --- DCTRL Register ---*/\r
+\r
+/* SDIO DCTRL Clear Mask */\r
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)\r
+\r
+/* --- CMD Register ---*/\r
+\r
+/* CMD Register clear mask */\r
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)\r
+\r
+/* SDIO RESP Registers Address */\r
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SDIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ==============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SDIO peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SDIO_DeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); \r
+}\r
+\r
+/**\r
+ * @brief Initializes the SDIO peripheral according to the specified \r
+ * parameters in the SDIO_InitStruct.\r
+ * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure \r
+ * that contains the configuration information for the SDIO peripheral.\r
+ * @retval None\r
+ */\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));\r
+ assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));\r
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));\r
+ assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));\r
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); \r
+ \r
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/ \r
+ /* Get the SDIO CLKCR value */\r
+ tmpreg = SDIO->CLKCR;\r
+ \r
+ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */\r
+ tmpreg &= CLKCR_CLEAR_MASK;\r
+ \r
+ /* Set CLKDIV bits according to SDIO_ClockDiv value */\r
+ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */\r
+ /* Set BYPASS bit according to SDIO_ClockBypass value */\r
+ /* Set WIDBUS bits according to SDIO_BusWide value */\r
+ /* Set NEGEDGE bits according to SDIO_ClockEdge value */\r
+ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */\r
+ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |\r
+ SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |\r
+ SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); \r
+ \r
+ /* Write to SDIO CLKCR */\r
+ SDIO->CLKCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_InitStruct member with its default value.\r
+ * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which \r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)\r
+{\r
+ /* SDIO_InitStruct members default value */\r
+ SDIO_InitStruct->SDIO_ClockDiv = 0x00;\r
+ SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;\r
+ SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;\r
+ SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;\r
+ SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;\r
+ SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO Clock.\r
+ * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_ClockCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Sets the power status of the controller.\r
+ * @param SDIO_PowerState: new state of the Power state. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_PowerState_OFF: SDIO Power OFF.\r
+ * @arg SDIO_PowerState_ON: SDIO Power ON.\r
+ * @retval None\r
+ */\r
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));\r
+\r
+ SDIO->POWER = SDIO_PowerState;\r
+}\r
+\r
+/**\r
+ * @brief Gets the power status of the controller.\r
+ * @param None\r
+ * @retval Power status of the controller. The returned value can\r
+ * be one of the following:\r
+ * - 0x00: Power OFF\r
+ * - 0x02: Power UP\r
+ * - 0x03: Power ON \r
+ */\r
+uint32_t SDIO_GetPowerState(void)\r
+{\r
+ return (SDIO->POWER & (~PWR_PWRCTRL_MASK));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Group2 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### DMA transfers management functions #####\r
+ ==============================================================================\r
+ [..] This section provide functions allowing to program SDIO DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO DMA request.\r
+ * @param NewState: new state of the selected SDIO DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_DMACmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Group3 Command path state machine (CPSM) management functions\r
+ * @brief Command path state machine (CPSM) management functions \r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Command path state machine (CPSM) management functions #####\r
+ ==============================================================================\r
+ [..] This section provide functions allowing to program and read the Command \r
+ path state machine (CPSM).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SDIO Command according to the specified \r
+ * parameters in the SDIO_CmdInitStruct and send the command.\r
+ * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef \r
+ * structure that contains the configuration information for the SDIO command.\r
+ * @retval None\r
+ */\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));\r
+ assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));\r
+ assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));\r
+ assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));\r
+ \r
+/*---------------------------- SDIO ARG Configuration ------------------------*/\r
+ /* Set the SDIO Argument value */\r
+ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;\r
+ \r
+/*---------------------------- SDIO CMD Configuration ------------------------*/ \r
+ /* Get the SDIO CMD value */\r
+ tmpreg = SDIO->CMD;\r
+ /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */\r
+ tmpreg &= CMD_CLEAR_MASK;\r
+ /* Set CMDINDEX bits according to SDIO_CmdIndex value */\r
+ /* Set WAITRESP bits according to SDIO_Response value */\r
+ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */\r
+ /* Set CPSMEN bits according to SDIO_CPSM value */\r
+ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response\r
+ | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;\r
+ \r
+ /* Write to SDIO CMD */\r
+ SDIO->CMD = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_CmdInitStruct member with its default value.\r
+ * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)\r
+{\r
+ /* SDIO_CmdInitStruct members default value */\r
+ SDIO_CmdInitStruct->SDIO_Argument = 0x00;\r
+ SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;\r
+ SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;\r
+ SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;\r
+ SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Returns command index of last command for which response received.\r
+ * @param None\r
+ * @retval Returns the command index of the last command response received.\r
+ */\r
+uint8_t SDIO_GetCommandResponse(void)\r
+{\r
+ return (uint8_t)(SDIO->RESPCMD);\r
+}\r
+\r
+/**\r
+ * @brief Returns response received from the card for the last command.\r
+ * @param SDIO_RESP: Specifies the SDIO response register. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_RESP1: Response Register 1.\r
+ * @arg SDIO_RESP2: Response Register 2.\r
+ * @arg SDIO_RESP3: Response Register 3.\r
+ * @arg SDIO_RESP4: Response Register 4.\r
+ * @retval The Corresponding response register value.\r
+ */\r
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_RESP(SDIO_RESP));\r
+\r
+ tmp = SDIO_RESP_ADDR + SDIO_RESP;\r
+ \r
+ return (*(__IO uint32_t *) tmp); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Group4 Data path state machine (DPSM) management functions\r
+ * @brief Data path state machine (DPSM) management functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Data path state machine (DPSM) management functions #####\r
+ ==============================================================================\r
+ [..] This section provide functions allowing to program and read the Data path \r
+ state machine (DPSM).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SDIO data path according to the specified \r
+ * parameters in the SDIO_DataInitStruct.\r
+ * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that\r
+ * contains the configuration information for the SDIO command.\r
+ * @retval None\r
+ */\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));\r
+ assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));\r
+ assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));\r
+ assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));\r
+ assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));\r
+\r
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/\r
+ /* Set the SDIO Data TimeOut value */\r
+ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;\r
+\r
+/*---------------------------- SDIO DLEN Configuration -----------------------*/\r
+ /* Set the SDIO DataLength value */\r
+ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;\r
+\r
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/ \r
+ /* Get the SDIO DCTRL value */\r
+ tmpreg = SDIO->DCTRL;\r
+ /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */\r
+ tmpreg &= DCTRL_CLEAR_MASK;\r
+ /* Set DEN bit according to SDIO_DPSM value */\r
+ /* Set DTMODE bit according to SDIO_TransferMode value */\r
+ /* Set DTDIR bit according to SDIO_TransferDir value */\r
+ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */\r
+ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir\r
+ | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;\r
+\r
+ /* Write to SDIO DCTRL */\r
+ SDIO->DCTRL = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_DataInitStruct member with its default value.\r
+ * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
+{\r
+ /* SDIO_DataInitStruct members default value */\r
+ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;\r
+ SDIO_DataInitStruct->SDIO_DataLength = 0x00;\r
+ SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;\r
+ SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;\r
+ SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; \r
+ SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Returns number of remaining data bytes to be transferred.\r
+ * @param None\r
+ * @retval Number of remaining data bytes to be transferred\r
+ */\r
+uint32_t SDIO_GetDataCounter(void)\r
+{ \r
+ return SDIO->DCOUNT;\r
+}\r
+\r
+/**\r
+ * @brief Read one data word from Rx FIFO.\r
+ * @param None\r
+ * @retval Data received\r
+ */\r
+uint32_t SDIO_ReadData(void)\r
+{ \r
+ return SDIO->FIFO;\r
+}\r
+\r
+/**\r
+ * @brief Write one data word to Tx FIFO.\r
+ * @param Data: 32-bit data word to write.\r
+ * @retval None\r
+ */\r
+void SDIO_WriteData(uint32_t Data)\r
+{ \r
+ SDIO->FIFO = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of words left to be written to or read from FIFO. \r
+ * @param None\r
+ * @retval Remaining number of words.\r
+ */\r
+uint32_t SDIO_GetFIFOCount(void)\r
+{ \r
+ return SDIO->FIFOCNT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Group5 SDIO IO Cards mode management functions\r
+ * @brief SDIO IO Cards mode management functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### SDIO IO Cards mode management functions #####\r
+ ==============================================================================\r
+ [..] This section provide functions allowing to program and read the SDIO IO \r
+ Cards.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the SD I/O Read Wait operation. \r
+ * @param NewState: new state of the Start SDIO Read Wait operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;\r
+}\r
+\r
+/**\r
+ * @brief Stops the SD I/O Read Wait operation. \r
+ * @param NewState: new state of the Stop SDIO Read Wait operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;\r
+}\r
+\r
+/**\r
+ * @brief Sets one of the two options of inserting read wait interval.\r
+ * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.\r
+ * This parametre can be:\r
+ * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK.\r
+ * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2.\r
+ * @retval None\r
+ */\r
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SD I/O Mode Operation.\r
+ * @param NewState: new state of SDIO specific operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SetSDIOOperation(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SD I/O Mode suspend command sending.\r
+ * @param NewState: new state of the SD I/O Mode suspend command.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Group6 CE-ATA mode management functions\r
+ * @brief CE-ATA mode management functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### CE-ATA mode management functions #####\r
+ ==============================================================================\r
+ [..] This section provide functions allowing to program and read the CE-ATA \r
+ card.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the command completion signal.\r
+ * @param NewState: new state of command completion signal. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CE-ATA interrupt.\r
+ * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_CEATAITCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));\r
+}\r
+\r
+/**\r
+ * @brief Sends CE-ATA command (CMD61).\r
+ * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SendCEATACmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Group7 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+\r
+\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ==============================================================================\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO interrupts.\r
+ * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt.\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt.\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt.\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt.\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt.\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.\r
+ * @param NewState: new state of the specified SDIO interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None \r
+ */\r
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_IT(SDIO_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SDIO interrupts */\r
+ SDIO->MASK |= SDIO_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SDIO interrupts */\r
+ SDIO->MASK &= ~SDIO_IT;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SDIO flag is set or not.\r
+ * @param SDIO_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).\r
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).\r
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout.\r
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout.\r
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.\r
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error.\r
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed).\r
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required).\r
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).\r
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode.\r
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).\r
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress.\r
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress.\r
+ * @arg SDIO_FLAG_RXACT: Data receive in progress.\r
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty.\r
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full.\r
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full.\r
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full.\r
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty.\r
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty.\r
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO.\r
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO.\r
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received.\r
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.\r
+ * @retval The new state of SDIO_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)\r
+{ \r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_FLAG(SDIO_FLAG));\r
+ \r
+ if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SDIO's pending flags.\r
+ * @param SDIO_FLAG: specifies the flag to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).\r
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).\r
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout.\r
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout.\r
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.\r
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error.\r
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed).\r
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required).\r
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).\r
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode.\r
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).\r
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received.\r
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.\r
+ * @retval None\r
+ */\r
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));\r
+ \r
+ SDIO->ICR = SDIO_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.\r
+ * @param SDIO_IT: specifies the SDIO interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt.\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt.\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt.\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt.\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt.\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.\r
+ * @retval The new state of SDIO_IT (SET or RESET).\r
+ */\r
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)\r
+{ \r
+ ITStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_GET_IT(SDIO_IT));\r
+ if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) \r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SDIO's interrupt pending bits.\r
+ * @param SDIO_IT: specifies the interrupt pending bit to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt.\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61.\r
+ * @retval None\r
+ */\r
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));\r
+ \r
+ SDIO->ICR = SDIO_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_spi.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Serial peripheral interface (SPI):\r
+ * + Initialization and Configuration\r
+ * + Data transfers functions\r
+ * + Hardware CRC Calculation\r
+ * + DMA transfers management\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ [..] The I2S feature is not implemented in STM32L1xx Ultra Low Power\r
+ Medium-density devices and it's supported only STM32L1xx Ultra Low Power\r
+ Medium-density Plus and High-density devices.\r
+ \r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)\r
+ function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)\r
+ function for SPI2 or using RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE)\r
+ for SPI3.\r
+ \r
+ (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using \r
+ RCC_AHBPeriphClockCmd() function. \r
+ \r
+ (#) Peripherals alternate function: \r
+ (++) Connect the pin to the desired peripherals' Alternate \r
+ Function (AF) using GPIO_PinAFConfig() function.\r
+ (++) Configure the desired pin in alternate function by:\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
+ (++) Select the type, pull-up/pull-down and output speed via \r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
+ (++) Call GPIO_Init() function.\r
+ \r
+ (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave \r
+ Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
+ function.In I2S mode, program the Mode, Standard, Data Format, MCLK \r
+ Output, Audio frequency and Polarity using I2S_Init() function.\r
+ \r
+ (#) Enable the NVIC and the corresponding interrupt using the function \r
+ SPI_ITConfig() if you need to use interrupt mode. \r
+ \r
+ (#) When using the DMA mode \r
+ (++) Configure the DMA using DMA_Init() function.\r
+ (++) Active the needed channel Request using SPI_I2S_DMACmd() function.\r
+ \r
+ (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using\r
+ I2S_Cmd().\r
+ \r
+ (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. \r
+ \r
+ (#) Optionally, you can enable/configure the following parameters without\r
+ re-initialization (i.e there is no need to call again SPI_Init() function):\r
+ (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)\r
+ is programmed as Data direction parameter using the SPI_Init() \r
+ function it can be possible to switch between SPI_Direction_Tx \r
+ or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.\r
+ (++) When SPI_NSS_Soft is selected as Slave Select Management parameter \r
+ using the SPI_Init() function it can be possible to manage the \r
+ NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.\r
+ (++) Reconfigure the data size using the SPI_DataSizeConfig() function.\r
+ (++) Enable or disable the SS output using the SPI_SSOutputCmd() function. \r
+ \r
+ (#) To use the CRC Hardware calculation feature refer to the Peripheral \r
+ CRC hardware Calculation subsection.\r
+ \r
+ @endverbatim \r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_spi.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI \r
+ * @brief SPI driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_MASK ((uint16_t)0x3040)\r
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides a set of functions allowing to initialize the SPI \r
+ Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS \r
+ Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.\r
+ [..] The SPI_Init() function follows the SPI configuration procedures for \r
+ Master mode and Slave mode (details for these procedures are available \r
+ in reference manual (RM0038)).\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SPIx peripheral registers to their default\r
+ * reset values.\r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ if (SPIx == SPI1)\r
+ {\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ }\r
+ else if (SPIx == SPI2)\r
+ {\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (SPIx == SPI3)\r
+ {\r
+ /* Enable SPI3 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r
+ /* Release SPI3 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the SPI_InitStruct.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Check the SPI parameters */\r
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_MASK;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/salve mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+\r
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
+ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);\r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the I2S_InitStruct.\r
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral\r
+ * (configured in I2S mode).\r
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral\r
+ * configured in I2S mode.\r
+ * @note\r
+ * The function calculates the optimal prescaler needed to obtain the most \r
+ * accurate audio frequency (depending on the I2S clock source, the PLL values \r
+ * and the product configuration). But in case the prescaler value is greater \r
+ * than 511, the default value (0x02) will be configured instead. \r
+ * @retval None\r
+ */\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
+ uint32_t tmp = 0;\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+ uint32_t sourceclock = 0;\r
+ \r
+ /* Check the I2S parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
+\r
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
+ SPIx->I2SPR = 0x0002;\r
+ \r
+ /* Get the I2SCFGR register value */\r
+ tmpreg = SPIx->I2SCFGR;\r
+ \r
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
+ {\r
+ i2sodd = (uint16_t)0;\r
+ i2sdiv = (uint16_t)2; \r
+ }\r
+ /* If the requested audio frequency is not the default, compute the prescaler */\r
+ else\r
+ {\r
+ /* Check the frame length (For the Prescaler computing) */\r
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
+ {\r
+ /* Packet length is 16 bits */\r
+ packetlength = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Packet length is 32 bits */\r
+ packetlength = 2;\r
+ }\r
+\r
+ /* I2S Clock source is System clock: Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks); \r
+ \r
+ /* Get the source clock value: based on System Clock value */\r
+ sourceclock = RCC_Clocks.SYSCLK_Frequency; \r
+ \r
+ /* Compute the Real divider depending on the MCLK output state with a flaoting point */\r
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
+ {\r
+ /* MCLK output is enabled */\r
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ else\r
+ {\r
+ /* MCLK output is disabled */\r
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ \r
+ /* Remove the flaoting point */\r
+ tmp = tmp / 10; \r
+ \r
+ /* Check the parity of the divider */\r
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
+ \r
+ /* Compute the i2sdiv prescaler */\r
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
+ \r
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
+ i2sodd = (uint16_t) (i2sodd << 8);\r
+ }\r
+ \r
+ /* Test if the divider is 1 or 0 or greater than 0xFF */\r
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
+ {\r
+ /* Set the default values */\r
+ i2sdiv = 2;\r
+ i2sodd = 0;\r
+ }\r
+\r
+ /* Write to SPIx I2SPR register the computed value */\r
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); \r
+ \r
+ /* Configure the I2S with the SPI_InitStruct values */\r
+ tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \\r
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\r
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));\r
+ \r
+ /* Write to SPIx I2SCFGR */ \r
+ SPIx->I2SCFGR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Fills each SPI_InitStruct member with its default value.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ /* initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+ /* initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2S_InitStruct member with its default value.\r
+ * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+/*--------------- Reset I2S init structure parameters values -----------------*/\r
+ /* Initialize the I2S_Mode member */\r
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
+ \r
+ /* Initialize the I2S_Standard member */\r
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
+ \r
+ /* Initialize the I2S_DataFormat member */\r
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
+ \r
+ /* Initialize the I2S_MCLKOutput member */\r
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
+ \r
+ /* Initialize the I2S_AudioFreq member */\r
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
+ \r
+ /* Initialize the I2S_CPOL member */\r
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= SPI_CR1_SPE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral in I2S mode */\r
+ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the data size for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_DataSize: specifies the SPI data size.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit.\r
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit.\r
+ * @retval None.\r
+ */\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
+ /* Clear DFF bit */\r
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
+ /* Set new DFF bit value */\r
+ SPIx->CR1 |= SPI_DataSize;\r
+}\r
+\r
+/**\r
+ * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction.\r
+ * @arg SPI_Direction_Rx: Selects Rx receive direction.\r
+ * @retval None\r
+ */\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures internally by software the NSS pin for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally.\r
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally.\r
+ * @retval None\r
+ */\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SS output for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx SS output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group2 Data transfers functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Data transfers functions #####\r
+ ===============================================================================\r
+....[..] This section provides a set of functions allowing to manage the SPI data \r
+ transfers.\r
+....[..] In reception, data are received and then stored into an internal Rx buffer \r
+ while In transmission, data are first stored into an internal Tx buffer \r
+ before being transmitted.\r
+....[..] The read access of the SPI_DR register can be done using the \r
+ SPI_I2S_ReceiveData() function and returns the Rx buffered value. \r
+ Whereas a write access to the SPI_DR can be done using SPI_I2S_SendData() \r
+ function and stores the written data into Tx buffer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3\r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+ * @retval The value of the received data.\r
+ */\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the data in the DR register */\r
+ return SPIx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+ * @param Data: Data to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Write in the DR register the data to be sent */\r
+ SPIx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions\r
+ * @brief Hardware CRC Calculation functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Hardware CRC Calculation functions #####\r
+ ===============================================================================\r
+ [..] This section provides a set of functions allowing to manage the SPI CRC \r
+ hardware calculation SPI communication using CRC is possible through \r
+ the following procedure:\r
+ (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate \r
+ Prescaler, Slave Management, Peripheral Mode and CRC Polynomial \r
+ values using the SPI_Init() function.\r
+ (#) Enable the CRC calculation using the SPI_CalculateCRC() function.\r
+ (#) Enable the SPI using the SPI_Cmd() function.\r
+ (#) Before writing the last data to the TX buffer, set the CRCNext bit \r
+ using the SPI_TransmitCRC() function to indicate that after \r
+ transmission of the last data, the CRC should be transmitted.\r
+ (#) After transmitting the last data, the SPI transmits the CRC.\r
+ The SPI_CR1_CRCNEXT bit is reset. The CRC is also received and \r
+ compared against the SPI_RXCRCR value. \r
+ If the value does not match, the SPI_FLAG_CRCERR flag is set and an \r
+ interrupt can be generated when the SPI_I2S_IT_ERR interrupt is enabled.\r
+ -@-\r
+ (+@) It is advised to don't read the calculate CRC values during the communication.\r
+ (+@) When the SPI is in slave mode, be careful to enable CRC calculation only \r
+ when the clock is stable, that is, when the clock is in the steady state. \r
+ If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive \r
+ to the SCK slave input clock as soon as CRCEN is set, and this, whatever \r
+ the value of the SPE bit.\r
+ (+@) With high bitrate frequencies, be careful when transmitting the CRC.\r
+ As the number of used CPU cycles has to be as low as possible in the CRC \r
+ transfer phase, it is forbidden to call software functions in the CRC \r
+ transmission sequence to avoid errors in the last data and CRC reception. \r
+ In fact, CRCNEXT bit has to be written before the end of the transmission/\r
+ reception of the last data.\r
+ (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the\r
+ degradation of the SPI speed performance due to CPU accesses impacting the \r
+ SPI bandwidth.\r
+ (+@) When the STM32L15xxx are configured as slaves and the NSS hardware mode is \r
+ used, the NSS pin needs to be kept low between the data phase and the CRC \r
+ phase.\r
+ (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC\r
+ calculation takes place even if a high level is applied on the NSS pin. \r
+ This may happen for example in case of a multislave environment where the \r
+ communication master addresses slaves alternately.\r
+ (+@) Between a slave deselection (high level on NSS) and a new slave selection \r
+ (low level on NSS), the CRC value should be cleared on both master and slave\r
+ sides in order to resynchronize the master and slave for their respective \r
+ CRC calculation.\r
+ -@- To clear the CRC, follow the procedure below:\r
+ (#@) Disable SPI using the SPI_Cmd() function\r
+ (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.\r
+ (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.\r
+ (#@) Enable SPI using the SPI_Cmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx CRC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= SPI_CR1_CRCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit the SPIx CRC value.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= SPI_CR1_CRCNEXT;\r
+}\r
+\r
+/**\r
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_CRC: specifies the CRC register to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_CRC_Tx: Selects Tx CRC register.\r
+ * @arg SPI_CRC_Rx: Selects Rx CRC register.\r
+ * @retval The selected CRC register value.\r
+ */\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
+{\r
+ uint16_t crcreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC(SPI_CRC));\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the CRC Polynomial register value for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval The CRC Polynomial register value.\r
+ */\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group4 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DMA transfers management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.\r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+ * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request.\r
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request.\r
+ * @param NewState: new state of the selected SPI DMA transfer request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI DMA requests */\r
+ SPIx->CR2 |= SPI_I2S_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI DMA requests */\r
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group5 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] This section provides a set of functions allowing to configure the SPI \r
+ Interrupts sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to \r
+ manage the communication: Polling mode, Interrupt mode or DMA mode.\r
+ *** Polling Mode ***\r
+ ====================\r
+ [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:\r
+ (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer \r
+ register.\r
+ (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer \r
+ register.\r
+ (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer \r
+ of the SPI.\r
+ (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.\r
+ (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.\r
+ (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.\r
+ (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.\r
+ (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.\r
+ (#) I2S_FLAG_CHSIDE: to indicate Channel Side.\r
+ -@- Do not use the BSY flag to handle each data transmission or reception.\r
+ It is better to use the TXE and RXNE flags instead.\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).\r
+ (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).\r
+\r
+ *** Interrupt Mode ***\r
+ ======================\r
+ [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt \r
+ sources and 7 pending bits: \r
+ [..] Pending Bits:\r
+ (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.\r
+ (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.\r
+ (#) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur.\r
+ (#) SPI_IT_MODF : to indicate if a Mode Fault error occur.\r
+ (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.\r
+ (#) I2S_IT_UDR : to indicate an Underrun Error occurs.\r
+ (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.\r
+ [..] Interrupt Source:\r
+ (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty \r
+ interrupt.\r
+ (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
+ empty interrupt.\r
+ (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT,\r
+ FunctionalState NewState).\r
+ (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).\r
+ (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).\r
+\r
+ *** DMA Mode ***\r
+ ================\r
+ [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel \r
+ requests:\r
+ (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.\r
+ (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.\r
+\r
+ [..] In this Mode it is advised to use the following function:\r
+ (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq,\r
+ FunctionalState NewState).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI/I2S interrupts.\r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+\r
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask.\r
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask.\r
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask.\r
+ * @param NewState: new state of the specified SPI interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
+{\r
+ uint16_t itpos = 0, itmask = 0 ;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = (uint16_t)1 << (uint16_t)itpos;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI interrupt */\r
+ SPIx->CR2 &= (uint16_t)~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPIx/I2Sx flag is set or not.\r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+\r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
+ * @arg SPI_FLAG_MODF: Mode Fault flag.\r
+ * @arg SPI_FLAG_CRCERR: CRC Error flag.\r
+ * @arg SPI_I2S_FLAG_FRE: Format Error.\r
+ * @arg I2S_FLAG_UDR: Underrun Error flag.\r
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.\r
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Check the status of the specified SPI flag */\r
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
+ {\r
+ /* SPI_I2S_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+\r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
+ * This function clears only CRCERR flag.\r
+\r
+ * @note OVR (OverRun error) flag is cleared by software sequence: a read \r
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * @note UDR (UnderRun error) flag is cleared by a read operation to \r
+ * SPI_SR register (SPI_I2S_GetFlagStatus()). \r
+ * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Clear the selected SPI CRC Error (CRCERR) flag */\r
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.\r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+\r
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
+ * @arg SPI_IT_MODF: Mode Fault interrupt.\r
+ * @arg SPI_IT_CRCERR: CRC Error interrupt.\r
+ * @arg I2S_IT_UDR: Underrun interrupt. \r
+ * @arg SPI_I2S_IT_FRE: Format Error interrupt. \r
+ * @retval The new state of SPI_I2S_IT (SET or RESET).\r
+ */\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI_I2S_IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Get the SPI_I2S_IT IT mask */\r
+ itmask = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = 0x01 << itmask;\r
+\r
+ /* Get the SPI_I2S_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI interrupt */\r
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
+ {\r
+ /* SPI_I2S_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
+ * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r
+ * in SPI mode or 2 or 3 in I2S mode.\r
+\r
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
+ * This function clears only CRCERR interrupt pending bit. \r
+\r
+ * OVR (OverRun Error) interrupt pending bit is cleared by software \r
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetITStatus()). \r
+ * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
+ * the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ uint16_t itpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI_I2S IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
+ SPIx->SR = (uint16_t)~itpos;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_syscfg.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following\r
+ * functionalities of the SYSCFG and RI peripherals:\r
+ * + SYSCFG Initialization and Configuration\r
+ * + RI Initialization and Configuration\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..] This driver provides functions for:\r
+ (#) Remapping the memory accessible in the code area using\r
+ SYSCFG_MemoryRemapConfig().\r
+ (#) Manage the EXTI lines connection to the GPIOs using\r
+ SYSCFG_EXTILineConfig().\r
+ (#) Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4).\r
+ (#) Input routing of COMP1 and COMP2.\r
+ (#) Routing of internal reference voltage VREFINT to PB0 and PB1.\r
+ (#) The RI registers can be accessed only when the comparator\r
+ APB interface clock is enabled.\r
+ To enable comparator clock use:\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).\r
+ Following functions uses RI registers:\r
+ (++) SYSCFG_RIDeInit()\r
+ (++) SYSCFG_RITIMSelect()\r
+ (++) SYSCFG_RITIMInputCaptureConfig()\r
+ (++) SYSCFG_RIResistorConfig()\r
+ (++) SYSCFG_RIChannelSpeedConfig()\r
+ (++) SYSCFG_RIIOSwitchConfig()\r
+ (++) SYSCFG_RISwitchControlModeCmd()\r
+ (++) SYSCFG_RIHysteresisConfig()\r
+ (#) The SYSCFG registers can be accessed only when the SYSCFG\r
+ interface APB clock is enabled.\r
+ To enable SYSCFG APB clock use:\r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ Following functions uses SYSCFG registers:\r
+ (++) SYSCFG_DeInit() \r
+ (++) SYSCFG_MemoryRemapConfig()\r
+ (++) SYSCFG_GetBootMode() \r
+ (++) SYSCFG_USBPuCmd()\r
+ (++) SYSCFG_EXTILineConfig()\r
+@endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_syscfg.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG \r
+ * @brief SYSCFG driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */\r
+#define IC_ROUTING_MASK ((uint32_t)0x0000000F) /*!< Input Capture routing mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions\r
+ * @brief SYSCFG Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### SYSCFG Initialization and Configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SYSCFG registers to their default reset values.\r
+ * @param None.\r
+ * @retval None.\r
+ * @Note: MEMRMP bits are not reset by APB2 reset.\r
+ */\r
+void SYSCFG_DeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the RI registers to their default reset values.\r
+ * @param None.\r
+ * @retval None.\r
+ */\r
+void SYSCFG_RIDeInit(void)\r
+{\r
+ RI->ICR = ((uint32_t)0x00000000); /*!< Set RI->ICR to reset value */\r
+ RI->ASCR1 = ((uint32_t)0x00000000); /*!< Set RI->ASCR1 to reset value */\r
+ RI->ASCR2 = ((uint32_t)0x00000000); /*!< Set RI->ASCR2 to reset value */\r
+ RI->HYSCR1 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR1 to reset value */\r
+ RI->HYSCR2 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR2 to reset value */\r
+ RI->HYSCR3 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR3 to reset value */\r
+ RI->HYSCR4 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR4 to reset value */\r
+}\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified memory.\r
+ * @param SYSCFG_Memory: selects the memory remapping.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 \r
+ * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000\r
+ * @arg SYSCFG_MemoryRemap_FSMC: FSMC memory mapped at 0x00000000 \r
+ * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000\r
+ * @retval None\r
+ */\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));\r
+ SYSCFG->MEMRMP = SYSCFG_MemoryRemap;\r
+}\r
+\r
+/**\r
+ * @brief Returns the boot mode as configured by user.\r
+ * @param None.\r
+ * @retval The boot mode as configured by user. The returned value can be one \r
+ * of the following values:\r
+ * - 0x00000000: Boot is configured in Main Flash memory\r
+ * - 0x00000100: Boot is configured in System Flash memory\r
+ * - 0x00000200: Boot is configured in FSMC memory\r
+ * - 0x00000300: Boot is configured in Embedded SRAM memory\r
+ */\r
+uint32_t SYSCFG_GetBootMode(void)\r
+{\r
+ return (SYSCFG->MEMRMP & SYSCFG_MEMRMP_BOOT_MODE);\r
+}\r
+\r
+/**\r
+ * @brief Control the internal pull-up on USB DP line.\r
+ * @param NewState: New state of the internal pull-up on USB DP line. \r
+ * This parameter can be ENABLE: Connect internal pull-up on USB DP line.\r
+ * or DISABLE: Disconnect internal pull-up on USB DP line.\r
+ * @retval None\r
+ */\r
+void SYSCFG_USBPuCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Connect internal pull-up on USB DP line */\r
+ SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;\r
+ }\r
+ else\r
+ {\r
+ /* Disconnect internal pull-up on USB DP line */\r
+ SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as EXTI Line.\r
+ * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source \r
+ * for EXTI lines where x can be (A, B, C, D, E, F, G or H).\r
+ * @param EXTI_PinSourcex: specifies the EXTI line to be configured.\r
+ * This parameter can be EXTI_PinSourcex where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r
+{\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r
+ assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r
+ \r
+ tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Group2 RI Initialization and Configuration functions\r
+ * @brief RI Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RI Initialization and Configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the routing interface to select which Timer to be routed.\r
+ * @note Routing capability can be applied only on one of the three timers\r
+ * (TIM2, TIM3 or TIM4) at a time.\r
+ * @param TIM_Select: Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Select_None: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_Select_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_Select_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_Select_TIM4: Timer 4 Input Captures to be routed.\r
+ * @retval None.\r
+ */\r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_TIM(TIM_Select));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = RI->ICR;\r
+\r
+ /* Clear the TIMx select bits */\r
+ tmpreg &= TIM_SELECT_MASK;\r
+\r
+ /* Select the Timer */\r
+ tmpreg |= (TIM_Select);\r
+\r
+ /* Write to RI->ICR register */\r
+ RI->ICR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 1, 2, 3 or 4\r
+ * to a selected I/O pin.\r
+ * @param RI_InputCapture selects which input capture to be routed.\r
+ * This parameter can be one (or combination) of the following parameters:\r
+ * @arg RI_InputCapture_IC1: Input capture 1 is selected.\r
+ * @arg RI_InputCapture_IC2: Input capture 2 is selected.\r
+ * @arg RI_InputCapture_IC3: Input capture 3 is selected.\r
+ * @arg RI_InputCapture_IC4: Input capture 4 is selected.\r
+ * @param RI_InputCaptureRouting: selects which pin to be routed to Input Capture.\r
+ * This parameter can be one of the following values:\r
+ * @param RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15\r
+ * e.g.\r
+ * SYSCFG_RITIMSelect(TIM_Select_TIM2)\r
+ * SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1)\r
+ * allows routing of Input capture IC1 of TIM2 to PA4.\r
+ * For details about correspondence between RI_InputCaptureRouting_x \r
+ * and I/O pins refer to the parameters' description in the header file\r
+ * or refer to the product reference manual.\r
+ * @note Input capture selection bits are not reset by this function.\r
+ * To reset input capture selection bits, use SYSCFG_RIDeInit() function.\r
+ * @note The I/O should be configured in alternate function mode (AF14) using\r
+ * GPIO_PinAFConfig() function.\r
+ * @retval None.\r
+ */\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = RI->ICR;\r
+\r
+ /* Select input captures to be routed */\r
+ tmpreg |= (RI_InputCapture);\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~IC_ROUTING_MASK);\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( RI_InputCaptureRouting);\r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4));\r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8));\r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12));\r
+ }\r
+\r
+ /* Write to RI->ICR register */\r
+ RI->ICR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Pull-up and Pull-down Resistors \r
+ * @param RI_Resistor selects the resistor to connect. \r
+ * This parameter can be one of the following values:\r
+ * @arg RI_Resistor_10KPU: 10K pull-up resistor.\r
+ * @arg RI_Resistor_400KPU: 400K pull-up resistor.\r
+ * @arg RI_Resistor_10KPD: 10K pull-down resistor.\r
+ * @arg RI_Resistor_400KPD: 400K pull-down resistor.\r
+ * @param NewState: New state of the analog switch associated to the selected \r
+ * resistor.\r
+ * This parameter can be:\r
+ * ENABLE so the selected resistor is connected\r
+ * or DISABLE so the selected resistor is disconnected.\r
+ * @note To avoid extra power consumption, only one resistor should be enabled\r
+ * at a time. \r
+ * @retval None\r
+ */\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_RESISTOR(RI_Resistor));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the resistor */\r
+ COMP->CSR |= (uint32_t) RI_Resistor;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Resistor */\r
+ COMP->CSR &= (uint32_t) (~RI_Resistor);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADC channels speed.\r
+ * @param RI_Channel selects the channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg RI_Channel_3: Channel 3 is selected.\r
+ * @arg RI_Channel_8: Channel 8 is selected.\r
+ * @arg RI_Channel_13: Channel 13 is selected.\r
+ * @param RI_ChannelSpeed: The speed of the selected ADC channel\r
+ * This parameter can be:\r
+ * RI_ChannelSpeed_Fast: The selected channel is a fast ADC channel \r
+ * or RI_ChannelSpeed_Slow: The selected channel is a slow ADC channel.\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_CHANNEL(RI_Channel));\r
+ assert_param(IS_RI_CHANNELSPEED(RI_ChannelSpeed));\r
+\r
+ if(RI_ChannelSpeed != RI_ChannelSpeed_Fast)\r
+ {\r
+ /* Set the selected channel as a slow ADC channel */\r
+ COMP->CSR &= (uint32_t) (~RI_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Set the selected channel as a fast ADC channel */\r
+ COMP->CSR |= (uint32_t) (RI_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Close or Open the routing interface Input Output switches.\r
+ * @param RI_IOSwitch: selects the I/O analog switch number.\r
+ * This parameter can be one of the following values:\r
+ * @param RI_IOSwitch_CH0 --> RI_IOSwitch_CH15.\r
+ * @param RI_IOSwitch_CH18 --> RI_IOSwitch_CH25.\r
+ * @param RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4.\r
+ * @param RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2.\r
+ * @param RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3.\r
+ * @param RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3.\r
+ * @param RI_IOSwitch_VCOMP\r
+ * RI_IOSwitch_CH27\r
+ * @param RI_IOSwitch_CH28 --> RI_IOSwitch_CH30\r
+ * @param RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4\r
+ * @param RI_IOSwitch_GR6_1\r
+ * @param RI_IOSwitch_GR6_2\r
+ * @param RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3\r
+ * @param RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_4\r
+ * @param RI_IOSwitch_CH0b --> RI_IOSwitch_CH3b\r
+ * @param RI_IOSwitch_CH6b --> RI_IOSwitch_CH12b\r
+ * @param RI_IOSwitch_GR6_3\r
+ * @param RI_IOSwitch_GR6_4\r
+ * @param RI_IOSwitch_GR5_4\r
+ \r
+ * @param NewState: New state of the analog switch. \r
+ * This parameter can be \r
+ * ENABLE so the Input Output switch is closed\r
+ * or DISABLE so the Input Output switch is open.\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)\r
+{\r
+ uint32_t ioswitchmask = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RI_IOSWITCH(RI_IOSwitch));\r
+ \r
+ /* Read Analog switch register index */\r
+ ioswitchmask = RI_IOSwitch >> 31;\r
+ \r
+ /* Get Bits[30:0] of the IO switch */\r
+ RI_IOSwitch &= 0x7FFFFFFF;\r
+ \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ if (ioswitchmask != 0)\r
+ {\r
+ /* Close the analog switches */\r
+ RI->ASCR1 |= RI_IOSwitch;\r
+ }\r
+ else\r
+ {\r
+ /* Open the analog switches */\r
+ RI->ASCR2 |= RI_IOSwitch;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (ioswitchmask != 0)\r
+ {\r
+ /* Close the analog switches */\r
+ RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);\r
+ }\r
+ else\r
+ {\r
+ /* Open the analog switches */\r
+ RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the switch control mode.\r
+ * @param NewState: New state of the switch control mode. This parameter can\r
+ * be ENABLE: ADC analog switches closed if the corresponding \r
+ * I/O switch is also closed.\r
+ * When using COMP1, switch control mode must be enabled.\r
+ * or DISABLE: ADC analog switches open or controlled by the ADC interface.\r
+ * When using the ADC for acquisition, switch control mode \r
+ * must be disabled.\r
+ * @note COMP1 comparator and ADC cannot be used at the same time since \r
+ * they share the ADC switch matrix.\r
+ * @retval None\r
+ */\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Switch control mode */\r
+ RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Switch control mode */\r
+ RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A..E\r
+ * When the I/Os are programmed in input mode by standard I/O port \r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the \r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param RI_Port: selects the GPIO Port.\r
+ * This parameter can be one of the following values:\r
+ * @arg RI_PortA: Port A is selected\r
+ * @arg RI_PortB: Port B is selected\r
+ * @arg RI_PortC: Port C is selected\r
+ * @arg RI_PortD: Port D is selected\r
+ * @arg RI_PortE: Port E is selected\r
+ * @arg RI_PortF: Port F is selected\r
+ * @arg RI_PortG: Port G is selected\r
+ * @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.\r
+ * @param NewState new state of the Hysteresis.\r
+ * This parameter can be:\r
+ * ENABLE so the Hysteresis is on\r
+ * or DISABLE so the Hysteresis is off\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+ FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_PORT(RI_Port));\r
+ assert_param(IS_RI_PIN(RI_Pin));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(RI_Port == RI_PortA)\r
+ { \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR1 |= (uint32_t) RI_Pin;\r
+ }\r
+ }\r
+ \r
+ else if(RI_Port == RI_PortB)\r
+ {\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+ }\r
+ } \r
+ \r
+ else if(RI_Port == RI_PortC)\r
+ {\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR2 |= (uint32_t) (RI_Pin );\r
+ }\r
+ } \r
+ else if(RI_Port == RI_PortD)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+\r
+ }\r
+ }\r
+ else if(RI_Port == RI_PortE)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR3 |= (uint32_t) (RI_Pin );\r
+ }\r
+ }\r
+ else if(RI_Port == RI_PortF)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR3 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+ }\r
+ }\r
+ else /* RI_Port == RI_PortG */\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR4 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR4 |= (uint32_t) (RI_Pin);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_tim.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the TIM peripheral:\r
+ * + TimeBase management\r
+ * + Output Compare management\r
+ * + Input Capture management\r
+ * + Interrupts, DMA and flags management\r
+ * + Clocks management\r
+ * + Synchronization management\r
+ * + Specific interface management\r
+ * + Specific remapping management \r
+ * \r
+* @verbatim\r
+ \r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..] This driver provides functions to configure and program the TIM \r
+ of all STM32L1xx devices These functions are split in 8 groups: \r
+ (#) TIM TimeBase management: this group includes all needed functions \r
+ to configure the TM Timebase unit:\r
+ (++) Set/Get Prescaler.\r
+ (++) Set/Get Autoreload.\r
+ (++) Counter modes configuration.\r
+ (++) Set Clock division.\r
+ (++) Select the One Pulse mode.\r
+ (++) Update Request Configuration.\r
+ (++) Update Disable Configuration.\r
+ (++) Auto-Preload Configuration.\r
+ (++) Enable/Disable the counter.\r
+ \r
+ (#) TIM Output Compare management: this group includes all needed \r
+ functions to configure the Capture/Compare unit used in Output \r
+ compare mode: \r
+ (++) Configure each channel, independently, in Output Compare mode.\r
+ (++) Select the output compare modes.\r
+ (++) Select the Polarities of each channel.\r
+ (++) Set/Get the Capture/Compare register values.\r
+ (++) Select the Output Compare Fast mode. \r
+ (++) Select the Output Compare Forced mode. \r
+ (++) Output Compare-Preload Configuration. \r
+ (++) Clear Output Compare Reference.\r
+ (++) Select the OCREF Clear signal.\r
+ (++) Enable/Disable the Capture/Compare Channels. \r
+ \r
+ (#) TIM Input Capture management: this group includes all needed \r
+ functions to configure the Capture/Compare unit used in \r
+ Input Capture mode:\r
+ (++) Configure each channel in input capture mode.\r
+ (++) Configure Channel1/2 in PWM Input mode.\r
+ (++) Set the Input Capture Prescaler.\r
+ (++) Get the Capture/Compare values. \r
+ \r
+ (#) TIM interrupts, DMA and flags management.\r
+ (++) Enable/Disable interrupt sources.\r
+ (++) Get flags status.\r
+ (++) Clear flags/ Pending bits.\r
+ (++) Enable/Disable DMA requests. \r
+ (++) Configure DMA burst mode.\r
+ (++) Select CaptureCompare DMA request. \r
+ \r
+ (#) TIM clocks management: this group includes all needed functions \r
+ to configure the clock controller unit:\r
+ (++) Select internal/External clock.\r
+ (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.\r
+ \r
+ (#) TIM synchronization management: this group includes all needed. \r
+ functions to configure the Synchronization unit:\r
+ (++) Select Input Trigger. \r
+ (++) Select Output Trigger. \r
+ (++) Select Master Slave Mode. \r
+ (++) ETR Configuration when used as external trigger. \r
+ \r
+ (#) TIM specific interface management, this group includes all \r
+ needed functions to use the specific TIM interface:\r
+ (++) Encoder Interface Configuration.\r
+ (++) Select Hall Sensor. \r
+ \r
+ (#) TIM specific remapping management includes the Remapping \r
+ configuration of specific timers\r
+ \r
+@endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_tim.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM \r
+ * @brief TIM driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ---------------------- TIM registers bit mask ------------------------ */\r
+#define SMCR_ETR_MASK ((uint16_t)0x00FF) \r
+#define CCMR_OFFSET ((uint16_t)0x0018)\r
+#define CCER_CCE_SET ((uint16_t)0x0001) \r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Group1 TimeBase management functions\r
+ * @brief TimeBase management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### TimeBase management functions #####\r
+ ===============================================================================\r
+ \r
+ *** TIM Driver: how to use it in Timing(Time base) Mode ***\r
+ ===============================================================================\r
+ [..] To use the Timer in Timing(Time base) mode, the following steps are \r
+ mandatory:\r
+ (#) Enable TIM clock using \r
+ RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.\r
+ (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.\r
+ (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure \r
+ the Time Base unit with the corresponding configuration.\r
+ (#) Enable the NVIC if you need to generate the update interrupt. \r
+ (#) Enable the corresponding interrupt using the function \r
+ TIM_ITConfig(TIMx, TIM_IT_Update). \r
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ [..]\r
+ (@) All other functions can be used seperatly to modify, if needed,\r
+ a specific feature of the Timer. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval None\r
+ * \r
+ */\r
+void TIM_DeInit(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ \r
+ if (TIMx == TIM2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
+ }\r
+ else if (TIMx == TIM3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
+ }\r
+ else if (TIMx == TIM4)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
+ } \r
+ else if (TIMx == TIM5)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);\r
+ } \r
+ else if (TIMx == TIM6)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
+ } \r
+ else if (TIMx == TIM7)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
+ } \r
+\r
+ else if (TIMx == TIM9)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);\r
+ } \r
+ else if (TIMx == TIM10)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (TIMx == TIM11)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
+ } \r
+ }\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Time Base Unit peripheral according to \r
+ * the specified parameters in the TIM_TimeBaseInitStruct.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure that contains the configuration information for\r
+ * the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
+\r
+ tmpcr1 = TIMx->CR1; \r
+\r
+ if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4) || ((TIMx) == TIM5))\r
+ { \r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
+ }\r
+ \r
+ if(((TIMx) != TIM6) && ((TIMx) != TIM7))\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
+ }\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
+ \r
+ /* Generate an update event to reload the Prescaler value immediatly */\r
+ TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;\r
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Prescaler.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Prescaler: specifies the Prescaler Register value.\r
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.\r
+ * @retval None\r
+ */\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Prescaler;\r
+ /* Set or reset the UG Bit */\r
+ TIMx->EGR = TIM_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Specifies the TIMx Counter Mode to be used.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_CounterMode: specifies the Counter Mode to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode.\r
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode.\r
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1.\r
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2.\r
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3.\r
+ * @retval None\r
+ */\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
+ \r
+ tmpcr1 = TIMx->CR1;\r
+ /* Reset the CMS and DIR Bits */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ /* Set the Counter Mode */\r
+ tmpcr1 |= TIM_CounterMode;\r
+ /* Write to TIMx CR1 register */\r
+ TIMx->CR1 = tmpcr1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Counter Register value\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Counter: specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Set the Counter Register value */\r
+ TIMx->CNT = Counter;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Autoreload Register value\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Autoreload: specifies the Autoreload register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Set the Autoreload Register value */\r
+ TIMx->ARR = Autoreload;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Counter value.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval Counter Register value.\r
+ */\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Get the Counter Register value */\r
+ return TIMx->CNT;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Prescaler value.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval Prescaler Register value.\r
+ */\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Get the Prescaler Register value */\r
+ return TIMx->PSC;\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TIMx Update event.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx UDIS bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the Update Disable Bit */\r
+ TIMx->CR1 |= TIM_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the Update Disable Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Update Request Interrupt source.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_UpdateSource: specifies the Update source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_UpdateSource_Global: Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller.\r
+ * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
+ \r
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
+ {\r
+ /* Set the URS Bit */\r
+ TIMx->CR1 |= TIM_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the URS Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx peripheral Preload register\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ARR Preload Bit */\r
+ TIMx->CR1 |= TIM_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the ARR Preload Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx's One Pulse Mode.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_OPMode: specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMode_Single:: TIM One Pulse Single Mode (Counter stops counting \r
+ * at the next update event (clearing the bit CEN)).\r
+ * @arg TIM_OPMode_Repetitive: TIM One Pulse Repetitive Mode \r
+ * (Counter is not stopped at update event).\r
+ * @retval None\r
+ */\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
+ \r
+ /* Reset the OPM Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
+ /* Configure the OPM Mode */\r
+ TIMx->CR1 |= TIM_OPMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Clock Division value.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_CKD: specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim.\r
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim.\r
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim.\r
+ * @retval None\r
+ */\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
+ \r
+ /* Reset the CKD Bits */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
+ /* Set the CKD value */\r
+ TIMx->CR1 |= TIM_CKD;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM peripheral.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
+ * @param NewState: new state of the TIMx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Counter */\r
+ TIMx->CR1 |= TIM_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Counter */\r
+ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group2 Output Compare management functions\r
+ * @brief Output Compare management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Output Compare management functions #####\r
+ ===============================================================================\r
+ *** TIM Driver: how to use it in Output Compare Mode ***\r
+ ===============================================================================\r
+ [..] To use the Timer in Output Compare mode, the following steps are mandatory:\r
+ (#) Enable TIM clock using \r
+ RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.\r
+ (#) Configure the TIM pins by configuring the corresponding GPIO pins\r
+ (#) Configure the Time base unit as described in the first part of this \r
+ driver, if needed, else the Timer will run with the default \r
+ configuration:\r
+ (++) Autoreload value = 0xFFFF.\r
+ (++) Prescaler value = 0x0000.\r
+ (++) Counter mode = Up counting.\r
+ (++) Clock Division = TIM_CKD_DIV1.\r
+ (#) Fill the TIM_OCInitStruct with the desired parameters including:\r
+ (++) The TIM Output Compare mode: TIM_OCMode.\r
+ (++) TIM Output State: TIM_OutputState.\r
+ (++) TIM Pulse value: TIM_Pulse.\r
+ (++) TIM Output Compare Polarity : TIM_OCPolarity.\r
+ (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired \r
+ channel with the corresponding configuration.\r
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ [..]\r
+ (@) All other functions can be used separately to modify, if needed,\r
+ a specific feature of the Timer.\r
+ (@) In case of PWM mode, this function is mandatory:\r
+ TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).\r
+ (@) If the corresponding interrupt or DMA request are needed, the user should:\r
+ (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).\r
+ (#@) Enable the corresponding interrupt (or DMA request) using the function\r
+ TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel1 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel2 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
+ \r
+ /* Get the TIMx CCER register value */ \r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel3 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel4 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+\r
+ /* Disable the Channel 2: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR2 */ \r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_OCInitStruct member with its default value.\r
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM Output Compare Mode.\r
+ * @note This function disables the selected channel before changing the Output\r
+ * Compare Mode.\r
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1.\r
+ * @arg TIM_Channel_2: TIM Channel 2.\r
+ * @arg TIM_Channel_3: TIM Channel 3.\r
+ * @arg TIM_Channel_4: TIM Channel 4.\r
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCMode_Timing: TIM Output Compare Timing mode.\r
+ * @arg TIM_OCMode_Active: TIM Output Compare Active mode.\r
+ * @arg TIM_OCMode_Inactive: TIM Output Compare Inactive mode.\r
+ * @arg TIM_OCMode_Toggle: TIM Output Compare Toggle mode.\r
+ * @arg TIM_OCMode_PWM1: TIM Output Compare PWM1 mode.\r
+ * @arg TIM_OCMode_PWM2: TIM Output Compare PWM2 mode.\r
+ * @arg TIM_ForcedAction_Active: TIM Forced Action Active mode.\r
+ * @arg TIM_ForcedAction_InActive: TIM Forced Action Inactive mode.\r
+ * @retval None\r
+ */\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint16_t tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OCM(TIM_OCMode));\r
+ \r
+ tmp = (uint32_t) TIMx;\r
+ tmp += CCMR_OFFSET;\r
+\r
+ tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;\r
+\r
+ /* Disable the Channel: Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp1;\r
+\r
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
+ {\r
+ tmp += (TIM_Channel>>1);\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= TIM_OCMode;\r
+ }\r
+ else\r
+ {\r
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare1 Register value\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param Compare1: specifies the Capture Compare1 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare1 Register value */\r
+ TIMx->CCR1 = Compare1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare2 Register value.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param Compare2: specifies the Capture Compare2 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare2 Register value */\r
+ TIMx->CCR2 = Compare2;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare3 Register value.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param Compare3: specifies the Capture Compare3 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare3 Register value */\r
+ TIMx->CCR3 = Compare3;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare4 Register value.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param Compare4: specifies the Capture Compare4 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare4 Register value */\r
+ TIMx->CCR4 = Compare4;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF.\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+ \r
+/**\r
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM \r
+ * peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF.\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF.\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF.\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable: Enable TIM output compare Preload\r
+ * @arg TIM_OCPreload_Disable: Disable TIM output compare Preload\r
+ * @retval None\r
+ */\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable: Enable TIM output compare Preload\r
+ * @arg TIM_OCPreload_Disable: Disable TIM output compare Preload\r
+ * @retval None\r
+ */\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable: Enable TIM output compare Preload\r
+ * @arg TIM_OCPreload_Disable: Disable TIM output compare Preload\r
+ * @retval None\r
+ */\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable: Enable TIM output compare Preload\r
+ * @arg TIM_OCPreload_Disable: Disable TIM output compare Preload\r
+ * @retval None\r
+ */\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 1 Fast feature.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable.\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable.\r
+ * @retval None\r
+ */\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 2 Fast feature.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable.\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable.\r
+ * @retval None\r
+ */\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 3 Fast feature.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable.\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable.\r
+ * @retval None\r
+ */\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 4 Fast feature.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable.\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable.\r
+ * @retval None\r
+ */\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF1 signal on an external event\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable.\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable.\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF2 signal on an external event\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable.\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable .\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF3 signal on an external event\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable.\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable.\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF4 signal on an external event\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable.\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable.\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 1 polarity.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC1 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high.\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low.\r
+ * @retval None\r
+ */\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
+ tmpccer |= TIM_OCPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 2 polarity.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC2 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high.\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low.\r
+ * @retval None\r
+ */\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 3 polarity.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC3 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high.\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low.\r
+ * @retval None\r
+ */\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 4 polarity.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC4 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high.\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low.\r
+ * @retval None\r
+ */\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC4P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Selects the OCReference Clear source.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_OCReferenceClear: specifies the OCReference Clear source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.\r
+ * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. \r
+ * @retval None\r
+ */\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));\r
+\r
+ /* Set the TIM_OCReferenceClear source */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);\r
+ TIMx->SMCR |= TIM_OCReferenceClear;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1.\r
+ * @arg TIM_Channel_2: TIM Channel 2.\r
+ * @arg TIM_Channel_3: TIM Channel 3.\r
+ * @arg TIM_Channel_4: TIM Channel 4.\r
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_CCX(TIM_CCx));\r
+\r
+ tmp = CCER_CCE_SET << TIM_Channel;\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t)~ tmp;\r
+\r
+ /* Set or reset the CCxE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group3 Input Capture management functions\r
+ * @brief Input Capture management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Input Capture management functions #####\r
+ ===============================================================================\r
+ \r
+ *** TIM Driver: how to use it in Input Capture Mode ***\r
+ ===============================================================================\r
+ [..] To use the Timer in Input Capture mode, the following steps are mandatory:\r
+ (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) \r
+ function.\r
+ (#) Configure the TIM pins by configuring the corresponding GPIO pins.\r
+ (#) Configure the Time base unit as described in the first part of this \r
+ driver, if needed, else the Timer will run with the default configuration:\r
+ (++) Autoreload value = 0xFFFF.\r
+ (++) Prescaler value = 0x0000.\r
+ (++) Counter mode = Up counting.\r
+ (++) Clock Division = TIM_CKD_DIV1.\r
+ (#) Fill the TIM_ICInitStruct with the desired parameters including:\r
+ (++) TIM Channel: TIM_Channel.\r
+ (++) TIM Input Capture polarity: TIM_ICPolarity.\r
+ (++) TIM Input Capture selection: TIM_ICSelection.\r
+ (++) TIM Input Capture Prescaler: TIM_ICPrescaler.\r
+ (++) TIM Input CApture filter value: TIM_ICFilter.\r
+ (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired \r
+ channel with the corresponding configuration and to measure only \r
+ frequency or duty cycle of the input signal,or, Call \r
+ TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired \r
+ channels with the corresponding configuration and to measure the \r
+ frequency and the duty cycle of the input signal.\r
+ (#) Enable the NVIC or the DMA to read the measured frequency.\r
+ (#) Enable the corresponding interrupt (or DMA request) to read \r
+ the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)\r
+ (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).\r
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ (#) Use TIM_GetCapturex(TIMx); to read the captured value.\r
+ [..]\r
+ (@) All other functions can be used separately to modify, if needed,\r
+ a specific feature of the Timer. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
+ \r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_ICInitStruct member with its default value.\r
+ * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Falling;\r
+ }\r
+ else\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Rising;\r
+ }\r
+ /* Select the Opposite Input */\r
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
+ {\r
+ icoppositeselection = TIM_ICSelection_IndirectTI;\r
+ }\r
+ else\r
+ {\r
+ icoppositeselection = TIM_ICSelection_DirectTI;\r
+ }\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ { \r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 1 value.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @retval Capture Compare 1 Register value.\r
+ */\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 1 Register value */\r
+ return TIMx->CCR1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 2 value.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @retval Capture Compare 2 Register value.\r
+ */\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 2 Register value */\r
+ return TIMx->CCR2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 3 value.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ \r
+ /* Get the Capture 3 Register value */\r
+ return TIMx->CCR3;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 4 value.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @retval Capture Compare 4 Register value.\r
+ */\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 4 Register value */\r
+ return TIMx->CCR4;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 1 prescaler.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler.\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events.\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events.\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events.\r
+ * @retval None\r
+ */\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
+ /* Set the IC1PSC value */\r
+ TIMx->CCMR1 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 2 prescaler.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler.\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events.\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events.\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events.\r
+ * @retval None\r
+ */\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC2PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
+ /* Set the IC2PSC value */\r
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 3 prescaler.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler.\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events.\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events.\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events.\r
+ * @retval None\r
+ */\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC3PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
+ /* Set the IC3PSC value */\r
+ TIMx->CCMR2 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 4 prescaler.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler.\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events.\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events.\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events.\r
+ * @retval None\r
+ */\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC4PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
+ /* Set the IC4PSC value */\r
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group4 Interrupts DMA and flags management functions\r
+ * @brief Interrupts, DMA and flags management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts, DMA and flags management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM interrupts.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source.\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source.\r
+ * @note TIM6 and TIM7 can only generate an update interrupt. \r
+ * @note TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11.\r
+ * @note TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9. \r
+ * @param NewState: new state of the TIM interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIMx->DIER |= TIM_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx event to be generate by software.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_EventSource: specifies the event source.\r
+ * This parameter can be one or more of the following values: \r
+ * @arg TIM_EventSource_Update: Timer update Event source.\r
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source.\r
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source.\r
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source.\r
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source.\r
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source.\r
+ * @note TIM6 and TIM7 can only generate an update event. \r
+ * @note TIM9 can only generate an update event, Capture Compare 1 event, \r
+ * Capture Compare 2 event and TIM_EventSource_Trigger. \r
+ * @note TIM10 and TIM11 can only generate an update event and Capture Compare 1 event. \r
+ * @retval None\r
+ */\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); \r
+ /* Set the event sources */\r
+ TIMx->EGR = TIM_EventSource;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM flag is set or not.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag.\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag.\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag.\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag.\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag.\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag.\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag.\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag.\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag.\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag.\r
+ *\r
+ * @note TIM6 and TIM7 can have only one update flag.\r
+ * @note TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,\r
+ * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags. \r
+ * @note TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags \r
+ * @retval The new state of TIM_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ ITStatus bitstatus = RESET; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
+ \r
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's pending flags.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag.\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag.\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag.\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag.\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag.\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag.\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag.\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag.\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag.\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag.\r
+ * @note TIM6 and TIM7 can have only one update flag. \r
+ * @note TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags\r
+ * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags. \r
+ * @note TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1\r
+ * or TIM_FLAG_CC1OF flags \r
+ * @retval None\r
+ */\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ TIMx->SR = (uint16_t)~TIM_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the TIM interrupt has occurred or not.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source.\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source.\r
+ *\r
+ * @note TIM6 and TIM7 can generate only an update interrupt.\r
+ * @note TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,\r
+ * interrupt and TIM_IT_Trigger interrupt.\r
+ * @note TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1\r
+ * interrupt \r
+ * @retval The new state of the TIM_IT(SET or RESET).\r
+ */\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ ITStatus bitstatus = RESET; \r
+ uint16_t itstatus = 0x0, itenable = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_IT(TIM_IT));\r
+ \r
+ itstatus = TIMx->SR & TIM_IT;\r
+ \r
+ itenable = TIMx->DIER & TIM_IT;\r
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's interrupt pending bits.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source.\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source.\r
+ * @note\r
+ * @note TIM6 and TIM7 can generate only an update interrupt.\r
+ * @note TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,\r
+ * and TIM_IT_Trigger interrupt. \r
+ * @note TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1\r
+ * interrupt \r
+ * @retval None\r
+ */\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ \r
+ /* Clear the IT pending Bit */\r
+ TIMx->SR = (uint16_t)~TIM_IT;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx's DMA interface.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_DMABase: DMA Base address.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABase_CR1: TIM CR1 register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CR2: TIM CR2 register as TIM DMA Base.\r
+ * @arg TIM_DMABase_SMCR: TIM SMCR register as TIM DMA Base.\r
+ * @arg TIM_DMABase_DIER: TIM DIER register as TIM DMA Base.\r
+ * @arg TIM_DMABase_SR: TIM SR register as TIM DMA Base.\r
+ * @arg TIM_DMABase_EGR: TIM EGR register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CCMR1: TIM CCMR1 register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CCMR2: TIM CCMR2 register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CCER: TIM CCER register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CNT: TIM CNT register as TIM DMA Base.\r
+ * @arg TIM_DMABase_PSC: TIM PSC register as TIM DMA Base.\r
+ * @arg TIM_DMABase_ARR: TIM ARR register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CCR1: TIM CCR1 register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CCR2: TIM CCR2 register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CCR3: TIM CCR3 register as TIM DMA Base.\r
+ * @arg TIM_DMABase_CCR4: TIM CCR4 register as TIM DMA Base.\r
+ * @arg TIM_DMABase_DCR: TIM DCR register as TIM DMA Base.\r
+ * @arg TIM_DMABase_OR: TIM OR register as TIM DMA Base.\r
+ * @param TIM_DMABurstLength: DMA Burst length.\r
+ * This parameter can be one value between:\r
+ * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.\r
+ * @retval None\r
+ */\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); \r
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
+ /* Set the DMA Base and the DMA Burst Length */\r
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx's DMA Requests.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 6 or 7 to select the TIM peripheral. \r
+ * @param TIM_DMASource: specifies the DMA Request sources.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_DMA_Update: TIM update Interrupt source.\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source.\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source.\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source.\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source.\r
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source.\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA sources */\r
+ TIMx->DIER |= TIM_DMASource; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param NewState: new state of the Capture Compare DMA source\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCDS Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCDS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCDS Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group5 Clocks management functions\r
+ * @brief Clocks management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Clocks management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIMx internal Clock\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Internal Trigger as External Clock\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_ITRSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @param TIM_TS_ITR0: Internal Trigger 0.\r
+ * @param TIM_TS_ITR1: Internal Trigger 1.\r
+ * @param TIM_TS_ITR2: Internal Trigger 2.\r
+ * @param TIM_TS_ITR3: Internal Trigger 3.\r
+ * @retval None\r
+ */\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+ /* Select the Internal Trigger */\r
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Trigger as External Clock\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_TIxExternalCLKSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector.\r
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1.\r
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2.\r
+ * @param TIM_ICPolarity: specifies the TIx Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising:\r
+ * @arg TIM_ICPolarity_Falling:\r
+ * @param ICFilter : specifies the filter value.\r
+ * This parameter must be a value between 0x0 and 0xF.\r
+ * @retval None\r
+ */\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_FILTER(ICFilter));\r
+ \r
+ /* Configure the Timer Input Clock Source */\r
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
+ {\r
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ /* Select the Trigger source */\r
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode1\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ /* Select the External clock mode1 */\r
+ tmpsmcr |= TIM_SlaveMode_External1;\r
+ /* Select the Trigger selection : ETRF */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ tmpsmcr |= TIM_TS_ETRF;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode2\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ /* Enable the External clock mode2 */\r
+ TIMx->SMCR |= TIM_SMCR_ECE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group6 Synchronization management functions\r
+ * @brief Synchronization management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Synchronization management functions #####\r
+ ===============================================================================\r
+ *** TIM Driver: how to use it in synchronization Mode ***\r
+ ===============================================================================\r
+ [..] Case of two/several Timers\r
+ (#) Configure the Master Timers using the following functions:\r
+ (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,\r
+ uint16_t TIM_TRGOSource).\r
+ (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,\r
+ uint16_t TIM_MasterSlaveMode); \r
+ (#) Configure the Slave Timers using the following functions: \r
+ (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, \r
+ uint16_t TIM_InputTriggerSource); \r
+ (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+ [..] Case of Timers and external trigger(ETR pin)\r
+ (#) Configure the Etrenal trigger using this function:\r
+ (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,\r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+ (#) Configure the Slave Timers using the following functions:\r
+ (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,\r
+ uint16_t TIM_InputTriggerSource);\r
+ (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx: where x can be 2, 3, 4, 5, or 9 to select the TIM peripheral.\r
+ * @param TIM_InputTriggerSource: The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0.\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1.\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2.\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3.\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector.\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1.\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2.\r
+ * @arg TIM_TS_ETRF: External Trigger input.\r
+ * @retval None\r
+ */\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= TIM_InputTriggerSource;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Trigger Output Mode.\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 6, 7 or 9 to select the TIM peripheral.\r
+ * @param TIM_TRGOSource: specifies the Trigger Output source.\r
+ * This paramter can be one of the following values:\r
+ *\r
+ * @param For all TIMx\r
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
+ *\r
+ * @param For all TIMx except TIM6 and TIM7\r
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
+ * is to be set, as soon as a capture or compare match occurs (TRGO).\r
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
+\r
+ * @param For all TIMx except TIM6, TIM7, TIM10 and TIM11\r
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
+\r
+ * @param For TIM2, TIM3 and TIM4\r
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
+ *\r
+ * @retval None\r
+ */\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
+\r
+ /* Reset the MMS Bits */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
+ /* Select the TRGO source */\r
+ TIMx->CR2 |= TIM_TRGOSource;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Slave Mode.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
+ * the counter and triggers an update of the registers.\r
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
+ * @retval None\r
+ */\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
+ \r
+ /* Reset the SMS Bits */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
+ /* Select the Slave Mode */\r
+ TIMx->SMCR |= TIM_SlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIMx Master/Slave Mode.\r
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.\r
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
+ * and its slaves (through TRGO).\r
+ * @arg TIM_MasterSlaveMode_Disable: No action\r
+ * @retval None\r
+ */\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
+ \r
+ /* Reset the MSM Bit */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
+ \r
+ /* Set or Reset the MSM Bit */\r
+ TIMx->SMCR |= TIM_MasterSlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= SMCR_ETR_MASK;\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group7 Specific interface management functions\r
+ * @brief Specific interface management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Specific interface management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIMx Encoder Interface.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
+ * on the level of the other input.\r
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity.\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @retval None\r
+ */\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ uint16_t tmpccmr1 = 0;\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ tmpsmcr |= TIM_EncoderMode;\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx's Hall sensor interface.\r
+ * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx Hall sensor interface.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the TI1S Bit */\r
+ TIMx->CR2 |= TIM_CR2_TI1S;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the TI1S Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group8 Specific remapping management function\r
+ * @brief Specific remapping management function\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Specific remapping management function #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIM2, TIM3, TIM9, TIM10 and TIM11 Remapping input \r
+ * Capabilities.\r
+ * @param TIMx: where x can be 2, 3, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Remap: specifies the TIM input remapping source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM2_TIM10_OC: TIM2 ITR1 is connected to TIM10 output compare(default).\r
+ * @arg TIM2_TIM5_TRGO: TIM2 ITR1 is connected to TIM5 Trigger output.\r
+ * @arg TIM3_TIM11_OC: TIM3 ITR2 is connected to TIM11 output compare(default).\r
+ * @arg TIM3_TIM5_TRGO: TIM3 ITR2 is connected to TIM5 Trigger output.\r
+ * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default).\r
+ * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.\r
+ * @arg TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO.\r
+ * @arg TIM9_TS_IO: TIM9 ITR1 is connected to Touch Sense IO.\r
+ * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default).\r
+ * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.\r
+ * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.\r
+ * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event.\r
+ * @arg TIM10_RI: TIM10 Channel 1 is connected to Routing Interface (RI). \r
+ * @arg TIM10_ETR_LSE: TIM10 ETR input is connected to LSE Clock.\r
+ * @arg TIM10_ETR_TIM9_TRGO: TIM10 ETR input is connected to TIM9 Trigger Output.\r
+ * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default). \r
+ * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.\r
+ * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.\r
+ * @arg TIM11_RI: TIM11 Channel 1 is connected to Routing Interface (RI). \r
+ * @arg TIM11_ETR_LSE: TIM11 ETR input is connected to LSE Clock.\r
+ * @arg TIM11_ETR_TIM9_TRGO: TIM11 ETR input is connected to TIM9 Trigger Output.\r
+ * @retval None\r
+ */\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_REMAP(TIM_Remap));\r
+\r
+ /* Set the Timer remapping configuration */\r
+ TIMx->OR &= (uint16_t)(TIM_Remap >> 16);\r
+ TIMx->OR |= (uint16_t)TIM_Remap;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0;\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 4);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 8);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 12);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
+\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_usart.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Universal synchronous asynchronous receiver\r
+ * transmitter (USART): \r
+ * + Initialization and Configuration\r
+ * + Data transfers\r
+ * + Multi-Processor Communication\r
+ * + LIN mode\r
+ * + Half-duplex mode\r
+ * + Smartcard mode\r
+ * + IrDA mode\r
+ * + DMA transfers management\r
+ * + Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (#) Enable peripheral clock using\r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) function for\r
+ USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)\r
+ function for USART2 and USART3.\r
+ (#) According to the USART mode, enable the GPIO clocks using\r
+ RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,\r
+ or and SCLK).\r
+ (#) Peripheral's alternate function:\r
+ (++) Connect the pin to the desired peripherals' Alternate\r
+ Function (AF) using GPIO_PinAFConfig() function.\r
+ (++) Configure the desired pin in alternate function by:\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
+ (++) Select the type, pull-up/pull-down and output speed via\r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
+ (++) Call GPIO_Init() function.\r
+ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware\r
+ flow control and Mode(Receiver/Transmitter) using the SPI_Init()\r
+ function.\r
+ (#) For synchronous mode, enable the clock and program the polarity,\r
+ phase and last bit using the USART_ClockInit() function.\r
+ (#) Enable the NVIC and the corresponding interrupt using the function\r
+ USART_ITConfig() if you need to use interrupt mode.\r
+ (#) When using the DMA mode.\r
+ (++) Configure the DMA using DMA_Init() function.\r
+ (++) Active the needed channel Request using USART_DMACmd() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.\r
+ [..]\r
+ Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections\r
+ for more details.\r
+ \r
+@endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_usart.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART \r
+ * @brief USART driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */\r
+#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \\r
+ USART_CR1_PS | USART_CR1_TE | \\r
+ USART_CR1_RE))\r
+\r
+/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */\r
+#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \\r
+ USART_CR2_CPHA | USART_CR2_LBCL))\r
+\r
+/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */\r
+#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
+\r
+/*!< USART Interrupts mask */\r
+#define IT_MASK ((uint16_t)0x001F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USART \r
+ in asynchronous and in synchronous modes.\r
+ (+) For the asynchronous mode only these parameters can be configured: \r
+ (+) Baud Rate.\r
+ (+) Word Length.\r
+ (+) Stop Bit.\r
+ (+) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ the possible USART frame formats are as listed in the following table:\r
+ [..]\r
+ +-------------------------------------------------------------+\r
+ | M bit | PCE bit | USART frame |\r
+ |---------------------|---------------------------------------|\r
+ | 0 | 0 | | SB | 8 bit data | STB | |\r
+ |---------|-----------|---------------------------------------|\r
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
+ |---------|-----------|---------------------------------------|\r
+ | 1 | 0 | | SB | 9 bit data | STB | |\r
+ |---------|-----------|---------------------------------------|\r
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
+ +-------------------------------------------------------------+\r
+ [..]\r
+ (+) Hardware flow control.\r
+ (+) Receiver/transmitter modes.\r
+ [..] The USART_Init() function follows the USART asynchronous configuration \r
+ procedure(details for the procedure are available in reference manual \r
+ (RM0038)).\r
+ (+) For the synchronous mode in addition to the asynchronous mode parameters\r
+ these parameters should be also configured:\r
+ (++) USART Clock Enabled.\r
+ (++) USART polarity.\r
+ (++) USART phase.\r
+ (++) USART LastBit.\r
+ [..] These parameters can be configured using the USART_ClockInit() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values: USART1, USART2, USART3, \r
+ * UART4 or UART5.\r
+ * @retval None.\r
+ */\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+ if (USARTx == USART1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+ }\r
+ else if (USARTx == USART2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+ }\r
+ else if (USARTx == USART3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r
+ } \r
+ else if (USARTx == UART4)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (USARTx == UART5)\r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);\r
+ }\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral according to the specified\r
+ * parameters in the USART_InitStruct.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values: USART1, USART2, USART3, \r
+ * UART4 or UART5.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that \r
+ * contains the configuration information for the specified USART peripheral.\r
+ * @retval None.\r
+ */\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00, apbclock = 0x00;\r
+ uint32_t integerdivider = 0x00;\r
+ uint32_t fractionaldivider = 0x00;\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+\r
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */\r
+ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ }\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear STOP[13:12] bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);\r
+\r
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set STOP[13:12] bits according to USART_StopBits value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
+ \r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR1;\r
+ /* Clear M, PCE, PS, TE and RE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);\r
+\r
+ /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+ /* Set the M bits according to USART_WordLength value */\r
+ /* Set PCE and PS bits according to USART_Parity value */\r
+ /* Set TE and RE bits according to USART_Mode value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+ USART_InitStruct->USART_Mode;\r
+\r
+ /* Write to USART CR1 */\r
+ USARTx->CR1 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/ \r
+ tmpreg = USARTx->CR3;\r
+ /* Clear CTSE and RTSE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);\r
+\r
+ /* Configure the USART HFC -------------------------------------------------*/\r
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+\r
+ /* Write to USART CR3 */\r
+ USARTx->CR3 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+ /* Configure the USART Baud Rate -------------------------------------------*/\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ if (USARTx == USART1) \r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
+ }\r
+ else\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
+ }\r
+\r
+ /* Determine the integer part */\r
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 8 Samples */\r
+ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 16 Samples */\r
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ tmpreg = (integerdivider / 100) << 4;\r
+\r
+ /* Determine the fractional part */\r
+ fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
+\r
+ /* Implement the fractional part in the register */\r
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
+ }\r
+ \r
+ /* Write to USART BRR */\r
+ USARTx->BRR = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_InitStruct member with its default value.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ /* USART_InitStruct members default value */\r
+ USART_InitStruct->USART_BaudRate = 9600;\r
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+ USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral Clock according to the \r
+ * specified parameters in the USART_ClockInitStruct.\r
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure that contains the configuration information for the specified \r
+ * USART peripheral.\r
+ * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.\r
+ * @retval None.\r
+ */\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);\r
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set CLKEN bit according to USART_Clock value */\r
+ /* Set CPOL bit according to USART_CPOL value */\r
+ /* Set CPHA bit according to USART_CPHA value */\r
+ /* Set LBCL bit according to USART_LastBit value */\r
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_ClockInitStruct member with its default value.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ /* USART_ClockInitStruct members default value */\r
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USARTx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART by setting the UE bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_UE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the system clock prescaler.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_Prescaler: specifies the prescaler clock. \r
+ * @note The function is used for IrDA mode with UART4 and UART5. \r
+ * @retval None.\r
+ */\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART prescaler */\r
+ USARTx->GTPR &= USART_GTPR_GT;\r
+ /* Set the USART prescaler */\r
+ USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's 8x oversampling mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART 8x oversampling mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ *\r
+ * @note\r
+ * This function has to be called before calling USART_Init()\r
+ * function in order to have correct baudrate Divider value.\r
+ * @retval None\r
+ */\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_OVER8;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the USART's one bit sampling method.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART one bit sampling method.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_ONEBIT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group2 Data transfers functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Data transfers functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage \r
+ the USART data transfers.\r
+ [..] During an USART reception, data shifts in least significant bit first \r
+ through the RX pin. In this mode, the USART_DR register consists of \r
+ a buffer (RDR) between the internal bus and the received shift register.\r
+ When a transmission is taking place, a write instruction to \r
+ the USART_DR register stores the data in the TDR register and which is \r
+ copied in the shift register at the end of the current transmission.\r
+ [..] The read access of the USART_DR register can be done using \r
+ the USART_ReceiveData() function and returns the RDR buffered value.\r
+ Whereas a write access to the USART_DR can be done using USART_SendData()\r
+ function and stores the written data into TDR buffer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits single data through the USARTx peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param Data: the data to transmit.\r
+ * @retval None.\r
+ */\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DATA(Data)); \r
+ \r
+ /* Transmit Data */\r
+ USARTx->DR = (Data & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the USARTx peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @retval The received data.\r
+ */\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Receive Data */\r
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group3 MultiProcessor Communication functions\r
+ * @brief Multi-Processor Communication functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Multi-Processor Communication functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART \r
+ multiprocessor communication.\r
+ [..] For instance one of the USARTs can be the master, its TX output is\r
+ connected to the RX input of the other USART. The others are slaves,\r
+ their respective TX outputs are logically ANDed together and connected \r
+ to the RX input of the master. USART multiprocessor communication is \r
+ possible through the following procedure:\r
+ (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values \r
+ using the USART_Init() function.\r
+ (#) Configures the USART address using the USART_SetAddress() function.\r
+ (#) Configures the wake up methode (USART_WakeUp_IdleLine or \r
+ USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only \r
+ for the slaves.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() \r
+ function.\r
+\r
+ [..] The USART Slave exit from mute mode when receive the wake up condition.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the address of the USART node.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_Address: Indicates the address of the USART node.\r
+ * @retval None\r
+ */\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_ADDRESS(USART_Address)); \r
+ \r
+ /* Clear the USART address */\r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);\r
+ /* Set the USART address node */\r
+ USARTx->CR2 |= USART_Address;\r
+}\r
+\r
+/**\r
+ * @brief Determines if the USART is in mute mode or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART mute mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_RWU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);\r
+ }\r
+}\r
+/**\r
+ * @brief Selects the USART WakeUp method.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_WakeUp: specifies the USART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection.\r
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark.\r
+ * @retval None.\r
+ */\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
+ \r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);\r
+ USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group4 LIN mode functions\r
+ * @brief LIN mode functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### LIN mode functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART \r
+ LIN Mode communication.\r
+ [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance \r
+ with the LIN standard.\r
+ [..] Only this LIN Feature is supported by the USART IP:\r
+ (+) LIN Master Synchronous Break send capability and LIN slave break \r
+ detection capability : 13-bit break generation and 10/11 bit break \r
+ detection.\r
+ [..] USART LIN Master transmitter communication is possible through the \r
+ following procedure:\r
+ (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values \r
+ using the USART_Init() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Enable the LIN mode using the USART_LINCmd() function.\r
+ (#) Send the break character using USART_SendBreak() function.\r
+ [..] USART LIN Master receiver communication is possible through the \r
+ following procedure:\r
+ (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values \r
+ using the USART_Init() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Configures the break detection length \r
+ using the USART_LINBreakDetectLengthConfig() function.\r
+ (#) Enable the LIN mode using the USART_LINCmd() function.\r
+ -@- In LIN mode, the following bits must be kept cleared:\r
+ (+@) CLKEN in the USART_CR2 register.\r
+ (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the USART LIN Break detection length.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection.\r
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection.\r
+ * @retval None.\r
+ */\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+ \r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);\r
+ USARTx->CR2 |= USART_LINBreakDetectLength; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's LIN mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART LIN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ USARTx->CR2 |= USART_CR2_LINEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @retval None.\r
+ */\r
+void USART_SendBreak(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Send break characters */\r
+ USARTx->CR1 |= USART_CR1_SBK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group5 Halfduplex mode function\r
+ * @brief Half-duplex mode function \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Half-duplex mode function #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART\r
+ Half-duplex communication.\r
+ [..] The USART can be configured to follow a single-wire half-duplex protocol \r
+ where the TX and RX lines are internally connected.\r
+ [..] USART Half duplex communication is possible through the following procedure:\r
+ (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter \r
+ or Mode receiver and hardware flow control values using the USART_Init()\r
+ function.\r
+ (#) Configures the USART address using the USART_SetAddress() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.\r
+ -@- The RX pin is no longer used.\r
+ -@- In Half-duplex mode the following bits must be kept cleared:\r
+ (+@) LINEN and CLKEN bits in the USART_CR2 register.\r
+ (+@) SCEN and IREN bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the USART's Half Duplex communication.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART Communication.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_HDSEL;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup USART_Group6 Smartcard mode functions\r
+ * @brief Smartcard mode functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Smartcard mode functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART \r
+ Smartcard communication.\r
+ [..] The Smartcard interface is designed to support asynchronous protocol \r
+ Smartcards as defined in the ISO 7816-3 standard. The USART can provide \r
+ a clock to the smartcard through the SCLK output. In smartcard mode, \r
+ SCLK is not associated to the communication but is simply derived from \r
+ the internal peripheral input clock through a 5-bit prescaler.\r
+ [..] Smartcard communication is possible through the following procedure:\r
+ (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() \r
+ function.\r
+ (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() \r
+ function.\r
+ (#) Program the USART clock using the USART_ClockInit() function as following:\r
+ (++) USART Clock enabled.\r
+ (++) USART CPOL Low.\r
+ (++) USART CPHA on first edge.\r
+ (++) USART Last Bit Clock Enabled.\r
+ (#) Program the Smartcard interface using the USART_Init() function as \r
+ following:\r
+ (++) Word Length = 9 Bits.\r
+ (++) 1.5 Stop Bit.\r
+ (++) Even parity.\r
+ (++) BaudRate = 12096 baud.\r
+ (++) Hardware flow control disabled (RTS and CTS signals).\r
+ (++) Tx and Rx enabled\r
+ (#) Optionally you can enable the parity error interrupt using \r
+ the USART_ITConfig() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.\r
+ (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.\r
+ [..] \r
+ Please refer to the ISO 7816-3 specification for more details.\r
+ [..] \r
+ (@) It is also possible to choose 0.5 stop bit for receiving but it is \r
+ recommended to use 1.5 stop bits for both transmitting and receiving \r
+ to avoid switching between the two configurations.\r
+ (@) In smartcard mode, the following bits must be kept cleared:\r
+ (+@) LINEN bit in the USART_CR2 register.\r
+ (+@) HDSEL and IREN bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the specified USART guard time.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_GuardTime: specifies the guard time. \r
+ * @retval None.\r
+ */\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART Guard time */\r
+ USARTx->GTPR &= USART_GTPR_PSC;\r
+ /* Set the USART guard time */\r
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's Smart Card mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_SCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables NACK transmission.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the NACK transmission.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None.\r
+ */\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_NACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group7 IrDA mode functions\r
+ * @brief IrDA mode functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IrDA mode functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART \r
+ IrDA communication.\r
+ [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, \r
+ any data on the IrDA receive line will be ignored by the IrDA decoder \r
+ and if the Receiver is busy, data on the TX from the USART to IrDA will \r
+ not be encoded by IrDA. While receiving data, transmission should be \r
+ avoided as the data to be transmitted could be corrupted.\r
+\r
+ [..] IrDA communication is possible through the following procedure:\r
+ (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, \r
+ Transmitter/Receiver modes and hardware flow control values using \r
+ the USART_Init() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Configures the IrDA pulse width by configuring the prescaler using \r
+ the USART_SetPrescaler() function.\r
+ (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal \r
+ mode using the USART_IrDAConfig() function.\r
+ (#) Enable the IrDA using the USART_IrDACmd() function.\r
+\r
+ [..]\r
+ (@) A pulse of width less than two and greater than one PSC period(s) may or \r
+ may not be rejected.\r
+ (@) The receiver set up time should be managed by software. The IrDA physical \r
+ layer specification specifies a minimum of 10 ms delay between \r
+ transmission and reception (IrDA is a half duplex protocol).\r
+ (@) In IrDA mode, the following bits must be kept cleared:\r
+ (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.\r
+ (+@) SCEN and HDSEL bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the USART's IrDA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IrDAMode: specifies the IrDA mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IrDAMode_LowPower: USART IrDA Low Power mode selected.\r
+ * @arg USART_IrDAMode_Normal: USART IrDA Normal mode selected.\r
+ * @retval None\r
+ */\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+ \r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);\r
+ USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's IrDA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the IrDA mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_IREN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group8 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DMA transfers management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the USART's DMA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_DMAReq: specifies the DMA request.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_DMAReq_Tx: USART DMA transmit request.\r
+ * @arg USART_DMAReq_Rx: USART DMA receive request.\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 |= USART_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup USART_Group9 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to configure the \r
+ USART Interrupts sources, DMA channels requests and check or clear the \r
+ flags or pending bits status. The user should identify which mode will \r
+ be used in his application to manage the communication: Polling mode, \r
+ Interrupt mode or DMA mode.\r
+ *** Polling Mode ***\r
+ ====================\r
+ [..] In Polling Mode, the SPI communication can be managed by 10 flags:\r
+ (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.\r
+ (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.\r
+ (#) USART_FLAG_TC: to indicate the status of the transmit operation.\r
+ (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.\r
+ (#) USART_FLAG_CTS: to indicate the status of the nCTS input.\r
+ (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.\r
+ (#) USART_FLAG_NE: to indicate if a noise error occur.\r
+ (#) USART_FLAG_FE: to indicate if a frame error occur.\r
+ (#) USART_FLAG_PE: to indicate if a parity error occur.\r
+ (#) USART_FLAG_ORE: to indicate if an Overrun error occur.\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).\r
+ (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).\r
+ \r
+ *** Interrupt Mode ***\r
+ ======================\r
+ [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt \r
+ sources and 10 pending bits:\r
+ (+) Pending Bits:\r
+ (##) USART_IT_TXE: to indicate the status of the transmit buffer \r
+ register.\r
+ (##) USART_IT_RXNE: to indicate the status of the receive buffer \r
+ register.\r
+ (##) USART_IT_TC: to indicate the status of the transmit operation.\r
+ (##) USART_IT_IDLE: to indicate the status of the Idle Line.\r
+ (##) USART_IT_CTS: to indicate the status of the nCTS input.\r
+ (##) USART_IT_LBD: to indicate the status of the LIN break detection.\r
+ (##) USART_IT_NE: to indicate if a noise error occur.\r
+ (##) USART_IT_FE: to indicate if a frame error occur.\r
+ (##) USART_IT_PE: to indicate if a parity error occur.\r
+ (##) USART_IT_ORE: to indicate if an Overrun error occur\r
+ (if the RXNEIE or EIE bits are set).\r
+\r
+ (+) Interrupt Source:\r
+ (##) USART_IT_TXE: specifies the interrupt source for the Tx buffer \r
+ empty interrupt. \r
+ (##) USART_IT_RXNE: specifies the interrupt source for the Rx buffer \r
+ not empty interrupt.\r
+ (##) USART_IT_TC: specifies the interrupt source for the Transmit \r
+ complete interrupt. \r
+ (##) USART_IT_IDLE: specifies the interrupt source for the Idle Line \r
+ interrupt.\r
+ (##) USART_IT_CTS: specifies the interrupt source for the CTS interrupt. \r
+ (##) USART_IT_LBD: specifies the interrupt source for the LIN break \r
+ detection interrupt. \r
+ (##) USART_IT_PE: specifies the interrupt source for theparity error \r
+ interrupt. \r
+ (##) USART_IT_ERR: specifies the interrupt source for the errors \r
+ interrupt.\r
+ -@@- Some parameters are coded in order to use them as interrupt \r
+ source or as pending bits.\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, \r
+ FunctionalState NewState).\r
+ (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).\r
+ (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).\r
+ \r
+ *** DMA Mode ***\r
+ ================\r
+ [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel \r
+ requests:\r
+ (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.\r
+ (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.\r
+ [..] In this Mode it is advised to use the following function:\r
+ (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, \r
+ FunctionalState NewState).\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART interrupts.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt.\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt.\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.\r
+ * @arg USART_IT_TC: Transmission complete interrupt.\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt.\r
+ * @arg USART_IT_PE: Parity Error interrupt.\r
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error).\r
+ * @param NewState: new state of the specified USARTx interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
+{\r
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
+ uint32_t usartxbase = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CONFIG_IT(USART_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* The CTS interrupt is not available for UART4 and UART5 */\r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ usartxbase = (uint32_t)USARTx;\r
+\r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itpos = USART_IT & IT_MASK;\r
+ itmask = (((uint32_t)0x01) << itpos);\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ usartxbase += 0x0C;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ usartxbase += 0x10;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ usartxbase += 0x14; \r
+ }\r
+ if (NewState != DISABLE)\r
+ {\r
+ *(__IO uint32_t*)usartxbase |= itmask;\r
+ }\r
+ else\r
+ {\r
+ *(__IO uint32_t*)usartxbase &= ~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART flag is set or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg USART_FLAG_TXE: Transmit data register empty flag.\r
+ * @arg USART_FLAG_TC: Transmission Complete flag.\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
+ * @arg USART_FLAG_IDLE: Idle Line detection flag.\r
+ * @arg USART_FLAG_ORE: OverRun Error flag.\r
+ * @arg USART_FLAG_NE: Noise Error flag.\r
+ * @arg USART_FLAG_FE: Framing Error flag.\r
+ * @arg USART_FLAG_PE: Parity Error flag.\r
+ * @retval The new state of USART_FLAG (SET or RESET).\r
+ */\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_FLAG(USART_FLAG));\r
+\r
+ /* The CTS flag is not available for UART4 and UART5 */\r
+ if (USART_FLAG == USART_FLAG_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx's pending flags.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg USART_FLAG_TC: Transmission Complete flag.\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
+ * \r
+ *\r
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) flags are cleared by software \r
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
+ * @note RXNE flag can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * @note TC flag can be also cleared by software sequence: a read operation to \r
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
+ * to USART_DR register (USART_SendData()).\r
+ * @note TXE flag is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+\r
+ /* The CTS flag is not available for UART4 and UART5 */\r
+ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ USARTx->SR = (uint16_t)~USART_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART interrupt has occurred or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_ORE_RX: OverRun Error interrupt if the RXNEIE bit is set.\r
+ * @arg USART_IT_ORE_ER: OverRun Error interrupt if the EIE bit is set. \r
+ * @arg USART_IT_NE: Noise Error interrupt\r
+ * @arg USART_IT_FE: Framing Error interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of USART_IT (SET or RESET).\r
+ */\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_GET_IT(USART_IT)); \r
+\r
+ /* The CTS interrupt is not available for UART4 and UART5 */ \r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+ /* Get the interrupt position */\r
+ itmask = USART_IT & IT_MASK;\r
+ itmask = (uint32_t)0x01 << itmask;\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ itmask &= USARTx->CR1;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ itmask &= USARTx->CR2;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ itmask &= USARTx->CR3;\r
+ }\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ bitpos = (uint32_t)0x01 << bitpos;\r
+ bitpos &= USARTx->SR;\r
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx's interrupt pending bits.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt. \r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+ * \r
+\r
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) pending bits are cleared by \r
+ * software sequence: a read operation to USART_SR register \r
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * @note RXNE pending bit can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * @note TC pending bit can be also cleared by software sequence: a read \r
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
+ * operation to USART_DR register (USART_SendData()).\r
+ * @note TXE pending bit is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint16_t bitpos = 0x00, itmask = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_IT(USART_IT)); \r
+\r
+ /* The CTS interrupt is not available for UART4 and UART5 */\r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
+ USARTx->SR = (uint16_t)~itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.1\r
+ * @date 05-March-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Window watchdog (WWDG) peripheral: \r
+ * + Prescaler, Refresh window and Counter configuration\r
+ * + WWDG activation\r
+ * + Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ * \r
+ ============================================================================== \r
+ ##### WWDG features ##### \r
+ ============================================================================== \r
+ [..] Once enabled the WWDG generates a system reset on expiry of a programmed\r
+ time period, unless the program refreshes the counter (downcounter) \r
+ before to reach 0x3F value (i.e. a reset is generated when the counter\r
+ value rolls over from 0x40 to 0x3F). \r
+ [..] An MCU reset is also generated if the counter value is refreshed\r
+ before the counter has reached the refresh window value. This \r
+ implies that the counter must be refreshed in a limited window.\r
+\r
+ [..] Once enabled the WWDG cannot be disabled except by a system reset.\r
+\r
+ [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG\r
+ reset occurs.\r
+\r
+ [..] The WWDG counter input clock is derived from the APB clock divided \r
+ by a programmable prescaler.\r
+\r
+ [..] WWDG counter clock = PCLK1 / Prescaler.\r
+ [..] WWDG timeout = (WWDG counter clock) * (counter value).\r
+\r
+ [..] Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms.\r
+\r
+ ##### How to use this driver ##### \r
+ ==============================================================================\r
+ [..]\r
+ (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) \r
+ function.\r
+ \r
+ (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.\r
+ \r
+ (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.\r
+ \r
+ (#) Set the WWDG counter value and start it using WWDG_Enable() function.\r
+ When the WWDG is enabled the counter value should be configured to \r
+ a value greater than 0x40 to prevent generating an immediate reset.\r
+ \r
+ (#) Optionally you can enable the Early wakeup interrupt which is \r
+ generated when the counter reach 0x40.\r
+ Once enabled this interrupt cannot be disabled except by a system reset.\r
+ \r
+ (#) Then the application program must refresh the WWDG counter at regular\r
+ intervals during normal operation to prevent an MCU reset, using\r
+ WWDG_SetCounter() function. This operation must occur only when\r
+ the counter value is lower than the refresh window value, \r
+ programmed using WWDG_SetWindowValue().\r
+ \r
+ * @endverbatim \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_wwdg.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG \r
+ * @brief WWDG driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ----------- WWDG registers bit address in the alias region ----------- */\r
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
+\r
+/* Alias word address of EWI bit */\r
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
+#define EWI_BitNumber 0x09\r
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
+\r
+/* --------------------- WWDG registers bit mask ------------------------ */\r
+\r
+/* CFR register bit mask */\r
+#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)\r
+#define CFR_W_MASK ((uint32_t)0xFFFFFF80)\r
+#define BIT_MASK ((uint8_t)0x7F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions\r
+ * @brief Prescaler, Refresh window and Counter configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Prescaler, Refresh window and Counter configuration functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG Prescaler.\r
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
+ * @retval None\r
+ */\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
+ /* Clear WDGTB[1:0] bits */\r
+ tmpreg = WWDG->CFR & CFR_WDGTB_MASK;\r
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
+ tmpreg |= WWDG_Prescaler;\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG window value.\r
+ * @param WindowValue: specifies the window value to be compared to the downcounter.\r
+ * This parameter value must be lower than 0x80.\r
+ * @retval None\r
+ */\r
+void WWDG_SetWindowValue(uint8_t WindowValue)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
+ /* Clear W[6:0] bits */\r
+\r
+ tmpreg = WWDG->CFR & CFR_W_MASK;\r
+\r
+ /* Set W[6:0] bits according to WindowValue value */\r
+ tmpreg |= WindowValue & (uint32_t) BIT_MASK;\r
+\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
+ * @note Once enabled this interrupt cannot be disabled except by a system reset. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_EnableIT(void)\r
+{\r
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG counter value.\r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
+ * an immediate reset).\r
+ * @retval None\r
+ */\r
+void WWDG_SetCounter(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ /* Write to T[6:0] bits to configure the counter value, no need to do\r
+ a read-modify-write; writing a 0 to WDGA bit does nothing */\r
+ WWDG->CR = Counter & BIT_MASK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Group2 WWDG activation functions\r
+ * @brief WWDG activation functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### WWDG activation function #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables WWDG and load the counter value. \r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
+ * an immediate reset).\r
+ * @retval None\r
+ */\r
+void WWDG_Enable(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ WWDG->CR = WWDG_CR_WDGA | Counter;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).\r
+ */\r
+FlagStatus WWDG_GetFlagStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ if ((WWDG->SR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears Early Wakeup interrupt flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_ClearFlag(void)\r
+{\r
+ WWDG->SR = (uint32_t)RESET;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+<html>\r
+<head>\r
+<style>\r
+<!--\r
+/* Style Definitions */\r
+p.MsoNormal, li.MsoNormal, div.MsoNormal\r
+{margin-top:0cm;margin-right:0cm;margin-bottom:8pt;margin-left:0cm;line-height:normal;font-size:10.0pt;font-family:Verdana,sans-serif;}\r
+p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph\r
+{margin-top:0cm;margin-right:0cm;margin-bottom:2pt;margin-left:0cm;line-height:normal;font-size:10.0pt;font-family:Verdana,sans-serif;}\r
+-->\r
+</style>\r
+<title>\r
+STMTouch Driver Release Notes\r
+</title>\r
+</head>\r
+<body lang=EN-US>\r
+<p class=MsoNormal align=center style='text-align:center;line-height:normal'><b><span style='font-size:18.0pt;color: rgb(51, 102, 255)'>\r
+Release Notes for\r
+</span></b></p>\r
+<p class=MsoNormal align=center style='text-align:center;line-height:normal'><b><span style='font-size:18.0pt;color: rgb(51, 102, 255)'>\r
+STMTouch Driver\r
+</span></b></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal align=center style='line-height:center;line-height:normal'><span style='font-size:10.0pt'>\r
+Copyright © 2013 STMicroelectronics\r
+</span></p>\r
+<p class=MsoNormal align=center style='line-height:center;line-height:normal'><span style='font-size:10.0pt'>\r
+Microcontrollers Division - Application Team\r
+</span></p>\r
+<p class=MsoNormal align=center> <img id=_rnc_img0 src=../../_htmresc/st_logo.png border=0> </span></p>\r
+<p class=MsoNormal align=center> <img id=_rnc_img1 src=../../_htmresc/stmtouch.bmp border=0> </span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;margin-right:4cm;width:80%;background:rgb(51, 102, 255)'>\r
+<td style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-left:0cm;margin-bottom:0cm;line-height:normal'><b><span style='font-size:12.0pt;color:white'>\r
+Update History</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>\r
+<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>\r
+V1.3.2 / 22-January-2013</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Main Changes\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Change in STM32L1xx acquisition: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ GPIOs speed configured to "Very Low" (400 kHz). \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Content\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM8TL5xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F0xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F3xx devices (ALPHA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx High-density devices using hardware and software acquisition modes (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density Plus devices using hardware and software acquisition modes (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density devices using sofware acquisition mode (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of proximity, touchkey and linear/rotary touch sensors. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Debounce mechanism for all states. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Environment Change System (ECS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Exclusion System (DXS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Time Out (DTO). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Noise filtering capability on measurement and delta. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Development Toolchains and Compilers\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM8 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ ST Visual Develop (STVD). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Cosmic STM8 C Compiler. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM32 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Keil MDK-ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Altium Tasking. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Atollic TrueSTUDIO. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-Arm. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Known Limitations\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+None. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>\r
+<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>\r
+V1.3.1 / 15-January-2013</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Main Changes\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Improvement of STM32L1xx acquisition. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Typo corrections. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Content\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM8TL5xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F0xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F3xx devices (ALPHA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx High-density devices using hardware and software acquisition modes (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density Plus devices using hardware and software acquisition modes (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density devices using sofware acquisition mode (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of proximity, touchkey and linear/rotary touch sensors. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Debounce mechanism for all states. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Environment Change System (ECS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Exclusion System (DXS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Time Out (DTO). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Noise filtering capability on measurement and delta. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Development Toolchains and Compilers\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM8 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ ST Visual Develop (STVD). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Cosmic STM8 C Compiler. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM32 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Keil MDK-ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Altium Tasking. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Atollic TrueSTUDIO. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-Arm. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Known Limitations\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+None. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>\r
+<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>\r
+V1.3.0 / 10-December-2012</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Main Changes\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Add support of STM32F30x and STM32F37x devices. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Content\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM8TL5xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F0xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F3xx devices (ALPHA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx High-density devices using hardware and software acquisition modes (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density Plus devices using hardware and software acquisition modes (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density devices using sofware acquisition mode (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of proximity, touchkey and linear/rotary touch sensors. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Debounce mechanism for all states. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Environment Change System (ECS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Exclusion System (DXS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Time Out (DTO). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Noise filtering capability on measurement and delta. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Development Toolchains and Compilers\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM8 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ ST Visual Develop (STVD). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Cosmic STM8 C Compiler. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM32 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Keil MDK-ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Altium Tasking. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Atollic TrueSTUDIO. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-Arm. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Known Limitations\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+None. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>\r
+<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>\r
+V1.2.0 / 30-November-2012</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Main Changes\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Common. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Change LinRot sensors position offset tables names (Mono, Half-ended, Dual). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Add more LinRot sensors position offset tables with conditional compilation. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM8TL5x acquisition. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Increase TSLPRM_KEY_TARGET_REFERENCE max value to 2000. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM32F0xx acquisition. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Improvement of capacitors discharge processing. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Add automatic GPIO configuration. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM32L1xx acquisition. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Add support of Medium-density Plus devices. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Rename files ("hw/sw" put after "stm32l1xx"). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Software acquisition is now done if TSLPRM_STM32L1XX_SW_ACQ is defined (was previously TSLPRM_STM32L1XX_HD_SW or TSLPRM_STM32L1XX_MDP_SW). \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Content\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM8TL5xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F0xx devices (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx High-density devices using hardware and software acquisition modes (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density Plus devices using hardware and software acquisition modes (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density devices using sofware acquisition mode (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of proximity, touchkey and linear/rotary touch sensors (1, 3, 5 and 6 channels). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Debounce mechanism for all states. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Environment Change System (ECS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Exclusion System (DXS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Time Out (DTO). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Noise filtering capability on measurement and delta. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Development Toolchains and Compilers\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM8 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ ST Visual Develop (STVD). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Cosmic STM8 C Compiler. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM32 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Keil MDK-ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Altium Tasking. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Atollic TrueSTUDIO. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-Arm. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Known Limitations\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+None. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>\r
+<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>\r
+V1.1.0 / 08-August-2012</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Main Changes\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Improvement of hardware acquisition mode of STM32L1xx High-density devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Disable hysteresis on sampling capacitor IOs to reduce acquisition noise level. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Use of the timer TSUSP mode. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Add support of Medium-density devices. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Add sofware acquisition mode on STM32L1xx High and Medium density devices. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Add TSLPRM_LINROT_USE_NORMDELTA parameter. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Content\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM8TL5xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F0xx devices (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx High-density devices using hardware and software acquisition modes (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx Medium-density devices using sofware acquisition mode (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of proximity, touchkey and linear/rotary touch sensors (1, 3, 5 and 6 channels). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Debounce mechanism for all states. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Environment Change System (ECS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Exclusion System (DXS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Time Out (DTO). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Noise filtering capability on measurement and delta. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Development Toolchains and Compilers\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM8 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ ST Visual Develop (STVD). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Cosmic STM8 C Compiler. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM32 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Keil MDK-ARM. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Known Limitations\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+None. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>\r
+<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>\r
+V1.0.0 / 25-June-2012</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Main Changes\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+First official release. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Content\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM8TL5xx devices (OFFICIAL). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32F0xx devices (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of STM32L1xx High-density devices using hardware acquisition mode (BETA). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Support of proximity, touchkey and linear/rotary touch sensors (1, 3, 5 and 6 channels). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Debounce mechanism for all states. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Environment Change System (ECS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Exclusion System (DXS). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Detection Time Out (DTO). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Noise filtering capability on measurement and delta. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Development Toolchains and Compilers\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM8 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ ST Visual Develop (STVD). \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Cosmic STM8 C Compiler. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Raisonance Ride7/RKit-STM8. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+STM32 devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ IAR Embedded Workbench for ARM. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ Keil MDK-ARM. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>\r
+Known Limitations\r
+</span></u></b></p>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+Use of Linear/Rotary sensors with STM32L1xx High-density devices: \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ The hardware acquisition is too noisy to properly support Linear/Rotary sensors. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ This noise induces an important jitter of the reported position. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ As a workaround, the position resolution must be configured to 4 bits maximum. \r
+</span>\r
+<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>\r
+ The Touchkey sensors are not impacted by this issue. \r
+</span></p>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;margin-right:4cm;width:80%;background:rgb(51, 102, 255)'>\r
+<td style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-left:0cm;margin-bottom:0cm;line-height:normal'><b><span style='font-size:12.0pt;color:white'>\r
+License</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>\r
+<p class=MsoNormal style='margin-left:4cm;margin-right:4cm;line-height:normal'><span style='font-size:10.0pt;color:black'>Licensed under MCD-ST Liberty SW License Agreement V2, (the "License").\r
+You may not use this file except in compliance with the License.\r
+You may obtain a copy of the License at:\r
+\r
+\r
+</span></p>\r
+<p class=MsoNormal style='text-align:center;line-height:normal'><span style='font-size:10.0pt'>\r
+<a href=http://www.st.com/software_license_agreement_liberty_v2> http://www.st.com/software_license_agreement_liberty_v2</a></span></p>\r
+<p class=MsoNormal style='margin-left:4cm;margin-right:4cm;line-height:normal'><span style='font-size:10.0pt;color:black'>Unless required by applicable law or agreed to in writing, software\r
+distributed under the License is distributed on an "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+See the License for the specific language governing permissions and\r
+limitations under the License.\r
+</a></span></p>\r
+<p class=MsoNormal style='line-height:normal'><b><span style='font-size:10.0pt'> </span></b></p>\r
+<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%\r
+style='margin-left:4cm;margin-right:4cm;width:80%;background:rgb(51, 102, 255)'>\r
+<td style='padding:0cm 5.4pt 0cm 5.4pt'>\r
+<p class=MsoNormal style='margin-left:0cm;margin-bottom:0cm;line-height:4pt'><b><span style='font-size:10.0pt;color:rgb(51, 102, 255)'>\r
+---</span></b></p></td></tr></table>\r
+<p class=MsoNormal style='line-height:normal'><b><span style='font-size:10.0pt'> </span></b></p>\r
+<p class=MsoNormal style='text-align:center;line-height:normal'><span style='font-size:10.0pt'>\r
+For complete documentation on <b>STMTouch</b> microcontrollers please visit <a href=http://www.st.com/stmtouch> http://www.st.com/stmtouch</a></span></p>\r
+<p class=MsoNormal style='line-height:normal'><b><span style='font-size:10.0pt'> </span></b></p>\r
+<p class=MsoNormal align=right style='margin-right:1cm;line-height:normal'><span style='font-size:8.0pt'>Generated by RNcreator v2.3\r
+</span></p>\r
+<!-- Generated by RNcreator v2.3 on 22-Jan-13 12:40:56 -->\r
+</div>\r
+</body>\r
+</html>\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_conf_stm32f0xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief Acquisition parameters for STM32F0xx products.\r
+ * @note This file must be copied in the application project and values\r
+ * changed for the application.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CONF_STM32F0XX_H\r
+#define __TSL_CONF_STM32F0XX_H\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup Common_Parameters Common Parameters\r
+ * @{ */\r
+\r
+//==============================================================================\r
+// Number of elements\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements\r
+ * @{ */\r
+\r
+/** Total number of channels in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_CHANNELS (1)\r
+\r
+/** Total number of banks in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_BANKS (1)\r
+\r
+/** Total number of "Extended" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS (1)\r
+\r
+/** Total number of "Basic" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS_B (1)\r
+\r
+/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS (1)\r
+\r
+/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS_B (1)\r
+\r
+/** Total number of sensors/objects in application (range=1..255)\r
+ - Count all TouchKeys, Linear and Rotary sensors\r
+*/\r
+#define TSLPRM_TOTAL_OBJECTS (1)\r
+\r
+/** @} Common_Parameters_Number_Of_Elements */\r
+\r
+//==============================================================================\r
+// Optional features\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Options 02 - Optional features\r
+ * @{ */\r
+\r
+/** Record the last measure (0=No, 1=Yes)\r
+ - If No the measure is recalculated using the Reference and Delta\r
+*/\r
+#define TSLPRM_USE_MEAS (1)\r
+\r
+/** Zone management usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_ZONE (1)\r
+\r
+/** Proximity detection usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_PROX (1)\r
+\r
+/** Use the Timer tick callback (0=No, 1=Yes)\r
+ - When equal to 1, the function TSL_CallBack_TimerTick must be defined in\r
+ the application code. It is called for each timer interruption.\r
+*/\r
+#define TSLPRM_USE_TIMER_CALLBACK (1)\r
+\r
+/** Acquisition interrupt mode (0=No, 1=Yes)\r
+ - If No the TS interrupt is not used.\r
+ - If Yes the TS interrupt is used.\r
+*/\r
+#define TSLPRM_USE_ACQ_INTERRUPT (1)\r
+\r
+/** @} Common_Parameters_Options */\r
+\r
+//==============================================================================\r
+// Acquisition limits\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits\r
+ * @{ */\r
+\r
+/** Minimum acquisition measurement (range=0..65535)\r
+ - This is the minimum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is below this value.\r
+*/\r
+#define TSLPRM_ACQ_MIN (10)\r
+\r
+/** Maximum acquisition measurement (range=255, 511, 1023, 2047, 8191, 16383)\r
+ - This is the maximum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is above this value.\r
+*/\r
+#define TSLPRM_ACQ_MAX (8191)\r
+\r
+/** @} Common_Parameters_Acquisition_Limits */\r
+\r
+//==============================================================================\r
+// Calibration\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Calibration 04 - Calibration\r
+ * @{ */\r
+\r
+/** Number of calibration samples (range=4, 8, 16)\r
+ - Low value = faster calibration but less precision.\r
+ - High value = slower calibration but more precision.\r
+*/\r
+#define TSLPRM_CALIB_SAMPLES (8)\r
+\r
+/** Delay in measurement samples before starting the calibration (range=0..40)\r
+ - This is usefull if a noise filter is used.\r
+ - Write 0 to disable the delay.\r
+*/\r
+#define TSLPRM_CALIB_DELAY (10)\r
+\r
+/** @} Common_Parameters_Calibration */\r
+\r
+//==============================================================================\r
+// Thresholds for TouchKey sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors\r
+ * @{ */\r
+\r
+/** TouchKeys Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_PROX_IN_TH (10)\r
+\r
+/** TouchKeys Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_PROX_OUT_TH (5)\r
+\r
+/** TouchKeys Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_DETECT_IN_TH (20)\r
+\r
+/** TouchKeys Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_DETECT_OUT_TH (15)\r
+\r
+/** TouchKeys re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_CALIB_TH (20)\r
+\r
+/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)\r
+ This multiplier coefficient is applied on Detect thresholds only.\r
+ - 0: feature disabled\r
+ - 1: thresholds x 2\r
+ - 2: thresholds x 4\r
+ - 3: thresholds x 8\r
+ - 4: thresholds x 16\r
+*/\r
+#define TSLPRM_COEFF_TH (1)\r
+\r
+/** @} Common_Parameters_TouchKey_Thresholds */\r
+\r
+//==============================================================================\r
+// Thresholds for Linear and Rotary sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors\r
+ * @{ */\r
+\r
+/** Linear/Rotary Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_PROX_IN_TH (10)\r
+\r
+/** Linear/Rotary Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_PROX_OUT_TH (5)\r
+\r
+/** Linear/Rotary Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_DETECT_IN_TH (20)\r
+\r
+/** Linear/Rotary Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_DETECT_OUT_TH (15)\r
+\r
+/** Linear/Rotary re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+ - A low absolute value will result in a higher sensitivity and thus some spurious\r
+ recalibration may be issued.\r
+*/\r
+#define TSLPRM_LINROT_CALIB_TH (20)\r
+\r
+/** Linear/Rotary Delta normalization (0=No, 1=Yes)\r
+ - When this parameter is set, a coefficient is applied on all Delta of all sensors\r
+ in order to normalize them and to improve the position calculation.\r
+ - These coefficients must be defined in a constant table in the application (see Library examples).\r
+ - The MSB is the coefficient integer part, the LSB is the coefficient real part.\r
+ - Examples:\r
+ - To apply a factor 1.10:\r
+ 0x01 to the MSB\r
+ 0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)\r
+ - To apply a factor 0.90:\r
+ 0x00 to the MSB\r
+ 0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)\r
+ - To apply no factor:\r
+ 0x01 to the MSB\r
+ 0x00 to the LSB\r
+*/\r
+#define TSLPRM_LINROT_USE_NORMDELTA (1)\r
+\r
+/** @} Common_Parameters_LinRot_Thresholds */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors used\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used\r
+ * @{ */\r
+\r
+/** Select which Linear and Rotary sensors you use in your application.\r
+ - 0 = Not Used\r
+ - 1 = Used\r
+\r
+ LIN = Linear sensor\r
+ ROT = Rotary sensor\r
+ M1 = Mono electrodes design with 0/255 position at extremities of the sensor\r
+ M2 = Mono electrodes design\r
+ H = Half-ended electrodes design\r
+ D = Dual electrodes design\r
+*/\r
+#define TSLPRM_USE_3CH_LIN_M1 (1)\r
+#define TSLPRM_USE_3CH_LIN_M2 (1)\r
+#define TSLPRM_USE_3CH_LIN_H (1)\r
+#define TSLPRM_USE_3CH_ROT_M (1)\r
+\r
+#define TSLPRM_USE_4CH_LIN_M1 (1)\r
+#define TSLPRM_USE_4CH_LIN_M2 (1)\r
+#define TSLPRM_USE_4CH_LIN_H (1)\r
+#define TSLPRM_USE_4CH_ROT_M (1)\r
+\r
+#define TSLPRM_USE_5CH_LIN_M1 (1)\r
+#define TSLPRM_USE_5CH_LIN_M2 (1)\r
+#define TSLPRM_USE_5CH_LIN_H (1)\r
+#define TSLPRM_USE_5CH_ROT_M (1)\r
+#define TSLPRM_USE_5CH_ROT_D (1)\r
+\r
+#define TSLPRM_USE_6CH_LIN_M1 (1)\r
+#define TSLPRM_USE_6CH_LIN_M2 (1)\r
+#define TSLPRM_USE_6CH_LIN_H (1)\r
+#define TSLPRM_USE_6CH_ROT_M (1)\r
+\r
+/** @} Common_Parameters_LinRot_used */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors position\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position\r
+ * @{ */\r
+\r
+/** Position resolution in number of bits (range=1..8)\r
+ - A Low value will result in a low resolution and will be less subject to noise.\r
+ - A High value will result in a high resolution and will be more subject to noise.\r
+*/\r
+#define TSLPRM_LINROT_RESOLUTION (7)\r
+\r
+/** Direction change threshold in position unit (range=0..255)\r
+ - Defines the default threshold used during the change direction process.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_POS (10)\r
+\r
+/** Direction change debounce (range=0..63)\r
+ - Defines the default integrator counter used during the change direction process.\r
+ - This counter is decremented when the same change in the position is detected and the direction will\r
+ change after this counter reaches zero.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_DEB (1)\r
+\r
+/** @} Common_Parameters_LinRot_Position */\r
+\r
+//==============================================================================\r
+// Debounce counters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Debounce 09 - Debounce counters\r
+ * @{ */\r
+\r
+/** Proximity state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_PROX (3)\r
+\r
+/** Detect state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_DETECT (3)\r
+\r
+/** Release state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the end-detection but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_RELEASE (3)\r
+\r
+/** Re-calibration state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the recalibration but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_CALIB (3)\r
+\r
+/** Error state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity to enter in error state.\r
+ - A High value will result in a lower sensitivity to enter in error state.\r
+*/\r
+#define TSLPRM_DEBOUNCE_ERROR (3)\r
+\r
+/** @} Common_Parameters_Debounce */\r
+\r
+//==============================================================================\r
+// Environment Change System (ECS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_ECS 10 - ECS\r
+ * @{ */\r
+\r
+/** Environment Change System Slow K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_SLOW (10)\r
+\r
+/** Environment Change System Fast K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_FAST (20)\r
+\r
+/** Environment Change System delay in msec (range=0..5000)\r
+ - The ECS will be started after this delay and when all sensors are in Release state.\r
+*/\r
+#define TSLPRM_ECS_DELAY (500)\r
+\r
+/** @} Common_Parameters_ECS */\r
+\r
+//==============================================================================\r
+// Detection Time Out (DTO)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DTO 11 - DTO\r
+ * @{ */\r
+\r
+/** Detection Time Out delay in seconds (range=0..63)\r
+ - Value 0: DTO processing not compiled in the code (to gain size if not used).\r
+ - Value 1: Default time out infinite.\r
+ - Value between 2 and 63: Default time out between value n-1 and n.\r
+ - Examples:\r
+ - With a DTO equal to 2, the time out is between 1s and 2s.\r
+ - With a DTO equal to 63, the time out is between 62s and 63s.\r
+\r
+@note The DTO can be changed in run-time by the application only if the\r
+ default value is between 1 and 63.\r
+*/\r
+#define TSLPRM_DTO (5)\r
+\r
+/** @} Common_Parameters_DTO */\r
+\r
+//==============================================================================\r
+// Detection Exclusion System (DXS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DXS 12 - DXS\r
+ * @{ */\r
+\r
+/** Detection Exclusion System (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_DXS (1)\r
+\r
+/** @} Common_Parameters_DXS */\r
+\r
+//==============================================================================\r
+// Miscellaneous parameters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Misc 13 - Miscellaneous\r
+ * @{ */\r
+\r
+/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)\r
+ - Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms\r
+*/\r
+#define TSLPRM_TICK_FREQ (1000)\r
+\r
+/** @} Common_Parameters_Misc */\r
+\r
+/** @} Common_Parameters */\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup STM32F0xx_Parameters STM32F0xx Parameters\r
+ * @{ */\r
+\r
+//==============================================================================\r
+// GPIO configuration\r
+//==============================================================================\r
+\r
+/** @defgroup STM32F0xx_Parameters_GPIO_Config 01 - TSC GPIOs Configuration\r
+ * @{ */\r
+\r
+/** TSC GPIOs Configuration selection (range=0..1)\r
+ - 0: Manual. The TSC GPIOs configuration must be done by the application code.\r
+ - 1: Automatic. The TSLPRM_TSC_GROUPx_IOy parameters below must be filled up.\r
+ The TSC GPIOs configuration is automatically done by the STMTouch driver.\r
+*/\r
+#define TSLPRM_TSC_GPIO_CONFIG (1)\r
+\r
+//+++ DO NOT CHANGE THESE VALUES +++++++++++++++++++++++++++++++++\r
+// These defines must be applied to the TSLPRM_TSC_GROUPx_IOy parameters below.\r
+#define NU (0) // Not Used IO\r
+#define CHANNEL (1) // Channel IO\r
+#define SHIELD (2) // Shield IO (= Channel IO but not acquired)\r
+#define SAMPCAP (3) // Sampling Capacitor IO\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// If TSLPRM_TSC_GPIO_CONFIG=1 assign each TSLPRM_TSC_GROUPx_IOy parameters below.\r
+// If TSLPRM_TSC_GPIO_CONFIG=0 these parameters are ignored.\r
+\r
+#define TSLPRM_TSC_GROUP1_IO1 NU // PA0\r
+#define TSLPRM_TSC_GROUP1_IO2 NU // PA1\r
+#define TSLPRM_TSC_GROUP1_IO3 NU // PA2\r
+#define TSLPRM_TSC_GROUP1_IO4 NU // PA3\r
+\r
+#define TSLPRM_TSC_GROUP2_IO1 NU // PA4\r
+#define TSLPRM_TSC_GROUP2_IO2 NU // PA5\r
+#define TSLPRM_TSC_GROUP2_IO3 NU // PA6\r
+#define TSLPRM_TSC_GROUP2_IO4 NU // PA7\r
+\r
+#define TSLPRM_TSC_GROUP3_IO1 NU // PC5\r
+#define TSLPRM_TSC_GROUP3_IO2 NU // PB0\r
+#define TSLPRM_TSC_GROUP3_IO3 NU // PB1\r
+#define TSLPRM_TSC_GROUP3_IO4 NU // PB2\r
+\r
+#define TSLPRM_TSC_GROUP4_IO1 NU // PA9\r
+#define TSLPRM_TSC_GROUP4_IO2 NU // PA10\r
+#define TSLPRM_TSC_GROUP4_IO3 NU // PA11\r
+#define TSLPRM_TSC_GROUP4_IO4 NU // PA12\r
+\r
+#define TSLPRM_TSC_GROUP5_IO1 NU // PB3\r
+#define TSLPRM_TSC_GROUP5_IO2 NU // PB4\r
+#define TSLPRM_TSC_GROUP5_IO3 NU // PB6\r
+#define TSLPRM_TSC_GROUP5_IO4 NU // PB7\r
+\r
+#define TSLPRM_TSC_GROUP6_IO1 NU // PB11\r
+#define TSLPRM_TSC_GROUP6_IO2 NU // PB12\r
+#define TSLPRM_TSC_GROUP6_IO3 NU // PB13\r
+#define TSLPRM_TSC_GROUP6_IO4 NU // PB14\r
+\r
+/** @} STM32F0xx_Parameters_GPIO_Config */\r
+\r
+//==============================================================================\r
+// Charge Transfer Pulses\r
+//==============================================================================\r
+\r
+/** @defgroup STM32F0xx_Parameters_CT_Pulses 02 - Charge Transfer Pulses\r
+ * @{ */\r
+\r
+/** Charge Transfer Pulse High (range=0..15)\r
+ - 0: 1 x tPGCLK\r
+ - 1: 2 x tPGCLK\r
+ - ...\r
+ - 15: 16 x tPGCLK\r
+*/\r
+#define TSLPRM_TSC_CTPH (1)\r
+\r
+/** Charge Transfer Pulse Low (range=0..15)\r
+ - 0: 1 x tPGCLK\r
+ - 1: 2 x tPGCLK\r
+ - ...\r
+ - 15: 16 x tPGCLK\r
+*/\r
+#define TSLPRM_TSC_CTPL (1)\r
+\r
+/** Pulse Generator Prescaler (range=0..7)\r
+ - 0: fPGCLK = fHCLK\r
+ - 1: fPGCLK = fHCLK/2\r
+ - ...\r
+ - 7: fPGCLK = fHCLK/128\r
+*/\r
+#define TSLPRM_TSC_PGPSC (5)\r
+\r
+/** @} STM32F0xx_Parameters_CT_Pulses */\r
+\r
+//==============================================================================\r
+// IOs\r
+//==============================================================================\r
+\r
+/** @defgroup STM32F0xx_Parameters_IOs 03 - I/Os\r
+ * @{ */\r
+\r
+/** TSC IOs default mode when no on-going acquisition (range=0..1)\r
+ - 0: Output push-pull low\r
+ - 1: Input floating\r
+*/\r
+#define TSLPRM_TSC_IODEF (0)\r
+\r
+/** Acquisition Mode (range=0..1)\r
+ - 0: Normal acquisition mode\r
+ - 1: Synchronized acquisition mode\r
+*/\r
+#define TSLPRM_TSC_AM (0)\r
+\r
+/** Synchronization Pin (range=0..1)\r
+ - 0: PB08\r
+ - 1: PB10\r
+*/\r
+#define TSLPRM_TSC_SYNC_PIN (0)\r
+\r
+/** Synchronization Polarity (range=0..1)\r
+ - 0: Falling edge only\r
+ - 1: Rising edge and high level\r
+*/\r
+#define TSLPRM_TSC_SYNC_POL (0)\r
+\r
+/** @} STM32F0xx_Parameters_Misc */\r
+\r
+//==============================================================================\r
+// Spread Spectrum\r
+//==============================================================================\r
+\r
+/** @defgroup STM32F0xx_Parameters_SpreadSpectrum 04 - Spread Spectrum\r
+ * @{ */\r
+\r
+/** Use Spread Spectrum (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_TSC_USE_SS (0)\r
+\r
+/** Spread Spectrum Deviation (range=0..127)\r
+ - 0: 1 x tSSCLK\r
+ - 1: 2 x tSSCLK\r
+ - ...\r
+ - 127: 128 x tSSCLK\r
+*/\r
+#define TSLPRM_TSC_SSD (0)\r
+\r
+/** Spread Spectrum Prescaler (range=0..1)\r
+ - 0: fSSCLK = fHCLK\r
+ - 1: fSSCLK = fHCLK/2\r
+*/\r
+#define TSLPRM_TSC_SSPSC (0)\r
+\r
+/** @} STM32F0xx_Parameters_SpreadSpectrum */\r
+\r
+/** @} STM32F0xx_Parameters */\r
+\r
+// DO NOT REMOVE !!!\r
+#include "tsl_check_config.h"\r
+\r
+#endif /* __TSL_CONF_STM32F0XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_conf_stm32f3xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief Acquisition parameters for STM32F3xx products.\r
+ * @note This file must be copied in the application project and values\r
+ * changed for the application.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CONF_STM32F3XX_H\r
+#define __TSL_CONF_STM32F3XX_H\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup Common_Parameters Common Parameters\r
+ * @{ */\r
+\r
+//==============================================================================\r
+// Number of elements\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements\r
+ * @{ */\r
+\r
+/** Total number of channels in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_CHANNELS (1)\r
+\r
+/** Total number of banks in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_BANKS (1)\r
+\r
+/** Total number of "Extended" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS (1)\r
+\r
+/** Total number of "Basic" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS_B (1)\r
+\r
+/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS (1)\r
+\r
+/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS_B (1)\r
+\r
+/** Total number of sensors/objects in application (range=1..255)\r
+ - Count all TouchKeys, Linear and Rotary sensors\r
+*/\r
+#define TSLPRM_TOTAL_OBJECTS (1)\r
+\r
+/** @} Common_Parameters_Number_Of_Elements */\r
+\r
+//==============================================================================\r
+// Optional features\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Options 02 - Optional features\r
+ * @{ */\r
+\r
+/** Record the last measure (0=No, 1=Yes)\r
+ - If No the measure is recalculated using the Reference and Delta\r
+*/\r
+#define TSLPRM_USE_MEAS (1)\r
+\r
+/** Zone management usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_ZONE (1)\r
+\r
+/** Proximity detection usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_PROX (1)\r
+\r
+/** Use the Timer tick callback (0=No, 1=Yes)\r
+ - When equal to 1, the function TSL_CallBack_TimerTick must be defined in\r
+ the application code. It is called for each timer interruption.\r
+*/\r
+#define TSLPRM_USE_TIMER_CALLBACK (1)\r
+\r
+/** Acquisition interrupt mode (0=No, 1=Yes)\r
+ - If No the TS interrupt is not used.\r
+ - If Yes the TS interrupt is used.\r
+*/\r
+#define TSLPRM_USE_ACQ_INTERRUPT (1)\r
+\r
+/** @} Common_Parameters_Options */\r
+\r
+//==============================================================================\r
+// Acquisition limits\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits\r
+ * @{ */\r
+\r
+/** Minimum acquisition measurement (range=0..65535)\r
+ - This is the minimum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is below this value.\r
+*/\r
+#define TSLPRM_ACQ_MIN (10)\r
+\r
+/** Maximum acquisition measurement (range=255, 511, 1023, 2047, 8191, 16383)\r
+ - This is the maximum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is above this value.\r
+*/\r
+#define TSLPRM_ACQ_MAX (8191)\r
+\r
+/** @} Common_Parameters_Acquisition_Limits */\r
+\r
+//==============================================================================\r
+// Calibration\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Calibration 04 - Calibration\r
+ * @{ */\r
+\r
+/** Number of calibration samples (range=4, 8, 16)\r
+ - Low value = faster calibration but less precision.\r
+ - High value = slower calibration but more precision.\r
+*/\r
+#define TSLPRM_CALIB_SAMPLES (8)\r
+\r
+/** Delay in measurement samples before starting the calibration (range=0..40)\r
+ - This is usefull if a noise filter is used.\r
+ - Write 0 to disable the delay.\r
+*/\r
+#define TSLPRM_CALIB_DELAY (10)\r
+\r
+/** @} Common_Parameters_Calibration */\r
+\r
+//==============================================================================\r
+// Thresholds for TouchKey sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors\r
+ * @{ */\r
+\r
+/** TouchKeys Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_PROX_IN_TH (10)\r
+\r
+/** TouchKeys Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_PROX_OUT_TH (5)\r
+\r
+/** TouchKeys Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_DETECT_IN_TH (20)\r
+\r
+/** TouchKeys Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_DETECT_OUT_TH (15)\r
+\r
+/** TouchKeys re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_CALIB_TH (20)\r
+\r
+/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)\r
+ This multiplier coefficient is applied on Detect thresholds only.\r
+ - 0: feature disabled\r
+ - 1: thresholds x 2\r
+ - 2: thresholds x 4\r
+ - 3: thresholds x 8\r
+ - 4: thresholds x 16\r
+*/\r
+#define TSLPRM_COEFF_TH (1)\r
+\r
+/** @} Common_Parameters_TouchKey_Thresholds */\r
+\r
+//==============================================================================\r
+// Thresholds for Linear and Rotary sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors\r
+ * @{ */\r
+\r
+/** Linear/Rotary Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_PROX_IN_TH (10)\r
+\r
+/** Linear/Rotary Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_PROX_OUT_TH (5)\r
+\r
+/** Linear/Rotary Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_DETECT_IN_TH (20)\r
+\r
+/** Linear/Rotary Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_DETECT_OUT_TH (15)\r
+\r
+/** Linear/Rotary re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+ - A low absolute value will result in a higher sensitivity and thus some spurious\r
+ recalibration may be issued.\r
+*/\r
+#define TSLPRM_LINROT_CALIB_TH (20)\r
+\r
+/** Linear/Rotary Delta normalization (0=No, 1=Yes)\r
+ - When this parameter is set, a coefficient is applied on all Delta of all sensors\r
+ in order to normalize them and to improve the position calculation.\r
+ - These coefficients must be defined in a constant table in the application (see Library examples).\r
+ - The MSB is the coefficient integer part, the LSB is the coefficient real part.\r
+ - Examples:\r
+ - To apply a factor 1.10:\r
+ 0x01 to the MSB\r
+ 0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)\r
+ - To apply a factor 0.90:\r
+ 0x00 to the MSB\r
+ 0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)\r
+ - To apply no factor:\r
+ 0x01 to the MSB\r
+ 0x00 to the LSB\r
+*/\r
+#define TSLPRM_LINROT_USE_NORMDELTA (1)\r
+\r
+/** @} Common_Parameters_LinRot_Thresholds */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors used\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used\r
+ * @{ */\r
+\r
+/** Select which Linear and Rotary sensors you use in your application.\r
+ - 0 = Not Used\r
+ - 1 = Used\r
+\r
+ LIN = Linear sensor\r
+ ROT = Rotary sensor\r
+ M1 = Mono electrodes design with 0/255 position at extremities of the sensor\r
+ M2 = Mono electrodes design\r
+ H = Half-ended electrodes design\r
+ D = Dual electrodes design\r
+*/\r
+#define TSLPRM_USE_3CH_LIN_M1 (1)\r
+#define TSLPRM_USE_3CH_LIN_M2 (1)\r
+#define TSLPRM_USE_3CH_LIN_H (1)\r
+#define TSLPRM_USE_3CH_ROT_M (1)\r
+\r
+#define TSLPRM_USE_4CH_LIN_M1 (1)\r
+#define TSLPRM_USE_4CH_LIN_M2 (1)\r
+#define TSLPRM_USE_4CH_LIN_H (1)\r
+#define TSLPRM_USE_4CH_ROT_M (1)\r
+\r
+#define TSLPRM_USE_5CH_LIN_M1 (1)\r
+#define TSLPRM_USE_5CH_LIN_M2 (1)\r
+#define TSLPRM_USE_5CH_LIN_H (1)\r
+#define TSLPRM_USE_5CH_ROT_M (1)\r
+#define TSLPRM_USE_5CH_ROT_D (1)\r
+\r
+#define TSLPRM_USE_6CH_LIN_M1 (1)\r
+#define TSLPRM_USE_6CH_LIN_M2 (1)\r
+#define TSLPRM_USE_6CH_LIN_H (1)\r
+#define TSLPRM_USE_6CH_ROT_M (1)\r
+\r
+/** @} Common_Parameters_LinRot_used */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors position\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position\r
+ * @{ */\r
+\r
+/** Position resolution in number of bits (range=1..8)\r
+ - A Low value will result in a low resolution and will be less subject to noise.\r
+ - A High value will result in a high resolution and will be more subject to noise.\r
+*/\r
+#define TSLPRM_LINROT_RESOLUTION (7)\r
+\r
+/** Direction change threshold in position unit (range=0..255)\r
+ - Defines the default threshold used during the change direction process.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_POS (10)\r
+\r
+/** Direction change debounce (range=0..63)\r
+ - Defines the default integrator counter used during the change direction process.\r
+ - This counter is decremented when the same change in the position is detected and the direction will\r
+ change after this counter reaches zero.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_DEB (1)\r
+\r
+/** @} Common_Parameters_LinRot_Position */\r
+\r
+//==============================================================================\r
+// Debounce counters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Debounce 09 - Debounce counters\r
+ * @{ */\r
+\r
+/** Proximity state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_PROX (3)\r
+\r
+/** Detect state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_DETECT (3)\r
+\r
+/** Release state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the end-detection but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_RELEASE (3)\r
+\r
+/** Re-calibration state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the recalibration but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_CALIB (3)\r
+\r
+/** Error state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity to enter in error state.\r
+ - A High value will result in a lower sensitivity to enter in error state.\r
+*/\r
+#define TSLPRM_DEBOUNCE_ERROR (3)\r
+\r
+/** @} Common_Parameters_Debounce */\r
+\r
+//==============================================================================\r
+// Environment Change System (ECS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_ECS 10 - ECS\r
+ * @{ */\r
+\r
+/** Environment Change System Slow K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_SLOW (10)\r
+\r
+/** Environment Change System Fast K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_FAST (20)\r
+\r
+/** Environment Change System delay in msec (range=0..5000)\r
+ - The ECS will be started after this delay and when all sensors are in Release state.\r
+*/\r
+#define TSLPRM_ECS_DELAY (500)\r
+\r
+/** @} Common_Parameters_ECS */\r
+\r
+//==============================================================================\r
+// Detection Time Out (DTO)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DTO 11 - DTO\r
+ * @{ */\r
+\r
+/** Detection Time Out delay in seconds (range=0..63)\r
+ - Value 0: DTO processing not compiled in the code (to gain size if not used).\r
+ - Value 1: Default time out infinite.\r
+ - Value between 2 and 63: Default time out between value n-1 and n.\r
+ - Examples:\r
+ - With a DTO equal to 2, the time out is between 1s and 2s.\r
+ - With a DTO equal to 63, the time out is between 62s and 63s.\r
+\r
+@note The DTO can be changed in run-time by the application only if the\r
+ default value is between 1 and 63.\r
+*/\r
+#define TSLPRM_DTO (5)\r
+\r
+/** @} Common_Parameters_DTO */\r
+\r
+//==============================================================================\r
+// Detection Exclusion System (DXS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DXS 12 - DXS\r
+ * @{ */\r
+\r
+/** Detection Exclusion System (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_DXS (1)\r
+\r
+/** @} Common_Parameters_DXS */\r
+\r
+//==============================================================================\r
+// Miscellaneous parameters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Misc 13 - Miscellaneous\r
+ * @{ */\r
+\r
+/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)\r
+ - Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms\r
+*/\r
+#define TSLPRM_TICK_FREQ (1000)\r
+\r
+/** @} Common_Parameters_Misc */\r
+\r
+/** @} Common_Parameters */\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup STM32F3xx_Parameters STM32F3xx Parameters\r
+ * @{ */\r
+\r
+//==============================================================================\r
+// GPIO configuration\r
+//==============================================================================\r
+\r
+/** @defgroup STM32F3xx_Parameters_GPIO_Config 01 - TSC GPIOs Configuration\r
+ * @{ */\r
+\r
+/** TSC GPIOs Configuration selection (range=0..1)\r
+ - 0: Manual. The TSC GPIOs configuration must be done by the application code.\r
+ - 1: Automatic. The TSLPRM_TSC_GROUPx_IOy parameters below must be filled up.\r
+ The TSC GPIOs configuration is automatically done by the STMTouch driver.\r
+*/\r
+#define TSLPRM_TSC_GPIO_CONFIG (1)\r
+\r
+//+++ DO NOT CHANGE THESE VALUES +++++++++++++++++++++++++++++++++\r
+// These defines must be applied to the TSLPRM_TSC_GROUPx_IOy parameters below.\r
+#define NU (0) // Not Used IO\r
+#define CHANNEL (1) // Channel IO\r
+#define SHIELD (2) // Shield IO (= Channel IO but not acquired)\r
+#define SAMPCAP (3) // Sampling Capacitor IO\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// If TSLPRM_TSC_GPIO_CONFIG=1 assign each TSLPRM_TSC_GROUPx_IOy parameters below.\r
+// If TSLPRM_TSC_GPIO_CONFIG=0 these parameters are ignored.\r
+// STM32F30X STM32F37X\r
+#define TSLPRM_TSC_GROUP1_IO1 NU // PA0 PA0\r
+#define TSLPRM_TSC_GROUP1_IO2 NU // PA1 PA1\r
+#define TSLPRM_TSC_GROUP1_IO3 NU // PA2 PA2\r
+#define TSLPRM_TSC_GROUP1_IO4 NU // PA3 PA3\r
+\r
+#define TSLPRM_TSC_GROUP2_IO1 NU // PA4 PA4\r
+#define TSLPRM_TSC_GROUP2_IO2 NU // PA5 PA5\r
+#define TSLPRM_TSC_GROUP2_IO3 NU // PA6 PA6\r
+#define TSLPRM_TSC_GROUP2_IO4 NU // PA7 PA7\r
+\r
+#define TSLPRM_TSC_GROUP3_IO1 NU // PC5 PC4 << diff\r
+#define TSLPRM_TSC_GROUP3_IO2 NU // PB0 PC5 << diff\r
+#define TSLPRM_TSC_GROUP3_IO3 NU // PB1 PB0 << diff\r
+#define TSLPRM_TSC_GROUP3_IO4 NU // PB2 PB1 << diff\r
+\r
+#define TSLPRM_TSC_GROUP4_IO1 NU // PA9 PA9\r
+#define TSLPRM_TSC_GROUP4_IO2 NU // PA10 PA10\r
+#define TSLPRM_TSC_GROUP4_IO3 NU // PA13 PA13\r
+#define TSLPRM_TSC_GROUP4_IO4 NU // PA14 PA14\r
+\r
+#define TSLPRM_TSC_GROUP5_IO1 NU // PB3 PB3\r
+#define TSLPRM_TSC_GROUP5_IO2 NU // PB4 PB4\r
+#define TSLPRM_TSC_GROUP5_IO3 NU // PB6 PB6\r
+#define TSLPRM_TSC_GROUP5_IO4 NU // PB7 PB7\r
+\r
+#define TSLPRM_TSC_GROUP6_IO1 NU // PB11 PB14 << diff\r
+#define TSLPRM_TSC_GROUP6_IO2 NU // PB12 PB15 << diff\r
+#define TSLPRM_TSC_GROUP6_IO3 NU // PB13 PD8 << diff\r
+#define TSLPRM_TSC_GROUP6_IO4 NU // PB14 PD9 << diff\r
+\r
+#define TSLPRM_TSC_GROUP7_IO1 NU // PE2 PE2\r
+#define TSLPRM_TSC_GROUP7_IO2 NU // PE3 PE3\r
+#define TSLPRM_TSC_GROUP7_IO3 NU // PE4 PE4\r
+#define TSLPRM_TSC_GROUP7_IO4 NU // PE5 PE5\r
+\r
+#define TSLPRM_TSC_GROUP8_IO1 NU // PD12 PD12\r
+#define TSLPRM_TSC_GROUP8_IO2 NU // PD13 PD13\r
+#define TSLPRM_TSC_GROUP8_IO3 NU // PD14 PD14\r
+#define TSLPRM_TSC_GROUP8_IO4 NU // PD15 PD15\r
+\r
+/** @} STM32F3xx_Parameters_GPIO_Config */\r
+\r
+//==============================================================================\r
+// Charge Transfer Pulses\r
+//==============================================================================\r
+\r
+/** @defgroup STM32F3xx_Parameters_CT_Pulses 02 - Charge Transfer Pulses\r
+ * @{ */\r
+\r
+/** Charge Transfer Pulse High (range=0..15)\r
+ - 0: 1 x tPGCLK\r
+ - 1: 2 x tPGCLK\r
+ - ...\r
+ - 15: 16 x tPGCLK\r
+*/\r
+#define TSLPRM_TSC_CTPH (1)\r
+\r
+/** Charge Transfer Pulse Low (range=0..15)\r
+ - 0: 1 x tPGCLK\r
+ - 1: 2 x tPGCLK\r
+ - ...\r
+ - 15: 16 x tPGCLK\r
+*/\r
+#define TSLPRM_TSC_CTPL (1)\r
+\r
+/** Pulse Generator Prescaler (range=0..7)\r
+ - 0: fPGCLK = fHCLK\r
+ - 1: fPGCLK = fHCLK/2\r
+ - ...\r
+ - 7: fPGCLK = fHCLK/128\r
+*/\r
+#define TSLPRM_TSC_PGPSC (5)\r
+\r
+/** @} STM32F3xx_Parameters_CT_Pulses */\r
+\r
+//==============================================================================\r
+// IOs\r
+//==============================================================================\r
+\r
+/** @defgroup STM32F3xx_Parameters_IOs 03 - I/Os\r
+ * @{ */\r
+\r
+/** TSC IOs default mode when no on-going acquisition (range=0..1)\r
+ - 0: Output push-pull low\r
+ - 1: Input floating\r
+*/\r
+#define TSLPRM_TSC_IODEF (0)\r
+\r
+/** Acquisition Mode (range=0..1)\r
+ - 0: Normal acquisition mode\r
+ - 1: Synchronized acquisition mode\r
+*/\r
+#define TSLPRM_TSC_AM (0)\r
+\r
+/** Synchronization Pin (range=0..1)\r
+ - 0: PB08\r
+ - 1: PB10\r
+*/\r
+#define TSLPRM_TSC_SYNC_PIN (0)\r
+\r
+/** Synchronization Polarity (range=0..1)\r
+ - 0: Falling edge only\r
+ - 1: Rising edge and high level\r
+*/\r
+#define TSLPRM_TSC_SYNC_POL (0)\r
+\r
+/** @} STM32F3xx_Parameters_Misc */\r
+\r
+//==============================================================================\r
+// Spread Spectrum\r
+//==============================================================================\r
+\r
+/** @defgroup STM32F3xx_Parameters_SpreadSpectrum 04 - Spread Spectrum\r
+ * @{ */\r
+\r
+/** Use Spread Spectrum (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_TSC_USE_SS (0)\r
+\r
+/** Spread Spectrum Deviation (range=0..127)\r
+ - 0: 1 x tSSCLK\r
+ - 1: 2 x tSSCLK\r
+ - ...\r
+ - 127: 128 x tSSCLK\r
+*/\r
+#define TSLPRM_TSC_SSD (0)\r
+\r
+/** Spread Spectrum Prescaler (range=0..1)\r
+ - 0: fSSCLK = fHCLK\r
+ - 1: fSSCLK = fHCLK/2\r
+*/\r
+#define TSLPRM_TSC_SSPSC (0)\r
+\r
+/** @} STM32F3xx_Parameters_SpreadSpectrum */\r
+\r
+/** @} STM32F3xx_Parameters */\r
+\r
+// DO NOT REMOVE !!!\r
+#include "tsl_check_config.h"\r
+\r
+#endif /* __TSL_CONF_STM32F3XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_conf_stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief Acquisition parameters for STM32L1xx products.\r
+ * @note This file must be copied in the application project and values\r
+ * changed for the application.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CONF_STM32L1xx_H\r
+#define __TSL_CONF_STM32L1xx_H\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup Common_Parameters Common Parameters\r
+ * @{ */\r
+\r
+//==============================================================================\r
+// Number of elements\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements\r
+ * @{ */\r
+\r
+/** Total number of channels in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_CHANNELS (1)\r
+\r
+/** Total number of banks in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_BANKS (1)\r
+\r
+/** Total number of "Extended" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS (1)\r
+\r
+/** Total number of "Basic" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS_B (1)\r
+\r
+/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS (1)\r
+\r
+/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS_B (1)\r
+\r
+/** Total number of sensors/objects in application (range=1..255)\r
+ - Count all TouchKeys, Linear and Rotary sensors\r
+*/\r
+#define TSLPRM_TOTAL_OBJECTS (1)\r
+\r
+/** @} Common_Parameters_Number_Of_Elements */\r
+\r
+//==============================================================================\r
+// Optional features\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Options 02 - Optional features\r
+ * @{ */\r
+\r
+/** Record the last measure (0=No, 1=Yes)\r
+ - If No the measure is recalculated using the Reference and Delta\r
+*/\r
+#define TSLPRM_USE_MEAS (1)\r
+\r
+/** Zone management usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_ZONE (1)\r
+\r
+/** Proximity detection usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_PROX (1)\r
+\r
+/** Use the Timer tick callback (0=No, 1=Yes)\r
+ - When equal to 1, the function TSL_CallBack_TimerTick must be defined in\r
+ the application code. It is called for each timer interruption.\r
+*/\r
+#define TSLPRM_USE_TIMER_CALLBACK (1)\r
+\r
+/** Acquisition interrupt mode (0=No, 1=Yes)\r
+ - If No the TS interrupt is not used.\r
+ - If Yes the TS interrupt is used.\r
+*/\r
+#define TSLPRM_USE_ACQ_INTERRUPT (1)\r
+\r
+/** @} Common_Parameters_Options */\r
+\r
+//==============================================================================\r
+// Acquisition limits\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits\r
+ * @{ */\r
+\r
+/** Minimum acquisition measurement (range=0..65535)\r
+ - This is the minimum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is below this value.\r
+*/\r
+#define TSLPRM_ACQ_MIN (10)\r
+\r
+/** Maximum acquisition measurement (range=0..65535)\r
+ - This is the maximum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is above this value.\r
+*/\r
+#define TSLPRM_ACQ_MAX (4000)\r
+\r
+/** @} Common_Parameters_Acquisition_Limits */\r
+\r
+//==============================================================================\r
+// Calibration\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Calibration 04 - Calibration\r
+ * @{ */\r
+\r
+/** Number of calibration samples (range=4, 8, 16)\r
+ - Low value = faster calibration but less precision.\r
+ - High value = slower calibration but more precision.\r
+*/\r
+#define TSLPRM_CALIB_SAMPLES (8)\r
+\r
+/** Delay in measurement samples before starting the calibration (range=0..40)\r
+ - This is usefull if a noise filter is used.\r
+ - Write 0 to disable the delay.\r
+*/\r
+#define TSLPRM_CALIB_DELAY (10)\r
+\r
+/** @} Common_Parameters_Calibration */\r
+\r
+//==============================================================================\r
+// Thresholds for TouchKey sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors\r
+ * @{ */\r
+\r
+/** TouchKeys Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_PROX_IN_TH (10)\r
+\r
+/** TouchKeys Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_PROX_OUT_TH (5)\r
+\r
+/** TouchKeys Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_DETECT_IN_TH (20)\r
+\r
+/** TouchKeys Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_DETECT_OUT_TH (15)\r
+\r
+/** TouchKeys re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_CALIB_TH (20)\r
+\r
+/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)\r
+ This multiplier coefficient is applied on Detect thresholds only.\r
+ - 0: feature disabled\r
+ - 1: thresholds x 2\r
+ - 2: thresholds x 4\r
+ - 3: thresholds x 8\r
+ - 4: thresholds x 16\r
+*/\r
+#define TSLPRM_COEFF_TH (1)\r
+\r
+/** @} Common_Parameters_TouchKey_Thresholds */\r
+\r
+//==============================================================================\r
+// Thresholds for Linear and Rotary sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors\r
+ * @{ */\r
+\r
+/** Linear/Rotary Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_PROX_IN_TH (10)\r
+\r
+/** Linear/Rotary Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_PROX_OUT_TH (5)\r
+\r
+/** Linear/Rotary Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_DETECT_IN_TH (20)\r
+\r
+/** Linear/Rotary Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_DETECT_OUT_TH (15)\r
+\r
+/** Linear/Rotary re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+ - A low absolute value will result in a higher sensitivity and thus some spurious\r
+ recalibration may be issued.\r
+*/\r
+#define TSLPRM_LINROT_CALIB_TH (20)\r
+\r
+/** Linear/Rotary Delta normalization (0=No, 1=Yes)\r
+ - When this parameter is set, a coefficient is applied on all Delta of all sensors\r
+ in order to normalize them and to improve the position calculation.\r
+ - These coefficients must be defined in a constant table in the application (see Library examples).\r
+ - The MSB is the coefficient integer part, the LSB is the coefficient real part.\r
+ - Examples:\r
+ - To apply a factor 1.10:\r
+ 0x01 to the MSB\r
+ 0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)\r
+ - To apply a factor 0.90:\r
+ 0x00 to the MSB\r
+ 0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)\r
+ - To apply no factor:\r
+ 0x01 to the MSB\r
+ 0x00 to the LSB\r
+*/\r
+#define TSLPRM_LINROT_USE_NORMDELTA (1)\r
+\r
+/** @} Common_Parameters_LinRot_Thresholds */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors used\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used\r
+ * @{ */\r
+\r
+/** Select which Linear and Rotary sensors you use in your application.\r
+ - 0 = Not Used\r
+ - 1 = Used\r
+\r
+ LIN = Linear sensor\r
+ ROT = Rotary sensor\r
+ M1 = Mono electrodes design with 0/255 position at extremities of the sensor\r
+ M2 = Mono electrodes design\r
+ H = Half-ended electrodes design\r
+ D = Dual electrodes design\r
+*/\r
+#define TSLPRM_USE_3CH_LIN_M1 (1)\r
+#define TSLPRM_USE_3CH_LIN_M2 (1)\r
+#define TSLPRM_USE_3CH_LIN_H (1)\r
+#define TSLPRM_USE_3CH_ROT_M (1)\r
+\r
+#define TSLPRM_USE_4CH_LIN_M1 (1)\r
+#define TSLPRM_USE_4CH_LIN_M2 (1)\r
+#define TSLPRM_USE_4CH_LIN_H (1)\r
+#define TSLPRM_USE_4CH_ROT_M (1)\r
+\r
+#define TSLPRM_USE_5CH_LIN_M1 (1)\r
+#define TSLPRM_USE_5CH_LIN_M2 (1)\r
+#define TSLPRM_USE_5CH_LIN_H (1)\r
+#define TSLPRM_USE_5CH_ROT_M (1)\r
+#define TSLPRM_USE_5CH_ROT_D (1)\r
+\r
+#define TSLPRM_USE_6CH_LIN_M1 (1)\r
+#define TSLPRM_USE_6CH_LIN_M2 (1)\r
+#define TSLPRM_USE_6CH_LIN_H (1)\r
+#define TSLPRM_USE_6CH_ROT_M (1)\r
+\r
+/** @} Common_Parameters_LinRot_used */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors position\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position\r
+ * @{ */\r
+\r
+/** Position resolution in number of bits (range=1..8)\r
+ - A Low value will result in a low resolution and will be less subject to noise.\r
+ - A High value will result in a high resolution and will be more subject to noise.\r
+*/\r
+#define TSLPRM_LINROT_RESOLUTION (7)\r
+\r
+/** Direction change threshold in position unit (range=0..255)\r
+ - Defines the default threshold used during the change direction process.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_POS (10)\r
+\r
+/** Direction change debounce (range=0..63)\r
+ - Defines the default integrator counter used during the change direction process.\r
+ - This counter is decremented when the same change in the position is detected and the direction will\r
+ change after this counter reaches zero.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_DEB (1)\r
+\r
+/** @} Common_Parameters_LinRot_Position */\r
+\r
+//==============================================================================\r
+// Debounce counters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Debounce 09 - Debounce counters\r
+ * @{ */\r
+\r
+/** Proximity state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_PROX (3)\r
+\r
+/** Detect state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_DETECT (3)\r
+\r
+/** Release state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the end-detection but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_RELEASE (3)\r
+\r
+/** Re-calibration state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the recalibration but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_CALIB (3)\r
+\r
+/** Error state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity to enter in error state.\r
+ - A High value will result in a lower sensitivity to enter in error state.\r
+*/\r
+#define TSLPRM_DEBOUNCE_ERROR (3)\r
+\r
+/** @} Common_Parameters_Debounce */\r
+\r
+//==============================================================================\r
+// Environment Change System (ECS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_ECS 10 - ECS\r
+ * @{ */\r
+\r
+/** Environment Change System Slow K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_SLOW (10)\r
+\r
+/** Environment Change System Fast K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_FAST (20)\r
+\r
+/** Environment Change System delay in msec (range=0..5000)\r
+ - The ECS will be started after this delay and when all sensors are in Release state.\r
+*/\r
+#define TSLPRM_ECS_DELAY (500)\r
+\r
+/** @} Common_Parameters_ECS */\r
+\r
+//==============================================================================\r
+// Detection Time Out (DTO)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DTO 11 - DTO\r
+ * @{ */\r
+\r
+/** Detection Time Out delay in seconds (range=0..63)\r
+ - Value 0: DTO processing not compiled in the code (to gain size if not used).\r
+ - Value 1: Default time out infinite.\r
+ - Value between 2 and 63: Default time out between value n-1 and n.\r
+ - Examples:\r
+ - With a DTO equal to 2, the time out is between 1s and 2s.\r
+ - With a DTO equal to 63, the time out is between 62s and 63s.\r
+\r
+@note The DTO can be changed in run-time by the application only if the\r
+ default value is between 1 and 63.\r
+*/\r
+#define TSLPRM_DTO (5)\r
+\r
+/** @} Common_Parameters_DTO */\r
+\r
+//==============================================================================\r
+// Detection Exclusion System (DXS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DXS 12 - DXS\r
+ * @{ */\r
+\r
+/** Detection Exclusion System (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_DXS (1)\r
+\r
+/** @} Common_Parameters_DXS */\r
+\r
+//==============================================================================\r
+// Miscellaneous parameters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Misc 13 - Miscellaneous\r
+ * @{ */\r
+\r
+/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)\r
+ - Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms\r
+*/\r
+#define TSLPRM_TICK_FREQ (1000)\r
+\r
+/** @} Common_Parameters_Misc */\r
+\r
+/** @} Common_Parameters */\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup STM32L1xx_Parameters STM32L1xx Parameters\r
+ * @{ */\r
+\r
+/** @defgroup STM32L1xx_Parameters_Misc 01 - Miscellaneous\r
+ * @{ */\r
+\r
+/** Shield with a channel (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_SHIELD (1)\r
+\r
+/** IOs default mode when no on-going acquisition (range=0..1)\r
+ - 0: Output push-pull low\r
+ - 1: Input floating\r
+*/\r
+#define TSLPRM_IODEF (1)\r
+\r
+/** Master timer prescaler for HW acquisition only (range=0..65535)\r
+ - Divide the timer input clock by this value plus one\r
+*/\r
+#define TSLPRM_TIM_PRESCALER (0)\r
+\r
+/** Master timer reload value for HW acquisition only (range=4..65534, even number)\r
+ - Set the auto-reload value for the center aligned counter\r
+*/\r
+#define TSLPRM_TIM_RELOAD (64)\r
+\r
+/** IT disabling for IO protection for SW acquisition only (range=0..1)\r
+ - 0: IO not protected\r
+ - 1: IO protected\r
+*/\r
+#define TSLPRM_PROTECT_IO_ACCESS (0)\r
+\r
+/** Which GPIO will be used for SW acquisition only (range=0..1)\r
+ - 0: Not used\r
+ - 1: Used\r
+*/\r
+#define TSLPRM_USE_GPIOA (1)\r
+#define TSLPRM_USE_GPIOB (1)\r
+#define TSLPRM_USE_GPIOC (1)\r
+#define TSLPRM_USE_GPIOF (0)\r
+#define TSLPRM_USE_GPIOG (0)\r
+\r
+/** @} STM32L1xx_Parameters_Misc */\r
+\r
+/** @} STM32L1xx_Parameters */\r
+\r
+// DO NOT REMOVE !!!\r
+#include "tsl_check_config.h"\r
+\r
+#endif /* __TSL_CONF_STM32L1xx_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_conf_stm8tl5x.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief Acquisition parameters for STM8TL5x products.\r
+ * @note This file must be copied in the application project and values\r
+ * changed for the application.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CONF_STM8TL5X_H\r
+#define __TSL_CONF_STM8TL5X_H\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup Common_Parameters Common Parameters\r
+ * @{ */\r
+\r
+//==============================================================================\r
+// Number of elements\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements\r
+ * @{ */\r
+\r
+/** Total number of channels in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_CHANNELS (1)\r
+\r
+/** Total number of banks in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_BANKS (1)\r
+\r
+/** Total number of "Extended" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS (1)\r
+\r
+/** Total number of "Basic" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS_B (1)\r
+\r
+/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS (1)\r
+\r
+/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS_B (1)\r
+\r
+/** Total number of sensors/objects in application (range=1..255)\r
+ - Count all TouchKeys, Linear and Rotary sensors\r
+*/\r
+#define TSLPRM_TOTAL_OBJECTS (1)\r
+\r
+/** @} Common_Parameters_Number_Of_Elements */\r
+\r
+//==============================================================================\r
+// Optional features\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Options 02 - Optional features\r
+ * @{ */\r
+\r
+/** Record the last measure (0=No, 1=Yes)\r
+ - If No the measure is recalculated using the Reference and Delta\r
+*/\r
+#define TSLPRM_USE_MEAS (1)\r
+\r
+/** Zone management usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_ZONE (1)\r
+\r
+/** Proximity detection usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_PROX (1)\r
+\r
+/** Use the Timer tick callback (0=No, 1=Yes)\r
+ - When equal to 1, the function TSL_CallBack_TimerTick must be defined in\r
+ the application code. It is called for each timer interruption.\r
+*/\r
+#define TSLPRM_USE_TIMER_CALLBACK (1)\r
+\r
+/** Acquisition interrupt mode (0=No, 1=Yes)\r
+ - If No the acquisition is managed in the main routine using polling mode.\r
+ - If Yes the acquisition is managed in the interrupt routines.\r
+*/\r
+#define TSLPRM_USE_ACQ_INTERRUPT (1)\r
+\r
+/** @} Common_Parameters_Options */\r
+\r
+//==============================================================================\r
+// Acquisition limits\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits\r
+ * @{ */\r
+\r
+/** Minimum acquisition measurement (range=0..65535)\r
+ - This is the minimum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is below this value.\r
+*/\r
+#define TSLPRM_ACQ_MIN (50)\r
+\r
+/** Maximum acquisition measurement (range=0..65535)\r
+ - This is the maximum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is above this value.\r
+*/\r
+#define TSLPRM_ACQ_MAX (4000)\r
+\r
+/** @} Common_Parameters_Acquisition_Limits */\r
+\r
+//==============================================================================\r
+// Calibration\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Calibration 04 - Calibration\r
+ * @{ */\r
+\r
+/** Number of calibration samples (range=4, 8, 16)\r
+ - Low value = faster calibration but less precision.\r
+ - High value = slower calibration but more precision.\r
+*/\r
+#define TSLPRM_CALIB_SAMPLES (8)\r
+\r
+/** Delay in measurement samples before starting the calibration (range=0..40)\r
+ - This is usefull if a noise filter is used.\r
+ - Write 0 to disable the delay.\r
+*/\r
+#define TSLPRM_CALIB_DELAY (10)\r
+\r
+/** @} Common_Parameters_Calibration */\r
+\r
+//==============================================================================\r
+// Thresholds for TouchKey sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors\r
+ * @{ */\r
+\r
+/** TouchKeys Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_PROX_IN_TH (15)\r
+\r
+/** TouchKeys Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_PROX_OUT_TH (5)\r
+\r
+/** TouchKeys Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_DETECT_IN_TH (50)\r
+\r
+/** TouchKeys Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_DETECT_OUT_TH (40)\r
+\r
+/** TouchKeys re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_CALIB_TH (20)\r
+\r
+/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)\r
+ This multiplier coefficient is applied on Detect thresholds only.\r
+ - 0: feature disabled\r
+ - 1: thresholds x 2\r
+ - 2: thresholds x 4\r
+ - 3: thresholds x 8\r
+ - 4: thresholds x 16\r
+*/\r
+#define TSLPRM_COEFF_TH (1)\r
+\r
+/** @} Common_Parameters_TouchKey_Thresholds */\r
+\r
+//==============================================================================\r
+// Thresholds for Linear and Rotary sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors\r
+ * @{ */\r
+\r
+/** Linear/Rotary Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_PROX_IN_TH (15)\r
+\r
+/** Linear/Rotary Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_PROX_OUT_TH (5)\r
+\r
+/** Linear/Rotary Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_DETECT_IN_TH (50)\r
+\r
+/** Linear/Rotary Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_DETECT_OUT_TH (30)\r
+\r
+/** Linear/Rotary re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+ - A low absolute value will result in a higher sensitivity and thus some spurious\r
+ recalibration may be issued.\r
+*/\r
+#define TSLPRM_LINROT_CALIB_TH (20)\r
+\r
+/** Linear/Rotary Delta normalization (0=No, 1=Yes)\r
+ - When this parameter is set, a coefficient is applied on all Delta of all sensors\r
+ in order to normalize them and to improve the position calculation.\r
+ - These coefficients must be defined in a constant table in the application (see Library examples).\r
+ - The MSB is the coefficient integer part, the LSB is the coefficient real part.\r
+ - Examples:\r
+ - To apply a factor 1.10:\r
+ 0x01 to the MSB\r
+ 0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)\r
+ - To apply a factor 0.90:\r
+ 0x00 to the MSB\r
+ 0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)\r
+ - To apply no factor:\r
+ 0x01 to the MSB\r
+ 0x00 to the LSB\r
+*/\r
+#define TSLPRM_LINROT_USE_NORMDELTA (1)\r
+\r
+/** @} Common_Parameters_LinRot_Thresholds */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors used\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used\r
+ * @{ */\r
+\r
+/** Select which Linear and Rotary sensors you use in your application.\r
+ - 0 = Not Used\r
+ - 1 = Used\r
+\r
+ LIN = Linear sensor\r
+ ROT = Rotary sensor\r
+ M1 = Mono electrodes design with 0/255 position at extremities of the sensor\r
+ M2 = Mono electrodes design\r
+ H = Half-ended electrodes design\r
+ D = Dual electrodes design\r
+*/\r
+#define TSLPRM_USE_3CH_LIN_M1 (1)\r
+#define TSLPRM_USE_3CH_LIN_M2 (1)\r
+#define TSLPRM_USE_3CH_LIN_H (1)\r
+#define TSLPRM_USE_3CH_ROT_M (1)\r
+\r
+#define TSLPRM_USE_4CH_LIN_M1 (1)\r
+#define TSLPRM_USE_4CH_LIN_M2 (1)\r
+#define TSLPRM_USE_4CH_LIN_H (1)\r
+#define TSLPRM_USE_4CH_ROT_M (1)\r
+\r
+#define TSLPRM_USE_5CH_LIN_M1 (1)\r
+#define TSLPRM_USE_5CH_LIN_M2 (1)\r
+#define TSLPRM_USE_5CH_LIN_H (1)\r
+#define TSLPRM_USE_5CH_ROT_M (1)\r
+#define TSLPRM_USE_5CH_ROT_D (1)\r
+\r
+#define TSLPRM_USE_6CH_LIN_M1 (1)\r
+#define TSLPRM_USE_6CH_LIN_M2 (1)\r
+#define TSLPRM_USE_6CH_LIN_H (1)\r
+#define TSLPRM_USE_6CH_ROT_M (1)\r
+\r
+/** @} Common_Parameters_LinRot_used */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors position\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position\r
+ * @{ */\r
+\r
+/** Position resolution in number of bits (range=1..8)\r
+ - A Low value will result in a low resolution and will be less subject to noise.\r
+ - A High value will result in a high resolution and will be more subject to noise.\r
+*/\r
+#define TSLPRM_LINROT_RESOLUTION (7)\r
+\r
+/** Direction change threshold in position unit (range=0..255)\r
+ - Defines the default threshold used during the change direction process.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_POS (10)\r
+\r
+/** Direction change debounce (range=0..63)\r
+ - Defines the default integrator counter used during the change direction process.\r
+ - This counter is decremented when the same change in the position is detected and the direction will\r
+ change after this counter reaches zero.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_DEB (1)\r
+\r
+/** @} Common_Parameters_LinRot_Position */\r
+\r
+//==============================================================================\r
+// Debounce counters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Debounce 09 - Debounce counters\r
+ * @{ */\r
+\r
+/** Proximity state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_PROX (3)\r
+\r
+/** Detect state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_DETECT (3)\r
+\r
+/** Release state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the end-detection but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_RELEASE (3)\r
+\r
+/** Re-calibration state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the recalibration but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_CALIB (3)\r
+\r
+/** Error state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity to enter in error state.\r
+ - A High value will result in a lower sensitivity to enter in error state.\r
+*/\r
+#define TSLPRM_DEBOUNCE_ERROR (3)\r
+\r
+/** @} Common_Parameters_Debounce */\r
+\r
+//==============================================================================\r
+// Environment Change System (ECS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_ECS 10 - ECS\r
+ * @{ */\r
+\r
+/** Environment Change System Slow K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_SLOW (5)\r
+\r
+/** Environment Change System Fast K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_FAST (40)\r
+\r
+/** Environment Change System delay in msec (range=0..5000)\r
+ - The ECS will be started after this delay and when all sensors are in Release state.\r
+*/\r
+#define TSLPRM_ECS_DELAY (500)\r
+\r
+/** @} Common_Parameters_ECS */\r
+\r
+//==============================================================================\r
+// Detection Time Out (DTO)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DTO 11 - DTO\r
+ * @{ */\r
+\r
+/** Detection Time Out delay in seconds (range=0..63)\r
+ - Value 0: DTO processing not compiled in the code (to gain size if not used).\r
+ - Value 1: Default time out infinite.\r
+ - Value between 2 and 63: Default time out between value n-1 and n.\r
+ - Examples:\r
+ - With a DTO equal to 2, the time out is between 1s and 2s.\r
+ - With a DTO equal to 63, the time out is between 62s and 63s.\r
+\r
+@note The DTO can be changed in run-time by the application only if the\r
+ default value is between 1 and 63.\r
+*/\r
+#define TSLPRM_DTO (5)\r
+\r
+/** @} Common_Parameters_DTO */\r
+\r
+//==============================================================================\r
+// Detection Exclusion System (DXS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DXS 12 - DXS\r
+ * @{ */\r
+\r
+/** Detection Exclusion System (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_DXS (1)\r
+\r
+/** @} Common_Parameters_DXS */\r
+\r
+//==============================================================================\r
+// Miscellaneous parameters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Misc 13 - Miscellaneous\r
+ * @{ */\r
+\r
+/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)\r
+ - Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms\r
+*/\r
+#define TSLPRM_TICK_FREQ (1000)\r
+\r
+/** @} Common_Parameters_Misc */\r
+\r
+/** @} Common_Parameters */\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// DO NOT MODIFY THE LINES BELOW!!!\r
+#define STM8TL53C4 (0)\r
+#define STM8TL53G4 (1)\r
+#define STM8TL53F4 (2)\r
+#define STM8TL52G4 (3)\r
+#define STM8TL52F4 (4)\r
+\r
+/** @defgroup STM8TL5x_Parameters STM8TL5x Parameters\r
+ * @{ */\r
+\r
+//==============================================================================\r
+// Device selection\r
+//==============================================================================\r
+\r
+/** @defgroup STM8TL5x_Parameters_Device_Selection 01 - Device Selection\r
+ * @{ */\r
+\r
+/** STM8TL5x device selection (range=0..4)\r
+ - Select a MCU in the above list\r
+*/\r
+#define TSLPRM_MCU STM8TL53C4\r
+\r
+/** @} STM8TL5x_Parameters_Device_Selection */\r
+\r
+//==============================================================================\r
+// Reference adjustment\r
+//==============================================================================\r
+\r
+/** @defgroup STM8TL5x_Parameters_Reference_Adjustment 02 - Reference adjustment\r
+ * @{ */\r
+\r
+/** Used to calibrate the EPCC to get the Reference closed to this value (range=100..2000)\r
+ - The range values are recommended values.\r
+ - The higher the Reference, the higher the sensitivity\r
+*/\r
+#define TSLPRM_KEY_TARGET_REFERENCE (500)\r
+\r
+/** Used to calibrate the EPCC (range=1..TSLPRM_KEY_TARGET_REFERENCE)\r
+*/\r
+#define TSLPRM_KEY_TARGET_REFERENCE_ERROR (25)\r
+\r
+/** Number of iteration after the dichotomy to fine tune the EPCC value (range=3..5)\r
+*/\r
+#define TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION (3)\r
+\r
+/** Used to calibrate the CS (range=1,2,4,8)\r
+*/\r
+#define TSLPRM_KEY_TARGET_ATTENUATION (4)\r
+\r
+/** Below (TSLPRM_KEY_TARGET_REFERENCE - TSLPRM_TOUCHKEY_REFERENCE_RANGE) the EPCC is updated for the TKeys (range=1..TSLPRM_KEY_TARGET_REFERENCE)\r
+*/\r
+#define TSLPRM_TOUCHKEY_REFERENCE_RANGE (75)\r
+\r
+/** Below (TSLPRM_KEY_TARGET_REFERENCE - TSLPRM_LINROT_REFERENCE_RANGE) the EPCC is updated for the Linear/Rotary (range=1..TSLPRM_KEY_TARGET_REFERENCE)\r
+*/\r
+#define TSLPRM_LINROT_REFERENCE_RANGE (75)\r
+\r
+/** @} STM8TL5x_Parameters_Reference_Adjustment */\r
+\r
+//==============================================================================\r
+// PXS Clock\r
+//==============================================================================\r
+\r
+/** @defgroup STM8TL5x_Parameters_PXS_Clock 03 - PXS Clock\r
+ - These parameters define the acquisition clock settings.\r
+ * @{ */\r
+\r
+/** Acquisition frequency (values are 16000, 8000, 4000, 2000, 1000, 500, 250 or 125)\r
+*/\r
+#define TSLPRM_PXS_HSI (16000)\r
+\r
+/** Up phase length (range=1..7)\r
+*/\r
+#define TSLPRM_PXS_UP_LENGTH (1)\r
+\r
+/** Pass phase length (range=1..7)\r
+*/\r
+#define TSLPRM_PXS_PASS_LENGTH (1)\r
+\r
+/** @} STM8TL5x_Parameters_PXS_Clock */\r
+\r
+//==============================================================================\r
+// PXS Synchro\r
+//==============================================================================\r
+\r
+/** @defgroup STM8TL5x_Parameters_PXS_Synchro 04 - PXS Synchro\r
+ * @{ */\r
+\r
+/** Acquisition synchronized with SYNCHRO pin (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_PXS_SYNCHRONIZE (1)\r
+\r
+/** Synchronization edge (0=Fall, 1=Rise)\r
+*/\r
+#define TSLPRM_PXS_SYNCHRO_EDGE (1)\r
+\r
+/** @} STM8TL5x_Parameters_PXS_Synchro */\r
+\r
+//==============================================================================\r
+// PXS Miscellaneous\r
+//==============================================================================\r
+\r
+/** @defgroup STM8TL5x_Parameters_PXS_Miscellaneous 05 - PXS Miscellaneous\r
+ * @{ */\r
+\r
+/** Low power mode between acquisition (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_PXS_LOW_POWER_MODE (1)\r
+\r
+/** RF detection (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_PXS_RF_DETECTION (1)\r
+\r
+/** Transmitter inactive state (0=Grounded, 1=Floating)\r
+*/\r
+#define TSLPRM_PXS_INACTIVE_TX (1)\r
+\r
+/** Receiver inactive state (0=Grounded, 1=Floating)\r
+*/\r
+#define TSLPRM_PXS_INACTIVE_RX (1)\r
+\r
+/** Charge/Discharge cycle behaviour after VTHR is reached (0=stop, 1=continue)\r
+*/\r
+#define TSLPRM_PXS_RX_COUPLING (1)\r
+\r
+/** Stabilization time (values are LONG_STAB, MEDIUM_STAB, SHORT_STAB)\r
+*/\r
+#define TSLPRM_PXS_STAB LONG_STAB\r
+\r
+/** Bias (values are HIGH_BIAS, MEDIUM_BIAS, LOW_BIAS, VERY_LOW_BIAS)\r
+*/\r
+#define TSLPRM_PXS_BIAS HIGH_BIAS\r
+\r
+/** Index maximum of Rx channels ("N" of RxN)\r
+ - This value must not exceed 9 with STM8TL53C4 and 7 with STM8TL53G4\r
+*/\r
+#define TSLPRM_HIGH_CHANNEL_NB (9)\r
+\r
+/** @} STM8TL5x_Parameters_PXS_Miscellaneous */\r
+\r
+/** @} STM8TL5x_Parameters */\r
+\r
+// DO NOT REMOVE !!!\r
+#include "tsl_check_config.h"\r
+\r
+#endif /* __TSL_CONF_STM8TL5X_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_H\r
+#define __TSL_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq.h"\r
+#include "tsl_time.h"\r
+#include "tsl_touchkey.h"\r
+#include "tsl_linrot.h"\r
+#include "tsl_object.h"\r
+#include "tsl_dxs.h"\r
+#include "tsl_ecs.h"\r
+#include "tsl_filter.h"\r
+#include "tsl_globals.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported variables --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+TSL_Status_enum_T TSL_Init(CONST TSL_Bank_T *bank);\r
+\r
+#endif /* __TSL_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_acq.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_ACQ_H\r
+#define __TSL_ACQ_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+// Check the device selection.\r
+// It must be defined in the toolchain compiler preprocessor.\r
+// The same name as in the Standard Peripheral Library is used.\r
+#if !defined(STM8TL5X) &&\\r
+ !defined(STM32F0XX) &&\\r
+ !defined(STM32F30X) &&\\r
+ !defined(STM32F37X) &&\\r
+ !defined(STM32L1XX_HD) &&\\r
+ !defined(STM32L1XX_MD) &&\\r
+ !defined(STM32L1XX_MDP)\r
+#error "Device family not declared in the toolchain compiler preprocessor."\r
+#endif\r
+\r
+#if defined(STM8TL5X)\r
+#include "tsl_acq_stm8tl5x.h"\r
+#endif\r
+\r
+#if defined(STM32F0XX)\r
+#include "tsl_acq_stm32f0xx.h"\r
+#endif\r
+\r
+#if defined(STM32F30X) || defined(STM32F37X)\r
+#include "tsl_acq_stm32f3xx.h"\r
+#endif\r
+\r
+#if defined(STM32L1XX_HD)\r
+#if defined(TSLPRM_STM32L1XX_SW_ACQ)\r
+#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition\r
+#else\r
+#include "tsl_acq_stm32l1xx_hw.h" // Hardware acquisition with Timers (default)\r
+#endif\r
+#endif\r
+\r
+#if defined(STM32L1XX_MD)\r
+#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition only\r
+#endif\r
+\r
+#if defined(STM32L1XX_MDP)\r
+#if defined(TSLPRM_STM32L1XX_SW_ACQ)\r
+#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition\r
+#else\r
+#include "tsl_acq_stm32l1xx_hw.h" // Hardware acquisition with Timers (default)\r
+#endif\r
+#endif\r
+\r
+/* Defines -------------------------------------------------------------------*/\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+// Filter functions\r
+typedef TSL_tMeas_T(* TSL_pFuncMeasFilter_T)(TSL_tMeas_T, TSL_tMeas_T); /**< Pointer to the Measure filter function */\r
+typedef TSL_tDelta_T(* TSL_pFuncDeltaFilter_T)(TSL_tDelta_T); /**< Pointer to the Delta filter function */\r
+\r
+/** Structure containing all data of a Zone.\r
+ * A Zone is a set of Banks.\r
+ * Variables of this structure type can be placed in RAM or ROM.\r
+ */\r
+typedef struct\r
+{\r
+ // Common to all acquisitions\r
+ TSL_tIndex_T *BankIndex; /**< Pointer to an array of bank indexes */\r
+ TSL_pFuncDeltaFilter_T *dFilter; /**< Pointer to a Delta filter function */\r
+ TSL_tNb_T NbBanks; /**< Number of banks in the zone */\r
+}\r
+TSL_Zone_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+TSL_Status_enum_T TSL_acq_ZoneConfig(CONST TSL_Zone_T *zone, TSL_tIndex_T idx_bk);\r
+TSL_Status_enum_T TSL_acq_BankGetResult(TSL_tIndex_T idx_bk, TSL_pFuncMeasFilter_T mfilter, TSL_pFuncDeltaFilter_T dfilter);\r
+TSL_Status_enum_T TSL_acq_BankCalibrate(TSL_tIndex_T bank);\r
+void TSL_acq_BankClearData(TSL_tIndex_T bank);\r
+\r
+#endif /* __TSL_ACQ_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm32f0xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions prototypes that manage the TSC\r
+ * acquisition on STM32F0x products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_ACQ_STM32F0XX_H\r
+#define __TSL_ACQ_STM32F0XX_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+#include "tsl_conf_stm32f0xx.h"\r
+#include "tsl_types.h"\r
+\r
+/* Defines -------------------------------------------------------------------*/\r
+\r
+#ifndef CONST\r
+#define CONST const\r
+#endif\r
+\r
+// SysTick enable/disable interrupt macros\r
+#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;}\r
+#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;}\r
+\r
+#define TSL_NB_GROUPS (6) // Only 6 groups on STM32F0xx\r
+\r
+#define TSL_GROUP1 (0x01)\r
+#define TSL_GROUP2 (0x02)\r
+#define TSL_GROUP3 (0x04)\r
+#define TSL_GROUP4 (0x08)\r
+#define TSL_GROUP5 (0x10)\r
+#define TSL_GROUP6 (0x20)\r
+\r
+// GxIOy masks\r
+#define TSL_GROUP1_IO1 (0x00000001)\r
+#define TSL_GROUP1_IO2 (0x00000002)\r
+#define TSL_GROUP1_IO3 (0x00000004)\r
+#define TSL_GROUP1_IO4 (0x00000008)\r
+#define TSL_GROUP2_IO1 (0x00000010)\r
+#define TSL_GROUP2_IO2 (0x00000020)\r
+#define TSL_GROUP2_IO3 (0x00000040)\r
+#define TSL_GROUP2_IO4 (0x00000080)\r
+#define TSL_GROUP3_IO1 (0x00000100)\r
+#define TSL_GROUP3_IO2 (0x00000200)\r
+#define TSL_GROUP3_IO3 (0x00000400)\r
+#define TSL_GROUP3_IO4 (0x00000800)\r
+#define TSL_GROUP4_IO1 (0x00001000)\r
+#define TSL_GROUP4_IO2 (0x00002000)\r
+#define TSL_GROUP4_IO3 (0x00004000)\r
+#define TSL_GROUP4_IO4 (0x00008000)\r
+#define TSL_GROUP5_IO1 (0x00010000)\r
+#define TSL_GROUP5_IO2 (0x00020000)\r
+#define TSL_GROUP5_IO3 (0x00040000)\r
+#define TSL_GROUP5_IO4 (0x00080000)\r
+#define TSL_GROUP6_IO1 (0x00100000)\r
+#define TSL_GROUP6_IO2 (0x00200000)\r
+#define TSL_GROUP6_IO3 (0x00400000)\r
+#define TSL_GROUP6_IO4 (0x00800000)\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+// For all devices/acquisitions\r
+\r
+typedef uint16_t TSL_tMeas_T; /**< Measurement */\r
+typedef uint16_t TSL_tRef_T; /**< Reference */\r
+typedef int16_t TSL_tDelta_T; /**< Delta */\r
+\r
+typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */\r
+typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */\r
+\r
+typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */\r
+typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */\r
+\r
+typedef uint8_t TSL_tIndex_T; /**< Generic index */\r
+typedef uint16_t TSL_tNb_T; /**< Generic number */\r
+typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */\r
+\r
+typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */\r
+\r
+typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */\r
+typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */\r
+\r
+typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */\r
+typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */\r
+\r
+//------------------------------------------------------------------------------\r
+// Channel\r
+//------------------------------------------------------------------------------\r
+\r
+/** Channel destination index\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndexDest_T IdxDest; /**< Index in the Channel data array */\r
+} TSL_ChannelDest_T;\r
+\r
+/** Channel Source and Configuration\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndexSrc_T IdxSrc; /**< Index of TSC->IOGXCR[] registers */\r
+ // For stm32f0x TSC acquisition only\r
+ uint32_t msk_IOCCR_channel; /**< Mask of the Channel IO (electrodes ONLY) */\r
+ uint32_t msk_IOGCSR_group; /**< Mask of the Group used (electrodes ONLY) */\r
+} TSL_ChannelSrc_T;\r
+\r
+/** Channel flags\r
+ */\r
+typedef struct\r
+{\r
+ unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */\r
+ unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */\r
+ unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */\r
+} TSL_ChannelFlags_T;\r
+\r
+/** Channel Data\r
+ */\r
+typedef struct\r
+{\r
+ TSL_ChannelFlags_T Flags; /**< Flags */\r
+ TSL_tRef_T Ref; /**< Reference */\r
+ TSL_tRefRest_T RefRest; /**< Reference rest for ECS */\r
+ TSL_tDelta_T Delta; /**< Delta */\r
+#if TSLPRM_USE_MEAS > 0\r
+ TSL_tMeas_T Meas; /**< Hold the last acquisition measure */\r
+#endif\r
+} TSL_ChannelData_T;\r
+\r
+//------------------------------------------------------------------------------\r
+// Bank\r
+//------------------------------------------------------------------------------\r
+\r
+/** Bank\r
+ */\r
+typedef struct\r
+{\r
+ // Common to all acquisitions\r
+ CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */\r
+ CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */\r
+ TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */\r
+ TSL_tNb_T NbChannels; /**< Number of channels in the bank */\r
+ // For STM32F0x TSC acquisition only\r
+ uint32_t msk_IOCCR_channels; /**< Mask of all channel IOs (electrodes AND shields) */\r
+ uint32_t msk_IOGCSR_groups; /**< Mask of all groups used (electrodes ONLY) */\r
+} TSL_Bank_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+TSL_Status_enum_T TSL_acq_Init(void);\r
+void TSL_acq_InitGPIOs(void);\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);\r
+void TSL_acq_BankStartAcq(void);\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void);\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndexSrc_T index);\r
+TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas);\r
+TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta);\r
+\r
+#endif /* __TSL_ACQ_STM32F0XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm32f3xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions prototypes that manage the TSC\r
+ * acquisition on STM32F3xx products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_ACQ_STM32F3XX_H\r
+#define __TSL_ACQ_STM32F3XX_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#if defined(STM32F30X)\r
+#include "stm32f30x.h"\r
+#endif\r
+#if defined(STM32F37X)\r
+#include "stm32f37x.h"\r
+#endif\r
+#include "tsl_conf_stm32f3xx.h"\r
+#include "tsl_types.h"\r
+\r
+/* Defines -------------------------------------------------------------------*/\r
+\r
+#ifndef CONST\r
+#define CONST const\r
+#endif\r
+\r
+// SysTick enable/disable interrupt macros\r
+#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;}\r
+#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;}\r
+\r
+#define TSL_NB_GROUPS (8) // Number of groups available on STM32F3xx devices\r
+\r
+#define TSL_GROUP1 (0x01)\r
+#define TSL_GROUP2 (0x02)\r
+#define TSL_GROUP3 (0x04)\r
+#define TSL_GROUP4 (0x08)\r
+#define TSL_GROUP5 (0x10)\r
+#define TSL_GROUP6 (0x20)\r
+#define TSL_GROUP7 (0x40)\r
+#define TSL_GROUP8 (0x80)\r
+\r
+// GxIOy masks\r
+#define TSL_GROUP1_IO1 (0x00000001)\r
+#define TSL_GROUP1_IO2 (0x00000002)\r
+#define TSL_GROUP1_IO3 (0x00000004)\r
+#define TSL_GROUP1_IO4 (0x00000008)\r
+#define TSL_GROUP2_IO1 (0x00000010)\r
+#define TSL_GROUP2_IO2 (0x00000020)\r
+#define TSL_GROUP2_IO3 (0x00000040)\r
+#define TSL_GROUP2_IO4 (0x00000080)\r
+#define TSL_GROUP3_IO1 (0x00000100)\r
+#define TSL_GROUP3_IO2 (0x00000200)\r
+#define TSL_GROUP3_IO3 (0x00000400)\r
+#define TSL_GROUP3_IO4 (0x00000800)\r
+#define TSL_GROUP4_IO1 (0x00001000)\r
+#define TSL_GROUP4_IO2 (0x00002000)\r
+#define TSL_GROUP4_IO3 (0x00004000)\r
+#define TSL_GROUP4_IO4 (0x00008000)\r
+#define TSL_GROUP5_IO1 (0x00010000)\r
+#define TSL_GROUP5_IO2 (0x00020000)\r
+#define TSL_GROUP5_IO3 (0x00040000)\r
+#define TSL_GROUP5_IO4 (0x00080000)\r
+#define TSL_GROUP6_IO1 (0x00100000)\r
+#define TSL_GROUP6_IO2 (0x00200000)\r
+#define TSL_GROUP6_IO3 (0x00400000)\r
+#define TSL_GROUP6_IO4 (0x00800000)\r
+#define TSL_GROUP7_IO1 (0x01000000)\r
+#define TSL_GROUP7_IO2 (0x02000000)\r
+#define TSL_GROUP7_IO3 (0x04000000)\r
+#define TSL_GROUP7_IO4 (0x08000000)\r
+#define TSL_GROUP8_IO1 (0x10000000)\r
+#define TSL_GROUP8_IO2 (0x20000000)\r
+#define TSL_GROUP8_IO3 (0x40000000)\r
+#define TSL_GROUP8_IO4 (0x80000000)\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+// For all devices/acquisitions\r
+\r
+typedef uint16_t TSL_tMeas_T; /**< Measurement */\r
+typedef uint16_t TSL_tRef_T; /**< Reference */\r
+typedef int16_t TSL_tDelta_T; /**< Delta */\r
+\r
+typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */\r
+typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */\r
+\r
+typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */\r
+typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */\r
+\r
+typedef uint8_t TSL_tIndex_T; /**< Generic index */\r
+typedef uint16_t TSL_tNb_T; /**< Generic number */\r
+typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */\r
+\r
+typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */\r
+\r
+typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */\r
+typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */\r
+\r
+typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */\r
+typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */\r
+\r
+//------------------------------------------------------------------------------\r
+// Channel\r
+//------------------------------------------------------------------------------\r
+\r
+/** Channel destination index\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndexDest_T IdxDest; /**< Index in the Channel data array */\r
+} TSL_ChannelDest_T;\r
+\r
+/** Channel Source and Configuration\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndexSrc_T IdxSrc; /**< Index of TSC->IOGXCR[] registers */\r
+ // For STM32F3xx TSC acquisition only\r
+ uint32_t msk_IOCCR_channel; /**< Mask of the Channel IO (electrodes ONLY) */\r
+ uint32_t msk_IOGCSR_group; /**< Mask of the Group used (electrodes ONLY) */\r
+} TSL_ChannelSrc_T;\r
+\r
+/** Channel flags\r
+ */\r
+typedef struct\r
+{\r
+ unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */\r
+ unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */\r
+ unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */\r
+} TSL_ChannelFlags_T;\r
+\r
+/** Channel Data\r
+ */\r
+typedef struct\r
+{\r
+ TSL_ChannelFlags_T Flags; /**< Flags */\r
+ TSL_tRef_T Ref; /**< Reference */\r
+ TSL_tRefRest_T RefRest; /**< Reference rest for ECS */\r
+ TSL_tDelta_T Delta; /**< Delta */\r
+#if TSLPRM_USE_MEAS > 0\r
+ TSL_tMeas_T Meas; /**< Hold the last acquisition measure */\r
+#endif\r
+} TSL_ChannelData_T;\r
+\r
+//------------------------------------------------------------------------------\r
+// Bank\r
+//------------------------------------------------------------------------------\r
+\r
+/** Bank\r
+ */\r
+typedef struct\r
+{\r
+ // Common to all acquisitions\r
+ CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */\r
+ CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */\r
+ TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */\r
+ TSL_tNb_T NbChannels; /**< Number of channels in the bank */\r
+ // For STM32F3xx TSC acquisition only\r
+ uint32_t msk_IOCCR_channels; /**< Mask of all channel IOs (electrodes AND shields) */\r
+ uint32_t msk_IOGCSR_groups; /**< Mask of all groups used (electrodes ONLY) */\r
+} TSL_Bank_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+TSL_Status_enum_T TSL_acq_Init(void);\r
+void TSL_acq_InitGPIOs(void);\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);\r
+void TSL_acq_BankStartAcq(void);\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void);\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndexSrc_T index);\r
+TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas);\r
+TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta);\r
+\r
+#endif /* __TSL_ACQ_STM32F3XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm32l1xx_hw.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_acq_stm32l1xx_hw.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_ACQ_STM32L1XX_HW_H\r
+#define __TSL_ACQ_STM32L1XX_HW_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+#include "tsl_conf_stm32l1xx.h"\r
+#include "tsl_types.h"\r
+\r
+/* Defines -------------------------------------------------------------------*/\r
+\r
+#ifndef CONST\r
+#define CONST const\r
+#endif\r
+\r
+// SysTick enable/disable interrupt macros\r
+#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;}\r
+#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;}\r
+\r
+/** Groups list\r
+ */\r
+enum\r
+{\r
+ GR1,\r
+ GR2,\r
+ GR3,\r
+ GR4,\r
+ GR5,\r
+ GR6,\r
+ GR7,\r
+ GR8,\r
+ GR9,\r
+ GR10,\r
+ GR11\r
+};\r
+\r
+/** GPIOs list\r
+ High significant nibble for the IO port (GPIOA:0,...,GPIOG:6)\r
+ Low significant nibble for the IO number (pin0:0,...,pin15:F)\r
+ */\r
+enum\r
+{\r
+ PA0 = 0x00, /**< TSL_GROUP1_IO1 */\r
+ PA1 = 0x01,\r
+ PA2 = 0x02,\r
+ PA3 = 0x03,\r
+ PA6 = 0x06, /**< TSL_GROUP2_IO1 */\r
+ PA7 = 0x07,\r
+ PA8 = 0x08,\r
+ PA9 = 0x09,\r
+ PA10 = 0x0A,\r
+ PA13 = 0x0D, /**< TSL_GROUP5_IO1 */\r
+ PA14 = 0x0E,\r
+ PA15 = 0x0F,\r
+ PB0 = 0x10, /**< TSL_GROUP3_IO1 */\r
+ PB1 = 0x11,\r
+ PB2 = 0x12,\r
+ PB4 = 0x14, /**< TSL_GROUP6_IO1 */\r
+ PB5 = 0x15,\r
+ PB6 = 0x16,\r
+ PB7 = 0x17,\r
+ PB12 = 0x1C, /**< TSL_GROUP7_IO1 */\r
+ PB13 = 0x1D,\r
+ PB14 = 0x1E,\r
+ PB15 = 0x1F,\r
+ PC0 = 0x20, /**< TSL_GROUP8_IO1 */\r
+ PC1 = 0x21,\r
+ PC2 = 0x22,\r
+ PC3 = 0x23,\r
+ PC4 = 0x24,\r
+ PC5 = 0x25,\r
+ PC6 = 0x26,\r
+ PC7 = 0x27,\r
+ PC8 = 0x28,\r
+ PC9 = 0x29,\r
+ PF6 = 0x56, /**< TSL_GROUP11_IO1 */\r
+ PF7 = 0x57,\r
+ PF8 = 0x58,\r
+ PF9 = 0x59,\r
+ PF10 = 0x5A,\r
+ PF11 = 0x5B,\r
+ PF12 = 0x5C,\r
+ PF13 = 0x5D,\r
+ PF14 = 0x5E,\r
+ PF15 = 0x5F,\r
+ PG0 = 0x60, /**< TSL_GROUP2_IO4 */\r
+ PG1 = 0x61,\r
+ PG2 = 0x62,\r
+ PG3 = 0x63,\r
+ PG4 = 0x64\r
+};\r
+\r
+/** GPIOs list:\r
+ High significant nibble for the IO port (GPIOA:0,...,GPIOG:6)\r
+ Low significant nibble for the IO number (pin0:0,...,pin15:F)\r
+ */\r
+enum\r
+{\r
+ TSL_GROUP1_IO1 = 0x00, /**< PA0 */\r
+ TSL_GROUP1_IO2 = 0x01,\r
+ TSL_GROUP1_IO3 = 0x02,\r
+ TSL_GROUP1_IO4 = 0x03,\r
+ TSL_GROUP2_IO1 = 0x06, /**< PA6 */\r
+ TSL_GROUP2_IO2 = 0x07,\r
+ TSL_GROUP4_IO1 = 0x08,\r
+ TSL_GROUP4_IO2 = 0x09,\r
+ TSL_GROUP4_IO3 = 0x0A,\r
+ TSL_GROUP5_IO1 = 0x0D, /**< PA13 */\r
+ TSL_GROUP5_IO2 = 0x0E,\r
+ TSL_GROUP5_IO3 = 0x0F,\r
+ TSL_GROUP3_IO1 = 0x10, /**< PB0 */\r
+ TSL_GROUP3_IO2 = 0x11,\r
+ TSL_GROUP3_IO3 = 0x12,\r
+ TSL_GROUP6_IO1 = 0x14, /**< PB4 */\r
+ TSL_GROUP6_IO2 = 0x15,\r
+ TSL_GROUP6_IO3 = 0x16,\r
+ TSL_GROUP6_IO4 = 0x17,\r
+ TSL_GROUP7_IO1 = 0x1C, /**< PB12 */\r
+ TSL_GROUP7_IO2 = 0x1D,\r
+ TSL_GROUP7_IO3 = 0x1E,\r
+ TSL_GROUP7_IO4 = 0x1F,\r
+ TSL_GROUP8_IO1 = 0x20, /**< PC0 */\r
+ TSL_GROUP8_IO2 = 0x21,\r
+ TSL_GROUP8_IO3 = 0x22,\r
+ TSL_GROUP8_IO4 = 0x23,\r
+ TSL_GROUP9_IO1 = 0x24,\r
+ TSL_GROUP9_IO2 = 0x25,\r
+ TSL_GROUP10_IO1 = 0x26,\r
+ TSL_GROUP10_IO2 = 0x27,\r
+ TSL_GROUP10_IO3 = 0x28,\r
+ TSL_GROUP10_IO4 = 0x29,\r
+ TSL_GROUP11_IO1 = 0x56, /**< PF6 */\r
+ TSL_GROUP11_IO2 = 0x57,\r
+ TSL_GROUP11_IO3 = 0x58,\r
+ TSL_GROUP11_IO4 = 0x59,\r
+ TSL_GROUP11_IO5 = 0x5A,\r
+ TSL_GROUP3_IO4 = 0x5B,\r
+ TSL_GROUP3_IO5 = 0x5C,\r
+ TSL_GROUP9_IO3 = 0x5D,\r
+ TSL_GROUP9_IO4 = 0x5E,\r
+ TSL_GROUP2_IO3 = 0x5F,\r
+ TSL_GROUP2_IO4 = 0x60, /**< PG0 */\r
+ TSL_GROUP2_IO5 = 0x61,\r
+ TSL_GROUP7_IO5 = 0x62,\r
+ TSL_GROUP7_IO6 = 0x63,\r
+ TSL_GROUP7_IO7 = 0x64\r
+};\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ // RI\r
+ __IO uint32_t ICR;\r
+ __IO uint32_t ASCR1;\r
+ __IO uint32_t ASCR2;\r
+ __IO uint32_t HYSCR1;\r
+ __IO uint32_t HYSCR2;\r
+ __IO uint32_t HYSCR3;\r
+ __IO uint32_t HYSCR4;\r
+ // CP\r
+ __IO uint32_t ASMR1;\r
+ __IO uint32_t CMR1;\r
+ __IO uint32_t CICR1;\r
+ __IO uint32_t ASMR2;\r
+ __IO uint32_t CMR2;\r
+ __IO uint32_t CICR2;\r
+ __IO uint32_t ASMR3;\r
+ __IO uint32_t CMR3;\r
+ __IO uint32_t CICR3;\r
+ __IO uint32_t ASMR4;\r
+ __IO uint32_t CMR4;\r
+ __IO uint32_t CICR4;\r
+ __IO uint32_t ASMR5;\r
+ __IO uint32_t CMR5;\r
+ __IO uint32_t CICR5;\r
+} CPRI_TypeDef;\r
+\r
+// For all devices/acquisitions\r
+\r
+typedef uint16_t TSL_tMeas_T; /**< Measurement */\r
+typedef uint16_t TSL_tRef_T; /**< Reference */\r
+typedef int16_t TSL_tDelta_T; /**< Delta */\r
+\r
+typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */\r
+typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */\r
+\r
+typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */\r
+typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */\r
+\r
+typedef uint8_t TSL_tIndex_T; /**< Generic index */\r
+typedef uint16_t TSL_tNb_T; /**< Generic number */\r
+typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */\r
+\r
+typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */\r
+\r
+typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */\r
+typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */\r
+\r
+typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */\r
+typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */\r
+\r
+//------------------------------------------------------------------------------\r
+// Channel\r
+//------------------------------------------------------------------------------\r
+\r
+typedef uint8_t TSL_Conf_t;\r
+\r
+/** Channel destination index\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndex_T IdxDest; /**< Index in the Channel data array */\r
+} TSL_ChannelDest_T;\r
+\r
+/** Channel Source and Configuration\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndex_T IdxSrc; /**< Index of source value */\r
+ // For stm32l1x acquisition only\r
+ TSL_Conf_t t_sample; /**< Indicates which GPIO.n is used for the sample */\r
+ TSL_Conf_t t_channel; /**< Indicates which GPIO.n is used for the channel */\r
+} TSL_ChannelSrc_T;\r
+\r
+/** Channel flags\r
+ */\r
+typedef struct\r
+{\r
+ unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */\r
+ unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */\r
+ unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */\r
+} TSL_ChannelFlags_T;\r
+\r
+/** Channel Data\r
+ */\r
+typedef struct\r
+{\r
+ TSL_ChannelFlags_T Flags; /**< Flags */\r
+ TSL_tRef_T Ref; /**< Reference */\r
+ TSL_tRefRest_T RefRest; /**< Reference rest for ECS */\r
+ TSL_tDelta_T Delta; /**< Delta */\r
+#if TSLPRM_USE_MEAS > 0\r
+ TSL_tMeas_T Meas; /**< Hold the last acquisition measure */\r
+#endif\r
+} TSL_ChannelData_T;\r
+\r
+//------------------------------------------------------------------------------\r
+// Bank\r
+//------------------------------------------------------------------------------\r
+\r
+/** Bank\r
+ */\r
+typedef struct\r
+{\r
+ // Common to all acquisitions\r
+ CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */\r
+ CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */\r
+ TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */\r
+ TSL_tNb_T NbChannels; /**< Number of channels in the bank */\r
+ // For stm32l1x acquisition only\r
+ TSL_Conf_t shield_sample; /**< Indicates which GPIO.n is used for the shield sample */\r
+ TSL_Conf_t shield_channel; /**< Indicates which GPIO.n is used for the shield channel */\r
+} TSL_Bank_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+#define CPRI_BASE (APB1PERIPH_BASE + 0x7C04)\r
+#define CPRI ((CPRI_TypeDef *) CPRI_BASE)\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+TSL_Status_enum_T TSL_acq_Init(void);\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);\r
+void TSL_acq_BankStartAcq(void);\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void);\r
+void TSL_acq_ProcessIT(void);\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index);\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);\r
+TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas);\r
+TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta);\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);\r
+\r
+#endif // __TSL_ACQ_STM32L1XX_HW_H\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm32l1xx_sw.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_acq_stm32l1xx_sw.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_ACQ_STM32L1XX_SW_H\r
+#define __TSL_ACQ_STM32L1XX_SW_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+#include "tsl_conf_stm32l1xx.h"\r
+#include "tsl_types.h"\r
+\r
+/* Defines -------------------------------------------------------------------*/\r
+\r
+#ifndef CONST\r
+#define CONST const\r
+#endif\r
+\r
+// SysTick enable/disable interrupt macros\r
+#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;}\r
+#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;}\r
+\r
+enum\r
+{\r
+ GR1,\r
+ GR2,\r
+ GR3,\r
+ GR4,\r
+ GR5,\r
+ GR6,\r
+ GR7,\r
+ GR8,\r
+ GR9,\r
+ GR10,\r
+ GR11\r
+};\r
+\r
+enum\r
+{\r
+ TSL_BANK_GPIOA = 0,\r
+ TSL_BANK_GPIOB,\r
+ TSL_BANK_GPIOC,\r
+ TSL_BANK_GPIOE,\r
+ TSL_BANK_GPIOF,\r
+ TSL_BANK_GPIOG\r
+};\r
+\r
+/** GPIOs list\r
+ High significant nibble for the IO port (GPIOA:0,...,GPIOG:6)\r
+ Low significant nibble for the IO number (pin0:0,...,pin15:F)\r
+ */\r
+enum\r
+{\r
+ PA0 = 0x00, /**< TSL_GROUP1_IO1 */\r
+ PA1 = 0x01,\r
+ PA2 = 0x02,\r
+ PA3 = 0x03,\r
+ PA6 = 0x06, /**< TSL_GROUP2_IO1 */\r
+ PA7 = 0x07,\r
+ PA8 = 0x08,\r
+ PA9 = 0x09,\r
+ PA10 = 0x0A,\r
+ PA13 = 0x0D, /**< TSL_GROUP5_IO1 */\r
+ PA14 = 0x0E,\r
+ PA15 = 0x0F,\r
+ PB0 = 0x10, /**< TSL_GROUP3_IO1 */\r
+ PB1 = 0x11,\r
+ PB2 = 0x12,\r
+ PB4 = 0x14, /**< TSL_GROUP6_IO1 */\r
+ PB5 = 0x15,\r
+ PB6 = 0x16,\r
+ PB7 = 0x17,\r
+ PB12 = 0x1C, /**< TSL_GROUP7_IO1 */\r
+ PB13 = 0x1D,\r
+ PB14 = 0x1E,\r
+ PB15 = 0x1F,\r
+ PC0 = 0x20, /**< TSL_GROUP8_IO1 */\r
+ PC1 = 0x21,\r
+ PC2 = 0x22,\r
+ PC3 = 0x23,\r
+ PC4 = 0x24,\r
+ PC5 = 0x25,\r
+ PC6 = 0x26,\r
+ PC7 = 0x27,\r
+ PC8 = 0x28,\r
+ PC9 = 0x29,\r
+ PF6 = 0x56, /**< TSL_GROUP11_IO1 */\r
+ PF7 = 0x57,\r
+ PF8 = 0x58,\r
+ PF9 = 0x59,\r
+ PF10 = 0x5A,\r
+ PF11 = 0x5B,\r
+ PF12 = 0x5C,\r
+ PF13 = 0x5D,\r
+ PF14 = 0x5E,\r
+ PF15 = 0x5F,\r
+ PG0 = 0x60, /**< TSL_GROUP2_IO4 */\r
+ PG1 = 0x61,\r
+ PG2 = 0x62,\r
+ PG3 = 0x63,\r
+ PG4 = 0x64\r
+};\r
+\r
+/** GPIOs list:\r
+ - High significant nibble for the IO port (GPIOA:0,...,GPIOG:6)\r
+ - Low significant nibble for the IO number (pin0:0,...,pin15:F)\r
+ */\r
+enum\r
+{\r
+ TSL_GROUP1_IO1 = 0x00, /**< PA0 */\r
+ TSL_GROUP1_IO2 = 0x01,\r
+ TSL_GROUP1_IO3 = 0x02,\r
+ TSL_GROUP1_IO4 = 0x03,\r
+ TSL_GROUP2_IO1 = 0x06, /**< PA6 */\r
+ TSL_GROUP2_IO2 = 0x07,\r
+ TSL_GROUP4_IO1 = 0x08,\r
+ TSL_GROUP4_IO2 = 0x09,\r
+ TSL_GROUP4_IO3 = 0x0A,\r
+ TSL_GROUP5_IO1 = 0x0D, /**< PA13 */\r
+ TSL_GROUP5_IO2 = 0x0E,\r
+ TSL_GROUP5_IO3 = 0x0F,\r
+ TSL_GROUP3_IO1 = 0x10, /**< PB0 */\r
+ TSL_GROUP3_IO2 = 0x11,\r
+ TSL_GROUP3_IO3 = 0x12,\r
+ TSL_GROUP6_IO1 = 0x14, /**< PB4 */\r
+ TSL_GROUP6_IO2 = 0x15,\r
+ TSL_GROUP6_IO3 = 0x16,\r
+ TSL_GROUP6_IO4 = 0x17,\r
+ TSL_GROUP7_IO1 = 0x1C, /**< PB12 */\r
+ TSL_GROUP7_IO2 = 0x1D,\r
+ TSL_GROUP7_IO3 = 0x1E,\r
+ TSL_GROUP7_IO4 = 0x1F,\r
+ TSL_GROUP8_IO1 = 0x20, /**< PC0 */\r
+ TSL_GROUP8_IO2 = 0x21,\r
+ TSL_GROUP8_IO3 = 0x22,\r
+ TSL_GROUP8_IO4 = 0x23,\r
+ TSL_GROUP9_IO1 = 0x24,\r
+ TSL_GROUP9_IO2 = 0x25,\r
+ TSL_GROUP10_IO1 = 0x26,\r
+ TSL_GROUP10_IO2 = 0x27,\r
+ TSL_GROUP10_IO3 = 0x28,\r
+ TSL_GROUP10_IO4 = 0x29,\r
+ TSL_GROUP11_IO1 = 0x56, /**< PF6 */\r
+ TSL_GROUP11_IO2 = 0x57,\r
+ TSL_GROUP11_IO3 = 0x58,\r
+ TSL_GROUP11_IO4 = 0x59,\r
+ TSL_GROUP11_IO5 = 0x5A,\r
+ TSL_GROUP3_IO4 = 0x5B,\r
+ TSL_GROUP3_IO5 = 0x5C,\r
+ TSL_GROUP9_IO3 = 0x5D,\r
+ TSL_GROUP9_IO4 = 0x5E,\r
+ TSL_GROUP2_IO3 = 0x5F,\r
+ TSL_GROUP2_IO4 = 0x60, /**< PG0 */\r
+ TSL_GROUP2_IO5 = 0x61,\r
+ TSL_GROUP7_IO5 = 0x62,\r
+ TSL_GROUP7_IO6 = 0x63,\r
+ TSL_GROUP7_IO7 = 0x64\r
+};\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+// For all devices/acquisitions\r
+\r
+typedef uint16_t TSL_tMeas_T; /**< Measurement */\r
+typedef uint16_t TSL_tRef_T; /**< Reference */\r
+typedef int16_t TSL_tDelta_T; /**< Delta */\r
+\r
+typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */\r
+typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */\r
+\r
+typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */\r
+typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */\r
+\r
+typedef uint8_t TSL_tIndex_T; /**< Generic index */\r
+typedef uint16_t TSL_tNb_T; /**< Generic number */\r
+typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */\r
+\r
+typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */\r
+\r
+typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */\r
+typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */\r
+\r
+typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */\r
+typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */\r
+\r
+//------------------------------------------------------------------------------\r
+// Channel\r
+//------------------------------------------------------------------------------\r
+\r
+typedef uint8_t TSL_Conf_t;\r
+\r
+/** Channel destination index\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndex_T IdxDest; /**< Index in the Channel data array */\r
+} TSL_ChannelDest_T;\r
+\r
+/** Channel Source and Configuration\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndex_T IdxSrc; /**< Index of source value */\r
+ // For stm32l1x acquisition only\r
+ TSL_Conf_t t_sample; /**< Indicates which GPIO.n is used for the sample */\r
+ TSL_Conf_t t_channel; /**< Indicates which GPIO.n is used for the channel */\r
+} TSL_ChannelSrc_T;\r
+\r
+/** Channel flags\r
+ */\r
+typedef struct\r
+{\r
+ unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */\r
+ unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */\r
+ unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */\r
+} TSL_ChannelFlags_T;\r
+\r
+/** Channel Data\r
+ */\r
+typedef struct\r
+{\r
+ TSL_ChannelFlags_T Flags; /**< Flags */\r
+ TSL_tRef_T Ref; /**< Reference */\r
+ TSL_tRefRest_T RefRest; /**< Reference rest for ECS */\r
+ TSL_tDelta_T Delta; /**< Delta */\r
+#if TSLPRM_USE_MEAS > 0\r
+ TSL_tMeas_T Meas; /**< Hold the last acquisition measure */\r
+#endif\r
+} TSL_ChannelData_T;\r
+\r
+//------------------------------------------------------------------------------\r
+// Bank\r
+//------------------------------------------------------------------------------\r
+\r
+/** Bank\r
+ */\r
+typedef struct\r
+{\r
+ // Common to all acquisitions\r
+ CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */\r
+ CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */\r
+ TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */\r
+ TSL_tNb_T NbChannels; /**< Number of channels in the bank */\r
+ // For stm32l1x acquisition only\r
+ TSL_Conf_t shield_sample; /**< Indicates which GPIO.n is used for the shield sample */\r
+ TSL_Conf_t shield_channel; /**< Indicates which GPIO.n is used for the shield channel */\r
+} TSL_Bank_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+TSL_Status_enum_T TSL_acq_Init(void);\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);\r
+void TSL_acq_BankStartAcq(void);\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void);\r
+void TSL_acq_ProcessIT(void);\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index);\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);\r
+\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);\r
+TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas);\r
+TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta);\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);\r
+\r
+#endif /* __TSL_ACQ_STM32L1XX_SW_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm8tl5x.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions prototypes that manage the TSC\r
+ * acquisition on STM8TL5x products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_ACQ_STM8TL5X_H\r
+#define __TSL_ACQ_STM8TL5X_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8tl5x.h"\r
+#include "tsl_conf_stm8tl5x.h"\r
+#include "tsl_types.h"\r
+\r
+/*==============================================================================\r
+\r
+ *** RECEIVERS AND TRANSMITTERS DESCRIPTION ***\r
+\r
+ ProxSense receiver and transmitter description for STM8TL5x\r
+ For more details please refer to the Proxsense\r
+ section in the reference manual\r
+\r
+\r
+ Txi\r
+ Group Ai Rx0a __/____ |\r
+ Rx1a __/____ |\r
+ Rx2a __/____ |\r
+ Rx3a __/____ |\r
+ Rx4a __/____ |\r
+ Rx5a __/____ |\r
+ Rx6a __/____ |\r
+ Rx7a __/____ |\r
+ Rx8a __/____ |\r
+ Rx9a __/____ |\r
+\r
+ Group Bi Rx0b __/____ |\r
+ Rx1b __/____ |\r
+ Rx2b __/____ |\r
+ Rx3b __/____ |\r
+ Rx4b __/____ |\r
+ Rx5b __/____ |\r
+ Rx6b __/____ |\r
+ Rx7b __/____ |\r
+ Rx8b __/____ |\r
+ Rx9b __/____ |\r
+\r
+==============================================================================*/\r
+\r
+/* Defines -------------------------------------------------------------------*/\r
+\r
+// Receivers\r
+#define RX0 (0+0x8000)\r
+#define RX1 (1+0x8000)\r
+#define RX2 (2+0x8000)\r
+#define RX3 (3+0x8000)\r
+#define RX4 (4+0x8000)\r
+#define RX5 (5+0x8000)\r
+#define RX6 (6+0x8000)\r
+#define RX7 (7+0x8000)\r
+#define RX8 (8+0x8000)\r
+#define RX9 (9+0x8000)\r
+\r
+// Transmitters\r
+#define TX0 (0)\r
+#define TX1 (1)\r
+#define TX2 (2)\r
+#define TX3 (3)\r
+#define TX4 (4)\r
+#define TX5 (5)\r
+#define TX6 (6)\r
+#define TX7 (7)\r
+#define TX8 (8)\r
+#define TX9 (9)\r
+#define TX10 (10)\r
+#define TX11 (11)\r
+#define TX12 (12)\r
+#define TX13 (13)\r
+#define TX14 (14)\r
+\r
+#define BIT_MASK_RX(N) ((uint16_t)1<<(uint8_t)(N & 0xFF))\r
+#define BIT_MASK_TX(N) ((uint16_t)1<< N)\r
+\r
+// Acquisition Bank\r
+#define BANK01 1\r
+#define BANK02 2\r
+#define BANK03 3\r
+#define BANK04 4\r
+#define BANK05 5\r
+#define BANK06 6\r
+#define BANK07 7\r
+#define BANK08 8\r
+#define BANK09 9\r
+#define BANK10 10\r
+#define BANK11 11\r
+#define BANK12 12\r
+#define BANK13 13\r
+#define BANK14 14\r
+#define BANK15 15\r
+#define BANK16 16\r
+#define BANK17 17\r
+#define BANK18 18\r
+#define BANK19 19\r
+#define BANK20 20\r
+#define BANK21 21\r
+#define BANK22 22\r
+#define BANK23 23\r
+#define BANK24 24\r
+#define BANK25 25\r
+#define BANK26 26\r
+#define BANK27 27\r
+#define BANK28 28\r
+#define BANK29 29\r
+#define BANK30 30\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+// For all devices/acquisitions\r
+\r
+typedef uint16_t TSL_tMeas_T; /**< Measurement */\r
+typedef uint16_t TSL_tRef_T; /**< Reference */\r
+typedef int16_t TSL_tDelta_T; /**< Delta */\r
+\r
+typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */\r
+typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */\r
+\r
+typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */\r
+typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */\r
+\r
+typedef uint8_t TSL_tIndex_T; /**< Generic index */\r
+typedef uint16_t TSL_tNb_T; /**< Generic number */\r
+typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */\r
+\r
+typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */\r
+\r
+typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */\r
+typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */\r
+\r
+typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */\r
+typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */\r
+\r
+// For STM8TL5X only\r
+\r
+typedef uint16_t TSL_tMaskRX; /**< Receiver mask */\r
+typedef uint16_t TSL_tMaskTX; /**< Transmitter mask */\r
+\r
+//------------------------------------------------------------------------------\r
+// Channel\r
+//------------------------------------------------------------------------------\r
+\r
+/** Channel destination index\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndexDest_T IdxDest; /**< Index in the Channel data array */\r
+} TSL_ChannelDest_T;\r
+\r
+/** Channel Source and Configuration\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tIndexSrc_T IdxSrc; /**< Index of the receivers (between 0 and 9) */\r
+} TSL_ChannelSrc_T;\r
+\r
+#define TSL_EPCC_CHANGE_MASK (0x04) /**< EPCC change mask */\r
+\r
+/** EPCC status\r
+ */\r
+typedef enum\r
+{\r
+ TSL_EPCC_STATUS_UNLOCKED = 0, /**< EPCC is unlocked */\r
+ TSL_EPCC_STATUS_LOCKED = 1, /**< EPCC is locked */\r
+ TSL_EPCC_STATUS_DECREASE = 4, /**< EPCC must decreased */\r
+ TSL_EPCC_STATUS_INCREASE = 6 /**< EPCC must be increased */\r
+} TSL_EPCCStatus_enum_T;\r
+\r
+/** Channel flags\r
+ */\r
+typedef struct\r
+{\r
+ unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */\r
+ unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */\r
+ unsigned int EPCCStatus : 3; /**< Acquisition status (TSL_EPCCStatus_enum_T) */\r
+ unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */\r
+} TSL_ChannelFlags_T;\r
+\r
+/** Channel Data\r
+ */\r
+typedef struct\r
+{\r
+ TSL_ChannelFlags_T Flags; /**< Flags */\r
+ TSL_tRef_T Ref; /**< Reference */\r
+ TSL_tRefRest_T RefRest; /**< Reference rest for ECS */\r
+ TSL_tDelta_T Delta; /**< Delta */\r
+#if TSLPRM_USE_MEAS > 0\r
+ TSL_tMeas_T Meas; /**< Hold the last acquisition measure */\r
+#endif\r
+} TSL_ChannelData_T;\r
+\r
+//------------------------------------------------------------------------------\r
+// Bank\r
+//------------------------------------------------------------------------------\r
+\r
+/** Bank\r
+ */\r
+typedef struct\r
+{\r
+ // Common to all acquisitions\r
+ CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */\r
+ CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */\r
+ TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */\r
+ TSL_tNb_T NbChannels; /**< Number of channels in the bank */\r
+ // For stm8tl5x PXS acquisition only\r
+ TSL_tMaskRX msk_channels; /**< Mask of all receivers */\r
+ TSL_tMaskTX msk_TX; /**< Mask of Tx */\r
+ uint8_t msk_group; /**< Mask of group used (RX_GROUPA or RX_GROUPB) */\r
+ TSL_tMaskRX msk_RXEN; /**< Mask of all RX (receivers and transmitters) */\r
+} TSL_Bank_T;\r
+\r
+/** Bank Configuration\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t CSSEL[TSLPRM_HIGH_CHANNEL_NB+1]; /**< Array of CS values */\r
+ uint8_t EPCCSEL[TSLPRM_HIGH_CHANNEL_NB+1]; /**< Array of EPCC values */\r
+} TSL_BankConfig_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+#define TSL_acq_ComputeDelta(Reference,Measure) (TSL_tDelta_T)(Measure - Reference) /**< Calculate the Delta */\r
+#define TSL_acq_ComputeMeas(Reference,Delta) (TSL_tMeas_T)(Delta + Reference) /**< Calculate the Measure */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+TSL_Status_enum_T TSL_acq_Init(void);\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);\r
+void TSL_acq_BankStartAcq(void);\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void);\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndexSrc_T index);\r
+void TSL_acq_UpdateCS(uint8_t *pCSSEL, TSL_EPCCStatus_enum_T change);\r
+\r
+#endif /* __TSL_ACQ_STM8TL5X_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_check_config.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains the check of all parameters defined in the\r
+ * common configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CHECK_CONFIG_H\r
+#define __TSL_CHECK_CONFIG_H\r
+\r
+//==============================================================================\r
+// Common parameters check\r
+//==============================================================================\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TOTAL_CHANNELS\r
+#error "TSLPRM_TOTAL_CHANNELS is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_TOTAL_BANKS\r
+#error "TSLPRM_TOTAL_BANKS is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_TOTAL_TOUCHKEYS\r
+#error "TSLPRM_TOTAL_TOUCHKEYS is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_TOTAL_TOUCHKEYS_B\r
+#error "TSLPRM_TOTAL_TOUCHKEYS_B is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_TOTAL_LINROTS\r
+#error "TSLPRM_TOTAL_LINROTS is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_TOTAL_LINROTS_B\r
+#error "TSLPRM_TOTAL_LINROTS_B is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_TOTAL_OBJECTS\r
+#error "TSLPRM_TOTAL_OBJECTS is not defined."\r
+#endif\r
+\r
+#define TSLPRM_TOTAL_TKEYS (TSLPRM_TOTAL_TOUCHKEYS + TSLPRM_TOTAL_TOUCHKEYS_B)\r
+#define TSLPRM_TOTAL_LNRTS (TSLPRM_TOTAL_LINROTS + TSLPRM_TOTAL_LINROTS_B)\r
+\r
+#if ((TSLPRM_TOTAL_TKEYS == 0) && (TSLPRM_TOTAL_LNRTS == 0))\r
+#error "No TouchKey and No Linear/Rotary sensors are defined."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_CALIB_SAMPLES\r
+#error "TSLPRM_CALIB_SAMPLES is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_CALIB_SAMPLES != 4) && (TSLPRM_CALIB_SAMPLES != 8) && (TSLPRM_CALIB_SAMPLES != 16))\r
+#error "TSLPRM_CALIB_SAMPLES is out of range (4, 8, 16)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_CALIB_DELAY\r
+#error "TSLPRM_CALIB_DELAY is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_CALIB_DELAY < 0) || (TSLPRM_CALIB_DELAY > 40))\r
+#error "TSLPRM_CALIB_DELAY is out of range (0..40)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_ACQ_MIN\r
+#error "TSLPRM_ACQ_MIN is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_ACQ_MAX\r
+#error "TSLPRM_ACQ_MAX is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_ACQ_MIN < 1) || (TSLPRM_ACQ_MIN > (TSLPRM_ACQ_MAX-1)))\r
+#error "TSLPRM_ACQ_MIN is out of range (1 .. ACQ_MAX-1)."\r
+#endif\r
+\r
+#if ((TSLPRM_ACQ_MAX < (TSLPRM_ACQ_MIN+1)) || (TSLPRM_ACQ_MAX > 50000))\r
+#error "TSLPRM_ACQ_MAX is out of range (ACQ_MIN+1 .. 50000)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TKEY_PROX_IN_TH\r
+#error "TSLPRM_TKEY_PROX_IN_TH is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_TKEY_PROX_OUT_TH\r
+#error "TSLPRM_TKEY_PROX_OUT_TH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TKEY_PROX_OUT_TH < 0) || (TSLPRM_TKEY_PROX_OUT_TH > (TSLPRM_TKEY_PROX_IN_TH-1)))\r
+#error "TSLPRM_TKEY_PROX_OUT_TH is out of range (0 .. TSLPRM_TKEY_PROX_IN_TH-1)."\r
+#endif\r
+\r
+#if TSLPRM_COEFF_TH == 0\r
+#if ((TSLPRM_TKEY_PROX_IN_TH < (TSLPRM_TKEY_PROX_OUT_TH+1)) || (TSLPRM_TKEY_PROX_IN_TH > (TSLPRM_TKEY_DETECT_OUT_TH-1)))\r
+#error "TSLPRM_TKEY_PROX_IN_TH is out of range (TSLPRM_TKEY_PROX_OUT_TH+1 .. TSLPRM_TKEY_DETECT_OUT_TH-1)."\r
+#endif\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_LINROT_PROX_IN_TH\r
+#error "TSLPRM_LINROT_PROX_IN_TH is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_LINROT_PROX_OUT_TH\r
+#error "TSLPRM_LINROT_PROX_OUT_TH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_LINROT_PROX_OUT_TH < 0) || (TSLPRM_LINROT_PROX_OUT_TH > (TSLPRM_LINROT_PROX_IN_TH-1)))\r
+#error "TSLPRM_LINROT_PROX_OUT_TH is out of range (0 .. TSLPRM_LINROT_PROX_IN_TH-1)."\r
+#endif\r
+\r
+#if TSLPRM_COEFF_TH == 0\r
+#if ((TSLPRM_LINROT_PROX_IN_TH < (TSLPRM_LINROT_PROX_OUT_TH+1)) || (TSLPRM_LINROT_PROX_IN_TH > (TSLPRM_LINROT_DETECT_OUT_TH-1)))\r
+#error "TSLPRM_LINROT_PROX_IN_TH is out of range (TSLPRM_LINROT_PROX_OUT_TH+1 .. TSLPRM_LINROT_DETECT_OUT_TH-1)."\r
+#endif\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TKEY_DETECT_IN_TH\r
+#error "TSLPRM_TKEY_DETECT_IN_TH is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_TKEY_DETECT_OUT_TH\r
+#error "TSLPRM_TKEY_DETECT_OUT_TH is not defined."\r
+#endif\r
+\r
+#if TSLPRM_COEFF_TH == 0\r
+#if ((TSLPRM_TKEY_DETECT_OUT_TH < (TSLPRM_TKEY_PROX_IN_TH+1)) || (TSLPRM_TKEY_DETECT_OUT_TH > (TSLPRM_TKEY_DETECT_IN_TH-1)))\r
+#error "TSLPRM_TKEY_DETECT_OUT_TH is out of range (TSLPRM_TKEY_PROX_IN_TH+1 .. TSLPRM_TKEY_DETECT_IN_TH-1)."\r
+#endif\r
+#endif\r
+\r
+#if ((TSLPRM_TKEY_DETECT_IN_TH < (TSLPRM_TKEY_DETECT_OUT_TH+1)) || (TSLPRM_TKEY_DETECT_IN_TH > 255))\r
+#error "TSLPRM_TKEY_DETECT_IN_TH is out of range (TSLPRM_TKEY_DETECT_OUT_TH+1 .. 255)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_LINROT_DETECT_IN_TH\r
+#error "TSLPRM_LINROT_DETECT_IN_TH is not defined."\r
+#endif\r
+\r
+#ifndef TSLPRM_LINROT_DETECT_OUT_TH\r
+#error "TSLPRM_LINROT_DETECT_OUT_TH is not defined."\r
+#endif\r
+\r
+#if TSLPRM_COEFF_TH == 0\r
+#if ((TSLPRM_LINROT_DETECT_OUT_TH < (TSLPRM_LINROT_PROX_IN_TH+1)) || (TSLPRM_LINROT_DETECT_OUT_TH > (TSLPRM_LINROT_DETECT_IN_TH-1)))\r
+#error "TSLPRM_LINROT_DETECT_OUT_TH is out of range (TSLPRM_LINROT_PROX_IN_TH+1 .. TSLPRM_LINROT_DETECT_IN_TH-1)."\r
+#endif\r
+#endif\r
+\r
+#if ((TSLPRM_LINROT_DETECT_IN_TH < (TSLPRM_LINROT_DETECT_OUT_TH+1)) || (TSLPRM_LINROT_DETECT_IN_TH > 255))\r
+#error "TSLPRM_LINROT_DETECT_IN_TH is out of range (TSLPRM_LINROT_DETECT_OUT_TH+1 .. 255)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TKEY_CALIB_TH\r
+#error "TSLPRM_TKEY_CALIB_TH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TKEY_CALIB_TH < 0) || (TSLPRM_TKEY_CALIB_TH > 255))\r
+#error "TSLPRM_TKEY_CALIB_TH is out of range (0 .. 255)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_LINROT_CALIB_TH\r
+#error "TSLPRM_LINROT_CALIB_TH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_LINROT_CALIB_TH < 0) || (TSLPRM_LINROT_CALIB_TH > 255))\r
+#error "TSLPRM_LINROT_CALIB_TH is out of range (0 .. 255)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_LINROT_USE_NORMDELTA\r
+#error "TSLPRM_LINROT_USE_NORMDELTA is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_LINROT_USE_NORMDELTA < 0) || (TSLPRM_LINROT_USE_NORMDELTA > 1))\r
+#error "TSLPRM_LINROT_USE_NORMDELTA is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_COEFF_TH\r
+#error "TSLPRM_COEFF_TH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_COEFF_TH < 0) || (TSLPRM_COEFF_TH > 4))\r
+#error "TSLPRM_COEFF_TH is out of range (0 .. 4)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_LINROT_DIR_CHG_POS\r
+#error "TSLPRM_LINROT_DIR_CHG_POS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_LINROT_DIR_CHG_POS < 0) || (TSLPRM_LINROT_DIR_CHG_POS > 255))\r
+#error "TSLPRM_LINROT_DIR_CHG_POS is out of range (0 .. 255)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_LINROT_RESOLUTION\r
+#error "TSLPRM_LINROT_RESOLUTION is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_LINROT_RESOLUTION < 1) || (TSLPRM_LINROT_RESOLUTION > 8))\r
+#error "TSLPRM_LINROT_RESOLUTION is out of range (1 .. 8)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_DEBOUNCE_PROX\r
+#error "TSLPRM_DEBOUNCE_PROX is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_DEBOUNCE_PROX < 0) || (TSLPRM_DEBOUNCE_PROX > 63))\r
+#error "TSLPRM_DEBOUNCE_PROX is out of range (0 .. 63)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_DEBOUNCE_DETECT\r
+#error "TSLPRM_DEBOUNCE_DETECT is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_DEBOUNCE_DETECT < 0) || (TSLPRM_DEBOUNCE_DETECT > 63))\r
+#error "TSLPRM_DEBOUNCE_DETECT is out of range (0 .. 63)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_DEBOUNCE_RELEASE\r
+#error "TSLPRM_DEBOUNCE_RELEASE is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_DEBOUNCE_RELEASE < 0) || (TSLPRM_DEBOUNCE_RELEASE > 63))\r
+#error "TSLPRM_DEBOUNCE_RELEASE is out of range (0 .. 63)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_DEBOUNCE_CALIB\r
+#error "TSLPRM_DEBOUNCE_CALIB is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_DEBOUNCE_CALIB < 0) || (TSLPRM_DEBOUNCE_CALIB > 63))\r
+#error "TSLPRM_DEBOUNCE_CALIB is out of range (0 .. 63)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_DEBOUNCE_ERROR\r
+#error "TSLPRM_DEBOUNCE_ERROR is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_DEBOUNCE_ERROR < 0) || (TSLPRM_DEBOUNCE_ERROR > 63))\r
+#error "TSLPRM_DEBOUNCE_ERROR is out of range (0 .. 63)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_LINROT_DIR_CHG_DEB\r
+#error "TSLPRM_LINROT_DIR_CHG_DEB is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_LINROT_DIR_CHG_DEB < 0) || (TSLPRM_LINROT_DIR_CHG_DEB > 63))\r
+#error "TSLPRM_LINROT_DIR_CHG_DEB is out of range (0 .. 63)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_ECS_K_SLOW\r
+#error "TSLPRM_ECS_K_SLOW is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_ECS_K_SLOW < 0) || (TSLPRM_ECS_K_SLOW > 255))\r
+#error "TSLPRM_ECS_K_SLOW is out of range (0 .. 255)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_ECS_K_FAST\r
+#error "TSLPRM_ECS_K_FAST is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_ECS_K_FAST < 0) || (TSLPRM_ECS_K_FAST > 255))\r
+#error "TSLPRM_ECS_K_FAST is out of range (0 .. 255)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_ECS_DELAY\r
+#error "TSLPRM_ECS_DELAY is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_ECS_DELAY < 0) || (TSLPRM_ECS_DELAY > 5000))\r
+#error "TSLPRM_ECS_DELAY is out of range (0 .. 5000)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_USE_MEAS\r
+#error "TSLPRM_USE_MEAS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_MEAS != 0) && (TSLPRM_USE_MEAS != 1))\r
+#error "TSLPRM_USE_MEAS is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_USE_PROX\r
+#error "TSLPRM_USE_PROX is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_PROX != 0) && (TSLPRM_USE_PROX != 1))\r
+#error "TSLPRM_USE_PROX is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_USE_ZONE\r
+#error "TSLPRM_USE_ZONE is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_ZONE != 0) && (TSLPRM_USE_ZONE != 1))\r
+#error "TSLPRM_USE_ZONE is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_USE_ACQ_INTERRUPT\r
+#error "TSLPRM_USE_ACQ_INTERRUPT is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_ACQ_INTERRUPT != 0) && (TSLPRM_USE_ACQ_INTERRUPT != 1))\r
+#error "TSLPRM_USE_ACQ_INTERRUPT is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_DTO\r
+#error "TSLPRM_DTO is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_DTO < 0) || (TSLPRM_DTO > 63))\r
+#error "TSLPRM_DTO is out of range (0 .. 63)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TICK_FREQ\r
+#error "TSLPRM_TICK_FREQ is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TICK_FREQ != 125) && (TSLPRM_TICK_FREQ != 250) && (TSLPRM_TICK_FREQ != 500) &&\\r
+ (TSLPRM_TICK_FREQ != 1000) && (TSLPRM_TICK_FREQ != 2000))\r
+#error "TSLPRM_TICK_FREQ is out of range (125, 250, 500, 1000, 2000)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_USE_DXS\r
+#error "TSLPRM_USE_DXS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_DXS < 0) || (TSLPRM_USE_DXS > 1))\r
+#error "TSLPRM_USE_DXS is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_USE_TIMER_CALLBACK\r
+#error "TSLPRM_USE_TIMER_CALLBACK is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_TIMER_CALLBACK != 0) && (TSLPRM_USE_TIMER_CALLBACK != 1))\r
+#error "TSLPRM_USE_TIMER_CALLBACK is out of range (0 .. 1)."\r
+#endif\r
+\r
+//==============================================================================\r
+// Specific parameters check\r
+//==============================================================================\r
+\r
+#if defined(STM8TL5X)\r
+#include "tsl_check_config_stm8tl5x.h"\r
+#endif\r
+\r
+#if defined(STM32F0XX)\r
+#include "tsl_check_config_stm32f0xx.h"\r
+#endif\r
+\r
+#if defined(STM32F30X) || defined(STM32F37X)\r
+#include "tsl_check_config_stm32f3xx.h"\r
+#endif\r
+\r
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MDP)\r
+#include "tsl_check_config_stm32l1xx.h"\r
+#endif\r
+\r
+#endif /* __TSL_CHECK_CONFIG_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_check_config_stm32f0xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains the check of all parameters defined in the\r
+ * STM32F0XX configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CHECK_CONFIG_STM32F0XX_H\r
+#define __TSL_CHECK_CONFIG_STM32F0XX_H\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 24))\r
+#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 8))\r
+#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 8)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 24))\r
+#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 24))\r
+#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 24))\r
+#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 24))\r
+#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 24))\r
+#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TKEYS + TSLPRM_TOTAL_LNRTS) > 24)\r
+#error "The Sum of TouchKeys and Linear/Rotary sensors exceeds 24."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_GPIO_CONFIG\r
+#error "TSLPRM_TSC_GPIO_CONFIG is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_GPIO_CONFIG < 0) || (TSLPRM_TSC_GPIO_CONFIG > 1))\r
+#error "TSLPRM_TSC_GPIO_CONFIG is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_CTPH\r
+#error "TSLPRM_TSC_CTPH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_CTPH < 0) || (TSLPRM_TSC_CTPH > 15))\r
+#error "TSLPRM_TSC_CTPH is out of range (0 .. 15)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_CTPL\r
+#error "TSLPRM_TSC_CTPL is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_CTPL < 0) || (TSLPRM_TSC_CTPL > 15))\r
+#error "TSLPRM_TSC_CTPL is out of range (0 .. 15)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_PGPSC\r
+#error "TSLPRM_TSC_PGPSC is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_PGPSC < 0) || (TSLPRM_TSC_PGPSC > 7))\r
+#error "TSLPRM_TSC_PGPSC is out of range (0 .. 7)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if (TSLPRM_ACQ_MAX > 0) && (TSLPRM_ACQ_MAX < 256)\r
+#define TSLPRM_TSC_MCV 0 // 255\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 255) && (TSLPRM_ACQ_MAX < 512)\r
+#define TSLPRM_TSC_MCV 1 // 511\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 511) && (TSLPRM_ACQ_MAX < 1024)\r
+#define TSLPRM_TSC_MCV 2 // 1023\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 1023) && (TSLPRM_ACQ_MAX < 2048)\r
+#define TSLPRM_TSC_MCV 3 // 2047\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 2047) && (TSLPRM_ACQ_MAX < 4096)\r
+#define TSLPRM_TSC_MCV 4 // 4095\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 4095) && (TSLPRM_ACQ_MAX < 8192)\r
+#define TSLPRM_TSC_MCV 5 // 8191\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 8191)\r
+#define TSLPRM_TSC_MCV 6 // 16383\r
+#endif\r
+\r
+#ifndef TSLPRM_TSC_MCV\r
+#error "TSLPRM_TSC_MCV is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_MCV < 0) || (TSLPRM_TSC_MCV > 6))\r
+#error "TSLPRM_TSC_MCV is out of range (0 .. 6)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_IODEF\r
+#error "TSLPRM_TSC_IODEF is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_IODEF < 0) || (TSLPRM_TSC_IODEF > 1))\r
+#error "TSLPRM_TSC_IODEF is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_AM\r
+#error "TSLPRM_TSC_AM is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_AM < 0) || (TSLPRM_TSC_AM > 1))\r
+#error "TSLPRM_TSC_AM is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_SYNC_PIN\r
+#error "TSLPRM_TSC_SYNC_PIN is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_SYNC_PIN < 0) || (TSLPRM_TSC_SYNC_PIN > 1))\r
+#error "TSLPRM_TSC_SYNC_PIN is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_SYNC_POL\r
+#error "TSLPRM_TSC_SYNC_POL is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_SYNC_POL < 0) || (TSLPRM_TSC_SYNC_POL > 1))\r
+#error "TSLPRM_TSC_SYNC_POL is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_USE_SS\r
+#error "TSLPRM_TSC_USE_SS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_USE_SS < 0) || (TSLPRM_TSC_USE_SS > 1))\r
+#error "TSLPRM_TSC_USE_SS is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_SSD\r
+#error "TSLPRM_TSC_SSD is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_SSD < 0) || (TSLPRM_TSC_SSD > 127))\r
+#error "TSLPRM_TSC_SSD is out of range (0 .. 127)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_SSPSC\r
+#error "TSLPRM_TSC_SSPSC is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_SSPSC < 0) || (TSLPRM_TSC_SSPSC > 1))\r
+#error "TSLPRM_TSC_SSPSC is out of range (0 .. 1)."\r
+#endif\r
+\r
+#endif /* __TSL_CHECK_CONFIG_STM32F0XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_check_config_stm32f3xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains the check of all parameters defined in the\r
+ * STM32F3XX configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CHECK_CONFIG_STM32F3XX_H\r
+#define __TSL_CHECK_CONFIG_STM32F3XX_H\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 24))\r
+#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 8))\r
+#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 8)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 24))\r
+#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 24))\r
+#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 24))\r
+#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 24))\r
+#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 24))\r
+#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TKEYS + TSLPRM_TOTAL_LNRTS) > 24)\r
+#error "The Sum of TouchKeys and Linear/Rotary sensors exceeds 24."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_GPIO_CONFIG\r
+#error "TSLPRM_TSC_GPIO_CONFIG is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_GPIO_CONFIG < 0) || (TSLPRM_TSC_GPIO_CONFIG > 1))\r
+#error "TSLPRM_TSC_GPIO_CONFIG is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_CTPH\r
+#error "TSLPRM_TSC_CTPH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_CTPH < 0) || (TSLPRM_TSC_CTPH > 15))\r
+#error "TSLPRM_TSC_CTPH is out of range (0 .. 15)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_CTPL\r
+#error "TSLPRM_TSC_CTPL is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_CTPL < 0) || (TSLPRM_TSC_CTPL > 15))\r
+#error "TSLPRM_TSC_CTPL is out of range (0 .. 15)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_PGPSC\r
+#error "TSLPRM_TSC_PGPSC is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_PGPSC < 0) || (TSLPRM_TSC_PGPSC > 7))\r
+#error "TSLPRM_TSC_PGPSC is out of range (0 .. 7)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if (TSLPRM_ACQ_MAX > 0) && (TSLPRM_ACQ_MAX < 256)\r
+#define TSLPRM_TSC_MCV 0 // 255\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 255) && (TSLPRM_ACQ_MAX < 512)\r
+#define TSLPRM_TSC_MCV 1 // 511\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 511) && (TSLPRM_ACQ_MAX < 1024)\r
+#define TSLPRM_TSC_MCV 2 // 1023\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 1023) && (TSLPRM_ACQ_MAX < 2048)\r
+#define TSLPRM_TSC_MCV 3 // 2047\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 2047) && (TSLPRM_ACQ_MAX < 4096)\r
+#define TSLPRM_TSC_MCV 4 // 4095\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 4095) && (TSLPRM_ACQ_MAX < 8192)\r
+#define TSLPRM_TSC_MCV 5 // 8191\r
+#endif\r
+\r
+#if (TSLPRM_ACQ_MAX > 8191)\r
+#define TSLPRM_TSC_MCV 6 // 16383\r
+#endif\r
+\r
+#ifndef TSLPRM_TSC_MCV\r
+#error "TSLPRM_TSC_MCV is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_MCV < 0) || (TSLPRM_TSC_MCV > 6))\r
+#error "TSLPRM_TSC_MCV is out of range (0 .. 6)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_IODEF\r
+#error "TSLPRM_TSC_IODEF is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_IODEF < 0) || (TSLPRM_TSC_IODEF > 1))\r
+#error "TSLPRM_TSC_IODEF is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_AM\r
+#error "TSLPRM_TSC_AM is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_AM < 0) || (TSLPRM_TSC_AM > 1))\r
+#error "TSLPRM_TSC_AM is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_SYNC_PIN\r
+#error "TSLPRM_TSC_SYNC_PIN is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_SYNC_PIN < 0) || (TSLPRM_TSC_SYNC_PIN > 1))\r
+#error "TSLPRM_TSC_SYNC_PIN is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_SYNC_POL\r
+#error "TSLPRM_TSC_SYNC_POL is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_SYNC_POL < 0) || (TSLPRM_TSC_SYNC_POL > 1))\r
+#error "TSLPRM_TSC_SYNC_POL is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_USE_SS\r
+#error "TSLPRM_TSC_USE_SS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_USE_SS < 0) || (TSLPRM_TSC_USE_SS > 1))\r
+#error "TSLPRM_TSC_USE_SS is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_SSD\r
+#error "TSLPRM_TSC_SSD is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_SSD < 0) || (TSLPRM_TSC_SSD > 127))\r
+#error "TSLPRM_TSC_SSD is out of range (0 .. 127)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TSC_SSPSC\r
+#error "TSLPRM_TSC_SSPSC is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TSC_SSPSC < 0) || (TSLPRM_TSC_SSPSC > 1))\r
+#error "TSLPRM_TSC_SSPSC is out of range (0 .. 1)."\r
+#endif\r
+\r
+#endif /* __TSL_CHECK_CONFIG_STM32F3XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_check_config_stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains the check of all parameters defined in the\r
+ * STM32L1XX configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CHECK_CONFIG_STM32L1XX_H\r
+#define __TSL_CHECK_CONFIG_STM32L1XX_H\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 24))\r
+#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 8))\r
+#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 8)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 24))\r
+#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 24))\r
+#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 24))\r
+#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 24))\r
+#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 24))\r
+#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 24)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TKEYS + TSLPRM_TOTAL_LNRTS) > 24)\r
+#error "The Sum of TouchKeys and Linear/Rotary sensors exceeds 24."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_USE_SHIELD\r
+#error "TSLPRM_USE_SHIELD is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_SHIELD < 0) || (TSLPRM_USE_SHIELD > 1))\r
+#error "TSLPRM_USE_SHIELD is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_IODEF\r
+#error "TSLPRM_IODEF is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_IODEF < 0) || (TSLPRM_IODEF > 1))\r
+#error "TSLPRM_IODEF is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_HD) && !defined(TSLPRM_STM32L1XX_HD_SW)\r
+\r
+#ifndef TSLPRM_TIM_PRESCALER\r
+#error "TSLPRM_TIM_PRESCALER is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TIM_PRESCALER < 0) || (TSLPRM_TIM_PRESCALER > 65535))\r
+#error "TSLPRM_TIM_PRESCALER is out of range (0 .. 65535)."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_HD) && !defined(TSLPRM_STM32L1XX_HD_SW)\r
+\r
+#ifndef TSLPRM_TIM_RELOAD\r
+#error "TSLPRM_TIM_RELOAD is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TIM_RELOAD < 4) || (TSLPRM_TIM_RELOAD > 65534))\r
+#error "TSLPRM_TIM_RELOAD is out of range (4 .. 65534)."\r
+#endif\r
+\r
+#if ((TSLPRM_TIM_RELOAD % 2) != (0))\r
+#error "TSLPRM_TIM_RELOAD is odd and must be even."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_HD) && defined(TSLPRM_STM32L1XX_HD_SW)\r
+\r
+#ifndef TSLPRM_PROTECT_IO_ACCESS\r
+#error "TSLPRM_PROTECT_IO_ACCESS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PROTECT_IO_ACCESS < 0) || (TSLPRM_PROTECT_IO_ACCESS > 1))\r
+#error "TSLPRM_PROTECT_IO_ACCESS is out of range (0 .. 1)."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_HD) && defined(TSLPRM_STM32L1XX_HD_SW)\r
+\r
+#ifndef TSLPRM_USE_GPIOA\r
+#error "TSLPRM_USE_GPIOA is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOA < 0) || (TSLPRM_USE_GPIOA > 1))\r
+#error "TSLPRM_USE_GPIOA is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOB\r
+#error "TSLPRM_USE_GPIOB is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOB < 0) || (TSLPRM_USE_GPIOB > 1))\r
+#error "TSLPRM_USE_GPIOB is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOC\r
+#error "TSLPRM_USE_GPIOC is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOC < 0) || (TSLPRM_USE_GPIOC > 1))\r
+#error "TSLPRM_USE_GPIOC is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOF\r
+#error "TSLPRM_USE_GPIOA is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOF < 0) || (TSLPRM_USE_GPIOF > 1))\r
+#error "TSLPRM_USE_GPIOF is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOG\r
+#error "TSLPRM_USE_GPIOG is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOG < 0) || (TSLPRM_USE_GPIOG > 1))\r
+#error "TSLPRM_USE_GPIOG is out of range (0 .. 1)."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_MD)\r
+\r
+#ifndef TSLPRM_PROTECT_IO_ACCESS\r
+#error "TSLPRM_PROTECT_IO_ACCESS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PROTECT_IO_ACCESS < 0) || (TSLPRM_PROTECT_IO_ACCESS > 1))\r
+#error "TSLPRM_PROTECT_IO_ACCESS is out of range (0 .. 1)."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_MD)\r
+\r
+#ifndef TSLPRM_USE_GPIOA\r
+#error "TSLPRM_USE_GPIOA is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOA < 0) || (TSLPRM_USE_GPIOA > 1))\r
+#error "TSLPRM_USE_GPIOA is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOB\r
+#error "TSLPRM_USE_GPIOB is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOB < 0) || (TSLPRM_USE_GPIOB > 1))\r
+#error "TSLPRM_USE_GPIOB is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOC\r
+#error "TSLPRM_USE_GPIOC is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOC < 0) || (TSLPRM_USE_GPIOC > 1))\r
+#error "TSLPRM_USE_GPIOC is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOF\r
+#error "TSLPRM_USE_GPIOA is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOF < 0) || (TSLPRM_USE_GPIOF > 1))\r
+#error "TSLPRM_USE_GPIOF is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOG\r
+#error "TSLPRM_USE_GPIOG is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOG < 0) || (TSLPRM_USE_GPIOG > 1))\r
+#error "TSLPRM_USE_GPIOG is out of range (0 .. 1)."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_MDP) && !defined(TSLPRM_STM32L1XX_MDP_SW)\r
+\r
+#ifndef TSLPRM_TIM_PRESCALER\r
+#error "TSLPRM_TIM_PRESCALER is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TIM_PRESCALER < 0) || (TSLPRM_TIM_PRESCALER > 65535))\r
+#error "TSLPRM_TIM_PRESCALER is out of range (0 .. 65535)."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_MDP) && !defined(TSLPRM_STM32L1XX_MDP_SW)\r
+\r
+#ifndef TSLPRM_TIM_RELOAD\r
+#error "TSLPRM_TIM_RELOAD is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TIM_RELOAD < 4) || (TSLPRM_TIM_RELOAD > 65534))\r
+#error "TSLPRM_TIM_RELOAD is out of range (4 .. 65534)."\r
+#endif\r
+\r
+#if ((TSLPRM_TIM_RELOAD % 2) != (0))\r
+#error "TSLPRM_TIM_RELOAD is odd and must be even."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_MDP) && defined(TSLPRM_STM32L1XX_MDP_SW)\r
+\r
+#ifndef TSLPRM_PROTECT_IO_ACCESS\r
+#error "TSLPRM_PROTECT_IO_ACCESS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PROTECT_IO_ACCESS < 0) || (TSLPRM_PROTECT_IO_ACCESS > 1))\r
+#error "TSLPRM_PROTECT_IO_ACCESS is out of range (0 .. 1)."\r
+#endif\r
+\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(STM32L1XX_MDP) && defined(TSLPRM_STM32L1XX_MDP_SW)\r
+\r
+#ifndef TSLPRM_USE_GPIOA\r
+#error "TSLPRM_USE_GPIOA is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOA < 0) || (TSLPRM_USE_GPIOA > 1))\r
+#error "TSLPRM_USE_GPIOA is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOB\r
+#error "TSLPRM_USE_GPIOB is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOB < 0) || (TSLPRM_USE_GPIOB > 1))\r
+#error "TSLPRM_USE_GPIOB is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOC\r
+#error "TSLPRM_USE_GPIOC is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOC < 0) || (TSLPRM_USE_GPIOC > 1))\r
+#error "TSLPRM_USE_GPIOC is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOF\r
+#error "TSLPRM_USE_GPIOA is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOF < 0) || (TSLPRM_USE_GPIOF > 1))\r
+#error "TSLPRM_USE_GPIOF is out of range (0 .. 1)."\r
+#endif\r
+\r
+#ifndef TSLPRM_USE_GPIOG\r
+#error "TSLPRM_USE_GPIOG is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_USE_GPIOG < 0) || (TSLPRM_USE_GPIOG > 1))\r
+#error "TSLPRM_USE_GPIOG is out of range (0 .. 1)."\r
+#endif\r
+\r
+#endif\r
+\r
+#endif /* __TSL_CHECK_CONFIG_STM32L1XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_check_config_stm8tl5x.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains the check of all parameters defined in the\r
+ * STM8TL5X configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CHECK_CONFIG_STM8TL5X_H\r
+#define __TSL_CHECK_CONFIG_STM8TL5X_H\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if ((TSLPRM_MCU < 0) && (TSLPRM_MCU > 4))\r
+#error "The MCU selected is not in the STM8TL5x MCU list !"\r
+#endif\r
+\r
+#if (TSLPRM_MCU > 0)\r
+#define __MAX_RX 7\r
+#else\r
+#define __MAX_RX 9\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 300))\r
+#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 300)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 15))\r
+#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 15)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 256))\r
+#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 256)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 256))\r
+#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 256)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 256))\r
+#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 256)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 256))\r
+#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 256)."\r
+#endif\r
+\r
+#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 256))\r
+#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 256)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_KEY_TARGET_REFERENCE\r
+#error "TSLPRM_KEY_TARGET_REFERENCE is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_KEY_TARGET_REFERENCE < 100) || (TSLPRM_KEY_TARGET_REFERENCE > 2000))\r
+#error "TSLPRM_KEY_TARGET_REFERENCE is out of range (100 .. 2000)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_KEY_TARGET_REFERENCE_ERROR\r
+#error "TSLPRM_KEY_TARGET_REFERENCE_ERROR is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_KEY_TARGET_REFERENCE_ERROR < 1) || (TSLPRM_KEY_TARGET_REFERENCE_ERROR > TSLPRM_KEY_TARGET_REFERENCE))\r
+#error "TSLPRM_KEY_TARGET_REFERENCE_ERROR is out of range (1 .. TSLPRM_KEY_TARGET_REFERENCE)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION\r
+#error "TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION < 3) || (TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION > 5))\r
+#error "TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION is out of range (3 .. 5)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_KEY_TARGET_ATTENUATION\r
+#error "TSLPRM_KEY_TARGET_ATTENUATION is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_KEY_TARGET_ATTENUATION != 1) && (TSLPRM_KEY_TARGET_ATTENUATION != 2) &&\\r
+ (TSLPRM_KEY_TARGET_ATTENUATION != 4) && (TSLPRM_KEY_TARGET_ATTENUATION != 8))\r
+#error "TSLPRM_KEY_TARGET_ATTENUATION is out of range (1,2,4,8)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_TOUCHKEY_REFERENCE_RANGE\r
+#error "TSLPRM_TOUCHKEY_REFERENCE_RANGE is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_TOUCHKEY_REFERENCE_RANGE < 1) || (TSLPRM_TOUCHKEY_REFERENCE_RANGE > TSLPRM_KEY_TARGET_REFERENCE))\r
+#error "TSLPRM_TOUCHKEY_REFERENCE_RANGE is out of range (1 .. TSLPRM_KEY_TARGET_REFERENCE)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_LINROT_REFERENCE_RANGE\r
+#error "TSLPRM_LINROT_REFERENCE_RANGE is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_LINROT_REFERENCE_RANGE < 1) || (TSLPRM_LINROT_REFERENCE_RANGE > TSLPRM_KEY_TARGET_REFERENCE))\r
+#error "TSLPRM_LINROT_REFERENCE_RANGE is out of range (1 .. TSLPRM_KEY_TARGET_REFERENCE)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_HSI\r
+#error "TSLPRM_PXS_HSI is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_HSI != 16000) && (TSLPRM_PXS_HSI != 8000) && (TSLPRM_PXS_HSI != 4000) && \\r
+ (TSLPRM_PXS_HSI != 2000) && (TSLPRM_PXS_HSI != 1000) && (TSLPRM_PXS_HSI != 500) && \\r
+ (TSLPRM_PXS_HSI != 250) && (TSLPRM_PXS_HSI != 125))\r
+#error "TSLPRM_PXS_HSI is out of range (16000, 8000, 4000, 2000, 1000, 500, 250, 125)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_UP_LENGTH\r
+#error "TSLPRM_PXS_UP_LENGTH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_UP_LENGTH < 1) || (TSLPRM_PXS_UP_LENGTH > 7))\r
+#error "TSLPRM_PXS_UP_LENGTH is out of range (1 .. 7)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_PASS_LENGTH\r
+#error "TSLPRM_PXS_PASS_LENGTH is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_PASS_LENGTH < 1) || (TSLPRM_PXS_PASS_LENGTH > 7))\r
+#error "TSLPRM_PXS_PASS_LENGTH is out of range (1 .. 7)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_LOW_POWER_MODE\r
+#error "TSLPRM_PXS_LOW_POWER_MODE is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_LOW_POWER_MODE != 0) && (TSLPRM_PXS_LOW_POWER_MODE != 1))\r
+#error "TSLPRM_PXS_LOW_POWER_MODE is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_RF_DETECTION\r
+#error "TSLPRM_PXS_RF_DETECTION is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_RF_DETECTION != 0) && (TSLPRM_PXS_RF_DETECTION != 1))\r
+#error "TSLPRM_PXS_RF_DETECTION is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_SYNCHRONIZE\r
+#error "TSLPRM_PXS_SYNCHRONIZE is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_SYNCHRONIZE != 0) && (TSLPRM_PXS_SYNCHRONIZE != 1))\r
+#error "TSLPRM_PXS_SYNCHRONIZE is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_SYNCHRO_EDGE\r
+#error "TSLPRM_PXS_SYNCHRO_EDGE is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_SYNCHRO_EDGE != 0) && (TSLPRM_PXS_SYNCHRO_EDGE != 1))\r
+#error "TSLPRM_PXS_SYNCHRO_EDGE is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_INACTIVE_TX\r
+#error "TSLPRM_PXS_INACTIVE_TX is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_INACTIVE_TX != 0) && (TSLPRM_PXS_INACTIVE_TX != 1))\r
+#error "TSLPRM_PXS_INACTIVE_TX is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_INACTIVE_RX\r
+#error "TSLPRM_PXS_INACTIVE_RX is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_INACTIVE_RX != 0) && (TSLPRM_PXS_INACTIVE_RX != 1))\r
+#error "TSLPRM_PXS_INACTIVE_RX is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_RX_COUPLING\r
+#error "TSLPRM_PXS_RX_COUPLING is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_RX_COUPLING != 0) && (TSLPRM_PXS_RX_COUPLING != 1))\r
+#error "TSLPRM_PXS_RX_COUPLING is out of range (0 .. 1)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_STAB\r
+#error "TSLPRM_PXS_STAB is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_STAB != LONG_STAB) && (TSLPRM_PXS_STAB != MEDIUM_STAB) && (TSLPRM_PXS_STAB != SHORT_STAB))\r
+#error "TSLPRM_PXS_STAB is out of range (LONG_STAB, MEDIUM_STAB, SHORT_STAB)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_PXS_BIAS\r
+#error "TSLPRM_PXS_BIAS is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_PXS_BIAS != HIGH_BIAS) && (TSLPRM_PXS_BIAS != MEDIUM_BIAS) && (TSLPRM_PXS_BIAS != LOW_BIAS) && (TSLPRM_PXS_BIAS != VERY_LOW_BIAS))\r
+#error "TSLPRM_PXS_BIAS is out of range (HIGH_BIAS, MEDIUM_BIAS, LOW_BIAS, VERY_LOW_BIAS)."\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TSLPRM_HIGH_CHANNEL_NB\r
+#error "TSLPRM_HIGH_CHANNEL_NB is not defined."\r
+#endif\r
+\r
+#if ((TSLPRM_HIGH_CHANNEL_NB < 0) || (TSLPRM_HIGH_CHANNEL_NB > __MAX_RX))\r
+#error "TSLPRM_HIGH_CHANNEL_NB is out of range (0..9 for STM8TL53C4, 0..7 for STM8TL53G4)."\r
+#endif\r
+\r
+#endif /* __TSL_CHECK_CONFIG_STM8TL5X_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_dxs.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_dxs.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_DXS_H\r
+#define __TSL_DXS_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_object.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+void TSL_dxs_FirstObj(CONST TSL_ObjectGroup_T *objgrp);\r
+\r
+#endif /* __TSL_DXS_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_ecs.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_ecs.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_ECS_H\r
+#define __TSL_ECS_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_object.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+TSL_tKCoeff_T TSL_ecs_CalcK(CONST TSL_ObjectGroup_T *objgrp, TSL_tKCoeff_T k_slow, TSL_tKCoeff_T k_fast);\r
+void TSL_ecs_ProcessK(CONST TSL_ObjectGroup_T *objgrp, TSL_tKCoeff_T Kcoeff);\r
+TSL_Status_enum_T TSL_ecs_Process(CONST TSL_ObjectGroup_T *objgrp);\r
+\r
+#endif /* __TSL_ECS_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_filter.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_filter.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_FILTER_H\r
+#define __TSL_FILTER_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+TSL_tMeas_T TSL_filt_MeasFilter(TSL_tMeas_T measn1, TSL_tMeas_T measn);\r
+TSL_tDelta_T TSL_filt_DeltaFilter(TSL_tDelta_T delta);\r
+\r
+#endif /* __TSL_FILTER_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_globals.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_globals.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_GLOBALS_H\r
+#define __TSL_GLOBALS_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq.h"\r
+#include "tsl_object.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** Store all global variables shared between the STMTouch Driver and the Application.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tTick_ms_T Tick_ms; /**< Incremented each 0.5ms by timing interrupt routine */\r
+ TSL_tTick_sec_T Tick_sec; /**< Incremented each second by timing interrupt routine */\r
+ CONST TSL_Bank_T *Bank_Array; /**< Pointer to the array containing all Banks */\r
+ TSL_tIndex_T This_Bank; /**< Pointer to the current Bank */\r
+ CONST TSL_Object_T *This_Obj; /**< Pointer to the current Object */\r
+#if TSLPRM_USE_ZONE > 0\r
+ CONST TSL_Zone_T *This_Zone; /**< Pointer to the current Zone */\r
+ TSL_tIndex_T Index_In_This_Zone; /**< Index in the current Zone */\r
+#endif\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+ CONST TSL_TouchKey_T *This_TKey; /**< Pointer to the current TKey */\r
+#endif\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ CONST TSL_LinRot_T *This_LinRot; /**< Pointer to the current Linear or Rotary sensor */\r
+#endif\r
+}\r
+TSL_Globals_T;\r
+\r
+/** Store all global parametersshared between the STMTouch Driver and the Application .\r
+ @warning Only one variable of this structure type must be created and be placed\r
+ in RAM only.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_tMeas_T AcqMin; /**< Acquisition minimum limit */\r
+ TSL_tMeas_T AcqMax; /**< Acquisition maximum limit */\r
+ TSL_tNb_T NbCalibSamples; /**< Number of Calibration samples */\r
+ TSL_tTick_sec_T DTO; /**< Detection Time Out */\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+ CONST TSL_State_T *p_TKeySM; /**< Default state machine for TouchKey sensors */\r
+ CONST TSL_TouchKeyMethods_T *p_TKeyMT; /**< Default methods for TouchKey sensors */\r
+#endif\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ CONST TSL_State_T *p_LinRotSM; /**< Default state machine for Linear/Rotary sensors */\r
+ CONST TSL_LinRotMethods_T *p_LinRotMT; /**< Default methods for Linear/Rotary sensors */\r
+#endif\r
+}\r
+TSL_Params_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+extern TSL_Globals_T TSL_Globals;\r
+extern TSL_Params_T TSL_Params;\r
+\r
+#endif /* __TSL_GLOBALS_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_linrot.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_linrot.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_LINROT_H\r
+#define __TSL_LINROT_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq.h"\r
+#include "tsl_time.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** Contains all data related to Linear and Rotary sensor.\r
+ * Variables of this structure type must be placed in RAM only.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_StateId_enum_T StateId; /**< Current state identifier */\r
+ TSL_tPosition_T RawPosition; /**< Raw position */\r
+ TSL_tPosition_T Position; /**< Scaled position */\r
+ unsigned int Counter : 6; /**< Generic counter for state debounce, calibration & DTO (TSL_tCounter_T) */\r
+ unsigned int Change : 1; /**< The State is different from the previous one (TSL_StateChange_enum_T) */\r
+ unsigned int PosChange : 1; /**< The RawPosition/Position is different from the previous one (TSL_StateChange_enum_T) */\r
+ unsigned int Counter2 : 6; /**< Generic counter for direction debounce (TSL_tCounter_T) */\r
+ unsigned int DxSLock : 1; /**< The State is locked by the DxS (TSL_Bool_enum_T) */\r
+ unsigned int Direction : 1; /**< Movement direction (TSL_Bool_enum_T) */\r
+}\r
+TSL_LinRotData_T;\r
+\r
+/** Contains all parameters related to Linear and Rotary sensor.\r
+ * Variables of this structure type can be placed in RAM or ROM.\r
+ */\r
+typedef struct\r
+{\r
+ // Thresholds\r
+#if TSLPRM_USE_PROX > 0\r
+ TSL_tThreshold_T ProxInTh; /**< Proximity state in threshold */\r
+ TSL_tThreshold_T ProxOutTh; /**< Proximity state out threshold */\r
+#endif\r
+ TSL_tThreshold_T DetectInTh; /**< Detection state in threshold */\r
+ TSL_tThreshold_T DetectOutTh; /**< Detection state out threshold */\r
+ TSL_tThreshold_T CalibTh; /**< Calibration state threshold */\r
+ // Debounce counters\r
+ TSL_tCounter_T CounterDebCalib; /**< Debounce counter to enter in Calibration state */\r
+#if TSLPRM_USE_PROX > 0\r
+ TSL_tCounter_T CounterDebProx; /**< Debounce counter to enter in Proximity state */\r
+#endif\r
+ TSL_tCounter_T CounterDebDetect; /**< Debounce counter to enter in Detect state */\r
+ TSL_tCounter_T CounterDebRelease; /**< Debounce counter to enter in Release state */\r
+ TSL_tCounter_T CounterDebError; /**< Debounce counter to enter in Error state */\r
+ TSL_tCounter_T CounterDebDirection; /**< Debounce counter for the direction change */\r
+ // Other parameters\r
+ TSL_tCounter_T Resolution; /**< Position resolution */\r
+ TSL_tPosition_T DirChangePos; /**< Direction change position threshold */\r
+}\r
+TSL_LinRotParam_T;\r
+\r
+/** Contains definition of a Linear and Rotary sensor.\r
+ * Variables of this structure type can be placed in RAM or ROM.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_LinRotData_T *p_Data; /**< Data (state id, counter, flags, ...) */\r
+ TSL_LinRotParam_T *p_Param; /**< Parameters (thresholds, debounce, ...) */\r
+ TSL_ChannelData_T *p_ChD; /**< First Channel Data (Meas, Ref, Delta, ...) */\r
+ TSL_tNb_T NbChannels; /**< Number of channels */\r
+ CONST uint16_t *p_DeltaCoeff; /**< Coefficient to apply on Delta */\r
+ CONST TSL_tsignPosition_T *p_PosOff; /**< Position offset table */\r
+ TSL_tIndex_T SctComp; /**< Sector Computation */\r
+ TSL_tIndex_T PosCorr; /**< Position Correction */\r
+ CONST TSL_State_T *p_SM; /**< State Machine */\r
+ CONST TSL_LinRotMethods_T *p_Methods; /**< Methods */\r
+}\r
+TSL_LinRot_T;\r
+\r
+/** Contains definition of a Basic Linear and Rotary sensor.\r
+ * Variables of this structure type can be placed in RAM or ROM.\r
+ * Basic sensor does not contain its own state machine and methods. It used\r
+ * default ones instead to gain memory space.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_LinRotData_T *p_Data; /**< Data (state id, counter, flags, ...) */\r
+ TSL_LinRotParam_T *p_Param; /**< Parameters (thresholds, debounce, ...) */\r
+ TSL_ChannelData_T *p_ChD; /**< First Channel Data (Meas, Ref, Delta, ...) */\r
+ TSL_tNb_T NbChannels; /**< Number of channels */\r
+ CONST uint16_t *p_DeltaCoeff; /**< Coefficient to apply on Delta */\r
+ CONST TSL_tsignPosition_T *p_PosOff; /**< Position offset table */\r
+ TSL_tIndex_T SctComp; /**< Sector Computation */\r
+ TSL_tIndex_T PosCorr; /**< Position Correction */\r
+}\r
+TSL_LinRotB_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+// "Object methods" functions\r
+void TSL_linrot_Init(void);\r
+void TSL_linrot_Process(void);\r
+TSL_Status_enum_T TSL_linrot_CalcPos(void);\r
+\r
+// Utility functions\r
+void TSL_linrot_SetStateCalibration(TSL_tCounter_T delay);\r
+void TSL_linrot_SetStateOff(void);\r
+#if !defined(TSLPRM_STM8TL5X) && !defined(STM8TL5X)\r
+void TSL_linrot_SetStateBurstOnly(void);\r
+#endif\r
+TSL_StateId_enum_T TSL_linrot_GetStateId(void);\r
+TSL_StateMask_enum_T TSL_linrot_GetStateMask(void);\r
+TSL_tNb_T TSL_linrot_IsChanged(void);\r
+\r
+// State machine functions\r
+void TSL_linrot_CalibrationStateProcess(void);\r
+void TSL_linrot_DebCalibrationStateProcess(void);\r
+void TSL_linrot_ReleaseStateProcess(void);\r
+void TSL_linrot_DebReleaseProxStateProcess(void);\r
+void TSL_linrot_DebReleaseDetectStateProcess(void);\r
+void TSL_linrot_DebReleaseTouchStateProcess(void);\r
+void TSL_linrot_ProxStateProcess(void);\r
+void TSL_linrot_DebProxStateProcess(void);\r
+void TSL_linrot_DebProxDetectStateProcess(void);\r
+void TSL_linrot_DebProxTouchStateProcess(void);\r
+void TSL_linrot_DetectStateProcess(void);\r
+void TSL_linrot_DebDetectStateProcess(void);\r
+void TSL_linrot_TouchStateProcess(void);\r
+void TSL_linrot_DebTouchStateProcess(void);\r
+void TSL_linrot_ErrorStateProcess(void);\r
+void TSL_linrot_DebErrorStateProcess(void);\r
+void TSL_linrot_OffStateProcess(void);\r
+\r
+// Position offset constant tables and corrections\r
+\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_M1[3][3];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_M2[3][3];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_H[3][3];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_3CH_ROT_M[3][3];\r
+\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_M1[4][4];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_M2[4][4];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_H[4][4];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_4CH_ROT_M[4][4];\r
+\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_M1[5][5];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_M2[5][5];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_H[5][5];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_ROT_M[5][5];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_ROT_D[5][5];\r
+\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_M1[6][6];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_M2[6][6];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_H[6][6];\r
+extern CONST TSL_tsignPosition_T TSL_POSOFF_6CH_ROT_M[6][6];\r
+\r
+#define TSL_SCTCOMP_3CH_LIN_M1 (128)\r
+#define TSL_POSCORR_3CH_LIN_M1 (64)\r
+#define TSL_SCTCOMP_3CH_LIN_M2 (256)\r
+#define TSL_POSCORR_3CH_LIN_M2 (256)\r
+\r
+#define TSL_SCTCOMP_3CH_LIN_H (128)\r
+#define TSL_POSCORR_3CH_LIN_H (128)\r
+\r
+#define TSL_SCTCOMP_3CH_ROT_M (85)\r
+\r
+#define TSL_SCTCOMP_4CH_LIN_M1 (85)\r
+#define TSL_POSCORR_4CH_LIN_M1 (43)\r
+#define TSL_SCTCOMP_4CH_LIN_M2 (128)\r
+#define TSL_POSCORR_4CH_LIN_M2 (128)\r
+\r
+#define TSL_SCTCOMP_4CH_LIN_H (85)\r
+#define TSL_POSCORR_4CH_LIN_H (85)\r
+\r
+#define TSL_SCTCOMP_4CH_ROT_M (64)\r
+\r
+#define TSL_SCTCOMP_5CH_LIN_M1 (64)\r
+#define TSL_POSCORR_5CH_LIN_M1 (32)\r
+#define TSL_SCTCOMP_5CH_LIN_M2 (85)\r
+#define TSL_POSCORR_5CH_LIN_M2 (85)\r
+\r
+#define TSL_SCTCOMP_5CH_LIN_H (64)\r
+#define TSL_POSCORR_5CH_LIN_H (64)\r
+\r
+#define TSL_SCTCOMP_5CH_ROT_M (51)\r
+\r
+#define TSL_SCTCOMP_5CH_ROT_D (26)\r
+\r
+#define TSL_SCTCOMP_6CH_LIN_M1 (51)\r
+#define TSL_POSCORR_6CH_LIN_M1 (25)\r
+#define TSL_SCTCOMP_6CH_LIN_M2 (64)\r
+#define TSL_POSCORR_6CH_LIN_M2 (64)\r
+\r
+#define TSL_SCTCOMP_6CH_LIN_H (51)\r
+#define TSL_POSCORR_6CH_LIN_H (51)\r
+\r
+#define TSL_SCTCOMP_6CH_ROT_M (43)\r
+\r
+#endif /* __TSL_LINROT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_object.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_object.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_OBJECT_H\r
+#define __TSL_OBJECT_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_touchkey.h"\r
+#include "tsl_linrot.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+#define TSL_OBJ_TYPE_TKEY_MASK (0x10) /**< TouchKey object mask */\r
+#define TSL_OBJ_TYPE_LINROT_MASK (0x20) /**< Linear and Rotary objects mask */\r
+#define TSL_OBJ_TYPE_TRACKNAV_MASK (0x40) /**< TrackPad and NaviPad objects mask */\r
+\r
+/** Contains all different kinds of sensors.\r
+ */\r
+typedef enum\r
+{\r
+ TSL_OBJ_TOUCHKEY = (TSL_OBJ_TYPE_TKEY_MASK + 0), /**< Normal TouchKey */\r
+ TSL_OBJ_TOUCHKEYB = (TSL_OBJ_TYPE_TKEY_MASK + 1), /**< Basic TouchKey */\r
+ TSL_OBJ_LINEAR = (TSL_OBJ_TYPE_LINROT_MASK + 0), /**< Normal Linear sensor */\r
+ TSL_OBJ_LINEARB = (TSL_OBJ_TYPE_LINROT_MASK + 1), /**< Basic Linear sensor */\r
+ TSL_OBJ_ROTARY = (TSL_OBJ_TYPE_LINROT_MASK + 2), /**< Normal Rotary sensor */\r
+ TSL_OBJ_ROTARYB = (TSL_OBJ_TYPE_LINROT_MASK + 3), /**< Basic Rotary sensor */\r
+ TSL_OBJ_TRACKPAD = (TSL_OBJ_TYPE_TRACKNAV_MASK + 0), /**< TrackPad sensor */\r
+ TSL_OBJ_NAVIPAD = (TSL_OBJ_TYPE_TRACKNAV_MASK + 1) /**< NaviPad sensor */\r
+}\r
+TSL_ObjectType_enum_T;\r
+\r
+/** Contains the definition of an Object.\r
+ * Variables of this structure type can be placed in RAM or ROM.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_ObjectType_enum_T Type; /**< Object type */\r
+ void *Elmt; /**< Pointer to the object */\r
+}\r
+TSL_Object_T;\r
+\r
+/** Contains the definition of a Group of Objects.\r
+ * Variables of this structure type must be placed in RAM only.\r
+ */\r
+typedef struct\r
+{\r
+ CONST TSL_Object_T *p_Obj; /**< Pointer to the first object */\r
+ TSL_tNb_T NbObjects; /**< Number of objects in the group */\r
+ TSL_tNb_T StateMask; /**< "OR" of all objects state mask */\r
+ TSL_StateChange_enum_T Change; /**< The State is different from the previous one */\r
+}\r
+TSL_ObjectGroup_T;\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+void TSL_obj_GroupInit(TSL_ObjectGroup_T *objgrp);\r
+void TSL_obj_GroupProcess(TSL_ObjectGroup_T *objgrp);\r
+void TSL_obj_SetGlobalObj(CONST TSL_Object_T *pobj);\r
+\r
+#endif /* __TSL_OBJECT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_time.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_TIME_H\r
+#define __TSL_TIME_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+#if defined(STM8TL5X)\r
+#include "tsl_acq_stm8tl5x.h"\r
+#include "tsl_time_stm8tl5x.h"\r
+#endif\r
+\r
+#if defined(STM32F0XX)\r
+#include "tsl_acq_stm32f0xx.h"\r
+#include "tsl_time_stm32f0xx.h"\r
+#endif\r
+\r
+#if defined(STM32F30X) || defined(STM32F37X)\r
+#include "tsl_acq_stm32f3xx.h"\r
+#include "tsl_time_stm32f3xx.h"\r
+#endif\r
+\r
+#if defined(STM32L1XX_HD)\r
+#if defined(TSLPRM_STM32L1XX_SW_ACQ)\r
+#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition\r
+#else\r
+#include "tsl_acq_stm32l1xx_hw.h" // Hardware acquisition with Timers (default)\r
+#endif\r
+#include "tsl_time_stm32l1xx.h"\r
+#endif\r
+\r
+#if defined(STM32L1XX_MD)\r
+#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition only\r
+#include "tsl_time_stm32l1xx.h"\r
+#endif\r
+\r
+#if defined(STM32L1XX_MDP)\r
+#if defined(TSLPRM_STM32L1XX_SW_ACQ)\r
+#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition\r
+#else\r
+#include "tsl_acq_stm32l1xx_hw.h" // Hardware acquisition with Timers (default)\r
+#endif\r
+#include "tsl_time_stm32l1xx.h"\r
+#endif\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void TSL_tim_ProcessIT(void);\r
+TSL_Status_enum_T TSL_tim_CheckDelay_ms(TSL_tTick_ms_T delay_ms, __IO TSL_tTick_ms_T *last_tick);\r
+TSL_Status_enum_T TSL_tim_CheckDelay_sec(TSL_tTick_sec_T delay_sec, __IO TSL_tTick_sec_T *last_tick);\r
+void TSL_CallBack_TimerTick(void);\r
+\r
+#endif /* __TSL_TIME_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time_stm32f0xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_time_stm32f0xx.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_TIME_STM32F0XX_H\r
+#define __TSL_TIME_STM32F0XX_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+#include "tsl_conf_stm32f0xx.h"\r
+#include "tsl_types.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+TSL_Status_enum_T TSL_tim_Init(void);\r
+\r
+#endif /* __TSL_TIME_STM32F0XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time_stm32f3xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_time_stm32f3xx.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_TIME_STM32F3XX_H\r
+#define __TSL_TIME_STM32F3XX_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#if defined(STM32F30X)\r
+#include "stm32f30x.h"\r
+#endif\r
+#if defined(STM32F37X)\r
+#include "stm32f37x.h"\r
+#endif\r
+#include "tsl_conf_stm32f3xx.h"\r
+#include "tsl_types.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+TSL_Status_enum_T TSL_tim_Init(void);\r
+\r
+#endif /* __TSL_TIME_STM32F3XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time_stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_time_stm32l1xx.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_TIME_STM32L1XX_H\r
+#define __TSL_TIME_STM32L1XX_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+#include "tsl_conf_stm32l1xx.h"\r
+#include "tsl_types.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+TSL_Status_enum_T TSL_tim_Init(void);\r
+\r
+#endif /* __TSL_TIME_STM32L1XX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time_stm8tl5x.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_time_stm8tl5x.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_TIME_STM8TL5X_H\r
+#define __TSL_TIME_STM8TL5X_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8tl5x.h"\r
+#include "tsl_conf_stm8tl5x.h"\r
+#include "tsl_types.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+TSL_Status_enum_T TSL_tim_Init(void);\r
+\r
+#endif /* __TSL_TIME_STM8TL5X_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_touchkey.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains external declarations of the tsl_touchkey.c file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_TOUCHKEY_H\r
+#define __TSL_TOUCHKEY_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq.h"\r
+#include "tsl_time.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** Contains all data related to TouchKey sensor.\r
+ * Variables of this structure type must be placed in RAM only.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_StateId_enum_T StateId; /**< Current state identifier */\r
+ unsigned int Counter : 6; /**< Generic counter for debounce, calibration & DTO */\r
+ unsigned int Change : 1; /**< The State is different from the previous one (TSL_StateChange_enum_T) */\r
+ unsigned int DxSLock : 1; /**< The State is locked by the DxS (TSL_Bool_enum_T) */\r
+}\r
+TSL_TouchKeyData_T;\r
+\r
+/** Contains all parameters related to TouchKey sensor.\r
+ * Variables of this structure type can be placed in RAM or ROM.\r
+ */\r
+typedef struct\r
+{\r
+#if TSLPRM_USE_PROX > 0\r
+ TSL_tThreshold_T ProxInTh; /**< Proximity in threshold */\r
+ TSL_tThreshold_T ProxOutTh; /**< Proximity out threshold */\r
+#endif\r
+ TSL_tThreshold_T DetectInTh; /**< Detection in threshold */\r
+ TSL_tThreshold_T DetectOutTh; /**< Detection out threshold */\r
+ TSL_tThreshold_T CalibTh; /**< Calibration threshold */\r
+ TSL_tCounter_T CounterDebCalib; /**< Debounce counter to enter in Calibration state */\r
+#if TSLPRM_USE_PROX > 0\r
+ TSL_tCounter_T CounterDebProx; /**< Debounce counter to enter in Proximity state */\r
+#endif\r
+ TSL_tCounter_T CounterDebDetect; /**< Debounce counter to enter in Detect state */\r
+ TSL_tCounter_T CounterDebRelease; /**< Debounce counter to enter in Release state */\r
+ TSL_tCounter_T CounterDebError; /**< Debounce counter to enter in Error state */\r
+}\r
+TSL_TouchKeyParam_T;\r
+\r
+/** Contains definition of a TouchKey sensor.\r
+ * Variables of this structure type can be placed in RAM or ROM.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_TouchKeyData_T *p_Data; /**< Data (state id, counter, flags, ...) */\r
+ TSL_TouchKeyParam_T *p_Param; /**< Parameters (thresholds, debounce, ...) */\r
+ TSL_ChannelData_T *p_ChD; /**< Channel Data (Meas, Ref, Delta, ...) */\r
+ CONST TSL_State_T *p_SM; /**< State Machine */\r
+ CONST TSL_TouchKeyMethods_T *p_Methods; /**< Methods */\r
+}\r
+TSL_TouchKey_T;\r
+\r
+/** Contains definition of a Basic TouchKey sensor.\r
+ * Variables of this structure type can be placed in RAM or ROM.\r
+ * Basic sensor does not contain its own state machine and methods. It used\r
+ * default ones instead to gain memory space.\r
+ */\r
+typedef struct\r
+{\r
+ TSL_TouchKeyData_T *p_Data; /**< Data (state id, counter, flags, ...) */\r
+ TSL_TouchKeyParam_T *p_Param; /**< Parameters (thresholds, debounce, ...) */\r
+ TSL_ChannelData_T *p_ChD; /**< Channel Data (Meas, Ref, Delta, ...) */\r
+}\r
+TSL_TouchKeyB_T;\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+// "Object methods" functions\r
+void TSL_tkey_Init(void);\r
+void TSL_tkey_Process(void);\r
+\r
+// Utility functions\r
+void TSL_tkey_SetStateCalibration(TSL_tCounter_T delay);\r
+void TSL_tkey_SetStateOff(void);\r
+#if !defined(TSLPRM_STM8TL5X) && !defined(STM8TL5X)\r
+void TSL_tkey_SetStateBurstOnly(void);\r
+#endif\r
+TSL_StateId_enum_T TSL_tkey_GetStateId(void);\r
+TSL_StateMask_enum_T TSL_tkey_GetStateMask(void);\r
+TSL_tNb_T TSL_tkey_IsChanged(void);\r
+\r
+// State machine functions\r
+void TSL_tkey_CalibrationStateProcess(void);\r
+void TSL_tkey_DebCalibrationStateProcess(void);\r
+void TSL_tkey_ReleaseStateProcess(void);\r
+void TSL_tkey_DebReleaseProxStateProcess(void);\r
+void TSL_tkey_DebReleaseDetectStateProcess(void);\r
+void TSL_tkey_DebReleaseTouchStateProcess(void);\r
+void TSL_tkey_ProxStateProcess(void);\r
+void TSL_tkey_DebProxStateProcess(void);\r
+void TSL_tkey_DebProxDetectStateProcess(void);\r
+void TSL_tkey_DebProxTouchStateProcess(void);\r
+void TSL_tkey_DetectStateProcess(void);\r
+void TSL_tkey_DebDetectStateProcess(void);\r
+void TSL_tkey_TouchStateProcess(void);\r
+void TSL_tkey_DebTouchStateProcess(void);\r
+void TSL_tkey_ErrorStateProcess(void);\r
+void TSL_tkey_DebErrorStateProcess(void);\r
+void TSL_tkey_OffStateProcess(void);\r
+\r
+#endif /* __TSL_TOUCHKEY_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_types.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all general structures definition.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_TYPES_H\r
+#define __TSL_TYPES_H\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** Generic Boolean status\r
+*/\r
+typedef enum\r
+{\r
+ TSL_FALSE = 0, /**< A False value */\r
+ TSL_TRUE = 1 /**< A True value */\r
+}\r
+TSL_Bool_enum_T;\r
+\r
+/** Generic status returned by functions\r
+*/\r
+typedef enum\r
+{\r
+ TSL_STATUS_OK = 0, /**< The function has been executed correctly */\r
+ TSL_STATUS_BUSY = 1, /**< The function is in a Busy state */\r
+ TSL_STATUS_ERROR = 2 /**< The function has been executed not correctly */\r
+} TSL_Status_enum_T;\r
+\r
+/** DataReady status : 1 bit\r
+ - Used by acquisition to indicate if a new measurement is ready or not.\r
+*/\r
+typedef enum\r
+{\r
+ TSL_DATA_NOT_READY = 0, /**< No new measurement or measurement treated */\r
+ TSL_DATA_READY = 1 /**< A new measurement is ready */\r
+} TSL_DataReady_enum_T;\r
+\r
+/** State change status\r
+*/\r
+typedef enum\r
+{\r
+ TSL_STATE_NOT_CHANGED = 0, /**< The object has the same state */\r
+ TSL_STATE_CHANGED = 1 /**< The object has changed of state */\r
+} TSL_StateChange_enum_T;\r
+\r
+#define TSL_ACQ_STATUS_ERROR_MASK (0x02) /**< Associated to TSL_AcqStatus_enum_T */\r
+\r
+/** Acquisition status\r
+*/\r
+typedef enum\r
+{\r
+ TSL_ACQ_STATUS_OK = 0, /**< The acquisition is correct */\r
+ TSL_ACQ_STATUS_NOISE = 1, /**< Noise detected during the acquisition */\r
+ TSL_ACQ_STATUS_ERROR_MIN = TSL_ACQ_STATUS_ERROR_MASK, /**< The measure is below the minimum threshold */\r
+ TSL_ACQ_STATUS_ERROR_MAX = (TSL_ACQ_STATUS_ERROR_MASK | 0x01) /**< The measure is above the maximum threshold */\r
+} TSL_AcqStatus_enum_T;\r
+\r
+/** Bank status\r
+*/\r
+typedef enum\r
+{\r
+ TSL_BANK_STATUS_DISABLED = 0, /**< The bank is disabled */\r
+ TSL_BANK_STATUS_ENABLED = 1 /**< The bank is enabled */\r
+} TSL_BankStatus_enum_T;\r
+\r
+/** Zone status\r
+*/\r
+typedef enum\r
+{\r
+ TSL_ZONE_STATUS_DISABLED = 0, /**< The zone is disabled */\r
+ TSL_ZONE_STATUS_ENABLED = 1 /**< The zone is enabled */\r
+}TSL_ZoneStatus_enum_T;\r
+\r
+#define TSL_OBJ_STATUS_ACQ_MASK (0x01) /**< Associated to TSL_ObjStatus_enum_T */\r
+#define TSL_OBJ_STATUS_BURST_MASK (0x02) /**< Associated to TSL_ObjStatus_enum_T */\r
+\r
+/** Object status\r
+*/\r
+typedef enum\r
+{\r
+ TSL_OBJ_STATUS_OFF = 0, /**< No burst and no acquisition */\r
+ TSL_OBJ_STATUS_BURST_ONLY = TSL_OBJ_STATUS_BURST_MASK, /**< Burst only */\r
+ TSL_OBJ_STATUS_ON = (TSL_OBJ_STATUS_BURST_MASK | TSL_OBJ_STATUS_ACQ_MASK) /**< Burst and acquisition */\r
+} TSL_ObjStatus_enum_T;\r
+\r
+#define TSL_STATE_ERROR_BIT_MASK (0x80) /**< Associated to TSL_StateMask_enum_T */\r
+#define TSL_STATE_OFF_BIT_MASK (0x40) /**< Associated to TSL_StateMask_enum_T */\r
+#define TSL_STATE_DEBOUNCE_BIT_MASK (0x20) /**< Associated to TSL_StateMask_enum_T */\r
+#define TSL_STATE_CALIB_BIT_MASK (0x10) /**< Associated to TSL_StateMask_enum_T */\r
+#define TSL_STATE_TOUCH_BIT_MASK (0x08) /**< Associated to TSL_StateMask_enum_T */\r
+#define TSL_STATE_DETECT_BIT_MASK (0x04) /**< Associated to TSL_StateMask_enum_T */\r
+#define TSL_STATE_PROX_BIT_MASK (0x02) /**< Associated to TSL_StateMask_enum_T */\r
+#define TSL_STATE_RELEASE_BIT_MASK (0x01) /**< Associated to TSL_StateMask_enum_T */\r
+\r
+/** Object state masks\r
+*/\r
+typedef enum\r
+{\r
+ // Calibration states\r
+ TSL_STATEMASK_CALIB = TSL_STATE_CALIB_BIT_MASK, /**< 0x10 */\r
+ TSL_STATEMASK_DEB_CALIB = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_CALIB_BIT_MASK), /**< 0x30 */\r
+ // Release states\r
+ TSL_STATEMASK_RELEASE = TSL_STATE_RELEASE_BIT_MASK, /**< 0x01 */\r
+ TSL_STATEMASK_DEB_RELEASE_PROX = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_RELEASE_BIT_MASK | TSL_STATE_PROX_BIT_MASK), /**< 0x23 */\r
+ TSL_STATEMASK_DEB_RELEASE_DETECT = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_RELEASE_BIT_MASK | TSL_STATE_DETECT_BIT_MASK), /**< 0x25 */\r
+ TSL_STATEMASK_DEB_RELEASE_TOUCH = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_RELEASE_BIT_MASK | TSL_STATE_TOUCH_BIT_MASK), /**< 0x29 */\r
+ // Proximity states\r
+ TSL_STATEMASK_PROX = TSL_STATE_PROX_BIT_MASK, /**< 0x02 */\r
+ TSL_STATEMASK_DEB_PROX = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_PROX_BIT_MASK), /**< 0x22 */\r
+ TSL_STATEMASK_DEB_PROX_DETECT = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_PROX_BIT_MASK | TSL_STATE_DETECT_BIT_MASK), /**< 0x26 */\r
+ TSL_STATEMASK_DEB_PROX_TOUCH = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_PROX_BIT_MASK | TSL_STATE_TOUCH_BIT_MASK), /**< 0x2A */\r
+ // Detect states\r
+ TSL_STATEMASK_DETECT = TSL_STATE_DETECT_BIT_MASK, /**< 0x04 */\r
+ TSL_STATEMASK_DEB_DETECT = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_DETECT_BIT_MASK), /**< 0x24 */\r
+ // Touch state\r
+ TSL_STATEMASK_TOUCH = TSL_STATE_TOUCH_BIT_MASK, /**< 0x08 */\r
+ // Error states\r
+ TSL_STATEMASK_ERROR = TSL_STATE_ERROR_BIT_MASK, /**< 0x80 */\r
+ TSL_STATEMASK_DEB_ERROR_CALIB = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_CALIB_BIT_MASK), /**< 0xB0 */\r
+ TSL_STATEMASK_DEB_ERROR_RELEASE = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_RELEASE_BIT_MASK), /**< 0xA1 */\r
+ TSL_STATEMASK_DEB_ERROR_PROX = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_PROX_BIT_MASK), /**< 0xA2 */\r
+ TSL_STATEMASK_DEB_ERROR_DETECT = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_DETECT_BIT_MASK), /**< 0xA4 */\r
+ TSL_STATEMASK_DEB_ERROR_TOUCH = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_TOUCH_BIT_MASK), /**< 0xA8 */\r
+ // OFF state\r
+ TSL_STATEMASK_OFF = TSL_STATE_OFF_BIT_MASK, /**< 0x40 */\r
+ // Other states not associated to a state id\r
+ TSL_STATEMASK_ACTIVE = (TSL_STATE_PROX_BIT_MASK | TSL_STATE_DETECT_BIT_MASK | TSL_STATE_TOUCH_BIT_MASK | TSL_STATE_CALIB_BIT_MASK | TSL_STATE_DEBOUNCE_BIT_MASK), /**< 0x3E */\r
+ TSL_STATEMASK_UNKNOWN = 0 /**< 0x00 */\r
+} TSL_StateMask_enum_T;\r
+\r
+/** Object state identifiers\r
+*/\r
+typedef enum\r
+{\r
+ // Calibration states\r
+ TSL_STATEID_CALIB = 0, /**< 0 - Object is in Calibration */\r
+ TSL_STATEID_DEB_CALIB = 1, /**< 1 - Object is in Debounce Calibration */\r
+ // Release states\r
+ TSL_STATEID_RELEASE = 2, /**< 2 - Object is released */\r
+ TSL_STATEID_DEB_RELEASE_PROX = 3, /**< 3 - Object is in Debounce Release from Proximity state */\r
+ TSL_STATEID_DEB_RELEASE_DETECT = 4, /**< 4 - Object is in Debounce Release from Detect state */\r
+ TSL_STATEID_DEB_RELEASE_TOUCH = 5, /**< 5 - Object is in Debounce Release from Touch state */\r
+ // Proximity states\r
+ TSL_STATEID_PROX = 6, /**< 6 - Object is in Proximity */\r
+ TSL_STATEID_DEB_PROX = 7, /**< 7 - Object is in Debounce Proximity from Release state */\r
+ TSL_STATEID_DEB_PROX_DETECT = 8, /**< 8 - Object is in Debounce Proximity from Detect state */\r
+ TSL_STATEID_DEB_PROX_TOUCH = 9, /**< 9 - Object is in Debounce Proximity from Detect state */\r
+ // Detect states\r
+ TSL_STATEID_DETECT = 10, /**< 10 - Object is in Detect */\r
+ TSL_STATEID_DEB_DETECT = 11, /**< 11 - Object is in Debounce Detect */\r
+ // Touch state\r
+ TSL_STATEID_TOUCH = 12, /**< 12 - Object is in Touch */\r
+ // Error states\r
+ TSL_STATEID_ERROR = 13, /**< 13 - Object is in Error */\r
+ TSL_STATEID_DEB_ERROR_CALIB = 14, /**< 14 - Object is in Debounce Error from Calibration */\r
+ TSL_STATEID_DEB_ERROR_RELEASE = 15, /**< 15 - Object is in Debounce Error from Release */\r
+ TSL_STATEID_DEB_ERROR_PROX = 16, /**< 16 - Object is in Debounce Error from Proximity */\r
+ TSL_STATEID_DEB_ERROR_DETECT = 17, /**< 17 - Object is in Debounce Error from Detect */\r
+ TSL_STATEID_DEB_ERROR_TOUCH = 18, /**< 18 - Object is in Debounce Error from Touch */\r
+ // Other states\r
+ TSL_STATEID_OFF = 19 /**< 19 - Object is OFF (no burst, no acquisition) */\r
+} TSL_StateId_enum_T;\r
+\r
+/** Object state\r
+*/\r
+typedef struct\r
+{\r
+ TSL_StateMask_enum_T StateMask; /**< Current state mask */\r
+ void(* StateFunc)(void); /**< Function executed in the state */\r
+}\r
+TSL_State_T;\r
+\r
+/** Touchkey methods\r
+*/\r
+typedef struct\r
+{\r
+ void(* Init)(void); /**< Used to initialize the TouchKey sensor */\r
+ void(* Process)(void); /**< Used to execute the TouchKey sensor state machine */\r
+}\r
+TSL_TouchKeyMethods_T;\r
+\r
+/** Linear/Rotary methods\r
+*/\r
+typedef struct\r
+{\r
+ void(* Init)(void); /**< Used to initialize the Linear/Rotary sensor */\r
+ void(* Process)(void); /**< Used to execute the Linear/Rotary sensor state machine */\r
+ TSL_Status_enum_T(* CalcPosition)(void); /**< Used to calculate the Linear/Rotary sensor position */\r
+}\r
+TSL_LinRotMethods_T;\r
+\r
+#endif /* __TSL_TYPES_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains the STMTouch Driver main functions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initializes the TS interface.\r
+ * @param bank Array holding all the banks\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_Init(CONST TSL_Bank_T *bank)\r
+{\r
+ TSL_Status_enum_T retval;\r
+\r
+ // Get banks array\r
+ TSL_Globals.Bank_Array = bank;\r
+\r
+ // Initialization of the timing module\r
+ retval = TSL_tim_Init();\r
+\r
+ if (retval == TSL_STATUS_OK)\r
+ {\r
+ // Initialization of the acquisition module\r
+ retval = TSL_acq_Init();\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the acquisition in general.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq.h"\r
+#include "tsl_globals.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Read all channels measurement of a Bank, calculate Delta\r
+ * @param[in] idx_bk Index of the Bank to access\r
+ * @param[in] mfilter Pointer to the Measure filter function\r
+ * @param[in] dfilter Pointer to the Delta filter function\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankGetResult(TSL_tIndex_T idx_bk, TSL_pFuncMeasFilter_T mfilter, TSL_pFuncDeltaFilter_T dfilter)\r
+{\r
+ TSL_Status_enum_T retval = TSL_STATUS_OK;\r
+ TSL_tIndex_T idx_ch;\r
+ TSL_tIndexDest_T idx_dest;\r
+ TSL_tMeas_T old_meas, new_meas;\r
+ TSL_tDelta_T new_delta;\r
+ CONST TSL_Bank_T *bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ CONST TSL_ChannelDest_T *pchDest = bank->p_chDest;\r
+ CONST TSL_ChannelSrc_T *pchSrc = bank->p_chSrc;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ // For all channels in the bank copy the measure + calculate delta and store them.\r
+ for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)\r
+ {\r
+\r
+ // Get the Destination Index of the current channel\r
+ idx_dest = pchDest->IdxDest;\r
+\r
+ if (bank->p_chData[idx_dest].Flags.ObjStatus == TSL_OBJ_STATUS_ON)\r
+ {\r
+\r
+ // Initialize flag to inform the Object of that a new data is ready\r
+ bank->p_chData[idx_dest].Flags.DataReady = TSL_DATA_READY;\r
+\r
+ // Get the new measure (the access is different between acquisitions)\r
+ new_meas = TSL_acq_GetMeas(pchSrc->IdxSrc);\r
+\r
+ // Store last measure for the filter below\r
+#if TSLPRM_USE_MEAS > 0\r
+ old_meas = bank->p_chData[idx_dest].Meas;\r
+#else\r
+ old_meas = new_meas;\r
+#endif\r
+\r
+ // Store the new measure\r
+#if TSLPRM_USE_MEAS > 0\r
+ bank->p_chData[idx_dest].Meas = new_meas;\r
+#endif\r
+\r
+ // Check acquisition value min/max and set acquisition status flag\r
+ if (new_meas < TSL_Params.AcqMin)\r
+ {\r
+ bank->p_chData[idx_dest].Flags.AcqStatus = TSL_ACQ_STATUS_ERROR_MIN;\r
+ bank->p_chData[idx_dest].Delta = 0;\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ if (new_meas > TSL_Params.AcqMax)\r
+ {\r
+ bank->p_chData[idx_dest].Flags.AcqStatus = TSL_ACQ_STATUS_ERROR_MAX;\r
+ bank->p_chData[idx_dest].Delta = 0;\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+ else // The measure is OK\r
+ {\r
+ if (TSL_acq_UseFilter(&bank->p_chData[idx_dest]))\r
+ {\r
+ // Apply Measure filter if it exists\r
+ if (mfilter)\r
+ {\r
+ new_meas = mfilter(old_meas, new_meas);\r
+ // Store the measure (optional - used for debug purpose)\r
+#if TSLPRM_USE_MEAS > 0\r
+ bank->p_chData[idx_dest].Meas = new_meas;\r
+#endif\r
+ }\r
+\r
+ // Calculate the new Delta\r
+ new_delta = TSL_acq_ComputeDelta(bank->p_chData[idx_dest].Ref, new_meas);\r
+\r
+ // Check Noise (TSL_ACQ_STATUS_OK if no Noise or if Noise detection is not supported)\r
+ bank->p_chData[idx_dest].Flags.AcqStatus = TSL_acq_CheckNoise();\r
+\r
+ // Apply Delta filter if it exists\r
+ if (dfilter)\r
+ {\r
+ bank->p_chData[idx_dest].Delta = dfilter(new_delta);\r
+ }\r
+ else\r
+ {\r
+ bank->p_chData[idx_dest].Delta = new_delta;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ // Calculate the new Delta\r
+ bank->p_chData[idx_dest].Delta = TSL_acq_ComputeDelta(bank->p_chData[idx_dest].Ref, new_meas);\r
+\r
+ // Check Noise (TSL_ACQ_STATUS_OK if no Noise or if Noise detection is not supported)\r
+ bank->p_chData[idx_dest].Flags.AcqStatus = TSL_acq_CheckNoise();\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ // Next channel\r
+ pchDest++;\r
+ pchSrc++;\r
+\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Calibrate a Bank\r
+ * @param[in] idx_bk Index of the Bank to access\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankCalibrate(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_Status_enum_T retval;\r
+ TSL_Status_enum_T acq_status;\r
+ TSL_tIndex_T idx_ch;\r
+ TSL_tIndexDest_T idx_dest;\r
+ TSL_tMeas_T new_meas;\r
+ static TSL_tIndex_T calibration_ongoing = 0;\r
+ static TSL_tNb_T calibration_done = 0;\r
+ static TSL_tNb_T div;\r
+ CONST TSL_Bank_T *bank;\r
+ CONST TSL_ChannelDest_T *pchDest; // Pointer to the current channel\r
+ CONST TSL_ChannelSrc_T *pchSrc; // Pointer to the current channel\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+\r
+ if (calibration_ongoing == 0)\r
+ {\r
+ switch (TSL_Params.NbCalibSamples)\r
+ {\r
+ case 4:\r
+ div = 2;\r
+ break;\r
+ case 16:\r
+ div = 4;\r
+ break;\r
+ default:\r
+ TSL_Params.NbCalibSamples = 8;\r
+ div = 3;\r
+ break;\r
+ }\r
+ // Clear data for all channels of the bank\r
+ TSL_acq_BankClearData(idx_bk);\r
+ // Configure bank\r
+ if (TSL_acq_BankConfig(idx_bk) == TSL_STATUS_OK)\r
+ {\r
+ // Start acquisition\r
+ TSL_acq_BankStartAcq();\r
+ calibration_ongoing = 1; // Calibration started\r
+ calibration_done = TSL_Params.NbCalibSamples;\r
+ retval = TSL_STATUS_BUSY;\r
+ }\r
+ else\r
+ {\r
+ // Stop calibration\r
+ // Clear data for all channels of the bank\r
+ TSL_acq_BankClearData(idx_bk);\r
+ calibration_ongoing = 0;\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+\r
+ }\r
+ else // Calibration is on-going\r
+ {\r
+ // Check End of Acquisition\r
+ acq_status = TSL_acq_BankWaitEOC();\r
+ if (acq_status == TSL_STATUS_OK)\r
+ {\r
+\r
+ // Get the first channel of the bank\r
+ pchDest = bank->p_chDest;\r
+ pchSrc = bank->p_chSrc;\r
+\r
+ // Get new measurement for all channels of the bank\r
+ for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)\r
+ {\r
+\r
+ // Get index of the current channel\r
+ idx_dest = pchDest->IdxDest;\r
+\r
+ // Get the new measure (the access is different between acquisitions)\r
+ new_meas = TSL_acq_GetMeas(pchSrc->IdxSrc);\r
+\r
+ // Check min/max and set status flag\r
+ if ((new_meas < TSL_Params.AcqMin) || (new_meas > TSL_Params.AcqMax))\r
+ {\r
+ // Stop calibration\r
+ // Clear data for all channels of the bank\r
+ TSL_acq_BankClearData(idx_bk);\r
+ calibration_ongoing = 0;\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ // Add the measure\r
+ bank->p_chData[idx_dest].Ref += new_meas;\r
+ }\r
+\r
+ // Next channel\r
+ pchDest++;\r
+ pchSrc++;\r
+ }\r
+\r
+ // Check that we have all the needed measurements\r
+ calibration_done--;\r
+ if (calibration_done == 0)\r
+ {\r
+\r
+ // Get the first channel of the bank\r
+ pchDest = bank->p_chDest;\r
+\r
+ // Calculate the Reference for all channels of the bank\r
+ for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)\r
+ {\r
+ // Get index of the current channel\r
+ idx_dest = pchDest->IdxDest;\r
+ // Divide the Reference by the number of samples\r
+ bank->p_chData[idx_dest].Ref >>= div;\r
+ // Next channel\r
+ pchDest++;\r
+ }\r
+\r
+ // End\r
+ calibration_ongoing = 0;\r
+ retval = TSL_STATUS_OK;\r
+ }\r
+ else // Restart a new measurement on the bank\r
+ {\r
+ TSL_acq_BankStartAcq();\r
+ retval = TSL_STATUS_BUSY;\r
+ }\r
+ }\r
+ else\r
+ if (acq_status == TSL_STATUS_ERROR)\r
+ {\r
+ // Stop calibration\r
+ // Clear data for all channels of the bank\r
+ TSL_acq_BankClearData(idx_bk);\r
+ calibration_ongoing = 0;\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ retval = TSL_STATUS_BUSY;\r
+ }\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clear Reference and Delta on all channels of a Bank\r
+ * @param[in] idx_bk Index of the Bank to access\r
+ * @retval None\r
+ */\r
+void TSL_acq_BankClearData(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_tIndex_T idx_ch;\r
+ TSL_tIndexDest_T idx_Dest;\r
+ CONST TSL_Bank_T *bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ CONST TSL_ChannelDest_T *pchDest = bank->p_chDest;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ // For all channels of the bank\r
+ for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)\r
+ {\r
+ idx_Dest = pchDest->IdxDest;\r
+ bank->p_chData[idx_Dest].Ref = 0;\r
+ bank->p_chData[idx_Dest].Delta = 0;\r
+ pchDest++; // Next channel\r
+ }\r
+}\r
+\r
+\r
+#if TSLPRM_USE_ZONE > 0\r
+\r
+/**\r
+ * @brief Configures a Zone.\r
+ * @param[in] zone Zone to configure\r
+ * @param[in] idx_bk Bank index in the zone to configure\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_ZoneConfig(CONST TSL_Zone_T *zone, TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_Status_enum_T retval;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ TSL_Globals.This_Zone = zone;\r
+\r
+ do\r
+ {\r
+ retval = TSL_acq_BankConfig(zone->BankIndex[idx_bk]);\r
+ TSL_Globals.This_Bank = zone->BankIndex[idx_bk];\r
+ idx_bk++;\r
+ }\r
+ while ((idx_bk < zone->NbBanks) && (retval == TSL_STATUS_ERROR));\r
+\r
+ TSL_Globals.Index_In_This_Zone = idx_bk;\r
+\r
+#if TSLPRM_PXS_LOW_POWER_MODE > 0\r
+ if (idx_bk < zone->NbBanks)\r
+ {\r
+ resetPXSLowPower();\r
+ }\r
+#endif\r
+\r
+ return(retval);\r
+\r
+}\r
+\r
+#endif\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm32f0xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the TSC acquisition\r
+ * on STM32F0xx products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq_stm32f0xx.h"\r
+#include "tsl_globals.h"\r
+#include "stm32f0xx_it.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+#define TSL_DELAY_DISCHARGE (1000)\r
+\r
+#define NU (0) // Not Used IO\r
+#define CHANNEL (1) // Channel IO\r
+#define SHIELD (2) // Shield IO (= Channel IO but not acquired)\r
+#define SAMPCAP (3) // Sampling Capacitor IO\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))\r
+#define IS_SOURCE_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_CHANNELS)))\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+void SoftDelay(uint32_t val);\r
+\r
+/**\r
+ * @brief Initializes the TouchSensing GPIOs.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_InitGPIOs(void)\r
+{\r
+\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ uint32_t tmp_value_0;\r
+ uint32_t tmp_value_1;\r
+\r
+ //====================\r
+ // GPIOs configuration\r
+ //====================\r
+\r
+ // Enable GPIOs clocks\r
+ RCC->AHBENR |= (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN);\r
+\r
+ // Alternate function Output Open-Drain for Sampling Capacitor IOs\r
+ //----------------------------------------------------------------\r
+\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+\r
+ // GPIOA\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if TSLPRM_TSC_GROUP1_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_9;\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_10;\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOA, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOB\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if TSLPRM_TSC_GROUP3_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOC\r
+#if TSLPRM_TSC_GROUP3_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;\r
+ GPIO_Init(GPIOC, &GPIO_InitStructure);\r
+#endif\r
+\r
+ // Alternate function Output Push-Pull for Channel and Shield IOs\r
+ //---------------------------------------------------------------\r
+\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+\r
+ // GPIOA\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if (TSLPRM_TSC_GROUP1_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP1_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP1_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP1_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP2_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP2_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP2_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP2_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP4_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_9;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP4_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_10;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP4_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP4_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOA, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOB\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if (TSLPRM_TSC_GROUP3_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP3_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP3_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOC\r
+#if (TSLPRM_TSC_GROUP3_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;\r
+ GPIO_Init(GPIOC, &GPIO_InitStructure);\r
+#endif\r
+\r
+ // Set Alternate-Function AF3 for GPIOA and GPIOB\r
+ //-----------------------------------------------\r
+\r
+ // GPIOA\r
+ tmp_value_0 = 0;\r
+ tmp_value_1 = 0;\r
+#if TSLPRM_TSC_GROUP1_IO1 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (0 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (1 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (2 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO1 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (7 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO1 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (1 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO2 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (2 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO3 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO4 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+ if (tmp_value_0 != 0) {GPIOA->AFR[0] |= tmp_value_0;}\r
+ if (tmp_value_1 != 0) {GPIOA->AFR[1] |= tmp_value_1;}\r
+\r
+ // GPIOB\r
+ tmp_value_0 = 0;\r
+ tmp_value_1 = 0;\r
+#if TSLPRM_TSC_GROUP3_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (0 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (1 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (2 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (7 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO3 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+ if (tmp_value_0 != 0) {GPIOB->AFR[0] |= tmp_value_0;}\r
+ if (tmp_value_1 != 0) {GPIOB->AFR[1] |= tmp_value_1;}\r
+\r
+ //==================\r
+ // TSC configuration\r
+ //==================\r
+\r
+ // Enable TSC clock\r
+ RCC->AHBENR |= RCC_AHBENR_TSEN;\r
+\r
+ // Disable Schmitt trigger hysteresis on all used TS IOs (Channel, Shield and Sampling IOs)\r
+ //-----------------------------------------------------------------------------------------\r
+\r
+ tmp_value_0 = 0xFFFFFFFF;\r
+#if TSLPRM_TSC_GROUP1_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 0);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 1);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 2);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 3);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 4);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 5);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 6);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 7);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 8);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 9);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 10);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 11);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 12);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 13);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 14);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 15);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 16);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 17);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 18);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 19);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 20);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 21);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 22);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 23);\r
+#endif\r
+ if (tmp_value_0 != 0xFFFFFFFF) {TSC->IOHCR &= tmp_value_0;}\r
+\r
+ // Set Sampling Capacitor IOs\r
+ //---------------------------\r
+\r
+ tmp_value_0 = 0;\r
+#if TSLPRM_TSC_GROUP1_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 0);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 1);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 2);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 3);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 4);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 5);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 6);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 7);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 8);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 9);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 10);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 11);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 12);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 13);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 14);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 15);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 16);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 17);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 18);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 19);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 20);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 21);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 22);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 23);\r
+#endif\r
+ if (tmp_value_0 != 0) {TSC->IOSCR |= tmp_value_0;}\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the acquisition module.\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_Init(void)\r
+{\r
+\r
+#if TSLPRM_TSC_GPIO_CONFIG > 0\r
+ TSL_acq_InitGPIOs();\r
+#endif\r
+\r
+ // Enable TSC clock\r
+ RCC->AHBENR |= RCC_AHBENR_TSEN;\r
+\r
+ // TSC enabled\r
+ TSC->CR = 0x01;\r
+\r
+ // Set CTPH\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPH << 28) & 0xF0000000;\r
+\r
+ // Set CTPL\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPL << 24) & 0x0F000000;\r
+\r
+ // Set SpreadSpectrum\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_USE_SS << 16) & 0x00010000;\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSD << 17) & 0x00FE0000;\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSPSC << 15) & 0x00008000;\r
+\r
+ // Set Prescaler\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_PGPSC << 12) & 0x00007000;\r
+\r
+ // Set Max Count\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_MCV << 5) & 0x000000E0;\r
+\r
+ // Set IO default in Output PP Low to discharge all capacitors\r
+ TSC->CR &= (uint32_t)(~(1 << 4));\r
+\r
+ // Set Synchronization Mode\r
+#if TSLPRM_TSC_AM > 0\r
+\r
+ // Set Synchronization Pin in Alternate-Function mode\r
+ RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // Set GPIOB clock\r
+\r
+#if TSLPRM_TSC_SYNC_PIN == 0 // PB08\r
+ GPIOB->MODER &= 0xFFFCFFFF;\r
+ GPIOB->MODER |= 0x00020000;\r
+ GPIOB->AFR[1] |= 0x00000003;\r
+#else // PB10\r
+ GPIOB->MODER &= 0xFFCFFFFF;\r
+ GPIOB->MODER |= 0x00200000;\r
+ GPIOB->AFR[1] |= 0x00000300;\r
+#endif\r
+\r
+ // Set Synchronization Polarity\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SYNC_POL << 3) & 0x00000008;\r
+\r
+#endif\r
+\r
+ // Set acquisition mode\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_AM << 2) & 0x00000004;\r
+\r
+#if TSLPRM_USE_ACQ_INTERRUPT > 0\r
+\r
+ // Set both EOA and MCE interrupts\r
+ TSC->IER |= 0x03;\r
+\r
+ // Configure NVIC\r
+ NVIC_SetPriority(TS_IRQn, 0);\r
+ NVIC_EnableIRQ(TS_IRQn);\r
+\r
+#endif\r
+\r
+ return TSL_STATUS_OK;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures a Bank.\r
+ * @param[in] idx_bk Index of the Bank to configure\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_tIndex_T idx_ch;\r
+ uint32_t objs; /* bit field of TSL_ObjStatus_enum_T type */\r
+ uint32_t gx;\r
+ uint32_t ioy;\r
+ CONST TSL_Bank_T *bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ CONST TSL_ChannelSrc_T *pchSrc = bank->p_chSrc;\r
+ CONST TSL_ChannelDest_T *pchDest = bank->p_chDest;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ // Mark the current bank processed\r
+ TSL_Globals.This_Bank = idx_bk;\r
+\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ // Enable the Gx_IOy used as channels (channels + shield)\r
+ TSC->IOCCR = bank->msk_IOCCR_channels;\r
+ // Enable acquisition on selected Groups\r
+ TSC->IOGCSR = bank->msk_IOGCSR_groups;\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+ // For all channels of the bank check if they are OFF or BURST_ONLY\r
+ // and set acquisition status flag\r
+ for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)\r
+ {\r
+\r
+ // Check Object status flag\r
+ objs = bank->p_chData[pchDest->IdxDest].Flags.ObjStatus;\r
+\r
+ if (objs != TSL_OBJ_STATUS_ON)\r
+ {\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ // Get the Channel Group mask\r
+ gx = pchSrc->msk_IOGCSR_group;\r
+ // Stop acquisition of the Group\r
+ TSC->IOGCSR &= (uint32_t)~gx;\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+ if (objs == TSL_OBJ_STATUS_OFF)\r
+ {\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ // Get the Channel IO mask\r
+ ioy = pchSrc->msk_IOCCR_channel;\r
+ // Stop Burst of the Channel\r
+ TSC->IOCCR &= (uint32_t)~ioy;\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ }\r
+ }\r
+\r
+ // Next channel\r
+ pchSrc++;\r
+ pchDest++;\r
+ }\r
+\r
+ return TSL_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Start acquisition on a previously configured bank\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_BankStartAcq(void)\r
+{\r
+ // Clear both EOAIC and MCEIC flags\r
+ TSC->ICR |= 0x03;\r
+\r
+ // Wait capacitors discharge\r
+ SoftDelay(TSL_DELAY_DISCHARGE);\r
+\r
+#if TSLPRM_TSC_IODEF > 0 // Default = Input Floating\r
+ // Set IO default in Input Floating\r
+ TSC->CR |= (1 << 4);\r
+#endif\r
+\r
+ // Start acquisition\r
+ TSC->CR |= 0x02;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Wait end of acquisition\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void)\r
+{\r
+ TSL_Status_enum_T retval = TSL_STATUS_BUSY;\r
+\r
+ // Check EOAF flag\r
+ if (TSC->ISR & 0x01)\r
+ {\r
+\r
+#if TSLPRM_TSC_IODEF > 0 // Default = Input Floating\r
+ // Set IO default in Output PP Low to discharge all capacitors\r
+ TSC->CR &= (uint32_t)(~(1 << 4));\r
+#endif\r
+\r
+ // Check MCEF flag\r
+ if (TSC->ISR & 0x02)\r
+ {\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ retval = TSL_STATUS_OK;\r
+ }\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the current measure\r
+ * @param[in] index Index of the measure source\r
+ * @retval Measure\r
+ */\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index)\r
+{\r
+ return(TSC->IOGXCR[index]);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Compute the Delta value\r
+ * @param[in] ref Reference value\r
+ * @param[in] meas Last Measurement value\r
+ * @retval Delta value\r
+ */\r
+TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas)\r
+{\r
+ return((TSL_tDelta_T)(ref - meas));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Compute the Measurement value\r
+ * @param[in] ref Reference value\r
+ * @param[in] delta Delta value\r
+ * @retval Measurement value\r
+ */\r
+TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta)\r
+{\r
+ return((TSL_tMeas_T)(ref - delta));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check noise (not used)\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void)\r
+{\r
+ return TSL_ACQ_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a filter must be used on the current channel (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @retval Result TRUE if a filter can be applied\r
+ */\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh)\r
+{\r
+ return TSL_TRUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if the Reference is incorrect (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @retval Result TRUE if the Reference is out of range\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh)\r
+{\r
+ return TSL_FALSE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if the measure has crossed the reference target (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @param[in] new_meas Measure of the last acquisition on this channel\r
+ * @retval Result TRUE if the Reference is valid\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas)\r
+{\r
+ return TSL_TRUE;\r
+}\r
+\r
+\r
+#if defined(__IAR_SYSTEMS_ICC__) // IAR/EWARM\r
+#pragma optimize=low\r
+#elif defined(__CC_ARM) // Keil/MDK-ARM\r
+#pragma O1\r
+#pragma Ospace\r
+#elif defined(__TASKING__) // Altium/Tasking\r
+#pragma optimize O0\r
+#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit\r
+#pragma GCC push_options\r
+#pragma GCC optimize ("O0")\r
+#endif\r
+/**\r
+ * @brief Software delay (private routine)\r
+ * @param val Wait delay\r
+ * @retval None\r
+ */\r
+void SoftDelay(uint32_t val)\r
+{\r
+ __IO uint32_t i;\r
+ for (i = val; i > 0; i--)\r
+ {}\r
+}\r
+#if defined(__TASKING__)\r
+#pragma endoptimize\r
+#endif\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm32f3xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the TSC acquisition\r
+ * on STM32F3xx products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq_stm32f3xx.h"\r
+#include "tsl_globals.h"\r
+#if defined(STM32F30X)\r
+#include "stm32f30x_it.h"\r
+#endif\r
+#if defined(STM32F37X)\r
+#include "stm32f37x_it.h"\r
+#endif\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+#define TSL_DELAY_DISCHARGE (1000)\r
+\r
+#define NU (0) // Not Used IO\r
+#define CHANNEL (1) // Channel IO\r
+#define SHIELD (2) // Shield IO (= Channel IO but not acquired)\r
+#define SAMPCAP (3) // Sampling Capacitor IO\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))\r
+#define IS_SOURCE_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_CHANNELS)))\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+void SoftDelay(uint32_t val);\r
+\r
+/**\r
+ * @brief Initializes the TouchSensing GPIOs.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_InitGPIOs(void)\r
+{\r
+\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ uint32_t tmp_value_0;\r
+ uint32_t tmp_value_1;\r
+\r
+ //====================\r
+ // GPIOs configuration\r
+ //====================\r
+\r
+ // Enable GPIOs clocks\r
+ RCC->AHBENR |= (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN);\r
+\r
+ // Alternate function Output Open-Drain for Sampling Capacitor IOs\r
+ //----------------------------------------------------------------\r
+\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+\r
+ // GPIOA\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if TSLPRM_TSC_GROUP1_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_9;\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_10;\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOA, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOB\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+\r
+#if defined(STM32F30X)\r
+#if TSLPRM_TSC_GROUP3_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+#endif // STM32F30X\r
+\r
+#if defined(STM32F37X)\r
+#if TSLPRM_TSC_GROUP3_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_15;\r
+#endif\r
+#endif // STM32F37X\r
+\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOC\r
+#if defined(STM32F30X)\r
+#if TSLPRM_TSC_GROUP3_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;\r
+ GPIO_Init(GPIOC, &GPIO_InitStructure);\r
+#endif\r
+#endif // STM32F30X\r
+\r
+#if defined(STM32F37X)\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if TSLPRM_TSC_GROUP3_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOC, &GPIO_InitStructure);\r
+ }\r
+#endif // STM32F37X\r
+\r
+ // GPIOD\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+\r
+#if defined(STM32F37X)\r
+#if TSLPRM_TSC_GROUP6_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;\r
+#endif\r
+#endif // STM32F37X\r
+\r
+#if TSLPRM_TSC_GROUP8_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOD, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOE\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if TSLPRM_TSC_GROUP7_IO1 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO2 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO3 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO4 == SAMPCAP\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOE, &GPIO_InitStructure);\r
+ }\r
+\r
+ // Alternate function Output Push-Pull for Channel and Shield IOs\r
+ //---------------------------------------------------------------\r
+\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+\r
+ // GPIOA\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if (TSLPRM_TSC_GROUP1_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP1_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP1_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP1_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP2_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP2_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP2_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP2_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP4_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_9;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP4_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_10;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP4_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP4_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOA, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOB\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+\r
+#if defined(STM32F30X)\r
+#if (TSLPRM_TSC_GROUP3_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP3_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP3_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+#endif // STM32F30X\r
+\r
+#if defined(STM32F37X)\r
+#if (TSLPRM_TSC_GROUP3_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP3_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP5_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_15;\r
+#endif\r
+#endif // STM32F37X\r
+\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOC\r
+\r
+#if defined(STM32F30X)\r
+#if (TSLPRM_TSC_GROUP3_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;\r
+ GPIO_Init(GPIOC, &GPIO_InitStructure);\r
+#endif\r
+#endif // STM32F30X\r
+\r
+#if defined(STM32F37X)\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if (TSLPRM_TSC_GROUP3_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP3_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOC, &GPIO_InitStructure);\r
+ }\r
+#endif // STM32F37X\r
+\r
+ // GPIOD\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+\r
+#if defined(STM32F37X)\r
+#if (TSLPRM_TSC_GROUP6_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_8;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP6_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_9;\r
+#endif\r
+#endif // STM32F37X\r
+\r
+#if (TSLPRM_TSC_GROUP8_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP8_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP8_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP8_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP8_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP8_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP8_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP8_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_15;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOD, &GPIO_InitStructure);\r
+ }\r
+\r
+ // GPIOE\r
+ GPIO_InitStructure.GPIO_Pin = 0;\r
+#if (TSLPRM_TSC_GROUP7_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP7_IO1 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP7_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP7_IO2 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP7_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP7_IO3 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;\r
+#endif\r
+#if (TSLPRM_TSC_GROUP7_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP7_IO4 == SHIELD)\r
+ GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;\r
+#endif\r
+ if (GPIO_InitStructure.GPIO_Pin != 0)\r
+ {\r
+ GPIO_Init(GPIOE, &GPIO_InitStructure);\r
+ }\r
+\r
+ // Set Alternate-Function AF3 on used TSC IOs\r
+ //-------------------------------------------\r
+\r
+ // GPIOA\r
+ tmp_value_0 = 0;\r
+ tmp_value_1 = 0;\r
+#if TSLPRM_TSC_GROUP1_IO1 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (0 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (1 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (2 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO1 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (7 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO1 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (1 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO2 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (2 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO3 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO4 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+ if (tmp_value_0 != 0) {GPIOA->AFR[0] |= tmp_value_0;}\r
+ if (tmp_value_1 != 0) {GPIOA->AFR[1] |= tmp_value_1;}\r
+\r
+ // GPIOB\r
+ tmp_value_0 = 0;\r
+ tmp_value_1 = 0;\r
+\r
+#if defined(STM32F30X)\r
+#if TSLPRM_TSC_GROUP3_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (0 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (1 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (2 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (7 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO3 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+#endif // STM32F30X\r
+\r
+#if defined(STM32F37X)\r
+#if TSLPRM_TSC_GROUP3_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (0 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (1 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (7 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (7 * 4));\r
+#endif\r
+#endif // STM32F37X\r
+\r
+ if (tmp_value_0 != 0) {GPIOB->AFR[0] |= tmp_value_0;}\r
+ if (tmp_value_1 != 0) {GPIOB->AFR[1] |= tmp_value_1;}\r
+\r
+ // GPIOC\r
+#if defined(STM32F30X)\r
+#if TSLPRM_TSC_GROUP3_IO1 != NU\r
+ GPIOC->AFR[0] |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+#endif // STM32F30X\r
+\r
+#if defined(STM32F37X)\r
+#if TSLPRM_TSC_GROUP3_IO1 != NU\r
+ GPIOC->AFR[0] |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO2 != NU\r
+ GPIOC->AFR[0] |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+#endif // STM32F37X\r
+\r
+ // GPIOD\r
+ tmp_value_1 = 0;\r
+\r
+#if defined(STM32F37X)\r
+#if TSLPRM_TSC_GROUP6_IO3 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (0 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (1 * 4));\r
+#endif\r
+#endif // STM32F37X\r
+\r
+#if TSLPRM_TSC_GROUP8_IO1 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO2 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO3 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (6 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO4 != NU\r
+ tmp_value_1 |= (uint32_t)((uint32_t)3 << (7 * 4));\r
+#endif\r
+ if (tmp_value_1 != 0) {GPIOD->AFR[1] |= tmp_value_1;}\r
+\r
+ // GPIOE\r
+ tmp_value_0 = 0;\r
+#if TSLPRM_TSC_GROUP7_IO1 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (2 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO2 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (3 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO3 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (4 * 4));\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO4 != NU\r
+ tmp_value_0 |= (uint32_t)((uint32_t)3 << (5 * 4));\r
+#endif\r
+ if (tmp_value_0 != 0) {GPIOE->AFR[0] |= tmp_value_0;}\r
+\r
+ //==================\r
+ // TSC configuration\r
+ //==================\r
+\r
+ // Enable TSC clock\r
+ RCC->AHBENR |= RCC_AHBENR_TSEN;\r
+\r
+ // Disable Schmitt trigger hysteresis on all used TS IOs (Channel, Shield and Sampling IOs)\r
+ //-----------------------------------------------------------------------------------------\r
+\r
+ tmp_value_0 = 0xFFFFFFFF;\r
+#if TSLPRM_TSC_GROUP1_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 0);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 1);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 2);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 3);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 4);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 5);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 6);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 7);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 8);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 9);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 10);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 11);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 12);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 13);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 14);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 15);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 16);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 17);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 18);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 19);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 20);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 21);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 22);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 23);\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 24);\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 25);\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 26);\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 27);\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO1 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 28);\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO2 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 29);\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO3 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 30);\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO4 != NU\r
+ tmp_value_0 &= (uint32_t)~((uint32_t)1 << 31);\r
+#endif\r
+ if (tmp_value_0 != 0xFFFFFFFF) {TSC->IOHCR &= tmp_value_0;}\r
+\r
+ // Set Sampling Capacitor IOs\r
+ //---------------------------\r
+\r
+ tmp_value_0 = 0;\r
+#if TSLPRM_TSC_GROUP1_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 0);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 1);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 2);\r
+#endif\r
+#if TSLPRM_TSC_GROUP1_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 3);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 4);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 5);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 6);\r
+#endif\r
+#if TSLPRM_TSC_GROUP2_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 7);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 8);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 9);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 10);\r
+#endif\r
+#if TSLPRM_TSC_GROUP3_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 11);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 12);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 13);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 14);\r
+#endif\r
+#if TSLPRM_TSC_GROUP4_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 15);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 16);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 17);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 18);\r
+#endif\r
+#if TSLPRM_TSC_GROUP5_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 19);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 20);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 21);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 22);\r
+#endif\r
+#if TSLPRM_TSC_GROUP6_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 23);\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 24);\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 25);\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 26);\r
+#endif\r
+#if TSLPRM_TSC_GROUP7_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 27);\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO1 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 28);\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO2 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 29);\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO3 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 30);\r
+#endif\r
+#if TSLPRM_TSC_GROUP8_IO4 == SAMPCAP\r
+ tmp_value_0 |= (uint32_t)((uint32_t)1 << 31);\r
+#endif\r
+ if (tmp_value_0 != 0) {TSC->IOSCR |= tmp_value_0;}\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the acquisition module.\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_Init(void)\r
+{\r
+\r
+#if TSLPRM_TSC_GPIO_CONFIG > 0\r
+ TSL_acq_InitGPIOs();\r
+#endif\r
+\r
+ // Enable TSC clock\r
+ RCC->AHBENR |= RCC_AHBENR_TSEN;\r
+\r
+ // TSC enabled\r
+ TSC->CR = 0x01;\r
+\r
+ // Set CTPH\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPH << 28) & 0xF0000000;\r
+\r
+ // Set CTPL\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPL << 24) & 0x0F000000;\r
+\r
+ // Set SpreadSpectrum\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_USE_SS << 16) & 0x00010000;\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSD << 17) & 0x00FE0000;\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSPSC << 15) & 0x00008000;\r
+\r
+ // Set Prescaler\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_PGPSC << 12) & 0x00007000;\r
+\r
+ // Set Max Count\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_MCV << 5) & 0x000000E0;\r
+\r
+ // Set IO default in Output PP Low to discharge all capacitors\r
+ TSC->CR &= (uint32_t)(~(1 << 4));\r
+\r
+ // Set Synchronization Mode\r
+#if TSLPRM_TSC_AM > 0\r
+\r
+ // Set Synchronization Pin in Alternate-Function mode\r
+ RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // Set GPIOB clock\r
+\r
+#if TSLPRM_TSC_SYNC_PIN == 0 // PB08\r
+ GPIOB->MODER &= 0xFFFCFFFF;\r
+ GPIOB->MODER |= 0x00020000;\r
+ GPIOB->AFR[1] |= 0x00000003;\r
+#else // PB10\r
+ GPIOB->MODER &= 0xFFCFFFFF;\r
+ GPIOB->MODER |= 0x00200000;\r
+ GPIOB->AFR[1] |= 0x00000300;\r
+#endif\r
+\r
+ // Set Synchronization Polarity\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SYNC_POL << 3) & 0x00000008;\r
+\r
+#endif\r
+\r
+ // Set acquisition mode\r
+ TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_AM << 2) & 0x00000004;\r
+\r
+#if TSLPRM_USE_ACQ_INTERRUPT > 0\r
+\r
+ // Set both EOA and MCE interrupts\r
+ TSC->IER |= 0x03;\r
+\r
+ // Configure NVIC\r
+ NVIC_SetPriority(EXTI2_TS_IRQn, 0);\r
+ NVIC_EnableIRQ(EXTI2_TS_IRQn);\r
+\r
+#endif\r
+\r
+ return TSL_STATUS_OK;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures a Bank.\r
+ * @param[in] idx_bk Index of the Bank to configure\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_tIndex_T idx_ch;\r
+ uint32_t objs; /* bit field of TSL_ObjStatus_enum_T type */\r
+ uint32_t gx;\r
+ uint32_t ioy;\r
+ CONST TSL_Bank_T *bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ CONST TSL_ChannelSrc_T *pchSrc = bank->p_chSrc;\r
+ CONST TSL_ChannelDest_T *pchDest = bank->p_chDest;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ // Mark the current bank processed\r
+ TSL_Globals.This_Bank = idx_bk;\r
+\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ // Enable the Gx_IOy used as channels (channels + shield)\r
+ TSC->IOCCR = bank->msk_IOCCR_channels;\r
+ // Enable acquisition on selected Groups\r
+ TSC->IOGCSR = bank->msk_IOGCSR_groups;\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+ // For all channels of the bank check if they are OFF or BURST_ONLY\r
+ // and set acquisition status flag\r
+ for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)\r
+ {\r
+\r
+ // Check Object status flag\r
+ objs = bank->p_chData[pchDest->IdxDest].Flags.ObjStatus;\r
+\r
+ if (objs != TSL_OBJ_STATUS_ON)\r
+ {\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ // Get the Channel Group mask\r
+ gx = pchSrc->msk_IOGCSR_group;\r
+ // Stop acquisition of the Group\r
+ TSC->IOGCSR &= (uint32_t)~gx;\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+ if (objs == TSL_OBJ_STATUS_OFF)\r
+ {\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ // Get the Channel IO mask\r
+ ioy = pchSrc->msk_IOCCR_channel;\r
+ // Stop Burst of the Channel\r
+ TSC->IOCCR &= (uint32_t)~ioy;\r
+ //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ }\r
+ }\r
+\r
+ // Next channel\r
+ pchSrc++;\r
+ pchDest++;\r
+ }\r
+\r
+ return TSL_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Start acquisition on a previously configured bank\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_BankStartAcq(void)\r
+{\r
+ // Clear both EOAIC and MCEIC flags\r
+ TSC->ICR |= 0x03;\r
+\r
+ // Wait capacitors discharge\r
+ SoftDelay(TSL_DELAY_DISCHARGE);\r
+\r
+#if TSLPRM_TSC_IODEF > 0 // Default = Input Floating\r
+ // Set IO default in Input Floating\r
+ TSC->CR |= (1 << 4);\r
+#endif\r
+\r
+ // Start acquisition\r
+ TSC->CR |= 0x02;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Wait end of acquisition\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void)\r
+{\r
+ TSL_Status_enum_T retval = TSL_STATUS_BUSY;\r
+\r
+ // Check EOAF flag\r
+ if (TSC->ISR & 0x01)\r
+ {\r
+\r
+#if TSLPRM_TSC_IODEF > 0 // Default = Input Floating\r
+ // Set IO default in Output PP Low to discharge all capacitors\r
+ TSC->CR &= (uint32_t)(~(1 << 4));\r
+#endif\r
+\r
+ // Check MCEF flag\r
+ if (TSC->ISR & 0x02)\r
+ {\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ retval = TSL_STATUS_OK;\r
+ }\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the current measure\r
+ * @param[in] index Index of the measure source\r
+ * @retval Measure\r
+ */\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index)\r
+{\r
+ return(TSC->IOGXCR[index]);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Compute the Delta value\r
+ * @param[in] ref Reference value\r
+ * @param[in] meas Last Measurement value\r
+ * @retval Delta value\r
+ */\r
+TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas)\r
+{\r
+ return((TSL_tDelta_T)(ref - meas));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Compute the Measurement value\r
+ * @param[in] ref Reference value\r
+ * @param[in] delta Delta value\r
+ * @retval Measurement value\r
+ */\r
+TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta)\r
+{\r
+ return((TSL_tMeas_T)(ref - delta));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check noise (not used)\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void)\r
+{\r
+ return TSL_ACQ_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a filter must be used on the current channel (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @retval Result TRUE if a filter can be applied\r
+ */\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh)\r
+{\r
+ return TSL_TRUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if the Reference is incorrect (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @retval Result TRUE if the Reference is out of range\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh)\r
+{\r
+ return TSL_FALSE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if the measure has crossed the reference target (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @param[in] new_meas Measure of the last acquisition on this channel\r
+ * @retval Result TRUE if the Reference is valid\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas)\r
+{\r
+ return TSL_TRUE;\r
+}\r
+\r
+\r
+#if defined(__IAR_SYSTEMS_ICC__) // IAR/EWARM\r
+#pragma optimize=low\r
+#elif defined(__CC_ARM) // Keil/MDK-ARM\r
+#pragma O1\r
+#pragma Ospace\r
+#elif defined(__TASKING__) // Altium/Tasking\r
+#pragma optimize O0\r
+#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit\r
+#pragma GCC push_options\r
+#pragma GCC optimize ("O0")\r
+#endif\r
+/**\r
+ * @brief Software delay (private routine)\r
+ * @param val Wait delay\r
+ * @retval None\r
+ */\r
+void SoftDelay(uint32_t val)\r
+{\r
+ __IO uint32_t i;\r
+ for (i = val; i > 0; i--)\r
+ {}\r
+}\r
+#if defined(__TASKING__)\r
+#pragma endoptimize\r
+#endif\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm32l1xx_hw.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the acquisition\r
+ * on STM32l1xx products using the Hardware mode (with Timers).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq_stm32l1xx_hw.h"\r
+#include "tsl_globals.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+\r
+// Register configuration\r
+typedef struct\r
+{\r
+ unsigned int RI_ASCR : 3;\r
+ unsigned int RI_ASCR_bit : 5;\r
+} TSL_RIConf_t;\r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))\r
+\r
+#define TSL_CHANNEL_PORT(channel) (channel >> 4)\r
+#define TSL_CHANNEL_IO(channel) (channel & 0x0F)\r
+\r
+#define TSL_GPIO_AFR(channel) ((TSL_CHANNEL_IO(channel) < 8) ? 0 : 1)\r
+#define TSL_GPIO_AFR_Shift(channel) ((TSL_CHANNEL_IO(channel) < 8) ? (4 * TSL_CHANNEL_IO(channel)) : (4 * (TSL_CHANNEL_IO(channel) - 8)))\r
+\r
+#define TSL_CPRI_HYSCR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))\r
+#define TSL_CPRI_ASMR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))\r
+#define TSL_CPRI_CMR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))\r
+#define TSL_CPRI_CICR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))\r
+\r
+#define TSL_RCC_AHBENR_Config(channel) (RCC->AHBENR |= TSL_GPIO_Clock_LookUpTable[TSL_CHANNEL_PORT(channel)])\r
+\r
+#define TSL_CPRI_ASCR_Config(channel) (*TSL_CPRI_ASCR_LookUpTable[TSL_RI_Conf_LookUpTable[channel].RI_ASCR] |= (1 << (TSL_RI_Conf_LookUpTable[channel].RI_ASCR_bit)))\r
+#define TSL_CPRI_HYSCR_Config(channel) (*TSL_CPRI_HYSCR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_CPRI_HYSCR_MASK(channel))\r
+#define TSL_CPRI_ASMR_Config(channel) (*TSL_CPRI_ASMR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_CPRI_ASMR_MASK(channel))\r
+#define TSL_CPRI_ASMR_Config_Clear(channel) (*TSL_CPRI_ASMR_LookUpTable[TSL_CHANNEL_PORT(channel)] &= (uint32_t)(~TSL_CPRI_ASMR_MASK(channel)))\r
+#define TSL_CPRI_CMR_Config(channel) (*TSL_CPRI_CMR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_CPRI_CMR_MASK(channel))\r
+#define TSL_CPRI_CMR_Config_Clear(channel) (*TSL_CPRI_CMR_LookUpTable[TSL_CHANNEL_PORT(channel)] &= (uint32_t)(~TSL_CPRI_CMR_MASK(channel)))\r
+#define TSL_CPRI_CICR_Config(channel) (*TSL_CPRI_CICR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_CPRI_CICR_MASK(channel))\r
+#define TSL_CPRI_CICR_Config_Clear(channel) (*TSL_CPRI_CICR_LookUpTable[TSL_CHANNEL_PORT(channel)] &= (uint32_t)(~TSL_CPRI_CICR_MASK(channel)))\r
+\r
+#define TSL_GPIO_MODER_IN_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER &= (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel)))))\r
+#define TSL_GPIO_MODER_AF_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER = (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER & (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel))))) | (2 << (2 * TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_MODER_OUT_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER = (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER & (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel))))) | (1 << (2 * TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_PUPDR_NO_PUPD_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->PUPDR &= (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel)))))\r
+#define TSL_GPIO_OTYPER_PP_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->OTYPER &= (uint32_t)(~(1 << TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_OSPEEDR_VL_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->OSPEEDR &= (uint32_t)~(3 << (2 * TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_AFR_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->AFR[TSL_GPIO_AFR(channel)] |= (0x0E << (TSL_GPIO_AFR_Shift(channel))))\r
+#define TSL_GPIO_BS_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->BSRRL = (uint16_t)(1 << (TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_BR_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->BSRRH = (uint16_t)(1 << (TSL_CHANNEL_IO(channel))))\r
+\r
+#define TSL_GPIO_AFR_NOAF_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->AFR[TSL_GPIO_AFR(channel)] &= (uint32_t)(~(0x0F << (TSL_GPIO_AFR_Shift(channel)))))\r
+\r
+#define TSL_GPIO_IDR_XOR_CPRI_CMR(channel) ((TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->IDR)^(*TSL_CPRI_CMR_LookUpTable[TSL_CHANNEL_PORT(channel)]))\r
+#define TSL_GPIO_IDR_AND_CPRI_CMR(channel) ((TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->IDR)&(*TSL_CPRI_CMR_LookUpTable[TSL_CHANNEL_PORT(channel)]))\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+CONST TSL_Bank_T *bank;\r
+TSL_tIndex_T NumberOfChannelOn = 0;\r
+TSL_tNb_T NumberOfChannels = 0;\r
+uint32_t tab_MeasurementCounter[11];\r
+TSL_Status_enum_T TSL_Acq_Status = TSL_STATUS_BUSY;\r
+static uint16_t GroupToCheck = 0;\r
+static TSL_tIndex_T NumberOfChannelChecked = 0;\r
+\r
+uint32_t TSL_GPIO_Clock_LookUpTable[] = {RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB, RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_AHBPeriph_GPIOE, RCC_AHBPeriph_GPIOF, RCC_AHBPeriph_GPIOG, RCC_AHBPeriph_GPIOH};\r
+GPIO_TypeDef *TSL_GPIO_LookUpTable[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH};\r
+\r
+uint32_t *TSL_CPRI_ASCR_LookUpTable[] = {(uint32_t *)&CPRI->ASCR1, (uint32_t *)&CPRI->ASCR2};\r
+\r
+uint16_t *TSL_CPRI_HYSCR_LookUpTable[] =\r
+{\r
+ (uint16_t *)&CPRI->HYSCR1, (uint16_t *)&CPRI->HYSCR1 + 1,\r
+ (uint16_t *)&CPRI->HYSCR2, (uint16_t *)&CPRI->HYSCR2 + 1,\r
+ (uint16_t *)&CPRI->HYSCR3, (uint16_t *)&CPRI->HYSCR3 + 1,\r
+ (uint16_t *)&CPRI->HYSCR4, (uint16_t *)&CPRI->HYSCR4 + 1\r
+};\r
+\r
+uint32_t *TSL_CPRI_ASMR_LookUpTable[] = {(uint32_t *)&CPRI->ASMR1, (uint32_t *)&CPRI->ASMR2, (uint32_t *)&CPRI->ASMR3, 0, 0, (uint32_t *)&CPRI->ASMR4, (uint32_t *)&CPRI->ASMR5};\r
+uint32_t *TSL_CPRI_CMR_LookUpTable[] = {(uint32_t *)&CPRI->CMR1, (uint32_t *)&CPRI->CMR2, (uint32_t *)&CPRI->CMR3, 0, 0, (uint32_t *)&CPRI->CMR4, (uint32_t *)&CPRI->CMR5};\r
+uint32_t *TSL_CPRI_CICR_LookUpTable[] = {(uint32_t *)&CPRI->CICR1, (uint32_t *)&CPRI->CICR2, (uint32_t *)&CPRI->CICR3, 0, 0, (uint32_t *)&CPRI->CICR4, (uint32_t *)&CPRI->CICR5};\r
+\r
+CONST TSL_RIConf_t TSL_RI_Conf_LookUpTable[101] =\r
+{\r
+ {0, 0},\r
+ {0, 1},\r
+ {0, 2},\r
+ {0, 3},\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 6},\r
+ {0, 7},\r
+ {1, 9},\r
+ {1, 10},\r
+ {1, 11},\r
+ {1, 15},\r
+ {0, 0},//padding\r
+ {1, 6},\r
+ {1, 7},\r
+ {1, 8},\r
+\r
+ {0, 8},\r
+ {0, 9},\r
+ {1, 16},\r
+ {0, 0},//padding\r
+ {1, 4},\r
+ {1, 5},\r
+ {1, 27},\r
+ {1, 28},\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 18},\r
+ {0, 19},\r
+ {0, 20},\r
+ {0, 21},\r
+\r
+ {0, 10},\r
+ {0, 11},\r
+ {0, 12},\r
+ {0, 13},\r
+ {0, 14},\r
+ {0, 15},\r
+ {1, 0},\r
+ {1, 1},\r
+ {1, 2},\r
+ {1, 3},\r
+ {1, 29},\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 27},\r
+ {0, 28},\r
+ {0, 29},\r
+ {0, 30},\r
+ {0, 16},\r
+ {1, 17},\r
+ {1, 18},\r
+ {1, 19},\r
+ {1, 20},\r
+ {1, 21},\r
+\r
+ {1, 22},\r
+ {1, 23},\r
+ {1, 24},\r
+ {1, 25},\r
+ {1, 26}\r
+};\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+void TSL_Init_GPIOs(void);\r
+void TSL_Init_TIMs(void);\r
+void TSL_Init_RI(void);\r
+uint8_t TSL_Check_GPIO_IDR(uint8_t sample);\r
+void SoftDelay(uint16_t val);\r
+\r
+\r
+/**\r
+ * @brief Initializes the TouchSensing GPIOs.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_Init_GPIOs(void)\r
+{\r
+ CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);\r
+ TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;\r
+ TSL_tNb_T LocalNumberOfChannels = 0;\r
+ TSL_tIndex_T idx_bk;\r
+ TSL_tIndex_T idx_ch;\r
+ CONST TSL_ChannelSrc_T *p_chSrc = LocalBank->p_chSrc; // Pointer to the current channel\r
+\r
+ for (idx_bk = 0; idx_bk < NumberOfBanks; idx_bk++)\r
+ {\r
+ LocalBank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ p_chSrc = LocalBank->p_chSrc;\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ // Enables GPIOs clock\r
+ TSL_RCC_AHBENR_Config(LocalBank->shield_sample);\r
+\r
+ // Bank shield configuration\r
+ TSL_GPIO_OTYPER_PP_Config(LocalBank->shield_channel);\r
+ TSL_GPIO_OSPEEDR_VL_Config(LocalBank->shield_channel);\r
+ TSL_GPIO_PUPDR_NO_PUPD_Config(LocalBank->shield_channel);\r
+ TSL_GPIO_AFR_Config(LocalBank->shield_channel);\r
+\r
+ TSL_GPIO_OSPEEDR_VL_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_BR_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_OTYPER_PP_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_PUPDR_NO_PUPD_Config(LocalBank->shield_sample);\r
+\r
+ TSL_GPIO_MODER_OUT_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_MODER_OUT_Config(LocalBank->shield_channel);\r
+#endif\r
+\r
+ LocalNumberOfChannels = LocalBank->NbChannels;\r
+\r
+ for (idx_ch = 0;\r
+ idx_ch < LocalNumberOfChannels;\r
+ idx_ch++)\r
+ {\r
+ TSL_RCC_AHBENR_Config(p_chSrc->t_sample);\r
+ TSL_RCC_AHBENR_Config(p_chSrc->t_channel);\r
+\r
+ TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_channel);\r
+ TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_channel);\r
+ TSL_GPIO_PUPDR_NO_PUPD_Config(p_chSrc->t_channel);\r
+ TSL_GPIO_AFR_Config(p_chSrc->t_channel);\r
+\r
+ TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_BR_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_PUPDR_NO_PUPD_Config(p_chSrc->t_sample);\r
+\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_channel);\r
+\r
+ p_chSrc++;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TouchSensing timers.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_Init_TIMs(void)\r
+{\r
+ // Enable Timers clocks\r
+ RCC->APB2ENR |= ((1 << 4) | (1 << 2)); // TIM11, TIM9\r
+\r
+ //==============================\r
+ // TIMER 9 configuration: Master\r
+ //==============================\r
+ // Set the option register to redirect cpri_tim9_itr_O to TIM9_itr\r
+ TIM9->OR |= 4;\r
+ // Set the Autoreload value (signal frequency)\r
+ //TIM9->ARR = 64; // freq = (64*2)*31.25ns = 1us\r
+ TIM9->ARR = TSLPRM_TIM_RELOAD; // freq = (64*2)*31.25ns = 1us\r
+ // Set the Prescaler value\r
+ //TIM9->PSC = 0; // fCK_CNT = 32MHz/(0+1) = 32MHz --> T=31.25ns\r
+ TIM9->PSC = TSLPRM_TIM_PRESCALER; // fCK_CNT = 32MHz/(1+1) = 32MHz --> T=31.25ns\r
+ // Set UP counter, Center-Aligned mode 1\r
+ TIM9->CR1 = 0x20;\r
+ // OC1REF used as TRGO\r
+ TIM9->CR2 |= 0x40; // MMS=100\r
+ // Select Master mode\r
+ TIM9->SMCR = 0x95;\r
+ // Set Update generation\r
+ TIM9->EGR |= 0x01;\r
+\r
+ // Channel 1 PWM configuration\r
+ // Set the Output Compare Mode, PWM2\r
+ TIM9->CCMR1 |= 0x0070;\r
+ // Set the Pulse value\r
+ //TIM9->CCR1 = 34; // duty cycle\r
+ TIM9->CCR1 = (TSLPRM_TIM_RELOAD >> 1) + 1; // duty cycle\r
+ // Compare output enable, active high\r
+ TIM9->CCER |= 0x01;\r
+\r
+ // Channel 2 PWM configuration\r
+ // Set the Output Compare Mode, PWM2\r
+ TIM9->CCMR1 |= 0x6000;\r
+ // Set the Pulse value\r
+ //TIM9->CCR2 = 30;\r
+ TIM9->CCR2 = (TSLPRM_TIM_RELOAD >> 1) - 1;\r
+ // Compare output enable, active high\r
+ TIM9->CCER |= 0x10;\r
+\r
+ //==============================\r
+ // TIMER 11 configuration: slave\r
+ //==============================\r
+ // Set the option register to redirect TIM11_ic_o to TIM11_ti\r
+ TIM11->OR |= 8;\r
+ // Set the option register to redirect TIM9_tgo_cktim to TIM11_etri\r
+ TIM11->OR |= 4;\r
+ // Set the Prescaler value\r
+ TIM11->PSC = 0;\r
+ // Set UP counter, edge-aligned mode\r
+ TIM11->CR1 = 0;\r
+ // Select Slave mode, Internal Trigger 2 (ITR2 = TIM9), External clock mode 1\r
+ TIM11->SMCR = 0x4000; // ECE bit\r
+ // Channel 1 configured in Input capture mode\r
+ TIM11->CCMR1 = 0x01; // No prescaler, no filter\r
+ // Channel 1 capture enable (CCE1 = 1)\r
+ TIM11->CCER = 0x01;\r
+ // Interrupt Enable, active high\r
+ TIM11->DIER |= 0x02;\r
+ // Start slave timer\r
+ TIM11->CR1 |= 0x01;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Init TS routing interface.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_Init_RI(void)\r
+{\r
+ CONST TSL_Bank_T *LocalBank;\r
+ TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;\r
+ TSL_tNb_T LocalNumberOfChannels = 0;\r
+ TSL_tIndex_T idx_bk;\r
+ TSL_tIndex_T idx_ch;\r
+ CONST TSL_ChannelSrc_T *p_chSrc; // Pointer to the current channel\r
+\r
+ RCC->APB1ENR |= (uint32_t)((uint32_t)1 << 31); // COMP enable\r
+\r
+ for (idx_bk = 0; idx_bk < NumberOfBanks; idx_bk++)\r
+ {\r
+ LocalBank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ TSL_CPRI_HYSCR_Config(LocalBank->shield_sample);\r
+ TSL_CPRI_CICR_Config(LocalBank->shield_sample);\r
+ TSL_CPRI_CICR_Config_Clear(LocalBank->shield_channel);\r
+\r
+ TSL_CPRI_ASCR_Config(LocalBank->shield_sample);\r
+#endif\r
+\r
+ LocalNumberOfChannels = LocalBank->NbChannels;\r
+\r
+ p_chSrc = LocalBank->p_chSrc;\r
+ for (idx_ch = 0; idx_ch < LocalNumberOfChannels; idx_ch++)\r
+ {\r
+ TSL_CPRI_HYSCR_Config(p_chSrc->t_sample);\r
+ TSL_CPRI_CICR_Config(p_chSrc->t_sample);\r
+ TSL_CPRI_CICR_Config_Clear(p_chSrc->t_channel);\r
+ TSL_CPRI_ASCR_Config(p_chSrc->t_sample);\r
+ p_chSrc++;\r
+ }\r
+ }\r
+\r
+ // Reset TSUSP bit, TIM9 ITR enabled to suspend OC TIM9 generation\r
+ COMP->CSR &= (uint32_t)(~0x80000000);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the acquisition module.\r
+ * @param None\r
+ * @retval retval\r
+ */\r
+TSL_Status_enum_T TSL_acq_Init(void)\r
+{\r
+ NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+ NVIC_InitStructure.NVIC_IRQChannel = TIM11_IRQn;\r
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;\r
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+ NVIC_Init(&NVIC_InitStructure);\r
+\r
+ TSL_Init_GPIOs();\r
+ TSL_Init_TIMs();\r
+ TSL_Init_RI();\r
+\r
+ return TSL_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures a Bank.\r
+ * @param[in] idx_bk Index of the Bank to configure\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_tIndex_T idx_dest;\r
+ TSL_tIndex_T idx_ch;\r
+ CONST TSL_ChannelDest_T *p_chDest; // Pointer to the current channel\r
+ CONST TSL_ChannelSrc_T *p_chSrc; // Pointer to the current channel\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+\r
+ NumberOfChannels = bank->NbChannels;\r
+\r
+ GroupToCheck = 0;//init group to check\r
+ NumberOfChannelOn = 0;//init number of channel on\r
+\r
+ // init CPRI ASMR\r
+ CPRI->ASMR1 = 0;\r
+ CPRI->ASMR2 = 0;\r
+ CPRI->ASMR3 = 0;\r
+ CPRI->ASMR4 = 0;\r
+ CPRI->ASMR5 = 0;\r
+\r
+ p_chDest = bank->p_chDest;\r
+ p_chSrc = bank->p_chSrc;\r
+ for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)\r
+ {\r
+ // Get index in the result array associated to the current channel\r
+ idx_dest = p_chDest->IdxDest;\r
+ if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)\r
+ {\r
+ TSL_CPRI_CMR_Config(p_chSrc->t_sample);\r
+ TSL_CPRI_ASMR_Config(p_chSrc->t_channel);\r
+ GroupToCheck |= (1 << (p_chSrc->IdxSrc));\r
+ NumberOfChannelOn++;\r
+ }\r
+ p_chDest++;\r
+ p_chSrc++;\r
+ }\r
+\r
+ return TSL_STATUS_OK;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Start acquisition on a previously configured bank\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_BankStartAcq(void)\r
+{\r
+#if (TSLPRM_IODEF > 0)\r
+ CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);\r
+ TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;\r
+ TSL_tNb_T LocalNumberOfChannels = 0;\r
+ TSL_tIndex_T BankIndex;\r
+#endif\r
+ CONST TSL_ChannelSrc_T *p_chSrc;\r
+ CONST TSL_ChannelDest_T *p_chDest;\r
+ TSL_tIndex_T idx_dest;\r
+ TSL_tIndex_T idx_ch;\r
+\r
+ if (NumberOfChannelOn)\r
+ {\r
+#if (TSLPRM_IODEF > 0)\r
+ //============================\r
+ // All GPIOs in Input floating\r
+ //============================\r
+ for (BankIndex = 0; BankIndex < NumberOfBanks; BankIndex++)\r
+ {\r
+ LocalBank = &(TSL_Globals.Bank_Array[BankIndex]);\r
+ p_chSrc = LocalBank->p_chSrc;\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ TSL_GPIO_MODER_IN_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_MODER_IN_Config(LocalBank->shield_channel);\r
+#endif\r
+\r
+ LocalNumberOfChannels = LocalBank->NbChannels;\r
+\r
+ for (idx_ch = 0;\r
+ idx_ch < LocalNumberOfChannels;\r
+ idx_ch++)\r
+ {\r
+ TSL_GPIO_MODER_IN_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_MODER_IN_Config(p_chSrc->t_channel);\r
+\r
+ p_chSrc++;\r
+ }\r
+ }\r
+#endif\r
+\r
+\r
+ // Reset count\r
+ TIM11->CNT = 0;\r
+\r
+ // Discharge sample capacitors\r
+ p_chDest = bank->p_chDest;\r
+ p_chSrc = bank->p_chSrc;\r
+ for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)\r
+ {\r
+ // Get index in the result array associated to the current channel\r
+ idx_dest = p_chDest->IdxDest;\r
+ if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)\r
+ {\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);\r
+ }\r
+ p_chDest++;\r
+ p_chSrc++;\r
+ }\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ // Discharge shield sample capacitor\r
+ TSL_GPIO_MODER_OUT_Config(bank->shield_sample);\r
+#endif\r
+\r
+ // Wait for capa discharge\r
+ SoftDelay(0x80);\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ // Init sample shield in floating input\r
+ TSL_GPIO_MODER_IN_Config(bank->shield_sample);\r
+ TSL_GPIO_MODER_AF_Config(bank->shield_channel);\r
+\r
+ TSL_CPRI_ASMR_Config(bank->shield_channel);\r
+#endif\r
+\r
+ // Init samples in floating input and channels in alternate\r
+ p_chDest = bank->p_chDest;\r
+ p_chSrc = bank->p_chSrc;\r
+ for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)\r
+ {\r
+ // Get index in the result array associated to the current channel\r
+ idx_dest = p_chDest->IdxDest;\r
+\r
+ if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)\r
+ {\r
+ TSL_GPIO_MODER_IN_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_MODER_AF_Config(p_chSrc->t_channel);\r
+ }\r
+\r
+ p_chDest++;\r
+ p_chSrc++;\r
+ }\r
+\r
+ /* Start acquisition */\r
+ TSL_Acq_Status = TSL_STATUS_BUSY;\r
+ TIM9 ->CR1 |= 0x01; // Master\r
+ }\r
+ else\r
+ {\r
+ TSL_Acq_Status = TSL_STATUS_OK;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Wait end of acquisition\r
+ * @param None\r
+ * @retval status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void)\r
+{\r
+ return TSL_Acq_Status;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the current measure\r
+ * @param[in] index Index of the measure source\r
+ * @retval Measure\r
+ */\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index)\r
+{\r
+ return(tab_MeasurementCounter[index]);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check noise (not used)\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void)\r
+{\r
+ return TSL_ACQ_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check GPIO IDR for the sample\r
+ * @param[in] sample\r
+ * @retval Status\r
+ */\r
+uint8_t TSL_Check_GPIO_IDR(uint8_t sample)\r
+{\r
+ GPIO_TypeDef *GPIO;\r
+ uint32_t GPIO_IDR_Mask = 0;\r
+\r
+ GPIO = TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(sample)];\r
+\r
+ GPIO_IDR_Mask = (1 << (sample & 0x0F));\r
+\r
+ if (((GPIO->IDR) & GPIO_IDR_Mask) == GPIO_IDR_Mask)\r
+ {\r
+ return 1;\r
+ }\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Process the TS Interrupt routine\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_ProcessIT(void)\r
+{\r
+ CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);\r
+ TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;\r
+ TSL_tNb_T LocalNumberOfChannels = 0;\r
+ TSL_tIndex_T BankIndex;\r
+\r
+ CONST TSL_ChannelSrc_T *p_chSrc;\r
+ CONST TSL_ChannelDest_T *p_chDest;\r
+ TSL_tIndex_T idx_dest;\r
+ TSL_tIndex_T idx_ch;\r
+\r
+ // Reset flags\r
+ TIM11->SR = 0;\r
+ idx_ch = 0;\r
+\r
+ p_chDest = bank->p_chDest;\r
+ p_chSrc = bank->p_chSrc;\r
+ do\r
+ {\r
+ // Get index in the result array associated to the current channel\r
+ idx_dest = p_chDest->IdxDest;\r
+\r
+ if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)\r
+ {\r
+ if ((TSL_Check_GPIO_IDR(p_chSrc->t_sample)) &&\r
+ ((GroupToCheck & (1 << (p_chSrc->IdxSrc))) == (1 << (p_chSrc->IdxSrc))))\r
+ {\r
+ tab_MeasurementCounter[p_chSrc->IdxSrc] = TIM11->CCR1;\r
+ NumberOfChannelChecked++;\r
+ GroupToCheck &= (uint32_t)(~(1 << (p_chSrc->IdxSrc)));\r
+\r
+ // Reset CMR register to restart the timer\r
+ TSL_CPRI_CMR_Config_Clear(p_chSrc->t_sample);\r
+ }\r
+ }\r
+ p_chDest++;\r
+ p_chSrc++;\r
+ idx_ch++;\r
+ }\r
+ while (idx_ch < NumberOfChannels);\r
+\r
+ if (NumberOfChannelChecked >= NumberOfChannelOn)\r
+ {\r
+ NumberOfChannelOn = 0;\r
+ NumberOfChannelChecked = 0;\r
+\r
+ // Disable master counter\r
+ TIM9->CR1 &= (uint16_t)(~0x01);\r
+\r
+ //====================\r
+ // All GPIOs in PP Low\r
+ //====================\r
+ for (BankIndex = 0; BankIndex < NumberOfBanks; BankIndex++)\r
+ {\r
+ LocalBank = &(TSL_Globals.Bank_Array[BankIndex]);\r
+ p_chSrc = LocalBank->p_chSrc;\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ TSL_GPIO_BR_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_BR_Config(LocalBank->shield_channel);\r
+ TSL_GPIO_MODER_OUT_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_MODER_OUT_Config(LocalBank->shield_channel);\r
+#endif\r
+\r
+ LocalNumberOfChannels = LocalBank->NbChannels;\r
+\r
+ for (idx_ch = 0;\r
+ idx_ch < LocalNumberOfChannels;\r
+ idx_ch++)\r
+ {\r
+ TSL_GPIO_BR_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_BR_Config(p_chSrc->t_channel);\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_channel);\r
+\r
+ p_chSrc++;\r
+ }\r
+ }\r
+ TSL_Acq_Status = TSL_STATUS_OK;\r
+ }\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a filter must be used on the current channel (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @retval Result TRUE if a filter can be applied\r
+ */\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh)\r
+{\r
+ return TSL_TRUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Compute the Delta value\r
+ * @param[in] ref Reference value\r
+ * @param[in] meas Last Measurement value\r
+ * @retval Delta value\r
+ */\r
+TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas)\r
+{\r
+ return((TSL_tDelta_T)(ref - meas));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Compute the Measurement value\r
+ * @param[in] ref Reference value\r
+ * @param[in] delta Delta value\r
+ * @retval Measurement value\r
+ */\r
+TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta)\r
+{\r
+ return((TSL_tMeas_T)(ref - delta));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if the Reference is incorrect (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @retval Result TRUE if the Reference is out of range\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh)\r
+{\r
+ return TSL_FALSE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if the measure has crossed the reference target (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @param[in] new_meas Measure of the last acquisition on this channel\r
+ * @retval Result TRUE if the Reference is valid\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas)\r
+{\r
+ return TSL_TRUE;\r
+}\r
+\r
+\r
+#if defined(__IAR_SYSTEMS_ICC__) // IAR/EWARM\r
+#pragma optimize=medium\r
+#elif defined(__CC_ARM) // Keil/MDK-ARM\r
+#pragma O1\r
+#pragma Ospace\r
+#elif defined(__TASKING__) // Altium/Tasking\r
+#pragma optimize O0\r
+#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit\r
+#pragma GCC push_options\r
+#pragma GCC optimize ("O0")\r
+#endif\r
+/**\r
+ * @brief Software delay (private routine)\r
+ * @param val Wait delay\r
+ * With fHCLK = 32MHz: 1 = ~1µs, 50 = ~14µs, 100 = ~25µs, 200 = ~50µs\r
+ * @retval None\r
+ */\r
+void SoftDelay(uint16_t val)\r
+{\r
+ __IO uint16_t i;\r
+ for (i = val; i > 0; i--)\r
+ {}\r
+}\r
+#if defined(__TASKING__)\r
+#pragma endoptimize\r
+#endif\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm32l1xx_sw.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the acquisition\r
+ * on STM32l1xx products using the software mode.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq_stm32l1xx_sw.h"\r
+#include "tsl_globals.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+\r
+// Register configuration\r
+typedef struct\r
+{\r
+ unsigned int RI_ASCR : 3;\r
+ unsigned int RI_ASCR_bit : 5;\r
+} TSL_RIConf_t;\r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+#define SIZEOFBANKCONF (17) //2 mask RIRs + 5 ports x 3 mask registers(MODER input, output, ODR) => 17 registers\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))\r
+\r
+#define TSL_CHANNEL_PORT(channel) (channel >> 4)\r
+#define TSL_CHANNEL_IO(channel) (channel & 0x0F)\r
+\r
+\r
+#define TSL_RI_HYSCR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))\r
+\r
+#define TSL_RCC_AHBENR_Config(channel) (RCC->AHBENR |= TSL_GPIO_Clock_LookUpTable[TSL_CHANNEL_PORT(channel)])\r
+\r
+#define TSL_RI_HYSCR_Config(channel) (*TSL_RI_HYSCR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_RI_HYSCR_MASK(channel))\r
+\r
+#define TSL_GPIO_MODER_IN_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER &= (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel)))))\r
+#define TSL_GPIO_MODER_OUT_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER = (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER & (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel))))) | (1 << (2 * TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_PUPDR_NO_PUPD_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->PUPDR &= (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel)))))\r
+#define TSL_GPIO_OTYPER_PP_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->OTYPER &= (uint32_t)(~(1 << TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_OSPEEDR_VL_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->OSPEEDR &= (uint32_t)~(3 << (2 * TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_BS_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->BSRRL = (uint16_t)(1 << (TSL_CHANNEL_IO(channel))))\r
+#define TSL_GPIO_BR_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->BSRRH = (uint16_t)(1 << (TSL_CHANNEL_IO(channel))))\r
+\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+uint32_t TSL_BankSampleConf[SIZEOFBANKCONF];\r
+uint32_t TSL_BankChannelConf[SIZEOFBANKCONF];\r
+uint32_t tab_MeasurementCounter[11];\r
+extern TSL_Params_T TSL_Params;\r
+\r
+CONST TSL_Bank_T *bank;\r
+TSL_tIndex_T NumberOfChannelOn = 0;\r
+TSL_tNb_T NumberOfChannels = 0;\r
+TSL_Status_enum_T TSL_Acq_Status = TSL_STATUS_BUSY;\r
+uint16_t GroupToCheck = 0;\r
+\r
+uint32_t TSL_GPIO_Clock_LookUpTable[] = {RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB, RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_AHBPeriph_GPIOE, RCC_AHBPeriph_GPIOF, RCC_AHBPeriph_GPIOG, RCC_AHBPeriph_GPIOH};\r
+GPIO_TypeDef *TSL_GPIO_LookUpTable[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH};\r
+\r
+uint16_t *TSL_RI_HYSCR_LookUpTable[] =\r
+{\r
+ (uint16_t *)&RI->HYSCR1, (uint16_t *)&RI->HYSCR1 + 1,\r
+ (uint16_t *)&RI->HYSCR2, (uint16_t *)&RI->HYSCR2 + 1,\r
+ (uint16_t *)&RI->HYSCR3, (uint16_t *)&RI->HYSCR3 + 1,\r
+ (uint16_t *)&RI->HYSCR4, (uint16_t *)&RI->HYSCR4 + 1\r
+};\r
+\r
+CONST TSL_RIConf_t TSL_RI_Conf_LookUpTable[101] =\r
+{\r
+ {0, 0},\r
+ {0, 1},\r
+ {0, 2},\r
+ {0, 3},\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 6},\r
+ {0, 7},\r
+ {1, 9},\r
+ {1, 10},\r
+ {1, 11},\r
+ {1, 15},\r
+ {0, 0},//padding\r
+ {1, 6},\r
+ {1, 7},\r
+ {1, 8},\r
+\r
+ {0, 8},\r
+ {0, 9},\r
+ {1, 16},\r
+ {0, 0},//padding\r
+ {1, 4},\r
+ {1, 5},\r
+ {1, 27},\r
+ {1, 28},\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 18},\r
+ {0, 19},\r
+ {0, 20},\r
+ {0, 21},\r
+\r
+ {0, 10},\r
+ {0, 11},\r
+ {0, 12},\r
+ {0, 13},\r
+ {0, 14},\r
+ {0, 15},\r
+ {1, 0},\r
+ {1, 1},\r
+ {1, 2},\r
+ {1, 3},\r
+ {1, 29},\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 0},//padding\r
+ {0, 27},\r
+ {0, 28},\r
+ {0, 29},\r
+ {0, 30},\r
+ {0, 16},\r
+ {1, 17},\r
+ {1, 18},\r
+ {1, 19},\r
+ {1, 20},\r
+ {1, 21},\r
+\r
+ {1, 22},\r
+ {1, 23},\r
+ {1, 24},\r
+ {1, 25},\r
+ {1, 26}\r
+};\r
+\r
+#if (TSLPRM_USE_GPIOA)\r
+uint32_t GPIOA_IDR_Mask = 0;\r
+#endif\r
+#if (TSLPRM_USE_GPIOB)\r
+uint32_t GPIOB_IDR_Mask = 0;\r
+#endif\r
+#if (TSLPRM_USE_GPIOC)\r
+uint32_t GPIOC_IDR_Mask = 0;\r
+#endif\r
+#if (TSLPRM_USE_GPIOF)\r
+uint32_t GPIOF_IDR_Mask = 0;\r
+#endif\r
+#if (TSLPRM_USE_GPIOG)\r
+uint32_t GPIOG_IDR_Mask = 0;\r
+#endif\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+void SoftDelay(uint16_t val);\r
+void TSL_BankConf(uint32_t * BankConf, TSL_Conf_t Conf);\r
+void TSL_acq_GroupDone(uint16_t EndedGroup);\r
+\r
+/**\r
+ * @brief Configures the acquisition module.\r
+ * @param[in] BankConf Pointer to the bank to configure\r
+ * @param[in] Conf Configuration\r
+ * @retval None\r
+ */\r
+void TSL_BankConf(uint32_t *BankConf, TSL_Conf_t Conf)\r
+{\r
+ BankConf[TSL_RI_Conf_LookUpTable[Conf].RI_ASCR] |= (1 << (TSL_RI_Conf_LookUpTable[Conf].RI_ASCR_bit));\r
+\r
+ switch (TSL_CHANNEL_PORT(Conf))\r
+ {\r
+ case TSL_BANK_GPIOA: BankConf[2] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input\r
+ BankConf[3] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output\r
+ BankConf[4] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR\r
+ break;\r
+ case TSL_BANK_GPIOB: BankConf[5] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input\r
+ BankConf[6] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output\r
+ BankConf[7] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR\r
+ break;\r
+ case TSL_BANK_GPIOC: BankConf[8] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input\r
+ BankConf[9] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output\r
+ BankConf[10] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR\r
+ break;\r
+ case TSL_BANK_GPIOF: BankConf[11] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input\r
+ BankConf[12] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output\r
+ BankConf[13] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR\r
+ break;\r
+ case TSL_BANK_GPIOG: BankConf[14] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input\r
+ BankConf[15] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output\r
+ BankConf[16] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR\r
+ break;\r
+ default: break;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the acquisition module.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+TSL_Status_enum_T TSL_acq_Init(void)\r
+{\r
+ CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);\r
+ TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;\r
+ TSL_tNb_T LocalNumberOfChannels = 0;\r
+ TSL_tIndex_T idx_bk;\r
+ TSL_tIndex_T idx_ch;\r
+ CONST TSL_ChannelSrc_T *p_chSrc = LocalBank->p_chSrc; // Pointer to the current channel\r
+\r
+ /* Enables the comparator interface clock */\r
+ RCC->APB1ENR |= RCC_APB1Periph_COMP;\r
+\r
+ //====================\r
+ // GPIOs configuration\r
+ //====================\r
+ for (idx_bk = 0; idx_bk < NumberOfBanks; idx_bk++)\r
+ {\r
+ LocalBank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ p_chSrc = LocalBank->p_chSrc;\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ // Enables GPIOs clock\r
+ TSL_RCC_AHBENR_Config(LocalBank->shield_sample);\r
+\r
+ // Bank shield configuration\r
+ /* Disables Hysteresis Register */\r
+ TSL_RI_HYSCR_Config(LocalBank->shield_sample);\r
+\r
+ /* Output PP config */\r
+ TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_channel);\r
+ /* 400kHz config */\r
+ TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_channel);\r
+ /* No pull up/pull down config */\r
+ TSL_GPIO_PUPDR_NO_PUPD_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_PUPDR_NO_PUPD_Config(LocalBank->shield_channel);\r
+ /* Set ODR */\r
+ TSL_GPIO_BR_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_BR_Config(LocalBank->shield_channel);\r
+ /* Output mode */\r
+ TSL_GPIO_MODER_OUT_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_MODER_OUT_Config(LocalBank->shield_channel);\r
+#endif\r
+\r
+ LocalNumberOfChannels = LocalBank->NbChannels;\r
+\r
+ for (idx_ch = 0;\r
+ idx_ch < LocalNumberOfChannels;\r
+ idx_ch++)\r
+ {\r
+ /* Enables GPIOs clock */\r
+ TSL_RCC_AHBENR_Config(p_chSrc->t_sample);\r
+ TSL_RCC_AHBENR_Config(p_chSrc->t_channel);\r
+\r
+ // Bank/channel configuration\r
+ /* Disables Hysteresis Register */\r
+ TSL_RI_HYSCR_Config(p_chSrc->t_sample);\r
+ /* Output PP config */\r
+ TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_channel);\r
+ /* 400kHz config */\r
+ TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_channel);\r
+ /* No pull up/pull down config */\r
+ TSL_GPIO_PUPDR_NO_PUPD_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_PUPDR_NO_PUPD_Config(p_chSrc->t_channel);\r
+ /* Set ODR */\r
+ TSL_GPIO_BR_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_BR_Config(p_chSrc->t_channel);\r
+ /* Output mode */\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_channel);\r
+\r
+ p_chSrc++;\r
+ }\r
+ }\r
+\r
+ /* Enable RI Switch */\r
+ RI->ASCR1 &= (uint32_t)(~0x80000000); // ADC analog switches open !!!\r
+\r
+ return TSL_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures a Bank.\r
+ * @param[in] idx_bk Index of the Bank to configure\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_tIndex_T index;\r
+ TSL_tIndex_T idx_dest;\r
+ TSL_tIndex_T idx_ch;\r
+ CONST TSL_ChannelDest_T *p_chDest; // Pointer to the current channel\r
+ CONST TSL_ChannelSrc_T *p_chSrc; // Pointer to the current channel\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+\r
+ for (index = 0;index < SIZEOFBANKCONF;index++)\r
+ {\r
+ TSL_BankSampleConf[index] = 0x00000000;\r
+ TSL_BankChannelConf[index] = 0x00000000;\r
+ }\r
+\r
+ NumberOfChannels = bank->NbChannels;\r
+ NumberOfChannelOn = 0;\r
+ GroupToCheck = 0;//init group to check\r
+\r
+ p_chDest = bank->p_chDest;\r
+ p_chSrc = bank->p_chSrc;\r
+ for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)\r
+ {\r
+ // Get index in the result array associated to the current channel\r
+ idx_dest = p_chDest->IdxDest;\r
+\r
+ if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)\r
+ {\r
+ TSL_BankConf(TSL_BankSampleConf, p_chSrc->t_sample);\r
+ TSL_BankConf(TSL_BankChannelConf, p_chSrc->t_channel);\r
+ GroupToCheck |= (1 << (p_chSrc->IdxSrc));\r
+ NumberOfChannelOn++;\r
+ }\r
+\r
+ p_chSrc++;\r
+ p_chDest++;\r
+ }\r
+\r
+#if (TSLPRM_USE_GPIOA)\r
+ GPIOA_IDR_Mask = TSL_BankSampleConf[4];\r
+#endif\r
+\r
+#if (TSLPRM_USE_GPIOB)\r
+ GPIOB_IDR_Mask = TSL_BankSampleConf[7];\r
+#endif\r
+\r
+#if (TSLPRM_USE_GPIOC)\r
+ GPIOC_IDR_Mask = TSL_BankSampleConf[10];\r
+#endif\r
+\r
+#if (TSLPRM_USE_GPIOF)\r
+ GPIOF_IDR_Mask = TSL_BankSampleConf[13];\r
+#endif\r
+\r
+#if (TSLPRM_USE_GPIOG)\r
+ GPIOG_IDR_Mask = TSL_BankSampleConf[16];\r
+#endif\r
+\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ if (NumberOfChannelOn != 0)\r
+ {\r
+ TSL_BankConf(TSL_BankSampleConf, bank->shield_sample);\r
+ TSL_BankConf(TSL_BankChannelConf, bank->shield_channel);\r
+ }\r
+#endif\r
+\r
+ return TSL_STATUS_OK;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check which group is not over\r
+ * @param[in] EndedGroup\r
+ * @retval None\r
+ */\r
+void TSL_acq_GroupDone(uint16_t EndedGroup)\r
+{\r
+ uint16_t i;\r
+\r
+ for (i = 0;i < 11;i++)\r
+ {\r
+ if ((EndedGroup & (1 << i)) != (1 << i))\r
+ {\r
+ tab_MeasurementCounter[i] = TSL_Params.AcqMax + 1;\r
+ }\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Start acquisition on a previously configured bank\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_BankStartAcq(void)\r
+{\r
+ CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);\r
+ TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;\r
+ TSL_tNb_T LocalNumberOfChannels = 0;\r
+ TSL_tIndex_T BankIndex;\r
+\r
+ uint16_t MeasurementCounter = 0;\r
+ CONST TSL_ChannelSrc_T *p_chSrc;\r
+ TSL_tIndex_T idx_ch;\r
+ uint16_t GroupToCheckMask = 0;\r
+ uint32_t GPIO_IDR_Mask = 0;\r
+ uint8_t Check_Input = 0;\r
+\r
+#if (TSLPRM_USE_GPIOA)\r
+ uint16_t TSL_GPIOA_IDR = 0;\r
+#endif\r
+#if (TSLPRM_USE_GPIOB)\r
+ uint16_t TSL_GPIOB_IDR = 0;\r
+#endif\r
+#if (TSLPRM_USE_GPIOC)\r
+ uint16_t TSL_GPIOC_IDR = 0;\r
+#endif\r
+#if (TSLPRM_USE_GPIOF)\r
+ uint16_t TSL_GPIOF_IDR = 0;\r
+#endif\r
+#if (TSLPRM_USE_GPIOG)\r
+ uint16_t TSL_GPIOG_IDR = 0;\r
+#endif\r
+ uint16_t GPIO_IDR = 0;\r
+\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __disable_irq();\r
+#endif\r
+#if (TSLPRM_IODEF > 0)\r
+ //============================\r
+ // All GPIOs in Input floating\r
+ //============================\r
+ for (BankIndex = 0; BankIndex < NumberOfBanks; BankIndex++)\r
+ {\r
+ LocalBank = &(TSL_Globals.Bank_Array[BankIndex]);\r
+ p_chSrc = LocalBank->p_chSrc;\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ TSL_GPIO_MODER_IN_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_MODER_IN_Config(LocalBank->shield_channel);\r
+#endif\r
+\r
+ LocalNumberOfChannels = LocalBank->NbChannels;\r
+\r
+ for (idx_ch = 0;\r
+ idx_ch < LocalNumberOfChannels;\r
+ idx_ch++)\r
+ {\r
+ TSL_GPIO_MODER_IN_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_MODER_IN_Config(p_chSrc->t_channel);\r
+\r
+ p_chSrc++;\r
+ }\r
+ }\r
+#endif\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __enable_irq();\r
+#endif\r
+\r
+ /* Open the analog switches */\r
+ RI->ASCR1 &= (uint32_t)(~(TSL_BankSampleConf[0] | TSL_BankChannelConf[0]));\r
+ RI->ASCR2 &= (uint32_t)(~(TSL_BankSampleConf[1] | TSL_BankChannelConf[1]));\r
+\r
+ /* All IO to pushpull LOW for discharging all capacitors (Ctouch and Csense) */\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __disable_irq();\r
+#endif\r
+ /* Discharging sampling capacitor and CTouch */\r
+#if (TSLPRM_USE_GPIOA)\r
+ GPIOA->ODR &= (uint32_t)(~(TSL_BankSampleConf[4] | TSL_BankChannelConf[4]));\r
+ GPIOA->MODER = (GPIOA->MODER & (uint32_t)(~(TSL_BankSampleConf[2] | TSL_BankChannelConf[2]))) | (TSL_BankSampleConf[3] | TSL_BankChannelConf[3]);\r
+#endif\r
+#if (TSLPRM_USE_GPIOB)\r
+ GPIOB->ODR &= (uint32_t)(~(TSL_BankSampleConf[7] | TSL_BankChannelConf[7]));\r
+ GPIOB->MODER = (GPIOB->MODER & (uint32_t)(~(TSL_BankSampleConf[5] | TSL_BankChannelConf[5]))) | (TSL_BankSampleConf[6] | TSL_BankChannelConf[6]);\r
+#endif\r
+#if (TSLPRM_USE_GPIOC)\r
+ GPIOC->ODR &= (uint32_t)(~(TSL_BankSampleConf[10] | TSL_BankChannelConf[10]));\r
+ GPIOC->MODER = (GPIOC->MODER & (uint32_t)(~(TSL_BankSampleConf[8] | TSL_BankChannelConf[8]))) | (TSL_BankSampleConf[9] | TSL_BankChannelConf[9]);\r
+#endif\r
+#if (TSLPRM_USE_GPIOF)\r
+ GPIOF->ODR &= (uint32_t)(~(TSL_BankSampleConf[13] | TSL_BankChannelConf[13]));\r
+ GPIOF->MODER = (GPIOF->MODER & (uint32_t)(~(TSL_BankSampleConf[11] | TSL_BankChannelConf[11]))) | (TSL_BankSampleConf[12] | TSL_BankChannelConf[12]);\r
+#endif\r
+#if (TSLPRM_USE_GPIOG)\r
+ GPIOG->ODR &= (uint32_t)(~(TSL_BankSampleConf[16] | TSL_BankChannelConf[16]));\r
+ GPIOG->MODER = (GPIOG->MODER & (uint32_t)(~(TSL_BankSampleConf[14] | TSL_BankChannelConf[14]))) | (TSL_BankSampleConf[15] | TSL_BankChannelConf[15]);\r
+#endif\r
+\r
+\r
+\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __enable_irq();\r
+#endif\r
+\r
+ /* Wait a while for a good discharging of all capacitors */\r
+ SoftDelay(50); // ~14µs with fHCLK = 32MHz\r
+ //this time depends of the size of the sampling capacitor\r
+\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __disable_irq();\r
+#endif\r
+ /* All IO in input floating */\r
+#if (TSLPRM_USE_GPIOA)\r
+ GPIOA->MODER &= (uint32_t)(~(TSL_BankSampleConf[2] | TSL_BankChannelConf[2]));\r
+#endif\r
+#if (TSLPRM_USE_GPIOB)\r
+ GPIOB->MODER &= (uint32_t)(~(TSL_BankSampleConf[5] | TSL_BankChannelConf[5]));\r
+#endif\r
+#if (TSLPRM_USE_GPIOC)\r
+ GPIOC->MODER &= (uint32_t)(~(TSL_BankSampleConf[8] | TSL_BankChannelConf[8]));\r
+#endif\r
+#if (TSLPRM_USE_GPIOF)\r
+ GPIOF->MODER &= (uint32_t)(~(TSL_BankSampleConf[11] | TSL_BankChannelConf[11]));\r
+#endif\r
+#if (TSLPRM_USE_GPIOG)\r
+ GPIOG->MODER &= (uint32_t)(~(TSL_BankSampleConf[14] | TSL_BankChannelConf[14]));\r
+#endif\r
+\r
+ /* set the IO to Vdd (io in push-pull HIGH when in output mode) */\r
+#if (TSLPRM_USE_GPIOA)\r
+ GPIOA->ODR |= (TSL_BankSampleConf[4] | TSL_BankChannelConf[4]); /* HIGH level */\r
+#endif\r
+#if (TSLPRM_USE_GPIOB)\r
+ GPIOB->ODR |= (TSL_BankSampleConf[7] | TSL_BankChannelConf[7]); /* HIGH level */\r
+#endif\r
+#if (TSLPRM_USE_GPIOC)\r
+ GPIOC->ODR |= (TSL_BankSampleConf[10] | TSL_BankChannelConf[10]); /* HIGH level */\r
+#endif\r
+#if (TSLPRM_USE_GPIOF)\r
+ GPIOF->ODR |= (TSL_BankSampleConf[13] | TSL_BankChannelConf[13]); /* HIGH level */\r
+#endif\r
+#if (TSLPRM_USE_GPIOG)\r
+ GPIOG->ODR |= (TSL_BankSampleConf[16] | TSL_BankChannelConf[16]); /* HIGH level */\r
+#endif\r
+\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __enable_irq();\r
+#endif\r
+\r
+ /* Close the sampling capacitor analog switch */\r
+ RI->ASCR1 |= (TSL_BankSampleConf[0]);\r
+ RI->ASCR2 |= (TSL_BankSampleConf[1]);\r
+\r
+\r
+ /* Loop while all the 1st channel of each group have not reach the VIH level */\r
+ do\r
+ {\r
+\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __disable_irq();\r
+#endif\r
+ /* Charging Ctouch by connecting the IO to Vdd (io in push-pull HIGH) */\r
+#if (TSLPRM_USE_GPIOA)\r
+ GPIOA->MODER |= (TSL_BankChannelConf[3]); /* Output push pull config */\r
+#endif\r
+#if (TSLPRM_USE_GPIOB)\r
+ GPIOB->MODER |= (TSL_BankChannelConf[6]); /* Output push pull config */\r
+#endif\r
+#if (TSLPRM_USE_GPIOC)\r
+ GPIOC->MODER |= (TSL_BankChannelConf[9]); /* Output push pull config */\r
+#endif\r
+#if (TSLPRM_USE_GPIOF)\r
+ GPIOF->MODER |= (TSL_BankChannelConf[12]); /* Output push pull config */\r
+#endif\r
+#if (TSLPRM_USE_GPIOG)\r
+ GPIOG->MODER |= (TSL_BankChannelConf[15]); /* Output push pull config */\r
+#endif\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __enable_irq();\r
+#endif\r
+\r
+ /* Wait a while for a good charging (programmable delay) */\r
+ SoftDelay(1);\r
+\r
+ /* test GPIOx->IDR bit + group configuration for each channel */\r
+\r
+#if (TSLPRM_USE_GPIOA)\r
+ TSL_GPIOA_IDR = GPIOA->IDR;\r
+ if ((TSL_GPIOA_IDR & GPIOA_IDR_Mask) != 0)\r
+ {\r
+ Check_Input = 1;\r
+ GPIOA_IDR_Mask &= (uint32_t)(~TSL_GPIOA_IDR);\r
+ }\r
+#endif\r
+\r
+#if (TSLPRM_USE_GPIOB)\r
+ TSL_GPIOB_IDR = GPIOB->IDR;\r
+ if ((TSL_GPIOB_IDR & GPIOB_IDR_Mask) != 0)\r
+ {\r
+ Check_Input = (1 << 1);\r
+ GPIOB_IDR_Mask &= (uint32_t)(~TSL_GPIOB_IDR);\r
+ }\r
+#endif\r
+\r
+#if (TSLPRM_USE_GPIOC)\r
+ TSL_GPIOC_IDR = GPIOC->IDR;\r
+ if ((TSL_GPIOC_IDR & GPIOC_IDR_Mask) != 0)\r
+ {\r
+ Check_Input = (1 << 2);\r
+ GPIOC_IDR_Mask &= (uint32_t)(~TSL_GPIOC_IDR);\r
+ }\r
+#endif\r
+\r
+#if (TSLPRM_USE_GPIOF)\r
+ TSL_GPIOF_IDR = GPIOF->IDR;\r
+ if ((TSL_GPIOF_IDR & GPIOF_IDR_Mask) != 0)\r
+ {\r
+ Check_Input = (1 << 5);\r
+ GPIOF_IDR_Mask &= (uint32_t)(~TSL_GPIOF_IDR);\r
+ }\r
+#endif\r
+\r
+#if (TSLPRM_USE_GPIOG)\r
+ TSL_GPIOG_IDR = GPIOG->IDR;\r
+ if ((TSL_GPIOG_IDR & GPIOG_IDR_Mask) != 0)\r
+ {\r
+ Check_Input = (1 << 6);\r
+ GPIOG_IDR_Mask &= (uint32_t)(~TSL_GPIOG_IDR);\r
+ }\r
+#endif\r
+\r
+\r
+ if (Check_Input)\r
+ {\r
+ p_chSrc = bank->p_chSrc;\r
+ for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)\r
+ {\r
+ GroupToCheckMask = (1 << (p_chSrc->IdxSrc));\r
+ if ((GroupToCheck & GroupToCheckMask) == (GroupToCheckMask))\r
+ {\r
+ GPIO_IDR_Mask = (1 << TSL_CHANNEL_IO(p_chSrc->t_sample));\r
+\r
+ switch (TSL_CHANNEL_PORT(p_chSrc->t_sample))\r
+ {\r
+#if (TSLPRM_USE_GPIOA)\r
+ case 0: GPIO_IDR = TSL_GPIOA_IDR; break;\r
+#endif\r
+#if (TSLPRM_USE_GPIOB)\r
+ case 1: GPIO_IDR = TSL_GPIOB_IDR; break;\r
+#endif\r
+#if (TSLPRM_USE_GPIOC)\r
+ case 2: GPIO_IDR = TSL_GPIOC_IDR; break;\r
+#endif\r
+#if (TSLPRM_USE_GPIOF)\r
+ case 5: GPIO_IDR = TSL_GPIOF_IDR; break;\r
+#endif\r
+#if (TSLPRM_USE_GPIOG)\r
+ case 6: GPIO_IDR = TSL_GPIOG_IDR; break;\r
+#endif\r
+ default: break;\r
+ }\r
+\r
+ if ((GPIO_IDR & GPIO_IDR_Mask) == GPIO_IDR_Mask)\r
+ {\r
+ tab_MeasurementCounter[p_chSrc->IdxSrc] = MeasurementCounter;\r
+ GroupToCheck &= (uint32_t)(~(1 << (p_chSrc->IdxSrc)));\r
+ Check_Input &= (uint32_t)(~(1 << TSL_CHANNEL_PORT(p_chSrc->t_sample)));\r
+ }\r
+ }\r
+ p_chSrc++;\r
+ }\r
+ }\r
+\r
+ MeasurementCounter++;\r
+\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __disable_irq();\r
+#endif\r
+ /* Configure All channels in input floating */\r
+#if (TSLPRM_USE_GPIOA)\r
+ GPIOA->MODER &= (uint32_t)(~(TSL_BankChannelConf[2]));\r
+#endif\r
+#if (TSLPRM_USE_GPIOB)\r
+ GPIOB->MODER &= (uint32_t)(~(TSL_BankChannelConf[5]));\r
+#endif\r
+#if (TSLPRM_USE_GPIOC)\r
+ GPIOC->MODER &= (uint32_t)(~(TSL_BankChannelConf[8]));\r
+#endif\r
+#if (TSLPRM_USE_GPIOF)\r
+ GPIOF->MODER &= (uint32_t)(~(TSL_BankChannelConf[11]));\r
+#endif\r
+#if (TSLPRM_USE_GPIOG)\r
+ GPIOG->MODER &= (uint32_t)(~(TSL_BankChannelConf[14]));\r
+#endif\r
+\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __enable_irq();\r
+#endif\r
+\r
+ /* Charging the Csense cap with connecting it to Ctouch by closing the analog switch */\r
+ RI->ASCR1 |= (TSL_BankChannelConf[0]);\r
+ RI->ASCR2 |= (TSL_BankChannelConf[1]);\r
+\r
+ /* Wait a while for a good charge transfering (programmable delay) */\r
+ SoftDelay(1);\r
+\r
+ RI->ASCR1 &= (uint32_t)(~(TSL_BankChannelConf[0]));\r
+ RI->ASCR2 &= (uint32_t)(~(TSL_BankChannelConf[1]));\r
+\r
+ /*it's better to implement this like that because it's much more faster than to put this test in the "while test" below */\r
+ if (MeasurementCounter > TSL_Params.AcqMax)\r
+ {\r
+ TSL_acq_GroupDone(GroupToCheck);\r
+ __NOP();\r
+ break;\r
+ }\r
+\r
+ }\r
+ while (GroupToCheck != 0);\r
+\r
+\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __disable_irq();\r
+#endif\r
+ //====================\r
+ // All GPIOs in PP Low\r
+ //====================\r
+ for (BankIndex = 0; BankIndex < NumberOfBanks; BankIndex++)\r
+ {\r
+ LocalBank = &(TSL_Globals.Bank_Array[BankIndex]);\r
+ p_chSrc = LocalBank->p_chSrc;\r
+\r
+#if (TSLPRM_USE_SHIELD > 0)\r
+ TSL_GPIO_BR_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_BR_Config(LocalBank->shield_channel);\r
+ TSL_GPIO_MODER_OUT_Config(LocalBank->shield_sample);\r
+ TSL_GPIO_MODER_OUT_Config(LocalBank->shield_channel);\r
+#endif\r
+\r
+ LocalNumberOfChannels = LocalBank->NbChannels;\r
+\r
+ for (idx_ch = 0;\r
+ idx_ch < LocalNumberOfChannels;\r
+ idx_ch++)\r
+ {\r
+ TSL_GPIO_BR_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_BR_Config(p_chSrc->t_channel);\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);\r
+ TSL_GPIO_MODER_OUT_Config(p_chSrc->t_channel);\r
+\r
+ p_chSrc++;\r
+ }\r
+ }\r
+#if (TSLPRM_PROTECT_IO_ACCESS > 0)\r
+ __enable_irq();\r
+#endif\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Wait end of acquisition\r
+ * @param None\r
+ * @retval status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void)\r
+{\r
+ TSL_Status_enum_T retval = TSL_STATUS_BUSY;\r
+ retval = TSL_STATUS_OK;\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the current measure\r
+ * @param[in] index Index of the measure source\r
+ * @retval Measure\r
+ */\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index)\r
+{\r
+ return(tab_MeasurementCounter[index]);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check noise (not used)\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void)\r
+{\r
+ return TSL_ACQ_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Process the TS Interrupt routine\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_ProcessIT(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief Check if a filter must be used on the current channel (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @retval Result TRUE if a filter can be applied\r
+ */\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh)\r
+{\r
+ return TSL_TRUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Compute the Delta value\r
+ * @param[in] ref Reference value\r
+ * @param[in] meas Last Measurement value\r
+ * @retval Delta value\r
+ */\r
+TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas)\r
+{\r
+ return((TSL_tDelta_T)(ref - meas));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Compute the Measurement value\r
+ * @param[in] ref Reference value\r
+ * @param[in] delta Delta value\r
+ * @retval Measurement value\r
+ */\r
+TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta)\r
+{\r
+ return((TSL_tMeas_T)(ref - delta));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if the Reference is incorrect (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @retval Result TRUE if the Reference is out of range\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh)\r
+{\r
+ return TSL_FALSE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if the measure has crossed the reference target (not used)\r
+ * @param[in] pCh Pointer on the channel data information\r
+ * @param[in] new_meas Measure of the last acquisition on this channel\r
+ * @retval Result TRUE if the Reference is valid\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas)\r
+{\r
+ return TSL_TRUE;\r
+}\r
+\r
+\r
+#if defined(__IAR_SYSTEMS_ICC__) // IAR/EWARM\r
+#pragma optimize=medium\r
+#elif defined(__CC_ARM) // Keil/MDK-ARM\r
+#pragma O1\r
+#pragma Ospace\r
+#elif defined(__TASKING__) // Altium/Tasking\r
+#pragma optimize O0\r
+#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit\r
+#pragma GCC push_options\r
+#pragma GCC optimize ("O0")\r
+#endif\r
+/**\r
+ * @brief Software delay (private routine)\r
+ * @param val Wait delay\r
+ * With fHCLK = 32MHz: 1 = ~1µs, 50 = ~14µs, 100 = ~25µs, 200 = ~50µs\r
+ * @retval None\r
+ */\r
+void SoftDelay(uint16_t val)\r
+{\r
+ __IO uint16_t i;\r
+ for (i = val; i > 0; i--)\r
+ {}\r
+}\r
+#if defined(__TASKING__)\r
+#pragma endoptimize\r
+#endif\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_acq_stm8tl5x.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the PXS acquisition\r
+ * on STM8TL5x products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_acq_stm8tl5x.h"\r
+#include "tsl_globals.h"\r
+#include "stm8tl5x_it.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+#define EPCC_INIT_VALUE (0x80)\r
+#define CS_MIDDLE_VALUE (17)\r
+#define CS_MAX_VALUE (32)\r
+#define MAX_MEASURE (0xFFFF)\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))\r
+#define IS_SOURCE_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_CHANNELS)))\r
+#define IS_EPCC_STATUS_OK(STATUS) ((STATUS & TSL_EPCC_CHANGE_MASK) != 0)\r
+#define IS_CSSEL_OK(CSSEL) (((CSSEL) == 0) || (((CSSEL) > 0) && ((CSSEL) < CS_MAX_VALUE)))\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+TSL_BankConfig_T PXS_BankConfig[TSLPRM_TOTAL_BANKS];\r
+CONST uint8_t PXS_CSsorting[] = {0, 1, 2, 8, 3, 4, 5, 9, 6, 10, 16, 11, 7, 12, 17, 13, 18, 19, 14, 24, 15, 20, 25, 21, 26, 22, 27, 23, 28, 29, 30, 31};\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+void TSL_PXS_CS_CalibrateBank(TSL_tIndex_T idx_bk);\r
+int8_t TSL_PXS_EPCC_CalibrateBank(TSL_tIndex_T bank);\r
+TSL_Status_enum_T TSL_PXS_EPCC_CalibrateZone(CONST TSL_Zone_T *);\r
+void SoftDelay(uint32_t val);\r
+\r
+/**\r
+ * @brief Initializes the acquisition module.\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_Init(void)\r
+{\r
+\r
+ TSL_Status_enum_T retval = TSL_STATUS_OK;\r
+\r
+ TSL_tIndex_T i;\r
+ TSL_tIndex_T j;\r
+ TSL_tIndex_T idx_bk; // Bank index\r
+ uint16_t TxInUseMask = 0;\r
+ uint16_t RxInUseMask = 0;\r
+ CONST TSL_Bank_T *bank;\r
+ uint8_t *CSArray;\r
+\r
+ // Enable the PXS IP clock\r
+ CLK->PCKENR1 |= CLK_PCKENR1_PXS;\r
+\r
+ // Initialization of PXS IP\r
+ PXS->CKCR1 &= (uint8_t)~PXS_CKCR1_PRESC;\r
+\r
+#if (TSLPRM_PXS_HSI == 16000)\r
+ PXS->CKCR1 |= PXS_CKCR1_16MHZ;\r
+#elif (TSLPRM_PXS_HSI == 8000)\r
+ PXS->CKCR1 |= PXS_CKCR1_8MHZ;\r
+#elif (TSLPRM_PXS_HSI == 4000)\r
+ PXS->CKCR1 |= PXS_CKCR1_4MHZ;\r
+#elif (TSLPRM_PXS_HSI == 2000)\r
+ PXS->CKCR1 |= PXS_CKCR1_2MHZ;\r
+#elif (TSLPRM_PXS_HSI == 1000)\r
+ PXS->CKCR1 |= PXS_CKCR1_1MHZ;\r
+#elif (TSLPRM_PXS_HSI == 500)\r
+ PXS->CKCR1 |= PXS_CKCR1_500KHZ;\r
+#elif (TSLPRM_PXS_HSI == 250)\r
+ PXS->CKCR1 |= PXS_CKCR1_250KHZ;\r
+#elif (TSLPRM_PXS_HSI == 125)\r
+ PXS->CKCR1 |= PXS_CKCR1_125KHZ;\r
+#else\r
+ PXS->CKCR1 |= PXS_CKCR1_16MHZ; // Default\r
+#endif\r
+\r
+ PXS->CKCR2 = (uint8_t)(((uint8_t)TSLPRM_PXS_UP_LENGTH & 0x07) << 4) | ((uint8_t)TSLPRM_PXS_PASS_LENGTH & 0x07);\r
+\r
+#if TSLPRM_PXS_RF_DETECTION > 0\r
+ enablePXSNoiseDetection();\r
+#endif\r
+\r
+ setPXSStab(TSLPRM_PXS_STAB);\r
+ setPXSBias(TSLPRM_PXS_BIAS);\r
+\r
+ // Initialization of the GPIO shared with the used TX\r
+ for (i = 0; i < TSLPRM_TOTAL_BANKS; i++)\r
+ {\r
+ bank = &(TSL_Globals.Bank_Array[i]);\r
+ CSArray = PXS_BankConfig[i].CSSEL;\r
+ TxInUseMask |= bank->msk_TX;\r
+ // Set the mask with the receivers use as receiver or as transmitter\r
+ RxInUseMask |= bank->msk_RXEN;\r
+ // Set the CS to 0\r
+ for (j = 0; j <= TSLPRM_HIGH_CHANNEL_NB; j++)\r
+ {\r
+ *CSArray = 0;\r
+ CSArray++;\r
+ }\r
+ }\r
+\r
+ GPIOD->ODR &= (uint8_t)(~(TxInUseMask & 0x00FF));\r
+ // Set the port as output\r
+ GPIOD->DDR |= (uint8_t)(TxInUseMask & 0x00FF);\r
+ // Configure the port as open-drain\r
+ GPIOD->CR1 &= (uint8_t)(~(TxInUseMask & 0x00FF));\r
+#if TSLPRM_PXS_INACTIVE_TX > 0\r
+ // Configure as floating\r
+ GPIOD->ODR |= (uint8_t)(TxInUseMask & 0x00FF);\r
+#else\r
+ // Drive them to VSS\r
+ GPIOD->ODR &= (uint8_t)(~(TxInUseMask & 0x00FF));\r
+#endif\r
+ GPIOB->ODR &= (uint8_t)(~((TxInUseMask & 0xFF00) >> 8));\r
+ // Set the port as output\r
+ GPIOB->DDR |= (uint8_t)((TxInUseMask & 0xFF00) >> 8);\r
+ // Configure the port as open-drain\r
+ GPIOB->CR1 &= (uint8_t)(~((TxInUseMask & 0xFF00) >> 8));\r
+#if TSLPRM_PXS_INACTIVE_TX > 0\r
+ // Configure as floating\r
+ GPIOB->ODR |= (uint8_t)((TxInUseMask & 0xFF00) >> 8);\r
+#else\r
+ // Drive it to VSS\r
+ GPIOB->ODR &= (uint8_t)(~((TxInUseMask & 0xFF00) >> 8));\r
+#endif\r
+\r
+ enablePXS();\r
+\r
+#if TSLPRM_PXS_INACTIVE_RX > 0\r
+ PXS->RXINSR = 0x3FF;\r
+#else\r
+ PXS->RXINSR = 0x0000;\r
+#endif\r
+\r
+#if TSLPRM_PXS_RX_COUPLING > 0\r
+ enablePXSCoupling();\r
+#else\r
+ disablePXSCoupling()\r
+#endif\r
+\r
+#if TSLPRM_PXS_SYNCHRONIZE > 0\r
+ enablePXSSync();\r
+#if TSLPRM_PXS_SYNCHRO_EDGE > 0\r
+ selectPXSSyncRisingEdge();\r
+#else\r
+ selectPXSSyncFallingEdge();\r
+#endif\r
+#else\r
+ disablePXSSync();\r
+#endif\r
+\r
+#if TSLPRM_USE_ACQ_INTERRUPT > 0\r
+ enablePXSInterrupts(PXS_CR2_EOCITEN);\r
+#endif\r
+ // Configure the acquisition mode\r
+ PXS->RXCR3 = (uint16_t)RxInUseMask;\r
+ PXS->RXCR2 = (uint16_t)RxInUseMask;\r
+\r
+#if TSLPRM_ACQ_MAX > 0\r
+ PXS->MAXR = TSLPRM_ACQ_MAX;\r
+ PXS->MAXENR = 0x03FF;\r
+#else\r
+ PXS->MAXENR = 0;\r
+#endif\r
+\r
+ // Calibrate the CS for all banks\r
+ for (idx_bk = 0;idx_bk < TSLPRM_TOTAL_BANKS;idx_bk++)\r
+ {\r
+ TSL_PXS_CS_CalibrateBank(idx_bk);\r
+ }\r
+\r
+\r
+ // Calibrate the EPCC for all banks\r
+ for (idx_bk = 0;idx_bk < TSLPRM_TOTAL_BANKS;idx_bk++)\r
+ {\r
+ if (TSL_PXS_EPCC_CalibrateBank(idx_bk) > 0)\r
+ {\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+ }\r
+#if TSLPRM_PXS_LOW_POWER_MODE > 0\r
+ setPXSLowPower();\r
+#else\r
+ resetPXSLowPower();\r
+#endif\r
+\r
+ return retval;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Calibrate the CS for a selected acquisition bank\r
+ * @param[in] idx_bk Index of the bank\r
+ * @retval Number of Receivers not correctly calibrated\r
+ */\r
+void TSL_PXS_CS_CalibrateBank(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_tIndex_T idx_ch;\r
+ uint8_t currentCS = 24;\r
+ uint8_t CS_delta = 4; // Value to add/substract to/from the current CS\r
+ CONST TSL_Bank_T *bank;\r
+ CONST uint16_t targetCount = TSLPRM_KEY_TARGET_REFERENCE / TSLPRM_KEY_TARGET_ATTENUATION;\r
+ CONST uint16_t targetCountError = targetCount >> 3;\r
+ bool CalibrationDone = FALSE;\r
+ uint16_t measSup[TSLPRM_HIGH_CHANNEL_NB+1];\r
+ uint16_t measInf[TSLPRM_HIGH_CHANNEL_NB+1];\r
+ uint8_t CSsup[TSLPRM_HIGH_CHANNEL_NB+1];\r
+ uint8_t CSinf[TSLPRM_HIGH_CHANNEL_NB+1];\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+#if TSLPRM_USE_ACQ_INTERRUPT == 0\r
+ enablePXSInterrupts(PXS_CR2_EOCITEN);\r
+#endif\r
+\r
+ bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ resetPXSLowPower();\r
+ TSL_acq_BankConfig(idx_bk);\r
+\r
+ PXS->MAXR = TSLPRM_KEY_TARGET_REFERENCE;\r
+\r
+ WFE->CR1 |= WFE_CR1_PXS_EV;\r
+ for (idx_ch = 0; idx_ch <= TSLPRM_HIGH_CHANNEL_NB; idx_ch++)\r
+ {\r
+ PXS->RXEPCCSELR[idx_ch] = 0;\r
+ PXS->RXCSSELR[idx_ch] = currentCS;\r
+ CSsup[idx_ch] = 0;\r
+ CSinf[idx_ch] = 0;\r
+ measInf[idx_ch] = 0;\r
+ measSup[idx_ch] = 0xFFFF;\r
+\r
+ }\r
+ do\r
+ {\r
+ startPXSAcquisition();\r
+ wfe();\r
+ clearPXS_ISR_EOCF;\r
+ for (idx_ch = 0; idx_ch <= TSLPRM_HIGH_CHANNEL_NB; idx_ch++)\r
+ {\r
+ if (bank->msk_channels & (uint16_t)((uint16_t)1 << idx_ch))\r
+ {\r
+ if (!(PXS->RXSR & (uint16_t)((uint16_t)1 << idx_ch)) || (PXS->RXCNTR[idx_ch] > targetCount - targetCountError))\r
+ {\r
+ PXS->RXCSSELR[idx_ch] -= 8;\r
+ }\r
+ }\r
+ }\r
+ currentCS -= 8;\r
+ }\r
+ while (currentCS);\r
+\r
+\r
+ for (idx_ch = 0; idx_ch <= TSLPRM_HIGH_CHANNEL_NB; idx_ch++)\r
+ {\r
+ PXS->RXCSSELR[idx_ch] += CS_delta;\r
+ }\r
+\r
+ do\r
+ {\r
+ CS_delta >>= 1;\r
+ if ((CS_delta == 0) && (CalibrationDone == FALSE))\r
+ {\r
+ CalibrationDone = TRUE;\r
+ CS_delta = 1;\r
+ }\r
+\r
+ startPXSAcquisition();\r
+ wfe();\r
+ clearPXS_ISR_EOCF;\r
+ for (idx_ch = 0; idx_ch <= TSLPRM_HIGH_CHANNEL_NB; idx_ch++)\r
+ {\r
+ if (bank->msk_channels & (uint16_t)((uint16_t)1 << idx_ch))\r
+ {\r
+ if (!(PXS->RXSR & (uint16_t)((uint16_t)1 << idx_ch)) || (PXS->RXCNTR[idx_ch] > targetCount))\r
+ {\r
+ measSup[idx_ch] = PXS->RXCNTR[idx_ch];\r
+ CSsup[idx_ch] = PXS->RXCSSELR[idx_ch];\r
+ PXS->RXCSSELR[idx_ch] -= CS_delta;\r
+ }\r
+ else //if (PXS->RXCNTR[idx_ch] < targetCount )\r
+ {\r
+ measInf[idx_ch] = PXS->RXCNTR[idx_ch];\r
+ CSinf[idx_ch] = PXS->RXCSSELR[idx_ch];\r
+ PXS->RXCSSELR[idx_ch] += CS_delta;\r
+ }\r
+// else\r
+// {\r
+ // Do nothing (MISRA requirement)\r
+// }\r
+ }\r
+ }\r
+ }\r
+ while ((CalibrationDone == FALSE) || (CS_delta != 0));\r
+\r
+\r
+ // Restore configuration\r
+#if TSLPRM_ACQ_MAX > 0\r
+ PXS->MAXR = TSLPRM_ACQ_MAX;\r
+#else\r
+ PXS->MAXENR = 0;\r
+#endif\r
+\r
+ WFE->CR1 &= (uint8_t)~WFE_CR1_PXS_EV;\r
+#if TSLPRM_USE_ACQ_INTERRUPT == 0\r
+ disablePXSInterrupts(PXS_CR2_EOCITEN);\r
+#endif\r
+\r
+ // Store the CS\r
+ for (idx_ch = 0;idx_ch <= TSLPRM_HIGH_CHANNEL_NB;idx_ch++)\r
+ {\r
+ if ((measSup[idx_ch] == 0) || ((measSup[idx_ch] - targetCount) > (targetCount - measInf[idx_ch])))\r
+ {\r
+ PXS_BankConfig[idx_bk].CSSEL[idx_ch] = CSinf[idx_ch];\r
+ }\r
+ else\r
+ {\r
+ PXS_BankConfig[idx_bk].CSSEL[idx_ch] = CSsup[idx_ch];\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Calibrate the EPCC for a selected acquisition bank\r
+ * @param[in] idx_bk Index of the bank\r
+ * @retval Number Number of Receivers not correctly calibrated\r
+ */\r
+int8_t TSL_PXS_EPCC_CalibrateBank(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_tIndex_T idx_ch;\r
+ uint8_t currentEPCC, trial, goodEPCC = 0;\r
+ uint8_t EPCCtoCompute = 0; // Used to define if all the EPCC have their final value\r
+ uint8_t EPCC_delta = EPCC_INIT_VALUE; // Value to add/substract to/from the current EPCC\r
+ CONST TSL_Bank_T *bank;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+#if TSLPRM_USE_ACQ_INTERRUPT == 0\r
+ enablePXSInterrupts(PXS_CR2_EOCITEN);\r
+#endif\r
+\r
+ bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ resetPXSLowPower();\r
+ TSL_acq_BankConfig(idx_bk);\r
+\r
+ PXS->MAXR = 2 * TSLPRM_KEY_TARGET_REFERENCE;\r
+\r
+ WFE->CR1 |= WFE_CR1_PXS_EV;\r
+ for (idx_ch = 0; idx_ch <= TSLPRM_HIGH_CHANNEL_NB; idx_ch++)\r
+ {\r
+ PXS->RXEPCCSELR[idx_ch] = EPCC_delta;\r
+ if (bank->msk_channels & (uint16_t)((uint16_t)1 << idx_ch))\r
+ {\r
+ EPCCtoCompute++;\r
+ }\r
+ }\r
+ do\r
+ {\r
+ EPCC_delta >>= 1;\r
+ startPXSAcquisition();\r
+ wfe();\r
+ clearPXS_ISR_EOCF;\r
+ for (idx_ch = 0; idx_ch <= TSLPRM_HIGH_CHANNEL_NB; idx_ch++)\r
+ {\r
+ if (bank->msk_channels & (uint16_t)((uint16_t)1 << idx_ch))\r
+ {\r
+ if (!(PXS->RXSR & (uint16_t)((uint16_t)1 << idx_ch)) || (PXS->RXCNTR[idx_ch] > TSLPRM_KEY_TARGET_REFERENCE))\r
+ {\r
+ PXS->RXEPCCSELR[idx_ch] -= EPCC_delta;\r
+ }\r
+ else if (PXS->RXCNTR[idx_ch] < TSLPRM_KEY_TARGET_REFERENCE)\r
+ {\r
+ PXS->RXEPCCSELR[idx_ch] += EPCC_delta;\r
+ }\r
+ else\r
+ {\r
+ // Do nothing (MISRA requirement)\r
+ }\r
+ }\r
+ }\r
+ }\r
+ while (EPCC_delta >= 1);\r
+ // Second pass to fine-tune\r
+ trial = TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION;\r
+ do\r
+ {\r
+ startPXSAcquisition();\r
+ goodEPCC = 0; // Reset the goodEPCC variable\r
+ wfe();\r
+ clearPXS_ISR_EOCF;\r
+ for (idx_ch = 0; idx_ch <= TSLPRM_HIGH_CHANNEL_NB; idx_ch++)\r
+ {\r
+ if (bank->msk_channels & (uint16_t)((uint16_t)1 << idx_ch))\r
+ {\r
+ currentEPCC = PXS->RXEPCCSELR[idx_ch]; //this affectation allow to avoid computation of the structure address\r
+ if (!(PXS->RXSR & (uint16_t)((uint16_t)1 << idx_ch)) || (PXS->RXCNTR[idx_ch] > (TSLPRM_KEY_TARGET_REFERENCE + TSLPRM_KEY_TARGET_REFERENCE_ERROR)))\r
+ {\r
+ if (currentEPCC > 0)\r
+ {\r
+ if ((currentEPCC & 0x07) != 0)\r
+ {\r
+ currentEPCC--;\r
+ }\r
+ else\r
+ {\r
+ currentEPCC -= 3; // This is due to the non linearity of the EPCC\r
+ }\r
+ }\r
+ }\r
+ else if (PXS->RXCNTR[idx_ch] < (TSLPRM_KEY_TARGET_REFERENCE - TSLPRM_KEY_TARGET_REFERENCE_ERROR))\r
+ {\r
+ if (currentEPCC < 0xFF)\r
+ {\r
+ if ((currentEPCC & 0x07) != 0x07)\r
+ {\r
+ currentEPCC++;\r
+ }\r
+ else\r
+ {\r
+ currentEPCC += 2; // This is due to the non linearity of the EPCC\r
+ }\r
+ }\r
+ else // Invert the change in case the sorting is not reliable\r
+ {\r
+ currentEPCC--;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ goodEPCC++;\r
+ }\r
+ PXS->RXEPCCSELR[idx_ch] = currentEPCC;\r
+ }\r
+ }\r
+ trial--;\r
+ }\r
+ while ((goodEPCC < EPCCtoCompute) && (trial));\r
+\r
+ // Restore configuration\r
+#if TSLPRM_ACQ_MAX > 0\r
+ PXS->MAXR = TSLPRM_ACQ_MAX;\r
+#else\r
+ PXS->MAXENR = 0;\r
+#endif\r
+\r
+ WFE->CR1 &= (uint8_t)~WFE_CR1_PXS_EV;\r
+#if TSLPRM_USE_ACQ_INTERRUPT == 0\r
+ disablePXSInterrupts(PXS_CR2_EOCITEN);\r
+#endif\r
+\r
+ // Store the EPCC\r
+ for (idx_ch = 0;idx_ch <= TSLPRM_HIGH_CHANNEL_NB;idx_ch++)\r
+ {\r
+ PXS_BankConfig[idx_bk].EPCCSEL[idx_ch] = PXS->RXEPCCSELR[idx_ch];\r
+ }\r
+\r
+ return((int8_t)(EPCCtoCompute - goodEPCC));\r
+}\r
+\r
+\r
+#if TSLPRM_USE_ZONE > 0\r
+/**\r
+ * @brief Calibrate the EPCC for a set of acquisition banks.\r
+ * @param[in] zone Set of banks to calibrate the EPCC\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_PXS_EPCC_CalibrateZone(CONST TSL_Zone_T *zone)\r
+{\r
+ uint16_t idx_bk;\r
+ TSL_Status_enum_T retval = TSL_STATUS_OK;\r
+ for (idx_bk = 0; idx_bk < zone->NbBanks; idx_bk++)\r
+ {\r
+ if (TSL_PXS_EPCC_CalibrateBank(zone->BankIndex[idx_bk]) > 0)\r
+ {\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+ }\r
+ return(retval);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Test the reference and update the EPCC/CS if needed\r
+ * @param[in] pCh pointer on the channel data information\r
+ * @retval Result\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh)\r
+{\r
+ uint16_t reference, target_error = 0;\r
+ TSL_Bool_enum_T result = TSL_FALSE;\r
+\r
+ if (pCh->Flags.EPCCStatus != TSL_EPCC_STATUS_LOCKED)\r
+ {\r
+ reference = pCh->Ref;\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+ if (TSL_Globals.This_Obj->Type & TSL_OBJ_TYPE_TKEY_MASK)\r
+ {\r
+ target_error = TSLPRM_TOUCHKEY_REFERENCE_RANGE;\r
+ }\r
+#endif\r
+\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ if (TSL_Globals.This_Obj->Type & TSL_OBJ_TYPE_LINROT_MASK)\r
+ {\r
+ target_error = TSLPRM_LINROT_REFERENCE_RANGE;\r
+ }\r
+#endif\r
+ if ((reference != 0) && ((reference > (TSLPRM_KEY_TARGET_REFERENCE + target_error)) || (reference < (TSLPRM_KEY_TARGET_REFERENCE - target_error))))\r
+ {\r
+ if (reference < (TSLPRM_KEY_TARGET_REFERENCE - target_error))\r
+ {\r
+ pCh->Flags.EPCCStatus = TSL_EPCC_STATUS_INCREASE;\r
+ }\r
+ else if (reference > (TSLPRM_KEY_TARGET_REFERENCE + target_error))\r
+ {\r
+ pCh->Flags.EPCCStatus = TSL_EPCC_STATUS_DECREASE;\r
+ }\r
+ else\r
+ {\r
+ // Do nothing (MISRA requirement)\r
+ }\r
+ result = TSL_TRUE;\r
+ }\r
+ }\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Test if the measure has crossed the reference target\r
+ * @param[in] pCh Pointer to the channel Data under test\r
+ * @param[in] new_meas Measure of the last acquisition on this channel\r
+ * @retval Result Result of the test\r
+ */\r
+TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas)\r
+{\r
+ TSL_Bool_enum_T result = TSL_TRUE;\r
+ TSL_EPCCStatus_enum_T EPCCStatus;\r
+\r
+ EPCCStatus = pCh->Flags.EPCCStatus;\r
+ if (EPCCStatus & TSL_EPCC_CHANGE_MASK)\r
+ {\r
+ // If the previous reference and the new one are on each side of the reference target\r
+ // the EPCC is no more tested and the calibration continues.\r
+ if (((EPCCStatus == TSL_EPCC_STATUS_INCREASE) && (new_meas >= TSLPRM_KEY_TARGET_REFERENCE))\r
+ || ((EPCCStatus == TSL_EPCC_STATUS_DECREASE) && (new_meas <= TSLPRM_KEY_TARGET_REFERENCE)))\r
+ {\r
+ pCh->Flags.EPCCStatus = TSL_EPCC_STATUS_UNLOCKED;\r
+ }\r
+ else\r
+ {\r
+ result = TSL_FALSE;\r
+ }\r
+ }\r
+\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Increase or decrease the CS value\r
+ * @param[in] pCSSEL Address of the CS to be modified\r
+ * @param[in] change Define if the Cs must be increased or decreased\r
+ * @retval None\r
+ */\r
+void TSL_acq_UpdateCS(uint8_t *pCSSEL, TSL_EPCCStatus_enum_T change)\r
+{\r
+ uint16_t indexCS;\r
+\r
+ assert_param(IS_EPCC_STATUS_OK(change));\r
+ assert_param(IS_CSSEL_OK(*pCSSEL));\r
+\r
+ if (*pCSSEL > CS_MIDDLE_VALUE)\r
+ {\r
+ indexCS = (CS_MIDDLE_VALUE - 1);\r
+ }\r
+ else\r
+ {\r
+ indexCS = 0;\r
+ }\r
+ while ((PXS_CSsorting[indexCS] != *pCSSEL) && (indexCS < CS_MAX_VALUE))\r
+ {\r
+ indexCS++;\r
+ }\r
+ if (change == TSL_EPCC_STATUS_INCREASE)\r
+ {\r
+ *pCSSEL = PXS_CSsorting[indexCS + 1];\r
+ }\r
+ else\r
+ {\r
+ *pCSSEL = PXS_CSsorting[indexCS - 1];\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures a Bank.\r
+ * @param[in] idx_bk Index of the Bank to configure\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk)\r
+{\r
+ TSL_Status_enum_T retval = TSL_STATUS_OK;\r
+ uint16_t idx_ch;\r
+ TSL_ChannelFlags_T flags;\r
+ CONST TSL_Bank_T *bank = &(TSL_Globals.Bank_Array[idx_bk]);\r
+ CONST TSL_ChannelSrc_T *pchSrc = bank->p_chSrc;\r
+ CONST TSL_ChannelDest_T *pchDest = bank->p_chDest;\r
+ TSL_tMaskRX enabledRX = 0;\r
+ uint8_t *pEPCCSEL, *pCSSEL;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_BANK_INDEX_OK(idx_bk));\r
+\r
+ TSL_Globals.This_Bank = idx_bk;\r
+\r
+ selectPXSRxGroup(bank->msk_group);\r
+ for (idx_ch = 0;idx_ch < bank->NbChannels;idx_ch++)\r
+ {\r
+ flags = bank->p_chData[pchDest->IdxDest].Flags;\r
+ if (flags.ObjStatus == TSL_OBJ_STATUS_ON)\r
+ {\r
+ enabledRX |= (1 << pchSrc->IdxSrc);\r
+ if (flags.EPCCStatus & TSL_EPCC_CHANGE_MASK)\r
+ {\r
+ pEPCCSEL = &PXS_BankConfig[idx_bk].EPCCSEL[pchSrc->IdxSrc];\r
+ if (flags.EPCCStatus == TSL_EPCC_STATUS_INCREASE)\r
+ {\r
+ if ((*pEPCCSEL) < 0xFF)\r
+ {\r
+ if (((*pEPCCSEL) & 0x07) != 0x07)\r
+ {\r
+ (*pEPCCSEL)++;\r
+ }\r
+ else\r
+ {\r
+ if ((*pEPCCSEL) < 0xFE)\r
+ {\r
+ (*pEPCCSEL) += 2; // This is due to the non linearity of the PCC\r
+ }\r
+ else\r
+ {\r
+ (*pEPCCSEL)++;\r
+ }\r
+ }\r
+\r
+ }\r
+ else\r
+ {\r
+ pCSSEL = &PXS_BankConfig[idx_bk].CSSEL[pchSrc->IdxSrc];\r
+ if (*pCSSEL < 0x1F)\r
+ {\r
+ TSL_acq_UpdateCS(pCSSEL, TSL_EPCC_STATUS_INCREASE);\r
+ }\r
+ else\r
+ {}\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((*pEPCCSEL) > 0)\r
+ {\r
+ if (((*pEPCCSEL) & 0x07) != 0)\r
+ {\r
+ (*pEPCCSEL)--;\r
+ }\r
+ else\r
+ {\r
+ if ((*pEPCCSEL) > 3)\r
+ {\r
+ (*pEPCCSEL) -= 3; // This is due to the non linearity of the PCC\r
+ }\r
+ else\r
+ {\r
+ (*pEPCCSEL)--;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pCSSEL = &PXS_BankConfig[idx_bk].CSSEL[pchSrc->IdxSrc];\r
+ if (*pCSSEL > 0)\r
+ {\r
+ TSL_acq_UpdateCS(pCSSEL, TSL_EPCC_STATUS_DECREASE);\r
+ }\r
+ else\r
+ {}\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ // Next channel\r
+ pchSrc++;\r
+ pchDest++;\r
+ }\r
+\r
+ // The two following loops are more efficient than the two instructions in the same loop\r
+ for (idx_ch = 0;idx_ch <= TSLPRM_HIGH_CHANNEL_NB;idx_ch++)\r
+ {\r
+ PXS->RXCSSELR[idx_ch] = PXS_BankConfig[idx_bk].CSSEL[idx_ch];\r
+ }\r
+ for (idx_ch = 0;idx_ch <= TSLPRM_HIGH_CHANNEL_NB;idx_ch++)\r
+ {\r
+ PXS->RXEPCCSELR[idx_ch] = PXS_BankConfig[idx_bk].EPCCSEL[idx_ch];\r
+ }\r
+\r
+ PXS->TXENR = bank->msk_TX; // Enable the Tx selected (if any)\r
+ PXS->RXCR1 = bank->msk_channels; // Configure the Rx and the Tx function modes\r
+\r
+ // Enable the Rx which are not disabled including the potential Rx configured as Tx\r
+ PXS->RXENR = bank->msk_RXEN & ((uint16_t)(~bank->msk_channels) | enabledRX);\r
+\r
+ if (enabledRX == 0)\r
+ {\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+\r
+ return(retval);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Test if EPCC are changing\r
+ * @param[in] pCh Channel to be processed\r
+ * @retval bool Test result\r
+ */\r
+TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh)\r
+{\r
+ if (pCh->Flags.EPCCStatus & TSL_EPCC_CHANGE_MASK)\r
+ {\r
+ return (TSL_FALSE);\r
+ }\r
+ else\r
+ {\r
+ return(TSL_TRUE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Start acquisition on a previously configured bank\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_acq_BankStartAcq(void)\r
+{\r
+ // Start acquisition\r
+ startPXSAcquisition();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Wait end of acquisition\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_acq_BankWaitEOC(void)\r
+{\r
+ TSL_Status_enum_T retval = TSL_STATUS_BUSY;\r
+\r
+ if (checkPXSInterruptStatusFlag(PXS_ISR_EOCF)) // Check EOC flag\r
+ {\r
+ if (PXS->RXSR != TSL_Globals.Bank_Array[TSL_Globals.This_Bank].msk_channels) // Check MCE flag\r
+ {\r
+ retval = TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ retval = TSL_STATUS_OK;\r
+ }\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check noise detection\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void)\r
+{\r
+ TSL_AcqStatus_enum_T retval = TSL_ACQ_STATUS_OK;\r
+#if TSLPRM_PXS_RF_DETECTION > 0\r
+ if (checkPXSInterruptStatusFlag(PXS_ISR_NOISEDETF) == PXS_ISR_NOISEDETF)\r
+ {\r
+ retval = TSL_ACQ_STATUS_NOISE;\r
+ }\r
+#endif\r
+ return(retval);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the current measure\r
+ * @param[in] index Index of the measure source\r
+ * @retval Measure\r
+ */\r
+TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndexSrc_T index)\r
+{\r
+ uint16_t CurrentReceiver;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_SOURCE_INDEX_OK(index));\r
+\r
+ CurrentReceiver = (uint16_t)(((uint16_t)1) << index);\r
+\r
+ if (PXS->RXSR & CurrentReceiver)\r
+ {\r
+ return(PXS->RXCNTR[index]);\r
+ }\r
+ else\r
+ {\r
+ return(MAX_MEASURE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Process the PXS Interrupt routine\r
+ * @param None\r
+ * @retval None\r
+ */\r
+INTERRUPT_HANDLER(TSL_acq_ProcessIT, 2)\r
+{\r
+ clearPXS_ISR_EOCF;\r
+\r
+ TSL_acq_BankGetResult(TSL_Globals.This_Bank, 0, 0); // No noise filter\r
+\r
+#if TSLPRM_USE_ZONE > 0\r
+ if ((TSL_Globals.This_Zone == 0) || (TSL_Globals.Index_In_This_Zone >= TSL_Globals.This_Zone->NbBanks))\r
+ {\r
+ CFG->GCR &= (uint8_t)(~CFG_GCR_AL); // Reset Activation level to resume main processing\r
+ PXS->RXENR = 0; // To reduce consumption\r
+ PXS->TXENR = 0; // To reduce consumption\r
+ TSL_Globals.This_Bank = 0;\r
+ }\r
+ else\r
+ {\r
+ if (TSL_acq_ZoneConfig(TSL_Globals.This_Zone, TSL_Globals.Index_In_This_Zone) != TSL_STATUS_ERROR)\r
+ {\r
+ // Start Bank acquisition\r
+ TSL_acq_BankStartAcq();\r
+#if TSLPRM_PXS_LOW_POWER_MODE > 0\r
+ if (TSL_Globals.Index_In_This_Zone >= TSL_Globals.This_Zone->NbBanks)\r
+ {\r
+ setPXSLowPower();\r
+ }\r
+#endif\r
+ }\r
+\r
+ }\r
+#else\r
+ CFG->GCR &= (uint8_t)(~CFG_GCR_AL); // Reset Activation level to resume main processing\r
+ PXS->RXENR = 0; // To reduce consumption\r
+ PXS->TXENR = 0; // To reduce consumption\r
+#endif\r
+}\r
+\r
+\r
+#ifdef __IAR_SYSTEMS_ICC__\r
+#pragma optimize=low\r
+#elif defined (__CC_ARM)\r
+#pragma O1\r
+#pragma Ospace\r
+#endif\r
+/**\r
+ * @brief Software delay (private routine)\r
+ * @param val Wait delay\r
+ * @retval None\r
+ */\r
+void SoftDelay(uint32_t val)\r
+{\r
+ uint32_t i;\r
+ for (i = val; i > 0; i--)\r
+ {}\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_dxs.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the\r
+ * Detection Exclusion System (DxS) algorithm.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_dxs.h"\r
+#include "tsl_globals.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+\r
+#define THIS_OBJ_TYPE TSL_Globals.This_Obj->Type\r
+\r
+#define THIS_TKEY TSL_Globals.This_TKey\r
+#define THIS_TKEY_STATEID TSL_Globals.This_TKey->p_Data->StateId\r
+#define THIS_TKEY_DXSLOCK TSL_Globals.This_TKey->p_Data->DxSLock\r
+#define THIS_TKEY_CHANGE TSL_Globals.This_TKey->p_Data->Change\r
+\r
+#define THIS_LINROT TSL_Globals.This_LinRot\r
+#define THIS_LINROT_STATEID TSL_Globals.This_LinRot->p_Data->StateId\r
+#define THIS_LINROT_DXSLOCK TSL_Globals.This_LinRot->p_Data->DxSLock\r
+#define THIS_LINROT_CHANGE TSL_Globals.This_LinRot->p_Data->Change\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Detection Exclusion System on the first object in detect state\r
+ * @param[in] objgrp Pointer to the objects group to process\r
+ * @retval None\r
+ */\r
+void TSL_dxs_FirstObj(CONST TSL_ObjectGroup_T *objgrp)\r
+{\r
+#if TSLPRM_USE_DXS > 0\r
+\r
+ TSL_tIndex_T idx_obj;\r
+ CONST TSL_Object_T *pobj;\r
+ CONST TSL_Object_T *pobj_candidate = 0; // Candidate object for being in Detect state + DxSLock flag\r
+ TSL_tIndex_T obj_locked = 0; // Object with Lock flag\r
+\r
+ // Exit if no object are in DETECT state.\r
+ if ((objgrp->StateMask & TSL_STATE_DETECT_BIT_MASK) == 0)\r
+ {\r
+ return;\r
+ }\r
+\r
+ pobj = objgrp->p_Obj; // First object in the group\r
+\r
+ // Process all objects\r
+ for (idx_obj = 0; idx_obj < objgrp->NbObjects; idx_obj++)\r
+ {\r
+\r
+ // Assign global object\r
+ TSL_obj_SetGlobalObj(pobj);\r
+\r
+ //--------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_TOUCHKEY) || (THIS_OBJ_TYPE == TSL_OBJ_TOUCHKEYB))\r
+ {\r
+ if (THIS_TKEY_STATEID == TSL_STATEID_DETECT)\r
+ {\r
+ if (THIS_TKEY_DXSLOCK == TSL_TRUE)\r
+ {\r
+ if (!obj_locked)\r
+ {\r
+ obj_locked = 1;\r
+ pobj_candidate = 0;\r
+ }\r
+ else\r
+ {\r
+ THIS_TKEY_STATEID = TSL_STATEID_TOUCH;\r
+ THIS_TKEY_CHANGE = TSL_STATE_CHANGED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ THIS_TKEY_STATEID = TSL_STATEID_TOUCH;\r
+ THIS_TKEY_CHANGE = TSL_STATE_CHANGED;\r
+ if ((!pobj_candidate) && (!obj_locked))\r
+ {\r
+ pobj_candidate = pobj;\r
+ }\r
+ }\r
+ }\r
+ }\r
+#endif // TSLPRM_TOTAL_TKEYS > 0\r
+\r
+ //--------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_LINEAR) || (THIS_OBJ_TYPE == TSL_OBJ_LINEARB) ||\r
+ (THIS_OBJ_TYPE == TSL_OBJ_ROTARY) || (THIS_OBJ_TYPE == TSL_OBJ_ROTARYB))\r
+ {\r
+ if (THIS_LINROT_STATEID == TSL_STATEID_DETECT)\r
+ {\r
+ if (THIS_LINROT_DXSLOCK == TSL_TRUE)\r
+ {\r
+ if (!obj_locked)\r
+ {\r
+ obj_locked = 1;\r
+ pobj_candidate = 0;\r
+ }\r
+ else\r
+ {\r
+ THIS_LINROT_STATEID = TSL_STATEID_TOUCH;\r
+ THIS_LINROT_CHANGE = TSL_STATE_CHANGED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ THIS_LINROT_STATEID = TSL_STATEID_TOUCH;\r
+ THIS_LINROT_CHANGE = TSL_STATE_CHANGED;\r
+ if ((!pobj_candidate) && (!obj_locked))\r
+ {\r
+ pobj_candidate = pobj;\r
+ }\r
+ }\r
+ }\r
+ }\r
+#endif // TSLPRM_TOTAL_LNRTS > 0\r
+\r
+ pobj++; // Next object\r
+\r
+ } // // for all objects\r
+\r
+ // Change state from TOUCH to DETECT + DxSLock flag on the candidate object only\r
+ if (pobj_candidate)\r
+ {\r
+\r
+ // Assign global object\r
+ TSL_obj_SetGlobalObj(pobj_candidate);\r
+\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_TOUCHKEY) || (THIS_OBJ_TYPE == TSL_OBJ_TOUCHKEYB))\r
+ {\r
+ THIS_TKEY_STATEID = TSL_STATEID_DETECT;\r
+ THIS_TKEY_CHANGE = TSL_STATE_CHANGED;\r
+ THIS_TKEY_DXSLOCK = TSL_TRUE;\r
+ }\r
+#endif // TSLPRM_TOTAL_TKEYS > 0\r
+\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_LINEAR) || (THIS_OBJ_TYPE == TSL_OBJ_LINEARB) ||\r
+ (THIS_OBJ_TYPE == TSL_OBJ_ROTARY) || (THIS_OBJ_TYPE == TSL_OBJ_ROTARYB))\r
+ {\r
+ THIS_LINROT_STATEID = TSL_STATEID_DETECT;\r
+ THIS_LINROT_CHANGE = TSL_STATE_CHANGED;\r
+ THIS_LINROT_DXSLOCK = TSL_TRUE;\r
+ }\r
+#endif // TSLPRM_TOTAL_LNRTS > 0\r
+\r
+ }\r
+\r
+#endif // TSLPRM_USE_DXS > 0\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_ecs.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the ECS.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_ecs.h"\r
+#include "tsl_globals.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+\r
+#define THIS_OBJ_TYPE TSL_Globals.This_Obj->Type\r
+#define THIS_TKEY_REF TSL_Globals.This_TKey->p_ChD->Ref\r
+#define THIS_TKEY_REFREST TSL_Globals.This_TKey->p_ChD->RefRest\r
+#define THIS_TKEY_DELTA TSL_Globals.This_TKey->p_ChD->Delta\r
+#define THIS_TKEY_STATEID TSL_Globals.This_TKey->p_Data->StateId\r
+\r
+#define THIS_LINROT_STATEID TSL_Globals.This_LinRot->p_Data->StateId\r
+#define THIS_LINROT_NB_CHANNELS TSL_Globals.This_LinRot->NbChannels\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+#define IS_K_COEFF_OK(COEFF) (((COEFF) == 0) || (((COEFF) > 0) && ((COEFF) < 256)))\r
+#define IS_POINTER_INITIALIZED(POINTER) ((POINTER) != 0)\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Calculate the K coefficient\r
+ * @param[in] objgrp Pointer to the objects group to process\r
+ * @param[in] k_slow K coefficient when objects have different delta variation\r
+ * @param[in] k_fast K coefficient when objects have the same delta variation\r
+ * @retval K coefficient (slow or fast)\r
+ */\r
+TSL_tKCoeff_T TSL_ecs_CalcK(CONST TSL_ObjectGroup_T *objgrp, TSL_tKCoeff_T k_slow, TSL_tKCoeff_T k_fast)\r
+{\r
+ TSL_tIndex_T idx_obj; // Index of current object\r
+ TSL_tIndex_T idx_ch; // Index of current channel\r
+ TSL_tDelta_T ldelta = 0; // Temporary delta\r
+ TSL_tDelta_T ECS_Fast_Enable = 1;\r
+ TSL_tDelta_T ECS_Fast_Direction = 0;\r
+ CONST TSL_Object_T *pobj;\r
+ TSL_tKCoeff_T retval = k_slow;\r
+ TSL_tNb_T nb_channels = 0; // Number of channels inside current object\r
+ TSL_ChannelData_T *p_Ch = 0;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_K_COEFF_OK(k_slow));\r
+ assert_param(IS_K_COEFF_OK(k_fast));\r
+\r
+ pobj = objgrp->p_Obj; // First object in the group\r
+\r
+ // Process all objects\r
+ for (idx_obj = 0; idx_obj < objgrp->NbObjects; idx_obj++)\r
+ {\r
+\r
+ // Assign global object\r
+ TSL_obj_SetGlobalObj(pobj);\r
+\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_TOUCHKEY) || (THIS_OBJ_TYPE == TSL_OBJ_TOUCHKEYB))\r
+ {\r
+ // Ignore object if not in Release state\r
+ if (THIS_TKEY_STATEID != TSL_STATEID_RELEASE)\r
+ {\r
+ continue; // Take next object\r
+ }\r
+ nb_channels = 1;\r
+ p_Ch = TSL_Globals.This_TKey->p_ChD;\r
+ }\r
+#endif\r
+\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_LINEAR) || (THIS_OBJ_TYPE == TSL_OBJ_LINEARB) ||\r
+ (THIS_OBJ_TYPE == TSL_OBJ_ROTARY) || (THIS_OBJ_TYPE == TSL_OBJ_ROTARYB))\r
+ {\r
+ // Ignore object if not in Release state\r
+ if (THIS_LINROT_STATEID != TSL_STATEID_RELEASE)\r
+ {\r
+ continue; // Take next object\r
+ }\r
+ nb_channels = THIS_LINROT_NB_CHANNELS;\r
+ p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ }\r
+#endif\r
+\r
+ // Check channel pointer variable (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_POINTER_INITIALIZED(p_Ch));\r
+\r
+ // Check all channels of current object\r
+ for (idx_ch = 0; idx_ch < nb_channels; idx_ch++)\r
+ {\r
+\r
+ ldelta = p_Ch->Delta;\r
+\r
+ // Check delta\r
+ if (ldelta == 0) // No Fast ECS !\r
+ {\r
+ ECS_Fast_Enable = 0;\r
+ }\r
+ else\r
+ {\r
+ if (ldelta < 0)\r
+ {\r
+ if (ECS_Fast_Direction > 0) // No Fast ECS !\r
+ {\r
+ ECS_Fast_Enable = 0;\r
+ }\r
+ else\r
+ {\r
+ ECS_Fast_Direction = -1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (ECS_Fast_Direction < 0) // No Fast ECS !\r
+ {\r
+ ECS_Fast_Enable = 0;\r
+ }\r
+ else\r
+ {\r
+ ECS_Fast_Direction = 1;\r
+ }\r
+ }\r
+ }\r
+\r
+ p_Ch++; // Next channel\r
+\r
+ } // for all channels of current object\r
+\r
+ pobj++; // Next object\r
+\r
+ } // for all objects\r
+\r
+ // Assign K fast following Delta variations\r
+ if (ECS_Fast_Enable)\r
+ {\r
+ retval = k_fast;\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Calculate the new Reference on a group of objects\r
+ * @param[in] objgrp Pointer to the objects group to process\r
+ * @param[in] Kcoeff K coefficient to apply\r
+ * @retval None\r
+ */\r
+void TSL_ecs_ProcessK(CONST TSL_ObjectGroup_T *objgrp, TSL_tKCoeff_T Kcoeff)\r
+{\r
+ TSL_tIndex_T idx_obj; // Index of current object\r
+ TSL_tIndex_T idx_ch; // Index of current channel\r
+ CONST TSL_Object_T *pobj;\r
+ TSL_tKCoeff_T Kcoeff_comp;\r
+ uint32_t ECS_meas;\r
+ uint32_t ECS_ref;\r
+ TSL_tNb_T nb_channels = 0; // Number of channels inside current object\r
+ TSL_ChannelData_T *p_Ch = 0;\r
+ void(*pFunc_SetStateCalibration)(TSL_tCounter_T delay) = 0;\r
+\r
+ // Check parameters (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_K_COEFF_OK(Kcoeff));\r
+\r
+ pobj = objgrp->p_Obj; // First object in the group\r
+\r
+ // Calculate the K coefficient complement\r
+ Kcoeff_comp = (0xFF ^ Kcoeff) + 1;\r
+\r
+ // Process all objects\r
+ for (idx_obj = 0; idx_obj < objgrp->NbObjects; idx_obj++)\r
+ {\r
+\r
+ // Assign global object\r
+ TSL_obj_SetGlobalObj(pobj);\r
+\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_TOUCHKEY) || (THIS_OBJ_TYPE == TSL_OBJ_TOUCHKEYB))\r
+ {\r
+ // Ignore object if not in Release state\r
+ if (THIS_TKEY_STATEID != TSL_STATEID_RELEASE)\r
+ {\r
+ continue; // Take next object\r
+ }\r
+ nb_channels = 1;\r
+ p_Ch = TSL_Globals.This_TKey->p_ChD;\r
+ pFunc_SetStateCalibration = &TSL_tkey_SetStateCalibration;\r
+ }\r
+#endif\r
+\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_LINEAR) || (THIS_OBJ_TYPE == TSL_OBJ_LINEARB) ||\r
+ (THIS_OBJ_TYPE == TSL_OBJ_ROTARY) || (THIS_OBJ_TYPE == TSL_OBJ_ROTARYB))\r
+ {\r
+ // Ignore object if not in Release state\r
+ if (THIS_LINROT_STATEID != TSL_STATEID_RELEASE)\r
+ {\r
+ continue; // Take next object\r
+ }\r
+ nb_channels = THIS_LINROT_NB_CHANNELS;\r
+ p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ pFunc_SetStateCalibration = &TSL_linrot_SetStateCalibration;\r
+ }\r
+#endif\r
+\r
+ // Check channel pointer variable (if USE_FULL_ASSERT is defined)\r
+ assert_param(IS_POINTER_INITIALIZED(p_Ch));\r
+\r
+ // Calculate the new reference + rest for all channels\r
+ for (idx_ch = 0; idx_ch < nb_channels; idx_ch++)\r
+ {\r
+ ECS_meas = TSL_acq_ComputeMeas(p_Ch->Ref, p_Ch->Delta);\r
+ ECS_meas <<= 8;\r
+\r
+ ECS_ref = (uint32_t)(p_Ch->Ref);\r
+ ECS_ref <<= 8;\r
+ ECS_ref += p_Ch->RefRest;\r
+ ECS_ref *= Kcoeff_comp;\r
+ ECS_ref += (Kcoeff * ECS_meas);\r
+\r
+ p_Ch->RefRest = (TSL_tRefRest_T)((ECS_ref >> 8) & 0xFF);\r
+ p_Ch->Ref = (TSL_tRef_T)(ECS_ref >> 16);\r
+\r
+ // Go in Calibration state in the Reference is out of Range\r
+ if (TSL_acq_TestReferenceOutOfRange(p_Ch) == TSL_TRUE)\r
+ {\r
+ pFunc_SetStateCalibration(0);\r
+ }\r
+\r
+ p_Ch++; // Next channel\r
+ }\r
+\r
+ pobj++; // Next object\r
+\r
+ } // for all objects\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief ECS algorithm on a group of objects\r
+ * The ECS is only performed if at least an object is in Release state and\r
+ * if no objects are in active states (Prox, Detect or Touch)\r
+ * An optional delay is added after the ECS condition (all sensors in Release state) is reached.\r
+ * @param[in] objgrp Pointer to the objects group to process\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_ecs_Process(CONST TSL_ObjectGroup_T *objgrp)\r
+{\r
+ TSL_tKCoeff_T MyKcoeff;\r
+ TSL_Status_enum_T retval;\r
+ static TSL_tIndex_T exec = 0;\r
+#if TSLPRM_ECS_DELAY > 0\r
+ static TSL_tIndex_T wait = 0;\r
+ static TSL_tTick_ms_T start_time;\r
+#endif\r
+\r
+ if ((objgrp->StateMask & TSL_STATE_RELEASE_BIT_MASK) && !(objgrp->StateMask & TSL_STATEMASK_ACTIVE))\r
+ {\r
+#if TSLPRM_ECS_DELAY > 0\r
+ if (!wait)\r
+ {\r
+ disableInterrupts();\r
+ start_time = TSL_Globals.Tick_ms; // Save the current time\r
+ enableInterrupts();\r
+ wait = 1;\r
+ exec = 0;\r
+ }\r
+#else\r
+ exec = 1;\r
+#endif\r
+ }\r
+ else\r
+ {\r
+#if TSLPRM_ECS_DELAY > 0\r
+ wait = 0;\r
+#endif\r
+ exec = 0;\r
+ }\r
+\r
+#if TSLPRM_ECS_DELAY > 0\r
+ if ((wait) && (!exec))\r
+ {\r
+ // Execute the ECS only when the delay has elapsed\r
+ if (TSL_tim_CheckDelay_ms(TSLPRM_ECS_DELAY, &start_time) == TSL_STATUS_OK)\r
+ {\r
+ exec = 1;\r
+ }\r
+ }\r
+#endif\r
+\r
+ if (exec)\r
+ {\r
+ // Calculate the K coefficient\r
+ MyKcoeff = TSL_ecs_CalcK(objgrp, TSLPRM_ECS_K_SLOW, TSLPRM_ECS_K_FAST);\r
+ // Process the objects\r
+ TSL_ecs_ProcessK(objgrp, MyKcoeff);\r
+ retval = TSL_STATUS_OK;\r
+ }\r
+ else\r
+ {\r
+ retval = TSL_STATUS_BUSY;\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_filter.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the signal or delta filters.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_filter.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/* Noise Filter description\r
+ ------------------------\r
+\r
+The noise filter is a first order IRR digital filter based on the following formula:\r
+\r
+S(n) = (1-k).S(n-1)+ k.N(n)\r
+\r
+S(n) : sample number n of the filtered signal\r
+N(n) : sample number n of the raw signal\r
+k : filter coefficient parameter in [0..1]\r
+\r
+The filter sampling rate is the acquisition rate.\r
+\r
+In order to optimize the implementation in the firmware, the above formula is\r
+modified in order to have only one multiply operation:\r
+\r
+S(n) = S(n-1) + k.(N(n) - S(n-1))\r
+\r
+Additionally, we use k = K/256 with K an unsigned 8-bit integer.\r
+\r
+The K is given by the ACQ_FILTER_COEFF constant.\r
+\r
+S(n) = S(n-1) + K.(N(n) - S(n-1))/(2^8)\r
+\r
+and the division can be done easily with bit shifting.\r
+\r
+As we are in the digital world, this formula presents a drawback:\r
+if the difference between S(n-1) and N(n) is less than 1/k, there will be no\r
+difference between S(n-1) and S(n).\r
+\r
+As a consequence, there will be a static error of up to 1/k.\r
+\r
+In the STMTouch Driver, the S(n) is stored in the Meas element of the data\r
+structure after each acquisition:\r
+\r
+Meas(n) = S(n) = N(n)\r
+\r
+The formula is then:\r
+\r
+Meas(n) = Meas(n-1) + K.(Meas(n) - Meas(n-1))/(2^8)\r
+\r
+In order to reduce the static error, we can use "Meas(n) = S(n).2^P".\r
+\r
+The P is given by the ACQ_FILTER_RANGE constant.\r
+\r
+This would shift the signal value left and provides a few additional low\r
+significant bits useful to reduce the static error.\r
+\r
+Warning: all thresholds must be shifted accordingly if the parameter P is\r
+different from 0.\r
+\r
+If we report this into the filter formula we obtain:\r
+\r
+Meas(n) = Meas(n-1) + K.[ Meas(n)*2^P - Meas(n-1)]/2^8\r
+\r
+In this case the static error is reduced to 1/(k.2^P)\r
+*/\r
+\r
+#define ACQ_FILTER_RANGE (0) /* Range[0..5] - Warning: all thresholds must be shifted if different from 0 */\r
+\r
+#define ACQ_FILTER_COEFF (128) /* Range[1..255] - First order filter coefficient (k = ACQ_FILTER_COEFF/256) */\r
+\r
+/**\r
+ * @brief Example of measure value filter\r
+ * @param[in] measn1 Previous measure value\r
+ * @param[in] measn Current measure value\r
+ * @retval Filtered measure\r
+ */\r
+TSL_tMeas_T TSL_filt_MeasFilter(TSL_tMeas_T measn1, TSL_tMeas_T measn)\r
+{\r
+ TSL_tMeas_T val;\r
+\r
+ val = (TSL_tMeas_T)(measn << ACQ_FILTER_RANGE);\r
+\r
+ if (measn1 != 0)\r
+ {\r
+ if (val > measn1)\r
+ {\r
+ val = measn1 + ((ACQ_FILTER_COEFF * (val - measn1)) >> 8);\r
+ }\r
+ else\r
+ {\r
+ val = measn1 - ((ACQ_FILTER_COEFF * (measn1 - val)) >> 8);\r
+ }\r
+ }\r
+\r
+ return(val);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Example of delta value filter\r
+ * @param[in] delta Delta value to modify\r
+ * @retval Filtered delta\r
+ */\r
+TSL_tDelta_T TSL_filt_DeltaFilter(TSL_tDelta_T delta)\r
+{\r
+ return(delta);\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_globals.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains global variables.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_globals.h"\r
+\r
+TSL_Globals_T TSL_Globals; /**< Global variables used by main() and TSL modules */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_linrot.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage Linear and Rotary sensors.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_linrot.h"\r
+#include "tsl_globals.h"\r
+\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+#define THIS_OBJ_TYPE TSL_Globals.This_Obj->Type\r
+\r
+#define THIS_STATEID TSL_Globals.This_LinRot->p_Data->StateId\r
+#define THIS_RAW_POSITION TSL_Globals.This_LinRot->p_Data->RawPosition\r
+#define THIS_POSITION TSL_Globals.This_LinRot->p_Data->Position\r
+#define THIS_CHANGE TSL_Globals.This_LinRot->p_Data->Change\r
+#define THIS_POSCHANGE TSL_Globals.This_LinRot->p_Data->PosChange\r
+#define THIS_COUNTER TSL_Globals.This_LinRot->p_Data->Counter\r
+#define THIS_COUNTER2 TSL_Globals.This_LinRot->p_Data->Counter2\r
+#define THIS_DXSLOCK TSL_Globals.This_LinRot->p_Data->DxSLock\r
+#define THIS_DIRECTION TSL_Globals.This_LinRot->p_Data->Direction\r
+\r
+#define THIS_PROXIN_TH TSL_Globals.This_LinRot->p_Param->ProxInTh\r
+#define THIS_PROXOUT_TH TSL_Globals.This_LinRot->p_Param->ProxOutTh\r
+#define THIS_DETECTIN_TH TSL_Globals.This_LinRot->p_Param->DetectInTh\r
+#define THIS_DETECTOUT_TH TSL_Globals.This_LinRot->p_Param->DetectOutTh\r
+#define THIS_CALIB_TH TSL_Globals.This_LinRot->p_Param->CalibTh\r
+\r
+#define THIS_RESOLUTION TSL_Globals.This_LinRot->p_Param->Resolution\r
+#define THIS_DIR_CHG_POS TSL_Globals.This_LinRot->p_Param->DirChangePos\r
+\r
+#define THIS_COUNTER_DEB_CALIB TSL_Globals.This_LinRot->p_Param->CounterDebCalib\r
+#define THIS_COUNTER_DEB_PROX TSL_Globals.This_LinRot->p_Param->CounterDebProx\r
+#define THIS_COUNTER_DEB_DETECT TSL_Globals.This_LinRot->p_Param->CounterDebDetect\r
+#define THIS_COUNTER_DEB_RELEASE TSL_Globals.This_LinRot->p_Param->CounterDebRelease\r
+#define THIS_COUNTER_DEB_ERROR TSL_Globals.This_LinRot->p_Param->CounterDebError\r
+#define THIS_COUNTER_DEB_DIRECTION TSL_Globals.This_LinRot->p_Param->CounterDebDirection\r
+\r
+#define THIS_NB_CHANNELS TSL_Globals.This_LinRot->NbChannels\r
+#define THIS_SCT_COMP TSL_Globals.This_LinRot->SctComp\r
+#define THIS_POS_CORR TSL_Globals.This_LinRot->PosCorr\r
+\r
+#if TSLPRM_DTO > 0\r
+#define DTO_GET_TIME {TSL_linrot_DTOGetTime();}\r
+#else\r
+#define DTO_GET_TIME\r
+#endif\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+//================================================================\r
+// See AN2869 for more details on Linear and Rotary sensors design\r
+//================================================================\r
+\r
+//==============================================================================\r
+// 3 CHANNELS - LINEAR - MONO - 0/255 at extremities\r
+// i.e. CH1 CH2 CH3\r
+//==============================================================================\r
+#if TSLPRM_USE_3CH_LIN_M1 > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_M1[3][3] =\r
+{\r
+// sec = 1 2 3\r
+// j = 0 1 2\r
+ { 0, -96, 0 }, // maj = 1; i = 0\r
+ { 32, 0, -160 }, // maj = 2; i = 1\r
+ { 0, 96, 0 } // maj = 3; i = 2\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 3 CHANNELS - LINEAR - MONO\r
+// i.e. CH1 CH2 CH3\r
+//==============================================================================\r
+#if TSLPRM_USE_3CH_LIN_M2 > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_M2[3][3] =\r
+{\r
+// sec = 1 2 3\r
+// j = 0 1 2\r
+ { 0, -192, 0 }, // maj = 1; i = 0\r
+ { 64, 0, -320 }, // maj = 2; i = 1\r
+ { 0, 192, 0 } // maj = 3; i = 2\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 3 CHANNELS - LINEAR - HALF-ENDED\r
+// i.e. CH1 CH2 CH3 CH1\r
+//==============================================================================\r
+#if TSLPRM_USE_3CH_LIN_H > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_H[3][3] =\r
+{\r
+// sec = 1 2 3\r
+// j = 0 1 2\r
+ { 0, -96, 160 }, // maj = 1; i = 0\r
+ { 32, 0, -160 }, // maj = 2; i = 1\r
+ { -224, 96, 0 } // maj = 3; i = 2\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 3 CHANNELS - ROTARY - MONO\r
+// i.e. CH1 CH2 CH3\r
+//==============================================================================\r
+#if TSLPRM_USE_3CH_ROT_M > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_3CH_ROT_M[3][3] =\r
+{\r
+// sec = 1 2 3\r
+// j = 0 1 2\r
+ { 0, -64, 107 }, // maj = 1; i = 0\r
+ { 21, 0, -107 }, // maj = 2; i = 1\r
+ { -149, 64, 0 } // maj = 3; i = 2\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 4 CHANNELS - LINEAR - MONO - 0/255 at extremities\r
+// i.e. CH1 CH2 CH3 CH4\r
+//==============================================================================\r
+#if TSLPRM_USE_4CH_LIN_M1 > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_M1[4][4] =\r
+{\r
+// sec = 1 2 3 4\r
+// j = 0 1 2 3\r
+ { 0, -64, 0, 0 }, // maj = 1; i = 0\r
+ { 21, 0, -107, 0 }, // maj = 2; i = 1\r
+ { 0, 64, 0, -149 }, // maj = 3; i = 2\r
+ { 0, 0, 107, 0 } // maj = 4; i = 3\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 4 CHANNELS - LINEAR - MONO\r
+// i.e. CH1 CH2 CH3 CH4\r
+//==============================================================================\r
+#if TSLPRM_USE_4CH_LIN_M2 > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_M2[4][4] =\r
+{\r
+// sec = 1 2 3 4\r
+// j = 0 1 2 3\r
+ { 0, -96, 0, 0 }, // maj = 1; i = 0\r
+ { 32, 0, -160, 0 }, // maj = 2; i = 1\r
+ { 0, 96, 0, -224 }, // maj = 3; i = 2\r
+ { 0, 0, 160, 0 } // maj = 4; i = 3\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 4 CHANNELS - LINEAR - HALF-ENDED\r
+// i.e. CH1 CH2 CH3 CH4 CH1\r
+//==============================================================================\r
+#if TSLPRM_USE_4CH_LIN_H > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_H[4][4] =\r
+{\r
+// sec = 1 2 3 4\r
+// j = 0 1 2 3\r
+ { 0, -64, 0, 149 }, // maj = 1; i = 0\r
+ { 21, 0, -107, 0 }, // maj = 2; i = 1\r
+ { 0, 64, 0, -149 }, // maj = 3; i = 2\r
+ { -192, 0, 107, 0 } // maj = 4; i = 3\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 4 CHANNELS - ROTARY - MONO\r
+// i.e. CH1 CH2 CH3 CH4\r
+//==============================================================================\r
+#if TSLPRM_USE_4CH_ROT_M > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_4CH_ROT_M[4][4] =\r
+{\r
+// sec = 1 2 3 4\r
+// j = 0 1 2 3\r
+ { 0, -48, 0, 112 }, // maj = 1; i = 0\r
+ { 16, 0, -80, 0 }, // maj = 2; i = 1\r
+ { 0, 48, 0, -112 }, // maj = 3; i = 2\r
+ { -144, 0, 80, 0 } // maj = 4; i = 3\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 5 CHANNELS - LINEAR - MONO - 0/255 at extremities\r
+// i.e. CH1 CH2 CH3 CH4 CH5\r
+//==============================================================================\r
+#if TSLPRM_USE_5CH_LIN_M1 > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_M1[5][5] =\r
+{\r
+// sec = 1 2 3 4 5\r
+// j = 0 1 2 3 4\r
+ { 0, -48, 0, 0, 0 }, // maj = 1; i = 0\r
+ { 16, 0, -80, 0, 0 }, // maj = 2; i = 1\r
+ { 0, 48, 0, -112, 0 }, // maj = 3; i = 2\r
+ { 0, 0, 80, 0, -144 }, // maj = 4; i = 3\r
+ { 0, 0, 0, 112, 0 } // maj = 5; i = 4\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 5 CHANNELS - LINEAR - MONO\r
+// i.e. CH1 CH2 CH3 CH4 CH5\r
+//==============================================================================\r
+#if TSLPRM_USE_5CH_LIN_M2 > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_M2[5][5] =\r
+{\r
+// sec = 1 2 3 4 5\r
+// j = 0 1 2 3 4\r
+ { 0, -64, 0, 0, 0 }, // maj = 1; i = 0\r
+ { 21, 0, -107, 0, 0 }, // maj = 2; i = 1\r
+ { 0, 64, 0, -149, 0 }, // maj = 3; i = 2\r
+ { 0, 0, 107, 0, -192 }, // maj = 4; i = 3\r
+ { 0, 0, 0, 149, 0 } // maj = 5; i = 4\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 5 CHANNELS - LINEAR - HALF-ENDED\r
+// i.e. CH1 CH2 CH3 CH4 CH5 CH1\r
+//==============================================================================\r
+#if TSLPRM_USE_5CH_LIN_H > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_H[5][5] =\r
+{\r
+// sec = 1 2 3 4 5\r
+// j = 0 1 2 3 4\r
+ { 0, -48, 0, 0, 144 }, // maj = 1; i = 0\r
+ { 16, 0, -80, 0, 0 }, // maj = 2; i = 1\r
+ { 0, 48, 0, -112, 0 }, // maj = 3; i = 2\r
+ { 0, 0, 80, 0, -144 }, // maj = 4; i = 3\r
+ { -176, 0, 0, 112, 0 } // maj = 5; i = 4\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 5 CHANNELS - ROTARY - MONO\r
+// i.e. CH1 CH2 CH3 CH4 CH5\r
+//==============================================================================\r
+#if TSLPRM_USE_5CH_ROT_M > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_5CH_ROT_M[5][5] =\r
+{\r
+// sec = 1 2 3 4 5\r
+// j = 0 1 2 3 4\r
+ { 0, -38, 0, 0, 115 }, // maj = 1; i = 0\r
+ { 13, 0, -64, 0, 0 }, // maj = 2; i = 1\r
+ { 0, 38, 0, -90, 0 }, // maj = 3; i = 2\r
+ { 0, 0, 64, 0, -115 }, // maj = 4; i = 3\r
+ {-141, 0, 0, 90, 0 } // maj = 5; i = 4\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 5 CHANNELS - ROTARY - DUAL\r
+// i.e. CH1 CH2 CH3 CH4 CH5 CH1 CH3 CH5 CH2 CH4\r
+//==============================================================================\r
+#if TSLPRM_USE_5CH_ROT_D > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_5CH_ROT_D[5][5] =\r
+{\r
+// sec = 1 2 3 4 5\r
+// j = 0 1 2 3 4\r
+ { 0, -19, -83, 122, 58 }, // maj = 1; i = 0\r
+ { 6, 0, -32, -122, 96 }, // maj = 2; i = 1\r
+ { 70, 19, 0, -45, -96 }, // maj = 3; i = 2\r
+ {-134, 109, 32, 0, -58 }, // maj = 4; i = 3\r
+ { -70, -109, 83, 45, 0 } // maj = 5; i = 4\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 6 CHANNELS - LINEAR - MONO - 0/255 at extremities\r
+// i.e. CH1 CH2 CH3 CH4 CH5 CH6\r
+//==============================================================================\r
+#if TSLPRM_USE_6CH_LIN_M1 > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_M1[6][6] =\r
+{\r
+// sec = 1 2 3 4 5 6\r
+// j = 0 1 2 3 4 5\r
+ { 0, -38, 0, 0, 0, 0 }, // maj = 1; i = 0\r
+ { 13, 0, -64, 0, 0, 0 }, // maj = 2; i = 1\r
+ { 0, 38, 0, -90, 0, 0 }, // maj = 3; i = 2\r
+ { 0, 0, 64, 0, -115, 0 }, // maj = 4; i = 3\r
+ { 0, 0, 0, 90, 0, -141 }, // maj = 5; i = 4\r
+ { 0, 0, 0, 0, 115, 0 } // maj = 6; i = 5\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 6 CHANNELS - LINEAR - MONO\r
+// i.e. CH1 CH2 CH3 CH4 CH5 CH6\r
+//==============================================================================\r
+#if TSLPRM_USE_6CH_LIN_M2 > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_M2[6][6] =\r
+{\r
+// sec = 1 2 3 4 5 6\r
+// j = 0 1 2 3 4 5\r
+ { 0, -48, 0, 0, 0, 0 }, // maj = 1; i = 0\r
+ { 16, 0, -80, 0, 0, 0 }, // maj = 2; i = 1\r
+ { 0, 48, 0, -112, 0, 0 }, // maj = 3; i = 2\r
+ { 0, 0, 80, 0, -144, 0 }, // maj = 4; i = 3\r
+ { 0, 0, 0, 112, 0, -176 }, // maj = 5; i = 4\r
+ { 0, 0, 0, 0, 144, 0 } // maj = 6; i = 5\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 6 CHANNELS - LINEAR - HALF-ENDED\r
+// i.e. CH1 CH2 CH3 CH4 CH5 CH6 CH1\r
+//==============================================================================\r
+#if TSLPRM_USE_6CH_LIN_H > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_H[6][6] =\r
+{\r
+// sec = 1 2 3 4 5 6\r
+// j = 0 1 2 3 4 5\r
+ { 0, -38, 0, 0, 0, 141 }, // maj = 1; i = 0\r
+ { 13, 0, -64, 0, 0, 0 }, // maj = 2; i = 1\r
+ { 0, 38, 0, -90, 0, 0 }, // maj = 3; i = 2\r
+ { 0, 0, 64, 0, -115, 0 }, // maj = 4; i = 3\r
+ { 0, 0, 0, 90, 0, -141 }, // maj = 5; i = 4\r
+ {-166, 0, 0, 0, 115, 0 } // maj = 6; i = 5\r
+};\r
+#endif\r
+\r
+//==============================================================================\r
+// 6 CHANNELS - ROTARY - MONO\r
+// i.e. CH1 CH2 CH3 CH4 CH5 CH6\r
+//==============================================================================\r
+#if TSLPRM_USE_6CH_ROT_M > 0\r
+CONST TSL_tsignPosition_T TSL_POSOFF_6CH_ROT_M[6][6] =\r
+{\r
+// sec = 1 2 3 4 5 6\r
+// j = 0 1 2 3 4 5\r
+ { 0, -32, 0, 0, 0, 117 }, // maj = 1; i = 0\r
+ { 11, 0, -53, 0, 0, 0 }, // maj = 2; i = 1\r
+ { 0, 32, 0, -75, 0, 0 }, // maj = 3; i = 2\r
+ { 0, 0, 53, 0, -96, 0 }, // maj = 4; i = 3\r
+ { 0, 0, 0, 75, 0, -117 }, // maj = 5; i = 4\r
+ {-139, 0, 0, 0, 96, 0 } // maj = 6; i = 5\r
+};\r
+#endif\r
+\r
+//------------------\r
+// Common parameters\r
+//------------------\r
+\r
+#define DIRECTION_CHANGE_MAX_DISPLACEMENT (255)\r
+#define DIRECTION_CHANGE_TOTAL_STEPS (256)\r
+#define RESOLUTION_CALCULATION (8)\r
+\r
+static TSL_tNb_T CalibDiv;\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+void TSL_linrot_DTOGetTime(void);\r
+void TSL_linrot_ProcessCh_All_SetStatus(TSL_ObjStatus_enum_T sts);\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_DataReady(void);\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_All_AcqStatus(TSL_AcqStatus_enum_T sts);\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_AcqStatusError(void);\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_DeltaBelowEquMinus(TSL_tThreshold_T th);\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_DeltaAboveEqu(TSL_tThreshold_T th, TSL_tIndex_T coeff);\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_DeltaAbove(TSL_tThreshold_T th, TSL_tIndex_T coeff);\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_All_DeltaBelowEqu(TSL_tThreshold_T th, TSL_tIndex_T coeff);\r
+void TSL_linrot_ProcessCh_All_ClearRef(void);\r
+TSL_tDelta_T TSL_linrot_NormDelta(TSL_ChannelData_T *ch, TSL_tIndex_T idx);\r
+\r
+\r
+//==============================================================================\r
+// "Object methods" functions\r
+//==============================================================================\r
+\r
+/**\r
+ * @brief Init parameters with default values from configuration file\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_Init(void)\r
+{\r
+ // Thresholds\r
+#if TSLPRM_USE_PROX > 0\r
+ THIS_PROXIN_TH = TSLPRM_LINROT_PROX_IN_TH;\r
+ THIS_PROXOUT_TH = TSLPRM_LINROT_PROX_OUT_TH;\r
+#endif\r
+ THIS_DETECTIN_TH = TSLPRM_LINROT_DETECT_IN_TH;\r
+ THIS_DETECTOUT_TH = TSLPRM_LINROT_DETECT_OUT_TH;\r
+ THIS_CALIB_TH = TSLPRM_LINROT_CALIB_TH;\r
+\r
+ // Debounce counters\r
+ THIS_COUNTER_DEB_CALIB = TSLPRM_DEBOUNCE_CALIB;\r
+#if TSLPRM_USE_PROX > 0\r
+ THIS_COUNTER_DEB_PROX = TSLPRM_DEBOUNCE_PROX;\r
+#endif\r
+ THIS_COUNTER_DEB_DETECT = TSLPRM_DEBOUNCE_DETECT;\r
+ THIS_COUNTER_DEB_RELEASE = TSLPRM_DEBOUNCE_RELEASE;\r
+ THIS_COUNTER_DEB_ERROR = TSLPRM_DEBOUNCE_ERROR;\r
+\r
+ // Other parameters for linear/rotary only\r
+ THIS_RESOLUTION = TSLPRM_LINROT_RESOLUTION;\r
+ THIS_DIR_CHG_POS = TSLPRM_LINROT_DIR_CHG_POS;\r
+ THIS_COUNTER_DEB_DIRECTION = TSLPRM_LINROT_DIR_CHG_DEB;\r
+\r
+ // Initial state\r
+ TSL_linrot_SetStateCalibration(TSLPRM_CALIB_DELAY);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Process the State Machine\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_Process(void)\r
+{\r
+ TSL_StateId_enum_T prev_state_id;\r
+\r
+ // Check if at least one channel has a data ready\r
+ if ((TSL_linrot_ProcessCh_One_DataReady() == TSL_STATUS_OK) || (THIS_STATEID == TSL_STATEID_OFF))\r
+ {\r
+\r
+ prev_state_id = THIS_STATEID;\r
+\r
+#if TSLPRM_TOTAL_LINROTS > 0\r
+ if ((TSL_Globals.This_Obj->Type == TSL_OBJ_LINEAR) ||\r
+ (TSL_Globals.This_Obj->Type == TSL_OBJ_ROTARY))\r
+ {\r
+ // Launch the object state function\r
+ TSL_Globals.This_LinRot->p_SM[THIS_STATEID].StateFunc();\r
+ }\r
+#endif\r
+\r
+#if TSLPRM_TOTAL_LINROTS_B > 0\r
+ if ((TSL_Globals.This_Obj->Type == TSL_OBJ_LINEARB) ||\r
+ (TSL_Globals.This_Obj->Type == TSL_OBJ_ROTARYB))\r
+ {\r
+ // Launch the TSL_Params state function\r
+ TSL_Params.p_LinRotSM[THIS_STATEID].StateFunc();\r
+ }\r
+#endif\r
+\r
+ // Check if the new state has changed\r
+ if (THIS_STATEID == prev_state_id)\r
+ {\r
+ THIS_CHANGE = TSL_STATE_NOT_CHANGED;\r
+ }\r
+ else\r
+ {\r
+ THIS_CHANGE = TSL_STATE_CHANGED;\r
+ }\r
+\r
+#if TSLPRM_USE_DXS > 0\r
+ if (THIS_STATEID != TSL_STATEID_DETECT)\r
+ {\r
+ THIS_DXSLOCK = TSL_FALSE;\r
+ }\r
+ if (THIS_STATEID == TSL_STATEID_TOUCH)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ }\r
+#endif\r
+\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Calculate the position\r
+ * @param None\r
+ * @retval Status Return OK if position calculation is correct\r
+ * @note The position is calculated only if the number of channels is greater than 2\r
+ */\r
+TSL_Status_enum_T TSL_linrot_CalcPos(void)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ TSL_tDelta_T norm_delta;\r
+ static TSL_tDelta_T delta1, delta2, delta3;\r
+ static TSL_tIndex_T index1, index2;\r
+ TSL_tNb_T minor, major;\r
+ TSL_tNb_T sector_computation = 0;\r
+ TSL_tsignPosition_T new_position = 0;\r
+ TSL_tPosition_T u_new_position = 0;\r
+ TSL_tPosition_T position_correction = 0;\r
+\r
+ delta1 = 0;\r
+ delta2 = 0;\r
+ delta3 = 0;\r
+\r
+ index1 = 0;\r
+ index2 = 0;\r
+\r
+ // The position change flag will be set only if a new position is detected.\r
+ THIS_POSCHANGE = TSL_STATE_NOT_CHANGED;\r
+\r
+ // The position is calculated only if the number of channels is greater than 2\r
+ if (THIS_NB_CHANNELS < 3)\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+\r
+ //--------------------------------------------------------------------------\r
+ // Sort the channels' delta\r
+ // - delta1 and index1 = biggest\r
+ // - delta2 and index2 = middle\r
+ // - delta3 and index3 = lowest\r
+ //--------------------------------------------------------------------------\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+\r
+#if TSLPRM_LINROT_USE_NORMDELTA > 0\r
+ norm_delta = TSL_linrot_NormDelta(p_Ch, idx); // Normalize the Delta\r
+#else\r
+ norm_delta = p_Ch->Delta; // Take only the Delta\r
+#endif\r
+\r
+ // The Delta must be positive only otherwise it is noise\r
+ if (norm_delta < 0) {norm_delta = 0;}\r
+\r
+ if (norm_delta > delta1)\r
+ {\r
+ delta3 = delta2;\r
+ delta2 = delta1;\r
+ delta1 = norm_delta;\r
+ index2 = index1;\r
+ index1 = idx;\r
+ }\r
+ else\r
+ {\r
+ if (norm_delta > delta2)\r
+ {\r
+ delta3 = delta2;\r
+ delta2 = norm_delta;\r
+ index2 = idx;\r
+ }\r
+ else\r
+ {\r
+ if (norm_delta > delta3)\r
+ {\r
+ delta3 = norm_delta;\r
+ }\r
+ }\r
+ }\r
+\r
+ p_Ch++; // Next channel\r
+\r
+ } // for all channels\r
+\r
+ // Noise filter: we need at least two significant Delta measurements\r
+ if (delta2 < ((TSL_tThreshold_T)(THIS_DETECTOUT_TH >> 1) - 1))\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+\r
+ //----------------------------------------------------------------------------\r
+ // Position calculation...\r
+ //----------------------------------------------------------------------------\r
+\r
+ /*----------------------------------------------------------------------------\r
+ B = Biggest signal measured (Delta1/Index1)\r
+ M = Middle signal measured (Delta2/Index2)\r
+ S = Smallest signal measured (Delta3/Index3)\r
+ \r
+ - The equation to find the position is:\r
+ Position = Offset +/- [ Sector_Size x ( Major / (Major + Minor) ) ]\r
+ \r
+ - The Offset is the position of the middle of the Middle signal segment.\r
+ All the Offset values are stored in the ROM table Table_POSITION_OFFSET.\r
+ \r
+ - Major = Biggest - Smallest signals\r
+ Minor = Middle - Smallest signals\r
+ \r
+ - The Sector_Size depends of the number of channels used\r
+ ----------------------------------------------------------------------------*/\r
+\r
+ // Calculates the Major and Minor parameters\r
+ minor = (TSL_tNb_T)(delta2 - delta3); // Middle - Smallest signals\r
+ major = (TSL_tNb_T)(delta1 - delta3); // Biggest - Smallest signals\r
+\r
+ // Select the offset position in the position offset constant table\r
+ // Equal to: new_position = TABLE_POSITION_OFFSET_xCH_xxx[index1][index2];\r
+ new_position = *(TSL_Globals.This_LinRot->p_PosOff + (index1 * THIS_NB_CHANNELS) + index2);\r
+ sector_computation = THIS_SCT_COMP;\r
+ position_correction = THIS_POS_CORR;\r
+\r
+ // Calculates: [ Sector_Size x ( Major / (Major + Minor) ) ]\r
+ sector_computation = major * sector_computation;\r
+ sector_computation = sector_computation / (major + minor);\r
+\r
+ // Use the sign bit from position table to define the interpretation direction.\r
+ // The NewPosition is multiplied by 2 because the Offset stored in the ROM\r
+ // table is divided by 2...\r
+ if (new_position > 0) // Means Offset is > 0 in the position table\r
+ {\r
+ new_position = (TSL_tsignPosition_T)(new_position << 1);\r
+ new_position += sector_computation;\r
+ }\r
+ else // means Offset is <= 0 in the ROM table\r
+ {\r
+ new_position = (TSL_tsignPosition_T)((-new_position) << 1);\r
+ new_position -= sector_computation;\r
+ }\r
+\r
+ // Position is calculated differently if LINEAR or ROTARY sensor\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_LINEAR) || (THIS_OBJ_TYPE == TSL_OBJ_LINEARB))\r
+ {\r
+\r
+ // First adjustment used to shift all the values to obtain the "zero"\r
+ if (new_position > 0)\r
+ {\r
+ new_position -= position_correction;\r
+ }\r
+ else\r
+ {\r
+ new_position = new_position + (256 - position_correction);\r
+ }\r
+\r
+ // Second adjustment used to clamp the values at both ends of sensor\r
+ if (new_position < 0)\r
+ {\r
+ new_position = 0;\r
+ }\r
+\r
+ if (new_position > 255)\r
+ {\r
+ new_position = 255;\r
+ }\r
+\r
+ }\r
+ else // ROTARY sensor: keep only the low byte\r
+ {\r
+ new_position = (TSL_tPosition_T)new_position;\r
+ }\r
+\r
+ //----------------------------------------------------------------------------\r
+ // Direction Change Process\r
+ //----------------------------------------------------------------------------\r
+\r
+ if (THIS_DIRECTION == TSL_TRUE) // Anticlockwise direction ...\r
+ {\r
+\r
+ // Check Direction changed and Position overflow from 0x00 to 0xFF not realized !\r
+ if (((TSL_tPosition_T)new_position > THIS_RAW_POSITION) && (((TSL_tPosition_T)new_position - THIS_RAW_POSITION) < DIRECTION_CHANGE_MAX_DISPLACEMENT))\r
+ {\r
+ if (new_position < (uint16_t)(THIS_RAW_POSITION + THIS_DIR_CHG_POS))\r
+ {\r
+ THIS_COUNTER2 = THIS_COUNTER_DEB_DIRECTION;\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_COUNTER2--;\r
+ if (!THIS_COUNTER2)\r
+ {\r
+ THIS_COUNTER2 = THIS_COUNTER_DEB_DIRECTION;\r
+ THIS_DIRECTION = TSL_FALSE; // New direction accepted: clockwise.\r
+ }\r
+ else\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ // Check position overflow from 0xFF to 0x00 to be filtered !\r
+ if ((new_position + DIRECTION_CHANGE_MAX_DISPLACEMENT) < THIS_RAW_POSITION)\r
+ {\r
+ if ((new_position + DIRECTION_CHANGE_TOTAL_STEPS) < (uint16_t)(THIS_RAW_POSITION + THIS_DIR_CHG_POS))\r
+ {\r
+ THIS_COUNTER2 = THIS_COUNTER_DEB_DIRECTION;\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_COUNTER2--;\r
+ if (!THIS_COUNTER2)\r
+ {\r
+ THIS_COUNTER2 = THIS_COUNTER_DEB_DIRECTION;\r
+ THIS_DIRECTION = TSL_FALSE; // New direction accepted: clockwise.\r
+ }\r
+ else\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ }\r
+ else // Clockwise direction... DEFAULT SETTING !\r
+ {\r
+\r
+ // Check Direction changed and Position overflow from 0xFF to 0x00 not realized !\r
+ if (((TSL_tPosition_T)new_position < THIS_RAW_POSITION) && ((THIS_RAW_POSITION - (TSL_tPosition_T)new_position) < DIRECTION_CHANGE_MAX_DISPLACEMENT))\r
+ {\r
+ if ((new_position + THIS_DIR_CHG_POS) > THIS_RAW_POSITION)\r
+ {\r
+ THIS_COUNTER2 = THIS_COUNTER_DEB_DIRECTION;\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_COUNTER2--;\r
+ if (!THIS_COUNTER2)\r
+ {\r
+ THIS_COUNTER2 = THIS_COUNTER_DEB_DIRECTION;\r
+ THIS_DIRECTION = TSL_TRUE; // New direction accepted: anticlockwise.\r
+ }\r
+ else\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ // Check position overflow from 0x00 to 0xFF to be filtered !\r
+ if (new_position > (uint16_t)(THIS_RAW_POSITION + DIRECTION_CHANGE_MAX_DISPLACEMENT))\r
+ {\r
+ if ((new_position + THIS_DIR_CHG_POS) > (uint16_t)(THIS_RAW_POSITION + DIRECTION_CHANGE_TOTAL_STEPS))\r
+ {\r
+ THIS_COUNTER2 = THIS_COUNTER_DEB_DIRECTION;\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_COUNTER2--;\r
+ if (!THIS_COUNTER2)\r
+ {\r
+ THIS_COUNTER2 = THIS_COUNTER_DEB_DIRECTION;\r
+ THIS_DIRECTION = TSL_TRUE; // New direction accepted: anticlockwise.\r
+ }\r
+ else\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ //----------------------------------------------------------------------------\r
+ // Final result...\r
+ //----------------------------------------------------------------------------\r
+\r
+ // The Raw Position is always updated\r
+ // The Position is updated only if different from the previous one\r
+\r
+ THIS_RAW_POSITION = (TSL_tPosition_T)new_position;\r
+\r
+ u_new_position = (TSL_tPosition_T)((TSL_tPosition_T)new_position >> (RESOLUTION_CALCULATION - THIS_RESOLUTION));\r
+\r
+ if (THIS_POSITION == u_new_position)\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_POSITION = u_new_position;\r
+ THIS_POSCHANGE = TSL_STATE_CHANGED;\r
+ return TSL_STATUS_OK;\r
+ }\r
+\r
+}\r
+\r
+\r
+//==============================================================================\r
+// Utility functions\r
+//==============================================================================\r
+\r
+/**\r
+ * @brief Go in Calibration state\r
+ * @param[in] delay Delay before calibration starts (stabilization of noise filter)\r
+ * @retval None\r
+ */\r
+void TSL_linrot_SetStateCalibration(TSL_tCounter_T delay)\r
+{\r
+ THIS_STATEID = TSL_STATEID_CALIB;\r
+ THIS_CHANGE = TSL_STATE_CHANGED;\r
+ TSL_linrot_ProcessCh_All_SetStatus(TSL_OBJ_STATUS_ON);\r
+\r
+ switch (TSL_Params.NbCalibSamples)\r
+ {\r
+ case 4:\r
+ CalibDiv = 2;\r
+ break;\r
+ case 16:\r
+ CalibDiv = 4;\r
+ break;\r
+ default:\r
+ TSL_Params.NbCalibSamples = 8;\r
+ CalibDiv = 3;\r
+ break;\r
+ }\r
+\r
+ // If a noise filter is used, the counter must be initialized to a value\r
+ // different from 0 in order to stabilize the filter.\r
+ THIS_COUNTER = (TSL_tCounter_T)(delay + (TSL_tCounter_T)TSL_Params.NbCalibSamples);\r
+ TSL_linrot_ProcessCh_All_ClearRef();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Go in Off state with sensor "off"\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_SetStateOff(void)\r
+{\r
+ THIS_STATEID = TSL_STATEID_OFF;\r
+ THIS_CHANGE = TSL_STATE_CHANGED;\r
+ TSL_linrot_ProcessCh_All_SetStatus(TSL_OBJ_STATUS_OFF);\r
+}\r
+\r
+\r
+#if !defined(TSLPRM_STM8TL5X) && !defined(STM8TL5X)\r
+/**\r
+ * @brief Go in Off state with sensor in "Burst mode only"\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_SetStateBurstOnly(void)\r
+{\r
+ THIS_STATEID = TSL_STATEID_OFF;\r
+ THIS_CHANGE = TSL_STATE_CHANGED;\r
+ TSL_linrot_ProcessCh_All_SetStatus(TSL_OBJ_STATUS_BURST_ONLY);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Return the current state identifier\r
+ * @param None\r
+ * @retval State id\r
+ */\r
+TSL_StateId_enum_T TSL_linrot_GetStateId(void)\r
+{\r
+ return(THIS_STATEID);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the current state mask\r
+ * @param None\r
+ * @retval State mask\r
+ */\r
+TSL_StateMask_enum_T TSL_linrot_GetStateMask(void)\r
+{\r
+ TSL_StateMask_enum_T state_mask = TSL_STATEMASK_UNKNOWN;\r
+\r
+#if TSLPRM_TOTAL_LINROTS > 0\r
+ if ((TSL_Globals.This_Obj->Type == TSL_OBJ_LINEAR) ||\r
+ (TSL_Globals.This_Obj->Type == TSL_OBJ_ROTARY))\r
+ {\r
+ state_mask = TSL_Globals.This_LinRot->p_SM[THIS_STATEID].StateMask;\r
+ }\r
+#endif\r
+\r
+#if TSLPRM_TOTAL_LINROTS_B > 0\r
+ if ((TSL_Globals.This_Obj->Type == TSL_OBJ_LINEARB) ||\r
+ (TSL_Globals.This_Obj->Type == TSL_OBJ_ROTARYB))\r
+ {\r
+ state_mask = TSL_Params.p_LinRotSM[THIS_STATEID].StateMask;\r
+ }\r
+#endif\r
+\r
+ return state_mask;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the Change flag\r
+ * @param None\r
+ * @retval Change flag status\r
+ */\r
+TSL_tNb_T TSL_linrot_IsChanged(void)\r
+{\r
+ return(THIS_CHANGE);\r
+}\r
+\r
+\r
+//==============================================================================\r
+// State machine functions\r
+//==============================================================================\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Debounce Release processing (previous state = Proximity)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebReleaseProxStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX; // Go back to the previous state\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_PROXOUT_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX; // Go back to the previous state\r
+ }\r
+ else\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ // else stay in Debounce Release\r
+ }\r
+ }\r
+}\r
+#endif // if TSLPRM_USE_PROX > 0\r
+\r
+\r
+/**\r
+ * @brief Debounce Release processing (previous state = Detect)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebReleaseDetectStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT; // Go back to the previous state\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_DETECTOUT_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ }\r
+ else\r
+ {\r
+#if TSLPRM_USE_PROX > 0\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_PROXOUT_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ return;\r
+ }\r
+#endif\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ // else stay in Debounce Release\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Debounce Release processing (previous state = Touch)\r
+ * Same as Debounce Release Detect processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebReleaseTouchStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_TOUCH; // Go back to the previous state\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_DETECTOUT_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_TOUCH;\r
+ }\r
+ else\r
+ {\r
+#if TSLPRM_USE_PROX > 0\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_PROXOUT_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ return;\r
+ }\r
+#endif\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ // else stay in Debounce Release\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Release state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_ReleaseStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_RELEASE;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAboveEqu(THIS_DETECTIN_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_DETECT;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_DETECT;\r
+ }\r
+ return;\r
+ }\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+ if (TSL_linrot_ProcessCh_One_DeltaAboveEqu(THIS_PROXIN_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_PROX;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_PROX;\r
+ }\r
+ return;\r
+ }\r
+#endif\r
+\r
+ // Check delta for re-calibration\r
+ if (TSL_linrot_ProcessCh_One_DeltaBelowEquMinus(THIS_CALIB_TH) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_CALIB;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ TSL_linrot_SetStateCalibration(0);\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_CALIB;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Debounce Calibration processing (previous state = Release)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebCalibrationStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE; // Go back to the previous state\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaBelowEquMinus(THIS_CALIB_TH) == TSL_STATUS_OK) // Still below recalibration threshold\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ TSL_linrot_SetStateCalibration(0);\r
+ }\r
+ // else stay in Debounce Calibration\r
+ }\r
+ else // Go back to previous state\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Calibration state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_CalibrationStateProcess(void)\r
+{\r
+ TSL_tMeas_T new_meas;\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch;\r
+\r
+#if TSLPRM_CALIB_DELAY > 0\r
+ // Noise filter stabilization time\r
+ if (THIS_COUNTER > (TSL_tCounter_T)TSL_Params.NbCalibSamples)\r
+ {\r
+ THIS_COUNTER--;\r
+ return; // Skip the sample\r
+ }\r
+#endif\r
+\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_CALIB;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ // Process all channels\r
+ p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+\r
+ // Get the new measure or Calculate it\r
+#if TSLPRM_USE_MEAS > 0\r
+ new_meas = p_Ch->Meas;\r
+#else // Calculate it\r
+ new_meas = TSL_acq_ComputeMeas(p_Ch->Ref, p_Ch->Delta);\r
+#endif\r
+\r
+ // Verify the first Reference value\r
+ if (THIS_COUNTER == (TSL_tCounter_T)TSL_Params.NbCalibSamples)\r
+ {\r
+ if (TSL_acq_TestFirstReferenceIsValid(p_Ch, new_meas))\r
+ {\r
+ p_Ch->Ref = new_meas;\r
+ }\r
+ else\r
+ {\r
+ p_Ch->Ref = 0;\r
+ return;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ // Add the measure in temporary Reference\r
+ p_Ch->Ref += new_meas;\r
+\r
+ // Check reference overflow\r
+ if (p_Ch->Ref < new_meas)\r
+ {\r
+ p_Ch->Ref = 0; // Suppress the bad reference\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ return;\r
+ }\r
+ }\r
+\r
+ p_Ch++; // Next channel\r
+ }\r
+\r
+ // Check that we have all the needed measurements\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ // Process all channels\r
+ p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+ // Divide temporary Reference by the number of samples\r
+ p_Ch->Ref >>= CalibDiv;\r
+ p_Ch->RefRest = 0;\r
+ p_Ch->Delta = 0;\r
+ p_Ch++; // Next channel\r
+ }\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Debounce Proximity processing (previous state = Release)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebProxStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAboveEqu(THIS_DETECTIN_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_DETECT;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_DETECT;\r
+ }\r
+ return;\r
+ }\r
+\r
+ if (TSL_linrot_ProcessCh_One_DeltaAboveEqu(THIS_PROXIN_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ // else stay in Debounce Proximity\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Debounce Proximity processing (previous state = Detect)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebProxDetectStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_DETECTOUT_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ return;\r
+ }\r
+\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_PROXOUT_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ // else stay in Debounce Proximity\r
+ }\r
+ else\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_DETECT;\r
+ }\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Debounce Proximity processing (previous state = Touch)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebProxTouchStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_TOUCH;\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_DETECTOUT_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_TOUCH;\r
+ return;\r
+ }\r
+\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_PROXOUT_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ // else stay in Debounce Proximity\r
+ }\r
+ else\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_TOUCH;\r
+ }\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Proximity state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_ProxStateProcess(void)\r
+{\r
+#if TSLPRM_DTO > 0\r
+ TSL_tTick_sec_T tick_detected;\r
+#endif\r
+\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_PROX;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAboveEqu(THIS_DETECTIN_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_DETECT;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_DETECT;\r
+ }\r
+ return;\r
+ }\r
+\r
+ if (TSL_linrot_ProcessCh_All_DeltaBelowEqu(THIS_PROXOUT_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_PROX;\r
+ }\r
+ return;\r
+ }\r
+\r
+ // Stay in Proximity state\r
+#if TSLPRM_DTO > 0\r
+ //------------------------------------\r
+ // Detection Time Out (DTO) processing\r
+ //------------------------------------\r
+ if ((TSL_Params.DTO > 1) && (TSL_Params.DTO < 64))\r
+ {\r
+ tick_detected = THIS_COUNTER; // Get the detected time previously saved\r
+ // Enter in calibration state if the DTO duration has elapsed\r
+ if (TSL_tim_CheckDelay_sec(TSL_Params.DTO, &tick_detected) == TSL_STATUS_OK)\r
+ {\r
+ TSL_linrot_SetStateCalibration(0);\r
+ }\r
+ }\r
+#endif\r
+\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Debounce Detect processing (previous state = Release or Proximity)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebDetectStateProcess(void)\r
+{\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (TSL_linrot_ProcessCh_One_DeltaAboveEqu(THIS_DETECTIN_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ // else stay in Debounce Detect\r
+ }\r
+ else\r
+ {\r
+#if TSLPRM_USE_PROX > 0\r
+ if (TSL_linrot_ProcessCh_One_DeltaAboveEqu(THIS_PROXIN_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_PROX;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_PROX;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+#else\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+#endif\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Detect state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DetectStateProcess(void)\r
+{\r
+#if TSLPRM_DTO > 0\r
+ TSL_Status_enum_T pos_sts;\r
+ TSL_tTick_sec_T tick_detected;\r
+#endif\r
+\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_DETECT;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_DETECTOUT_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ //-------------------\r
+ // Calculate position\r
+ //-------------------\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_LINEAR) || (THIS_OBJ_TYPE == TSL_OBJ_ROTARY))\r
+ {\r
+ // Call the specific method\r
+#if TSLPRM_DTO > 0\r
+ pos_sts = TSL_Globals.This_LinRot->p_Methods->CalcPosition();\r
+#else\r
+ TSL_Globals.This_LinRot->p_Methods->CalcPosition();\r
+#endif\r
+ }\r
+ else // TSL_OBJ_LINEARB or TSL_OBJ_ROTARYB\r
+ {\r
+ // Call the default method\r
+#if TSLPRM_DTO > 0\r
+ pos_sts = TSL_Params.p_LinRotMT->CalcPosition();\r
+#else\r
+ TSL_Params.p_LinRotMT->CalcPosition();\r
+#endif\r
+ }\r
+#if TSLPRM_DTO > 0\r
+ //------------------------------------\r
+ // Detection Time Out (DTO) processing\r
+ // Only if the Position has NOT changed\r
+ //-------------------------------------\r
+ if (pos_sts == TSL_STATUS_OK)\r
+ {\r
+ DTO_GET_TIME; // Take current time\r
+ }\r
+ else\r
+ {\r
+ if ((TSL_Params.DTO > 1) && (TSL_Params.DTO < 64))\r
+ {\r
+ tick_detected = THIS_COUNTER; // Get the detected time previously saved\r
+ // Enter in calibration state if the DTO duration has elapsed\r
+ if (TSL_tim_CheckDelay_sec(TSL_Params.DTO, &tick_detected) == TSL_STATUS_OK)\r
+ {\r
+ TSL_linrot_SetStateCalibration(0);\r
+ }\r
+ }\r
+ }\r
+#endif\r
+ return; // Normal operation, stay in Detect state\r
+ }\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_PROXOUT_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_PROX;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_PROX_DETECT;\r
+ }\r
+ return;\r
+ }\r
+#endif\r
+\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_DETECT;\r
+ }\r
+\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Touch state processing\r
+ * Same as Detect state\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_TouchStateProcess(void)\r
+{\r
+#if TSLPRM_DTO > 0\r
+ TSL_Status_enum_T pos_sts;\r
+ TSL_tTick_sec_T tick_detected;\r
+#endif\r
+\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_TOUCH;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_DETECTOUT_TH, 1) == TSL_STATUS_OK)\r
+ {\r
+ //-------------------\r
+ // Calculate position\r
+ //-------------------\r
+ if ((THIS_OBJ_TYPE == TSL_OBJ_LINEAR) || (THIS_OBJ_TYPE == TSL_OBJ_ROTARY))\r
+ {\r
+ // Call the specific method\r
+#if TSLPRM_DTO > 0\r
+ pos_sts = TSL_Globals.This_LinRot->p_Methods->CalcPosition();\r
+#else\r
+ TSL_Globals.This_LinRot->p_Methods->CalcPosition();\r
+#endif\r
+ }\r
+ else // TSL_OBJ_LINEARB or TSL_OBJ_ROTARYB\r
+ {\r
+ // Call the default method\r
+#if TSLPRM_DTO > 0\r
+ pos_sts = TSL_Params.p_LinRotMT->CalcPosition();\r
+#else\r
+ TSL_Params.p_LinRotMT->CalcPosition();\r
+#endif\r
+ }\r
+#if TSLPRM_DTO > 0\r
+ //------------------------------------\r
+ // Detection Time Out (DTO) processing\r
+ // Only if the Position has NOT changed\r
+ //-------------------------------------\r
+ if (pos_sts == TSL_STATUS_OK)\r
+ {\r
+ DTO_GET_TIME; // Take current time\r
+ }\r
+ else\r
+ {\r
+ if ((TSL_Params.DTO > 1) && (TSL_Params.DTO < 64))\r
+ {\r
+ tick_detected = THIS_COUNTER; // Get the detected time previously saved\r
+ // Enter in calibration state if the DTO duration has elapsed\r
+ if (TSL_tim_CheckDelay_sec(TSL_Params.DTO, &tick_detected) == TSL_STATUS_OK)\r
+ {\r
+ TSL_linrot_SetStateCalibration(0);\r
+ }\r
+ }\r
+ }\r
+#endif\r
+ return; // Normal operation, stay in Touch state\r
+ }\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+ if (TSL_linrot_ProcessCh_One_DeltaAbove(THIS_PROXOUT_TH, 0) == TSL_STATUS_OK)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_PROX;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_PROX_TOUCH;\r
+ }\r
+ return;\r
+ }\r
+#endif\r
+\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_TOUCH;\r
+ }\r
+\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Debounce error state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DebErrorStateProcess(void)\r
+{\r
+ volatile TSL_StateMask_enum_T mask;\r
+\r
+ if (TSL_linrot_ProcessCh_One_AcqStatusError() == TSL_STATUS_OK) // Acquisition error (min or max)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ // Get state mask\r
+ mask = TSL_linrot_GetStateMask();\r
+ // Mask Error and Debounce bits\r
+#ifdef _RAISONANCE_\r
+ mask &= ~(TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK);\r
+#else\r
+ mask &= (TSL_StateMask_enum_T)(~(TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK));\r
+#endif\r
+ // Go back to the previous state\r
+ switch (mask)\r
+ {\r
+ case TSL_STATEMASK_RELEASE :\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ break;\r
+ case TSL_STATEMASK_PROX :\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ break;\r
+ case TSL_STATEMASK_DETECT :\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ break;\r
+ case TSL_STATEMASK_TOUCH :\r
+ THIS_STATEID = TSL_STATEID_TOUCH;\r
+ break;\r
+ default:\r
+ TSL_linrot_SetStateCalibration(0);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+//==============================================================================\r
+// Private functions\r
+//==============================================================================\r
+\r
+/**\r
+ * @brief Get the current time in second and affect it to the DTO counter (Private)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_DTOGetTime(void)\r
+{\r
+ disableInterrupts();\r
+ THIS_COUNTER = (TSL_tCounter_T)TSL_Globals.Tick_sec;\r
+ enableInterrupts();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set all channels status to ON, OFF or BURST ONLY\r
+ * @param sts Channel status\r
+ * @retval None\r
+ */\r
+void TSL_linrot_ProcessCh_All_SetStatus(TSL_ObjStatus_enum_T sts)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ // Init channels status\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+ p_Ch->Flags.ObjStatus = sts;\r
+ p_Ch++;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if at least one channel has a data ready\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_DataReady(void)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ TSL_Status_enum_T retval = TSL_STATUS_ERROR;\r
+ // Return OK if at least one channel has a data ready\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+ if (p_Ch->Flags.DataReady == TSL_DATA_READY)\r
+ {\r
+ p_Ch->Flags.DataReady = TSL_DATA_NOT_READY; // The new data is processed\r
+ retval = TSL_STATUS_OK;\r
+ }\r
+ p_Ch++;\r
+ }\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if all channels are equal to the status passed\r
+ * @param sts Status to be checked\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_All_AcqStatus(TSL_AcqStatus_enum_T sts)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ // Return OK if ALL channels have the correct acq status\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+ if (p_Ch->Flags.AcqStatus != sts)\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ p_Ch++;\r
+ }\r
+ return TSL_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if at least one channel is in error\r
+ * @param None\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_AcqStatusError(void)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ // Return OK if at least one channel is in acquisition error min or max\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+ if (p_Ch->Flags.AcqStatus & TSL_ACQ_STATUS_ERROR_MASK)\r
+ {\r
+ return TSL_STATUS_OK;\r
+ }\r
+ p_Ch++;\r
+ }\r
+ return TSL_STATUS_ERROR;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if at least one channel is below or equal a threshold (inverted)\r
+ * @param th Threshold\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_DeltaBelowEquMinus(TSL_tThreshold_T th)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ TSL_tDelta_T norm_delta;\r
+\r
+ // Return OK if at least one channel is below or equal the threshold\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+\r
+#if TSLPRM_LINROT_USE_NORMDELTA > 0\r
+ norm_delta = TSL_linrot_NormDelta(p_Ch, idx); // Normalize the Delta\r
+#else\r
+ norm_delta = p_Ch->Delta; // Take only the Delta\r
+#endif\r
+\r
+ if (norm_delta <= -th) // Warning!!! The threshold is inverted\r
+ {\r
+ return TSL_STATUS_OK;\r
+ }\r
+ p_Ch++;\r
+ }\r
+ return TSL_STATUS_ERROR;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if at least one channel is above or equal a threshold\r
+ * @param th Threshold\r
+ * @param coeff Enable or Disable the multiplier coefficient on threshold\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_DeltaAboveEqu(TSL_tThreshold_T th, TSL_tIndex_T coeff)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ TSL_tDelta_T norm_delta;\r
+\r
+#if TSLPRM_COEFF_TH > 0\r
+ uint16_t lth;\r
+ if (coeff)\r
+ {\r
+ lth = (uint16_t)((uint16_t)th << TSLPRM_COEFF_TH);\r
+ }\r
+ else\r
+ {\r
+ lth = th;\r
+ }\r
+#endif\r
+\r
+ // Return OK if at least one channel is above or equal the threshold\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+\r
+#if TSLPRM_LINROT_USE_NORMDELTA > 0\r
+ norm_delta = TSL_linrot_NormDelta(p_Ch, idx); // Normalize the Delta\r
+#else\r
+ norm_delta = p_Ch->Delta; // Take only the Delta\r
+#endif\r
+\r
+#if TSLPRM_COEFF_TH > 0\r
+ if (norm_delta >= lth)\r
+#else\r
+ if (norm_delta >= th)\r
+#endif\r
+ {\r
+#if TSLPRM_COEFF_TH > 0\r
+ if (norm_delta < 0)\r
+ {\r
+ p_Ch++;\r
+ continue;\r
+ }\r
+#endif\r
+ return TSL_STATUS_OK;\r
+ }\r
+ p_Ch++;\r
+ }\r
+ return TSL_STATUS_ERROR;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if at least one channel is stricly above a threshold\r
+ * @param th Threshold\r
+ * @param coeff Enable or Disable the multiplier coefficient on threshold\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_One_DeltaAbove(TSL_tThreshold_T th, TSL_tIndex_T coeff)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ TSL_tDelta_T norm_delta;\r
+\r
+#if TSLPRM_COEFF_TH > 0\r
+ uint16_t lth;\r
+ if (coeff)\r
+ {\r
+ lth = (uint16_t)((uint16_t)th << TSLPRM_COEFF_TH);\r
+ }\r
+ else\r
+ {\r
+ lth = th;\r
+ }\r
+#endif\r
+\r
+ // Return OK if at least one channel is above the threshold\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+\r
+#if TSLPRM_LINROT_USE_NORMDELTA > 0\r
+ norm_delta = TSL_linrot_NormDelta(p_Ch, idx); // Normalize the Delta\r
+#else\r
+ norm_delta = p_Ch->Delta; // Take only the Delta\r
+#endif\r
+\r
+#if TSLPRM_COEFF_TH > 0\r
+ if (norm_delta > lth)\r
+#else\r
+ if (norm_delta > th)\r
+#endif\r
+ {\r
+#if TSLPRM_COEFF_TH > 0\r
+ if (norm_delta < 0)\r
+ {\r
+ p_Ch++;\r
+ continue;\r
+ }\r
+#endif\r
+ return TSL_STATUS_OK;\r
+ }\r
+ p_Ch++;\r
+ }\r
+ return TSL_STATUS_ERROR;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if all channels are below or equal a threshold\r
+ * @param th Threshold\r
+ * @param coeff Enable or Disable the multiplier coefficient on threshold\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_linrot_ProcessCh_All_DeltaBelowEqu(TSL_tThreshold_T th, TSL_tIndex_T coeff)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ TSL_tDelta_T norm_delta;\r
+\r
+#if TSLPRM_COEFF_TH > 0\r
+ uint16_t lth;\r
+ if (coeff)\r
+ {\r
+ lth = (uint16_t)((uint16_t)th << TSLPRM_COEFF_TH);\r
+ }\r
+ else\r
+ {\r
+ lth = th;\r
+ }\r
+#endif\r
+\r
+ // Return OK if ALL channels are below or equal the threshold\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+\r
+#if TSLPRM_LINROT_USE_NORMDELTA > 0\r
+ norm_delta = TSL_linrot_NormDelta(p_Ch, idx); // Normalize the Delta\r
+#else\r
+ norm_delta = p_Ch->Delta; // Take only the Delta\r
+#endif\r
+\r
+#if TSLPRM_COEFF_TH > 0\r
+ if (norm_delta > lth)\r
+#else\r
+ if (norm_delta > th)\r
+#endif\r
+ {\r
+#if TSLPRM_COEFF_TH > 0\r
+ if (norm_delta < 0)\r
+ {\r
+ p_Ch++;\r
+ continue;\r
+ }\r
+#endif\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ p_Ch++;\r
+ }\r
+ return TSL_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clear the Reference and ReferenceRest for all channels\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_linrot_ProcessCh_All_ClearRef(void)\r
+{\r
+ TSL_tIndex_T idx;\r
+ TSL_ChannelData_T *p_Ch = TSL_Globals.This_LinRot->p_ChD;\r
+ for (idx = 0; idx < THIS_NB_CHANNELS; idx++)\r
+ {\r
+ p_Ch->Ref = 0;\r
+ p_Ch->RefRest = 0;\r
+ p_Ch++;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Normalize a Delta value\r
+ * @param ch Pointer to the current channel\r
+ * @param idx Index of the channel\r
+ * @retval Normalized Delta value\r
+ */\r
+TSL_tDelta_T TSL_linrot_NormDelta(TSL_ChannelData_T *ch, TSL_tIndex_T idx)\r
+{\r
+ uint32_t tmpdelta = ch->Delta;\r
+\r
+ // Apply coefficient\r
+ if (TSL_Globals.This_LinRot->p_DeltaCoeff[idx] != 0x0100)\r
+ {\r
+ tmpdelta = (uint32_t)(tmpdelta * TSL_Globals.This_LinRot->p_DeltaCoeff[idx]);\r
+ tmpdelta = tmpdelta >> (uint8_t)8;\r
+ }\r
+\r
+ return (TSL_tDelta_T)tmpdelta;\r
+}\r
+\r
+#endif\r
+// #if TSLPRM_TOTAL_LNRTS > 0\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_object.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the sensors in general.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_object.h"\r
+#include "tsl_globals.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initialize a group of Objects\r
+ * @param[in] objgrp Pointer to the group of objects\r
+ * @retval None\r
+ */\r
+void TSL_obj_GroupInit(TSL_ObjectGroup_T *objgrp)\r
+{\r
+ TSL_tIndex_T idx_obj;\r
+ CONST TSL_Object_T *pobj;\r
+ TSL_tNb_T objgrp_state_mask = 0;\r
+\r
+ pobj = objgrp->p_Obj; // First object in the group\r
+\r
+ objgrp->Change = TSL_STATE_NOT_CHANGED;\r
+\r
+ // Process all objects\r
+ for (idx_obj = 0; idx_obj < objgrp->NbObjects; idx_obj++)\r
+ {\r
+\r
+ // Assign global object\r
+ TSL_obj_SetGlobalObj(pobj);\r
+\r
+ switch (pobj->Type)\r
+ {\r
+ //------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_TOUCHKEYS > 0\r
+ case TSL_OBJ_TOUCHKEY:\r
+ // Call the specific method\r
+ TSL_Globals.This_TKey->p_Methods->Init();\r
+ // Check if the object has changed of state\r
+ if (TSL_Globals.This_TKey->p_Data->Change)\r
+ {\r
+ objgrp->Change = TSL_STATE_CHANGED;\r
+ }\r
+ // Update object group state mask\r
+ objgrp_state_mask |= TSL_Globals.This_TKey->p_SM[TSL_Globals.This_TKey->p_Data->StateId].StateMask;\r
+ break;\r
+#endif\r
+ //------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_TOUCHKEYS_B > 0\r
+ case TSL_OBJ_TOUCHKEYB:\r
+ // Call the default method\r
+ TSL_Params.p_TKeyMT->Init();\r
+ // Check if the object has changed of state\r
+ if (TSL_Globals.This_TKey->p_Data->Change)\r
+ {\r
+ objgrp->Change = TSL_STATE_CHANGED;\r
+ }\r
+ // Get object state mask from state machine in TSL_Params\r
+ objgrp_state_mask |= TSL_Params.p_TKeySM[TSL_Globals.This_TKey->p_Data->StateId].StateMask;\r
+ break;\r
+#endif\r
+ //------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_LINROTS > 0\r
+ case TSL_OBJ_LINEAR:\r
+ case TSL_OBJ_ROTARY:\r
+ // Call the specific method\r
+ TSL_Globals.This_LinRot->p_Methods->Init();\r
+ // Check if the object has changed of state\r
+ if (TSL_Globals.This_LinRot->p_Data->Change)\r
+ {\r
+ objgrp->Change = TSL_STATE_CHANGED;\r
+ }\r
+ // Update object group state mask\r
+ objgrp_state_mask |= TSL_Globals.This_LinRot->p_SM[TSL_Globals.This_LinRot->p_Data->StateId].StateMask;\r
+ break;\r
+#endif\r
+ //------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_LINROTS_B > 0\r
+ case TSL_OBJ_LINEARB:\r
+ case TSL_OBJ_ROTARYB:\r
+ // Call the default method\r
+ TSL_Params.p_LinRotMT->Init();\r
+ // Check if the object has changed of state\r
+ if (TSL_Globals.This_LinRot->p_Data->Change)\r
+ {\r
+ objgrp->Change = TSL_STATE_CHANGED;\r
+ }\r
+ // Get object state mask from state machine in TSL_Params\r
+ objgrp_state_mask |= TSL_Params.p_LinRotSM[TSL_Globals.This_LinRot->p_Data->StateId].StateMask;\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+\r
+ pobj++; // Next object\r
+ }\r
+\r
+ // Update the object group state mask\r
+ objgrp->StateMask = objgrp_state_mask;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Process the state machine on a group of Objects\r
+ * @param[in] objgrp Pointer to the group of objects to process\r
+ * @retval None\r
+ */\r
+void TSL_obj_GroupProcess(TSL_ObjectGroup_T *objgrp)\r
+{\r
+ TSL_tIndex_T idx_obj;\r
+ CONST TSL_Object_T *pobj;\r
+ TSL_tNb_T objgrp_state_mask = 0;\r
+\r
+ pobj = objgrp->p_Obj; // First object in the group\r
+\r
+ objgrp->Change = TSL_STATE_NOT_CHANGED;\r
+\r
+ // Process all objects\r
+ for (idx_obj = 0; idx_obj < objgrp->NbObjects; idx_obj++)\r
+ {\r
+\r
+ // Assign global object\r
+ TSL_obj_SetGlobalObj(pobj);\r
+\r
+ switch (pobj->Type)\r
+ {\r
+ //------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_TOUCHKEYS > 0\r
+ case TSL_OBJ_TOUCHKEY:\r
+ // Call the specific method\r
+ TSL_Globals.This_TKey->p_Methods->Process();\r
+ // Check if the object has changed of state\r
+ if (TSL_Globals.This_TKey->p_Data->Change)\r
+ {\r
+ objgrp->Change = TSL_STATE_CHANGED;\r
+ }\r
+ // Update object group state mask\r
+ objgrp_state_mask |= TSL_Globals.This_TKey->p_SM[TSL_Globals.This_TKey->p_Data->StateId].StateMask;\r
+ break;\r
+#endif\r
+ //------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_TOUCHKEYS_B > 0\r
+ case TSL_OBJ_TOUCHKEYB:\r
+ // Call the default method\r
+ TSL_Params.p_TKeyMT->Process();\r
+ // Check if the object has changed of state\r
+ if (TSL_Globals.This_TKey->p_Data->Change)\r
+ {\r
+ objgrp->Change = TSL_STATE_CHANGED;\r
+ }\r
+ // Get object state mask from state machine in TSL_Params\r
+ objgrp_state_mask |= TSL_Params.p_TKeySM[TSL_Globals.This_TKey->p_Data->StateId].StateMask;\r
+ break;\r
+#endif\r
+ //------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_LINROTS > 0\r
+ case TSL_OBJ_LINEAR:\r
+ case TSL_OBJ_ROTARY:\r
+ // Call the specific method\r
+ TSL_Globals.This_LinRot->p_Methods->Process();\r
+ // Check if the object has changed of state\r
+ if (TSL_Globals.This_LinRot->p_Data->Change)\r
+ {\r
+ objgrp->Change = TSL_STATE_CHANGED;\r
+ }\r
+ // Update object group state mask\r
+ objgrp_state_mask |= TSL_Globals.This_LinRot->p_SM[TSL_Globals.This_LinRot->p_Data->StateId].StateMask;\r
+ break;\r
+#endif\r
+ //------------------------------------------------------------------------\r
+#if TSLPRM_TOTAL_LINROTS_B > 0\r
+ case TSL_OBJ_LINEARB:\r
+ case TSL_OBJ_ROTARYB:\r
+ // Call the default method\r
+ TSL_Params.p_LinRotMT->Process();\r
+ // Check if the object has changed of state\r
+ if (TSL_Globals.This_LinRot->p_Data->Change)\r
+ {\r
+ objgrp->Change = TSL_STATE_CHANGED;\r
+ }\r
+ // Get object state mask from state machine in TSL_Params\r
+ objgrp_state_mask |= TSL_Params.p_LinRotSM[TSL_Globals.This_LinRot->p_Data->StateId].StateMask;\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+\r
+ pobj++; // Next object\r
+ }\r
+\r
+ // Update the object group state mask\r
+ objgrp->StateMask = objgrp_state_mask;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set the global object variable\r
+ * @param[in] pobj Pointer to the object to process\r
+ * @retval None\r
+ */\r
+void TSL_obj_SetGlobalObj(CONST TSL_Object_T *pobj)\r
+{\r
+\r
+ TSL_Globals.This_Obj = pobj;\r
+\r
+ switch (pobj->Type)\r
+ {\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+ case TSL_OBJ_TOUCHKEY:\r
+ case TSL_OBJ_TOUCHKEYB:\r
+ TSL_Globals.This_TKey = (TSL_TouchKey_T *)pobj->Elmt;\r
+ break;\r
+#endif\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ case TSL_OBJ_LINEAR:\r
+ case TSL_OBJ_LINEARB:\r
+ case TSL_OBJ_ROTARY:\r
+ case TSL_OBJ_ROTARYB:\r
+ TSL_Globals.This_LinRot = (TSL_LinRot_T *)pobj->Elmt;\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the timings in general.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_time.h"\r
+#include "tsl_globals.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Management of the timing module interrupt service routine.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tim_ProcessIT(void)\r
+{\r
+ static TSL_tTick_ms_T count_1s = 0;\r
+\r
+ // Count 1 global tick every xxx ms (defined by TSLPRM_TICK_FREQ parameter)\r
+ TSL_Globals.Tick_ms++;\r
+\r
+ // Check if 1 second has elapsed\r
+ count_1s++;\r
+ if (count_1s > (TSLPRM_TICK_FREQ - 1))\r
+ {\r
+ TSL_Globals.Tick_sec++; // 1 global tick every second\r
+ if (TSL_Globals.Tick_sec > 63) // Due to DTO counter on 6 bits...\r
+ {\r
+ TSL_Globals.Tick_sec = 0;\r
+ }\r
+ count_1s = 0;\r
+ }\r
+\r
+// Callback function\r
+#if TSLPRM_USE_TIMER_CALLBACK > 0\r
+ TSL_CallBack_TimerTick();\r
+#endif\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a delay (in ms) has elapsed.\r
+ * This function must be called regularly due to counter Roll-over only managed one time.\r
+ * @param[in] delay_ms Delay in ms\r
+ * @param[in] last_tick Variable holding the last tick value\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_tim_CheckDelay_ms(TSL_tTick_ms_T delay_ms, __IO TSL_tTick_ms_T *last_tick)\r
+{\r
+ TSL_tTick_ms_T tick;\r
+ TSL_tTick_ms_T diff;\r
+\r
+ disableInterrupts();\r
+\r
+ tick = TSL_Globals.Tick_ms;\r
+\r
+ if (delay_ms == 0)\r
+ {\r
+ enableInterrupts();\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+\r
+ // Counter Roll-over management\r
+ if (tick >= *last_tick)\r
+ {\r
+ diff = tick - *last_tick;\r
+ }\r
+ else\r
+ {\r
+ diff = (0xFFFF - *last_tick) + tick + 1;\r
+ }\r
+\r
+#if (TSLPRM_TICK_FREQ == 125)\r
+ if (diff >= (TSL_tTick_ms_T)(delay_ms >> 3)) // Divide by 8 for 8ms tick\r
+#endif\r
+#if (TSLPRM_TICK_FREQ == 250)\r
+ if (diff >= (TSL_tTick_ms_T)(delay_ms >> 2)) // Divide by 4 for 4ms tick\r
+#endif\r
+#if (TSLPRM_TICK_FREQ == 500)\r
+ if (diff >= (TSL_tTick_ms_T)(delay_ms >> 1)) // Divide by 2 for 2ms tick\r
+#endif\r
+#if (TSLPRM_TICK_FREQ == 1000)\r
+ if (diff >= (TSL_tTick_ms_T)delay_ms) // Direct value for 1ms tick\r
+#endif\r
+#if (TSLPRM_TICK_FREQ == 2000)\r
+ if (diff >= (TSL_tTick_ms_T)(delay_ms << 1)) // Multiply by 2 for 0.5ms tick\r
+#endif\r
+ {\r
+ // Save current time\r
+ *last_tick = tick;\r
+ enableInterrupts();\r
+ return TSL_STATUS_OK;\r
+ }\r
+\r
+ enableInterrupts();\r
+ return TSL_STATUS_BUSY;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a delay (in s) has elapsed.\r
+ * @param[in] delay_sec Delay in seconds\r
+ * @param[in] last_tick Variable holding the last tick value\r
+ * @retval Status\r
+ */\r
+TSL_Status_enum_T TSL_tim_CheckDelay_sec(TSL_tTick_sec_T delay_sec, __IO TSL_tTick_sec_T *last_tick)\r
+{\r
+ TSL_tTick_sec_T tick;\r
+ TSL_tTick_sec_T diff;\r
+\r
+ disableInterrupts();\r
+\r
+ tick = TSL_Globals.Tick_sec;\r
+\r
+ if (delay_sec == 0)\r
+ {\r
+ enableInterrupts();\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+\r
+ // Counter Roll-over management\r
+ if (tick >= *last_tick)\r
+ {\r
+ diff = (TSL_tTick_sec_T)(tick - *last_tick);\r
+ }\r
+ else\r
+ {\r
+ diff = (TSL_tTick_sec_T)((63 - *last_tick) + tick + 1); // DTO counter is on 6 bits\r
+ }\r
+\r
+ if (diff >= delay_sec)\r
+ {\r
+ // Save current time\r
+ *last_tick = tick;\r
+ enableInterrupts();\r
+ return TSL_STATUS_OK;\r
+ }\r
+\r
+ enableInterrupts();\r
+ return TSL_STATUS_BUSY;\r
+\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time_stm32f0xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the timing with STM32F0xx products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_time_stm32f0xx.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initialization of the timing module.\r
+ * @param None\r
+ * @retval Status Return TSL_STATUS_ERROR if the Systick configuration has failed.\r
+ */\r
+TSL_Status_enum_T TSL_tim_Init(void)\r
+{\r
+ // Program one systick interrupt every (1 / TSLPRM_TICK_FREQ) ms\r
+ if (SysTick_Config(SystemCoreClock / TSLPRM_TICK_FREQ))\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return TSL_STATUS_OK;\r
+ }\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time_stm32f3xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the timing with STM32F3xx products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_time_stm32f3xx.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initialization of the timing module.\r
+ * @param None\r
+ * @retval Status Return TSL_STATUS_ERROR if the Systick configuration has failed.\r
+ */\r
+TSL_Status_enum_T TSL_tim_Init(void)\r
+{\r
+ // Program one systick interrupt every (1 / TSLPRM_TICK_FREQ) ms\r
+ if (SysTick_Config(SystemCoreClock / TSLPRM_TICK_FREQ))\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return TSL_STATUS_OK;\r
+ }\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time_stm32l1xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the timing with STM32L1xx products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_time_stm32l1xx.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initialization of the timing module.\r
+ * @param None\r
+ * @retval Status Return TSL_STATUS_ERROR if the Systick configuration has failed.\r
+ */\r
+TSL_Status_enum_T TSL_tim_Init(void)\r
+{\r
+ // Program one systick interrupt every (1 / TSLPRM_TICK_FREQ) ms\r
+ if (SysTick_Config(SystemCoreClock / TSLPRM_TICK_FREQ))\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return TSL_STATUS_OK;\r
+ }\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_time_stm8tl5x.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage the timing with STM8TL5x products.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_time_stm8tl5x.h"\r
+#include "tsl_time.h"\r
+#include "stm8tl5x_it.h"\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initialization of the timing module to generate periodic interruptions\r
+ * @warning The CPU frequency must be equal to 16 MHz\r
+ * @param None\r
+ * @retval Status Return TSL_STATUS_ERROR if the CPU freq in uncorrect.\r
+ */\r
+TSL_Status_enum_T TSL_tim_Init(void)\r
+{\r
+ CLK->PCKENR1 |= CLK_PCKENR1_TIM4; // The peripheral clock are not enable by default\r
+\r
+ if (CLK->CKDIVR != 0x00) // The CPU frequency must be equal to 16 MHz\r
+ {\r
+ return TSL_STATUS_ERROR;\r
+ }\r
+\r
+ TIM4->SR1 = 0; // Clear overflow flag\r
+\r
+#if (TSLPRM_TICK_FREQ == 2000)\r
+ TIM4->PSCR = 6; // 16 MHz / 64 = 4 us clock\r
+ TIM4->ARR = 124; // 125 * 4 us = 0.5 ms\r
+#endif\r
+\r
+#if (TSLPRM_TICK_FREQ == 1000)\r
+ TIM4->PSCR = 6; // 16 MHz / 64 = 4 us clock\r
+ TIM4->ARR = 249; // 250 * 4 us = 1 ms\r
+#endif\r
+\r
+#if (TSLPRM_TICK_FREQ == 500)\r
+ TIM4->PSCR = 8; // 16 MHz / 256 = 16 us clock\r
+ TIM4->ARR = 124; // 125 * 16 us = 2 ms\r
+#endif\r
+\r
+#if (TSLPRM_TICK_FREQ == 250)\r
+ TIM4->PSCR = 8; // 16 MHz / 256 = 16 us clock\r
+ TIM4->ARR = 249; // 250 * 16 us = 4 ms\r
+#endif\r
+\r
+#if (TSLPRM_TICK_FREQ == 125)\r
+ TIM4->PSCR = 10; // 16 MHz / 1024 = 64 us clock\r
+ TIM4->ARR = 124; // 125 * 64 us = 8 ms\r
+#endif\r
+\r
+ TIM4->IER = 0x01; // Enable interrupt\r
+ TIM4->CR1 = 0x01; // Start timer\r
+\r
+ return TSL_STATUS_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Interrupt handler for TIM4 dedicated to ECS\r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if defined(_COSMIC_)\r
+// 'svlreg option' is added to force the saving of the virtual long register\r
+@svlreg INTERRUPT_HANDLER(TSL_Timer_ISR, 25)\r
+#else\r
+INTERRUPT_HANDLER(TSL_Timer_ISR, 25)\r
+#endif\r
+{\r
+ TIM4->SR1 &= (uint8_t)(~TIM4_SR1_UIF);\r
+ TSL_tim_ProcessIT();\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file tsl_touchkey.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 22-January-2013\r
+ * @brief This file contains all functions to manage TouchKey sensors.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "tsl_touchkey.h"\r
+#include "tsl_globals.h"\r
+\r
+#if TSLPRM_TOTAL_TKEYS > 0\r
+\r
+/* Private typedefs ----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+#define THIS_MEAS TSL_Globals.This_TKey->p_ChD->Meas\r
+#define THIS_DELTA TSL_Globals.This_TKey->p_ChD->Delta\r
+#define THIS_REF TSL_Globals.This_TKey->p_ChD->Ref\r
+#define THIS_REFREST TSL_Globals.This_TKey->p_ChD->RefRest\r
+#define THIS_CHANNEL_DATA TSL_Globals.This_TKey->p_ChD\r
+#define THIS_ACQ_STATUS TSL_Globals.This_TKey->p_ChD->Flags.AcqStatus\r
+#define THIS_OBJ_STATUS TSL_Globals.This_TKey->p_ChD->Flags.ObjStatus\r
+#define THIS_DATA_READY TSL_Globals.This_TKey->p_ChD->Flags.DataReady\r
+\r
+#define THIS_STATEID TSL_Globals.This_TKey->p_Data->StateId\r
+#define THIS_CHANGE TSL_Globals.This_TKey->p_Data->Change\r
+#define THIS_COUNTER TSL_Globals.This_TKey->p_Data->Counter\r
+#define THIS_DXSLOCK TSL_Globals.This_TKey->p_Data->DxSLock\r
+\r
+#define THIS_PROXIN_TH TSL_Globals.This_TKey->p_Param->ProxInTh\r
+#define THIS_PROXOUT_TH TSL_Globals.This_TKey->p_Param->ProxOutTh\r
+#define THIS_DETECTIN_TH TSL_Globals.This_TKey->p_Param->DetectInTh\r
+#define THIS_DETECTOUT_TH TSL_Globals.This_TKey->p_Param->DetectOutTh\r
+#define THIS_CALIB_TH TSL_Globals.This_TKey->p_Param->CalibTh\r
+\r
+#define THIS_COUNTER_DEB_CALIB TSL_Globals.This_TKey->p_Param->CounterDebCalib\r
+#define THIS_COUNTER_DEB_PROX TSL_Globals.This_TKey->p_Param->CounterDebProx\r
+#define THIS_COUNTER_DEB_DETECT TSL_Globals.This_TKey->p_Param->CounterDebDetect\r
+#define THIS_COUNTER_DEB_RELEASE TSL_Globals.This_TKey->p_Param->CounterDebRelease\r
+#define THIS_COUNTER_DEB_ERROR TSL_Globals.This_TKey->p_Param->CounterDebError\r
+\r
+#if TSLPRM_DTO > 0\r
+#define DTO_GET_TIME {TSL_tkey_DTOGetTime();}\r
+#else\r
+#define DTO_GET_TIME\r
+#endif\r
+\r
+#if TSLPRM_COEFF_TH > 0\r
+#define TEST_DELTA(OPER,TH) (THIS_DELTA OPER (uint16_t)((uint16_t)TH << TSLPRM_COEFF_TH))\r
+#define TEST_DELTA_NEGATIVE {if (THIS_DELTA < 0) {return;}}\r
+#else\r
+#define TEST_DELTA(OPER,TH) (THIS_DELTA OPER TH)\r
+#define TEST_DELTA_NEGATIVE\r
+#endif\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+static TSL_tNb_T CalibDiv;\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+void TSL_tkey_DTOGetTime(void);\r
+\r
+\r
+//==============================================================================\r
+// "Object methods" functions\r
+//==============================================================================\r
+\r
+/**\r
+ * @brief Init parameters with default values from configuration file\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_Init(void)\r
+{\r
+ // Thresholds\r
+#if TSLPRM_USE_PROX > 0\r
+ THIS_PROXIN_TH = TSLPRM_TKEY_PROX_IN_TH;\r
+ THIS_PROXOUT_TH = TSLPRM_TKEY_PROX_OUT_TH;\r
+#endif\r
+ THIS_DETECTIN_TH = TSLPRM_TKEY_DETECT_IN_TH;\r
+ THIS_DETECTOUT_TH = TSLPRM_TKEY_DETECT_OUT_TH;\r
+ THIS_CALIB_TH = TSLPRM_TKEY_CALIB_TH;\r
+\r
+ // Debounce counters\r
+ THIS_COUNTER_DEB_CALIB = TSLPRM_DEBOUNCE_CALIB;\r
+#if TSLPRM_USE_PROX > 0\r
+ THIS_COUNTER_DEB_PROX = TSLPRM_DEBOUNCE_PROX;\r
+#endif\r
+ THIS_COUNTER_DEB_DETECT = TSLPRM_DEBOUNCE_DETECT;\r
+ THIS_COUNTER_DEB_RELEASE = TSLPRM_DEBOUNCE_RELEASE;\r
+ THIS_COUNTER_DEB_ERROR = TSLPRM_DEBOUNCE_ERROR;\r
+\r
+ // Initial state\r
+ TSL_tkey_SetStateCalibration(TSLPRM_CALIB_DELAY);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Process the State Machine\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_Process(void)\r
+{\r
+ TSL_StateId_enum_T prev_state_id;\r
+\r
+ if ((THIS_DATA_READY != 0) || (THIS_STATEID == TSL_STATEID_OFF))\r
+ {\r
+\r
+ THIS_DATA_READY = TSL_DATA_NOT_READY; // The new data is processed\r
+\r
+ prev_state_id = THIS_STATEID;\r
+\r
+#if TSLPRM_TOTAL_TOUCHKEYS > 0\r
+ if (TSL_Globals.This_Obj->Type == TSL_OBJ_TOUCHKEY)\r
+ {\r
+ // Launch the TKey state function\r
+ TSL_Globals.This_TKey->p_SM[THIS_STATEID].StateFunc();\r
+ }\r
+#endif\r
+\r
+#if TSLPRM_TOTAL_TOUCHKEYS_B > 0\r
+ if (TSL_Globals.This_Obj->Type == TSL_OBJ_TOUCHKEYB)\r
+ {\r
+ // Launch the TSL_Params state function\r
+ TSL_Params.p_TKeySM[THIS_STATEID].StateFunc();\r
+ }\r
+#endif\r
+\r
+ // Check if the new state has changed\r
+ if (THIS_STATEID == prev_state_id)\r
+ {\r
+ THIS_CHANGE = TSL_STATE_NOT_CHANGED;\r
+ }\r
+ else\r
+ {\r
+ THIS_CHANGE = TSL_STATE_CHANGED;\r
+ }\r
+\r
+#if TSLPRM_USE_DXS > 0\r
+ if (THIS_STATEID != TSL_STATEID_DETECT)\r
+ {\r
+ THIS_DXSLOCK = TSL_FALSE;\r
+ }\r
+ if (THIS_STATEID == TSL_STATEID_TOUCH)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ }\r
+#endif\r
+\r
+ }\r
+}\r
+\r
+\r
+//==============================================================================\r
+// Utility functions\r
+//==============================================================================\r
+\r
+/**\r
+ * @brief Go in Calibration state\r
+ * @param[in] delay Delay before calibration starts (stabilization of noise filter)\r
+ * @retval None\r
+ */\r
+void TSL_tkey_SetStateCalibration(TSL_tCounter_T delay)\r
+{\r
+ THIS_STATEID = TSL_STATEID_CALIB;\r
+ THIS_CHANGE = TSL_STATE_CHANGED;\r
+ THIS_OBJ_STATUS = TSL_OBJ_STATUS_ON;\r
+\r
+ switch (TSL_Params.NbCalibSamples)\r
+ {\r
+ case 4:\r
+ CalibDiv = 2;\r
+ break;\r
+ case 16:\r
+ CalibDiv = 4;\r
+ break;\r
+ default:\r
+ TSL_Params.NbCalibSamples = 8;\r
+ CalibDiv = 3;\r
+ break;\r
+ }\r
+\r
+ // If a noise filter is used, the counter must be initialized to a value\r
+ // different from 0 in order to stabilize the filter.\r
+ THIS_COUNTER = (TSL_tCounter_T)(delay + (TSL_tCounter_T)TSL_Params.NbCalibSamples);\r
+ THIS_REF = 0;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Go in Off state with sensor "off"\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_SetStateOff(void)\r
+{\r
+ THIS_STATEID = TSL_STATEID_OFF;\r
+ THIS_CHANGE = TSL_STATE_CHANGED;\r
+ THIS_OBJ_STATUS = TSL_OBJ_STATUS_OFF;\r
+}\r
+\r
+\r
+#if !defined(TSLPRM_STM8TL5X) && !defined(STM8TL5X)\r
+/**\r
+ * @brief Go in Off state with sensor in "Burst mode only"\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_SetStateBurstOnly(void)\r
+{\r
+ THIS_STATEID = TSL_STATEID_OFF;\r
+ THIS_CHANGE = TSL_STATE_CHANGED;\r
+ THIS_OBJ_STATUS = TSL_OBJ_STATUS_BURST_ONLY;\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Return the current state identifier\r
+ * @param None\r
+ * @retval State id\r
+ */\r
+TSL_StateId_enum_T TSL_tkey_GetStateId(void)\r
+{\r
+ return(THIS_STATEID);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the current state mask\r
+ * @param None\r
+ * @retval State mask\r
+ */\r
+TSL_StateMask_enum_T TSL_tkey_GetStateMask(void)\r
+{\r
+ TSL_StateMask_enum_T state_mask = TSL_STATEMASK_UNKNOWN;\r
+\r
+#if TSLPRM_TOTAL_TOUCHKEYS > 0\r
+ if (TSL_Globals.This_Obj->Type == TSL_OBJ_TOUCHKEY)\r
+ {\r
+ state_mask = TSL_Globals.This_TKey->p_SM[THIS_STATEID].StateMask;\r
+ }\r
+#endif\r
+\r
+#if TSLPRM_TOTAL_TOUCHKEYS_B > 0\r
+ if (TSL_Globals.This_Obj->Type == TSL_OBJ_TOUCHKEYB)\r
+ {\r
+ state_mask = TSL_Params.p_TKeySM[THIS_STATEID].StateMask;\r
+ }\r
+#endif\r
+\r
+ return state_mask;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the Change flag\r
+ * @param None\r
+ * @retval Change flag status\r
+ */\r
+TSL_tNb_T TSL_tkey_IsChanged(void)\r
+{\r
+ return(THIS_CHANGE);\r
+}\r
+\r
+\r
+//==============================================================================\r
+// State machine functions\r
+//==============================================================================\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Debounce Release processing (previous state = Proximity)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebReleaseProxStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX; // Go back to the previous state\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if (THIS_DELTA > THIS_PROXOUT_TH)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX; // Go back to the previous state\r
+ }\r
+ else\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ // else stay in Debounce Release\r
+ }\r
+ }\r
+}\r
+#endif // if TSLPRM_USE_PROX > 0\r
+\r
+\r
+/**\r
+ * @brief Debounce Release processing (previous state = Detect)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebReleaseDetectStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT; // Go back to the previous state\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>, THIS_DETECTOUT_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ }\r
+ else\r
+ {\r
+#if TSLPRM_USE_PROX > 0\r
+ if (THIS_DELTA > THIS_PROXOUT_TH)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ return;\r
+ }\r
+#endif\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ // else stay in Debounce Release\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Debounce Release processing (previous state = Touch)\r
+ * Same as Debounce Release Detect processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebReleaseTouchStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_TOUCH; // Go back to the previous state\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>, THIS_DETECTOUT_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+ THIS_STATEID = TSL_STATEID_TOUCH;\r
+ }\r
+ else\r
+ {\r
+#if TSLPRM_USE_PROX > 0\r
+ if (THIS_DELTA > THIS_PROXOUT_TH)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ return;\r
+ }\r
+#endif\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ // else stay in Debounce Release\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Release state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_ReleaseStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_RELEASE;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>=, THIS_DETECTIN_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+ THIS_COUNTER = THIS_COUNTER_DEB_DETECT;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_DETECT;\r
+ }\r
+ return;\r
+ }\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+ if (THIS_DELTA >= THIS_PROXIN_TH)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_PROX;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_PROX;\r
+ }\r
+ return;\r
+ }\r
+#endif\r
+\r
+ // Check delta for re-calibration\r
+ // Warning: the threshold value is inverted\r
+ if (THIS_DELTA <= -THIS_CALIB_TH)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_CALIB;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ TSL_tkey_SetStateCalibration(0);\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_CALIB;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Debounce Calibration processing (previous state = Release)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebCalibrationStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE; // Go back to the previous state\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ // Still below recalibration threshold\r
+ // Warning: the threshold value is inverted\r
+ if (THIS_DELTA <= -THIS_CALIB_TH)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ TSL_tkey_SetStateCalibration(0);\r
+ }\r
+ // else stay in Debounce Calibration\r
+ }\r
+ else // Go back to previous state\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Calibration state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_CalibrationStateProcess(void)\r
+{\r
+ TSL_tMeas_T new_meas;\r
+\r
+#if TSLPRM_CALIB_DELAY > 0\r
+ // Noise filter stabilization time\r
+ if (THIS_COUNTER > (TSL_tCounter_T)TSL_Params.NbCalibSamples)\r
+ {\r
+ THIS_COUNTER--;\r
+ return; // Skip the sample\r
+ }\r
+#endif\r
+\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_CALIB;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+\r
+ // Get the new measure or Calculate it\r
+#if TSLPRM_USE_MEAS > 0\r
+ new_meas = THIS_MEAS;\r
+#else // Calculate it\r
+ new_meas = TSL_acq_ComputeMeas(THIS_REF, THIS_DELTA);\r
+#endif\r
+\r
+ // Verify the first Reference value\r
+ if (THIS_COUNTER == (TSL_tCounter_T)TSL_Params.NbCalibSamples)\r
+ {\r
+ if (TSL_acq_TestFirstReferenceIsValid(THIS_CHANNEL_DATA, new_meas))\r
+ {\r
+ THIS_REF = new_meas;\r
+ }\r
+ else\r
+ {\r
+ THIS_REF = 0;\r
+ return;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ // Add the measure in temporary Reference\r
+ THIS_REF += new_meas;\r
+\r
+ // Check reference overflow\r
+ if (THIS_REF < new_meas)\r
+ {\r
+ THIS_REF = 0; // Suppress the bad reference\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ return;\r
+ }\r
+ }\r
+\r
+ // Check that we have all the needed measurements\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ // Divide temporary Reference by the number of samples\r
+ THIS_REF >>= CalibDiv;\r
+ THIS_REFREST = 0;\r
+ THIS_DELTA = 0;\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Debounce Proximity processing (previous state = Release)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebProxStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>=, THIS_DETECTIN_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+ THIS_COUNTER = THIS_COUNTER_DEB_DETECT;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_DETECT;\r
+ }\r
+ return;\r
+ }\r
+\r
+ if (THIS_DELTA >= THIS_PROXIN_TH)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ // else stay in Debounce Proximity\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Debounce Proximity processing (previous state = Detect)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebProxDetectStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>, THIS_DETECTOUT_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ return;\r
+ }\r
+\r
+ if (THIS_DELTA > THIS_PROXOUT_TH)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ // else stay in Debounce Proximity\r
+ }\r
+ else\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_DETECT;\r
+ }\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Debounce Proximity processing (previous state = Touch)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebProxTouchStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_TOUCH;\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>, THIS_DETECTOUT_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+ THIS_STATEID = TSL_STATEID_TOUCH;\r
+ return;\r
+ }\r
+\r
+ if (THIS_DELTA > THIS_PROXOUT_TH)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ // else stay in Debounce Proximity\r
+ }\r
+ else\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_TOUCH;\r
+ }\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+/**\r
+ * @brief Proximity state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_ProxStateProcess(void)\r
+{\r
+#if TSLPRM_DTO > 0\r
+ TSL_tTick_sec_T tick_detected;\r
+#endif\r
+\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_PROX;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>=, THIS_DETECTIN_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+ THIS_COUNTER = THIS_COUNTER_DEB_DETECT;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_DETECT;\r
+ }\r
+ return;\r
+ }\r
+\r
+ if (THIS_DELTA <= THIS_PROXOUT_TH)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_PROX;\r
+ }\r
+ return;\r
+ }\r
+\r
+ // Stay in Proximity state\r
+#if TSLPRM_DTO > 0\r
+ //------------------------------------\r
+ // Detection Time Out (DTO) processing\r
+ //------------------------------------\r
+ if ((TSL_Params.DTO > 1) && (TSL_Params.DTO < 64))\r
+ {\r
+ tick_detected = THIS_COUNTER; // Get the detected time previously saved\r
+ // Enter in calibration state if the DTO duration has elapsed\r
+ if (TSL_tim_CheckDelay_sec(TSL_Params.DTO, &tick_detected) == TSL_STATUS_OK)\r
+ {\r
+ TSL_tkey_SetStateCalibration(0);\r
+ }\r
+ }\r
+#endif\r
+\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Debounce Detect processing (previous state = Release or Proximity)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebDetectStateProcess(void)\r
+{\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>=, THIS_DETECTIN_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ // else stay in Debounce Detect\r
+ }\r
+ else\r
+ {\r
+#if TSLPRM_USE_PROX > 0\r
+ if (THIS_DELTA >= THIS_PROXIN_TH)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_PROX;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_PROX;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+#else\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+#endif\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Detect state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DetectStateProcess(void)\r
+{\r
+#if TSLPRM_DTO > 0\r
+ TSL_tTick_sec_T tick_detected;\r
+#endif\r
+\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_DETECT;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>, THIS_DETECTOUT_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+#if TSLPRM_DTO > 0\r
+ //------------------------------------\r
+ // Detection Time Out (DTO) processing\r
+ //------------------------------------\r
+ if ((TSL_Params.DTO > 1) && (TSL_Params.DTO < 64))\r
+ {\r
+ tick_detected = THIS_COUNTER; // Get the detected time previously saved\r
+ // Enter in calibration state if the DTO duration has elapsed\r
+ if (TSL_tim_CheckDelay_sec(TSL_Params.DTO, &tick_detected) == TSL_STATUS_OK)\r
+ {\r
+ TSL_tkey_SetStateCalibration(0);\r
+ }\r
+ }\r
+#endif\r
+ return; // Normal operation, stay in Detect state\r
+ }\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+ if (THIS_DELTA > THIS_PROXOUT_TH)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_PROX;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_PROX_DETECT;\r
+ }\r
+ return;\r
+ }\r
+#endif\r
+\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_DETECT;\r
+ }\r
+\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Touch state processing\r
+ * Same as Detect state\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_TouchStateProcess(void)\r
+{\r
+#if TSLPRM_DTO > 0\r
+ TSL_tTick_sec_T tick_detected;\r
+#endif\r
+\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_ERROR;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_ERROR_TOUCH;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ if TEST_DELTA(>, THIS_DETECTOUT_TH)\r
+ {\r
+ TEST_DELTA_NEGATIVE;\r
+#if TSLPRM_DTO > 0\r
+ //------------------------------------\r
+ // Detection Time Out (DTO) processing\r
+ //------------------------------------\r
+ if ((TSL_Params.DTO > 1) && (TSL_Params.DTO < 64))\r
+ {\r
+ tick_detected = THIS_COUNTER; // Get the detected time previously saved\r
+ // Enter in calibration state if the DTO duration has elapsed\r
+ if (TSL_tim_CheckDelay_sec(TSL_Params.DTO, &tick_detected) == TSL_STATUS_OK)\r
+ {\r
+ TSL_tkey_SetStateCalibration(0);\r
+ }\r
+ }\r
+#endif\r
+ return; // Normal operation, stay in Touch state\r
+ }\r
+\r
+#if TSLPRM_USE_PROX > 0\r
+ if (THIS_DELTA > THIS_PROXOUT_TH)\r
+ {\r
+ THIS_COUNTER = THIS_COUNTER_DEB_PROX;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ DTO_GET_TIME; // Take current time for DTO processing\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_PROX_TOUCH;\r
+ }\r
+ return;\r
+ }\r
+#endif\r
+\r
+ THIS_COUNTER = THIS_COUNTER_DEB_RELEASE;\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ }\r
+ else\r
+ {\r
+ THIS_STATEID = TSL_STATEID_DEB_RELEASE_TOUCH;\r
+ }\r
+\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Debounce error state processing\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DebErrorStateProcess(void)\r
+{\r
+ volatile TSL_StateMask_enum_T mask;\r
+\r
+ if (THIS_ACQ_STATUS & TSL_ACQ_STATUS_ERROR_MASK) // Acquisition error (min or max)\r
+ {\r
+ if (THIS_COUNTER > 0) {THIS_COUNTER--;}\r
+ if (THIS_COUNTER == 0)\r
+ {\r
+ THIS_STATEID = TSL_STATEID_ERROR;\r
+ }\r
+ }\r
+ else // Acquisition is OK or has NOISE\r
+ {\r
+ // Get state mask\r
+ mask = TSL_tkey_GetStateMask();\r
+ // Mask Error and Debounce bits\r
+#ifdef _RAISONANCE_\r
+ mask &= ~(TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK);\r
+#else\r
+ mask &= (TSL_StateMask_enum_T)(~(TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK));\r
+#endif\r
+ // Go back to the previous state\r
+ switch (mask)\r
+ {\r
+ case TSL_STATEMASK_RELEASE :\r
+ THIS_STATEID = TSL_STATEID_RELEASE;\r
+ break;\r
+ case TSL_STATEMASK_PROX :\r
+ THIS_STATEID = TSL_STATEID_PROX;\r
+ break;\r
+ case TSL_STATEMASK_DETECT :\r
+ THIS_STATEID = TSL_STATEID_DETECT;\r
+ break;\r
+ case TSL_STATEMASK_TOUCH :\r
+ THIS_STATEID = TSL_STATEID_TOUCH;\r
+ break;\r
+ default:\r
+ TSL_tkey_SetStateCalibration(0);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+//==============================================================================\r
+// Private functions\r
+//==============================================================================\r
+\r
+/**\r
+ * @brief Get the current time in second and affect it to the DTO counter (Private)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_tkey_DTOGetTime(void)\r
+{\r
+ disableInterrupts();\r
+ THIS_COUNTER = (TSL_tCounter_T)TSL_Globals.Tick_sec;\r
+ enableInterrupts();\r
+}\r
+\r
+#endif\r
+// #if TSLPRM_TOTAL_TKEYS > 0\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file discover_board.h\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Input/Output defines\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+\r
+#ifndef __DISCOVER_BOARD_H\r
+#define __DISCOVER_BOARD_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h" \r
+\r
+#define bool _Bool\r
+#define FALSE 0\r
+#define TRUE !FALSE\r
+\r
+/* MACROs for SET, RESET or TOGGLE Output port */\r
+\r
+#define GPIO_HIGH(a,b) a->BSRRL = b\r
+#define GPIO_LOW(a,b) a->BSRRH = b\r
+#define GPIO_TOGGLE(a,b) a->ODR ^= b \r
+\r
+#define USERBUTTON_GPIO_PORT GPIOA\r
+#define USERBUTTON_GPIO_PIN GPIO_Pin_0\r
+#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+\r
+#define LD_GPIO_PORT GPIOB\r
+#define LD_GREEN_GPIO_PIN GPIO_Pin_7\r
+#define LD_BLUE_GPIO_PIN GPIO_Pin_6\r
+#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB\r
+\r
+#define CTN_GPIO_PORT GPIOC\r
+#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13\r
+#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+\r
+#define WAKEUP_GPIO_PORT GPIOA\r
+\r
+#define IDD_MEASURE_PORT GPIOA\r
+#define IDD_MEASURE GPIO_Pin_4\r
+\r
+#endif\r
+\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l_discovery_lcd.c\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief This file includes driver for the glass LCD Module mounted on \r
+ * STM32l discovery board MB963\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l_discovery_lcd.h"\r
+#include "discover_board.h"\r
+#include "stm32l1xx_lcd.h"\r
+#include "main.h"\r
+\r
+/* this variable can be used for accelerate the scrolling exit when push user button */\r
+volatile bool KeyPressed = FALSE; \r
+ \r
+/* LCD BAR status: We don't write directly in LCD RAM for save the bar setting */\r
+uint8_t t_bar[2]={0x0,0X0};\r
+ \r
+/* =========================================================================\r
+ LCD MAPPING\r
+ =========================================================================\r
+ A\r
+ _ ----------\r
+COL |_| |\ |J /|\r
+ F| H | K |B\r
+ _ | \ | / |\r
+COL |_| --G-- --M--\r
+ | /| \ |\r
+ E| Q | N |C\r
+ _ | / |P \| \r
+DP |_| ----------- \r
+ D \r
+\r
+ An LCD character coding is based on the following matrix:\r
+ { E , D , P , N }\r
+ { M , C , COL , DP}\r
+ { B , A , K , J }\r
+ { G , F , Q , H }\r
+\r
+ The character 'A' for example is:\r
+ -------------------------------\r
+LSB { 1 , 0 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+MSB { 1 , 1 , 0 , 0 }\r
+ -------------------\r
+ 'A' = F E 0 0 hexa\r
+\r
+*/\r
+\r
+/* Constant table for cap characters 'A' --> 'Z' */\r
+const uint16_t CapLetterMap[26]=\r
+ {\r
+ /* A B C D E F G H I */\r
+ 0xFE00,0x6714,0x1d00,0x4714,0x9d00,0x9c00,0x3f00,0xfa00,0x0014,\r
+ /* J K L M N O P Q R */\r
+ 0x5300,0x9841,0x1900,0x5a48,0x5a09,0x5f00,0xFC00,0x5F01,0xFC01,\r
+ /* S T U V W X Y Z */\r
+ 0xAF00,0x0414,0x5b00,0x18c0,0x5a81,0x00c9,0x0058,0x05c0\r
+ };\r
+\r
+/* Constant table for number '0' --> '9' */\r
+const uint16_t NumberMap[10]=\r
+ {\r
+ /* 0 1 2 3 4 5 6 7 8 9 */\r
+ 0x5F00,0x4200,0xF500,0x6700,0xEa00,0xAF00,0xBF00,0x04600,0xFF00,0xEF00\r
+ };\r
+\r
+static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column,uint8_t* digit);\r
+\r
+/**\r
+ * @brief Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_Init(void)\r
+{\r
+ LCD_InitTypeDef LCD_InitStruct;\r
+\r
+ \r
+ LCD_InitStruct.LCD_Prescaler = LCD_Prescaler_1;\r
+ LCD_InitStruct.LCD_Divider = LCD_Divider_31;\r
+ LCD_InitStruct.LCD_Duty = LCD_Duty_1_4;\r
+ LCD_InitStruct.LCD_Bias = LCD_Bias_1_3;\r
+ LCD_InitStruct.LCD_VoltageSource = LCD_VoltageSource_Internal;\r
+\r
+ \r
+ /* Initialize the LCD */\r
+ LCD_Init(&LCD_InitStruct);\r
+ \r
+ LCD_MuxSegmentCmd(ENABLE);\r
+ \r
+ /* To set contrast to mean value */\r
+ LCD_ContrastConfig(LCD_Contrast_Level_4);\r
+ \r
+ LCD_DeadTimeConfig(LCD_DeadTime_0);\r
+ LCD_PulseOnDurationConfig(LCD_PulseOnDuration_4);\r
+\r
+ /* Wait Until the LCD FCR register is synchronized */\r
+ LCD_WaitForSynchro();\r
+ \r
+ /* Enable LCD peripheral */\r
+ LCD_Cmd(ENABLE);\r
+ \r
+ /* Wait Until the LCD is enabled */\r
+ while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)\r
+ {\r
+ }\r
+ /*!< Wait Until the LCD Booster is ready */ \r
+ while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)\r
+ {\r
+ } \r
+\r
+ LCD_BlinkConfig(LCD_BlinkMode_Off,LCD_BlinkFrequency_Div32); \r
+ LCD_GLASS_Clear();\r
+}\r
+\r
+/**\r
+ * @brief To initialize the LCD pins\r
+ * @caller main\r
+ * @param None\r
+ * @retval None\r
+ */\r
+\r
+void LCD_GLASS_Configure_GPIO(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ \r
+/* Enable GPIOs clock */ \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
+ RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, ENABLE);\r
+\r
+ \r
+/* Configure Output for LCD */\r
+/* Port A */\r
+ GPIO_StructInit(&GPIO_InitStructure);\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOA, &GPIO_InitStructure);\r
+\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ; \r
+ \r
+/* Configure Output for LCD */\r
+/* Port B */ \r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \\r
+ | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOB, &GPIO_InitStructure);\r
+ \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ; \r
+ \r
+/* Configure Output for LCD */\r
+/* Port C*/ \r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \\r
+ | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOC, &GPIO_InitStructure); \r
+ \r
+\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ; \r
+\r
+/* Disable GPIOs clock */ \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
+ RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, DISABLE);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief LCD contrast setting min-->max-->min by pressing user button\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_contrast()\r
+{\r
+ uint32_t contrast ;\r
+ \r
+ /* To get the actual contrast value in register */\r
+ contrast = LCD->FCR & LCD_Contrast_Level_7;\r
+ \r
+ while ((GPIOC->IDR & USERBUTTON_GPIO_PIN) == 0x0)\r
+ {\r
+ contrast += LCD_Contrast_Level_1; \r
+ \r
+ if (contrast > LCD_Contrast_Level_7)\r
+ contrast=LCD_Contrast_Level_0;\r
+ \r
+ LCD_ContrastConfig(contrast);\r
+ Delay(100);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Setting bar on LCD, writes bar value in LCD frame buffer \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_bar()\r
+{\r
+ \r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xffff5fff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xffff5fff;\r
+/* bar1 bar3 */\r
+ LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(t_bar[0]<<12);\r
+ \r
+/*bar0 bar2 */\r
+ LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(t_bar[1]<<12);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Converts an ascii char to the a LCD digit.\r
+ * @param c: a char to display.\r
+ * @param point: a point to add in front of char\r
+ * This parameter can be: POINT_OFF or POINT_ON\r
+ * @param column : flag indicating if a column has to be add in front\r
+ * of displayed character.\r
+ * This parameter can be: COLUMN_OFF or COLUMN_ON.\r
+ * @param digit array with segment \r
+ * @retval None\r
+ */\r
+static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit)\r
+{\r
+ uint16_t ch = 0 ;\r
+ uint8_t i,j;\r
+ \r
+ switch (*c)\r
+ {\r
+ case ' ' : \r
+ ch = 0x00;\r
+ break;\r
+ \r
+ case '*':\r
+ ch = star;\r
+ break;\r
+ \r
+ case 'µ' :\r
+ ch = C_UMAP;\r
+ break;\r
+ \r
+ case 'm' :\r
+ ch = C_mMap;\r
+ break;\r
+ \r
+ case 'n' :\r
+ ch = C_nMap;\r
+ break; \r
+ \r
+ case '-' :\r
+ ch = C_minus;\r
+ break;\r
+ \r
+ case '/' :\r
+ ch = C_slatch;\r
+ break; \r
+ \r
+ case '°' :\r
+ ch = C_percent_1;\r
+ break; \r
+ case '%' :\r
+ ch = C_percent_2; \r
+ break;\r
+ case 255 :\r
+ ch = C_full;\r
+ break ;\r
+ \r
+ case '0':\r
+ case '1':\r
+ case '2':\r
+ case '3':\r
+ case '4':\r
+ case '5':\r
+ case '6':\r
+ case '7':\r
+ case '8':\r
+ case '9': \r
+ ch = NumberMap[*c-0x30]; \r
+ break;\r
+ \r
+ default:\r
+ /* The character c is one letter in upper case*/\r
+ if ( (*c < 0x5b) && (*c > 0x40) )\r
+ {\r
+ ch = CapLetterMap[*c-'A'];\r
+ }\r
+ /* The character c is one letter in lower case*/\r
+ if ( (*c <0x7b) && ( *c> 0x60) )\r
+ {\r
+ ch = CapLetterMap[*c-'a'];\r
+ }\r
+ break;\r
+ }\r
+ \r
+ /* Set the digital point can be displayed if the point is on */\r
+ if (point)\r
+ {\r
+ ch |= 0x0002;\r
+ }\r
+\r
+ /* Set the "COL" segment in the character that can be displayed if the column is on */\r
+ if (column)\r
+ {\r
+ ch |= 0x0020;\r
+ } \r
+\r
+ for (i = 12,j=0 ;j<4; i-=4,j++)\r
+ {\r
+ digit[j] = (ch >> i) & 0x0f; //To isolate the less signifiant dibit\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD frame buffer.\r
+ * @param ch: the character to display.\r
+ * @param point: a point to add in front of char\r
+ * This parameter can be: POINT_OFF or POINT_ON\r
+ * @param column: flag indicating if a column has to be add in front\r
+ * of displayed character.\r
+ * This parameter can be: COLUMN_OFF or COLUMN_ON. \r
+ * @param position: position in the LCD of the caracter to write [0:7]\r
+ * @retval None\r
+ * @par Required preconditions: The LCD should be cleared before to start the\r
+ * write operation. \r
+ */\r
+void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column, uint8_t position)\r
+{\r
+ uint8_t digit[4]; /* Digit frame buffer */\r
+ \r
+/* To convert displayed character in segment in array digit */\r
+ LCD_Conv_Char_Seg(ch,point,column,digit);\r
+\r
+ \r
+ switch (position)\r
+ {\r
+ /* Position 1 on LCD (Digit1)*/\r
+ case 1:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xcffffffc;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 26 ) | (digit[0]& 0x03) ; // 1G 1B 1M 1E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 26 ) | (digit[1]& 0x03) ; // 1F 1A 1C 1D \r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 26 ) | (digit[2]& 0x03) ; // 1Q 1K 1Col 1P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 26 ) | (digit[3]& 0x03) ; // 1H 1J 1DP 1N\r
+\r
+ break;\r
+ \r
+ /* Position 2 on LCD (Digit2)*/\r
+ case 2:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xf3ffff03;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xf3ffff03; \r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xf3ffff03;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xf3ffff03;\r
+ \r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 24 )|((digit[0]& 0x02) << 6 )|((digit[0]& 0x01) << 2 ) ; // 2G 2B 2M 2E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 24 )|((digit[1]& 0x02) << 6 )|((digit[1]& 0x01) << 2 ) ; // 2F 2A 2C 2D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 24 )|((digit[2]& 0x02) << 6 )|((digit[2]& 0x01) << 2 ) ; // 2Q 2K 2Col 2P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 24 )|((digit[3]& 0x02) << 6 )|((digit[3]& 0x01) << 2 ) ; // 2H 2J 2DP 2N\r
+ \r
+ break;\r
+ \r
+ /* Position 3 on LCD (Digit3)*/\r
+ case 3:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfcfffcff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 22 ) | ((digit[0]& 0x03) << 8 ) ; // 3G 3B 3M 3E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 22 ) | ((digit[1]& 0x03) << 8 ) ; // 3F 3A 3C 3D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 22 ) | ((digit[2]& 0x03) << 8 ) ; // 3Q 3K 3Col 3P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 22 ) | ((digit[3]& 0x03) << 8 ) ; // 3H 3J 3DP 3N\r
+ \r
+ break;\r
+ \r
+ /* Position 4 on LCD (Digit4)*/\r
+ case 4:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xffcff3ff;\r
+ \r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 18 ) | ((digit[0]& 0x03) << 10 ) ; // 4G 4B 4M 4E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 18 ) | ((digit[1]& 0x03) << 10 ) ; // 4F 4A 4C 4D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 18 ) | ((digit[2]& 0x03) << 10 ) ; // 4Q 4K 4Col 4P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 18 ) | ((digit[3]& 0x03) << 10 ) ; // 4H 4J 4DP 4N\r
+ \r
+ break;\r
+ \r
+ /* Position 5 on LCD (Digit5)*/\r
+ case 5:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfff3cfff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfff3cfff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfff3efff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfff3efff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 16 ) | ((digit[0]& 0x03) << 12 ) ; // 5G 5B 5M 5E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 16 ) | ((digit[1]& 0x03) << 12 ) ; // 5F 5A 5C 5D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 16 ) | ((digit[2]& 0x01) << 12 ) ; // 5Q 5K 5P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 16 ) | ((digit[3]& 0x01) << 12 ) ; // 5H 5J 5N\r
+ \r
+ break;\r
+ \r
+ /* Position 6 on LCD (Digit6)*/\r
+ case 6:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfffc3fff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x04) << 15 ) | ((digit[0]& 0x08) << 13 ) | ((digit[0]& 0x03) << 14 ) ; // 6B 6G 6M 6E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x04) << 15 ) | ((digit[1]& 0x08) << 13 ) | ((digit[1]& 0x03) << 14 ) ; // 6A 6F 6C 6D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x04) << 15 ) | ((digit[2]& 0x08) << 13 ) | ((digit[2]& 0x01) << 14 ) ; // 6K 6Q 6P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x04) << 15 ) | ((digit[3]& 0x08) << 13 ) | ((digit[3]& 0x01) << 14 ) ; // 6J 6H 6N\r
+ \r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+/* Refresh LCD bar */\r
+ LCD_bar();\r
+\r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD RAM.\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_DisplayString(uint8_t* ptr)\r
+{\r
+ uint8_t i = 0x01;\r
+\r
+ /* wait for LCD Ready */ \r
+ while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
+ \r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr != 0) & (i < 8))\r
+ {\r
+ /* Display one character on LCD */\r
+ LCD_GLASS_WriteChar(ptr, FALSE, FALSE, i);\r
+\r
+ /* Point on the next character */\r
+ ptr++;\r
+\r
+ /* Increment the character counter */\r
+ i++;\r
+ }\r
+\r
+ /* Update the LCD display */\r
+ LCD_UpdateDisplayRequest();\r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD RAM.\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @retval None\r
+ * @par Required preconditions: Char is ASCCI value "Ored" with decimal point or Column flag\r
+ */\r
+void LCD_GLASS_DisplayStrDeci(uint16_t* ptr)\r
+{\r
+ uint8_t i = 0x01;\r
+ uint8_t char_tmp;\r
+\r
+ /* TO wait LCD Ready */ \r
+ while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
+ \r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr != 0) & (i < 8))\r
+ { \r
+ char_tmp = (*ptr) & 0x00ff;\r
+ \r
+ switch ((*ptr) & 0xf000)\r
+ {\r
+ case DOT:\r
+ /* Display one character on LCD with decimal point */\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_ON, COLUMN_OFF, i);\r
+ break;\r
+ case DOUBLE_DOT:\r
+ /* Display one character on LCD with decimal point */\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_ON, i);\r
+ break;\r
+ default:\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_OFF, i); \r
+ break;\r
+ }/* Point on the next character */\r
+ ptr++;\r
+ \r
+ /* Increment the character counter */\r
+ i++;\r
+ }\r
+ /* Update the LCD display */\r
+ LCD_UpdateDisplayRequest();\r
+}\r
+\r
+/**\r
+ * @brief This function Clear the whole LCD RAM.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_Clear(void)\r
+{\r
+ uint32_t counter = 0;\r
+ \r
+ /* TO wait LCD Ready */ \r
+ while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
+ \r
+ for (counter = LCD_RAMRegister_0; counter <= LCD_RAMRegister_15; counter++)\r
+ {\r
+ LCD->RAM[counter] = 0;\r
+ }\r
+\r
+ /* Update the LCD display */\r
+ LCD_UpdateDisplayRequest();\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Display a string in scrolling mode\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @param nScroll: Specifies how many time the message will be scrolled\r
+ * @param ScrollSpeed : Speciifes the speed of the scroll, low value gives\r
+ * higher speed \r
+ * @retval None\r
+ * @par Required preconditions: The LCD should be cleared before to start the\r
+ * write operation.\r
+ */\r
+void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)\r
+{\r
+ uint8_t Repetition;\r
+ uint8_t Char_Nb;\r
+ uint8_t* ptr1;\r
+ uint8_t str[7]="";\r
+ uint8_t Str_size;\r
+ \r
+ if (ptr == 0) return;\r
+\r
+/* To calculate end of string */\r
+ for (ptr1=ptr,Str_size = 0 ; *ptr1 != 0; Str_size++,ptr1++) ;\r
+ \r
+ ptr1 = ptr;\r
+ \r
+ LCD_GLASS_DisplayString(ptr);\r
+ Delay(ScrollSpeed);\r
+ \r
+/* To shift the string for scrolling display*/\r
+ for (Repetition=0; Repetition<nScroll; Repetition++)\r
+ {\r
+ for (Char_Nb=0; Char_Nb<Str_size; Char_Nb++)\r
+ {\r
+ *(str) =* (ptr1+((Char_Nb+1)%Str_size));\r
+ *(str+1) =* (ptr1+((Char_Nb+2)%Str_size));\r
+ *(str+2) =* (ptr1+((Char_Nb+3)%Str_size));\r
+ *(str+3) =* (ptr1+((Char_Nb+4)%Str_size));\r
+ *(str+4) =* (ptr1+((Char_Nb+5)%Str_size));\r
+ *(str+5) =* (ptr1+((Char_Nb+6)%Str_size));\r
+ LCD_GLASS_Clear();\r
+ LCD_GLASS_DisplayString(str);\r
+ \r
+ /* user button pressed stop the scrolling sentence */\r
+ if (KeyPressed)\r
+ return; \r
+ Delay(ScrollSpeed);\r
+ } \r
+ }\r
+\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file stm32l_discovery_lcd.h\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief This file contains all the functions prototypes for the glass LCD\r
+ * firmware driver.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __stm32l_discovery_lcd\r
+#define __stm32l_discovery_lcd\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h" \r
+#include "discover_board.h"\r
+\r
+/* Define for scrolling sentences*/\r
+#define SCROLL_SPEED 75\r
+#define SCROLL_SPEED_L 600\r
+#define SCROLL_NUM 1\r
+\r
+/* Define for character '.' */\r
+#define POINT_OFF FALSE\r
+#define POINT_ON TRUE\r
+\r
+/* Define for caracter ":" */\r
+#define COLUMN_OFF FALSE\r
+#define COLUMN_ON TRUE\r
+\r
+#define DOT 0x8000 /* for add decimal point in string */\r
+#define DOUBLE_DOT 0x4000 /* for add decimal point in string */\r
+\r
+\r
+/* =========================================================================\r
+ LCD MAPPING\r
+ =========================================================================\r
+ A\r
+ _ ----------\r
+COL |_| |\ |J /|\r
+ F| H | K |B\r
+ _ | \ | / |\r
+COL |_| --G-- --M--\r
+ | /| \ |\r
+ E| Q | N |C\r
+ _ | / |P \| \r
+DP |_| ----------- \r
+ D \r
+\r
+ An LCD character coding is based on the following matrix:\r
+ { E , D , P , N }\r
+ { M , C , COL , DP}\r
+ { B , A , K , J }\r
+ { G , F , Q , H }\r
+\r
+ The character 'A' for example is:\r
+ -------------------------------\r
+LSB { 1 , 0 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+MSB { 1 , 1 , 0 , 0 }\r
+ -------------------\r
+ 'A' = F E 0 0 hexa\r
+\r
+*/\r
+/* Macros used for set/reset bar LCD bar */\r
+#define BAR0_ON t_bar[1] |= 8\r
+#define BAR0_OFF t_bar[1] &= ~8\r
+#define BAR1_ON t_bar[0] |= 8\r
+#define BAR1_OFF t_bar[0] &= ~8\r
+#define BAR2_ON t_bar[1] |= 2\r
+#define BAR2_OFF t_bar[1] &= ~2\r
+#define BAR3_ON t_bar[0] |= 2 \r
+#define BAR3_OFF t_bar[0] &= ~2 \r
+\r
+/* code for 'µ' character */\r
+#define C_UMAP 0x6084\r
+\r
+/* code for 'm' character */\r
+#define C_mMap 0xb210\r
+\r
+/* code for 'n' character */\r
+#define C_nMap 0x2210\r
+\r
+/* constant code for '*' character */\r
+#define star 0xA0DD\r
+\r
+/* constant code for '-' character */\r
+#define C_minus 0xA000\r
+\r
+/* constant code for '/' */\r
+#define C_slatch 0x00c0\r
+\r
+/* constant code for ° */\r
+#define C_percent_1 0xec00\r
+\r
+/* constant code for small o */\r
+#define C_percent_2 0xb300\r
+\r
+#define C_full 0xffdd\r
+\r
+void LCD_bar(void);\r
+void LCD_GLASS_Init(void);\r
+void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column,uint8_t position);\r
+void LCD_GLASS_DisplayString(uint8_t* ptr);\r
+void LCD_GLASS_DisplayStrDeci(uint16_t* ptr);\r
+void LCD_GLASS_ClearChar(uint8_t position);\r
+void LCD_GLASS_Clear(void);\r
+void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);\r
+void LCD_GLASS_WriteTime(char a, uint8_t posi, bool column);\r
+void LCD_GLASS_Configure_GPIO(void);\r
+\r
+#endif /* stm32l_discovery_lcd*/\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file discover_board.h\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Input/Output defines\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+\r
+#ifndef __DISCOVER_BOARD_H\r
+#define __DISCOVER_BOARD_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h" \r
+\r
+#define bool _Bool\r
+#define FALSE 0\r
+#define TRUE !FALSE\r
+\r
+/* MACROs for SET, RESET or TOGGLE Output port */\r
+\r
+#define GPIO_HIGH(a,b) a->BSRRL = b\r
+#define GPIO_LOW(a,b) a->BSRRH = b\r
+#define GPIO_TOGGLE(a,b) a->ODR ^= b \r
+\r
+#define USERBUTTON_GPIO_PORT GPIOA\r
+#define USERBUTTON_GPIO_PIN GPIO_Pin_0\r
+#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+\r
+#define LD_GPIO_PORT GPIOB\r
+#define LD_GREEN_GPIO_PIN GPIO_Pin_7\r
+#define LD_BLUE_GPIO_PIN GPIO_Pin_6\r
+#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB\r
+\r
+#define CTN_GPIO_PORT GPIOC\r
+#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13\r
+#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+\r
+#define WAKEUP_GPIO_PORT GPIOA\r
+\r
+#define IDD_MEASURE_PORT GPIOA\r
+#define IDD_MEASURE GPIO_Pin_4\r
+\r
+#endif\r
+\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l_discovery_lcd.c\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief This file includes driver for the glass LCD Module mounted on \r
+ * STM32l discovery board MB963\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l_discovery_lcd.h"\r
+#include "discover_board.h"\r
+#include "stm32l1xx_lcd.h"\r
+#include "main.h"\r
+\r
+/* this variable can be used for accelerate the scrolling exit when push user button */\r
+volatile bool KeyPressed = FALSE; \r
+ \r
+/* LCD BAR status: We don't write directly in LCD RAM for save the bar setting */\r
+uint8_t t_bar[2]={0x0,0X0};\r
+ \r
+/* =========================================================================\r
+ LCD MAPPING\r
+ =========================================================================\r
+ A\r
+ _ ----------\r
+COL |_| |\ |J /|\r
+ F| H | K |B\r
+ _ | \ | / |\r
+COL |_| --G-- --M--\r
+ | /| \ |\r
+ E| Q | N |C\r
+ _ | / |P \| \r
+DP |_| ----------- \r
+ D \r
+\r
+ An LCD character coding is based on the following matrix:\r
+ { E , D , P , N }\r
+ { M , C , COL , DP}\r
+ { B , A , K , J }\r
+ { G , F , Q , H }\r
+\r
+ The character 'A' for example is:\r
+ -------------------------------\r
+LSB { 1 , 0 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+MSB { 1 , 1 , 0 , 0 }\r
+ -------------------\r
+ 'A' = F E 0 0 hexa\r
+\r
+*/\r
+\r
+/* Constant table for cap characters 'A' --> 'Z' */\r
+const uint16_t CapLetterMap[26]=\r
+ {\r
+ /* A B C D E F G H I */\r
+ 0xFE00,0x6714,0x1d00,0x4714,0x9d00,0x9c00,0x3f00,0xfa00,0x0014,\r
+ /* J K L M N O P Q R */\r
+ 0x5300,0x9841,0x1900,0x5a48,0x5a09,0x5f00,0xFC00,0x5F01,0xFC01,\r
+ /* S T U V W X Y Z */\r
+ 0xAF00,0x0414,0x5b00,0x18c0,0x5a81,0x00c9,0x0058,0x05c0\r
+ };\r
+\r
+/* Constant table for number '0' --> '9' */\r
+const uint16_t NumberMap[10]=\r
+ {\r
+ /* 0 1 2 3 4 5 6 7 8 9 */\r
+ 0x5F00,0x4200,0xF500,0x6700,0xEa00,0xAF00,0xBF00,0x04600,0xFF00,0xEF00\r
+ };\r
+\r
+static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column,uint8_t* digit);\r
+\r
+/**\r
+ * @brief Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_Init(void)\r
+{\r
+ LCD_InitTypeDef LCD_InitStruct;\r
+\r
+ \r
+ LCD_InitStruct.LCD_Prescaler = LCD_Prescaler_1;\r
+ LCD_InitStruct.LCD_Divider = LCD_Divider_31;\r
+ LCD_InitStruct.LCD_Duty = LCD_Duty_1_4;\r
+ LCD_InitStruct.LCD_Bias = LCD_Bias_1_3;\r
+ LCD_InitStruct.LCD_VoltageSource = LCD_VoltageSource_Internal;\r
+\r
+ \r
+ /* Initialize the LCD */\r
+ LCD_Init(&LCD_InitStruct);\r
+ \r
+ LCD_MuxSegmentCmd(ENABLE);\r
+ \r
+ /* To set contrast to mean value */\r
+ LCD_ContrastConfig(LCD_Contrast_Level_4);\r
+ \r
+ LCD_DeadTimeConfig(LCD_DeadTime_0);\r
+ LCD_PulseOnDurationConfig(LCD_PulseOnDuration_4);\r
+\r
+ /* Wait Until the LCD FCR register is synchronized */\r
+ LCD_WaitForSynchro();\r
+ \r
+ /* Enable LCD peripheral */\r
+ LCD_Cmd(ENABLE);\r
+ \r
+ /* Wait Until the LCD is enabled */\r
+ while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)\r
+ {\r
+ }\r
+ /*!< Wait Until the LCD Booster is ready */ \r
+ while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)\r
+ {\r
+ } \r
+\r
+ LCD_BlinkConfig(LCD_BlinkMode_Off,LCD_BlinkFrequency_Div32); \r
+ LCD_GLASS_Clear();\r
+}\r
+\r
+/**\r
+ * @brief To initialize the LCD pins\r
+ * @caller main\r
+ * @param None\r
+ * @retval None\r
+ */\r
+\r
+void LCD_GLASS_Configure_GPIO(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ \r
+/* Enable GPIOs clock */ \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
+ RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, ENABLE);\r
+\r
+ \r
+/* Configure Output for LCD */\r
+/* Port A */\r
+ GPIO_StructInit(&GPIO_InitStructure);\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOA, &GPIO_InitStructure);\r
+\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ; \r
+ \r
+/* Configure Output for LCD */\r
+/* Port B */ \r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \\r
+ | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOB, &GPIO_InitStructure);\r
+ \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ; \r
+ \r
+/* Configure Output for LCD */\r
+/* Port C*/ \r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \\r
+ | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOC, &GPIO_InitStructure); \r
+ \r
+\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ; \r
+\r
+/* Disable GPIOs clock */ \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
+ RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, DISABLE);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief LCD contrast setting min-->max-->min by pressing user button\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_contrast()\r
+{\r
+ uint32_t contrast ;\r
+ \r
+ /* To get the actual contrast value in register */\r
+ contrast = LCD->FCR & LCD_Contrast_Level_7;\r
+ \r
+ while ((GPIOC->IDR & USERBUTTON_GPIO_PIN) == 0x0)\r
+ {\r
+ contrast += LCD_Contrast_Level_1; \r
+ \r
+ if (contrast > LCD_Contrast_Level_7)\r
+ contrast=LCD_Contrast_Level_0;\r
+ \r
+ LCD_ContrastConfig(contrast);\r
+ Delay(100);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Setting bar on LCD, writes bar value in LCD frame buffer \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_bar()\r
+{\r
+ \r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xffff5fff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xffff5fff;\r
+/* bar1 bar3 */\r
+ LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(t_bar[0]<<12);\r
+ \r
+/*bar0 bar2 */\r
+ LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(t_bar[1]<<12);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Converts an ascii char to the a LCD digit.\r
+ * @param c: a char to display.\r
+ * @param point: a point to add in front of char\r
+ * This parameter can be: POINT_OFF or POINT_ON\r
+ * @param column : flag indicating if a column has to be add in front\r
+ * of displayed character.\r
+ * This parameter can be: COLUMN_OFF or COLUMN_ON.\r
+ * @param digit array with segment \r
+ * @retval None\r
+ */\r
+static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit)\r
+{\r
+ uint16_t ch = 0 ;\r
+ uint8_t i,j;\r
+ \r
+ switch (*c)\r
+ {\r
+ case ' ' : \r
+ ch = 0x00;\r
+ break;\r
+ \r
+ case '*':\r
+ ch = star;\r
+ break;\r
+ \r
+ case 'µ' :\r
+ ch = C_UMAP;\r
+ break;\r
+ \r
+ case 'm' :\r
+ ch = C_mMap;\r
+ break;\r
+ \r
+ case 'n' :\r
+ ch = C_nMap;\r
+ break; \r
+ \r
+ case '-' :\r
+ ch = C_minus;\r
+ break;\r
+ \r
+ case '/' :\r
+ ch = C_slatch;\r
+ break; \r
+ \r
+ case '°' :\r
+ ch = C_percent_1;\r
+ break; \r
+ case '%' :\r
+ ch = C_percent_2; \r
+ break;\r
+ case 255 :\r
+ ch = C_full;\r
+ break ;\r
+ \r
+ case '0':\r
+ case '1':\r
+ case '2':\r
+ case '3':\r
+ case '4':\r
+ case '5':\r
+ case '6':\r
+ case '7':\r
+ case '8':\r
+ case '9': \r
+ ch = NumberMap[*c-0x30]; \r
+ break;\r
+ \r
+ default:\r
+ /* The character c is one letter in upper case*/\r
+ if ( (*c < 0x5b) && (*c > 0x40) )\r
+ {\r
+ ch = CapLetterMap[*c-'A'];\r
+ }\r
+ /* The character c is one letter in lower case*/\r
+ if ( (*c <0x7b) && ( *c> 0x60) )\r
+ {\r
+ ch = CapLetterMap[*c-'a'];\r
+ }\r
+ break;\r
+ }\r
+ \r
+ /* Set the digital point can be displayed if the point is on */\r
+ if (point)\r
+ {\r
+ ch |= 0x0002;\r
+ }\r
+\r
+ /* Set the "COL" segment in the character that can be displayed if the column is on */\r
+ if (column)\r
+ {\r
+ ch |= 0x0020;\r
+ } \r
+\r
+ for (i = 12,j=0 ;j<4; i-=4,j++)\r
+ {\r
+ digit[j] = (ch >> i) & 0x0f; //To isolate the less signifiant dibit\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD frame buffer.\r
+ * @param ch: the character to display.\r
+ * @param point: a point to add in front of char\r
+ * This parameter can be: POINT_OFF or POINT_ON\r
+ * @param column: flag indicating if a column has to be add in front\r
+ * of displayed character.\r
+ * This parameter can be: COLUMN_OFF or COLUMN_ON. \r
+ * @param position: position in the LCD of the caracter to write [0:7]\r
+ * @retval None\r
+ * @par Required preconditions: The LCD should be cleared before to start the\r
+ * write operation. \r
+ */\r
+void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column, uint8_t position)\r
+{\r
+ uint8_t digit[4]; /* Digit frame buffer */\r
+ \r
+/* To convert displayed character in segment in array digit */\r
+ LCD_Conv_Char_Seg(ch,point,column,digit);\r
+\r
+ \r
+ switch (position)\r
+ {\r
+ /* Position 1 on LCD (Digit1)*/\r
+ case 1:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xcffffffc;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 26 ) | (digit[0]& 0x03) ; // 1G 1B 1M 1E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 26 ) | (digit[1]& 0x03) ; // 1F 1A 1C 1D \r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 26 ) | (digit[2]& 0x03) ; // 1Q 1K 1Col 1P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 26 ) | (digit[3]& 0x03) ; // 1H 1J 1DP 1N\r
+\r
+ break;\r
+ \r
+ /* Position 2 on LCD (Digit2)*/\r
+ case 2:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xf3ffff03;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xf3ffff03; \r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xf3ffff03;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xf3ffff03;\r
+ \r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 24 )|((digit[0]& 0x02) << 6 )|((digit[0]& 0x01) << 2 ) ; // 2G 2B 2M 2E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 24 )|((digit[1]& 0x02) << 6 )|((digit[1]& 0x01) << 2 ) ; // 2F 2A 2C 2D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 24 )|((digit[2]& 0x02) << 6 )|((digit[2]& 0x01) << 2 ) ; // 2Q 2K 2Col 2P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 24 )|((digit[3]& 0x02) << 6 )|((digit[3]& 0x01) << 2 ) ; // 2H 2J 2DP 2N\r
+ \r
+ break;\r
+ \r
+ /* Position 3 on LCD (Digit3)*/\r
+ case 3:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfcfffcff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 22 ) | ((digit[0]& 0x03) << 8 ) ; // 3G 3B 3M 3E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 22 ) | ((digit[1]& 0x03) << 8 ) ; // 3F 3A 3C 3D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 22 ) | ((digit[2]& 0x03) << 8 ) ; // 3Q 3K 3Col 3P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 22 ) | ((digit[3]& 0x03) << 8 ) ; // 3H 3J 3DP 3N\r
+ \r
+ break;\r
+ \r
+ /* Position 4 on LCD (Digit4)*/\r
+ case 4:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xffcff3ff;\r
+ \r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 18 ) | ((digit[0]& 0x03) << 10 ) ; // 4G 4B 4M 4E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 18 ) | ((digit[1]& 0x03) << 10 ) ; // 4F 4A 4C 4D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 18 ) | ((digit[2]& 0x03) << 10 ) ; // 4Q 4K 4Col 4P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 18 ) | ((digit[3]& 0x03) << 10 ) ; // 4H 4J 4DP 4N\r
+ \r
+ break;\r
+ \r
+ /* Position 5 on LCD (Digit5)*/\r
+ case 5:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfff3cfff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfff3cfff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfff3efff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfff3efff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 16 ) | ((digit[0]& 0x03) << 12 ) ; // 5G 5B 5M 5E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 16 ) | ((digit[1]& 0x03) << 12 ) ; // 5F 5A 5C 5D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 16 ) | ((digit[2]& 0x01) << 12 ) ; // 5Q 5K 5P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 16 ) | ((digit[3]& 0x01) << 12 ) ; // 5H 5J 5N\r
+ \r
+ break;\r
+ \r
+ /* Position 6 on LCD (Digit6)*/\r
+ case 6:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfffc3fff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x04) << 15 ) | ((digit[0]& 0x08) << 13 ) | ((digit[0]& 0x03) << 14 ) ; // 6B 6G 6M 6E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x04) << 15 ) | ((digit[1]& 0x08) << 13 ) | ((digit[1]& 0x03) << 14 ) ; // 6A 6F 6C 6D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x04) << 15 ) | ((digit[2]& 0x08) << 13 ) | ((digit[2]& 0x01) << 14 ) ; // 6K 6Q 6P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x04) << 15 ) | ((digit[3]& 0x08) << 13 ) | ((digit[3]& 0x01) << 14 ) ; // 6J 6H 6N\r
+ \r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+/* Refresh LCD bar */\r
+ LCD_bar();\r
+\r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD RAM.\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_DisplayString(uint8_t* ptr)\r
+{\r
+ uint8_t i = 0x01;\r
+\r
+ /* wait for LCD Ready */ \r
+ while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
+ \r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr != 0) & (i < 8))\r
+ {\r
+ /* Display one character on LCD */\r
+ LCD_GLASS_WriteChar(ptr, FALSE, FALSE, i);\r
+\r
+ /* Point on the next character */\r
+ ptr++;\r
+\r
+ /* Increment the character counter */\r
+ i++;\r
+ }\r
+\r
+ /* Update the LCD display */\r
+ LCD_UpdateDisplayRequest();\r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD RAM.\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @retval None\r
+ * @par Required preconditions: Char is ASCCI value "Ored" with decimal point or Column flag\r
+ */\r
+void LCD_GLASS_DisplayStrDeci(uint16_t* ptr)\r
+{\r
+ uint8_t i = 0x01;\r
+ uint8_t char_tmp;\r
+\r
+ /* TO wait LCD Ready */ \r
+ while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
+ \r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr != 0) & (i < 8))\r
+ { \r
+ char_tmp = (*ptr) & 0x00ff;\r
+ \r
+ switch ((*ptr) & 0xf000)\r
+ {\r
+ case DOT:\r
+ /* Display one character on LCD with decimal point */\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_ON, COLUMN_OFF, i);\r
+ break;\r
+ case DOUBLE_DOT:\r
+ /* Display one character on LCD with decimal point */\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_ON, i);\r
+ break;\r
+ default:\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_OFF, i); \r
+ break;\r
+ }/* Point on the next character */\r
+ ptr++;\r
+ \r
+ /* Increment the character counter */\r
+ i++;\r
+ }\r
+ /* Update the LCD display */\r
+ LCD_UpdateDisplayRequest();\r
+}\r
+\r
+/**\r
+ * @brief This function Clear the whole LCD RAM.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_Clear(void)\r
+{\r
+ uint32_t counter = 0;\r
+ \r
+ /* TO wait LCD Ready */ \r
+ while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
+ \r
+ for (counter = LCD_RAMRegister_0; counter <= LCD_RAMRegister_15; counter++)\r
+ {\r
+ LCD->RAM[counter] = 0;\r
+ }\r
+\r
+ /* Update the LCD display */\r
+ LCD_UpdateDisplayRequest();\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Display a string in scrolling mode\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @param nScroll: Specifies how many time the message will be scrolled\r
+ * @param ScrollSpeed : Speciifes the speed of the scroll, low value gives\r
+ * higher speed \r
+ * @retval None\r
+ * @par Required preconditions: The LCD should be cleared before to start the\r
+ * write operation.\r
+ */\r
+void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)\r
+{\r
+ uint8_t Repetition;\r
+ uint8_t Char_Nb;\r
+ uint8_t* ptr1;\r
+ uint8_t str[7]="";\r
+ uint8_t Str_size;\r
+ \r
+ if (ptr == 0) return;\r
+\r
+/* To calculate end of string */\r
+ for (ptr1=ptr,Str_size = 0 ; *ptr1 != 0; Str_size++,ptr1++) ;\r
+ \r
+ ptr1 = ptr;\r
+ \r
+ LCD_GLASS_DisplayString(ptr);\r
+ Delay(ScrollSpeed);\r
+ \r
+/* To shift the string for scrolling display*/\r
+ for (Repetition=0; Repetition<nScroll; Repetition++)\r
+ {\r
+ for (Char_Nb=0; Char_Nb<Str_size; Char_Nb++)\r
+ {\r
+ *(str) =* (ptr1+((Char_Nb+1)%Str_size));\r
+ *(str+1) =* (ptr1+((Char_Nb+2)%Str_size));\r
+ *(str+2) =* (ptr1+((Char_Nb+3)%Str_size));\r
+ *(str+3) =* (ptr1+((Char_Nb+4)%Str_size));\r
+ *(str+4) =* (ptr1+((Char_Nb+5)%Str_size));\r
+ *(str+5) =* (ptr1+((Char_Nb+6)%Str_size));\r
+ LCD_GLASS_Clear();\r
+ LCD_GLASS_DisplayString(str);\r
+ \r
+ /* user button pressed stop the scrolling sentence */\r
+ if (KeyPressed)\r
+ return; \r
+ Delay(ScrollSpeed);\r
+ } \r
+ }\r
+\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file stm32l_discovery_lcd.h\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief This file contains all the functions prototypes for the glass LCD\r
+ * firmware driver.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __stm32l_discovery_lcd\r
+#define __stm32l_discovery_lcd\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h" \r
+#include "discover_board.h"\r
+\r
+/* Define for scrolling sentences*/\r
+#define SCROLL_SPEED 75\r
+#define SCROLL_SPEED_L 600\r
+#define SCROLL_NUM 1\r
+\r
+/* Define for character '.' */\r
+#define POINT_OFF FALSE\r
+#define POINT_ON TRUE\r
+\r
+/* Define for caracter ":" */\r
+#define COLUMN_OFF FALSE\r
+#define COLUMN_ON TRUE\r
+\r
+#define DOT 0x8000 /* for add decimal point in string */\r
+#define DOUBLE_DOT 0x4000 /* for add decimal point in string */\r
+\r
+\r
+/* =========================================================================\r
+ LCD MAPPING\r
+ =========================================================================\r
+ A\r
+ _ ----------\r
+COL |_| |\ |J /|\r
+ F| H | K |B\r
+ _ | \ | / |\r
+COL |_| --G-- --M--\r
+ | /| \ |\r
+ E| Q | N |C\r
+ _ | / |P \| \r
+DP |_| ----------- \r
+ D \r
+\r
+ An LCD character coding is based on the following matrix:\r
+ { E , D , P , N }\r
+ { M , C , COL , DP}\r
+ { B , A , K , J }\r
+ { G , F , Q , H }\r
+\r
+ The character 'A' for example is:\r
+ -------------------------------\r
+LSB { 1 , 0 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+MSB { 1 , 1 , 0 , 0 }\r
+ -------------------\r
+ 'A' = F E 0 0 hexa\r
+\r
+*/\r
+/* Macros used for set/reset bar LCD bar */\r
+#define BAR0_ON t_bar[1] |= 8\r
+#define BAR0_OFF t_bar[1] &= ~8\r
+#define BAR1_ON t_bar[0] |= 8\r
+#define BAR1_OFF t_bar[0] &= ~8\r
+#define BAR2_ON t_bar[1] |= 2\r
+#define BAR2_OFF t_bar[1] &= ~2\r
+#define BAR3_ON t_bar[0] |= 2 \r
+#define BAR3_OFF t_bar[0] &= ~2 \r
+\r
+/* code for 'µ' character */\r
+#define C_UMAP 0x6084\r
+\r
+/* code for 'm' character */\r
+#define C_mMap 0xb210\r
+\r
+/* code for 'n' character */\r
+#define C_nMap 0x2210\r
+\r
+/* constant code for '*' character */\r
+#define star 0xA0DD\r
+\r
+/* constant code for '-' character */\r
+#define C_minus 0xA000\r
+\r
+/* constant code for '/' */\r
+#define C_slatch 0x00c0\r
+\r
+/* constant code for ° */\r
+#define C_percent_1 0xec00\r
+\r
+/* constant code for small o */\r
+#define C_percent_2 0xb300\r
+\r
+#define C_full 0xffdd\r
+\r
+void LCD_bar(void);\r
+void LCD_GLASS_Init(void);\r
+void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column,uint8_t position);\r
+void LCD_GLASS_DisplayString(uint8_t* ptr);\r
+void LCD_GLASS_DisplayStrDeci(uint16_t* ptr);\r
+void LCD_GLASS_ClearChar(uint8_t position);\r
+void LCD_GLASS_Clear(void);\r
+void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);\r
+void LCD_GLASS_WriteTime(char a, uint8_t posi, bool column);\r
+void LCD_GLASS_Configure_GPIO(void);\r
+\r
+#endif /* stm32l_discovery_lcd*/\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************\r
+;* File Name : startup_stm32l1xx_md.s\r
+;* Author : MCD Application Team\r
+;* Version : V1.1.1\r
+;* Date : 09-March-2012\r
+;* Description : STM32L1xx Ultra Low Power Medium-density Devices vector \r
+;* table for EWARM toolchain.\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == __iar_program_start,\r
+;* - Set the vector table entries with the exceptions ISR \r
+;* address.\r
+;* After Reset the Cortex-M3 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* \r
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+;* You may not use this file except in compliance with the License.\r
+;* You may obtain a copy of the License at:\r
+;* \r
+;* http://www.st.com/software_license_agreement_liberty_v2\r
+;* \r
+;* Unless required by applicable law or agreed to in writing, software \r
+;* distributed under the License is distributed on an "AS IS" BASIS, \r
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+;* See the License for the specific language governing permissions and\r
+;* limitations under the License.\r
+;* \r
+;*******************************************************************************/\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ EXTERN SystemInit \r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window Watchdog\r
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect\r
+ DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp\r
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup\r
+ DCD FLASH_IRQHandler ; FLASH\r
+ DCD RCC_IRQHandler ; RCC\r
+ DCD EXTI0_IRQHandler ; EXTI Line 0\r
+ DCD EXTI1_IRQHandler ; EXTI Line 1\r
+ DCD EXTI2_IRQHandler ; EXTI Line 2\r
+ DCD EXTI3_IRQHandler ; EXTI Line 3\r
+ DCD EXTI4_IRQHandler ; EXTI Line 4\r
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1\r
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2\r
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3\r
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4\r
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5\r
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6\r
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7\r
+ DCD ADC1_IRQHandler ; ADC1\r
+ DCD USB_HP_IRQHandler ; USB High Priority\r
+ DCD USB_LP_IRQHandler ; USB Low Priority\r
+ DCD DAC_IRQHandler ; DAC\r
+ DCD COMP_IRQHandler ; COMP through EXTI Line\r
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5\r
+ DCD LCD_IRQHandler ; LCD\r
+ DCD TIM9_IRQHandler ; TIM9\r
+ DCD TIM10_IRQHandler ; TIM10\r
+ DCD TIM11_IRQHandler ; TIM11\r
+ DCD TIM2_IRQHandler ; TIM2\r
+ DCD TIM3_IRQHandler ; TIM3\r
+ DCD TIM4_IRQHandler ; TIM4\r
+ DCD I2C1_EV_IRQHandler ; I2C1 Event\r
+ DCD I2C1_ER_IRQHandler ; I2C1 Error\r
+ DCD I2C2_EV_IRQHandler ; I2C2 Event\r
+ DCD I2C2_ER_IRQHandler ; I2C2 Error\r
+ DCD SPI1_IRQHandler ; SPI1\r
+ DCD SPI2_IRQHandler ; SPI2\r
+ DCD USART1_IRQHandler ; USART1\r
+ DCD USART2_IRQHandler ; USART2\r
+ DCD USART3_IRQHandler ; USART3\r
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10\r
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line\r
+ DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend\r
+ DCD TIM6_IRQHandler ; TIM6\r
+ DCD TIM7_IRQHandler ; TIM7\r
+ \r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+ \r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+ \r
+ \r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+ \r
+ \r
+ PUBWEAK MemManage_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+ B MemManage_Handler\r
+ \r
+ \r
+ PUBWEAK BusFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+ B BusFault_Handler\r
+ \r
+ \r
+ PUBWEAK UsageFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+ B UsageFault_Handler\r
+ \r
+ \r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+ \r
+ \r
+ PUBWEAK DebugMon_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+ B DebugMon_Handler\r
+ \r
+ \r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+ \r
+ \r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+ \r
+ \r
+ PUBWEAK WWDG_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+WWDG_IRQHandler\r
+ B WWDG_IRQHandler\r
+ \r
+ \r
+ PUBWEAK PVD_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+PVD_IRQHandler\r
+ B PVD_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TAMPER_STAMP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TAMPER_STAMP_IRQHandler\r
+ B TAMPER_STAMP_IRQHandler\r
+ \r
+ \r
+ PUBWEAK RTC_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+RTC_WKUP_IRQHandler\r
+ B RTC_WKUP_IRQHandler\r
+ \r
+ \r
+ PUBWEAK FLASH_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+FLASH_IRQHandler\r
+ B FLASH_IRQHandler\r
+ \r
+ \r
+ PUBWEAK RCC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+RCC_IRQHandler\r
+ B RCC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI0_IRQHandler\r
+ B EXTI0_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI1_IRQHandler\r
+ B EXTI1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI2_IRQHandler\r
+ B EXTI2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI3_IRQHandler\r
+ B EXTI3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI4_IRQHandler\r
+ B EXTI4_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel1_IRQHandler\r
+ B DMA1_Channel1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel2_IRQHandler\r
+ B DMA1_Channel2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel3_IRQHandler\r
+ B DMA1_Channel3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel4_IRQHandler\r
+ B DMA1_Channel4_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel5_IRQHandler\r
+ B DMA1_Channel5_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel6_IRQHandler\r
+ B DMA1_Channel6_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel7_IRQHandler\r
+ B DMA1_Channel7_IRQHandler\r
+ \r
+ \r
+ PUBWEAK ADC1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ADC1_IRQHandler\r
+ B ADC1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USB_HP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USB_HP_IRQHandler\r
+ B USB_HP_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USB_LP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USB_LP_IRQHandler\r
+ B USB_LP_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DAC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DAC_IRQHandler\r
+ B DAC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK COMP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+COMP_IRQHandler\r
+ B COMP_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI9_5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI9_5_IRQHandler\r
+ B EXTI9_5_IRQHandler\r
+ \r
+ \r
+ PUBWEAK LCD_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+LCD_IRQHandler\r
+ B LCD_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM9_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM9_IRQHandler\r
+ B TIM9_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM10_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM10_IRQHandler\r
+ B TIM10_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM11_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM11_IRQHandler\r
+ B TIM11_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM2_IRQHandler\r
+ B TIM2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM3_IRQHandler\r
+ B TIM3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM4_IRQHandler\r
+ B TIM4_IRQHandler\r
+ \r
+ \r
+ PUBWEAK I2C1_EV_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C1_EV_IRQHandler\r
+ B I2C1_EV_IRQHandler\r
+ \r
+ \r
+ PUBWEAK I2C1_ER_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C1_ER_IRQHandler\r
+ B I2C1_ER_IRQHandler\r
+ \r
+ \r
+ PUBWEAK I2C2_EV_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C2_EV_IRQHandler\r
+ B I2C2_EV_IRQHandler\r
+ \r
+ \r
+ PUBWEAK I2C2_ER_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C2_ER_IRQHandler\r
+ B I2C2_ER_IRQHandler\r
+ \r
+ \r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI1_IRQHandler\r
+ B SPI1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK SPI2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI2_IRQHandler\r
+ B SPI2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USART1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART1_IRQHandler\r
+ B USART1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USART2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART2_IRQHandler\r
+ B USART2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USART3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART3_IRQHandler\r
+ B USART3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI15_10_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI15_10_IRQHandler\r
+ B EXTI15_10_IRQHandler\r
+ \r
+ \r
+ PUBWEAK RTC_Alarm_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+RTC_Alarm_IRQHandler\r
+ B RTC_Alarm_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USB_FS_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USB_FS_WKUP_IRQHandler\r
+ B USB_FS_WKUP_IRQHandler\r
+ \r
+\r
+ PUBWEAK TIM6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM6_IRQHandler\r
+ B TIM6_IRQHandler\r
+ \r
+\r
+ PUBWEAK TIM7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM7_IRQHandler\r
+ B TIM7_IRQHandler \r
+\r
+ END\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32l1xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
+ * This file contains the system clock configuration for STM32L1xx Ultra\r
+ * Low Medium-density devices, and is generated by the clock configuration\r
+ * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls".\r
+ * \r
+ * 1. This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
+ * and Divider factors, AHB/APBx prescalers and Flash settings),\r
+ * depending on the configuration made in the clock xls tool. \r
+ * This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32l1xx_md.s" file.\r
+ * \r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution. \r
+ * \r
+ * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.\r
+ * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to\r
+ * configure the system clock before to branch to main program. \r
+ * \r
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
+ * function will do nothing and MSI still used as system clock source. User can \r
+ * add some code to deal with this issue inside the SetSysClock() function. \r
+ * \r
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define\r
+ * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or\r
+ * through PLL, and you are using different crystal you have to adapt the HSE\r
+ * value to your own configuration.\r
+ * \r
+ * 5. This file configures the system clock as follows: \r
+ *=============================================================================\r
+ * System Clock Configuration\r
+ *=============================================================================\r
+ * System clock source | HSI\r
+ *----------------------------------------------------------------------------- \r
+ * SYSCLK | 16000000 Hz\r
+ *----------------------------------------------------------------------------- \r
+ * HCLK | 16000000 Hz\r
+ *----------------------------------------------------------------------------- \r
+ * AHB Prescaler | 1\r
+ *----------------------------------------------------------------------------- \r
+ * APB1 Prescaler | 1\r
+ *----------------------------------------------------------------------------- \r
+ * APB2 Prescaler | 1\r
+ *----------------------------------------------------------------------------- \r
+ * HSE Frequency | 8000000 Hz\r
+ *----------------------------------------------------------------------------- \r
+ * PLL DIV | Not Used\r
+ *----------------------------------------------------------------------------- \r
+ * PLL MUL | Not Used\r
+ *----------------------------------------------------------------------------- \r
+ * VDD | 3.3 V\r
+ *----------------------------------------------------------------------------- \r
+ * Vcore | 1.8 V (Range 1)\r
+ *----------------------------------------------------------------------------- \r
+ * Flash Latency | 0 WS\r
+ *----------------------------------------------------------------------------- \r
+ * Require 48MHz for USB clock | Disabled\r
+ *----------------------------------------------------------------------------- \r
+ *=============================================================================\r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32L1xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32l1xx.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Defines\r
+ * @{\r
+ */\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */ \r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Variables\r
+ * @{\r
+ */\r
+uint32_t SystemCoreClock = 16000000;\r
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit (void)\r
+{\r
+ /*!< Set MSION bit */\r
+ RCC->CR |= (uint32_t)0x00000100;\r
+\r
+ /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+ RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+ \r
+ /*!< Reset HSION, HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+ /*!< Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+ /*!< Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+ \r
+ /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */\r
+ SetSysClock();\r
+\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI \r
+ * value as defined by the MSI range.\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ case 0x04: /* HSI used as system clock */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x08: /* HSE used as system clock */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x0C: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+ pllmul = PLLMulTable[(pllmul >> 18)];\r
+ plldiv = (plldiv >> 22) + 1;\r
+ \r
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+ if (pllsource == 0x00)\r
+ {\r
+ /* HSI oscillator clock selected as PLL clock entry */\r
+ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\r
+ }\r
+ else\r
+ {\r
+ /* HSE selected as PLL clock entry */\r
+ SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\r
+ }\r
+ break;\r
+ default: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ }\r
+ /* Compute HCLK clock frequency --------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK clock frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash \r
+ * settings.\r
+ * @note This function should be called only once the RCC clock configuration \r
+ * is reset to the default reset state (done in SystemInit() function). \r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSIStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+ /* Enable HSI */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSION);\r
+ \r
+ /* Wait till HSI is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSIStatus = RCC->CR & RCC_CR_HSIRDY;\r
+ } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));\r
+\r
+ if ((RCC->CR & RCC_CR_HSIRDY) != RESET)\r
+ {\r
+ HSIStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSIStatus = (uint32_t)0x00;\r
+ }\r
+ \r
+ if (HSIStatus == (uint32_t)0x01)\r
+ {\r
+ /* Flash 0 wait state */\r
+ FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+ \r
+ /* Disable Prefetch Buffer */\r
+ FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+ /* Disable 64-bit access */\r
+ FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+ \r
+\r
+ /* Power enable */\r
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+ \r
+ /* Select the Voltage Range 1 (1.8 V) */\r
+ PWR->CR = PWR_CR_VOS_0;\r
+ \r
+ \r
+ /* Wait Until the Voltage Regulator is ready */\r
+ while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+ {\r
+ }\r
+ \r
+ /* HCLK = SYSCLK /1*/\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ /* PCLK2 = HCLK /1*/\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK /1*/\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+ \r
+ /* Select HSI as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;\r
+\r
+ /* Wait till HSI is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* If HSI fails to start-up, the application will have wrong clock\r
+ configuration. User can add here some code to deal with this error */\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file discover_functions.c\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Discover demo functions\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+/* stm32l1xxx std peripheral drivers headers*/ \r
+#include "stm32l1xx_exti.h"\r
+#include "misc.h"\r
+\r
+/* touch sensing library headers*/ \r
+//#include "stm32_tsl_api.h" -- superseded\r
+//#include "stm32l15x_tsl_ct_acquisition.h" -- superseded\r
+#include "tsl.h"\r
+#include "tsl_user.h"\r
+/* discover application headers*/ \r
+#include "discover_board.h"\r
+#include "discover_functions.h"\r
+#include "stm32l_discovery_lcd.h"\r
+#include "icc_measure.h"\r
+ \r
+/*Variables placed in DataFlash */\r
+\r
+/* ADC converter value for Bias current value*/\r
+#if (defined ( __CC_ARM ))\r
+uint8_t Bias_Current __attribute__((at(0x08080000))); \r
+#elif (defined (__ICCARM__))\r
+uint8_t Bias_Current @ ".DataFlash" ; \r
+#elif (defined (__GNUC__))\r
+/* ADC converter value for Bias current value*/\r
+uint8_t Bias_Current __attribute__((section(".DataFlash")));\r
+#endif\r
+\r
+/* Flag for autotest placed in Data Flash for return from RESET after STANDBY */\r
+#if (defined ( __CC_ARM ))\r
+bool self_test __attribute__((at(0x08080004))); \r
+#elif (defined (__ICCARM__))\r
+bool self_test @ ".DataFlash" ;\r
+#elif (defined (__GNUC__))\r
+/* Flag for autotest placed in Data Flash for return from RESET after STANDBY */\r
+bool self_test __attribute__((section(".DataFlash")));\r
+#endif\r
+\r
+extern float Current_STBY;\r
+extern uint8_t t_bar[2];\r
+extern uint16_t Int_CurrentSTBY;\r
+\r
+/* Used for indicate that the automatic test is ON (set in interrupt handler).*/\r
+\r
+/* To indicate if user button function is actived*/\r
+bool UserButton ;\r
+/* Used for detect keypressed*/\r
+extern volatile bool KeyPressed;\r
+\r
+\r
+/**\r
+ * @brief automatic test for VDD \r
+ * @caller auto_test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void test_vdd(void)\r
+{\r
+ uint16_t vdd_test;\r
+ uint16_t Message[6];\r
+ \r
+ /* Display test name*/\r
+ LCD_GLASS_DisplayString(" VDD ");\r
+ DELAY;\r
+ /* get VDD voltage value */ \r
+ vdd_test = (int)Vref_measure();\r
+ DELAY;\r
+ /* Check if value is correct */ \r
+ if ((vdd_test>VCC_MAX) || (vdd_test<VCC_MIN))\r
+ {\r
+ /* if not correct stay in following infinit loop -- Press reset for exit */\r
+ while(1)\r
+ {\r
+ /* Display VDD ERROR message*/\r
+ LCD_GLASS_ScrollSentence("VDD ERROR ",1,SCROLL_SPEED); \r
+ DELAY;\r
+ /*convert vdd_test value in char and stor it into Message */\r
+ convert_into_char (vdd_test, Message);\r
+ /* Add unit and decimal point to Message */\r
+ Message[5] = 'V';\r
+ Message[4] = ' ';\r
+ Message[1] |= DOT; \r
+ Message[0] = ' ';\r
+ /*Display Message*/ \r
+ LCD_GLASS_DisplayStrDeci(Message); \r
+ DELAY;\r
+ DELAY; \r
+ }\r
+ }\r
+ /* Display VDD OK message*/\r
+ LCD_GLASS_DisplayString("VDD OK");\r
+ DELAY ;\r
+}\r
+\r
+/**\r
+ * @brief Automatic test current in Run Mode \r
+ * @caller auto_test\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+void test_icc_Run(void)\r
+{\r
+ uint16_t icc_test;\r
+ uint16_t Message[6];\r
+ \r
+ /* Display test name*/\r
+ LCD_GLASS_DisplayString("RUN ");\r
+ DELAY;\r
+ \r
+ /* get ICC current value in RUN mode*/ \r
+ icc_test = (int)Icc_RUN();\r
+ DELAY;\r
+ /* Check if value is correct */ \r
+ if ((icc_test>ICC_RUN_MAX) || (icc_test<ICC_RUN_MIN))\r
+ {\r
+ /* if not correct stay in following infinit loop -- Press reset for exit */\r
+ while (1)\r
+ {\r
+ KeyPressed = FALSE;\r
+ /* Display RUN ERROR message*/\r
+ LCD_GLASS_ScrollSentence("RUN ERROR ",1,SCROLL_SPEED); \r
+ DELAY;\r
+ /*convert icc_test value in char and stor it into tab */\r
+ convert_into_char((uint32_t)(icc_test), Message);\r
+ /* Add unit and decimal point to Message */\r
+ Message[5] = 'A';\r
+ Message[4] = 'm';\r
+ Message[3] = ' ';\r
+ Message[0] |= DOT;\r
+ /*Display Message*/ \r
+ LCD_GLASS_DisplayStrDeci(Message);\r
+ DELAY;\r
+ DELAY;\r
+ }\r
+ }\r
+ /* Display RUN OK message*/\r
+ LCD_GLASS_DisplayString("RUN OK");\r
+ DELAY;\r
+}\r
+\r
+/**\r
+ * @brief Automatic test bias value\r
+ * @caller auto_test\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+void test_Bias(void)\r
+{\r
+ float Current = 0;\r
+ /* Display test name*/\r
+ LCD_GLASS_DisplayString("BIAS ");\r
+ DELAY;\r
+ /* Get operational amplifier BIAS current value*/ \r
+ Current = Bias_Current * Vdd_appli()/ADC_CONV; \r
+ Current *= 20L;\r
+ display_MuAmp((uint32_t)Current);\r
+ DELAY;\r
+ /* Check if value is correct */ \r
+ if ((Bias_Current > ICC_BIAS_MAX) || (Bias_Current == 0 ))\r
+ {\r
+ /* if not correct stay in following infinit loop */\r
+ while (1)\r
+ {\r
+ KeyPressed = FALSE;\r
+ /* Display BIAS ERROR message and BIAS current*/\r
+ LCD_GLASS_ScrollSentence("BIAS ERROR ",1,SCROLL_SPEED);\r
+ DELAY;\r
+ display_MuAmp((uint32_t)Current);\r
+ DELAY;\r
+ DELAY;\r
+ }\r
+ }\r
+ /* Display BIAS OK message*/\r
+ LCD_GLASS_DisplayString("BIASOK");\r
+ DELAY;\r
+}\r
+\r
+/**\r
+ * @brief Automatic test current in STOP Mode\r
+ * @caller auto_test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void test_icc_STOP(void)\r
+{\r
+ uint16_t icc_test;\r
+ /* Display test name*/\r
+ LCD_GLASS_DisplayString("STOP ");\r
+ DELAY;\r
+ \r
+ /* Get operational Icc current value in Stop mode no RTC*/ \r
+ icc_test = (int)Icc_Stop_NoRTC();\r
+ DELAY;\r
+ /* Test if value is correct */\r
+ if ((icc_test>ICC_STOP_MAX) || (icc_test<ICC_STOP_MIN))\r
+ {\r
+ /* if not correct stay in following infinite loop */\r
+ while (1)\r
+ {\r
+ KeyPressed = FALSE;\r
+ /* Display ICC STOP ERROR message*/\r
+ LCD_GLASS_ScrollSentence("ICC STOP ERROR ",1,SCROLL_SPEED);\r
+ DELAY;\r
+ /* Display ICC STOPvalue*/\r
+ display_MuAmp((uint32_t)icc_test);\r
+ DELAY;\r
+ DELAY;\r
+ }\r
+ }\r
+ /* Display STOP OK message*/\r
+ LCD_GLASS_DisplayString("STOPOK");\r
+ DELAY;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Automatic test current in STBY Mode\r
+ * @caller auto_test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void test_icc_STBY(void)\r
+{\r
+ /* Display test name*/\r
+ LCD_GLASS_DisplayString("STBY ");\r
+ DELAY;\r
+ /* Current value measured in Standby mode*/ \r
+ ADC_Icc_Test(MCU_STBY);\r
+ /* No Return software reset performed in ADC_Icc_Test function */\r
+}\r
+\r
+/**\r
+ * @brief Run auto test\r
+ * @caller main \r
+ * @param None\r
+ * @retval None\r
+ */ \r
+void auto_test(void)\r
+{\r
+ uint16_t tab[6]={0x20,0x20,0x20,0x20,0x20,0x20};\r
+ \r
+ AUTOTEST(TRUE) ;\r
+ \r
+ /* Switch off leds*/\r
+ GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);\r
+ \r
+ /* reset LCD bar indicator*/\r
+ BAR0_OFF;\r
+ BAR1_OFF;\r
+ BAR2_OFF;\r
+ BAR3_OFF;\r
+ \r
+ /* To display version */\r
+ LCD_GLASS_DisplayString(" TEST ");\r
+ DELAY;\r
+ STR_VERSION;\r
+ LCD_GLASS_DisplayStrDeci(tab);\r
+ DELAY;\r
+ DELAY;\r
+ \r
+ /* And launch the tests*/\r
+ test_vdd();\r
+ test_icc_Run();\r
+ test_Bias();\r
+ test_icc_STOP();\r
+ test_icc_STBY();\r
+ \r
+ /* Infinite loop: Press reset button at the end of test for exit*/\r
+ while (1)\r
+ {\r
+ LCD_GLASS_ScrollSentence("TEST OK ",1,SCROLL_SPEED);\r
+ KeyPressed = FALSE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Second part of Run auto test (run after sw reset)\r
+ * @caller main after RESET \r
+ * @param None\r
+ * @retval None\r
+ */ \r
+void auto_test_part2(void)\r
+{\r
+ float Current_STBY;\r
+ \r
+ /* Substract operational amplifier bias current from mesured standby current*/\r
+ if ( Int_CurrentSTBY > Bias_Current )\r
+ Int_CurrentSTBY -= Bias_Current;\r
+ /* convert value in uA */ \r
+ Current_STBY = Int_CurrentSTBY * Vdd_appli()/ADC_CONV; \r
+ Current_STBY *= 20L;\r
+ /*Display Standby Icc current value*/\r
+ display_MuAmp((uint32_t)Current_STBY);\r
+ DELAY;\r
+ /* Test if value is correct */\r
+ if ((Current_STBY > ICC_STBY_MAX) || (Current_STBY < ICC_STBY_MIN))\r
+ {\r
+ /* if not correct stay in following infinite loop */\r
+ while (1)\r
+ {\r
+ KeyPressed = FALSE;\r
+ /* Display ICC STBY error message */ \r
+ LCD_GLASS_ScrollSentence("ICC STBY ERROR ",1,SCROLL_SPEED); \r
+ DELAY;\r
+ /* Display ICC STBY current */\r
+ display_MuAmp((uint32_t)Current_STBY);\r
+ DELAY;\r
+ DELAY;\r
+ }\r
+ }\r
+ /* Display ICC STBY test OK*/ \r
+ LCD_GLASS_DisplayString("STBYOK");\r
+ DELAY; \r
+ \r
+ /* Infinite loop: Press reset button at the end of autotest to restart application*/\r
+ while (1)\r
+ {\r
+ LCD_GLASS_ScrollSentence("TEST OK ",1,SCROLL_SPEED);\r
+ KeyPressed = FALSE;\r
+ }\r
+}\r
+/**\r
+ * @brief Measures the BIAS current PJ1 Must be on OFF position\r
+ * @caller main \r
+ * @param None\r
+ * @retval None\r
+ */ \r
+void Bias_measurement(void)\r
+{\r
+ float Current;\r
+ uint16_t MeasurINT;\r
+ /* indicate that applicartion run in ** BIAS CURRENT ** mode */\r
+ LCD_GLASS_ScrollSentence(" ** BIAS CURRENT ** JP1 OFF **",1,SCROLL_SPEED); \r
+ \r
+ /* Get operational amplifier Bias current value */\r
+ MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);\r
+ \r
+ /* convert mesured value in uA*/\r
+ Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
+ Current *= 20L;\r
+ \r
+ /*display bias current value */\r
+ display_MuAmp((uint32_t)Current);\r
+\r
+ /* unlock E²Prom write access*/\r
+ DATA_EEPROM_Unlock();\r
+ \r
+ /* Store the value in E²Prom for application needs*/\r
+ DATA_EEPROM_FastProgramByte((uint32_t)&Bias_Current, MeasurINT) ;\r
+ \r
+ /* Lock back E²PROM write access */\r
+ DATA_EEPROM_Lock(); \r
+ \r
+ /* Infinite loop: BIAS current display -- Press reset button in order to restart application*/\r
+ while (1) \r
+ { \r
+ /* Get operational amplifier Bias current value */\r
+ MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);\r
+ /* convert mesured value in uA*/\r
+ Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
+ Current *= 20L;\r
+ /*display bias current value */\r
+ display_MuAmp((uint32_t)Current);\r
+ Delay(800) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief converts a 32bit unsined int into ASCII \r
+ * @caller several callers for display values\r
+ * @param Number digit to displays\r
+ * p_tab values in array in ASCII \r
+ * @retval None\r
+ */ \r
+void convert_into_char(uint32_t number, uint16_t *p_tab)\r
+{\r
+ uint16_t units=0, tens=0, hundreds=0, thousands=0, misc=0;\r
+ \r
+ units = (((number%10000)%1000)%100)%10;\r
+ tens = ((((number-units)/10)%1000)%100)%10;\r
+ hundreds = (((number-tens-units)/100))%100%10;\r
+ thousands = ((number-hundreds-tens-units)/1000)%10;\r
+ misc = ((number-thousands-hundreds-tens-units)/10000);\r
+ \r
+ *(p_tab+4) = units + 0x30;\r
+ *(p_tab+3) = tens + 0x30;\r
+ *(p_tab+2) = hundreds + 0x30;\r
+ *(p_tab+1) = thousands + 0x30;\r
+ *(p_tab) = misc + 0x30;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Function to return the VDD measurement\r
+ * @caller All measurements: VDD display or Current\r
+ *\r
+ * Method for VDD measurement:\r
+ * The VREFINT is not stored in memory.\r
+ * In this case:\r
+ * Vdd_appli = (Theorical_Vref/Vref mesure) * ADC_Converter\r
+ * Theorical_Vref = 1.224V\r
+ * ADC_Converter 4096\r
+ * ---> LSBIdeal = VREF/4096 or VDA/4096\r
+ * @param None \r
+ * @retval VDD measurements\r
+ */\r
+float Vdd_appli(void)\r
+{\r
+ uint16_t MeasurINT ;\r
+\r
+ float f_Vdd_appli ;\r
+ \r
+ /*Read the BandGap value on ADC converter*/\r
+ MeasurINT = ADC_Supply(); \r
+ \r
+ /* We use the theorical value */\r
+ f_Vdd_appli = (VREF/MeasurINT) * ADC_CONV;\r
+\r
+ /* convert Vdd_appli into mV */ \r
+ f_Vdd_appli *= 1000L;\r
+ \r
+ return f_Vdd_appli;\r
+}\r
+\r
+/**\r
+ * @brief Function to measure VDD\r
+ * @caller main\r
+ * @param None \r
+ * @retval Vdd value in mV\r
+ */\r
+uint16_t Vref_measure(void)\r
+{\r
+ uint16_t tab[6]; \r
+ uint16_t Vdd_mV ;\r
+ \r
+ Vdd_mV = (uint16_t)Vdd_appli();\r
+\r
+ convert_into_char (Vdd_mV, tab);\r
+ \r
+ /* To add unit and decimal point */\r
+ tab[5] = 'V';\r
+ tab[4] = ' ';\r
+ tab[1] |= DOT; /* To add decimal point for display in volt */\r
+ tab[0] = ' ';\r
+ \r
+ LCD_GLASS_DisplayStrDeci(tab);\r
+\r
+ return Vdd_mV;\r
+}\r
+\r
+/**\r
+ * @brief funtion to display the current in µA\r
+ * @caller several funcions\r
+ * @param Current value.\r
+ * @retval none\r
+ */ \r
+void display_MuAmp (uint32_t Current)\r
+{\r
+ uint16_t tab[6];\r
+ \r
+ convert_into_char(Current, tab);\r
+ tab[5] = 'A';\r
+ tab[4] = 'µ';\r
+ \r
+/* Test the significant digit for displays 3 or 4 digits*/\r
+ if ( tab[0] != '0')\r
+ {\r
+ tab[1] |= DOT; /* To add decimal point */\r
+ } else {\r
+ /* To shift for suppress '0' before decimal */\r
+ tab[0] = tab[1] ; \r
+ tab[0] |= DOT ;\r
+ tab[1] = tab[2] ;\r
+ tab[2] = tab[3] ; \r
+ tab[3] = ' ';\r
+ }\r
+ \r
+ LCD_GLASS_DisplayStrDeci(tab);\r
+}\r
+\r
+/**\r
+ * @brief funtion Current measurement in RUN mode\r
+ * @caller main and test_icc_RUN\r
+ * @param none\r
+ * @retval Current (mA)\r
+ */ \r
+float Icc_RUN(void)\r
+{\r
+ float Current;\r
+ uint16_t MeasurINT;\r
+ uint16_t tab[6]; \r
+ /* Get Icc current value in Run mode*/ \r
+ MeasurINT = ADC_Icc_Test(MCU_RUN);\r
+ /* Convert value in mA*/ \r
+ Current = MeasurINT * Vdd_appli()/ADC_CONV;\r
+ Current *= 100L; \r
+ /* Convert value in ASCII and store it into tab*/\r
+ convert_into_char((uint32_t)(Current), tab);\r
+ /* Add unit and decimal point */\r
+ tab[5] = 'A';\r
+ tab[4] = 'm';\r
+ tab[3] = ' ';\r
+ tab[0] |= DOT; \r
+ /* Display mesured value */\r
+ LCD_GLASS_DisplayStrDeci(tab);\r
+ \r
+ return (Current);\r
+}\r
+\r
+/**\r
+ * @brief funtion Current measurement in SLEEP mode\r
+ * @caller main\r
+ * @param none\r
+ * @retval Current (mA)\r
+ */ \r
+float Icc_SLEEP(void)\r
+{\r
+ float Current;\r
+ uint16_t MeasurINT;\r
+ uint16_t tab[6]; \r
+ \r
+ /* Get Icc current value in Sleep mode*/ \r
+ MeasurINT = ADC_Icc_Test(MCU_SLEEP);\r
+ /* Substract operational amplifier bias current from value*/\r
+ Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
+ /* Convert value in mA*/ \r
+ Current *= 100L;\r
+ /* Convert value in ASCII and store it into tab*/\r
+ convert_into_char((uint32_t)(Current), tab);\r
+ /* Add unit and decimal point */\r
+ tab[5] = 'A';\r
+ tab[4] = 'm';\r
+ tab[3] = ' ';\r
+ tab[0] |= DOT; \r
+ /*Display mesured value */\r
+ LCD_GLASS_DisplayStrDeci(tab);\r
+ /* Return value in mA*/\r
+ return(Current);\r
+}\r
+\r
+/**\r
+ * @brief funtion Current measurement in Low power\r
+ * @caller main\r
+ * @param none\r
+ * @retval Current (uA)\r
+ */ \r
+float Icc_LPRUN(void)\r
+{\r
+ float Current;\r
+ uint16_t MeasurINT;\r
+\r
+ /* Get Icc current value in Low power mode*/\r
+ MeasurINT = ADC_Icc_Test(MCU_LP_RUN);\r
+ /* Substract operational amplifier bias current from value*/\r
+ if ( MeasurINT > Bias_Current )\r
+ MeasurINT -= Bias_Current;\r
+ /* Convert value in uA*/ \r
+ Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
+ Current *= 20L;\r
+ /* Display mesured value */\r
+ display_MuAmp((uint32_t)Current);\r
+ /* Return value in uA*/ \r
+ return(Current);\r
+}\r
+\r
+/**\r
+ * @brief funtion Current measurement in Low power\r
+ * @caller main\r
+ * @param none\r
+ * @retval Current (µA)\r
+ */ \r
+float Icc_LPSLEEP(void)\r
+{\r
+ float Current;\r
+ uint16_t MeasurINT;\r
+ /* Get Icc current value in Low power sleep mode*/\r
+ MeasurINT = ADC_Icc_Test(MCU_LP_SLEEP);\r
+ /* Substract operational amplifier bias current from value*/\r
+ if ( MeasurINT > Bias_Current )\r
+ MeasurINT -= Bias_Current;\r
+ /* Convert value in uA*/\r
+ Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
+ Current *= 20L;\r
+ /* Test if value is correct */\r
+ if ((int) Current<MAX_CURRENT)\r
+ {\r
+ /* if correct : Display mesured value */\r
+ display_MuAmp((uint32_t)Current);\r
+ } else{\r
+ /* if not correct : Display ERROR */\r
+ LCD_GLASS_Clear();\r
+ LCD_GLASS_DisplayString("Error");\r
+ }\r
+ /* Return value in uA*/\r
+ return(Current);\r
+}\r
+\r
+/**\r
+ * @brief funtion Current measurement in Stop mode with LCD ON\r
+ * @caller main and test_icc_LCD\r
+ * @param none\r
+ * @retval Current (µA)\r
+ */\r
+float Icc_STOP(void)\r
+{\r
+ float Current;\r
+ uint16_t MeasurINT;\r
+ \r
+ /* Get Icc current value in STOP mode*/ \r
+ MeasurINT = ADC_Icc_Test(MCU_STOP_RTC); \r
+ /* Substract operational amplifier bias current from value*/\r
+ if ( MeasurINT > Bias_Current )\r
+ MeasurINT -= Bias_Current;\r
+ /* Convert value in uA*/\r
+ Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
+ Current *= 20L; \r
+ /* test if value is correct */\r
+ if ((int) Current<MAX_CURRENT)\r
+ {\r
+ /* if correct : Display mesured value */\r
+ display_MuAmp((uint32_t)Current);\r
+ }\r
+ else\r
+ {\r
+ /* if not correct : Display error if not in autotest */\r
+ if (!self_test)\r
+ {\r
+ LCD_GLASS_Clear();\r
+ LCD_GLASS_DisplayString("Error");\r
+ }\r
+ }\r
+ /* Return value in uA*/\r
+ return (Current);\r
+}\r
+\r
+/**\r
+ * @brief funtion Current measurement in Stop mode with LCD OFF\r
+ * @caller main\r
+ * @param none\r
+ * @retval none\r
+ */\r
+float Icc_Stop_NoRTC(void)\r
+{\r
+ float Current;\r
+ uint16_t MeasurINT;\r
+ \r
+ /* Get Icc current value in STOP mode with no RTC */ \r
+ MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);\r
+ /* Substract operational amplifier bias current from value*/\r
+ if ( MeasurINT > Bias_Current )\r
+ MeasurINT -= Bias_Current;\r
+ /* Convert value in uA*/\r
+ Current = MeasurINT * Vdd_appli()/ADC_CONV; \r
+ Current *= 20L;\r
+ /* Display mesured value */ \r
+ display_MuAmp((uint32_t)Current);\r
+ /* Return value in uA*/\r
+ return (Current);\r
+} \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file icc_measure.c\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Current measurements\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */\r
+ \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+#include "stm32l1xx.h"\r
+#include "stm32l1xx_adc.h"\r
+#include "stm32l1xx_lcd.h"\r
+#include "stm32l1xx_rcc.h"\r
+#include "stm32l1xx_rtc.h"\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_gpio.h"\r
+#include "discover_board.h"\r
+#include "icc_measure.h"\r
+#include "discover_functions.h"\r
+#include "stm32l_discovery_lcd.h"\r
+#include "stm32l1xx_conf.h"\r
+\r
+/* Current measurment in RAM for Run mode and LPOWER run mode */\r
+#define TESTINRAM 1\r
+\r
+extern bool UserButton; /* Indicate if GPIO PA1 is used for user button instead of wake up signal */\r
+volatile bool Idd_WakeUP; /* Indicate Wake UP setted in IT handler */\r
+\r
+/* Variables used for save GPIO configuration */\r
+uint32_t GPIOA_MODER, GPIOB_MODER, GPIOC_MODER,GPIOD_MODER,GPIOE_MODER ,GPIOE_MODER,GPIOH_MODER;\r
+uint32_t GPIOA_PUPDR, GPIOB_PUPDR , GPIOC_PUPDR, GPIOD_PUPDR,GPIOE_PUPDR,GPIOH_PUPDR;\r
+\r
+/**\r
+ * @brief Function used to Configure the GPIO in low consumption\r
+ * @caller ADC_Icc_Test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void GPIO_LowPower_Config(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* store GPIO configuration before lowpower switch */\r
+ GPIOA_MODER = GPIOA->MODER;\r
+ GPIOB_MODER = GPIOB->MODER;\r
+ GPIOC_MODER = GPIOC->MODER;\r
+ GPIOD_MODER = GPIOD->MODER;\r
+ GPIOE_MODER = GPIOE->MODER;\r
+ GPIOH_MODER = GPIOH->MODER;\r
+ GPIOA_PUPDR = GPIOA->PUPDR;\r
+ GPIOB_PUPDR = GPIOB->PUPDR;\r
+ GPIOC_PUPDR = GPIOC->PUPDR;\r
+ GPIOD_PUPDR = GPIOD->PUPDR;\r
+ GPIOE_PUPDR = GPIOE->PUPDR;\r
+ GPIOH_PUPDR = GPIOH->PUPDR;\r
+ \r
+ /* Configure all GPIO port pins in Analog input mode (trigger OFF) */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_400KHz;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+\r
+ \r
+ GPIOD->MODER = 0xFFFFFFFF;\r
+ GPIOE->MODER = 0xFFFFFFFF;\r
+ GPIOH->MODER = 0xFFFFFFFF;\r
+ \r
+ /* all GPIOA */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6| GPIO_Pin_7 \\r
+ | GPIO_Pin_13 | GPIO_Pin_14|GPIO_Pin_5 | GPIO_Pin_8 |GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 |GPIO_Pin_15 ;\r
+\r
+ GPIO_Init(GPIOA, &GPIO_InitStructure); \r
+\r
+ /* All GPIOC except PC13 which is used for mesurement */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4| GPIO_Pin_5 |GPIO_Pin_6| GPIO_Pin_7| GPIO_Pin_8 \\r
+ | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 ;\r
+ GPIO_Init(GPIOC, &GPIO_InitStructure); \r
+\r
+ /* all GPIOB except PB6 and PB7 used for LED*/\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4| GPIO_Pin_5 | GPIO_Pin_8 \\r
+ | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 |GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15 ;\r
+ GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+ \r
+ \r
+ GPIO_LOW(GPIOB,GPIO_Pin_6);\r
+ GPIO_LOW(GPIOB,GPIO_Pin_7);\r
+}\r
+\r
+/**\r
+ * @brief To restore register values for GPIO.\r
+ * @caller ADC_Icc_Test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void Restore_GPIO_Config(void)\r
+{\r
+ GPIOA->MODER = GPIOA_MODER;\r
+ GPIOB->MODER = GPIOB_MODER;\r
+ GPIOC->MODER = GPIOC_MODER;\r
+ GPIOD->MODER = GPIOD_MODER;\r
+ GPIOE->MODER = GPIOE_MODER;\r
+ GPIOH->MODER = GPIOH_MODER;\r
+\r
+ GPIOA->PUPDR = GPIOA_PUPDR;\r
+ GPIOB->PUPDR = GPIOB_PUPDR;\r
+ GPIOC->PUPDR = GPIOC_PUPDR;\r
+ GPIOD->PUPDR = GPIOD_PUPDR;\r
+ GPIOE->PUPDR = GPIOE_PUPDR;\r
+ GPIOH->PUPDR = GPIOH_PUPDR;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the clock system\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void Config_Systick()\r
+{\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+ RCC_GetClocksFreq(&RCC_Clocks);\r
+ SysTick_Config(RCC_Clocks.HCLK_Frequency / 2000);\r
+}\r
+\r
+/**\r
+ * @brief Configures the clock system in low frequency\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void Config_Systick_50ms()\r
+{\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+ RCC_GetClocksFreq(&RCC_Clocks);\r
+ SysTick_Config(RCC_Clocks.HCLK_Frequency / 2);\r
+}\r
+\r
+/**\r
+ * @brief To select MSI as System clock source \r
+ * @caller ADC_Icc_Test\r
+ * @param Frequence, DIV by 2 ot not , With or without RTC\r
+ * @retval None\r
+ */\r
+void SetHSICLKToMSI(uint32_t freq,bool div2,bool With_RTC)\r
+{\r
+ \r
+ /* RCC system reset */\r
+ RCC_DeInit();\r
+\r
+ /* Flash no latency*/\r
+ FLASH_SetLatency(FLASH_Latency_0);\r
+ \r
+ /* Disable Prefetch Buffer */\r
+ FLASH_PrefetchBufferCmd(DISABLE);\r
+\r
+ /* Disable 64-bit access */\r
+ FLASH_ReadAccess64Cmd(DISABLE);\r
+ \r
+ /* Disable FLASH during SLeep */\r
+ FLASH_SLEEPPowerDownCmd(ENABLE);\r
+ \r
+ /* Enable the PWR APB1 Clock */\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);\r
+\r
+ /* Select the Voltage Range 3 (1.2V) */\r
+ PWR_VoltageScalingConfig(PWR_VoltageScaling_Range3);\r
+\r
+ /* Wait Until the Voltage Regulator is ready */\r
+ while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET);\r
+\r
+ /* Configure the MSI frequency */\r
+ RCC_MSIRangeConfig(freq);\r
+ \r
+ /* Select MSI as system clock source */\r
+ RCC_SYSCLKConfig(RCC_SYSCLKSource_MSI);\r
+\r
+ /* Wait until MSI is used as system clock source */\r
+ while (RCC_GetSYSCLKSource() != 0x00);\r
+\r
+ if (div2)\r
+ {\r
+ RCC_HCLKConfig(RCC_SYSCLK_Div2); \r
+ }\r
+\r
+ RCC_HSICmd(DISABLE);\r
+\r
+ /* Disable HSE clock */\r
+ RCC_HSEConfig(RCC_HSE_OFF);\r
+\r
+ /* Disable LSE clock */\r
+ if (! With_RTC)\r
+ RCC_LSEConfig(RCC_LSE_OFF);\r
+\r
+ /* Disable LSI clock */\r
+ RCC_LSICmd(DISABLE); \r
+\r
+}\r
+\r
+/**\r
+ * @brief To select HSI as System clock source \r
+ * @caller ADC_Icc_Test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SetHSICLK(void)\r
+{\r
+ /* Enable HSI Clock */\r
+ RCC_HSICmd(ENABLE);\r
+ \r
+ /*!< Wait till HSI is ready */\r
+ while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);\r
+ \r
+ /* Enable 64-bit access */\r
+ FLASH_ReadAccess64Cmd(ENABLE);\r
+ \r
+ /* Enable Prefetch Buffer */\r
+ FLASH_PrefetchBufferCmd(ENABLE);\r
+ \r
+ /* Flash 1 wait state */\r
+ FLASH_SetLatency(FLASH_Latency_1);\r
+ \r
+ RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);\r
+ \r
+ while (RCC_GetSYSCLKSource() != 0x04);\r
+ \r
+ RCC_HCLKConfig(RCC_SYSCLK_Div1); \r
+ /* PCLK2 = HCLK */\r
+ RCC_PCLK2Config(RCC_HCLK_Div1);\r
+\r
+ /* PCLK1 = HCLK */\r
+ RCC_PCLK1Config(RCC_HCLK_Div1); \r
+ \r
+}\r
+\r
+\r
+/**\r
+ * @brief ADC initialization (ADC_Channel_4)\r
+ * @caller main and ADC_Icc_Test\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+void ADC_Icc_Init(void)\r
+{\r
+ ADC_InitTypeDef ADC_InitStructure;\r
+\r
+/* Enable ADC clock */\r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+\r
+/* de-initialize ADC */\r
+ ADC_DeInit(ADC1);\r
+\r
+/* ADC configured as follow:\r
+ - NbrOfChannel = 1 - ADC_Channel_4\r
+ - Mode = Single ConversionMode(ContinuousConvMode disabled)\r
+ - Resolution = 12Bits\r
+ - Prescaler = /1\r
+ - sampling time 192 */\r
+\r
+ /* ADC Configuration */\r
+ ADC_StructInit(&ADC_InitStructure);\r
+ ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;\r
+ ADC_InitStructure.ADC_ScanConvMode = ENABLE;\r
+ ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;\r
+ ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r
+ ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;\r
+ ADC_InitStructure.ADC_NbrOfConversion = 1;\r
+ ADC_Init(ADC1, &ADC_InitStructure);\r
+\r
+ /* ADC1 regular channel4 configuration */\r
+ ADC_RegularChannelConfig(ADC1, ADC_Channel_4, 1, ADC_SampleTime_192Cycles);\r
+ ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze);\r
+\r
+ ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE);\r
+ \r
+ /* Enable ADC1 */\r
+ ADC_Cmd(ADC1, ENABLE);\r
+ \r
+ /* Wait until ADC1 ON status */\r
+ while (ADC_GetFlagStatus(ADC1, ADC_FLAG_ADONS) == RESET);\r
+}\r
+\r
+/**\r
+ * @brief To return the supply measurmeent\r
+ * @caller several functions\r
+ * @param None\r
+ * @retval ADC value\r
+ */ \r
+uint16_t ADC_Supply(void)\r
+{\r
+ uint8_t i;\r
+ uint16_t res;\r
+\r
+ /* Initializes ADC */\r
+ ADC_Icc_Init();\r
+ \r
+ ADC_TempSensorVrefintCmd(ENABLE);\r
+\r
+ /* ADC1 regular channel 17 for VREF configuration */\r
+ ADC_RegularChannelConfig(ADC1, ADC_Channel_17, 1, ADC_SampleTime_192Cycles);\r
+ \r
+ /* initialize result */\r
+ res = 0;\r
+ for(i=4; i>0; i--)\r
+ {\r
+ /* start ADC convertion by software */\r
+ ADC_SoftwareStartConv(ADC1);\r
+\r
+ /* wait until end-of-covertion */\r
+ while( ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == 0 );\r
+ /* read ADC convertion result */\r
+ res += ADC_GetConversionValue(ADC1);\r
+ }\r
+ \r
+ /* de-initialize ADC */\r
+ ADC_TempSensorVrefintCmd(DISABLE);\r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+ \r
+ return (res>>2);\r
+}\r
+\r
+/**\r
+ * @brief To confgure RCC for current measurmeent\r
+ * @caller ADC_Icc_Test\r
+ * @param Structure address for save the RCC configuration\r
+ * @retval None\r
+ */\r
+void Config_RCC(RCC_TypeDef *sav_RCC)\r
+{\r
+ /* Save the RCC configuration registers */\r
+ sav_RCC->AHBENR = RCC->AHBENR;\r
+ sav_RCC->APB1ENR = RCC->APB1ENR;\r
+ sav_RCC->APB2ENR = RCC->APB2ENR;\r
+ sav_RCC->AHBLPENR = RCC->AHBLPENR;\r
+ sav_RCC->APB1LPENR = RCC->APB1LPENR;\r
+ sav_RCC->APB2LPENR = RCC->APB2LPENR;\r
+ \r
+ /* Set low power configuration */\r
+ RCC->AHBENR = 0x05; // Ports A and C enable\r
+ RCC->AHBLPENR = 0x05; \r
+ RCC->APB1ENR = RCC_APB1ENR_PWREN; // PWR management enable \r
+ RCC->APB2ENR = 0;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Current measurement\r
+ * @caller main and ADC_Icc_Test\r
+ * @param None\r
+ * @retval ADC conversion value\r
+ */\r
+uint16_t Current_Measurement (void)\r
+{\r
+ uint16_t res,i;\r
+\r
+ /* re-start ADC chanel 24 for Current measurement */\r
+ ADC_Icc_Init(); \r
+\r
+ /* initialize result */\r
+ res = 0;\r
+\r
+ for(i=4; i>0; i--)\r
+ {\r
+ /* start ADC convertion by software */\r
+ ADC_SoftwareStartConv(ADC1);\r
+ \r
+ /* wait until end-of-covertion */\r
+ while( ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == 0 );\r
+ \r
+ /* read ADC convertion result */\r
+ res += ADC_GetConversionValue(ADC1);\r
+ }\r
+ \r
+ return (res>>2);\r
+}\r
+\r
+/**\r
+ * @brief Current measurement in different MCU modes:\r
+ * RUN/SLEEP/LowPower/STANDBY with/without RTC\r
+ * @caller main and ADC_Icc_Test\r
+ * @param MCU state\r
+ * @retval ADC value.\r
+ */\r
+uint16_t ADC_Icc_Test(uint8_t Mcu_State)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ uint16_t adc_measure;\r
+ uint32_t i;\r
+ RCC_TypeDef SavRCC;\r
+ /* Reset UserButton State */\r
+ UserButton = FALSE;\r
+ /* Start counter */\r
+ GPIO_HIGH(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);\r
+ /* Disable the RTC Wakeup Interrupt */\r
+ RTC_ITConfig(RTC_IT_WUT, DISABLE);\r
+ /* Disable LCD */\r
+ LCD_Cmd(DISABLE);\r
+ /* wait until LCD disable */\r
+ while (LCD_GetFlagStatus(LCD_FLAG_ENS) == SET);\r
+ /*Reset Idd-WakeUP flag*/\r
+ Idd_WakeUP = FALSE;\r
+ /* Set IO in lowpower configuration*/\r
+ GPIO_LowPower_Config(); \r
+ /*Disable fast wakeUp*/\r
+ PWR_FastWakeUpCmd(DISABLE);\r
+ \r
+/* Test MCU state for configuration */\r
+ switch (Mcu_State)\r
+ {\r
+ /* Run mode : Measurement Measurement performed with MSI 4 MHz without RTC*/ \r
+ case MCU_RUN:\r
+ /* switch on MSI clock */\r
+ SetHSICLKToMSI(RCC_MSIRange_6,NoDIV2,NoRTC) ; \r
+ /* shitch on MSI clock */\r
+ Config_RCC(&SavRCC); \r
+ SysTick->CTRL = 0; \r
+ RCC->APB1ENR = 0;\r
+\r
+ /* To run nops during measurement:\r
+ it's the best case for low current */ \r
+\r
+ for (i=0;i<0xffff;i++) {\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ }\r
+ \r
+ break;\r
+\r
+ /* SLEEP mode : Measurement performed with MSI 4 MHz without RTC in WFI mode*/\r
+ case MCU_SLEEP:\r
+ \r
+ SetHSICLKToMSI(RCC_MSIRange_6,NoDIV2,NoRTC) ; \r
+ Config_RCC(&SavRCC); \r
+ Config_Systick_50ms();\r
+ Delay(1);\r
+\r
+ /* Request Wait For Interrupt */\r
+ PWR_EnterSleepMode(PWR_Regulator_ON,PWR_SLEEPEntry_WFI); \r
+ \r
+ break; \r
+\r
+ /* RUN LOW POWER mode : Measurement performed with MSI 32 Khz without RTC */\r
+ case MCU_LP_RUN:\r
+ \r
+ /* Disable PVD */\r
+ PWR_PVDCmd(DISABLE);\r
+\r
+ /* Enable The ultra Low Power Mode */\r
+ PWR_UltraLowPowerCmd(ENABLE); \r
+\r
+ /* Save the RCC configuration registers */\r
+ Config_RCC(&SavRCC); \r
+ \r
+ /* Stop the sys tick in order to avoid IT */\r
+ SysTick->CTRL = 0; \r
+ \r
+#ifdef TESTINRAM \r
+ SetHSICLKToMSI(RCC_MSIRange_0,DIV2,NoRTC) ; \r
+ \r
+ PWR_EnterLowPowerRunMode(ENABLE);\r
+ while(PWR_GetFlagStatus(PWR_FLAG_REGLP) == RESET) ; \r
+\r
+ disableGlobalInterrupts();\r
+ EnterLPRUNModeRAM();\r
+ enableGlobalInterrupts(); \r
+#else \r
+ /* Swith in MSI 32KHz */\r
+ SetHSICLKToMSI(RCC_MSIRange_64KHz,DIV2,NoRTC) ; \r
+ \r
+ PWR_EnterLowPowerRunMode(ENABLE);\r
+ while(PWR_GetFlagStatus(PWR_FLAG_REGLP) == RESET) ; \r
+ \r
+ /* Launch the counter */\r
+ GPIO_LOW(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN); \r
+ \r
+ /* To run the nop during measurement:\r
+ it's the best case for low current\r
+ until counter reach detected by IT --> Idd_WakeUP */\r
+ do{\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP(); \r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP(); \r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP(); \r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP(); \r
+ } while (Idd_WakeUP == FALSE ); \r
+#endif \r
+ \r
+ PWR_EnterLowPowerRunMode(DISABLE);\r
+ while(PWR_GetFlagStatus(PWR_FLAG_REGLP) != RESET) ; \r
+ \r
+ break; \r
+ \r
+ /* SLEEP LOW POWER mode\r
+ Measurement done to MSI 32 Khz without RTC\r
+ */ \r
+ case MCU_LP_SLEEP:\r
+ \r
+ /* Disable PVD */\r
+ PWR_PVDCmd(DISABLE); \r
+ \r
+ /* Enable Ultra low power mode */\r
+ PWR_UltraLowPowerCmd(ENABLE);\r
+\r
+ \r
+ /* To save the RCC configuration registers */\r
+ Config_RCC(&SavRCC); \r
+ \r
+ /* To stop the sys tick for avoid IT */\r
+ SysTick->CTRL = 0; \r
+ \r
+ /* Swith in MSI 32KHz */\r
+ SetHSICLKToMSI(RCC_MSIRange_0,DIV2,NoRTC) ;\r
+\r
+#ifdef TESTINRAM\r
+ disableGlobalInterrupts();\r
+ EnterLPSLEEPModeRAM();\r
+ enableGlobalInterrupts();\r
+#else \r
+ /* Falling edge for start counter */ \r
+ GPIO_LOW(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);\r
+\r
+ /* Request Wait For Interrupt */ \r
+ PWR_EnterSleepMode(PWR_Regulator_LowPower,PWR_SLEEPEntry_WFI);\r
+#endif \r
+ break; \r
+ \r
+ /* STOP modes\r
+ Measurement done to MSI 32 Khz without or with RTC\r
+ */ \r
+ case MCU_STOP_NoRTC:\r
+ case MCU_STOP_RTC:\r
+\r
+ /* Disable PVD */\r
+ PWR_PVDCmd(DISABLE);\r
+ \r
+ /* Enable Ultra low power mode */\r
+ PWR_UltraLowPowerCmd(ENABLE); \r
+ \r
+ /* To save the RCC configuration registers */\r
+ Config_RCC(&SavRCC); \r
+\r
+ /* To stop the sys tick for avoid IT */\r
+ SysTick->CTRL = 0; \r
+ \r
+ /* Swith in MSI 32KHz */\r
+ if( Mcu_State == MCU_STOP_NoRTC )\r
+ SetHSICLKToMSI(RCC_MSIRange_0,DIV2,NoRTC) ;\r
+ else\r
+ SetHSICLKToMSI(RCC_MSIRange_0,DIV2,WITHRTC) ; \r
+\r
+ /* Falling edge for start counter */ \r
+ GPIO_LOW(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);\r
+ \r
+ /* Request Wait For Interrupt */ \r
+ PWR_EnterSTOPMode(PWR_Regulator_LowPower,PWR_STOPEntry_WFI); \r
+\r
+ break; \r
+ \r
+ /* Standby mode without RTC\r
+ Measurement done to MSI 32 Khz without RTC\r
+ */\r
+ case MCU_STBY:\r
+ \r
+ /* Disable PVD */\r
+ PWR_PVDCmd(DISABLE);\r
+ \r
+ /* Enable Ultra low power mode */\r
+ PWR_UltraLowPowerCmd(ENABLE);\r
+ \r
+ RTC_OutputTypeConfig(RTC_OutputType_PushPull);\r
+ RTC_OutputConfig(RTC_Output_WakeUp,RTC_OutputPolarity_High); \r
+ \r
+ /* To configure PC13 WakeUP output */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 ;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_400KHz; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOC, &GPIO_InitStructure); \r
+ \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource13,GPIO_AF_RTC_AF1) ;\r
+ Config_RCC(&SavRCC); \r
+ \r
+ SysTick->CTRL = 0; \r
+ \r
+ /* Swith in MSI 32KHz */\r
+ SetHSICLKToMSI(RCC_MSIRange_0,DIV2,NoRTC) ; \r
+ \r
+ PWR_WakeUpPinCmd(PWR_WakeUpPin_1,ENABLE);\r
+ \r
+ PWR_UltraLowPowerCmd(ENABLE); \r
+ \r
+ PWR_EnterSTANDBYMode();\r
+ /* Stop here WakeUp EXIT on RESET */\r
+ \r
+ break;\r
+ }\r
+ \r
+ SetHSICLK(); \r
+\r
+ Config_Systick(); \r
+ RCC->AHBENR = SavRCC.AHBENR; \r
+ \r
+ PWR_VoltageScalingConfig(PWR_VoltageScaling_Range1);\r
+ /* Wait Until the Voltage Regulator is ready */\r
+ while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET) ;\r
+\r
+ /* Read ADC for current measurmeent */\r
+ adc_measure = Current_Measurement();\r
+ \r
+ /* ICC_CNT_EN Hi */\r
+ GPIO_HIGH(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);\r
+ UserButton = TRUE;\r
+\r
+ /* To restore RCC registers */\r
+ RCC->APB1ENR = SavRCC.APB1ENR;\r
+ RCC->APB2ENR = SavRCC.APB2ENR; \r
+ RCC->AHBLPENR = SavRCC.AHBLPENR; \r
+ RCC->APB1LPENR = SavRCC.APB1LPENR;\r
+ RCC->APB2LPENR = SavRCC.APB2LPENR;\r
+ \r
+ /* Need to reinit RCC for LCD*/\r
+ RCC_Configuration();\r
+\r
+ PWR_EnterLowPowerRunMode(DISABLE);\r
+ \r
+ /* Disable Ultra low power mode */\r
+ PWR_UltraLowPowerCmd(DISABLE);\r
+ \r
+ /* Disable FLASH during SLeep LP */\r
+ FLASH_SLEEPPowerDownCmd(DISABLE);\r
+ \r
+ Restore_GPIO_Config(); \r
+ \r
+ /* Clear Wake Up flag */\r
+ PWR_ClearFlag(PWR_FLAG_WU);\r
+ \r
+ /* Enable PVD */\r
+ PWR_PVDCmd(ENABLE);\r
+\r
+ LCD_GLASS_Init();\r
+ \r
+ return (adc_measure);\r
+}\r
+\r
+\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file icc_measure_Ram.c\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Ram functions used for ICC current measurments\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */\r
+ \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+#include "stm32l1xx.h"\r
+#include "stm32l1xx_adc.h"\r
+#include "stm32l1xx_lcd.h"\r
+#include "stm32l1xx_rcc.h"\r
+#include "stm32l1xx_rtc.h"\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_gpio.h"\r
+#include "discover_board.h"\r
+#include "icc_measure.h"\r
+#include "discover_functions.h"\r
+#include "stm32l1xx_conf.h"\r
+\r
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
+\r
+\r
+#if (defined ( __CC_ARM ))\r
+ #define __RAMFUNC void \r
+#elif (defined (__ICCARM__))\r
+ #define __RAMFUNC __ramfunc void\r
+#elif defined ( __GNUC__ )\r
+#define __RAMFUNC void __attribute__((section(".data")))\r
+#endif\r
+/**\r
+ * @brief Enable or disable the power down mode during RUN mode .\r
+ * @param NewState: new state of the power down mode during RUN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+__RAMFUNC RAM_FLASH_RUNPowerDownCmd(FunctionalState NewState)\r
+{\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Unlock the RUN_PD bit */\r
+ FLASH->PDKEYR = FLASH_PDKEY1;\r
+ FLASH->PDKEYR = FLASH_PDKEY2;\r
+\r
+ /* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */\r
+ FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enters/Exits the Low Power Run mode.\r
+ * @param NewState: new state of the Low Power Run mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+__RAMFUNC RAM_PWR_LowPowerRunModeCmd(FunctionalState NewState)\r
+{\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ PWR->CR |= PWR_CR_LPSDSR;\r
+ PWR->CR |= PWR_CR_LPRUN;\r
+ }\r
+ else\r
+ {\r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN);\r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Function in RAM for Low Power RUN current measurment\r
+ * @caller ADC_Icc_Test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__RAMFUNC EnterLPRUNModeRAM(void)\r
+{\r
+ \r
+ RAM_FLASH_RUNPowerDownCmd(ENABLE);\r
+ RAM_PWR_LowPowerRunModeCmd(ENABLE);\r
+ \r
+ /* The application Run with delay */\r
+ GPIO_LOW(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);\r
+ \r
+ do{\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ __NOP(); __NOP(); __NOP(); __NOP();\r
+ } while((USERBUTTON_GPIO_PORT->IDR & USERBUTTON_GPIO_PIN) == 0);\r
+ \r
+ \r
+ RAM_FLASH_RUNPowerDownCmd(DISABLE);\r
+ RAM_PWR_LowPowerRunModeCmd(DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Function in RAM for Low Power Sleep current measurment \r
+ * @caller ADC_Icc_Test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__RAMFUNC EnterLPSLEEPModeRAM(void)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ RAM_FLASH_RUNPowerDownCmd(ENABLE);\r
+ RAM_PWR_LowPowerRunModeCmd(ENABLE);\r
+ \r
+ /* The application Run with delay */\r
+ GPIO_LOW(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);\r
+\r
+ /* Select the regulator state in Sleep mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+\r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator_LowPower;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+ \r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
+\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ \r
+ RAM_FLASH_RUNPowerDownCmd(DISABLE);\r
+ RAM_PWR_LowPowerRunModeCmd(DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Function in RAM for Sleep current measurment \r
+ * @caller ADC_Icc_Test\r
+ * @param None\r
+ * @retval None\r
+ */\r
+\r
+__RAMFUNC EnterSLEEPModeRAM(void)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ RAM_FLASH_RUNPowerDownCmd(ENABLE);\r
+ RAM_PWR_LowPowerRunModeCmd(ENABLE);\r
+ \r
+ /* Select the regulator state in Sleep mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+\r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator_LowPower;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+ \r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
+\r
+ \r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ \r
+ RAM_FLASH_RUNPowerDownCmd(DISABLE);\r
+ RAM_PWR_LowPowerRunModeCmd(DISABLE);\r
+}\r
+\r
+\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file discover_functions.h\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief This file contains measurement values and board\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __DISCOVER_FUNCTIONS_H\r
+#define __DISCOVER_FUNCTIONS_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h" \r
+\r
+#define DELAY Delay(150)\r
+#define TEMPO if(!KeyPressed) DELAY\r
+\r
+//#define SLIDER_DETECTED (sMCKeyInfo[0].Setting.b.DETECTED)\r
+//#define SLIDER_POSITION (sMCKeyInfo[0].UnScaledPosition)\r
+\r
+#define enableGlobalInterrupts() __set_PRIMASK(0);\r
+#define disableGlobalInterrupts() __set_PRIMASK(1);\r
+\r
+#define STR_VERSION tab[1] = 'V';tab[2] = '2'|DOT; tab[3] = '0'|DOT; tab[4] = '4'\r
+\r
+#define STATE_VREF 0\r
+#define STATE_SLIDER_VALUE 1\r
+#define STATE_SLIDER_BUTTON 2\r
+#define STATE_ICC_RUN 3\r
+#define STATE_ICC_LP_RUN 4\r
+#define STATE_ICC_STOP 5\r
+#define STATE_ICC_STBY 6\r
+\r
+#define MAX_STATE 7\r
+\r
+\r
+/* Theorically BandGAP 1.224volt */\r
+#define VREF 1.224L\r
+\r
+\r
+/*\r
+ ADC Converter \r
+ LSBIdeal = VREF/4096 or VDA/4096\r
+*/\r
+#define ADC_CONV 4096\r
+\r
+/*\r
+ VDD Factory for VREFINT measurement \r
+*/\r
+#define VDD_FACTORY 3.0L\r
+\r
+#define MAX_CURRENT 99999\r
+\r
+/* AUTO TEST VALUE */\r
+\r
+#define VCC_MIN 2920 /* nominal Vcc/Vdd is 2.99V, allow 2.5% lower - Vref can be ~2% lower than 1.225 */\r
+#define VCC_MAX 3100\r
+#define ICC_RUN_MIN 6000\r
+#define ICC_RUN_MAX 11000 /* typical ICC_RUN is ~0.9mA */\r
+#define ICC_STOP_MIN 250\r
+#define ICC_STOP_MAX 800 /* typical ICC_STOP is 0.6uA */\r
+#define ICC_BIAS_MAX 30 /* ! converter value in decimal ! --> 3.0volts/4036* 30 = 21 mV */\r
+\r
+#define ICC_STBY_MIN 150 /* typical ICC_STAND BY is 0.3 uA */\r
+#define ICC_STBY_MAX 450 \r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+#define AUTOTEST(a) DATA_EEPROM_Unlock(); DATA_EEPROM_FastProgramByte((uint32_t)&self_test,a ) ; DATA_EEPROM_Lock() \r
+ \r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+\r
+void Init_Port (void);\r
+void convert_into_char(uint32_t number, uint16_t *p_tab);\r
+void LPR_init(void);\r
+void Halt_Init(void);\r
+uint16_t Vref_measure(void);\r
+void Icc_measure(void);\r
+float Icc_RUN(void);\r
+float Icc_SLEEP(void);\r
+float Icc_LPRUN(void);\r
+float Icc_LPSLEEP(void);\r
+float Icc_STOP(void);\r
+float Icc_Stop_NoRTC(void);\r
+void Icc_STBY(void);\r
+float Icc_STBY_NoRTC(void);\r
+void auto_test(void);\r
+void Bias_measurement(void);\r
+void test_vdd(void);\r
+void test_icc_Run(void);\r
+void test_icc_STOP(void);\r
+void test_icc_STBY(void);\r
+void display_MuAmp (uint32_t);\r
+void FLASH_ProgramBias(uint8_t) ;\r
+float Vdd_appli(void);\r
+uint16_t wake_up_measurement (void);\r
+void RCC_Configuration(void);\r
+void Init_clocks(void);\r
+void Init_GPIOs (void);\r
+void TimingDelay_Decrement(void);\r
+void Delay(uint32_t nTime);\r
+void ExtraCode_StateMachine(void);\r
+void Config_Systick(void);\r
+void Config_Systick_50ms(void); \r
+void Button_value(void);\r
+void Slider_value(void);\r
+void auto_test_part2(void);\r
+\r
+#endif /* __DISCOVER_FUNCTIONS_H*/\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file icc_measure.h\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Current measurements defines\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __ICC_MEASURE_H\r
+#define __ICC_MEASURE_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+#define MCU_RUN 0\r
+#define MCU_SLEEP 1\r
+#define MCU_LP_RUN 2\r
+#define MCU_LP_SLEEP 3\r
+#define MCU_STOP_RTC 4\r
+#define MCU_STOP_NoRTC 5\r
+#define MCU_STBY 6\r
+\r
+#define NoRTC FALSE\r
+#define WITHRTC !NoRTC\r
+#define NoDIV2 FALSE\r
+#define DIV2 !NoDIV2\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+uint16_t ADC_Supply(void);\r
+void ADC_Icc_Init(void);\r
+uint16_t ADC_Icc_Test(uint8_t Mcu_State);\r
+void GPIO_LowPower_Config(void);\r
+void STOP_Init(void);\r
+void STBY_Init(void);\r
+uint16_t Current_Measurement(void);\r
+void EnterLPSLEEPModeRAM(void);\r
+void SetHSICLKToMSI(uint32_t ,bool ,bool );\r
+void EnterLPRUNModeRAM(void);\r
+#endif /* __ICC_MEASURE_H*/\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Project/STM32L1xx_StdPeriph_Template/main.h \r
+ * @author MCD Application Team\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Header for main.c module\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */ \r
+ \r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MAIN_H\r
+#define __MAIN_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+#include "discover_board.h"\r
+#include "stm32l_discovery_lcd.h"\r
+#include <stdio.h>\r
+\r
+/* Touch sensing driver headers */\r
+#include "tsl.h"\r
+#include "tsl_user.h"\r
+\r
+/* discovery board and specific drivers headers*/\r
+#include "discover_board.h"\r
+#include "icc_measure.h"\r
+#include "discover_functions.h"\r
+#include "stm32l_discovery_lcd.h"\r
+\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void Delay(__IO uint32_t nTime);\r
+\r
+#endif /* __MAIN_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_conf.h \r
+ * @author MCD Application Team\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Library configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_CONF_H\r
+#define __STM32L1xx_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Comment the line below to disable peripheral header file inclusion */\r
+#include "stm32l1xx_adc.h"\r
+#include "stm32l1xx_crc.h"\r
+#include "stm32l1xx_comp.h"\r
+#include "stm32l1xx_dac.h"\r
+#include "stm32l1xx_dbgmcu.h"\r
+#include "stm32l1xx_dma.h"\r
+#include "stm32l1xx_exti.h"\r
+#include "stm32l1xx_flash.h"\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_syscfg.h"\r
+#include "stm32l1xx_i2c.h"\r
+#include "stm32l1xx_iwdg.h"\r
+#include "stm32l1xx_lcd.h"\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_rcc.h"\r
+#include "stm32l1xx_rtc.h"\r
+#include "stm32l1xx_spi.h"\r
+#include "stm32l1xx_tim.h"\r
+#include "stm32l1xx_usart.h"\r
+#include "stm32l1xx_wwdg.h"\r
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Uncomment the line below to expanse the "assert_param" macro in the \r
+ Standard Peripheral Library drivers code */\r
+/* #define USE_FULL_ASSERT 1 */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function which reports \r
+ * the name of the source file and the source line number of the call \r
+ * that failed. If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#endif /* __STM32L1xx_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.h \r
+ * @author MCD Application Team\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief This file contains the headers of the interrupt handlers.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_IT_H\r
+#define __STM32L1xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+void EXTI0_IRQHandler(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_IT_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file STM32L152_Ex06_Linear_DISC\inc\tsl_conf_stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Acquisition parameters for STM32L1xx products.\r
+ * @note This file must be copied in the application project and values\r
+ * changed for the application.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_CONF_STM32L1xx_H\r
+#define __TSL_CONF_STM32L1xx_H\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup Common_Parameters Common Parameters\r
+ * @{ */\r
+\r
+//==============================================================================\r
+// Number of elements\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements\r
+ * @{ */\r
+\r
+/** Total number of channels in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_CHANNELS (3)\r
+\r
+/** Total number of banks in application (range=1..255)\r
+*/\r
+#define TSLPRM_TOTAL_BANKS (1)\r
+\r
+/** Total number of "Extended" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS (0)\r
+\r
+/** Total number of "Basic" TouchKeys in application (range=0..255)\r
+*/\r
+#define TSLPRM_TOTAL_TOUCHKEYS_B (0)\r
+\r
+/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS (1)\r
+\r
+/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)\r
+ - Count also the 1-channel linear sensor used as TouchKey\r
+*/\r
+#define TSLPRM_TOTAL_LINROTS_B (0)\r
+\r
+/** Total number of sensors/objects in application (range=1..255)\r
+ - Count all TouchKeys, Linear and Rotary sensors\r
+*/\r
+#define TSLPRM_TOTAL_OBJECTS (1)\r
+\r
+/** @} Common_Parameters_Number_Of_Elements */\r
+\r
+//==============================================================================\r
+// Optional features\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Options 02 - Optional features\r
+ * @{ */\r
+\r
+/** Record the last measure (0=No, 1=Yes)\r
+ - If No the measure is recalculated using the Reference and Delta\r
+*/\r
+#define TSLPRM_USE_MEAS (1)\r
+\r
+/** Zone management usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_ZONE (0)\r
+\r
+/** Proximity detection usage (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_PROX (0)\r
+\r
+/** Use the Timer tick callback (0=No, 1=Yes)\r
+ - When equal to 1, the function TSL_CallBack_TimerTick must be defined in\r
+ the application code. It is called for each timer interruption.\r
+*/\r
+#define TSLPRM_USE_TIMER_CALLBACK (0)\r
+\r
+/** Acquisition interrupt mode (0=No, 1=Yes)\r
+ - If No the TS interrupt is not used.\r
+ - If Yes the TS interrupt is used.\r
+*/\r
+#define TSLPRM_USE_ACQ_INTERRUPT (0)\r
+\r
+/** @} Common_Parameters_Options */\r
+\r
+//==============================================================================\r
+// Acquisition limits\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits\r
+ * @{ */\r
+\r
+/** Minimum acquisition measurement (range=0..65535)\r
+ - This is the minimum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is below this value.\r
+*/\r
+#define TSLPRM_ACQ_MIN (50)\r
+\r
+/** Maximum acquisition measurement (range=0..65535)\r
+ - This is the maximum acceptable value for the acquisition measure.\r
+ - The acquisition will be in error if the measure is above this value.\r
+*/\r
+#define TSLPRM_ACQ_MAX (4000)\r
+\r
+/** @} Common_Parameters_Acquisition_Limits */\r
+\r
+//==============================================================================\r
+// Calibration\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Calibration 04 - Calibration\r
+ * @{ */\r
+\r
+/** Number of calibration samples (range=4, 8, 16)\r
+ - Low value = faster calibration but less precision.\r
+ - High value = slower calibration but more precision.\r
+*/\r
+#define TSLPRM_CALIB_SAMPLES (8)\r
+\r
+/** Delay in measurement samples before starting the calibration (range=0..40)\r
+ - This is usefull if a noise filter is used.\r
+ - Write 0 to disable the delay.\r
+*/\r
+#define TSLPRM_CALIB_DELAY (10)\r
+\r
+/** @} Common_Parameters_Calibration */\r
+\r
+//==============================================================================\r
+// Thresholds for TouchKey sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors\r
+ * @{ */\r
+\r
+/** TouchKeys Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_PROX_IN_TH (20)\r
+\r
+/** TouchKeys Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_PROX_OUT_TH (15)\r
+\r
+/** TouchKeys Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_TKEY_DETECT_IN_TH (30)\r
+\r
+/** TouchKeys Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_DETECT_OUT_TH (25)\r
+\r
+/** TouchKeys re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+*/\r
+#define TSLPRM_TKEY_CALIB_TH (30)\r
+\r
+/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)\r
+ This multiplier coefficient is applied on Detect thresholds only.\r
+ - 0: feature disabled\r
+ - 1: thresholds x 2\r
+ - 2: thresholds x 4\r
+ - 3: thresholds x 8\r
+ - 4: thresholds x 16\r
+*/\r
+#define TSLPRM_COEFF_TH (0)\r
+\r
+/** @} Common_Parameters_TouchKey_Thresholds */\r
+\r
+//==============================================================================\r
+// Thresholds for Linear and Rotary sensors\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors\r
+ * @{ */\r
+\r
+/** Linear/Rotary Proximity state input threshold (range=0..255)\r
+ - Enter Proximity state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_PROX_IN_TH (30)\r
+\r
+/** Linear/Rotary Proximity state output threshold (range=0..255)\r
+ - Exit Proximity state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_PROX_OUT_TH (20)\r
+\r
+/** Linear/Rotary Detect state input threshold (range=0..255)\r
+ - Enter Detect state if delta is above\r
+*/\r
+#define TSLPRM_LINROT_DETECT_IN_TH (50)\r
+\r
+/** Linear/Rotary Detect state output threshold (range=0..255)\r
+ - Exit Detect state if delta is below\r
+*/\r
+#define TSLPRM_LINROT_DETECT_OUT_TH (40)\r
+\r
+/** Linear/Rotary re-Calibration threshold (range=0..255)\r
+ - @warning The value is inverted in the sensor state machine\r
+ - Enter Calibration state if delta is below\r
+ - A low absolute value will result in a higher sensitivity and thus some spurious\r
+ recalibration may be issued.\r
+*/\r
+#define TSLPRM_LINROT_CALIB_TH (50)\r
+\r
+/** Linear/Rotary Delta normalization (0=No, 1=Yes)\r
+ - When this parameter is set, a coefficient is applied on all Delta of all sensors\r
+ in order to normalize them and to improve the position calculation.\r
+ - These coefficients must be defined in a constant table in the application (see Library examples).\r
+ - The MSB is the coefficient integer part, the LSB is the coefficient real part.\r
+ - Examples:\r
+ - To apply a factor 1.10:\r
+ 0x01 to the MSB\r
+ 0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)\r
+ - To apply a factor 0.90:\r
+ 0x00 to the MSB\r
+ 0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)\r
+ - To apply no factor:\r
+ 0x01 to the MSB\r
+ 0x00 to the LSB\r
+*/\r
+#define TSLPRM_LINROT_USE_NORMDELTA (1)\r
+\r
+/** @} Common_Parameters_LinRot_Thresholds */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors used\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used\r
+ * @{ */\r
+\r
+/** Select which Linear and Rotary sensors you use in your application.\r
+ - 0 = Not Used\r
+ - 1 = Used\r
+\r
+ LIN = Linear sensor\r
+ ROT = Rotary sensor\r
+ M = Mono electrodes design\r
+ H = Half-ended electrodes design\r
+ D = Dual electrodes design\r
+*/\r
+#define TSLPRM_USE_3CH_LIN_M (0)\r
+#define TSLPRM_USE_3CH_LIN_H (1)\r
+#define TSLPRM_USE_3CH_ROT_M (0)\r
+\r
+#define TSLPRM_USE_4CH_LIN_M (0)\r
+#define TSLPRM_USE_4CH_LIN_H (0)\r
+#define TSLPRM_USE_4CH_ROT_M (0)\r
+\r
+#define TSLPRM_USE_5CH_LIN_M (0)\r
+#define TSLPRM_USE_5CH_LIN_H (0)\r
+#define TSLPRM_USE_5CH_ROT_M (0)\r
+#define TSLPRM_USE_5CH_ROT_D (0)\r
+\r
+#define TSLPRM_USE_6CH_LIN_M (0)\r
+#define TSLPRM_USE_6CH_LIN_H (0)\r
+#define TSLPRM_USE_6CH_ROT_M (0)\r
+\r
+/** @} Common_Parameters_LinRot_used */\r
+\r
+//==============================================================================\r
+// Linear/Rotary sensors position\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position\r
+ * @{ */\r
+\r
+/** Position resolution in number of bits (range=1..8)\r
+ - A Low value will result in a low resolution and will be less subject to noise.\r
+ - A High value will result in a high resolution and will be more subject to noise.\r
+*/\r
+#define TSLPRM_LINROT_RESOLUTION (7)\r
+\r
+/** Direction change threshold in position unit (range=0..255)\r
+ - Defines the default threshold used during the change direction process.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_POS (10)\r
+\r
+/** Direction change debounce (range=0..63)\r
+ - Defines the default integrator counter used during the change direction process.\r
+ - This counter is decremented when the same change in the position is detected and the direction will\r
+ change after this counter reaches zero.\r
+ - A Low value will result in a faster direction change.\r
+ - A High value will result in a slower direction change.\r
+*/\r
+#define TSLPRM_LINROT_DIR_CHG_DEB (1)\r
+\r
+/** @} Common_Parameters_LinRot_Position */\r
+\r
+//==============================================================================\r
+// Debounce counters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Debounce 09 - Debounce counters\r
+ * @{ */\r
+\r
+/** Proximity state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_PROX (3)\r
+\r
+/** Detect state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the detection but with less noise filtering.\r
+ - A High value will result in improving the system noise immunity but will increase the system response time.\r
+*/\r
+#define TSLPRM_DEBOUNCE_DETECT (3)\r
+\r
+/** Release state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the end-detection but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_RELEASE (3)\r
+\r
+/** Re-calibration state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.\r
+ - A High value will result in a lower sensitivity during the recalibration but with more noise filtering.\r
+*/\r
+#define TSLPRM_DEBOUNCE_CALIB (3)\r
+\r
+/** Error state debounce in samples unit (range=0..63)\r
+ - A Low value will result in a higher sensitivity to enter in error state.\r
+ - A High value will result in a lower sensitivity to enter in error state.\r
+*/\r
+#define TSLPRM_DEBOUNCE_ERROR (3)\r
+\r
+/** @} Common_Parameters_Debounce */\r
+\r
+//==============================================================================\r
+// Environment Change System (ECS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_ECS 10 - ECS\r
+ * @{ */\r
+\r
+/** Environment Change System Slow K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_SLOW (10)\r
+\r
+/** Environment Change System Fast K factor (range=0..255)\r
+ - The higher value is K, the faster is the response time.\r
+*/\r
+#define TSLPRM_ECS_K_FAST (20)\r
+\r
+/** Environment Change System delay in msec (range=0..5000)\r
+ - The ECS will be started after this delay and when all sensors are in Release state.\r
+*/\r
+#define TSLPRM_ECS_DELAY (500)\r
+\r
+/** @} Common_Parameters_ECS */\r
+\r
+//==============================================================================\r
+// Detection Time Out (DTO)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DTO 11 - DTO\r
+ * @{ */\r
+\r
+/** Detection Time Out delay in seconds (range=0..63)\r
+ - Value 0: DTO processing not compiled in the code (to gain size if not used).\r
+ - Value 1: Default time out infinite.\r
+ - Value between 2 and 63: Default time out between value n-1 and n.\r
+ - Examples:\r
+ - With a DTO equal to 2, the time out is between 1s and 2s.\r
+ - With a DTO equal to 63, the time out is between 62s and 63s.\r
+\r
+@note The DTO can be changed in run-time by the application only if the\r
+ default value is between 1 and 63.\r
+*/\r
+#define TSLPRM_DTO (10)\r
+\r
+/** @} Common_Parameters_DTO */\r
+\r
+//==============================================================================\r
+// Detection Exclusion System (DXS)\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_DXS 12 - DXS\r
+ * @{ */\r
+\r
+/** Detection Exclusion System (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_DXS (0)\r
+\r
+/** @} Common_Parameters_DXS */\r
+\r
+//==============================================================================\r
+// Miscellaneous parameters\r
+//==============================================================================\r
+\r
+/** @defgroup Common_Parameters_Misc 13 - Miscellaneous\r
+ * @{ */\r
+\r
+/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)\r
+ - Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms\r
+*/\r
+#define TSLPRM_TICK_FREQ (2000)\r
+\r
+/** @} Common_Parameters_Misc */\r
+\r
+/** @} Common_Parameters */\r
+\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++\r
+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+/** @defgroup STM32L1xx_Parameters STM32L1xx Parameters\r
+ * @{ */\r
+\r
+/** @defgroup STM32L1xx_Parameters_Misc 01 - Miscellaneous\r
+ * @{ */\r
+\r
+/** Shield with a channel (0=No, 1=Yes)\r
+*/\r
+#define TSLPRM_USE_SHIELD (0)\r
+\r
+/** IOs default mode when no on-going acquisition (range=0..1)\r
+ - 0: Output push-pull low\r
+ - 1: Input floating\r
+*/\r
+#define TSLPRM_IODEF (0)\r
+\r
+/** Master timer prescaler for HW acquisition only (range=0..65535)\r
+ - Divide the timer input clock by this value plus one\r
+*/\r
+#define TSLPRM_TIM_PRESCALER (0)\r
+\r
+/** Master timer reload value for HW acquisition only (range=4..65534, even number)\r
+ - Set the auto-reload value for the center aligned counter\r
+*/\r
+#define TSLPRM_TIM_RELOAD (64)\r
+\r
+/** IT disabling for IO protection for SW acquisition only (range=0..1)\r
+ - 0: IO not protected\r
+ - 1: IO protected\r
+*/\r
+#define TSLPRM_PROTECT_IO_ACCESS (1)\r
+\r
+/** Which GPIO will be used for SW acquisition only (range=0..1)\r
+ - 0: Not used\r
+ - 1: Used\r
+*/\r
+#define TSLPRM_USE_GPIOA (1)\r
+#define TSLPRM_USE_GPIOB (1)\r
+#define TSLPRM_USE_GPIOC (1)\r
+#define TSLPRM_USE_GPIOF (0)\r
+#define TSLPRM_USE_GPIOG (0)\r
+\r
+/** @} STM32L1xx_Parameters_Misc */\r
+\r
+/** @} STM32L1xx_Parameters */\r
+\r
+// DO NOT REMOVE !!!\r
+#include "tsl_check_config.h"\r
+\r
+#endif /* __TSL_CONF_STM32L1xx_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file STM32L152_Ex06_Linear_DISC\inc\tsl_user.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Touch-Sensing user configuration and api file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __TSL_USER_H\r
+#define __TSL_USER_H\r
+\r
+#include "tsl.h"\r
+\r
+// LEDs definition on STM32L152B-DISC board\r
+// PB7 = LED_GREEN\r
+#define LED_GREEN_TOGGLE {GPIOB->ODR ^= (1<<7);}\r
+#define LED_GREEN_OFF {GPIOB->ODR &= ~(1<<7);}\r
+#define LED_GREEN_ON {GPIOB->ODR |= (1<<7);}\r
+// PB6 = LED_BLUE\r
+#define LED_BLUE_TOGGLE {GPIOB->ODR ^= (1<<6);}\r
+#define LED_BLUE_OFF {GPIOB->ODR &= ~(1<<6);}\r
+#define LED_BLUE_ON {GPIOB->ODR |= (1<<6);}\r
+\r
+//==============================================================================\r
+// IOs definition\r
+//==============================================================================\r
+\r
+// Channel IOs definition\r
+#define CHANNEL_0_SRC ((uint32_t)(GR2))\r
+#define CHANNEL_0_DEST (0)\r
+#define CHANNEL_0_SAMPLE_CONFIG TSL_GROUP2_IO2\r
+#define CHANNEL_0_CHANNEL_CONFIG TSL_GROUP2_IO1\r
+\r
+#define CHANNEL_1_SRC ((uint32_t)(GR9))\r
+#define CHANNEL_1_DEST (1)\r
+#define CHANNEL_1_SAMPLE_CONFIG TSL_GROUP9_IO2\r
+#define CHANNEL_1_CHANNEL_CONFIG TSL_GROUP9_IO1\r
+\r
+#define CHANNEL_2_SRC ((uint32_t)(GR3))\r
+#define CHANNEL_2_DEST (2)\r
+#define CHANNEL_2_SAMPLE_CONFIG TSL_GROUP3_IO2\r
+#define CHANNEL_2_CHANNEL_CONFIG TSL_GROUP3_IO1\r
+\r
+// Banks definition\r
+#define BANK_0_NBCHANNELS (3)\r
+#define BANK_0_INDEX (0) // Index of 1st channel used\r
+#define BANK_0_SHIELD_SAMPLE (0)\r
+#define BANK_0_SHIELD_CHANNEL (0)\r
+\r
+// User Parameters\r
+extern TSL_ObjectGroup_T MyObjGroup;\r
+extern CONST TSL_Object_T MyObjects[];\r
+extern CONST TSL_Bank_T MyBanks[];\r
+extern CONST TSL_LinRot_T MyLinRots[];\r
+\r
+void MyLinRots_ErrorStateProcess(void);\r
+void MyLinRots_OffStateProcess(void);\r
+\r
+void TSL_user_Init(void);\r
+TSL_Status_enum_T TSL_user_Action(void);\r
+void ProcessSensors(void);\r
+void ProcessSensorsButtons(void);\r
+\r
+\r
+#endif /* __TSL_USER_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file main.c\r
+ * @author Microcontroller Division\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Main program body\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */\r
+ \r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+#include "main.h"\r
+\r
+#define BOR_MODIFY\r
+#define BOR_LEVEL OB_BOR_OFF /*!< BOR is disabled at power down, the reset is asserted when the VDD power supply reachs the PDR(Power Down Reset) threshold (1.5V) */\r
+\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+static TSL_tTick_ms_T last_tick_tsl; /* Hold the last tsl time value */\r
+extern unsigned char Bias_Current; /* Bias Current stored in E²Prom used for ICC mesurement precision */\r
+extern uint8_t t_bar[2]; /* LCD bar graph: used for displaying active function */\r
+extern bool self_test; /* Auto_test activation flag: set by interrupt handler if user button is pressed for a few seconds */\r
+extern bool Idd_WakeUP; /* */\r
+extern volatile bool KeyPressed; /* */\r
+extern bool UserButton; /* Set by interrupt handler to indicate that user button is pressed */ \r
+uint8_t state_machine; /* Machine status used by main() wich indicats the active function, set by user button in interrupt handler */\r
+uint16_t Int_CurrentSTBY; /* */\r
+\r
+#ifdef STM32L1XX_MDP\r
+ uint8_t message[29] = " ** 32L152CDISCOVERY **";\r
+ #else\r
+ uint8_t message[29] = " ** STM32L1-DISCOVERY **";\r
+#endif\r
+/*******************************************************************************/\r
+/**\r
+ * @brief main entry point.\r
+ * @par Parameters None\r
+ * @retval void None\r
+ * @par Required preconditions: None\r
+ */\r
+int main(void)\r
+{ \r
+ bool StanbyWakeUp ;\r
+ float Current_STBY;\r
+ __IO uint32_t BOROptionBytes = 0;\r
+ \r
+ /*!< At this stage the microcontroller clock setting is already configured, \r
+ this is done through SystemInit() function which is called from startup\r
+ file (startup_stm32l1xx_md.s) before to branch to application main.\r
+ To reconfigure the default setting of SystemInit() function, refer to\r
+ system_stm32l1xx.c file\r
+ */ \r
+ \r
+ /* store Standby Current*/\r
+ Int_CurrentSTBY = Current_Measurement();\r
+ \r
+ /* Check if the StandBy flag is set */\r
+ if (PWR_GetFlagStatus(PWR_FLAG_SB) != RESET)\r
+ {\r
+ /* System resumed from STANDBY mode */\r
+ /* Clear StandBy flag */\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR,ENABLE);\r
+ PWR_ClearFlag(PWR_FLAG_SB); \r
+ /* set StandbyWakeup indicator*/\r
+ StanbyWakeUp = TRUE;\r
+ } else\r
+ {\r
+ /* Reset StandbyWakeup indicator*/\r
+ StanbyWakeUp = FALSE; \r
+ } \r
+\r
+ #ifdef BOR_MODIFY\r
+ /* Get BOR Option Bytes */\r
+ BOROptionBytes = FLASH_OB_GetBOR();\r
+\r
+ if((BOROptionBytes & 0x0F) != BOR_LEVEL) \r
+ {\r
+ /* Unlocks the option bytes block access */\r
+ FLASH_OB_Unlock();\r
+\r
+ /* Clears the FLASH pending flags */\r
+ FLASH_ClearFlag(FLASH_FLAG_EOP|FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR\r
+ | FLASH_FLAG_SIZERR | FLASH_FLAG_OPTVERR);\r
+\r
+ /* Select the desired V(BOR) Level ---------------------------------------*/\r
+ FLASH_OB_BORConfig(BOR_LEVEL); \r
+\r
+ /* Launch the option byte loading */\r
+ FLASH_OB_Launch(); \r
+ }\r
+#endif \r
+ \r
+ /* Configure Clocks for Application need */\r
+ RCC_Configuration();\r
+ \r
+ /* Set internal voltage regulator to 1.8V */\r
+ PWR_VoltageScalingConfig(PWR_VoltageScaling_Range1);\r
+ \r
+ /* Wait Until the Voltage Regulator is ready */\r
+ while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET) ;\r
+ \r
+ /* Init I/O ports */\r
+ Init_GPIOs();\r
+ \r
+ /* Initializes ADC */\r
+ ADC_Icc_Init();\r
+ \r
+ /* Enable General interrupts */\r
+ enableGlobalInterrupts(); \r
+ \r
+ /* Init Touch Sensing configuration */ \r
+ TSL_user_Init();\r
+\r
+ /* Initializes the LCD glass */\r
+ LCD_GLASS_Init();\r
+ \r
+ /* Reset Keypressed flag used in interrupt and Scrollsentence */\r
+ KeyPressed = FALSE;\r
+\r
+ /* user button actif */ \r
+ UserButton = TRUE;\r
+ \r
+ /* Check if User button press at Power ON */ \r
+ if ((USERBUTTON_GPIO_PORT->IDR & USERBUTTON_GPIO_PIN) != 0x0)\r
+ {\r
+ /* Measure operational amplifier bias current and store value in E²Prom for application need*/\r
+ Bias_measurement();\r
+ }\r
+\r
+ /* Standard application startup */\r
+ if ( !StanbyWakeUp )\r
+ { \r
+ /* Reset autotest flag stored in memory */\r
+ AUTOTEST(FALSE) ;\r
+\r
+ /* Display Welcome message */ \r
+ LCD_GLASS_ScrollSentence(message,1,SCROLL_SPEED);\r
+ if (!KeyPressed)\r
+ {\r
+ /* if welcome message not skipped Display blinking message JP1 ON*/\r
+ LCD_BlinkConfig(LCD_BlinkMode_AllSEG_AllCOM,LCD_BlinkFrequency_Div512);\r
+ LCD_GLASS_DisplayString("JP1 ON");\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ LCD_BlinkConfig(LCD_BlinkMode_Off,LCD_BlinkFrequency_Div32); \r
+ }\r
+ /* Wake up from Standby or autotest */\r
+ } else {\r
+ /*Check Autotest value stored in flash to get wakeup context*/\r
+ if (self_test)\r
+ {\r
+ /* Wake UP: Return of RESET by Auto test */\r
+ auto_test_part2(); \r
+ } else {\r
+ /* Wake UP: Return of RESET by Current STAND BY measurement */\r
+ LCD_GLASS_ScrollSentence(" STANDBY WAKEUP",1,SCROLL_SPEED);\r
+ /* Substract bias current from operational amplifier*/\r
+ if ( Int_CurrentSTBY > Bias_Current )\r
+ Int_CurrentSTBY -= Bias_Current;\r
+ Current_STBY = Int_CurrentSTBY * Vdd_appli()/ADC_CONV; \r
+ Current_STBY *= 20L;\r
+ display_MuAmp((uint32_t)Current_STBY);\r
+ /* Wait for user button press to continue */\r
+ while(!KeyPressed);\r
+ }\r
+ }\r
+ /* Reset KeyPress Flag */\r
+ KeyPressed = FALSE; \r
+ /* Clear LCD bars */\r
+ BAR0_OFF;\r
+ BAR1_OFF;\r
+ BAR2_OFF;\r
+ BAR3_OFF; \r
+ /* Switch off the leds*/\r
+ GPIO_HIGH(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN); \r
+ /* Set application state machine to VREF state */\r
+ state_machine = STATE_VREF ;\r
+ /*Until application reset*/\r
+ while (1)\r
+ {\r
+ /* run autotest if requested by the user */\r
+ if (self_test)\r
+ auto_test();\r
+ /* Perform Actions depending on current application State */\r
+ switch (state_machine)\r
+ {\r
+ /* VREF State : Display VRef value */\r
+ case STATE_VREF:\r
+ GPIO_TOGGLE(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);\r
+ GPIO_TOGGLE(LD_GPIO_PORT,LD_GREEN_GPIO_PIN);\r
+ Vref_measure();\r
+ TEMPO ;\r
+ break;\r
+ \r
+ /* Slider Value State : Display the TS slider value */\r
+ case STATE_SLIDER_VALUE:\r
+\r
+ // Execute STMTouch Driver state machine\r
+ if (TSL_user_Action() == TSL_STATUS_OK)\r
+ {\r
+ ProcessSensors(); // Execute sensors related tasks\r
+ }\r
+ break;\r
+ \r
+ /* Slider button State : Display the curent TS button pressed */\r
+ case STATE_SLIDER_BUTTON: \r
+ // Execute STMTouch Driver state machine\r
+ if (TSL_user_Action() == TSL_STATUS_OK)\r
+ {\r
+ ProcessSensorsButtons(); // Execute sensors related tasks\r
+ } \r
+ break;\r
+ \r
+ /* ICC RUN State : ICC mesurements in Run and Sleep modes */\r
+ case STATE_ICC_RUN:\r
+ LCD_GLASS_DisplayString(" RUN ");\r
+ TEMPO;\r
+ Icc_RUN();\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ LCD_GLASS_DisplayString(" SLEEP ");\r
+ TEMPO;\r
+ Icc_SLEEP(); \r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ break;\r
+ \r
+ /* ICC LOW POWER RUN State : ICC mesurements in LowPower run and LowPower Sleep modes */\r
+ case STATE_ICC_LP_RUN:\r
+ LCD_GLASS_DisplayString("LP RUN");\r
+ TEMPO;\r
+ Icc_LPRUN();\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ LCD_GLASS_DisplayString("LP SLP");\r
+ TEMPO;\r
+ Icc_LPSLEEP();\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO; \r
+ break;\r
+ \r
+ /* ICC STOP State : ICC mesurements in Stop and STOP NoRTC modes */\r
+ case STATE_ICC_STOP:\r
+ LCD_GLASS_DisplayString(" STOP ");\r
+ TEMPO;\r
+ Icc_STOP();\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO; \r
+ LCD_GLASS_DisplayString("SP-NRTC");\r
+ TEMPO;\r
+ Icc_Stop_NoRTC();\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO;\r
+ TEMPO; \r
+ break;\r
+ \r
+ /* ICC Standby State : ICC mesurements in Standby mode */\r
+ case STATE_ICC_STBY:\r
+ LCD_GLASS_DisplayString("STBY ");\r
+ TEMPO;\r
+ TEMPO; \r
+ ADC_Icc_Test(MCU_STBY);\r
+ /* Following break never performed dues to software reset in previous function */ \r
+ break;\r
+ \r
+ /* for safe: normaly never reaches */ \r
+ default:\r
+ LCD_GLASS_Clear();\r
+ LCD_GLASS_DisplayString("ERROR");\r
+ break;\r
+ }\r
+ /* Reset KeyPress flag*/\r
+ KeyPressed = FALSE;\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Configures the different system clocks.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_Configuration(void)\r
+{ \r
+ /* Enable HSI Clock */\r
+ RCC_HSICmd(ENABLE);\r
+ \r
+ /*!< Wait till HSI is ready */\r
+ while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);\r
+\r
+ /* Set HSI as sys clock*/\r
+ RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);\r
+ \r
+ /* Set MSI clock range to ~4.194MHz*/\r
+ RCC_MSIRangeConfig(RCC_MSIRange_6);\r
+ \r
+ /* Enable the GPIOs clocks */\r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC| RCC_AHBPeriph_GPIOD| RCC_AHBPeriph_GPIOE| RCC_AHBPeriph_GPIOH, ENABLE); \r
+\r
+ /* Enable comparator, LCD and PWR mngt clocks */\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP | RCC_APB1Periph_LCD | RCC_APB1Periph_PWR,ENABLE);\r
+ \r
+ /* Enable ADC & SYSCFG clocks */\r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_SYSCFG , ENABLE);\r
+\r
+ /* Allow access to the RTC */\r
+ PWR_RTCAccessCmd(ENABLE);\r
+\r
+ /* Reset RTC Backup Domain */\r
+ RCC_RTCResetCmd(ENABLE);\r
+ RCC_RTCResetCmd(DISABLE);\r
+\r
+ /* LSE Enable */\r
+ RCC_LSEConfig(RCC_LSE_ON);\r
+\r
+ /* Wait until LSE is ready */\r
+ while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET);\r
+ \r
+ /* RTC Clock Source Selection */ \r
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); \r
+ \r
+ /* Enable the RTC */\r
+ RCC_RTCCLKCmd(ENABLE); \r
+ \r
+ /*Disable HSE*/\r
+ RCC_HSEConfig(RCC_HSE_OFF);\r
+ if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET )\r
+ {\r
+ /* Stay in infinite loop if HSE is not disabled*/\r
+ while(1); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief To initialize the I/O ports\r
+ * @caller main\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void Init_GPIOs (void)\r
+{\r
+ /* GPIO, EXTI and NVIC Init structure declaration */\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ EXTI_InitTypeDef EXTI_InitStructure;\r
+ NVIC_InitTypeDef NVIC_InitStructure;\r
+ \r
+ /* Configure User Button pin as input */\r
+ GPIO_InitStructure.GPIO_Pin = USERBUTTON_GPIO_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+ GPIO_Init(USERBUTTON_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /* Select User Button pin as input source for EXTI Line */\r
+ SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA,EXTI_PinSource0);\r
+\r
+ /* Configure EXT1 Line 0 in interrupt mode trigged on Rising edge */\r
+ EXTI_InitStructure.EXTI_Line = EXTI_Line0 ; // PA0 for User button AND IDD_WakeUP\r
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; \r
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r
+ EXTI_Init(&EXTI_InitStructure);\r
+\r
+ /* Enable and set EXTI0 Interrupt to the lowest priority */\r
+ NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn ;\r
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+ NVIC_Init(&NVIC_InitStructure); \r
+\r
+ /* Configure the LED_pin as output push-pull for LD3 & LD4 usage*/\r
+ GPIO_InitStructure.GPIO_Pin = LD_GREEN_GPIO_PIN | LD_BLUE_GPIO_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_Init(LD_GPIO_PORT, &GPIO_InitStructure);\r
+ \r
+ /* Force a low level on LEDs*/ \r
+ GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);\r
+ \r
+/* Counter enable: GPIO set in output for enable the counter */\r
+ GPIO_InitStructure.GPIO_Pin = CTN_CNTEN_GPIO_PIN;\r
+ GPIO_Init( CTN_GPIO_PORT, &GPIO_InitStructure);\r
+ \r
+/* To prepare to start counter */\r
+ GPIO_HIGH(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);\r
+ \r
+/* Configure Port A LCD Output pins as alternate function */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOA, &GPIO_InitStructure);\r
+ \r
+/* Select LCD alternate function for Port A LCD Output pins */\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ; \r
+ \r
+ /* Configure Port B LCD Output pins as alternate function */ \r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \\r
+ | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOB, &GPIO_InitStructure);\r
+ \r
+ /* Select LCD alternate function for Port B LCD Output pins */\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ; \r
+ \r
+ /* Configure Port C LCD Output pins as alternate function */ \r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \\r
+ | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOC, &GPIO_InitStructure); \r
+\r
+ /* Select LCD alternate function for Port B LCD Output pins */\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ; \r
+ \r
+ /* Configure ADC (IDD_MEASURE) pin as Analogue */\r
+ GPIO_InitStructure.GPIO_Pin = IDD_MEASURE ; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;\r
+ GPIO_Init( IDD_MEASURE_PORT, &GPIO_InitStructure);\r
+} \r
+\r
+\r
+/**\r
+ * @brief Executed when a sensor is in Error state\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void MyLinRots_ErrorStateProcess(void)\r
+{\r
+ // Add here your own processing when a sensor is in Error state\r
+ TSL_linrot_SetStateOff();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Executed when a sensor is in Off state\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void MyLinRots_OffStateProcess(void)\r
+{\r
+ // Add here your own processing when a sensor is in Off state\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Inserts a delay time.\r
+ * @param nTime: specifies the delay time length, in 1 ms.\r
+ * @retval None\r
+ */\r
+void Delay(uint32_t nTime)\r
+{\r
+ while (TSL_tim_CheckDelay_ms((TSL_tTick_ms_T) nTime, &last_tick_tsl) != TSL_STATUS_OK);\r
+}\r
+\r
+\r
+#ifdef USE_FULL_ASSERT\r
+\r
+/**\r
+ * @brief Reports the name of the source file and the source line number\r
+ * where the assert_param error has occurred.\r
+ * @param file: pointer to the source file name\r
+ * @param line: assert_param error line source number\r
+ * @retval None\r
+ */\r
+void assert_failed(uint8_t* file, uint32_t line)\r
+{ \r
+ /* User can add his own implementation to report the file name and line number,\r
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
+ /* Infinite loop */\r
+ while (1);\r
+}\r
+\r
+#endif\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armstlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --macro "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\ST\Trace_STM32L1xx.dmac" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\ST\FlashSTM32L15xxB.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\ST\STM32L152xB.ddf" "--drv_verify_download" "--semihosting" "--device=STM32L152xB" "--stlink_interface=SWD" "--stlink_reset_strategy=0,2" "--drv_swo_clock_setup=32000000,1,2000000" \r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Debug-Log>\r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>124</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ <PreferedWindows>\r
+ <Position>2</Position>\r
+ <ScreenPosX>0</ScreenPosX>\r
+ <ScreenPosY>0</ScreenPosY>\r
+ <Windows/>\r
+ </PreferedWindows>\r
+ <ShowCodeCoverage>1</ShowCodeCoverage>\r
+ <ShowInstrProfiling>1</ShowInstrProfiling>\r
+ <col-names>\r
+ <item>Disassembly</item>\r
+ <item>_I0</item>\r
+ </col-names>\r
+ <col-widths>\r
+ <item>500</item>\r
+ <item>20</item>\r
+ </col-widths>\r
+ <DisasmHistory/>\r
+ </Disassembly>\r
+ </Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-5570-17231</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-5048-17240</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-16319-17234</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>STM32L-Discovery</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane/><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0134c060><key>iaridepm.enu1</key></Toolbar-0134c060></Sizes></Row0><Row1><Sizes><Toolbar-04f07500><key>debuggergui.enu1</key></Toolbar-04f07500></Sizes></Row1><Row2><Sizes><Toolbar-0620bde8><key>armstlink.enu1</key></Toolbar-0620bde8></Sizes></Row2></Top><Left><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>692</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>706721</sizeVertCY></Rect></Wnd3></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd2></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
+[Stack]\r
+FillEnabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnLogOnly=1\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[DebugChecksum]\r
+Checksum=-1039366939\r
+[Exceptions]\r
+StopOnUncaught=_ 0\r
+StopOnThrow=_ 0\r
+[CallStack]\r
+ShowArgs=0\r
+[Disassembly]\r
+MixedMode=1\r
+[SWOTraceHWSettings]\r
+OverrideDefaultClocks=0\r
+CpuClock=32000000\r
+ClockAutoDetect=1\r
+ClockWanted=2000000\r
+JtagSpeed=2000000\r
+Prescaler=16\r
+TimeStampPrescIndex=0\r
+TimeStampPrescData=0\r
+PcSampCYCTAP=1\r
+PcSampPOSTCNT=15\r
+PcSampIndex=0\r
+DataLogMode=0\r
+ITMportsEnable=0\r
+ITMportsTermIO=0\r
+ITMportsLogFile=0\r
+ITMlogFile=$PROJ_DIR$\ITM.log\r
+[Trace2]\r
+Enabled=0\r
+ShowSource=0\r
+[SWOTraceWindow]\r
+PcSampling=0\r
+InterruptLogs=0\r
+ForcedTimeStamps=0\r
+EventCPI=0\r
+EventEXC=0\r
+EventFOLD=0\r
+EventLSU=0\r
+EventSLEEP=0\r
+[DataLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints2]\r
+Count=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=3\r
+Graph=0\r
+Symbiont=0\r
+Exclusions=\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>STM32L-Discovery/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>250</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build><TerminalIO/></Static>\r
+ <Windows>\r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-15942-14785</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>STM32L-Discovery</ExpandedNode><ExpandedNode>STM32L-Discovery/Doc</ExpandedNode><ExpandedNode>STM32L-Discovery/EWARM</ExpandedNode><ExpandedNode>STM32L-Discovery/STM32L1xx_StdPeriph_Driver</ExpandedNode><ExpandedNode>STM32L-Discovery/User</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-11321-17123</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\ST_Code\libraries\CMSIS\Device\ST\STM32L1xx\Include\stm32l1xx.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>6309</YPos2><SelStart2>474779</SelStart2><SelEnd2>474779</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\ST_Code\libraries\STM32L1xx_StdPeriph_Driver\inc\stm32l1xx_exti.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>1477</SelStart2><SelEnd2>1477</SelEnd2></Tab><ActiveTab>1</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0134c060><key>iaridepm.enu1</key></Toolbar-0134c060></Sizes></Row0><Row1><Sizes><Toolbar-04f07500><key>debuggergui.enu1</key></Toolbar-04f07500></Sizes></Row1><Row2><Sizes><Toolbar-0620bde8><key>armstlink.enu1</key></Toolbar-0620bde8></Sizes></Row2></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>324</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>194048</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+do not initialize { section .DataFlash };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place at address mem:0x08080000 {readwrite section .DataFlash };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block HEAP };
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.c \r
+ * @author MCD Application Team\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Main Interrupt Service Routines.\r
+ * This file provides template for all exceptions handler and \r
+ * peripherals interrupt service routine.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_it.h"\r
+#include "stm32l1xx_exti.h"\r
+#include "stm32l1xx_rtc.h"\r
+#include "discover_functions.h"\r
+#include "discover_board.h"\r
+#include "stm32l_discovery_lcd.h"\r
+#include "tsl.h"\r
+\r
+\r
+extern volatile bool KeyPressed;\r
+extern uint8_t state_machine;\r
+extern bool self_test;\r
+extern bool UserButton;\r
+extern volatile bool Idd_WakeUP;\r
+extern uint8_t t_bar[2];\r
+\r
+/** @addtogroup Template_Project\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/* Cortex-M3 Processor Exceptions Handlers */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles NMI exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Hard Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * @brief This function handles Memory Manage exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void MemManage_Handler(void)\r
+{\r
+ /* Go to infinite loop when Memory Manage exception occurs */\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * @brief This function handles Bus Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BusFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Bus Fault exception occurs */\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * @brief This function handles Usage Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UsageFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Usage Fault exception occurs */\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * @brief This function handles SVCall exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SVC_Handler(void)\r
+{ \r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * @brief This function handles Debug Monitor exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DebugMon_Handler(void)\r
+{\r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * @brief This function handles PendSVC exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PendSV_Handler(void)\r
+{\r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * @brief This function handles SysTick interrupts.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SysTick_Handler(void)\r
+{\r
+// disableGlobalInterrupts();\r
+// TimingDelay_Decrement();\r
+// enableGlobalInterrupts();\r
+ \r
+ TSL_tim_ProcessIT();\r
+}\r
+\r
+/**\r
+ * @brief This function handles external interrupts generated by UserButton.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UserButtonHandler (void)\r
+{ \r
+ uint32_t i=0; \r
+ \r
+ /* set KeyPressed Flag */\r
+ KeyPressed = TRUE; \r
+ \r
+ /* check if user button is pressed for 4 seconds (approx.) */\r
+ while ((USERBUTTON_GPIO_PORT->IDR & USERBUTTON_GPIO_PIN) == 1 )\r
+ {\r
+ i++;\r
+ if (i == 0x0100000)\r
+ {\r
+ /* set autotest flag in E²prom*/\r
+ AUTOTEST(TRUE) ; \r
+ return;\r
+ }\r
+ }\r
+ \r
+ /* if autotest is set in E²prom exit interrupt handler */ \r
+ if (self_test)\r
+ return ;\r
+ \r
+ /* Go to next state of state machine*/\r
+ state_machine++;\r
+ if (state_machine == MAX_STATE)\r
+ state_machine = STATE_VREF;\r
+ \r
+ /* To update Bar graph & leds*/ \r
+ switch (state_machine)\r
+ {\r
+ case STATE_VREF:\r
+ GPIO_HIGH(LD_GPIO_PORT,LD_GREEN_GPIO_PIN);\r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);\r
+ BAR0_OFF;\r
+ BAR1_OFF;\r
+ BAR2_OFF;\r
+ BAR3_OFF;\r
+ break;\r
+ \r
+ case STATE_SLIDER_VALUE:\r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN); \r
+ GPIO_HIGH(LD_GPIO_PORT,LD_GREEN_GPIO_PIN);\r
+ break;\r
+ \r
+ case STATE_SLIDER_BUTTON:\r
+ GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
+ GPIO_HIGH(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);\r
+ break;\r
+ \r
+ case STATE_ICC_RUN:\r
+ GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN); \r
+ BAR0_ON;\r
+ BAR1_OFF;\r
+ BAR2_OFF;\r
+ BAR3_OFF;\r
+ break;\r
+ \r
+ case STATE_ICC_LP_RUN:\r
+ GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN); \r
+ BAR0_ON;\r
+ BAR1_ON;\r
+ BAR2_OFF;\r
+ BAR3_OFF;\r
+ break;\r
+\r
+ case STATE_ICC_STOP:\r
+ GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN); \r
+ BAR0_ON;\r
+ BAR1_ON;\r
+ BAR2_ON;\r
+ BAR3_OFF;\r
+ break; \r
+ \r
+ case STATE_ICC_STBY:\r
+ GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); \r
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN); \r
+ BAR0_ON;\r
+ BAR1_ON;\r
+ BAR2_ON;\r
+ BAR3_ON;\r
+ break; \r
+ } \r
+}\r
+\r
+void EXTI0_IRQHandler(void)\r
+{\r
+ /* Disable general interrupts */\r
+ disableGlobalInterrupts();\r
+ \r
+ /* UserButton usage activated*/ \r
+ if (UserButton)\r
+ {\r
+ UserButtonHandler();\r
+ }\r
+ else \r
+ {\r
+ /*Idd_Wakeup detected */\r
+ Idd_WakeUP = TRUE;\r
+ } \r
+ EXTI_ClearITPendingBit(EXTI_Line0);\r
+ enableGlobalInterrupts();\r
+}\r
+\r
+\r
+void RTC_WKUP_IRQHandler (void)\r
+{\r
+ RTC_ClearITPendingBit(RTC_IT_WUT);\r
+ EXTI_ClearITPendingBit(EXTI_Line20);\r
+}\r
+\r
+/******************************************************************************/\r
+/* STM32L1xx Peripherals Interrupt Handlers */\r
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r
+/* available peripheral interrupt handler's name please refer to the startup */\r
+/* file (startup_stm32l1xx_md.s). */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles PPP interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+/*void PPP_IRQHandler(void)\r
+{\r
+}*/\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file STM32L152_Ex06_Linear_DISC\src\tsl_user.c \r
+ * @author MCD Application Team\r
+ * @version V1.0.3\r
+ * @date May-2013\r
+ * @brief Touch-Sensing user configuration and api file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+#include "tsl_user.h"\r
+#include "stm32l_discovery_lcd.h"\r
+#include "discover_functions.h"\r
+\r
+// PB6 = LED_GREEN\r
+// #define LED_GREEN_TOGGLE {GPIOB->ODR ^= (1<<7);}\r
+// #define LED_GREEN_OFF {GPIOB->BSRRL = (1<<7);}\r
+// #define LED_GREEN_ON {GPIOB->BSRRH = (1<<7);}\r
+\r
+// PB7 = LED_BLUE\r
+// #define LED_BLUE_TOGGLE {GPIOB->ODR ^= (1<<6);}\r
+// #define LED_BLUE_OFF {GPIOB->BSRRL = (1<<6);}\r
+// #define LED_BLUE_ON {GPIOB->BSRRH = (1<<6);}\r
+\r
+\r
+unsigned char Slider_Position[7];\r
+extern uint8_t t_bar[2];\r
+\r
+//==============================================================================\r
+// Channels\r
+//==============================================================================\r
+\r
+// Channel Source and Configuration: Always placed in ROM\r
+const TSL_ChannelSrc_T MyChannels_Src[TSLPRM_TOTAL_CHANNELS] = {\r
+ { CHANNEL_0_SRC, CHANNEL_0_SAMPLE_CONFIG, CHANNEL_0_CHANNEL_CONFIG },\r
+ { CHANNEL_1_SRC, CHANNEL_1_SAMPLE_CONFIG, CHANNEL_1_CHANNEL_CONFIG },\r
+ { CHANNEL_2_SRC, CHANNEL_2_SAMPLE_CONFIG, CHANNEL_2_CHANNEL_CONFIG }\r
+};\r
+\r
+// Channel Destination: Always placed in ROM\r
+const TSL_ChannelDest_T MyChannels_Dest[TSLPRM_TOTAL_CHANNELS] = {\r
+ { CHANNEL_0_DEST },\r
+ { CHANNEL_1_DEST },\r
+ { CHANNEL_2_DEST }\r
+};\r
+\r
+// Channel Data: Always placed in RAM\r
+TSL_ChannelData_T MyChannels_Data[TSLPRM_TOTAL_CHANNELS];\r
+\r
+//------\r
+// Banks\r
+//------\r
+\r
+// Always placed in ROM\r
+CONST TSL_Bank_T MyBanks[TSLPRM_TOTAL_BANKS] = {\r
+ {&MyChannels_Src[0], &MyChannels_Dest[0], MyChannels_Data, BANK_0_NBCHANNELS, BANK_0_SHIELD_SAMPLE, BANK_0_SHIELD_CHANNEL} \r
+};\r
+\r
+\r
+//==============================================================================\r
+// Linear and Rotary sensors\r
+//==============================================================================\r
+\r
+// Data (RAM)\r
+TSL_LinRotData_T MyLinRots_Data[TSLPRM_TOTAL_LINROTS];\r
+\r
+// Parameters (RAM)\r
+TSL_LinRotParam_T MyLinRots_Param[TSLPRM_TOTAL_LINROTS];\r
+\r
+\r
+// State Machine (ROM)\r
+\r
+\r
+CONST TSL_State_T MyLinRots_StateMachine[] =\r
+{\r
+ // Calibration states\r
+ /* 0 */ { TSL_STATEMASK_CALIB, TSL_linrot_CalibrationStateProcess },\r
+ /* 1 */ { TSL_STATEMASK_DEB_CALIB, TSL_linrot_DebCalibrationStateProcess },\r
+ // Release states \r
+ /* 2 */ { TSL_STATEMASK_RELEASE, TSL_linrot_ReleaseStateProcess },\r
+#if TSLPRM_USE_PROX > 0\r
+ /* 3 */ { TSL_STATEMASK_DEB_RELEASE_PROX, TSL_linrot_DebReleaseProxStateProcess },\r
+#else\r
+ /* 3 */ { TSL_STATEMASK_DEB_RELEASE_PROX, 0 },\r
+#endif\r
+ /* 4 */ { TSL_STATEMASK_DEB_RELEASE_DETECT, TSL_linrot_DebReleaseDetectStateProcess },\r
+ /* 5 */ { TSL_STATEMASK_DEB_RELEASE_TOUCH, TSL_linrot_DebReleaseTouchStateProcess },\r
+#if TSLPRM_USE_PROX > 0\r
+ // Proximity states\r
+ /* 6 */ { TSL_STATEMASK_PROX, TSL_linrot_ProxStateProcess },\r
+ /* 7 */ { TSL_STATEMASK_DEB_PROX, TSL_linrot_DebProxStateProcess },\r
+ /* 8 */ { TSL_STATEMASK_DEB_PROX_DETECT, TSL_linrot_DebProxDetectStateProcess },\r
+ /* 9 */ { TSL_STATEMASK_DEB_PROX_TOUCH, TSL_linrot_DebProxTouchStateProcess },\r
+#else\r
+ /* 6 */ { TSL_STATEMASK_PROX, 0 },\r
+ /* 7 */ { TSL_STATEMASK_DEB_PROX, 0 },\r
+ /* 8 */ { TSL_STATEMASK_DEB_PROX_DETECT, 0 },\r
+ /* 9 */ { TSL_STATEMASK_DEB_PROX_TOUCH, 0 },\r
+#endif\r
+ // Detect states\r
+ /* 10 */ { TSL_STATEMASK_DETECT, TSL_linrot_DetectStateProcess },\r
+ /* 11 */ { TSL_STATEMASK_DEB_DETECT, TSL_linrot_DebDetectStateProcess },\r
+ // Touch state\r
+ /* 12 */ { TSL_STATEMASK_TOUCH, TSL_linrot_TouchStateProcess },\r
+ // Error states\r
+ /* 13 */ { TSL_STATEMASK_ERROR, MyLinRots_ErrorStateProcess },\r
+ /* 14 */ { TSL_STATEMASK_DEB_ERROR_CALIB, TSL_linrot_DebErrorStateProcess },\r
+ /* 15 */ { TSL_STATEMASK_DEB_ERROR_RELEASE, TSL_linrot_DebErrorStateProcess },\r
+ /* 16 */ { TSL_STATEMASK_DEB_ERROR_PROX, TSL_linrot_DebErrorStateProcess },\r
+ /* 17 */ { TSL_STATEMASK_DEB_ERROR_DETECT, TSL_linrot_DebErrorStateProcess },\r
+ /* 18 */ { TSL_STATEMASK_DEB_ERROR_TOUCH, TSL_linrot_DebErrorStateProcess },\r
+ // Other states\r
+ /* 19 */ { TSL_STATEMASK_OFF, MyLinRots_OffStateProcess }\r
+};\r
+\r
+// Methods for "extended" type (ROM)\r
+CONST TSL_LinRotMethods_T MyLinRots_Methods =\r
+{\r
+ TSL_linrot_Init,\r
+ TSL_linrot_Process,\r
+ TSL_linrot_CalcPos\r
+};\r
+\r
+// Delta Normalization Process\r
+// The MSB is the integer part, the LSB is the real part\r
+// Examples:\r
+// - To apply a factor 1.10:\r
+// 0x01 to the MSB\r
+// 0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)\r
+// - To apply a factor 0.90:\r
+// 0x00 to the MSB\r
+// 0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)\r
+CONST uint16_t MyLinRot_DeltaCoeff[3] = {0x0200, 0x0100, 0x0300};\r
+\r
+// LinRots list (ROM)\r
+CONST TSL_LinRot_T MyLinRots[TSLPRM_TOTAL_LINROTS] =\r
+{\r
+ {&MyLinRots_Data[0], &MyLinRots_Param[0], &MyChannels_Data[CHANNEL_0_DEST],\r
+ 3, // Number of channels\r
+ MyLinRot_DeltaCoeff,\r
+ (TSL_tsignPosition_T *)TSL_POSOFF_3CH_LIN_H,\r
+ TSL_SCTCOMP_3CH_LIN_H,\r
+ TSL_POSCORR_3CH_LIN_H, \r
+ MyLinRots_StateMachine,\r
+ &MyLinRots_Methods}\r
+};\r
+\r
+//----------------\r
+// Generic Objects\r
+//----------------\r
+\r
+// List (ROM)\r
+CONST TSL_Object_T MyObjects[TSLPRM_TOTAL_OBJECTS] =\r
+{\r
+ { TSL_OBJ_LINEAR, (TSL_LinRot_T *)&MyLinRots[0] }\r
+};\r
+\r
+// Group (RAM)\r
+TSL_ObjectGroup_T MyObjGroup =\r
+{\r
+ &MyObjects[0], // First object\r
+ TSLPRM_TOTAL_OBJECTS, // Number of objects\r
+ 0x00, // State mask reset value\r
+ TSL_STATE_NOT_CHANGED // Current state\r
+};\r
+\r
+//-------------------------------------------\r
+// TSL Common Parameters placed in RAM or ROM\r
+// --> external declaration in tsl_conf.h\r
+//-------------------------------------------\r
+\r
+TSL_Params_T TSL_Params =\r
+{\r
+ TSLPRM_ACQ_MIN,\r
+ TSLPRM_ACQ_MAX,\r
+ TSLPRM_CALIB_SAMPLES,\r
+ TSLPRM_DTO,\r
+#if TSLPRM_TOTAL_TKEYS > 0 \r
+ MyTKeys_StateMachine, // Default state machine for TKeys\r
+ &MyTKeys_Methods, // Default methods for TKeys\r
+#endif\r
+#if TSLPRM_TOTAL_LNRTS > 0\r
+ MyLinRots_StateMachine, // Default state machine for LinRots\r
+ &MyLinRots_Methods // Default methods for LinRots\r
+#endif\r
+};\r
+\r
+\r
+/* Private functions prototype -----------------------------------------------*/\r
+\r
+void TSL_user_InitGPIOs(void);\r
+void TSL_user_SetThresholds(void);\r
+\r
+/* Global variables ----------------------------------------------------------*/\r
+\r
+TSL_tTick_ms_T ECS_last_tick; // Hold the last time value for ECS\r
+uint32_t process_sensor; // asserted when there is no ECS => a finger is on the linear sensor\r
+\r
+\r
+/**\r
+ * @brief Initialize the STMTouch Driver\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_user_Init(void)\r
+{\r
+#if TSLPRM_USE_SHIELD == 0\r
+ TSL_user_InitGPIOs();\r
+#endif\r
+\r
+ TSL_obj_GroupInit(&MyObjGroup); // Init Objects\r
+ \r
+ TSL_Init(MyBanks); // Init timing and acquisition modules\r
+ \r
+ TSL_user_SetThresholds(); // Init thresholds for each object individually\r
+}\r
+\r
+\r
+/**\r
+ * @brief Execute STMTouch Driver main State machine\r
+ * @param None\r
+ * @retval status Return TSL_STATUS_OK if the acquisition is done\r
+ */\r
+TSL_Status_enum_T TSL_user_Action(void)\r
+{\r
+ static uint8_t idx_bank=0;\r
+ static uint8_t ConfigDone=0;\r
+ TSL_Status_enum_T status;\r
+ \r
+ if(!ConfigDone)\r
+ {\r
+ // Configure Bank\r
+ TSL_acq_BankConfig(idx_bank);\r
+ \r
+ // Start Bank acquisition\r
+ TSL_acq_BankStartAcq();\r
+ \r
+ // Set flag\r
+ ConfigDone=1;\r
+ }\r
+ \r
+ // Check Bank End of Acquisition\r
+ if (TSL_acq_BankWaitEOC() == TSL_STATUS_OK)\r
+ {\r
+ // Get Bank Result\r
+ TSL_acq_BankGetResult(idx_bank, 0, 0);\r
+ ConfigDone=0;\r
+ idx_bank++;\r
+ }\r
+ \r
+\r
+ if(idx_bank == TSLPRM_TOTAL_BANKS)\r
+ {\r
+ idx_bank=0;\r
+ \r
+ // Process Objects\r
+ TSL_obj_GroupProcess(&MyObjGroup);\r
+ \r
+ // DxS processing\r
+ // Warning: TSLPRM_USE_DXS must be set !!!\r
+ TSL_dxs_FirstObj(&MyObjGroup);\r
+\r
+ // ECS every 100ms\r
+ if (TSL_tim_CheckDelay_ms(100, &ECS_last_tick) == TSL_STATUS_OK)\r
+ {\r
+ LED_BLUE_TOGGLE;\r
+ if (TSL_ecs_Process(&MyObjGroup) == TSL_STATUS_OK)\r
+ {\r
+ LED_GREEN_ON;\r
+ process_sensor = 0;\r
+ }\r
+ else\r
+ {\r
+ LED_GREEN_OFF;\r
+ process_sensor = 1;\r
+ }\r
+ }\r
+\r
+ \r
+ status = TSL_STATUS_OK; // All banks have been acquired and sensors processed\r
+ \r
+ }\r
+ else\r
+ {\r
+ status = TSL_STATUS_BUSY;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Manage the activity on sensors when touched/released (example)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ProcessSensors(void)\r
+{\r
+ uint16_t Max_Value = 256/(9-TSLPRM_LINROT_RESOLUTION);\r
+\r
+ uint16_t Message[6]; \r
+ uint32_t percent_value;\r
+ Message[0] = ' ';\r
+ Message[1] = ' ';\r
+ Message[2] = ' ';\r
+ /*Add "%" in message*/ \r
+ Message[3] = '°' ;\r
+ Message[4] = '/' ;\r
+ Message[5] = '%' ;\r
+\r
+ if (!process_sensor) \r
+ {\r
+ /*Display message*/\r
+ LCD_GLASS_DisplayStrDeci(Message); \r
+ return;\r
+ }\r
+ \r
+ /* get Slider position and convert it in percent*/\r
+ percent_value = MyLinRots[0].p_Data->Position ;\r
+ percent_value *= 10000;\r
+ percent_value /= Max_Value;\r
+ /*Convert percent value in char and store it in message*/ \r
+ convert_into_char(percent_value,Message);\r
+ /*Add "%" in message*/ \r
+ Message[3] = '°' ;\r
+ Message[4] = '/' ;\r
+ Message[5] = '%' ;\r
+ /*Display message*/\r
+ LCD_GLASS_DisplayStrDeci(Message); \r
+ \r
+}\r
+\r
+/**\r
+ * @brief Manage the activity on sensors when touched/released (example)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ProcessSensorsButtons(void)\r
+{\r
+ uint8_t Message[6]; \r
+ \r
+ /* Prepare Message to display*/\r
+ Message[0] = ' ';\r
+ Message[1] = '0';\r
+ Message[2] = '0';\r
+ Message[3] = '0';\r
+ Message[4] = '0';\r
+ Message[5] = ' ';\r
+\r
+ if (process_sensor) \r
+ {\r
+ \r
+ #ifdef STM32L1XX_MDP // for medium density plus device\r
+ if( MyLinRots[0].p_Data->Position > 118 )\r
+ Message[4] = 255; \r
+ else if( MyLinRots[0].p_Data->Position > 80 ) \r
+ Message[3] = 255; \r
+ else if( MyLinRots[0].p_Data->Position > 5 ) \r
+ Message[2] = 255; \r
+ else \r
+ Message[1] = 255; \r
+ #else // for medium density device\r
+ if( MyLinRots[0].p_Data->Position < 127 )\r
+ {\r
+ if( MyLinRots[0].p_Data->Position > 110 )\r
+ Message[4] = 255; \r
+ else if( MyLinRots[0].p_Data->Position > 80 ) \r
+ Message[3] = 255; \r
+ else if( MyLinRots[0].p_Data->Position > 5 ) \r
+ Message[2] = 255; \r
+ else \r
+ Message[1] = 255; \r
+ }\r
+ #endif \r
+\r
+ }\r
+ LCD_GLASS_DisplayString(Message);\r
+ \r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Initializes the TouchSensing GPIOs.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_user_InitGPIOs(void)\r
+{\r
+ // Configure the Shield IO (PX.y) to ground when not used.\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set thresholds for each object (optional).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TSL_user_SetThresholds(void)\r
+{\r
+ // Example: Decrease the Detect thresholds for the TKEY 0\r
+ //MyTKeys_Param[0].DetectInTh -= 10;\r
+ //MyTKeys_Param[0].DetectOutTh -= 10;\r
+ \r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / commitdiff