\r
/* FreeRTOS includes. */\r
#include "FreeRTOS.h"\r
-#include "Task.h"\r
+#include "task.h"\r
\r
/* Xilinx includes. */\r
#include "xscutimer.h"\r
/* Enable Auto reload mode. */\r
XScuTimer_EnableAutoReload( &xTimer );\r
\r
+ /* Ensure there is no prescale. */\r
+ XScuTimer_SetPrescaler( &xTimer, 0 );\r
+\r
/* Load the timer counter register. */\r
XScuTimer_LoadTimer( &xTimer, XSCUTIMER_CLOCK_HZ / configTICK_RATE_HZ );\r
\r
#include "recmutex.h"\r
#include "death.h"\r
#include "partest.h"\r
-#include "comtest2.h"\r
-#include "serial.h"\r
#include "TimerDemo.h"\r
#include "QueueOverwrite.h"\r
#include "IntQueue.h"\r
{\r
/* An error has been detected in one of the tasks - flash the LED\r
at a higher frequency to give visible feedback that something has\r
- gone wrong (it might just be that the loop back connector required\r
- by the comtest tasks has not been fitted). */\r
+ gone wrong. */\r
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
}\r
}\r
xPeriod = xMinPeriod;\r
}\r
\r
+ /* Change the timer period and start the timer. */\r
xTimerChangePeriod( xTimer, xPeriod, portMAX_DELAY );\r
- xTimerStart( xTimer, portMAX_DELAY );\r
\r
/* Block waiting for the notification again with a different period.\r
Sometimes the period will be higher than the tasks block time, sometimes\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-#ifndef FREERTOS_CONFIG_H\r
-#define FREERTOS_CONFIG_H\r
-\r
-#include "xparameters.h"\r
-\r
-/*-----------------------------------------------------------\r
- * Application specific definitions.\r
- *\r
- * These definitions should be adjusted for your particular hardware and\r
- * application requirements.\r
- *\r
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
- *\r
- * See http://www.freertos.org/a00110.html.\r
- *----------------------------------------------------------*/\r
-\r
-#define configUSE_PREEMPTION 1\r
-#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 0\r
-#define configCPU_CLOCK_HZ ( ( unsigned long ) 100000000 )\r
-#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
-#define configMAX_PRIORITIES ( 4 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) )\r
-#define configMAX_TASK_NAME_LEN ( 5 )\r
-#define configUSE_TRACE_FACILITY 0\r
-#define configUSE_16_BIT_TICKS 0\r
-#define configIDLE_SHOULD_YIELD 0\r
-\r
-/* Co-routine definitions. */\r
-#define configUSE_CO_ROUTINES 0\r
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
-\r
-/* Set the following definitions to 1 to include the API function, or zero\r
-to exclude the API function. */\r
-\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 0\r
-#define INCLUDE_vTaskCleanUpResources 0\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
-\r
-\r
-#endif /* FREERTOS_CONFIG_H */\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*-----------------------------------------------------------\r
- * Simple parallel port IO routines.\r
- *-----------------------------------------------------------*/\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-\r
-/* Demo application includes. */\r
-#include "partest.h"\r
-\r
-/* Library includes. */\r
-#include "xgpio_l.h"\r
-\r
-/* Misc hardware specific definitions. */\r
-#define partstALL_AS_OUTPUT 0x00\r
-#define partstCHANNEL_1 0x01\r
-#define partstMAX_4BIT_LED 0x03\r
-\r
-/* The outputs are split into two IO sections, these variables maintain the \r
-current value of either section. */\r
-static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit;\r
-\r
-/*-----------------------------------------------------------*/\r
-/*\r
- * Setup the IO for the LED outputs.\r
- */\r
-void vParTestInitialise( void )\r
-{\r
- /* Set both sets of LED's on the demo board to outputs. */\r
- XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );\r
- XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );\r
-\r
- /* Start with all outputs off. */\r
- uxCurrentOutput4Bit = 0;\r
- XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 );\r
- uxCurrentOutput5Bit = 0;\r
- XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
-{\r
-unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;\r
-\r
- portENTER_CRITICAL();\r
- {\r
- /* Which IO section does the LED being set/cleared belong to? The\r
- 4 bit or 5 bit outputs? */\r
- if( uxLED <= partstMAX_4BIT_LED )\r
- {\r
- uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;\r
- puxCurrentValue = &uxCurrentOutput4Bit;\r
- } \r
- else\r
- {\r
- uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;\r
- puxCurrentValue = &uxCurrentOutput5Bit;\r
- uxLED -= partstMAX_4BIT_LED;\r
- }\r
-\r
- /* Setup the bit mask accordingly. */\r
- uxLED = 0x01 << uxLED;\r
-\r
- /* Maintain the current output value. */\r
- if( xValue )\r
- {\r
- *puxCurrentValue |= uxLED;\r
- }\r
- else\r
- {\r
- *puxCurrentValue &= ~uxLED;\r
- }\r
-\r
- /* Write the value to the port. */\r
- XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );\r
- }\r
- portEXIT_CRITICAL();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
-{\r
-unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;\r
-\r
- portENTER_CRITICAL();\r
- {\r
- /* Which IO section does the LED being toggled belong to? The\r
- 4 bit or 5 bit outputs? */\r
- if( uxLED <= partstMAX_4BIT_LED )\r
- {\r
- uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;\r
- puxCurrentValue = &uxCurrentOutput4Bit;\r
- } \r
- else\r
- {\r
- uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;\r
- puxCurrentValue = &uxCurrentOutput5Bit;\r
- uxLED -= partstMAX_4BIT_LED;\r
- }\r
-\r
- /* Setup the bit mask accordingly. */\r
- uxLED = 0x01 << uxLED;\r
-\r
- /* Maintain the current output value. */\r
- if( *puxCurrentValue & uxLED )\r
- {\r
- *puxCurrentValue &= ~uxLED;\r
- }\r
- else\r
- {\r
- *puxCurrentValue |= uxLED;\r
- }\r
-\r
- /* Write the value to the port. */\r
- XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );\r
- }\r
- portEXIT_CRITICAL();\r
-}\r
-\r
-\r
+++ /dev/null
- -pe microblaze_0 RTOSDemo/executable.elf\r
+++ /dev/null
- -p virtex4\r
+++ /dev/null
- -p virtex4 -lang vhdl -st xst\r
+++ /dev/null
-microblaze_0\r
-RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c \r
-RTOSDEMO_HEADERS = FreeRTOSConfig.h \r
-RTOSDEMO_CC = mb-gcc\r
-RTOSDEMO_CC_SIZE = mb-size\r
-RTOSDEMO_CC_OPT = -Os\r
-RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall\r
-RTOSDEMO_CC_SEARCH = # -B\r
-RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L\r
-RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze \r
-RTOSDEMO_LFLAGS = # -l\r
-RTOSDEMO_CC_PREPROC_FLAG = # -Wp,\r
-RTOSDEMO_CC_ASM_FLAG = # -Wa,\r
-RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map \r
-RTOSDEMO_LINKER_SCRIPT = \r
-RTOSDEMO_CC_DEBUG_FLAG = -g \r
-RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt\r
-RTOSDEMO_MODE = executable\r
-RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0\r
-RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul \r
-RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=\r
-RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=\r
- $(RTOSDEMO_CC_SOFTMUL_FLAG) \\r
+++ /dev/null
- -p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti\r
+++ /dev/null
-microblaze_0\r
-TESTAPP_PERIPHERAL_SOURCES = TestApp_Peripheral/src/TestApp_Peripheral.c TestApp_Peripheral/src/xuartlite_selftest_example.c \r
-TESTAPP_PERIPHERAL_HEADERS = \r
-TESTAPP_PERIPHERAL_CC = mb-gcc\r
-TESTAPP_PERIPHERAL_CC_SIZE = mb-size\r
-TESTAPP_PERIPHERAL_CC_OPT = -O2\r
-TESTAPP_PERIPHERAL_CFLAGS = \r
-TESTAPP_PERIPHERAL_CC_SEARCH = # -B\r
-TESTAPP_PERIPHERAL_LIBPATH = -L./microblaze_0/lib/ # -L\r
-TESTAPP_PERIPHERAL_INCLUDES = -I./microblaze_0/include/ # -I\r
-TESTAPP_PERIPHERAL_LFLAGS = # -l\r
-TESTAPP_PERIPHERAL_CC_PREPROC_FLAG = # -Wp,\r
-TESTAPP_PERIPHERAL_CC_ASM_FLAG = # -Wa,\r
-TESTAPP_PERIPHERAL_CC_LINKER_FLAG = # -Wl,\r
-TESTAPP_PERIPHERAL_LINKER_SCRIPT = TestApp_Peripheral/src/TestApp_Peripheral_LinkScr\r
-TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g \r
-TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -mxl-gp-opt\r
-TESTAPP_PERIPHERAL_MODE = executable\r
-TESTAPP_PERIPHERAL_LIBG_OPT = -$(TESTAPP_PERIPHERAL_MODE) microblaze_0\r
-TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG= -mno-xl-soft-mul \r
-TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=\r
-TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=\r
- $(TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG) \\r
+++ /dev/null
- -p xc4vfx12ff668-10\r
+++ /dev/null
--device xc4vfx12ff668-10\r
+++ /dev/null
-setMode -bs\r
-setCable -port auto\r
-identify\r
-identifyMPM\r
-setAttribute -position 3 -attr configFileName -value "implementation/download.bit"\r
-program -p 3 \r
-quit\r
+++ /dev/null
-###################################-*-asm*-
-#
-# Copyright (c) 2001 Xilinx, Inc. All rights reserved.
-#
-# Xilinx, Inc. CONFIDENTIAL
-#
-# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
-# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
-# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
-# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
-# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
-# AND FITNESS FOR A PARTICULAR PURPOSE.
-#
-# crt0.s
-#
-# C RunTime:
-# Used for initialization of small data
-# anchors and stack for programs compiled using
-# Xilinx Gnu Tools. This routine also intializes the
-# exception and interrupt handlers
-#
-# $Id: crt0.s,v 1.1.4.2 2005/05/26 21:50:39 vasanth Exp $
-#
-#######################################
-
-/* Vector map (Interrupts, Exceptions, Breakpoints) */
-# # 0x00 # Jump to Start
-# # 0x04 # nop
-# # 0x08 # Imm instr for soft exception address [Hi halfword]
-# # 0x0c # Jump to sof Exception handler [Lo halfword]
-# # 0x10 # Imm instr for interrupt address [Hi halfword]
-# # 0x14 # Jump to interrupt handler [Lo halfword]
-# # 0x18 # nop - Reserved for breakpoint vector
-# # 0x1C # nop - Reserved for breakpoint vector
-# # 0x20 # Imm instr for hw exception address [Hi halfword]
-# # 0x24 # Jump instr to hw exception handler [Lo halfword]
-
- .globl _start
-
-/* Set the exception and interrupt address vectors */
-/* to jump to the appropriate handlers */
-
- .align 2
- .ent _start
- _start:
- bri _start1 # 0x00
- nop # 0x04
- nop # 0x08 # Reserve space for software exception vector
- nop # 0x0c
- nop # 0x10 # Reserve space for interrupt vector
- nop # 0x14
- nop # 0x18 # Reserve space for breakpoint vector
- nop # 0x1c
- nop # 0x18 # Reserve space for hw exception vector
- nop # 0x1c
-
- _start1:
-/* Set the Small Data Anchors and the Stack pointer */
- la r13, r0, _SDA_BASE_
- la r2, r0, _SDA2_BASE_
- la r1, r0, _stack-16 # 16 bytes (4 words are needed by
- # crt for args and link reg )
-
-/* Set the opcodes brai and imm for handlers */
- la r6,r0,0xb8080000 # [opcode for brai ]
- swi r6,r0,0x4 # [brai opcode for reset]
- swi r6,r0,0xc # [brai opcode for exception]
- swi r6,r0,0x14 # [brai opcode for interrupt]
- swi r6,r0,0x24 # [brai opcode for hw exceptions]
-
- la r6,r0,0xb0000000 # [opcode for imm ]
- swi r6,r0,0x0 # [imm opcode for reset]
- swi r6,r0,0x8 # [imm opcode for exception]
- swi r6,r0,0x10 # [imm opocde for interrupt]
- swi r6,r0,0x20 # [imm opocde for hw exceptions]
-
-/* Set Reset vector */
- la r6,r0,_start1
- sw r6,r1,r0
- lhu r7,r1,r0
- shi r7,r0, 0x2 # [imm for reset]
- shi r6,r0, 0x6 # [lower half for reset]
-
-/* Set Software Exception Handler */
- la r6,r0,_exception_handler
- sw r6,r1,r0
- lhu r7,r1,r0
- shi r7,r0, 0xa # [imm for exception]
- shi r6,r0, 0xe # [lower half for exception ]
-
-/* Set Interrupt Handler */
- la r6,r0,_interrupt_handler
- sw r6,r1,r0
- lhu r7,r1,r0
- shi r7,r0, 0x12 # [imm for exception]
- shi r6,r0, 0x16 # [lower half for intterupt ]
-
-/* Set HW Exception Handler */
- la r6,r0,_hw_exception_handler
- sw r6,r1,r0
- lhu r7,r1,r0
- shi r7,r0, 0x22 # [imm for exception]
- shi r6,r0, 0x26 # [lower half for hw exception]
-
-/* initialize bss sections */
- brlid r15,_crtinit
- nop
-
-/* Adjust the stack pointer */
- addi r1,r1,16
-
-/* Fall through to exit */
- .end _start
-
-/* Use this exit function */
- .globl exit # exit library call
- .ent exit
-exit:
- bri exit
- .end exit
-
+++ /dev/null
-############################################################################\r
-## This system.ucf file is generated by Base System Builder based on the\r
-## settings in the selected Xilinx Board Definition file. Please add other\r
-## user constraints to this file based on customer design specifications.\r
-############################################################################\r
-\r
-Net sys_clk_pin LOC=AE14;\r
-Net sys_clk_pin IOSTANDARD = LVCMOS33;\r
-Net sys_rst_pin LOC=D6;\r
-Net sys_rst_pin PULLUP;\r
-## System level constraints\r
-Net sys_clk_pin TNM_NET = sys_clk_pin;\r
-TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;\r
-Net sys_rst_pin TIG;\r
-\r
-## FPGA pin constraints\r
-Net fpga_0_RS232_Uart_RX_pin LOC=W2;\r
-Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;\r
-Net fpga_0_RS232_Uart_TX_pin LOC=W1;\r
-Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;\r
+++ /dev/null
--g ConfigRate:4
--g CclkPin:PULLUP
--g TdoPin:PULLNONE
--g M1Pin:PULLDOWN
--g DonePin:PULLUP
--g DriveDone:No
--g StartUpClk:JTAGCLK
--g DONE_cycle:4
--g GTS_cycle:5
--g M0Pin:PULLUP
--g M2Pin:PULLUP
--g ProgPin:PULLUP
--g TckPin:PULLUP
--g TdiPin:PULLUP
--g TmsPin:PULLUP
--g DonePipe:No
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:NONE
--m
--g Persist:No
+++ /dev/null
--g CclkPin:PULLUP
--g TdoPin:PULLNONE
--g M1Pin:PULLDOWN
--g DonePin:PULLUP
--g StartUpClk:JTAGCLK
--g M0Pin:PULLUP
--g M2Pin:PULLUP
--g ProgPin:PULLUP
--g TckPin:PULLUP
--g TdiPin:PULLUP
--g TmsPin:PULLUP
--g LCK_cycle:NoWait
--g Security:NONE
--m
--g Persist:No
+++ /dev/null
-setMode -bscan\r
-setCable -p auto\r
-identify\r
-assignfile -p 3 -file implementation/download.bit\r
-program -p 3\r
-quit\r
+++ /dev/null
-FLOWTYPE = FPGA;
-###############################################################
-## Filename: fast_runtime.opt
-##
-## Option File For Xilinx FPGA Implementation Flow for Fast
-## Runtime.
-##
-## Version: 4.1.1
-###############################################################
-#
-# Options for Translator
-#
-# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
-#
-Program ngdbuild
--p <partname>; # Partname to use - picked from xflow commandline
--nt timestamp; # NGO File generation. Regenerate only when
- # source netlist is newer than existing
- # NGO file (default)
--bm <design>.bmm # Block RAM memory map file
-<userdesign>; # User design - pick from xflow command line
--uc <design>.ucf; # ucf constraints
-<design>.ngd; # Name of NGD file. Filebase same as design filebase
-End Program ngdbuild
-
-#
-# Options for Mapper
-#
-# Type "map -h <arch>" for a detailed list of map command line options
-#
-Program map
--o <design>_map.ncd; # Output Mapped ncd file
--pr b; # Pack internal FF/latches into IOBs
-#-fp <design>.mfp; # Floorplan file
-<inputdir><design>.ngd; # Input NGD file
-<inputdir><design>.pcf; # Physical constraints file
-END Program map
-
-#
-# Options for Post Map Trace
-#
-# Type "trce -h" for a detailed list of trce command line options
-#
-Program post_map_trce
--e 3; # Produce error report limited to 3 items per constraint
-#-o <design>_map.twr; # Output trace report file
--xml <design>_map.twx; # Output XML version of the timing report
-#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
-<inputdir><design>_map.ncd; # Input mapped ncd
-<inputdir><design>.pcf; # Physical constraints file
-END Program post_map_trce
-
-#
-# Options for Place and Route
-#
-# Type "par -h" for a detailed list of par command line options
-#
-Program par
--w; # Overwrite existing placed and routed ncd
--ol high; # Overall effort level
-<inputdir><design>_map.ncd; # Input mapped NCD file
-<design>.ncd; # Output placed and routed NCD
-<inputdir><design>.pcf; # Input physical constraints file
-END Program par
-
-#
-# Options for Post Par Trace
-#
-# Type "trce -h" for a detailed list of trce command line options
-#
-Program post_par_trce
--e 3; # Produce error report limited to 3 items per constraint
-#-o <design>.twr; # Output trace report file
--xml <design>.twx; # Output XML version of the timing report
-#-tsi <design>.tsi; # Produce Timing Specification Interaction report
-<inputdir><design>.ncd; # Input placed and routed ncd
-<inputdir><design>.pcf; # Physical constraints file
-END Program post_par_trce
-
-
+++ /dev/null
-connect mb mdm -cable type xilinx_parallel port LPT1 frequency 5000000 -debugdevice cpunr 1\r
+++ /dev/null
-#error This project has been reworked for use with a later version of the Xilinx tools and IP. Please find more up to date projects in other FreeRTOS/Demo/MicroBlaze_nnn directories.\r
-\r
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * Creates all the demo application tasks, then starts the scheduler. The WEB\r
- * documentation provides more details of the standard demo application tasks.\r
- *\r
- * In addition to the standard tasks, main() creates two "Register Check" \r
- * tasks. These tasks write known values into every general purpose register,\r
- * then check each register to ensure it still contains the expected (written)\r
- * value. The register check tasks operate at the idle priority so will get\r
- * repeatedly preempted. A register being found to contain an incorrect value\r
- * following such a preemption would be indicative of an error in the context\r
- * switch mechanism.\r
- * \r
- * Main.c also creates a task called "Check". This only executes every three \r
- * seconds but has the highest priority so is guaranteed to get processor time. \r
- * Its main function is to check that all the other tasks are still operational.\r
- * Each task (other than the "flash" tasks) maintains a unique count that is \r
- * incremented each time the task successfully completes its function. Should \r
- * any error occur within such a task the count is permanently halted. The \r
- * check task inspects the count of each task to ensure it has changed since\r
- * the last time the check task executed. If all the count variables have \r
- * changed all the tasks are still executing error free, and the check task\r
- * toggles the onboard LED. Should any task contain an error at any time \r
- * the LED toggle rate will change from 3 seconds to 500ms.\r
- *\r
- */\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Demo application includes. */\r
-#include "partest.h"\r
-#include "flash.h"\r
-#include "comtest2.h"\r
-#include "integer.h"\r
-#include "semtest.h"\r
-#include "BlockQ.h"\r
-#include "dynamic.h"\r
-#include "PollQ.h"\r
-\r
-/* Hardware library includes. */\r
-#include <xintc.h>\r
-\r
-/* The rate at which the 'check' LED will flash when no errors have been\r
-detected. */\r
-#define mainNO_ERROR_CHECK_PERIOD 3000\r
-\r
-/* The rate at which the 'check' LED will flash when an error has been\r
-detected in one of the demo tasks. */\r
-#define mainERROR_CHECK_PERIOD 500\r
-\r
-/* Demo application task priorities. */\r
-#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-\r
-/* Software cannot influence the BAUD rate used by the simple UART \r
-implementation. */\r
-#define mainBAUD_RATE 0\r
-\r
-/* The LED flashed by the 'check' task to indicate the system status. */\r
-#define mainCHECK_TASK_LED 3\r
-\r
-/* The first LED flashed by the COM port test tasks. LED mainCOM_TEST_LED + 1\r
-will also be used. */\r
-#define mainCOM_TEST_LED 4\r
-\r
-/* The register test task does not make any function calls so does not require\r
-much stack at all. */\r
-#define mainTINY_STACK 70\r
-\r
-/*\r
- * The task that executes at the highest priority and calls \r
- * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
- * of the file.\r
- */\r
-static void vErrorChecks( void *pvParameters );\r
-\r
-/*\r
- * Checks that all the demo application tasks are still executing without error\r
- * - as described at the top of the file.\r
- */\r
-static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void );\r
-\r
-/*\r
- * The register test task as described at the top of this file.\r
- */\r
-static void vRegisterTest( void *pvParameters );\r
-\r
-/*\r
- * Perform any necessary hardware configuration.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
-/* Set to pdFAIL should an error be discovered in the register test tasks. */\r
-static unsigned long ulRegisterTestStatus = pdPASS;\r
-const unsigned long *pulStatusAddr = &ulRegisterTestStatus;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Create all the demo tasks - then start the scheduler.\r
- */\r
-int main (void) \r
-{\r
- /* When re-starting a debug session (rather than cold booting) we want\r
- to ensure the installed interrupt handlers do not execute until after the\r
- scheduler has been started. */\r
- portDISABLE_INTERRUPTS();\r
-\r
- prvSetupHardware();\r
-\r
- /* Start the standard demo application tasks. */\r
- vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
- vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED );\r
- vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
- vStartDynamicPriorityTasks();\r
- vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
- \r
- /* Create two register check tasks - using a different parameter for each.\r
- The parameter is used to generate the known values written to the registers. */\r
- #if configUSE_PREEMPTION == 1\r
- xTaskCreate( vRegisterTest, "Reg1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( vRegisterTest, "Reg2", mainTINY_STACK, ( void * ) 20, tskIDLE_PRIORITY, NULL );\r
- #endif\r
-\r
- /* Create the 'check' task that is defined in this file. */\r
- xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
-\r
- /* Finally start the scheduler. */\r
- vTaskStartScheduler();\r
-\r
- /* Should not get here as the processor is now under control of the \r
- scheduler! */\r
-\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void vErrorChecks( void *pvParameters )\r
-{\r
-TickType_t xDelayPeriod = mainNO_ERROR_CHECK_PERIOD;\r
-\r
- /* The parameters are not used. */\r
- ( void ) pvParameters;\r
-\r
- /* Cycle for ever, delaying then checking all the other tasks are still\r
- operating without error. The delay period used will depend on whether\r
- or not an error has been discovered in one of the demo tasks. */\r
- for( ;; )\r
- {\r
- vTaskDelay( xDelayPeriod );\r
- if( !prvCheckOtherTasksAreStillRunning() )\r
- {\r
- /* An error has been found. Shorten the delay period to make\r
- the LED flash faster. */\r
- xDelayPeriod = mainERROR_CHECK_PERIOD;\r
- }\r
-\r
- vParTestToggleLED( mainCHECK_TASK_LED );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void )\r
-{\r
-static portBASE_TYPE xAllTestsPass = pdTRUE;\r
-\r
- /* Return pdFALSE if any demo application task set has encountered\r
- an error. */\r
-\r
- if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
- {\r
- xAllTestsPass = pdFALSE;\r
- }\r
-\r
- if( xAreComTestTasksStillRunning() != pdTRUE )\r
- {\r
- xAllTestsPass = pdFALSE;\r
- }\r
-\r
- if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- xAllTestsPass = pdFALSE;\r
- }\r
-\r
- if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
- {\r
- xAllTestsPass = pdFAIL;\r
- }\r
-\r
- if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
- {\r
- xAllTestsPass = ( long ) pdFAIL;\r
- }\r
-\r
- if( xArePollingQueuesStillRunning() != pdTRUE )\r
- {\r
- xAllTestsPass = ( long ) pdFAIL;\r
- }\r
-\r
- /* Mutual exclusion on this variable is not necessary as we only read it. */\r
- if( ulRegisterTestStatus != pdPASS )\r
- {\r
- xAllTestsPass = pdFALSE;\r
- }\r
-\r
- return xAllTestsPass;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupHardware( void )\r
-{\r
- /* Ensure the interrupt controller is enabled in order that subsequent \r
- code can successfully configure the peripherals. */\r
- XIntc_mMasterEnable( XPAR_OPB_INTC_0_BASEADDR );\r
-\r
- /* Initialise the GPIO used for the LED's. */\r
- vParTestInitialise();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void vRegisterTest( void *pvParameters )\r
-{\r
- for( ;; )\r
- {\r
- /* Fill the registers with their register number plus the offset \r
- (added) value. The added value is passed in as a parameter so\r
- is contained in r5. */\r
- asm volatile ( "addi r3, r5, 3 \n\t" \\r
- "addi r4, r5, 4 \n\t" \\r
- "addi r6, r5, 6 \n\t" \\r
- "addi r7, r5, 7 \n\t" \\r
- "addi r8, r5, 8 \n\t" \\r
- "addi r9, r5, 9 \n\t" \\r
- "addi r10, r5, 10 \n\t" \\r
- "addi r11, r5, 11 \n\t" \\r
- "addi r12, r5, 12 \n\t" \\r
- "addi r16, r5, 16 \n\t" \\r
- "addi r17, r5, 17 \n\t" \\r
- "addi r18, r5, 18 \n\t" \\r
- "addi r19, r5, 19 \n\t" \\r
- "addi r20, r5, 20 \n\t" \\r
- "addi r21, r5, 21 \n\t" \\r
- "addi r22, r5, 22 \n\t" \\r
- "addi r23, r5, 23 \n\t" \\r
- "addi r24, r5, 24 \n\t" \\r
- "addi r25, r5, 25 \n\t" \\r
- "addi r26, r5, 26 \n\t" \\r
- "addi r27, r5, 27 \n\t" \\r
- "addi r28, r5, 28 \n\t" \\r
- "addi r29, r5, 29 \n\t" \\r
- "addi r30, r5, 30 \n\t" \\r
- "addi r31, r5, 31 \n\t"\r
- );\r
-\r
- /* Now read back the register values to ensure they are as we expect. \r
- This task will get preempted frequently so other tasks are likely to\r
- have executed since the register values were written. */\r
-\r
- /* r3 should contain r5 + 3. Subtract 3 to leave r3 equal to r5. */\r
- asm volatile ( "addi r3, r3, -3 " );\r
-\r
- /* Compare r3 and r5. If they are not equal then either r3 or r5\r
- contains the wrong value and *pulStatusAddr is to pdFAIL. */\r
- asm volatile ( "cmp r3, r3, r5 \n\t" \\r
- "beqi r3, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \r
- );\r
-\r
- /* Repeat for all the other registers. */\r
- asm volatile ( "addi r4, r4, -4 \n\t" \\r
- "cmp r4, r4, r5 \n\t" \\r
- "beqi r4, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r6, r6, -6 \n\t" \\r
- "cmp r6, r6, r5 \n\t" \\r
- "beqi r6, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r7, r7, -7 \n\t" \\r
- "cmp r7, r7, r5 \n\t" \\r
- "beqi r7, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r8, r8, -8 \n\t" \\r
- "cmp r8, r8, r5 \n\t" \\r
- "beqi r8, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r9, r9, -9 \n\t" \\r
- "cmp r9, r9, r5 \n\t" \\r
- "beqi r9, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r10, r10, -10 \n\t" \\r
- "cmp r10, r10, r5 \n\t" \\r
- "beqi r10, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r11, r11, -11 \n\t" \\r
- "cmp r11, r11, r5 \n\t" \\r
- "beqi r11, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r12, r12, -12 \n\t" \\r
- "cmp r12, r12, r5 \n\t" \\r
- "beqi r12, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r16, r16, -16 \n\t" \\r
- "cmp r16, r16, r5 \n\t" \\r
- "beqi r16, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r17, r17, -17 \n\t" \\r
- "cmp r17, r17, r5 \n\t" \\r
- "beqi r17, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r18, r18, -18 \n\t" \\r
- "cmp r18, r18, r5 \n\t" \\r
- "beqi r18, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r19, r19, -19 \n\t" \\r
- "cmp r19, r19, r5 \n\t" \\r
- "beqi r19, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r20, r20, -20 \n\t" \\r
- "cmp r20, r20, r5 \n\t" \\r
- "beqi r20, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r21, r21, -21 \n\t" \\r
- "cmp r21, r21, r5 \n\t" \\r
- "beqi r21, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r22, r22, -22 \n\t" \\r
- "cmp r22, r22, r5 \n\t" \\r
- "beqi r22, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r23, r23, -23 \n\t" \\r
- "cmp r23, r23, r5 \n\t" \\r
- "beqi r23, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r24, r24, -24 \n\t" \\r
- "cmp r24, r24, r5 \n\t" \\r
- "beqi r24, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r25, r25, -25 \n\t" \\r
- "cmp r25, r25, r5 \n\t" \\r
- "beqi r25, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r26, r26, -26 \n\t" \\r
- "cmp r26, r26, r5 \n\t" \\r
- "beqi r26, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r27, r27, -27 \n\t" \\r
- "cmp r27, r27, r5 \n\t" \\r
- "beqi r27, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r28, r28, -28 \n\t" \\r
- "cmp r28, r28, r5 \n\t" \\r
- "beqi r28, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r29, r29, -29 \n\t" \\r
- "cmp r29, r29, r5 \n\t" \\r
- "beqi r29, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r30, r30, -30 \n\t" \\r
- "cmp r30, r30, r5 \n\t" \\r
- "beqi r30, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t" \\r
- "addi r31, r31, -31 \n\t" \\r
- "cmp r31, r31, r5 \n\t" \\r
- "beqi r31, 12 \n\t" \\r
- "lwi r3, r0, pulStatusAddr \n\t" \\r
- "sw r0, r0, r3 \n\t"\r
- );\r
- }\r
-}\r
-\r
-\r
-\r
+++ /dev/null
--p\r
-xc4vfx12ff668-10\r
--lang\r
-vhdl\r
--st\r
-xst\r
-system.mhs\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-\r
-/* \r
- BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART\r
-*/\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "queue.h"\r
-#include "task.h"\r
-\r
-/* Demo application includes. */\r
-#include "serial.h"\r
-\r
-/* Microblaze driver includes. */\r
-#include "xuartlite_l.h"\r
-#include "xintc_l.h"\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Queues used to hold received characters, and characters waiting to be\r
-transmitted. */\r
-static QueueHandle_t xRxedChars; \r
-static QueueHandle_t xCharsForTx; \r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
-{\r
-unsigned long ulControlReg, ulMask;\r
-\r
- /* NOTE: The baud rate used by this driver is determined by the hardware\r
- parameterization of the UART Lite peripheral, and the baud value passed to\r
- this function has no effect. */\r
-\r
- /* Create the queues used to hold Rx and Tx characters. */\r
- xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
- xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
-\r
- if( ( xRxedChars ) && ( xCharsForTx ) )\r
- {\r
- /* Disable the interrupt. */\r
- XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );\r
- \r
- /* Flush the fifos. */\r
- ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );\r
- XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );\r
-\r
- /* Enable the interrupt again. The interrupt controller has not yet been \r
- initialised so there is no chance of receiving an interrupt until the \r
- scheduler has been started. */\r
- XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );\r
-\r
- /* Enable the interrupt in the interrupt controller while maintaining \r
- all the other bit settings. */\r
- ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );\r
- ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;\r
- XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );\r
- XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );\r
- }\r
- \r
- return ( xComPortHandle ) 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )\r
-{\r
- /* The port handle is not required as this driver only supports one UART. */\r
- ( void ) pxPort;\r
-\r
- /* Get the next character from the buffer. Return false if no characters\r
- are available, or arrive before xBlockTime expires. */\r
- if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
- {\r
- return pdTRUE;\r
- }\r
- else\r
- {\r
- return pdFALSE;\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )\r
-{\r
-portBASE_TYPE xReturn = pdTRUE;\r
-\r
- portENTER_CRITICAL();\r
- {\r
- /* If the UART FIFO is full we can block posting the new data on the\r
- Tx queue. */\r
- if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )\r
- {\r
- if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
- {\r
- xReturn = pdFAIL;\r
- }\r
- }\r
- /* Otherwise, if there is data already in the queue we should add the\r
- new data to the back of the queue to ensure the sequencing is \r
- maintained. */\r
- else if( uxQueueMessagesWaiting( xCharsForTx ) )\r
- {\r
- if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
- {\r
- xReturn = pdFAIL;\r
- } \r
- }\r
- /* If the UART FIFO is not full and there is no data already in the\r
- queue we can write directly to the FIFO without disrupting the \r
- sequence. */\r
- else\r
- {\r
- XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );\r
- }\r
- }\r
- portEXIT_CRITICAL();\r
-\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vSerialClose( xComPortHandle xPort )\r
-{\r
- /* Not supported as not required by the demo application. */\r
- ( void ) xPort;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vSerialISR( void *pvBaseAddress )\r
-{\r
-unsigned long ulISRStatus;\r
-portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
-char cChar;\r
-\r
- /* Determine the cause of the interrupt. */\r
- ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );\r
-\r
- if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )\r
- {\r
- /* A character is available - place it in the queue of received\r
- characters. This might wake a task that was blocked waiting for \r
- data. */\r
- cChar = ( char )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );\r
- xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );\r
- }\r
-\r
- if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )\r
- {\r
- /* There is space in the FIFO - if there are any characters queue for\r
- transmission they can be send to the UART now. This might unblock a\r
- task that was waiting for space to become available on the Tx queue. */\r
- if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
- {\r
- XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );\r
- }\r
- }\r
-\r
- /* If we woke any tasks we may require a context switch. */\r
- if( xHigherPriorityTaskWoken )\r
- {\r
- portYIELD_FROM_ISR();\r
- }\r
-}\r
+++ /dev/null
-\e\84æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Dn\b\dDvC\84æÄ®Òôtt¦Êè\84ÞÂäÈ@D°ÒØÒÜðD@D¬ÒäèÊð@h@\9a\98h`f@\8aìÂØêÂèÒÞÜ@ ØÂèÌÞäÚD@DbDv,\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D\82¤\86\90\92¨\8a\86¨ª¤\8aD@DìÒäèÊðhDv,\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D\88\8a¬\92\86\8a¾¦\92´\8aD@DðÆhìÌðbdDv%\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D \82\86\96\82\8e\8aD@DÌÌllpDv&\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D¦ \8a\8a\88\8e¤\82\88\8aD@DZb`Dv"\84æÄ®Òôtt\82ÈÈ äÞÆÊææÞä@DÚÒÆäÞÄØÂôÊDv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\84ª¦¾\8c¤\8a¢D@Db``\``````Dv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\82\86\90\8aD@D\9c\9e@\86\82\86\90\8aDvN\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\82\86\90\8a\98\92\9c\96@\86\9e\9a \9e\9c\8a\9c¨D@D\88\88¤¾¦\88¤\82\9a¾lh\9aðfdDv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\98\96¾\8c¤\8a¢D@Db``\``````DvJ\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\88\8a\84ª\8e¾\92\8cD@D\9eÜZ\86ÐÒà@\90®@\88ÊÄêÎ@\9aÞÈêØÊDv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\98\9a\84\84¤\82\9a@¦\92´\8aD@DljjflDv>\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D ¤\9e\86¾\8c¤\8a¢D@Db``\``````Dv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D¤¦¨¾ \9e\98\82¤\92¨²D@D`Dv2\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäèD@DÞàľêÂäèØÒèÊDv9\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\86¾\84\82ª\88¤\82¨\8aD@Drl``Dv7\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\86¾\88\82¨\82¾\84\92¨¦D@DpDv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\86¾\9e\88\88¾ \82¤\92¨²D@D`Dv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\86¾ª¦\8a¾ \82¤\92¨²D@D`Dv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D\92\9e¨² \8aD@D°\92\98¾ª\82¤¨¾¬bDv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@Dª¦\8a¾\92\9c¨\8a¤¤ª ¨D@D¨¤ª\8aDv-\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D\98\8a\88æ¾h\84ÒèD@DÞàľÎàÒÞDv;\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D\98\8a\88æ¾h\84ÒèD@D\92\9e¨² \8aD@D°\92\98¾\8e \92\9e¾¬bDv2\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D\98\8a\88æ¾ ÞæÒèÒÞÜæD@DÞàľÎàÒÞDv@\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D\98\8a\88æ¾ ÞæÒèÒÞÜæD@D\92\9e¨² \8aD@D°\92\98¾\8e \92\9e¾¬bDv0\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@DÞàľèÒÚÊä¾bD@DÞàľèÒÚÊäDv;\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@D\86¾\86\9eª\9c¨¾®\92\88¨\90D@DfdDv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@D\86¾\9e\9c\8a¾¨\92\9a\8a¤¾\9e\9c\98²D@DbDv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@Dª¦\8a¾\92\9c¨\8a¤¤ª ¨D@D¨¤ª\8aDv/\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\8e\8a\9c\8a¤\82¨\8a¾\9a\8a\9a¨\8a¦¨D@D\8c\82\98¦\8aDv1\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\8e\8a\9c\8a¤\82¨\8a¾ \8a¤\92 \90¨\8a¦¨D@D¨¤ª\8aDv#\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\88\92\9cD@D\9cÞÜÊDv$\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\88\9eª¨D@D\9cÞÜÊDvA\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\88\82¨\82¾\92\9c¦D@DÈØÚľÆÜèØäD@D¨Êæè\82àྠÊäÒàÐÊäÂØDvA\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\88\82¨\82¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àྠÊäÒàÐÊäÂØDvD\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾ ¤\9e\8e¤\82\9a¾\92\9c¦D@DÒØÚľÆÜèØäD@D¨Êæè\82àྠÊäÒàÐÊäÂØDvD\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾ ¤\9e\8e¤\82\9a¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àྠÊäÒàÐÊäÂØDvB\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\82\86\96¾\92\9c¦D@DÈØÚľÆÜèØäD@D¨Êæè\82àྠÊäÒàÐÊäÂØDvB\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\82\86\96¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àྠÊäÒàÐÊäÂØDv
\ No newline at end of file
+++ /dev/null
-#################################################################\r
-# Makefile generated by Xilinx Platform Studio \r
-# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp\r
-#################################################################\r
-\r
-# Name of the Microprocessor system\r
-# The hardware specification of the system is in file :\r
-# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mhs\r
-# The software specification of the system is in file :\r
-# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mss\r
-\r
-include system_incl.make\r
-\r
-\r
-#################################################################\r
-# EXTERNAL TARGETS\r
-#################################################################\r
-all:\r
- @echo "Makefile to build a Microprocessor system :"\r
- @echo "Run make with any of the following targets"\r
- @echo " "\r
- @echo " netlist : Generates the netlist for the given MHS "\r
- @echo " bits : Runs Implementation tools to generate the bitstream"\r
- @echo " exporttopn:Export to ProjNav"\r
- @echo " "\r
- @echo " libs : Configures the sw libraries for this system"\r
- @echo " program : Compiles the program sources for all the processor instances"\r
- @echo " "\r
- @echo " init_bram: Initializes bitstream with BRAM data"\r
- @echo " ace : Generate ace file from bitstream and elf"\r
- @echo " download : Downloads the bitstream onto the board"\r
- @echo " "\r
- @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"\r
- @echo " simmodel : Generates HDL simulation models for chosen simulation mode"\r
- @echo " behavioral_model:Generates behavioral HDL models with BRAM initialization"\r
- @echo " structural_model:Generates structural simulation HDL models with BRAM initialization"\r
- @echo " timing_model : Generates timing simulation HDL models with BRAM initialization"\r
- @echo " vp : Generates virtual platform model"\r
- @echo " "\r
- @echo " netlistclean: Deletes netlist"\r
- @echo " bitsclean: Deletes bit, ncd, bmm files"\r
- @echo " hwclean : Deletes implementation dir"\r
- @echo " libsclean: Deletes sw libraries"\r
- @echo " programclean: Deletes compiled ELF files"\r
- @echo " swclean : Deletes sw libraries and ELF files"\r
- @echo " simclean : Deletes simulation dir"\r
- @echo " vpclean : Deletes virtualplatform dir"\r
- @echo " clean : Deletes all generated files/directories"\r
- @echo " "\r
- @echo " make <target> : (Default)"\r
- @echo " Creates a Microprocessor system using default initializations"\r
- @echo " specified for each processor in MSS file"\r
-\r
-\r
-bits: $(SYSTEM_BIT)\r
-\r
-ace: $(SYSTEM_ACE)\r
-\r
-netlist: $(POSTSYN_NETLIST)\r
-\r
-libs: $(LIBRARIES)\r
-\r
-program: $(ALL_USER_ELF_FILES)\r
-\r
-download: $(DOWNLOAD_BIT) dummy\r
- @echo "*********************************************"\r
- @echo "Downloading Bitstream onto the target board"\r
- @echo "*********************************************"\r
- impact -batch etc/download.cmd\r
-\r
-init_bram: $(DOWNLOAD_BIT)\r
-\r
-sim: $(DEFAULT_SIM_SCRIPT)\r
- cd simulation/behavioral; \\r
- $(SIM_CMD) &\r
-\r
-simmodel: $(DEFAULT_SIM_SCRIPT)\r
-\r
-behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)\r
-\r
-structural_model: $(STRUCTURAL_SIM_SCRIPT)\r
-\r
-timing_model: $(TIMING_SIM_SCRIPT)\r
-\r
-vp: $(VPEXEC)\r
-\r
-clean: hwclean libsclean programclean simclean vpclean\r
- rm -f _impact.cmd\r
-\r
-hwclean: netlistclean bitsclean\r
- rm -rf implementation synthesis xst hdl\r
- rm -rf xst.srp $(SYSTEM).srp\r
-\r
-netlistclean:\r
- rm -f $(POSTSYN_NETLIST)\r
- rm -f $(BMM_FILE)\r
-\r
-bitsclean:\r
- rm -f $(SYSTEM_BIT)\r
- rm -f implementation/$(SYSTEM).ncd\r
- rm -f implementation/$(SYSTEM)_bd.bmm \r
-\r
-bitsclean:\r
-\r
-simclean: \r
- rm -rf simulation/behavioral\r
-\r
-swclean: libsclean programclean\r
- @echo ""\r
-\r
-libsclean: $(LIBSCLEAN_TARGETS)\r
-\r
-programclean: $(PROGRAMCLEAN_TARGETS)\r
-\r
-vpclean:\r
- rm -rf virtualplatform\r
-\r
-#################################################################\r
-# SOFTWARE PLATFORM FLOW\r
-#################################################################\r
-\r
-\r
-$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt\r
- @echo "*********************************************"\r
- @echo "Creating software libraries..."\r
- @echo "*********************************************"\r
- libgen $(LIBGEN_OPTIONS) $(MSSFILE)\r
-\r
-\r
-microblaze_0_libsclean:\r
- rm -rf microblaze_0/lib/\r
-\r
-$(MICROBLAZE_0_XMDSTUB): $(LIBRARIES)\r
-\r
-#################################################################\r
-# SOFTWARE APPLICATION RTOSDEMO\r
-#################################################################\r
-\r
-RTOSDemo_program: $(RTOSDEMO_OUTPUT) \r
-\r
-$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \\r
- $(LIBRARIES) __xps/rtosdemo_compiler.opt\r
- @mkdir -p $(RTOSDEMO_OUTPUT_DIR) \r
- $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \\r
- $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \\r
- -xl-mode-$(RTOSDEMO_MODE) \\r
- $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) \r
- $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) \r
-\r
-RTOSDemo_programclean:\r
- rm -f $(RTOSDEMO_OUTPUT) \r
-\r
-#################################################################\r
-# BOOTLOOP ELF FILES\r
-#################################################################\r
-\r
-\r
-\r
-$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP)\r
- @mkdir -p $(BOOTLOOP_DIR)\r
- cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP)\r
-\r
-#################################################################\r
-# HARDWARE IMPLEMENTATION FLOW\r
-#################################################################\r
-\r
-\r
-$(BMM_FILE) \\r
-$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \\r
- $(CORE_STATE_DEVELOPMENT_FILES)\r
- @echo "****************************************************"\r
- @echo "Creating system netlist for hardware specification.."\r
- @echo "****************************************************"\r
- platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE)\r
-\r
-$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)\r
- @echo "Running synthesis..."\r
- bash -c "cd synthesis; ./synthesis.sh; cd .."\r
-\r
-$(SYSTEM_BIT): $(BMM_FILE) $(POSTSYN_NETLIST) __xps/xpsxflow.opt \\r
- $(UCF_FILE) $(BITGEN_UT_FILE) $(FASTRUNTIME_OPT_FILE)\r
- @echo "Copying Xilinx Implementation tool scripts.."\r
- @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut\r
- @cp -f $(FASTRUNTIME_OPT_FILE) implementation/fast_runtime.opt\r
- @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf\r
- @echo "*********************************************"\r
- @echo "Running Xilinx Implementation tools.."\r
- @echo "*********************************************"\r
- xflow -wd implementation -p $(DEVICE) -implement fast_runtime.opt $(SYSTEM).ngc\r
- cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)\r
-\r
-exporttopn: \r
- @echo "You have chosen XPS for implementation tool flow."\r
- @echo "Please select ProjNav as your implementation flow in Project Options."\r
- @echo "In batch mode, use commad xset pnproj <isefile>."\r
-\r
-$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt\r
- @cp -f implementation/$(SYSTEM)_bd.bmm .\r
- @echo "*********************************************"\r
- @echo "Initializing BRAM contents of the bitstream"\r
- @echo "*********************************************"\r
- bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \\r
- -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)\r
- @rm -f $(SYSTEM)_bd.bmm\r
-\r
-$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) \r
- @echo "*********************************************"\r
- @echo "Creating system ace file"\r
- @echo "*********************************************"\r
- xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -ace $(SYSTEM_ACE)\r
-\r
-#################################################################\r
-# SIMULATION FLOW\r
-#################################################################\r
-\r
-\r
-################## BEHAVIORAL SIMULATION ##################\r
-\r
-$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \\r
- $(BRAMINIT_ELF_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating behavioral simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)\r
-\r
-################## STRUCTURAL SIMULATION ##################\r
-\r
-$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \\r
- $(BRAMINIT_ELF_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating structural simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)\r
-\r
-\r
-################## TIMING SIMULATION ##################\r
-\r
-$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \\r
- $(BRAMINIT_ELF_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating timing simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)\r
-\r
-#################################################################\r
-# VIRTUAL PLATFORM FLOW\r
-#################################################################\r
-\r
-\r
-$(VPEXEC): $(MHSFILE) __xps/vpgen.opt\r
- @echo "****************************************************"\r
- @echo "Creating virtual platform for hardware specification.."\r
- @echo "****************************************************"\r
- vpgen $(VPGEN_OPTIONS) $(MHSFILE)\r
-\r
-dummy:\r
- @echo ""\r
-\r
+++ /dev/null
-# ##############################################################################\r
-# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1\r
-# Sun Nov 13 16:46:19 2005\r
-# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1\r
-# Family: virtex4\r
-# Device: xc4vfx12\r
-# Package: ff668\r
-# Speed Grade: -10\r
-# Processor: Microblaze\r
-# System clock frequency: 100.000000 MHz\r
-# Debug interface: On-Chip HW Debug Module\r
-# On Chip Memory : 64 KB\r
-# ##############################################################################\r
-\r
-\r
- PARAMETER VERSION = 2.1.0\r
-\r
-\r
- PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT\r
- PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT\r
- PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3]\r
- PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = INOUT, VEC = [0:4]\r
- PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK\r
- PORT sys_rst_pin = sys_rst_s, DIR = INPUT\r
-\r
-\r
-BEGIN microblaze\r
- PARAMETER INSTANCE = microblaze_0\r
- PARAMETER HW_VER = 4.00.a\r
- PARAMETER C_DEBUG_ENABLED = 1\r
- PARAMETER C_NUMBER_OF_PC_BRK = 2\r
- PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1\r
- PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1\r
- BUS_INTERFACE DLMB = dlmb\r
- BUS_INTERFACE ILMB = ilmb\r
- BUS_INTERFACE DOPB = mb_opb\r
- BUS_INTERFACE IOPB = mb_opb\r
- PORT CLK = sys_clk_s\r
- PORT DBG_CAPTURE = DBG_CAPTURE_s\r
- PORT DBG_CLK = DBG_CLK_s\r
- PORT DBG_REG_EN = DBG_REG_EN_s\r
- PORT DBG_TDI = DBG_TDI_s\r
- PORT DBG_TDO = DBG_TDO_s\r
- PORT DBG_UPDATE = DBG_UPDATE_s\r
- PORT Interrupt = Interrupt\r
-END\r
-\r
-BEGIN opb_v20\r
- PARAMETER INSTANCE = mb_opb\r
- PARAMETER HW_VER = 1.10.c\r
- PARAMETER C_EXT_RESET_HIGH = 0\r
- PORT SYS_Rst = sys_rst_s\r
- PORT OPB_Clk = sys_clk_s\r
-END\r
-\r
-BEGIN opb_mdm\r
- PARAMETER INSTANCE = debug_module\r
- PARAMETER HW_VER = 2.00.a\r
- PARAMETER C_MB_DBG_PORTS = 1\r
- PARAMETER C_USE_UART = 1\r
- PARAMETER C_UART_WIDTH = 8\r
- PARAMETER C_BASEADDR = 0x41400000\r
- PARAMETER C_HIGHADDR = 0x4140ffff\r
- BUS_INTERFACE SOPB = mb_opb\r
- PORT OPB_Clk = sys_clk_s\r
- PORT DBG_CAPTURE_0 = DBG_CAPTURE_s\r
- PORT DBG_CLK_0 = DBG_CLK_s\r
- PORT DBG_REG_EN_0 = DBG_REG_EN_s\r
- PORT DBG_TDI_0 = DBG_TDI_s\r
- PORT DBG_TDO_0 = DBG_TDO_s\r
- PORT DBG_UPDATE_0 = DBG_UPDATE_s\r
-END\r
-\r
-BEGIN lmb_v10\r
- PARAMETER INSTANCE = ilmb\r
- PARAMETER HW_VER = 1.00.a\r
- PARAMETER C_EXT_RESET_HIGH = 0\r
- PORT SYS_Rst = sys_rst_s\r
- PORT LMB_Clk = sys_clk_s\r
-END\r
-\r
-BEGIN lmb_v10\r
- PARAMETER INSTANCE = dlmb\r
- PARAMETER HW_VER = 1.00.a\r
- PARAMETER C_EXT_RESET_HIGH = 0\r
- PORT SYS_Rst = sys_rst_s\r
- PORT LMB_Clk = sys_clk_s\r
-END\r
-\r
-BEGIN lmb_bram_if_cntlr\r
- PARAMETER INSTANCE = dlmb_cntlr\r
- PARAMETER HW_VER = 1.00.b\r
- PARAMETER C_BASEADDR = 0x00000000\r
- PARAMETER C_HIGHADDR = 0x0000ffff\r
- BUS_INTERFACE SLMB = dlmb\r
- BUS_INTERFACE BRAM_PORT = dlmb_port\r
-END\r
-\r
-BEGIN lmb_bram_if_cntlr\r
- PARAMETER INSTANCE = ilmb_cntlr\r
- PARAMETER HW_VER = 1.00.b\r
- PARAMETER C_BASEADDR = 0x00000000\r
- PARAMETER C_HIGHADDR = 0x0000ffff\r
- BUS_INTERFACE SLMB = ilmb\r
- BUS_INTERFACE BRAM_PORT = ilmb_port\r
-END\r
-\r
-BEGIN bram_block\r
- PARAMETER INSTANCE = lmb_bram\r
- PARAMETER HW_VER = 1.00.a\r
- BUS_INTERFACE PORTA = ilmb_port\r
- BUS_INTERFACE PORTB = dlmb_port\r
-END\r
-\r
-BEGIN opb_uartlite\r
- PARAMETER INSTANCE = RS232_Uart\r
- PARAMETER HW_VER = 1.00.b\r
- PARAMETER C_BAUDRATE = 9600\r
- PARAMETER C_DATA_BITS = 8\r
- PARAMETER C_ODD_PARITY = 0\r
- PARAMETER C_USE_PARITY = 0\r
- PARAMETER C_CLK_FREQ = 100000000\r
- PARAMETER C_BASEADDR = 0x40600000\r
- PARAMETER C_HIGHADDR = 0x4060ffff\r
- BUS_INTERFACE SOPB = mb_opb\r
- PORT OPB_Clk = sys_clk_s\r
- PORT Interrupt = RS232_Uart_Interrupt\r
- PORT RX = fpga_0_RS232_Uart_RX\r
- PORT TX = fpga_0_RS232_Uart_TX\r
-END\r
-\r
-BEGIN opb_gpio\r
- PARAMETER INSTANCE = LEDs_4Bit\r
- PARAMETER HW_VER = 3.01.b\r
- PARAMETER C_GPIO_WIDTH = 4\r
- PARAMETER C_IS_DUAL = 0\r
- PARAMETER C_IS_BIDIR = 1\r
- PARAMETER C_ALL_INPUTS = 0\r
- PARAMETER C_BASEADDR = 0x40020000\r
- PARAMETER C_HIGHADDR = 0x4002ffff\r
- BUS_INTERFACE SOPB = mb_opb\r
- PORT OPB_Clk = sys_clk_s\r
- PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO\r
-END\r
-\r
-BEGIN opb_gpio\r
- PARAMETER INSTANCE = LEDs_Positions\r
- PARAMETER HW_VER = 3.01.b\r
- PARAMETER C_GPIO_WIDTH = 5\r
- PARAMETER C_IS_DUAL = 0\r
- PARAMETER C_IS_BIDIR = 1\r
- PARAMETER C_ALL_INPUTS = 0\r
- PARAMETER C_BASEADDR = 0x40000000\r
- PARAMETER C_HIGHADDR = 0x4000ffff\r
- BUS_INTERFACE SOPB = mb_opb\r
- PORT OPB_Clk = sys_clk_s\r
- PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO\r
-END\r
-\r
-BEGIN opb_timer\r
- PARAMETER INSTANCE = opb_timer_1\r
- PARAMETER HW_VER = 1.00.b\r
- PARAMETER C_COUNT_WIDTH = 32\r
- PARAMETER C_ONE_TIMER_ONLY = 1\r
- PARAMETER C_BASEADDR = 0x41c00000\r
- PARAMETER C_HIGHADDR = 0x41c0ffff\r
- BUS_INTERFACE SOPB = mb_opb\r
- PORT OPB_Clk = sys_clk_s\r
- PORT Interrupt = opb_timer_1_Interrupt\r
-END\r
-\r
-BEGIN opb_intc\r
- PARAMETER INSTANCE = opb_intc_0\r
- PARAMETER HW_VER = 1.00.c\r
- PARAMETER C_BASEADDR = 0x41200000\r
- PARAMETER C_HIGHADDR = 0x4120ffff\r
- PARAMETER C_HAS_IPR = 0\r
- BUS_INTERFACE SOPB = mb_opb\r
- PORT Irq = Interrupt\r
- PORT Intr = RS232_Uart_Interrupt & opb_timer_1_Interrupt\r
-END\r
-\r
-BEGIN dcm_module\r
- PARAMETER INSTANCE = dcm_0\r
- PARAMETER HW_VER = 1.00.a\r
- PARAMETER C_CLK0_BUF = TRUE\r
- PARAMETER C_CLKIN_PERIOD = 10.000000\r
- PARAMETER C_CLK_FEEDBACK = 1X\r
- PARAMETER C_EXT_RESET_HIGH = 1\r
- PORT CLKIN = dcm_clk_s\r
- PORT CLK0 = sys_clk_s\r
- PORT CLKFB = sys_clk_s\r
- PORT RST = net_gnd\r
- PORT LOCKED = dcm_0_lock\r
-END\r
-\r
+++ /dev/null
-\r
- PARAMETER VERSION = 2.2.0\r
-\r
-\r
-BEGIN OS\r
- PARAMETER OS_NAME = standalone\r
- PARAMETER OS_VER = 1.00.a\r
- PARAMETER PROC_INSTANCE = microblaze_0\r
-END\r
-\r
-\r
-BEGIN PROCESSOR\r
- PARAMETER DRIVER_NAME = cpu\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = microblaze_0\r
- PARAMETER COMPILER = mb-gcc\r
- PARAMETER ARCHIVER = mb-ar\r
- PARAMETER XMDSTUB_PERIPHERAL = debug_module\r
-END\r
-\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = opbarb\r
- PARAMETER DRIVER_VER = 1.02.a\r
- PARAMETER HW_INSTANCE = mb_opb\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = uartlite\r
- PARAMETER DRIVER_VER = 1.00.b\r
- PARAMETER HW_INSTANCE = debug_module\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = bram\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = dlmb_cntlr\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = bram\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = ilmb_cntlr\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = uartlite\r
- PARAMETER DRIVER_VER = 1.00.b\r
- PARAMETER HW_INSTANCE = RS232_Uart\r
- PARAMETER int_handler = vSerialISR, int_port = Interrupt\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = gpio\r
- PARAMETER DRIVER_VER = 2.00.a\r
- PARAMETER HW_INSTANCE = LEDs_4Bit\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = gpio\r
- PARAMETER DRIVER_VER = 2.00.a\r
- PARAMETER HW_INSTANCE = LEDs_Positions\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = tmrctr\r
- PARAMETER DRIVER_VER = 1.00.b\r
- PARAMETER HW_INSTANCE = opb_timer_1\r
- PARAMETER int_handler = vTickISR, int_port = Interrupt\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = intc\r
- PARAMETER DRIVER_VER = 1.00.c\r
- PARAMETER HW_INSTANCE = opb_intc_0\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = generic\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = dcm_0\r
-END\r
-\r
-\r
+++ /dev/null
-#Please do not modify this file by hand\r
-XmpVersion: 7.1\r
-IntStyle: default\r
-MHS File: system.mhs\r
-MSS File: system.mss\r
-NPL File: projnav/system.ise\r
-Architecture: virtex4\r
-Device: xc4vfx12\r
-Package: ff668\r
-SpeedGrade: -10\r
-UseProjNav: 0\r
-AddToNPL: 0\r
-PNImportBitFile: \r
-PNImportBmmFile: \r
-UserCmd1: \r
-UserCmd1Type: 0\r
-UserCmd2: \r
-UserCmd2Type: 0\r
-SynProj: xst\r
-ReloadPbde: 0\r
-MainMhsEditor: 0\r
-InsertNoPads: 0\r
-HdlLang: VHDL\r
-Simulator: mti\r
-SimModel: BEHAVIORAL\r
-SimXLib: \r
-SimEdkLib: \r
-MixLangSim: 1\r
-UcfFile: data/system.ucf\r
-Processor: microblaze_0\r
-BootLoop: 0\r
-XmdStub: 0\r
-SwProj: RTOSDemo\r
-Processor: microblaze_0\r
-Executable: RTOSDemo/executable.elf\r
-Source: main.c\r
-Source: ParTest/ParTest.c\r
-Source: ../../Source/tasks.c\r
-Source: ../../Source/queue.c\r
-Source: ../../Source/list.c\r
-Source: ../../Source/portable/MemMang/heap_1.c\r
-Source: ../../Source/portable/GCC/MicroBlaze/port.c\r
-Source: ../../Source/portable/GCC/MicroBlaze/portasm.s\r
-Source: ../Common/Minimal/flash.c\r
-Source: serial/serial.c\r
-Source: ../Common/Minimal/comtest.c\r
-Source: ../Common/Minimal/integer.c\r
-Source: ../Common/Minimal/semtest.c\r
-Source: ../Common/Minimal/dynamic.c\r
-Source: ../Common/Minimal/PollQ.c\r
-Source: ../Common/Minimal/BlockQ.c\r
-Header: FreeRTOSConfig.h\r
-DefaultInit: EXECUTABLE\r
-InitBram: 1\r
-Active: 1\r
-CompilerOptLevel: 4\r
-GlobPtrOpt: 0\r
-DebugSym: 1\r
-SearchIncl: . ../Common/include ../../Source/include ../../Source/portable/GCC/MicroBlaze\r
-AsmOpt: \r
-LinkOpt: -Map=rtosdemo.map\r
-ProgStart: \r
-StackSize: \r
-HeapSize: \r
-LinkerScript: \r
-ProgCCFlags: -D MICROBLAZE_GCC -Wall\r
+++ /dev/null
-#################################################################\r
-# Makefile generated by Xilinx Platform Studio \r
-# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp\r
-#################################################################\r
-\r
-XILINX_EDK_DIR = C:/devtools/xilinx/EDK\r
-\r
-SYSTEM = system\r
-\r
-MHSFILE = system.mhs\r
-\r
-MSSFILE = system.mss\r
-\r
-FPGA_ARCH = virtex4\r
-\r
-DEVICE = xc4vfx12ff668-10\r
-\r
-LANGUAGE = vhdl\r
-\r
-SEARCHPATHOPT = \r
-\r
-SUBMODULE_OPT = \r
-\r
-PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT)\r
-\r
-LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) \\r
- $(MICROBLAZE_0_LIBG_OPT)\r
-\r
-VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT)\r
-\r
-RTOSDEMO_OUTPUT_DIR = RTOSDemo\r
-RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf\r
-\r
-MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf\r
-PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf\r
-BOOTLOOP_DIR = bootloops\r
-\r
-MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf\r
-MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf\r
-\r
-BRAMINIT_ELF_FILES = $(RTOSDEMO_OUTPUT) \r
-BRAMINIT_ELF_FILE_ARGS = -pe microblaze_0 $(RTOSDEMO_OUTPUT) \r
-\r
-ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) \r
-\r
-SIM_CMD = vsim\r
-\r
-BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do\r
-\r
-STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do\r
-\r
-TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do\r
-\r
-DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)\r
-\r
-MIX_LANG_SIM_OPT = -mixed yes\r
-\r
-SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti\r
-\r
-MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf\r
-\r
-LIBRARIES = \\r
- microblaze_0/lib/libxil.a \r
-VPEXEC = virtualplatform/vpexec.exe\r
-\r
-LIBSCLEAN_TARGETS = microblaze_0_libsclean \r
-\r
-PROGRAMCLEAN_TARGETS = RTOSDemo_programclean \r
-\r
-CORE_STATE_DEVELOPMENT_FILES = \r
-\r
-WRAPPER_NGC_FILES = implementation/microblaze_0_wrapper.ngc \
-implementation/mb_opb_wrapper.ngc \
-implementation/debug_module_wrapper.ngc \
-implementation/ilmb_wrapper.ngc \
-implementation/dlmb_wrapper.ngc \
-implementation/dlmb_cntlr_wrapper.ngc \
-implementation/ilmb_cntlr_wrapper.ngc \
-implementation/lmb_bram_wrapper.ngc \
-implementation/rs232_uart_wrapper.ngc \
-implementation/leds_4bit_wrapper.ngc \
-implementation/leds_positions_wrapper.ngc \
-implementation/opb_timer_1_wrapper.ngc \
-implementation/opb_intc_0_wrapper.ngc \
-implementation/dcm_0_wrapper.ngc\r
-\r
-POSTSYN_NETLIST = implementation/$(SYSTEM).ngc\r
-\r
-SYSTEM_BIT = implementation/$(SYSTEM).bit\r
-\r
-DOWNLOAD_BIT = implementation/download.bit\r
-\r
-SYSTEM_ACE = implementation/$(SYSTEM).ace\r
-\r
-UCF_FILE = data/system.ucf\r
-\r
-BMM_FILE = implementation/$(SYSTEM).bmm\r
-\r
-FASTRUNTIME_OPT_FILE = etc/fast_runtime.opt\r
-BITGEN_UT_FILE = etc/bitgen.ut\r
-\r
-#################################################################\r
-# SOFTWARE APPLICATION RTOSDEMO\r
-#################################################################\r
-\r
-RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c \r
-\r
-RTOSDEMO_HEADERS = FreeRTOSConfig.h \r
-\r
-RTOSDEMO_CC = mb-gcc\r
-RTOSDEMO_CC_SIZE = mb-size\r
-RTOSDEMO_CC_OPT = -Os\r
-RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall\r
-RTOSDEMO_CC_SEARCH = # -B\r
-RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L\r
-RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze \r
-RTOSDEMO_LFLAGS = # -l\r
-RTOSDEMO_CC_PREPROC_FLAG = # -Wp,\r
-RTOSDEMO_CC_ASM_FLAG = # -Wa,\r
-RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map \r
-RTOSDEMO_LINKER_SCRIPT = \r
-RTOSDEMO_LINKER_SCRIPT_FLAG = #-Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) \r
-RTOSDEMO_CC_DEBUG_FLAG = -g \r
-RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt\r
-RTOSDEMO_MODE = executable\r
-RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0\r
-RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul \r
-RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=\r
-RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=\r
-RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \\r
- $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) \\r
- $(RTOSDEMO_CC_SOFTMUL_FLAG) \\r
- $(RTOSDEMO_CC_PREPROC_FLAG) $(RTOSDEMO_CC_ASM_FLAG) $(RTOSDEMO_CC_LINKER_FLAG) \\r
- $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) \r
+++ /dev/null
-
-PARAMETER VERSION = 2.2.0
-
-BEGIN OS
- PARAMETER OS_NAME = freertos
- PARAMETER STDIN = *
- PARAMETER STDOUT = *
- PARAMETER SYSTMR_SPEC = true
- PARAMETER SYSTMR_DEV = *
- PARAMETER SYSINTC_SPEC = *
-END
-
+++ /dev/null
-##############################################################################
-#
-# (c) Copyright 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information of Xilinx, Inc.
-# and is protected under U.S. and international copyright and other
-# intellectual property laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any rights to the
-# materials distributed herewith. Except as otherwise provided in a valid
-# license issued to you by Xilinx, and to the maximum extent permitted by
-# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-# and (2) Xilinx shall not be liable (whether in contract or tort, including
-# negligence, or under any other theory of liability) for any loss or damage
-# of any kind or nature related to, arising under or in connection with these
-# materials, including for any direct, or any indirect, special, incidental,
-# or consequential loss or damage (including loss of data, profits, goodwill,
-# or any type of loss or damage suffered as a result of any action brought by
-# a third party) even if such damage or loss was reasonably foreseeable or
-# Xilinx had been advised of the possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-safe, or for use in
-# any application requiring fail-safe performance, such as life-support or
-# safety devices or systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any other applications
-# that could lead to death, personal injury, or severe property or
-# environmental damage (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and liability of any use of
-# Xilinx products in Critical Applications, subject only to applicable laws
-# and regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-# AT ALL TIMES.
-#
-# This file is part of Xilkernel.
-#
-# $Id: xilkernel_v2_1_0.mld,v 1.1.2.4 2010/12/10 07:27:08 svemula Exp $
-###############################################################################
-
-OPTION psf_version = 2.1.0 ;
-BEGIN OS freertos
-
- OPTION DRC = kernel_drc ;
- OPTION SUPPORTED_PERIPHERALS = (microblaze);
- OPTION COPYFILES = all;
- OPTION DEPENDS = (standalone_v3_01_a);
- OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lxil,-lfreertos,-lgcc,-lc,--end-group";
-
- OPTION DESC = "FreeRTOS is a popular lightweight kernel."
-
- # STDIN/STDOUT
- PARAM name = stdin, type = peripheral_instance, requires_interface = stdin, default=none, desc = "Specify the instance name of the standard input peripheral";
- PARAM name = stdout, type = peripheral_instance, requires_interface = stdout, default=none, desc = "Specify the instance name of the standard output peripheral";
-
- # System timer specification
- PARAM name = systmr_interval, type = int, default = 10, desc = "Specify the frequency of the kernel tick (in Hz).";
-
- # System interrupt controller specification
- # PARAM name = sysintc_spec, type = peripheral_instance, range = (opb_intc, xps_intc, dcr_intc, axi_intc), default = none, desc = "Specify the instance name of the interrupt controller device driving system interrupts";
-
- BEGIN CATEGORY kernel_behavior
- PARAM name = kernel_behavior, type = bool, default = true, desc = "Parameters relating to the kernel behavior", permit = user;
- PARAM name = use_preemption, type = bool, default = true, desc = "Set to true to use the preemptive scheduler, or false to use the cooperative scheduler.";
- PARAM name = idle_yield, type = bool, default = true, desc = "Set to true if the Idle task should yield if another idle priority task is able to run, or false if the idle task should always use its entire time slice unless it is preempted.";
- PARAM name = max_priorities, type = int, default = 4, desc = "The number of task priorities that will be available. Priorities can be assigned from zero to (max_priorities - 1)";
- PARAM name = minimal_stack_size, type = int, default = 120, desc = "The size of the stack allocated to the Idle task. Also used by standard demo and test tasks found in the main FreeRTOS download.";
- PARAM name = total_heap_size, type = int, default = 65536, desc = "Only used if heap_1.c or heap_2.c is included in the project. Sets the amount of RAM reserved for use by the kernel - used when tasks, queues and semaphores are created.";
- PARAM name = max_task_name_len, type = int, default = 8, desc = "The maximum number of characters that can be in the name of a task.";
- END CATEGORY
-
- BEGIN CATEGORY kernel_features
- PARAM name = kernel_features, type = bool, default = true, desc = "Include or exclude kernel features", permit = user;
- PARAM name = use_mutexes, type = bool, default = true, desc = "Set to true to include mutex functionality, or false to exclude mutex functionality.";
- PARAM name = use_recursive_mutexes, type = bool, default = true, desc = "Set to true to include recursive mutex functionality, or false to exclude recursive mutex functionality.";
- PARAM name = use_counting_semaphores, type = bool, default = true, desc = "Set to true to include counting semaphore functionality, or false to exclude recursive mutex functionality.";
- PARAM name = queue_registry_size, type = int, default = 10, desc = "The maximum number of queues that can be registered at any one time. Registered queues can be viewed in the kernel aware debugger plug-in.";
- PARAM name = use_trace_facility, type = bool, default = true, desc = "Set to true to include the legacy trace functionality, and a few other features. traceMACROS are the preferred method of tracing now.";
- END CATEGORY
-
- BEGIN CATEGORY hook_functions
- PARAM name = hook_functions, type = bool, default = true, desc = "Include or exclude application defined hook (callback) functions. Callback functions must be defined by the application that is using FreeRTOS", permit = user;
- PARAM name = use_idle_hook, type = bool, default = false, desc = "Set to true for the kernel to call vApplicationIdleHook() on each iteration of the idle task. The application must provide an implementation of vApplicationIdleHook().";
- PARAM name = use_tick_hook, type = bool, default = false, desc = "Set to true for the kernel to call vApplicationTickHook() during each tick interrupt. The application must provide an implementation of vApplicationTickHook().";
- PARAM name = use_malloc_failed_hook, type = bool, default = true, desc = "Only used if heap_1.c, heap_2.c or heap_3.c is included in the project. Set to true for the kernel to call vApplicationMallocFailedHookHook() if there is insufficient FreeRTOS heap available for a task, queue or semaphore to be created. The application must provide an implementation of vApplicationMallocFailedHook().";
- PARAM name = check_for_stack_overflow, type = int, default = 2, desc = "Set to 1 to include basic run time task stack checking. Set to 2 to include more comprehensive run time task stack checking.";
- END CATEGORY
-
- BEGIN CATEGORY software_timers
- PARAM name = software_timers, type = bool, default = true, desc = "Options relating to the software timers functionality", permit = user;
- PARAM name = use_timers, type = bool, default = true, desc = "Set to true to include software timer functionality, or false to exclude software timer functionality";
- PARAM name = timer_task_priority, type = string, default = "(configMAX_PRIORITIES - 1)", desc = "The priority at which the software timer service/daemon task will execute.";
- PARAM name = timer_command_queue_length, type = int, default = 10, desc = "The number of commands the timer command queue can hold at any one time.";
- PARAM name = timer_task_stack_depth, type = string, default = "(configMINIMAL_STACK_SIZE), desc = "The size of the stack allocated to the timer service/daemon task.";
- END CATEGORY
-
-END OS
+++ /dev/null
-##############################################################################\r
-#\r
-# (c) Copyright 2011 Xilinx, Inc. All rights reserved.\r
-#\r
-# This file contains confidential and proprietary information of Xilinx, Inc.\r
-# and is protected under U.S. and international copyright and other\r
-# intellectual property laws.\r
-#\r
-# DISCLAIMER\r
-# This disclaimer is not a license and does not grant any rights to the\r
-# materials distributed herewith. Except as otherwise provided in a valid\r
-# license issued to you by Xilinx, and to the maximum extent permitted by\r
-# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
-# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
-# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
-# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
-# and (2) Xilinx shall not be liable (whether in contract or tort, including\r
-# negligence, or under any other theory of liability) for any loss or damage\r
-# of any kind or nature related to, arising under or in connection with these\r
-# materials, including for any direct, or any indirect, special, incidental,\r
-# or consequential loss or damage (including loss of data, profits, goodwill,\r
-# or any type of loss or damage suffered as a result of any action brought by\r
-# a third party) even if such damage or loss was reasonably foreseeable or\r
-# Xilinx had been advised of the possibility of the same.\r
-#\r
-# CRITICAL APPLICATIONS\r
-# Xilinx products are not designed or intended to be fail-safe, or for use in\r
-# any application requiring fail-safe performance, such as life-support or\r
-# safety devices or systems, Class III medical devices, nuclear facilities,\r
-# applications related to the deployment of airbags, or any other applications\r
-# that could lead to death, personal injury, or severe property or\r
-# environmental damage (individually and collectively, "Critical\r
-# Applications"). Customer assumes the sole risk and liability of any use of\r
-# Xilinx products in Critical Applications, subject only to applicable laws\r
-# and regulations governing limitations on product liability.\r
-#\r
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
-# AT ALL TIMES.\r
-#\r
-# This file is part of FreeRTOS.\r
-#\r
-# $Id: freertos_v2_1_0.tcl,v 1.1.2.8 2010/12/10 07:27:08 svemula Exp $\r
-###############################################################################\r
-\r
-# standalone bsp version. set this to the latest "ACTIVE" version.\r
-set standalone_version standalone_v3_01_a\r
-\r
-proc kernel_drc {os_handle} {\r
- set sw_proc_handle [xget_libgen_proc_handle]\r
- set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]\r
- set proctype [xget_value $hw_proc_handle "OPTION" "IPNAME"]\r
- set compiler [xget_value $sw_proc_handle "PARAMETER" "COMPILER"]\r
-\r
- # check for valid compiler\r
- if { [string first "mb-gcc" $compiler] == 0 && [string first "mb-g++" $compiler] == 0} {\r
- error "Wrong compiler requested. FreeRTOS can be compiled only with the GNU compiler for MicroBlaze." "" "mdt_error"\r
- }\r
-\r
- # check for valid stdio parameters\r
- set stdin [xget_value $os_handle "PARAMETER" "STDIN"]\r
- set stdout [xget_value $os_handle "PARAMETER" "STDOUT"]\r
- if { $stdin == "none" || $stdout == "none" } {\r
- error "The STDIN/STDOUT parameters are not set. FreeRTOS requires stdin/stdout to be set." "" "mdt_error"\r
- }\r
-\r
- # check if the design has a intc\r
- set intr_port [xget_value $hw_proc_handle "PORT" "Interrupt"]\r
- if { [llength $intr_port] == 0 } {\r
- error "CPU has no connection to Interrupt controller." "" "mdt_error"\r
- }\r
-\r
- # support only AXI/PLB\r
- set interconnect [xget_value $hw_proc_handle "PARAMETER" "C_INTERCONNECT"]\r
- if { $interconnect == 1 } {\r
- set bus_name [xget_hw_busif_value $hw_proc_handle "DPLB"]\r
- } elseif { $interconnect == 2 } {\r
- set bus_name [xget_hw_busif_value $hw_proc_handle "M_AXI_DP"]\r
- } else {\r
- error "FreeRTOS supports Microblaze with only a AXI or PLB interconnect" "" "mdt_error"\r
- }\r
-\r
- # obtain handles to all the peripherals in the design\r
- set mhs_handle [xget_hw_parent_handle $hw_proc_handle]\r
- set slave_ifs [xget_hw_connected_busifs_handle $mhs_handle $bus_name "slave"]\r
- set timer_count 0\r
- set timer_has_intr 0\r
-\r
- # check for a valid timer\r
- foreach if $slave_ifs {\r
- set ip_handle [xget_hw_parent_handle $if]\r
-\r
- if {$ip_handle != $hw_proc_handle} {\r
- set type [xget_hw_value $ip_handle]\r
- if { $type == "xps_timer" || $type == "axi_timer" } {\r
- incr timer_count\r
- \r
- # check if the timer interrupts are enabled\r
- set intr_port [xget_value $ip_handle "PORT" "Interrupt"]\r
- if { [llength $intr_port] != 0 } {\r
- set timer_has_intr 1\r
- }\r
- }\r
- }\r
- }\r
-\r
- if { $timer_count == 0 } {\r
- error "FreeRTOS for Microblaze requires an axi_timer or xps_timer. The HW platform doesn't have a valid timer." "" "mdt_error"\r
- }\r
-\r
- if { $timer_has_intr == 0 } {\r
- error "FreeRTOS for Microblaze requires interrupts enabled for a timer." "" "mdt_error"\r
- }\r
-\r
- set systmr_interval_ms [xget_value $os_handle "PARAMETER" "systmr_interval"]\r
- if { $systmr_interval_ms <= 0 } {\r
- error "Invalid value for parameter systmr_interval specified. Please specify a positive value." "" "mdt_error"\r
- }\r
-\r
- ### ToDo: Add DRC specific to FreeRTOS\r
-}\r
-\r
-proc generate {os_handle} {\r
-\r
- variable standalone_version\r
-\r
- set sw_proc_handle [xget_libgen_proc_handle]\r
- set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]\r
- set proctype [xget_value $hw_proc_handle "OPTION" "IPNAME"]\r
- set procver [xget_value $hw_proc_handle "PARAMETER" "HW_VER"]\r
- \r
- set need_config_file "false"\r
-\r
- # proctype should be "microblaze"\r
- set mbsrcdir "../${standalone_version}/src/microblaze"\r
- set commondir "../${standalone_version}/src/common"\r
- set datadir "../${standalone_version}/data"\r
-\r
- foreach entry [glob -nocomplain [file join $commondir *]] {\r
- file copy -force $entry [file join ".." "${standalone_version}" "src"]\r
- }\r
- \r
- # proctype should be "microblaze"\r
- switch -regexp $proctype {\r
- "microblaze" { \r
-\r
- foreach entry [glob -nocomplain [file join $mbsrcdir *]] {\r
- if { [string first "microblaze_interrupt_handler" $entry] == -1 } { ;# Do not copy over the Standalone BSP exception handler\r
- file copy -force $entry [file join ".." "${standalone_version}" "src"]\r
- }\r
- }\r
- set need_config_file "true"\r
- }\r
- "default" {puts "unknown processor type $proctype\n"}\r
- }\r
-\r
- # Write the config.make file\r
- set makeconfig [open "../standalone_v3_01_a/src/config.make" w] \r
- xprint_generated_header_tcl $makeconfig "Configuration parameters for Standalone Makefile"\r
-\r
- if { $proctype == "microblaze" } {\r
- if { [mb_has_exceptions $hw_proc_handle] } {\r
- puts $makeconfig "LIBSOURCES = *.s *.c *.S"\r
- } else {\r
- puts $makeconfig "LIBSOURCES = *.s *.c"\r
- }\r
- }\r
-\r
- puts $makeconfig "LIBS = standalone_libs"\r
- close $makeconfig\r
-\r
- # Remove microblaze directories...\r
- file delete -force $mbsrcdir\r
-\r
- # copy required files to the main src directory\r
- file copy -force [file join src Source tasks.c] src\r
- file copy -force [file join src Source queue.c] src\r
- file copy -force [file join src Source list.c] src\r
- file copy -force [file join src Source timers.c] src\r
- file copy -force [file join src Source portable MemMang heap_3.c] src\r
- file copy -force [file join src Source portable GCC MicroBlazeV8 port.c] src\r
- file copy -force [file join src Source portable GCC MicroBlazeV8 port_exceptions.c] src\r
- file copy -force [file join src Source portable GCC MicroBlazeV8 portasm.S] src\r
- file copy -force [file join src Source portable GCC MicroBlazeV8 portmacro.h] src\r
- set headers [glob -join ./src/Source/include *.\[h\]]\r
- foreach header $headers {\r
- file copy -force $header src\r
- }\r
-\r
- file delete -force [file join src Source]\r
- file delete -force [file join src Source]\r
-\r
- # Handle stdin and stdout\r
- xhandle_stdin $os_handle\r
- xhandle_stdout $os_handle\r
-\r
- # Create config file for microblaze interrupt handling\r
- if {[string compare -nocase $need_config_file "true"] == 0} {\r
- xhandle_mb_interrupts\r
- }\r
-\r
- # Create config files for Microblaze exception handling\r
- if { $proctype == "microblaze" && [mb_has_exceptions $hw_proc_handle] } {\r
- xcreate_mb_exc_config_file \r
- }\r
-\r
- # Create bspconfig file\r
- set bspcfg_fn [file join ".." "${standalone_version}" "src" "bspconfig.h"] \r
- file delete $bspcfg_fn\r
- set bspcfg_fh [open $bspcfg_fn w]\r
- xprint_generated_header $bspcfg_fh "Configurations for Standalone BSP"\r
-\r
- if { $proctype == "microblaze" && [mb_has_pvr $hw_proc_handle] } {\r
- \r
- set pvr [xget_value $hw_proc_handle "PARAMETER" "C_PVR"]\r
- \r
- switch $pvr {\r
- "0" {\r
- puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE"\r
- }\r
- "1" {\r
- puts $bspcfg_fh "#define MICROBLAZE_PVR_BASIC"\r
- }\r
- "2" {\r
- puts $bspcfg_fh "#define MICROBLAZE_PVR_FULL"\r
- }\r
- "default" {\r
- puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE"\r
- }\r
- } \r
- }\r
-\r
- close $bspcfg_fh\r
-\r
-# ToDO: FreeRTOS does not handle the following, refer xilkernel TCL script\r
-# - MPU settings\r
-\r
- set config_file [xopen_new_include_file "./src/FreeRTOSConfig.h" "FreeRTOS Configuration parameters"]\r
- puts $config_file "\#include \"xparameters.h\" \n"\r
-\r
- set val [xget_value $os_handle "PARAMETER" "use_preemption"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_PREEMPTION" "0"\r
- } else {\r
- xput_define $config_file "configUSE_PREEMPTION" "1"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "use_mutexes"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_MUTEXES" "0"\r
- } else {\r
- xput_define $config_file "configUSE_MUTEXES" "1"\r
- }\r
- \r
- set val [xget_value $os_handle "PARAMETER" "use_recursive_mutexes"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_RECURSIVE_MUTEXES" "0"\r
- } else {\r
- xput_define $config_file "configUSE_RECURSIVE_MUTEXES" "1"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "use_counting_semaphores"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_COUNTING_SEMAPHORES" "0"\r
- } else {\r
- xput_define $config_file "configUSE_COUNTING_SEMAPHORES" "1"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "use_timers"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_TIMERS" "0"\r
- } else {\r
- xput_define $config_file "configUSE_TIMERS" "1"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "use_idle_hook"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_IDLE_HOOK" "0"\r
- } else {\r
- xput_define $config_file "configUSE_IDLE_HOOK" "1"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "use_tick_hook"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_TICK_HOOK" "0"\r
- } else {\r
- xput_define $config_file "configUSE_TICK_HOOK" "1"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "use_malloc_failed_hook"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_MALLOC_FAILED_HOOK" "0"\r
- } else {\r
- xput_define $config_file "configUSE_MALLOC_FAILED_HOOK" "1"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "use_trace_facility"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configUSE_TRACE_FACILITY" "0"\r
- } else {\r
- xput_define $config_file "configUSE_TRACE_FACILITY" "1"\r
- }\r
-\r
- xput_define $config_file "configUSE_16_BIT_TICKS" "0"\r
- xput_define $config_file "configUSE_APPLICATION_TASK_TAG" "0"\r
- xput_define $config_file "configUSE_CO_ROUTINES" "0"\r
-\r
- # System timer tick rate (Microblaze only. kernel DRC ensures this)\r
- set systmr_interval [xget_value $os_handle "PARAMETER" "systmr_interval"]\r
- xput_define $config_file "configTICK_RATE_HZ" $systmr_interval\r
-\r
- set max_priorities [xget_value $os_handle "PARAMETER" "max_priorities"]\r
- xput_define $config_file "configMAX_PRIORITIES" $max_priorities\r
- xput_define $config_file "configMAX_CO_ROUTINE_PRIORITIES" "2"\r
- \r
- set min_stack [xget_value $os_handle "PARAMETER" "minimal_stack_size"]\r
- set min_stack [expr [expr $min_stack + 3] & 0xFFFFFFFC]\r
- xput_define $config_file "configMINIMAL_STACK_SIZE" $min_stack\r
-\r
- set total_heap_size [xget_value $os_handle "PARAMETER" "total_heap_size"]\r
- set total_heap_size [expr [expr $total_heap_size + 3] & 0xFFFFFFFC]\r
- xput_define $config_file "configTOTAL_HEAP_SIZE" $total_heap_size\r
-\r
- set max_task_name_len [xget_value $os_handle "PARAMETER" "max_task_name_len"]\r
- xput_define $config_file "configMAX_TASK_NAME_LEN" $max_task_name_len\r
- \r
- set val [xget_value $os_handle "PARAMETER" "idle_yield"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configIDLE_SHOULD_YIELD" "0"\r
- } else {\r
- xput_define $config_file "configIDLE_SHOULD_YIELD" "1"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "check_for_stack_overflow"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configCHECK_FOR_STACK_OVERFLOW" "0"\r
- } else {\r
- xput_define $config_file "configCHECK_FOR_STACK_OVERFLOW" "2"\r
- }\r
- \r
- set val [xget_value $os_handle "PARAMETER" "queue_registry_size"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configQUEUE_REGISTRY_SIZE" "0"\r
- } else {\r
- xput_define $config_file "configQUEUE_REGISTRY_SIZE" "10"\r
- }\r
-\r
- xput_define $config_file "configGENERATE_RUN_TIME_STATS" "0"\r
-\r
- set val [xget_value $os_handle "PARAMETER" "timer_task_priority"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configTIMER_TASK_PRIORITY" "0"\r
- } else {\r
- xput_define $config_file "configTIMER_TASK_PRIORITY" "10"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "timer_command_queue_length"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configTIMER_QUEUE_LENGTH" "0"\r
- } else {\r
- xput_define $config_file "configTIMER_QUEUE_LENGTH" "10"\r
- }\r
-\r
- set val [xget_value $os_handle "PARAMETER" "timer_task_stack_depth"]\r
- if {$val == "false"} {\r
- xput_define $config_file "configTIMER_TASK_STACK_DEPTH" "0"\r
- } else {\r
- xput_define $config_file "configTIMER_TASK_STACK_DEPTH" $min_stack\r
- }\r
-\r
- if { [mb_has_exceptions $hw_proc_handle] } { \r
- xput_define $config_file "configINSTALL_EXCEPTION_HANDLERS" "1"\r
- } else {\r
- xput_define $config_file "configINSTALL_EXCEPTION_HANDLERS" "0"\r
- }\r
-\r
- xput_define $config_file "configINTERRUPT_CONTROLLER_TO_USE" "XPAR_INTC_SINGLE_DEVICE_ID"\r
-\r
- xput_define $config_file "INCLUDE_vTaskCleanUpResources" "0"\r
- xput_define $config_file "INCLUDE_vTaskDelay" "1"\r
- xput_define $config_file "INCLUDE_vTaskDelayUntil" "1"\r
- xput_define $config_file "INCLUDE_vTaskDelete" "1"\r
- xput_define $config_file "INCLUDE_xTaskGetCurrentTaskHandle" "1"\r
- xput_define $config_file "INCLUDE_xTaskGetIdleTaskHandle" "1"\r
- xput_define $config_file "INCLUDE_xTaskGetSchedulerState" "1"\r
- xput_define $config_file "INCLUDE_xTimerGetTimerDaemonTaskHandle" "1"\r
- xput_define $config_file "INCLUDE_uxTaskGetStackHighWaterMark" "1"\r
- xput_define $config_file "INCLUDE_uxTaskPriorityGet" "1"\r
- xput_define $config_file "INCLUDE_vTaskPrioritySet" "1"\r
- xput_define $config_file "INCLUDE_xTaskResumeFromISR" "1"\r
- xput_define $config_file "INCLUDE_vTaskSuspend" "1"\r
- xput_define $config_file "INCLUDE_pcTaskGetTaskName" "1"\r
- xput_define $config_file "INCLUDE_xTaskGetIdleTaskHandle" "1"\r
- xput_define $config_file "INCLUDE_xTimerGetTimerDaemonTaskHandle" "1"\r
-\r
- # complete the header protectors\r
- puts $config_file "\#endif"\r
- close $config_file\r
-}\r
-\r
-proc xopen_new_include_file { filename description } {\r
- set inc_file [open $filename w]\r
- xprint_generated_header $inc_file $description\r
- set newfname [string map {. _} [lindex [split $filename {\/}] end]]\r
- puts $inc_file "\#ifndef _[string toupper $newfname]"\r
- puts $inc_file "\#define _[string toupper $newfname]\n\n"\r
- return $inc_file\r
-}\r
-\r
-proc xadd_define { config_file os_handle parameter } {\r
- set param_value [xget_value $os_handle "PARAMETER" $parameter]\r
- puts $config_file "#define [string toupper $parameter] $param_value\n"\r
-\r
- # puts "creating #define [string toupper $parameter] $param_value\n"\r
-}\r
-\r
-proc xput_define { config_file parameter param_value } {\r
- puts $config_file "#define $parameter $param_value\n"\r
-\r
- # puts "creating #define [string toupper $parameter] $param_value\n"\r
-}\r
-\r
-# args field of the array\r
-proc xadd_extern_fname {initfile oshandle arrayname arg} { \r
-\r
- set arrhandle [xget_handle $oshandle "ARRAY" $arrayname]\r
- set elements [xget_handle $arrhandle "ELEMENTS" "*"]\r
- set count 0\r
- set max_count [llength $elements]\r
-\r
- foreach ele $elements {\r
- incr count\r
- set arg_value [xget_value $ele "PARAMETER" $arg]\r
- puts $initfile "extern void $arg_value\(\)\;"\r
- }\r
- puts $initfile ""\r
-}\r
-\r
-# args is variable no - fields of the array\r
-proc xadd_struct {initfile oshandle structtype structname arrayname args} { \r
-\r
- set arrhandle [xget_handle $oshandle "ARRAY" $arrayname]\r
- set elements [xget_handle $arrhandle "ELEMENTS" "*"]\r
- set count 0\r
- set max_count [llength $elements]\r
- puts $initfile "struct $structtype $structname\[$max_count\] = \{"\r
-\r
- foreach ele $elements {\r
- incr count\r
- puts -nonewline $initfile "\t\{"\r
- foreach field $args {\r
- set field_value [xget_value $ele "PARAMETER" $field]\r
- # puts "$arrayname ( $count )->$field is $field_value"\r
- puts -nonewline $initfile "$field_value"\r
- if { $field != [lindex $args end] } {\r
- puts -nonewline $initfile ","\r
- }\r
- }\r
- if {$count < $max_count} {\r
- puts $initfile "\},"\r
- } else {\r
- puts $initfile "\}"\r
- }\r
- }\r
- puts $initfile "\}\;"\r
-}\r
-\r
-# return the sum of all the arg field values in arrayname\r
-proc get_field_sum {oshandle arrayname arg} { \r
-\r
- set arrhandle [xget_handle $oshandle "ARRAY" $arrayname]\r
- set elements [xget_handle $arrhandle "ELEMENTS" "*"]\r
- set count 0\r
- set max_count [llength $elements]\r
- \r
- foreach ele $elements {\r
- set field_value [xget_value $ele "PARAMETER" $arg]\r
- set count [expr $field_value+$count]\r
- }\r
- return $count\r
-}\r
-\r
-# return the sum of the product of field values in arrayname\r
-proc get_field_product_sum {oshandle arrayname field1 field2} { \r
-\r
- set arrhandle [xget_handle $oshandle "ARRAY" $arrayname]\r
- set elements [xget_handle $arrhandle "ELEMENTS" "*"]\r
- set count 0\r
- set max_count [llength $elements]\r
-\r
- foreach ele $elements {\r
- set field1_value [xget_value $ele "PARAMETER" $field1]\r
- set field2_value [xget_value $ele "PARAMETER" $field2]\r
- set incr_value [expr $field1_value*$field2_value]\r
- set count [expr $count+$incr_value]\r
- }\r
- return $count\r
-}\r
-\r
-proc xhandle_mb_interrupts {} {\r
-\r
- set default_interrupt_handler "XNullHandler"\r
- set default_arg "XNULL"\r
-\r
- set source_interrupt_handler $default_interrupt_handler\r
- set source_handler_arg $default_arg\r
- \r
- # Handle the interrupt pin\r
- set sw_proc_handle [xget_libgen_proc_handle] \r
- set periph [xget_handle $sw_proc_handle "IPINST"]\r
- set source_ports [xget_interrupt_sources $periph]\r
- if {[llength $source_ports] > 1} {\r
- error "Too many interrupting ports on the MicroBlaze. Should only find 1" "" "libgen_error"\r
- return\r
- }\r
- \r
- if {[llength $source_ports] == 1} {\r
- set source_port [lindex $source_ports 0]\r
- if {[llength $source_port] != 0} {\r
- set source_port_name [xget_value $source_port "VALUE"] \r
- set source_periph [xget_handle $source_port "PARENT"]\r
- set source_name [xget_value $source_periph "NAME"]\r
- set source_driver [xget_sw_driver_handle_for_ipinst $sw_proc_handle $source_name]\r
-\r
- if {[string compare -nocase $source_driver ""] != 0} {\r
- set int_array [xget_handle $source_driver "ARRAY" "interrupt_handler"]\r
- if {[llength $int_array] != 0} {\r
- set int_array_elems [xget_handle $int_array "ELEMENTS" "*"]\r
- if {[llength $int_array_elems] != 0} {\r
- foreach int_array_elem $int_array_elems {\r
- set int_port [xget_value $int_array_elem "PARAMETER" "int_port"]\r
- if {[llength $int_port] != 0} {\r
- if {[string compare -nocase $int_port $source_port_name] == 0 } {\r
- set source_interrupt_handler [xget_value $int_array_elem "PARAMETER" "int_handler"]\r
- set source_handler_arg [xget_value $int_array_elem "PARAMETER" "int_handler_arg"]\r
- if {[string compare -nocase $source_handler_arg DEVICE_ID] == 0 } {\r
- set source_handler_arg [xget_name $source_periph "DEVICE_ID"]\r
- } else {\r
- if {[string compare -nocase "global" [xget_port_type $source_port]] == 0} {\r
- set source_handler_arg $default_arg\r
- } else {\r
- set source_handler_arg [xget_name $source_periph "C_BASEADDR"]\r
- }\r
- }\r
- break\r
- }\r
- }\r
- }\r
- }\r
- }\r
- }\r
- }\r
- }\r
- \r
- # Generate microblaze_interrupts_g.c file...\r
- xcreate_mb_intr_config_file $source_interrupt_handler $source_handler_arg\r
- \r
-}\r
-\r
-\r
-proc xcreate_mb_intr_config_file {handler arg} {\r
- \r
- set mb_table "MB_InterruptVectorTable"\r
-\r
- set filename [file join "../standalone_v3_01_a/src" "microblaze_interrupts_g.c"] \r
- file delete $filename\r
- set config_file [open $filename w]\r
-\r
- xprint_generated_header $config_file "Interrupt Handler Table for MicroBlaze Processor"\r
- \r
- puts $config_file "#include \"microblaze_interrupts_i.h\""\r
- puts $config_file "#include \"xparameters.h\""\r
- puts $config_file "\n"\r
- puts $config_file [format "extern void %s (void *);" $handler]\r
- puts $config_file "\n/*"\r
- puts $config_file "* The interrupt handler table for microblaze processor"\r
- puts $config_file "*/\n"\r
- puts $config_file [format "%sEntry %s\[\] =" $mb_table $mb_table]\r
- puts $config_file "\{"\r
- puts -nonewline $config_file [format "\{\t%s" $handler]\r
- puts -nonewline $config_file [format ",\n\t(void*) %s\}" $arg]\r
- puts -nonewline $config_file "\n\};"\r
- puts $config_file "\n"\r
- close $config_file\r
-}\r
-\r
-\r
-# -------------------------------------------\r
-# Tcl procedure xcreate_mb_exc_config file\r
-# -------------------------------------------\r
-proc xcreate_mb_exc_config_file { } {\r
- \r
- set hfilename [file join "src" "microblaze_exceptions_g.h"] \r
- file delete $hfilename\r
- set hconfig_file [open $hfilename w]\r
-\r
- xprint_generated_header $hconfig_file "Exception Handling Header for MicroBlaze Processor"\r
- \r
- puts $hconfig_file "\n"\r
-\r
- set sw_proc_handle [xget_libgen_proc_handle]\r
- set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]\r
- set procver [xget_value $hw_proc_handle "PARAMETER" "HW_VER"]\r
-\r
- if { ![mb_has_exceptions $hw_proc_handle]} { ;# NO exceptions are enabled\r
- close $hconfig_file ;# Do not generate any info in either the header or the C file\r
- return\r
- }\r
- \r
- puts $hconfig_file "\#define MICROBLAZE_EXCEPTIONS_ENABLED 1"\r
- if { [mb_can_handle_exceptions_in_delay_slots $procver] } {\r
- puts $hconfig_file "#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS"\r
- }\r
-\r
- close $hconfig_file\r
-}\r
-\r
-# --------------------------------------\r
-# Tcl procedure post_generate\r
-# This proc removes from libxil.a the basic \r
-# and standalone BSP versions of \r
-# _interrupt_handler and _hw_exception_handler\r
-# routines\r
-# --------------------------------------\r
-proc post_generate {os_handle} {\r
- set sw_proc_handle [xget_libgen_proc_handle]\r
- set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]\r
- set proctype [xget_value $hw_proc_handle "OPTION" "IPNAME"]\r
- set procname [xget_value $hw_proc_handle "NAME"]\r
-\r
- set procdrv [xget_sw_driver_handle_for_ipinst $sw_proc_handle $procname]\r
- set archiver [xget_value $procdrv "PARAMETER" "archiver"]\r
-\r
- if {[string compare -nocase $proctype "microblaze"] == 0 } {\r
- # Remove _interrupt_handler.o from libxil.a for FreeRTOS\r
- set libxil_a [file join .. .. lib libxil.a]\r
- exec $archiver -d $libxil_a _interrupt_handler.o\r
-\r
- # We have linkage problems due to how these platforms are defined. Can't do this right now. \r
- # # Remove _exception_handler.o from libxil.a for FreeRTOS\r
- # exec bash -c "$archiver -d ../../lib/libxil.a _exception_handler.o"\r
- \r
- # Remove _hw_exception_handler.o from libxil.a for microblaze cores with exception support\r
- if {[mb_has_exceptions $hw_proc_handle]} {\r
- exec $archiver -d ../../lib/libxil.a _hw_exception_handler.o\r
- }\r
- }\r
-}\r
-\r
-# --------------------------------------\r
-# Tcl procedure execs_generate\r
-# This proc removes from libxil.a all \r
-# the stuff that we are overriding\r
-# with xilkernel\r
-# We currently override,\r
-# MicroBlaze\r
-# - Dummy _interrupt_hander and _hw_exception_handler \r
-# (in post_generate)\r
-# PPC\r
-# - xvectors.o; sleep.o (IF config_time is true)\r
-# Common to all processors\r
-# - errno.o\r
-# --------------------------------------\r
-proc execs_generate {os_handle} {\r
- set sw_proc_handle [xget_libgen_proc_handle]\r
- set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]\r
- set proctype [xget_value $hw_proc_handle "OPTION" "IPNAME"]\r
- set procname [xget_value $hw_proc_handle "NAME"]\r
-\r
- set procdrv [xget_sw_driver_handle_for_ipinst $sw_proc_handle $procname]\r
- # Remove _interrupt_handler.o from libxil.a for mb-gcc\r
- set archiver [xget_value $procdrv "PARAMETER" "archiver"]\r
-\r
- set libxil_a [file join .. .. lib libxil.a]\r
-# exec $archiver -d $libxil_a errno.o\r
-\r
- # We have linkage problems due to how these platforms are defined. Can't do this right now. \r
- # exec "$archiver -d $libxil_a microblaze_interrupt_handler.o"\r
-}\r
-\r
-# --------------------------------------\r
-# Return true if this MB has \r
-# exception handling support\r
-# --------------------------------------\r
-proc mb_has_exceptions { hw_proc_handle } {\r
- \r
- # Check if the following parameters exist on this MicroBlaze's MPD\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_UNALIGNED_EXCEPTIONS"]\r
- if { $ee != "" } {\r
- return true\r
- }\r
-\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_ILL_OPCODE_EXCEPTION"]\r
- if { $ee != "" } {\r
- return true\r
- }\r
-\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_IOPB_BUS_EXCEPTION"]\r
- if { $ee != "" } {\r
- return true\r
- }\r
-\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_DOPB_BUS_EXCEPTION"]\r
- if { $ee != "" } {\r
- return true\r
- }\r
-\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_DIV_BY_ZERO_EXCEPTION"]\r
- if { $ee != "" } {\r
- return true\r
- } \r
-\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_DIV_ZERO_EXCEPTION"]\r
- if { $ee != "" } {\r
- return true\r
- } \r
-\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_FPU_EXCEPTION"]\r
- if { $ee != "" } {\r
- return true\r
- } \r
-\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_USE_MMU"]\r
- if { $ee != "" && $ee != 0 } {\r
- return true\r
- } \r
-\r
- return false\r
-}\r
-\r
-# --------------------------------------\r
-# Return true if this MB has \r
-# FPU exception handling support\r
-# --------------------------------------\r
-proc mb_has_fpu_exceptions { hw_proc_handle } {\r
- \r
- # Check if the following parameters exist on this MicroBlaze's MPD\r
- set ee [xget_value $hw_proc_handle "PARAMETER" "C_FPU_EXCEPTION"]\r
- if { $ee != "" } {\r
- return true\r
- }\r
-\r
- return false\r
-}\r
-\r
-# --------------------------------------\r
-# Return true if this MB has PVR support\r
-# --------------------------------------\r
-proc mb_has_pvr { hw_proc_handle } {\r
- \r
- # Check if the following parameters exist on this MicroBlaze's MPD\r
- set pvr [xget_value $hw_proc_handle "PARAMETER" "C_PVR"]\r
- if { $pvr != "" } {\r
- return true\r
- } \r
-\r
- return false\r
-}\r
-\r
-# --------------------------------------\r
-# Return true if MB ver 'procver' has \r
-# support for handling exceptions in \r
-# delay slots\r
-# --------------------------------------\r
-proc mb_can_handle_exceptions_in_delay_slots { procver } {\r
- \r
- if { [string compare -nocase $procver "5.00.a"] >= 0 } {\r
- return true\r
- } else {\r
- return false\r
- }\r
-}\r
-\r
-# --------------------------------------------------------------------------\r
-# Gets all the handles that are memory controller cores.\r
-# --------------------------------------------------------------------------\r
-proc xget_memory_controller_handles { mhs } {\r
- set ret_list ""\r
-\r
- # Gets all MhsInsts in the system\r
- set mhsinsts [xget_hw_ipinst_handle $mhs "*"]\r
-\r
- # Loop thru each MhsInst and determine if have "ADDR_TYPE = MEMORY" in\r
- # the parameters.\r
- foreach mhsinst $mhsinsts {\r
- # Gets all parameters of the component\r
- set params [xget_hw_parameter_handle $mhsinst "*"]\r
-\r
- # Loop thru each param and find tag "ADDR_TYPE = MEMORY"\r
- foreach param $params {\r
- if {$param == 0} {\r
- continue\r
- } elseif {$param == ""} {\r
- continue\r
- }\r
- set addrTypeValue [ xget_hw_subproperty_value $param "ADDR_TYPE" ]\r
-\r
- # Found tag! Add MhsInst to list and break to go to next MhsInst\r
- if {[string compare -nocase $addrTypeValue "MEMORY"] == 0} {\r
- lappend ret_list $mhsinst\r
- break\r
- }\r
- }\r
- }\r
-\r
- return $ret_list\r
-}\r
+++ /dev/null
-The necessary files are copied to this BSP directory structure by executing \r
-the CreateProjectDirectoryStructure.bat batch file located in the \r
-FreeRTOS\\Demo\MicroBlaze_Spartan-6_EthernetLite\SDKProjects\RTOSDemoSource\r
-folder.
\ No newline at end of file
+++ /dev/null
-The FreeRTOS.org source code is licensed by the modified GNU General Public \r
-License (GPL) text provided below. The FreeRTOS download also includes \r
-demo application source code, some of which is provided by third parties \r
-AND IS LICENSED SEPARATELY FROM FREERTOS.ORG. \r
-\r
-For the avoidance of any doubt refer to the comment included at the top\r
-of each source and header file for license and copyright information.\r
-\r
-This is a list of files for which Real Time Engineers Ltd are not the \r
-copyright owner and are NOT COVERED BY THE GPL.\r
-\r
-\r
-1) Various header files provided by silicon manufacturers and tool vendors\r
- that define processor specific memory addresses and utility macros.\r
- Permission has been granted by the various copyright holders for these\r
- files to be included in the FreeRTOS download. Users must ensure license\r
- conditions are adhered to for any use other than compilation of the \r
- FreeRTOS demo applications.\r
-\r
-2) The uIP TCP/IP stack the copyright of which is held by Adam Dunkels.\r
- Users must ensure the open source license conditions stated at the top \r
- of each uIP source file is understood and adhered to.\r
-\r
-3) The lwIP TCP/IP stack the copyright of which is held by the Swedish \r
- Institute of Computer Science. Users must ensure the open source license \r
- conditions stated at the top of each lwIP source file is understood and \r
- adhered to.\r
-\r
-4) Various peripheral driver source files and binaries provided by silicon\r
- manufacturers and tool vendors. Permission has been granted by the\r
- various copyright holders for these files to be included in the FreeRTOS\r
- download. Users must ensure license conditions are adhered to for any\r
- use other than compilation of the FreeRTOS demo applications.\r
-\r
-5) The files contained within FreeRTOS\Demo\WizNET_DEMO_TERN_186\tern_code,\r
- which are slightly modified versions of code provided by and copyright to\r
- Tern Inc.\r
-\r
-Errors and omissions should be reported to Richard Barry, contact details for\r
-whom can be obtained from http://www.FreeRTOS.org.\r
-\r
-\r
-\r
-\r
-\r
-The GPL license text follows.\r
-\r
-A special exception to the GPL is included to allow you to distribute a \r
-combined work that includes FreeRTOS without being obliged to provide\r
-the source code for any proprietary components. See the licensing section\r
-of http://www.FreeRTOS.org for full details. The exception text is also\r
-included at the bottom of this file.\r
-\r
---------------------------------------------------------------------\r
-\r
-\r
-\r
- GNU GENERAL PUBLIC LICENSE\r
- Version 2, June 1991\r
-\r
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.\r
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
- Everyone is permitted to copy and distribute verbatim copies\r
- of this license document, but changing it is not allowed.\r
-\r
- Preamble\r
-\r
- The licenses for most software are designed to take away your\r
-freedom to share and change it. By contrast, the GNU General Public\r
-License is intended to guarantee your freedom to share and change free\r
-software--to make sure the software is free for all its users. This\r
-General Public License applies to most of the Free Software\r
-Foundation's software and to any other program whose authors commit to\r
-using it. (Some other Free Software Foundation software is covered by\r
-the GNU Library General Public License instead.) You can apply it to\r
-your programs, too.\r
-\r
- When we speak of free software, we are referring to freedom, not\r
-price. Our General Public Licenses are designed to make sure that you\r
-have the freedom to distribute copies of free software (and charge for\r
-this service if you wish), that you receive source code or can get it\r
-if you want it, that you can change the software or use pieces of it\r
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-\r
- To protect your rights, we need to make restrictions that forbid\r
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-\f\r
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- TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\r
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-FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN\r
-OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\r
-PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\r
-OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS\r
-TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE\r
-PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\r
-REPAIR OR CORRECTION.\r
-\r
- 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\r
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\r
-REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\r
-INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\r
-OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\r
-TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\r
-YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\r
-PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\r
-POSSIBILITY OF SUCH DAMAGES.\r
-\r
- END OF TERMS AND CONDITIONS\r
-\f\r
- How to Apply These Terms to Your New Programs\r
-\r
- If you develop a new program, and you want it to be of the greatest\r
-possible use to the public, the best way to achieve this is to make it\r
-free software which everyone can redistribute and change under these terms.\r
-\r
- To do so, attach the following notices to the program. It is safest\r
-to attach them to the start of each source file to most effectively\r
-convey the exclusion of warranty; and each file should have at least\r
-the "copyright" line and a pointer to where the full notice is found.\r
-\r
- <one line to give the program's name and a brief idea of what it does.>\r
- Copyright (C) <year> <name of author>\r
-\r
- This program is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU General Public License** as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- This program is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU General Public License for more details.\r
-\r
- You should have received a copy of the GNU General Public License\r
- along with this program; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-\r
-\r
-Also add information on how to contact you by electronic and paper mail.\r
-\r
-If the program is interactive, make it output a short notice like this\r
-when it starts in an interactive mode:\r
-\r
- Gnomovision version 69, Copyright (C) year name of author\r
- Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\r
- This is free software, and you are welcome to redistribute it\r
- under certain conditions; type `show c' for details.\r
-\r
-The hypothetical commands `show w' and `show c' should show the appropriate\r
-parts of the General Public License. Of course, the commands you use may\r
-be called something other than `show w' and `show c'; they could even be\r
-mouse-clicks or menu items--whatever suits your program.\r
-\r
-You should also get your employer (if you work as a programmer) or your\r
-school, if any, to sign a "copyright disclaimer" for the program, if\r
-necessary. Here is a sample; alter the names:\r
-\r
- Yoyodyne, Inc., hereby disclaims all copyright interest in the program\r
- `Gnomovision' (which makes passes at compilers) written by James Hacker.\r
-\r
- <signature of Ty Coon>, 1 April 1989\r
- Ty Coon, President of Vice\r
-\r
-This General Public License does not permit incorporating your program into\r
-proprietary programs. If your program is a subroutine library, you may\r
-consider it more useful to permit linking proprietary applications with the\r
-library. If this is what you want to do, use the GNU Library General\r
-Public License instead of this License.\r
-\r
-----------------------------------------------------------------------------\r
-\r
-The FreeRTOS GPL Exception Text:\r
-\r
-Any FreeRTOS source code, whether modified or in it's original release form, \r
-or whether in whole or in part, can only be distributed by you under the terms \r
-of the GNU General Public License plus this exception. An independent module is \r
-a module which is not derived from or based on FreeRTOS.\r
-\r
-Clause 1:\r
-\r
-Linking FreeRTOS statically or dynamically with other modules is making a \r
-combined work based on FreeRTOS. Thus, the terms and conditions of the GNU \r
-General Public License cover the whole combination.\r
-\r
-As a special exception, the copyright holder of FreeRTOS gives you permission \r
-to link FreeRTOS with independent modules that communicate with FreeRTOS \r
-solely through the FreeRTOS API interface, regardless of the license terms of \r
-these independent modules, and to copy and distribute the resulting combined \r
-work under terms of your choice, provided that\r
-\r
- + Every copy of the combined work is accompanied by a written statement that \r
- details to the recipient the version of FreeRTOS used and an offer by yourself \r
- to provide the FreeRTOS source code (including any modifications you may have \r
- made) should the recipient request it.\r
-\r
- + The combined work is not itself an RTOS, scheduler, kernel or related product.\r
-\r
- + The independent modules add significant and primary functionality to FreeRTOS \r
- and do not merely extend the existing functionality already present in FreeRTOS.\r
-\r
-Clause 2:\r
-\r
-FreeRTOS may not be used for any competitive or comparative purpose, including the \r
-publication of any form of run time or compile time metric, without the express \r
-permission of Real Time Engineers Ltd. (this is the norm within the industry and \r
-is intended to ensure information accuracy).\r
+++ /dev/null
-##############################################################################
-#
-# Copyright (c) 2010 Xilinx, Inc. All rights reserved.
-#
-# Xilinx, Inc.
-# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
-# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
-# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
-# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
-# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
-# AND FITNESS FOR A PARTICULAR PURPOSE.
-#
-# Top level Makefile
-#
-# $Id: $
-#
-##############################################################################
-
-#
-# Processor architecture
-# microblaze
-#
-ARCH = microblaze
-
-SYSTEMDIR = ../../..
-
-TOPDIR = .
-
-ARCH_PREFIX = mb
-
-#
-# gnu tools for Makefile
-#
-CC = $(ARCH_PREFIX)-gcc
-AR = $(ARCH_PREFIX)-ar
-CP = cp
-
-#
-# Compiler, linker and other options.
-#
-CFLAGS = ${COMPILER_FLAGS} ${EXTRA_COMPILER_FLAGS}
-
-#
-# System project directories.
-#
-LIBDIR = $(SYSTEMDIR)/lib
-INCLUDEDIR = $(SYSTEMDIR)/include
-
-# Kernel library.
-LIBFREERTOS = ${LIBDIR}/libfreertos.a
-
-INCLUDEFILES = ${TOPDIR}/*.h
-
-INCLUDES = -I$(INCLUDEDIR) \
- -I${TOPDIR}
-
-KERNEL_AR_OBJS = *.c *.S
-
-OUTS = *.o
-
-libs: $(KERNEL_AR_OBJS)
- @echo "Compiling FreeRTOS"
- @$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $^
- @$(ARCHIVER) -r ${LIBFREERTOS} ${OUTS}
- make clean
-
-.PHONY: include
-include:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OUTS}
+++ /dev/null
-Each real time kernel port consists of three files that contain the core kernel\r
-components and are common to every port, and one or more files that are \r
-specific to a particular microcontroller and/or compiler.\r
-\r
-\r
-+ The FreeRTOS/Source/Portable/MemMang directory contains the three sample \r
-memory allocators as described on the http://www.FreeRTOS.org WEB site.\r
-\r
-+ The other directories each contain files specific to a particular \r
-microcontroller or compiler.\r
-\r
-\r
-\r
-For example, if you are interested in the GCC port for the ATMega323 \r
-microcontroller then the port specific files are contained in\r
-FreeRTOS/Source/Portable/GCC/ATMega323 directory. If this is the only\r
-port you are interested in then all the other directories can be\r
-ignored.\r
-\r
+++ /dev/null
-Each real time kernel port consists of three files that contain the core kernel\r
-components and are common to every port, and one or more files that are \r
-specific to a particular microcontroller and or compiler.\r
-\r
-+ The FreeRTOS/Source directory contains the three files that are common to \r
-every port - list.c, queue.c and tasks.c. The kernel is contained within these \r
-three files. croutine.c implements the optional co-routine functionality - which\r
-is normally only used on very memory limited systems.\r
-\r
-+ The FreeRTOS/Source/Portable directory contains the files that are specific to \r
-a particular microcontroller and or compiler.\r
-\r
-+ The FreeRTOS/Source/include directory contains the real time kernel header \r
-files.\r
-\r
-See the readme file in the FreeRTOS/Source/Portable directory for more \r
-information.
\ No newline at end of file
+++ /dev/null
-The download includes the kernel source code, and a demo application for EVERY\r
-RTOS port. See http://www.freertos.org/a00017.html for full details of the \r
-directory structure and information on locating the files you require.\r
-\r
-The easiest way to use FreeRTOS is start start with one of the demo application \r
-projects. Once this is running the project can be modified to include your own\r
-source files. This way the correct files and compiler options will be \r
-automatically included in your application.\r
-\r
-+ The Source directory contains the real time kernel source files for every \r
-port. The kernel itself is only 3 files.\r
-\r
-+ The Demo directory contains the demo application source files for every \r
-port.\r
-\r
-+ The TraceCon directory contains the trace visualisation exe file.\r
-\r
-See the readme files in the respective directories for further information.\r
-\r
+++ /dev/null
-
- PARAMETER VERSION = 2.2.0
-
-
-BEGIN OS
- PARAMETER OS_NAME = freertos
- PARAMETER STDIN = *
- PARAMETER STDOUT = *
-END
+++ /dev/null
-proc swapp_get_name {} {
- return "FreeRTOS Hello World";
-}
-
-proc swapp_get_description {} {
- return "Let's say 'Hello World' in FreeRTOS.";
-}
-
-proc get_os {} {
- set oslist [xget_sw_modules "type" "os"];
- set os [lindex $oslist 0];
-
- if { $os == "" } {
- error "No Operating System specified in the Board Support Package.";
- }
-
- return $os;
-}
-
-proc get_stdout {} {
- set os [get_os];
- set stdout [xget_sw_module_parameter $os "STDOUT"];
- return $stdout;
-}
-
-proc check_stdout_hw {} {
- set uartlites [xget_ips "type" "uartlite"];
- set uart16550s [xget_ips "type" "uart16550"];
- if { ([llength $uartlites] == 0) && ([llength $uart16550s] == 0) } {
- # Check for MDM-Uart peripheral. The MDM would be listed as a peripheral
- # only if it has a UART interface. So no further check is required
- set mdmlist [xget_ips "type" "mdm"]
- if { [llength $mdmlist] == 0 } {
- error "This application requires a Uart IP in the hardware."
- }
- }
-}
-
-proc check_stdout_sw {} {
- set stdout [get_stdout];
- if { $stdout == "none" } {
- error "The STDOUT parameter is not set on the OS. Hello World requires stdout to be set."
- }
-}
-
-proc get_mem_size { memlist } {
- return [lindex $memlist 4];
-}
-
-proc require_memory {memsize} {
- set imemlist [xget_memory_ranges "access_type" "I"];
- set idmemlist [xget_memory_ranges "access_type" "ID"];
- set dmemlist [xget_memory_ranges "access_type" "D"];
-
- set memlist [concat $imemlist $idmemlist $dmemlist];
-
- while { [llength $memlist] > 3 } {
- set mem [lrange $memlist 0 4];
- set memlist [lreplace $memlist 0 4];
-
- if { [get_mem_size $mem] >= $memsize } {
- return 1;
- }
- }
-
- error "This application requires atleast $memsize bytes of memory.";
-}
-
-proc swapp_is_supported_hw {} {
- # check for uart peripheral
- check_stdout_hw;
-
- # require about 1M of memory
- require_memory "1000000";
-
- return 1;
-}
-
-proc swapp_is_supported_sw {} {
- # check for stdout being set
- check_stdout_sw;
-
- return 1;
-}
-
-proc generate_stdout_config { fid } {
- set stdout [get_stdout];
-
- # if stdout is uartlite, we don't have to generate anything
- set stdout_type [xget_ip_attribute "type" $stdout];
-
- if { [regexp -nocase "uartlite" $stdout_type] || [string match -nocase "mdm" $stdout_type] } {
- return;
- } elseif { [regexp -nocase "uart16550" $stdout_type] } {
- # mention that we have a 16550
- puts $fid "#define STDOUT_IS_16550";
-
- # and note down its base address
- set prefix "XPAR_";
- set postfix "_BASEADDR";
- set stdout_baseaddr_macro $prefix$stdout$postfix;
- set stdout_baseaddr_macro [string toupper $stdout_baseaddr_macro];
- puts $fid "#define STDOUT_BASEADDR $stdout_baseaddr_macro";
- }
-}
-
-# depending on the type of os (standalone|xilkernel), choose
-# the correct source files
-proc swapp_generate {} {
-
- # cleanup this file for writing
- set fid [open "platform_config.h" "w+"];
- puts $fid "#ifndef __PLATFORM_CONFIG_H_";
- puts $fid "#define __PLATFORM_CONFIG_H_\n";
-
- # if we have a uart16550 as stdout, then generate some config for that
- generate_stdout_config $fid;
-
- puts $fid "#endif";
- close $fid;
-}
-
-proc swapp_get_linker_constraints {} {
-
- # we need a 4k heap
- return "stack 40k heap 40k";
-}
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * FreeRTOS-main.c (this file) defines a very simple demo that creates two tasks,\r
- * one queue, and one timer.\r
- *\r
- * The main() Function:\r
- * main() creates one software timer, one queue, and two tasks. It then starts\r
- * the scheduler.\r
- *\r
- * The Queue Send Task:\r
- * The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
- * block for 200 milliseconds, before sending the value 100 to the queue that\r
- * was created within main(). Once the value is sent, the task loops back\r
- * around to block for another 200 milliseconds.\r
- *\r
- * The Queue Receive Task:\r
- * The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() sits in a loop that causes it to\r
- * repeatedly attempt to read data from the queue that was created within\r
- * main(). When data is received, the task checks the value of the data, and\r
- * if the value equals the expected 100, increments the ulRecieved variable.\r
- * The 'block time' parameter passed to the queue receive function specifies\r
- * that the task should be held in the Blocked state indefinitely to wait for\r
- * data to be available on the queue. The queue receive task will only leave\r
- * the Blocked state when the queue send task writes to the queue. As the queue\r
- * send task writes to the queue every 200 milliseconds, the queue receive task\r
- * leaves the Blocked state every 200 milliseconds, and therefore toggles the LED\r
- * every 200 milliseconds.\r
- *\r
- * The Software Timer:\r
- * The software timer is configured to be an "auto reset" timer. Its callback\r
- * function simply increments the ulCallback variable each time it executes.\r
- */\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "queue.h"\r
-#include "timers.h"\r
-\r
-/* BSP includes. */\r
-#include "xtmrctr.h"\r
-\r
-/* Priorities at which the tasks are created. */\r
-#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-\r
-/* The rate at which data is sent to the queue, specified in milliseconds, and\r
-converted to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
-\r
-/* The number of items the queue can hold. This is 1 as the receive task\r
-will remove items as they are added because it has the higher priority, meaning\r
-the send task should always find the queue empty. */\r
-#define mainQUEUE_LENGTH ( 1 )\r
-\r
-/* A block time of 0 simply means, "don't block". */\r
-#define mainDONT_BLOCK ( TickType_t ) 0\r
-\r
-/* The following constants describe the timer instance used in this application.\r
-They are defined here such that a user can easily change all the needed parameters\r
-in one place. */\r
-#define TIMER_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID\r
-#define TIMER_FREQ_HZ XPAR_TMRCTR_0_CLOCK_FREQ_HZ\r
-#define TIMER_INTR_ID XPAR_INTC_0_TMRCTR_0_VEC_ID\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * The tasks as described in the comments at the top of this file.\r
- */\r
-static void prvQueueReceiveTask( void *pvParameters );\r
-static void prvQueueSendTask( void *pvParameters );\r
-\r
-/*\r
- * The LED timer callback function. This does nothing but increment the\r
- * ulCallback variable each time it executes.\r
- */\r
-static void vSoftwareTimerCallback( TimerHandle_t xTimer );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The queue used by the queue send and queue receive tasks. */\r
-static QueueHandle_t xQueue = NULL;\r
-\r
-/* The LED software timer. This uses vSoftwareTimerCallback() as its callback\r
-function. */\r
-static TimerHandle_t xExampleSoftwareTimer = NULL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Structures that hold the state of the various peripherals used by this demo.\r
-These are used by the Xilinx peripheral driver API functions. */\r
-static XTmrCtr xTimer0Instance;\r
-\r
-/* The variable that is incremented each time the receive task receives the\r
-value 100. */\r
-static unsigned long ulReceived = 0UL;\r
-\r
-/* The variable that is incremented each time the software time callback function\r
-executes. */\r
-static unsigned long ulCallback = 0UL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-int main( void )\r
-{\r
- /***************************************************************************\r
- See http://www.FreeRTOS.org for full information on FreeRTOS, including\r
- an API reference, pdf API reference manuals, and FreeRTOS tutorial books.\r
-\r
- See http://www.freertos.org/Free-RTOS-for-Xilinx-MicroBlaze-on-Spartan-6-FPGA.html\r
- for comprehensive standalone FreeRTOS for MicroBlaze demos.\r
- ***************************************************************************/\r
-\r
- /* Create the queue used by the queue send and queue receive tasks as\r
- described in the comments at the top of this file. */\r
- xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
-\r
- /* Sanity check that the queue was created. */\r
- configASSERT( xQueue );\r
-\r
- /* Start the two tasks as described in the comments at the top of this\r
- file. */\r
- xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
- xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
-\r
- /* Create the software timer */\r
- xExampleSoftwareTimer = xTimerCreate( "SoftwareTimer", /* A text name, purely to help debugging. */\r
- ( 5000 / portTICK_PERIOD_MS ),/* The timer period, in this case 5000ms (5s). */\r
- pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
- ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
- vSoftwareTimerCallback /* The callback function that switches the LED off. */\r
- );\r
-\r
- /* Start the software timer. */\r
- xTimerStart( xExampleSoftwareTimer, mainDONT_BLOCK );\r
-\r
- /* Start the tasks and timer running. */\r
- vTaskStartScheduler();\r
-\r
- /* If all is well, the scheduler will now be running, and the following line\r
- will never be reached. If the following line does execute, then there was\r
- insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
- to be created. See the memory management section on the FreeRTOS web site\r
- for more details. */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The callback is executed when the software timer expires. */\r
-static void vSoftwareTimerCallback( TimerHandle_t xTimer )\r
-{\r
- /* Just increment the ulCallbac variable. */\r
- ulCallback++;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueSendTask( void *pvParameters )\r
-{\r
-TickType_t xNextWakeTime;\r
-const unsigned long ulValueToSend = 100UL;\r
-\r
- /* Initialise xNextWakeTime - this only needs to be done once. */\r
- xNextWakeTime = xTaskGetTickCount();\r
-\r
- for( ;; )\r
- {\r
- /* Place this task in the blocked state until it is time to run again.\r
- The block time is specified in ticks, the constant used converts ticks\r
- to ms. While in the Blocked state this task will not consume any CPU\r
- time. */\r
- vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
-\r
- /* Send to the queue - causing the queue receive task to unblock and\r
- toggle an LED. 0 is used as the block time so the sending operation\r
- will not block - it shouldn't need to block as the queue should always\r
- be empty at this point in the code. */\r
- xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueReceiveTask( void *pvParameters )\r
-{\r
-unsigned long ulReceivedValue;\r
-\r
- for( ;; )\r
- {\r
- /* Wait until something arrives in the queue - this task will block\r
- indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
- FreeRTOSConfig.h. */\r
- xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
-\r
- /* To get here something must have been received from the queue, but\r
- is it the expected value? If it is, increment the ulReceived variable. */\r
- if( ulReceivedValue == 100UL )\r
- {\r
- ulReceived++;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
- /* vApplicationMallocFailedHook() will only be called if\r
- configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
- function that will get called if a call to pvPortMalloc() fails.\r
- pvPortMalloc() is called internally by the kernel whenever a task, queue or\r
- semaphore is created. It is also called by various parts of the demo\r
- application. If heap_1.c or heap_2.c are used, then the size of the heap\r
- available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
- FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
- to query the size of free heap space that remains (although it does not\r
- provide information on how the remaining heap might be fragmented). */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( TaskHandle_t *pxTask, signed char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* vApplicationStackOverflowHook() will only be called if\r
- configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2. The handle and name\r
- of the offending task will be passed into the hook function via its\r
- parameters. However, when a stack has overflowed, it is possible that the\r
- parameters will have been corrupted, in which case the pxCurrentTCB variable\r
- can be inspected directly. */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIdleHook( void )\r
-{\r
- /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
- to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
- task. It is essential that code added to this hook function never attempts\r
- to block in any way (for example, call xQueueReceive() with a block time\r
- specified, or call vTaskDelay()). If the application makes use of the\r
- vTaskDelete() API function (as this demo application does) then it is also\r
- important that vApplicationIdleHook() is permitted to return to its calling\r
- function, because it is the responsibility of the idle task to clean up\r
- memory allocated by the kernel to any task that has since been deleted. */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationTickHook( void )\r
-{\r
- /* vApplicationTickHook() will only be called if configUSE_TICK_HOOK is set\r
- to 1 in FreeRTOSConfig.h. It executes from an interrupt context so must\r
- not use any FreeRTOS API functions that do not end in ...FromISR().\r
-\r
- This simple blinky demo does not use the tick hook, but a tick hook is\r
- required to be defined as the blinky and full demos share a\r
- FreeRTOSConfig.h header file. */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This is an application defined callback function used to install the tick\r
-interrupt handler. It is provided as an application callback because the kernel\r
-will run on lots of different MicroBlaze and FPGA configurations - there could\r
-be multiple timer instances in the hardware platform and the users can chose to\r
-use any one of them. This example uses Timer 0. If that is available in your\r
-hardware platform then this example callback implementation should not require\r
-modification. The definitions for the timer instance used are at the top of this\r
-file so that users can change them at one place based on the timer instance they\r
-use. The name of the interrupt handler that should be installed is vPortTickISR(),\r
-which the function below declares as an extern. */\r
-void vApplicationSetupTimerInterrupt( void )\r
-{\r
-portBASE_TYPE xStatus;\r
-const unsigned char ucTimerCounterNumber = ( unsigned char ) 0U;\r
-const unsigned long ulCounterValue = ( ( TIMER_FREQ_HZ / configTICK_RATE_HZ ) - 1UL );\r
-extern void vPortTickISR( void *pvUnused );\r
-\r
- /* Initialise the timer/counter. */\r
- xStatus = XTmrCtr_Initialize( &xTimer0Instance, TIMER_DEVICE_ID );\r
-\r
- if( xStatus == XST_SUCCESS )\r
- {\r
- /* Install the tick interrupt handler as the timer ISR.\r
- *NOTE* The xPortInstallInterruptHandler() API function must be used for\r
- this purpose. */\r
- xStatus = xPortInstallInterruptHandler( TIMER_INTR_ID, vPortTickISR, NULL );\r
- }\r
-\r
- if( xStatus == pdPASS )\r
- {\r
- /* Enable the timer interrupt in the interrupt controller.\r
- *NOTE* The vPortEnableInterrupt() API function must be used for this\r
- purpose. */\r
- vPortEnableInterrupt( TIMER_INTR_ID );\r
-\r
- /* Configure the timer interrupt handler. */\r
- XTmrCtr_SetHandler( &xTimer0Instance, ( void * ) vPortTickISR, NULL );\r
-\r
- /* Set the correct period for the timer. */\r
- XTmrCtr_SetResetValue( &xTimer0Instance, ucTimerCounterNumber, ulCounterValue );\r
-\r
- /* Enable the interrupts. Auto-reload mode is used to generate a\r
- periodic tick. Note that interrupts are disabled when this function is\r
- called, so interrupts will not start to be processed until the first\r
- task has started to run. */\r
- XTmrCtr_SetOptions( &xTimer0Instance, ucTimerCounterNumber, ( XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION | XTC_DOWN_COUNT_OPTION ) );\r
-\r
- /* Start the timer. */\r
- XTmrCtr_Start( &xTimer0Instance, ucTimerCounterNumber );\r
- }\r
-\r
- /* Sanity check that the function executed as expected. */\r
- configASSERT( ( xStatus == pdPASS ) );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This is an application defined callback function used to clear whichever\r
-interrupt was installed by the the vApplicationSetupTimerInterrupt() callback\r
-function - in this case the interrupt generated by the AXI timer. It is\r
-provided as an application callback because the kernel will run on lots of\r
-different MicroBlaze and FPGA configurations - not all of which will have the\r
-same timer peripherals defined or available. This example uses the AXI Timer 0.\r
-If that is available on your hardware platform then this example callback\r
-implementation should not require modification provided the example definition\r
-of vApplicationSetupTimerInterrupt() is also not modified. */\r
-void vApplicationClearTimerInterrupt( void )\r
-{\r
-unsigned long ulCSR;\r
-\r
- /* Clear the timer interrupt */\r
- ulCSR = XTmrCtr_GetControlStatusReg( XPAR_TMRCTR_0_BASEADDR, 0 );\r
- XTmrCtr_SetControlStatusReg( XPAR_TMRCTR_0_BASEADDR, 0, ulCSR );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-
-<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Wed Jul 27 11:49:37 2011">
-
- <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
-
- <EXTERNALPORTS>
- <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
- <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
- <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
- <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
- <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
- <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
- <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
- <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
- <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
- <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
- <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
- <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
- <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
- <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
- <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
- <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
- <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
- <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
- <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
- <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
- <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
- <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
- <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
- <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
- <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
- <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
- <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
- <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
- <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
- <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
- <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
- <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
- <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
- </EXTERNALPORTS>
-
- <MODULES>
- <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
- <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Base Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="2">
- <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of Master Slots </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
- <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
- <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>AXI Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff00000000c0000000">
- <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7ffffff">
- <DESCRIPTION>Master AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000">
- <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100">
- <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
- <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111101">
- <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5">
- <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5">
- <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003">
- <DESCRIPTION>AXI Connectivity</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100">
- <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
- <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000020">
- <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000002">
- <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
- <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
- <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Secure</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI W Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI R Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI B Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Generate Interrupts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
- <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
- <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Simulation debug</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="clk_100_0000MHzPLL0&clk_100_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0&clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
- <SIGNALS>
- <SIGNAL NAME="clk_100_0000MHzPLL0"/>
- <SIGNAL NAME="clk_100_0000MHzPLL0"/>
- </SIGNALS>
- </PORT>
- <PORT DEF_SIGNAME="axi4_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="15" MSB="9" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi4_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi4_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi4_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi4_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi4_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi4_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi4_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi4_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="38" MSB="9" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi4_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi4_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi4_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi4_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi4_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi4_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="axi4_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="59" MSB="4" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="axi4_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi4_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi4_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi4_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi4_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="axi4_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi4_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi4_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi4_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="axi4_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="84" MSB="4" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="axi4_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi4_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi4_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi4_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi4_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
- <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Base Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="7">
- <DESCRIPTION>Number of Master Slots </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
- <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
- <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002">
- <DESCRIPTION>AXI Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000002000000020000000200000002000000020000000200000002">
- <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000074800000">
- <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041c0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040e0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007480ffff">
- <DESCRIPTION>Master AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
- <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000102faf08002faf08002faf08002faf08002faf08002faf08002faf080">
- <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000">
- <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
- <DESCRIPTION>AXI Connectivity</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
- <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111101111">
- <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Secure</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI W Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI R Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI B Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Generate Interrupts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
- <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
- <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Simulation debug</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
- <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="3" MSB="6" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="48" MSB="6" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
- <SIGNALS>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- </SIGNALS>
- </PORT>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="49" MSB="6" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="50" MSB="223" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="51" MSB="55" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="52" MSB="20" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="53" MSB="13" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="54" MSB="13" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="55" MSB="27" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="56" MSB="20" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="57" MSB="27" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="58" MSB="27" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="59" MSB="6" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="60" MSB="6" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="61" MSB="6" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="62" MSB="6" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="63" MSB="223" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="64" MSB="27" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="65" MSB="6" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="66" MSB="6" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="67" MSB="6" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="68" MSB="6" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="69" MSB="6" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="70" MSB="13" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="71" MSB="6" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="72" MSB="6" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="73" MSB="6" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="74" MSB="6" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="75" MSB="223" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="76" MSB="55" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="77" MSB="20" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="78" MSB="13" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="79" MSB="13" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="80" MSB="27" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="81" MSB="20" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="82" MSB="27" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="83" MSB="27" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="84" MSB="6" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="85" MSB="6" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="86" MSB="6" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="87" MSB="6" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="88" MSB="223" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="89" MSB="13" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="90" MSB="6" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="91" MSB="6" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="92" MSB="6" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="93" MSB="6" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
- <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
- <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
- <PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Fault Tolerance Support</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0">
- <DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2">
- <DESCRIPTION>Select Bus Interfaces</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Select Stream Interfaces</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
- <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
- <PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Pattern Comparator</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Barrel Shifter</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="41" MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Integer Divider</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Integer Multiplier</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Floating Point Unit</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="40" MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="36" MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Instruction-side AXI Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="37" MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Data-side AXI Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="35" MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="34" MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Stream Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0">
- <DESCRIPTION><qt>Enable stack protection</qt></DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0">
- <DESCRIPTION>Specifies Processor Version Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00">
- <DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="7">
- <DESCRIPTION>Number of PC Breakpoints </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="2">
- <DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="2">
- <DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0">
- <DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1">
- <DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="39" MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="1">
- <DESCRIPTION><qt>Generate Illegal Instruction Exception for NULL Instruction</qt></DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Number of Stream Links </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Additional Stream Instructions</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
- <DESCRIPTION>I-Cache Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
- <DESCRIPTION>I-Cache High Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Instruction Cache </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable I-Cache Writes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="13"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
- <DESCRIPTION>Size of the I-Cache in Bytes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4">
- <DESCRIPTION>Instruction Cache Line Length</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
- <DESCRIPTION>Use Cache Links for All I-Cache Memory Accesses </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Number of I-Cache Victims</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Number of I-Cache Streams</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
- <DESCRIPTION>Use Distributed RAM for I-Cache Tags</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
- <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
- <DESCRIPTION>D-Cache Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
- <DESCRIPTION>D-Cache High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Data Cache</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable D-Cache Writes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="13"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
- <DESCRIPTION>Size of D-Cache in Bytes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4">
- <DESCRIPTION>Data Cache Line Length</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
- <DESCRIPTION>Use Cache Links for All D-Cache Memory Accesses </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Number of D-Cache Victims</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
- <DESCRIPTION>Use Distributed RAM for D-Cache Tags</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
- <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
- <PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0">
- <DESCRIPTION>Memory Management</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4">
- <DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2">
- <DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3">
- <DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16">
- <DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0">
- <DESCRIPTION>Privileged Instructions</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Branch Target Cache</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0">
- <DESCRIPTION>Branch Target Cache Size</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_M_AXI_DP_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_DP_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_DP_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_DP_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_DP_B_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_IC_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_IC_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_IC_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_IC_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_IC_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
- <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"/>
- <PORT BUS="DLMB:ILMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
- <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
- <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:31]"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="IPLB_MRearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="IPLB_MTimeout" SIGNAME="__NOC__"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="86" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="89" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="92" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="95" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="96" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="99" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="100" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="109" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="110" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="111" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="114" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="116" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="118" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="119" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="120" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="121" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="124" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="125" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="126" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="128" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="130" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="131" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="132" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="134" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="135" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="136" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="137" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="139" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="140" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="141" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="142" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="144" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="145" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="147" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="148" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="149" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="150" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="152" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="153" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="154" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="155" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="156" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="158" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RLAST" SIGNAME="axi4lite_0_S_RLAST"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="I" MPD_INDEX="160" NAME="M_AXI_DP_RVALID" SIGNAME="axi4lite_0_S_RVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="O" MPD_INDEX="161" NAME="M_AXI_DP_RREADY" SIGNAME="axi4lite_0_S_RREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="162" NAME="M_AXI_IC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="164" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="165" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="166" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="167" NAME="M_AXI_IC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="168" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="169" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="170" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="171" NAME="M_AXI_IC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="172" NAME="M_AXI_IC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="173" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="175" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="176" NAME="M_AXI_IC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="177" NAME="M_AXI_IC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="178" NAME="M_AXI_IC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="180" NAME="M_AXI_IC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="182" NAME="M_AXI_IC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="183" NAME="M_AXI_IC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="184" NAME="M_AXI_IC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="185" NAME="M_AXI_IC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="187" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="188" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="189" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="190" NAME="M_AXI_IC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="192" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="194" NAME="M_AXI_IC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="195" NAME="M_AXI_IC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="196" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="197" NAME="M_AXI_IC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="198" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="199" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_IC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="202" NAME="M_AXI_IC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="204" NAME="M_AXI_DC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="205" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="206" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="207" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="208" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="209" NAME="M_AXI_DC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="211" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="212" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="213" NAME="M_AXI_DC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="214" NAME="M_AXI_DC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="215" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="216" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="217" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="218" NAME="M_AXI_DC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="219" NAME="M_AXI_DC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="220" NAME="M_AXI_DC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="222" NAME="M_AXI_DC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="224" NAME="M_AXI_DC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="225" NAME="M_AXI_DC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="226" NAME="M_AXI_DC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="227" NAME="M_AXI_DC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="229" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="230" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="231" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="232" NAME="M_AXI_DC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="234" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="236" NAME="M_AXI_DC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="237" NAME="M_AXI_DC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="238" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="239" NAME="M_AXI_DC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="241" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="243" NAME="M_AXI_DC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="244" NAME="M_AXI_DC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="I" MPD_INDEX="246" NAME="DBG_CLK" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="I" MPD_INDEX="247" NAME="DBG_TDI" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="O" MPD_INDEX="248" NAME="DBG_TDO" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="249" MSB="0" NAME="DBG_REG_EN" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="I" MPD_INDEX="250" NAME="DBG_SHIFT" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="I" MPD_INDEX="251" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="I" MPD_INDEX="252" NAME="DBG_UPDATE" SIGNAME="microblaze_0_debug_Dbg_Update"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="I" MPD_INDEX="253" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_debug_Debug_Rst"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="254" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="255" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="256" MSB="0" NAME="Trace_PC" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="257" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="258" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="259" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="260" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="261" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="262" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="263" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="266" MSB="0" NAME="Trace_Data_Address" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="Trace_Data_Access" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="268" NAME="Trace_Data_Read" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="269" NAME="Trace_Data_Write" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="270" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="271" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="272" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="273" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="274" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="275" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="276" NAME="Trace_ICache_Req" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="277" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="278" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="279" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="280" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="281" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="286" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="287" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="288" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="289" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="290" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="291" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="292" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="293" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="294" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="295" NAME="FSL1_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="296" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="297" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="298" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="299" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="300" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="301" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="302" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="303" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="304" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="FSL2_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="306" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="307" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="308" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="309" NAME="FSL2_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="310" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="311" MSB="0" NAME="FSL2_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="FSL2_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="313" NAME="FSL2_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="FSL3_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="FSL3_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="316" MSB="0" NAME="FSL3_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="317" NAME="FSL3_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="318" NAME="FSL3_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="319" NAME="FSL3_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="320" NAME="FSL3_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="321" MSB="0" NAME="FSL3_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="FSL3_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="323" NAME="FSL3_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="324" NAME="FSL4_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="325" NAME="FSL4_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="326" MSB="0" NAME="FSL4_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="327" NAME="FSL4_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="328" NAME="FSL4_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="329" NAME="FSL4_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="330" NAME="FSL4_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="331" MSB="0" NAME="FSL4_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="332" NAME="FSL4_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="333" NAME="FSL4_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="334" NAME="FSL5_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="335" NAME="FSL5_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="336" MSB="0" NAME="FSL5_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="337" NAME="FSL5_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="338" NAME="FSL5_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="339" NAME="FSL5_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="340" NAME="FSL5_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="341" MSB="0" NAME="FSL5_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="342" NAME="FSL5_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="343" NAME="FSL5_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="344" NAME="FSL6_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="345" NAME="FSL6_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="346" MSB="0" NAME="FSL6_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="347" NAME="FSL6_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="348" NAME="FSL6_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="349" NAME="FSL6_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="350" NAME="FSL6_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="351" MSB="0" NAME="FSL6_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="352" NAME="FSL6_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="353" NAME="FSL6_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="354" NAME="FSL7_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="355" NAME="FSL7_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="356" MSB="0" NAME="FSL7_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="357" NAME="FSL7_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="358" NAME="FSL7_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="359" NAME="FSL7_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="360" NAME="FSL7_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="361" MSB="0" NAME="FSL7_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="362" NAME="FSL7_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="363" NAME="FSL7_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="364" NAME="FSL8_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="365" NAME="FSL8_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="366" MSB="0" NAME="FSL8_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="367" NAME="FSL8_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="368" NAME="FSL8_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="369" NAME="FSL8_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="370" NAME="FSL8_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="371" MSB="0" NAME="FSL8_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="372" NAME="FSL8_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="373" NAME="FSL8_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="374" NAME="FSL9_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="375" NAME="FSL9_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="376" MSB="0" NAME="FSL9_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="377" NAME="FSL9_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="378" NAME="FSL9_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="379" NAME="FSL9_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="380" NAME="FSL9_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="381" MSB="0" NAME="FSL9_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="382" NAME="FSL9_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="383" NAME="FSL9_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="384" NAME="FSL10_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="385" NAME="FSL10_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="386" MSB="0" NAME="FSL10_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="387" NAME="FSL10_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="388" NAME="FSL10_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="389" NAME="FSL10_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="390" NAME="FSL10_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="391" MSB="0" NAME="FSL10_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="392" NAME="FSL10_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="393" NAME="FSL10_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="394" NAME="FSL11_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="395" NAME="FSL11_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="396" MSB="0" NAME="FSL11_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="397" NAME="FSL11_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="398" NAME="FSL11_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="399" NAME="FSL11_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="400" NAME="FSL11_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="401" MSB="0" NAME="FSL11_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="402" NAME="FSL11_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="403" NAME="FSL11_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="404" NAME="FSL12_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="405" NAME="FSL12_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="406" MSB="0" NAME="FSL12_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="407" NAME="FSL12_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="408" NAME="FSL12_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="409" NAME="FSL12_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="410" NAME="FSL12_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="411" MSB="0" NAME="FSL12_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="412" NAME="FSL12_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="413" NAME="FSL12_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="414" NAME="FSL13_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="415" NAME="FSL13_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="416" MSB="0" NAME="FSL13_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="417" NAME="FSL13_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="418" NAME="FSL13_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="419" NAME="FSL13_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="420" NAME="FSL13_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="421" MSB="0" NAME="FSL13_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="422" NAME="FSL13_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="423" NAME="FSL13_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="424" NAME="FSL14_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="425" NAME="FSL14_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="426" MSB="0" NAME="FSL14_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="427" NAME="FSL14_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="428" NAME="FSL14_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="429" NAME="FSL14_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="430" NAME="FSL14_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="431" MSB="0" NAME="FSL14_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="432" NAME="FSL14_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="433" NAME="FSL14_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="434" NAME="FSL15_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="435" NAME="FSL15_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="436" MSB="0" NAME="FSL15_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="437" NAME="FSL15_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="438" NAME="FSL15_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="439" NAME="FSL15_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="440" NAME="FSL15_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="441" MSB="0" NAME="FSL15_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="442" NAME="FSL15_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="443" NAME="FSL15_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="444" NAME="M0_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="445" MSB="31" NAME="M0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M0_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="446" NAME="M0_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="447" NAME="M0_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="448" NAME="S0_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="449" MSB="31" NAME="S0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S0_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="450" NAME="S0_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="451" NAME="S0_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="452" NAME="M1_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="453" MSB="31" NAME="M1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M1_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="454" NAME="M1_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="455" NAME="M1_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="456" NAME="S1_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="457" MSB="31" NAME="S1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S1_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="458" NAME="S1_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="459" NAME="S1_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="460" NAME="M2_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="461" MSB="31" NAME="M2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M2_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="462" NAME="M2_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="463" NAME="M2_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="464" NAME="S2_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="465" MSB="31" NAME="S2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S2_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="466" NAME="S2_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="467" NAME="S2_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="468" NAME="M3_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="469" MSB="31" NAME="M3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M3_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="470" NAME="M3_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="471" NAME="M3_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="472" NAME="S3_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="473" MSB="31" NAME="S3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S3_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="474" NAME="S3_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="475" NAME="S3_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="476" NAME="M4_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="477" MSB="31" NAME="M4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M4_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="478" NAME="M4_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="479" NAME="M4_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="480" NAME="S4_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="481" MSB="31" NAME="S4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S4_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="482" NAME="S4_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="483" NAME="S4_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="484" NAME="M5_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="485" MSB="31" NAME="M5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M5_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="486" NAME="M5_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="487" NAME="M5_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="488" NAME="S5_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="489" MSB="31" NAME="S5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S5_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="490" NAME="S5_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="491" NAME="S5_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="492" NAME="M6_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="493" MSB="31" NAME="M6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M6_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="494" NAME="M6_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="495" NAME="M6_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="496" NAME="S6_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="497" MSB="31" NAME="S6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S6_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="498" NAME="S6_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="499" NAME="S6_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="500" NAME="M7_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="501" MSB="31" NAME="M7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M7_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="502" NAME="M7_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="503" NAME="M7_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="504" NAME="S7_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="505" MSB="31" NAME="S7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S7_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="506" NAME="S7_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="507" NAME="S7_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="508" NAME="M8_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="509" MSB="31" NAME="M8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M8_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="510" NAME="M8_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="511" NAME="M8_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="512" NAME="S8_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="513" MSB="31" NAME="S8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S8_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="514" NAME="S8_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="515" NAME="S8_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="516" NAME="M9_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="517" MSB="31" NAME="M9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M9_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="518" NAME="M9_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="519" NAME="M9_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="520" NAME="S9_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="521" MSB="31" NAME="S9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S9_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="522" NAME="S9_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="523" NAME="S9_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="524" NAME="M10_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="525" MSB="31" NAME="M10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M10_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="526" NAME="M10_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="527" NAME="M10_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="528" NAME="S10_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="529" MSB="31" NAME="S10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S10_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="530" NAME="S10_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="531" NAME="S10_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="532" NAME="M11_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="533" MSB="31" NAME="M11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M11_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="534" NAME="M11_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="535" NAME="M11_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="536" NAME="S11_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="537" MSB="31" NAME="S11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S11_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="538" NAME="S11_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="539" NAME="S11_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="540" NAME="M12_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="541" MSB="31" NAME="M12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M12_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="542" NAME="M12_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="543" NAME="M12_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="544" NAME="S12_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="545" MSB="31" NAME="S12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S12_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="546" NAME="S12_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="547" NAME="S12_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="548" NAME="M13_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="549" MSB="31" NAME="M13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M13_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="550" NAME="M13_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="551" NAME="M13_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="552" NAME="S13_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="553" MSB="31" NAME="S13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S13_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="554" NAME="S13_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="555" NAME="S13_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="556" NAME="M14_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="557" MSB="31" NAME="M14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M14_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="558" NAME="M14_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="559" NAME="M14_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="560" NAME="S14_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="561" MSB="31" NAME="S14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S14_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="562" NAME="S14_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="563" NAME="S14_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="564" NAME="M15_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="565" MSB="31" NAME="M15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M15_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="566" NAME="M15_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="567" NAME="M15_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="568" NAME="S15_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="569" MSB="31" NAME="S15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S15_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="570" NAME="S15_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="571" NAME="S15_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="572" NAME="ICACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="573" NAME="ICACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="574" MSB="0" NAME="ICACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="575" NAME="ICACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="576" NAME="ICACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="577" NAME="ICACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="578" NAME="ICACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="579" MSB="0" NAME="ICACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="580" NAME="ICACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="581" NAME="ICACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="582" NAME="DCACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="583" NAME="DCACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="584" MSB="0" NAME="DCACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="585" NAME="DCACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="586" NAME="DCACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="587" NAME="DCACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="588" NAME="DCACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="589" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="590" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="591" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="I" PHYSICAL="RESET"/>
- <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
- <PORTMAP DIR="I" PHYSICAL="DREADY"/>
- <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
- <PORTMAP DIR="I" PHYSICAL="DCE"/>
- <PORTMAP DIR="I" PHYSICAL="DUE"/>
- <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
- <PORTMAP DIR="O" PHYSICAL="D_AS"/>
- <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
- <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
- <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="I" PHYSICAL="RESET"/>
- <PORTMAP DIR="I" PHYSICAL="INSTR"/>
- <PORTMAP DIR="I" PHYSICAL="IREADY"/>
- <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
- <PORTMAP DIR="I" PHYSICAL="ICE"/>
- <PORTMAP DIR="I" PHYSICAL="IUE"/>
- <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
- <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
- <PORTMAP DIR="O" PHYSICAL="I_AS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="2" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
- <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
- <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" INSTANCE="Ethernet_Lite" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="microblaze_0_intc" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" INSTANCE="MCB_DDR3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="134217728" SIZEABRV="128M">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- </MEMORYMAP>
- <PERIPHERALS>
- <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/>
- <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/>
- <PERIPHERAL INSTANCE="debug_module"/>
- <PERIPHERAL INSTANCE="RS232_Uart_1"/>
- <PERIPHERAL INSTANCE="LEDs_4Bits"/>
- <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/>
- <PERIPHERAL INSTANCE="Ethernet_Lite"/>
- <PERIPHERAL INSTANCE="axi_timer_0"/>
- <PERIPHERAL INSTANCE="microblaze_0_intc"/>
- <PERIPHERAL INSTANCE="MCB_DDR3"/>
- </PERIPHERALS>
- <INTERRUPTINFO TYPE="TARGET">
- <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
- <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
- <DESCRIPTION>Active High External Reset</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- </PORTS>
- <BUSINTERFACES/>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
- <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
- <DESCRIPTION>Active High External Reset</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- </PORTS>
- <BUSINTERFACES/>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
- <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
- <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x40000000">
- <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
- <DESCRIPTION>Error Correction Code </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Select Interconnect </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
- <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
- <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
- <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
- <DESCRIPTION>Write Access setting </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
- <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
- <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SLMB"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
- <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
- <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x40000000">
- <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
- <DESCRIPTION>Error Correction Code </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Select Interconnect </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
- <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
- <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
- <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
- <DESCRIPTION>Write Access setting </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
- <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
- <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SLMB"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
- <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000">
- <DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
- <DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
- <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t">
- <DESCRIPTION>Device Subfamily</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
- <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
- <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>External Reset Active High </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
- <PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
- <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
- <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
- <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
- <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
- <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
- <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
- <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t">
- <DESCRIPTION>Device</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484">
- <DESCRIPTION>Package</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3">
- <DESCRIPTION>Speed Grade</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000">
- <DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="600000000">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Buffered </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="600000000">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0">
- <DESCRIPTION>Required Group </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0">
- <DESCRIPTION>Required Group </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Varaible Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="50000000">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="PLL0">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION> Varaible Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION> Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION> Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Clock Deskew</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Variable Phase Shift</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
- <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET"/>
- <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
- <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES/>
- </MODULE>
- <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
- <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2">
- <DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2">
- <DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x74800000">
- <DESCRIPTION>Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x7480ffff">
- <DESCRIPTION>High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3">
- <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8">
- <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Enable JTAG UART </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocal</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
- <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
- <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_debug_Dbg_Update"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_debug_Debug_Rst"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
- <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/>
- <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/>
- <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/>
- <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/>
- <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
- <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
- <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
- <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB"/>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
- <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
- <DESCRIPTION>AXI Clock Frequency </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200">
- <DESCRIPTION>UART Lite Baud Rate </DESCRIPTION>
- <DESCRIPTION>Baud Rate</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8">
- <DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION>
- <DESCRIPTION>Data Bits</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Use Parity </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Parity Type </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout">
- <DESCRIPTION>Serial Data Out</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin">
- <DESCRIPTION>Serial Data In</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="TX"/>
- <PORTMAP DIR="I" PHYSICAL="RX"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
- <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
- <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
- <DESCRIPTION>GPIO Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
- <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
- <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
- <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
- </PORT>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
- <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
- <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
- <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
- <DESCRIPTION>GPIO Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
- <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
- <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
- <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
- </PORT>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
- <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
- <DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Spartan-6 memory controller</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="R7"/>
- <PARAMETER MPD_INDEX="3" NAME="C_MCB_PERFORMANCE" TYPE="STRING" VALUE="STANDARD"/>
- <PARAMETER MPD_INDEX="4" NAME="C_BYPASS_CORE_UCF" VALUE="0"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="5" NAME="C_S0_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc0000000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="6" NAME="C_S0_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc7ffffff"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="7" NAME="C_S1_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="8" NAME="C_S1_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="9" NAME="C_S2_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="10" NAME="C_S2_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="11" NAME="C_S3_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="12" NAME="C_S3_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="13" NAME="C_S4_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="14" NAME="C_S4_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="15" NAME="C_S5_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_S5_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="18" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT41J64M16XX-187E"/>
- <PARAMETER MPD_INDEX="19" NAME="C_MEM_BASEPARTNO" TYPE="STRING" VALUE="NOT_SET"/>
- <PARAMETER MPD_INDEX="20" NAME="C_NUM_DQ_PINS" TYPE="INTEGER" VALUE="16"/>
- <PARAMETER MPD_INDEX="21" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="22" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="23" NAME="C_MEM_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="24" NAME="C_MEM_TRAS" TYPE="INTEGER" VALUE="37500"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="25" NAME="C_MEM_TRCD" TYPE="INTEGER" VALUE="13130"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="26" NAME="C_MEM_TREFI" TYPE="INTEGER" VALUE="7800000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_MEM_TRFC" TYPE="INTEGER" VALUE="160000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_MEM_TRP" TYPE="INTEGER" VALUE="13130"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="29" NAME="C_MEM_TWR" TYPE="INTEGER" VALUE="15000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="30" NAME="C_MEM_TRTP" TYPE="INTEGER" VALUE="7500"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="31" NAME="C_MEM_TWTR" TYPE="INTEGER" VALUE="7500"/>
- <PARAMETER MPD_INDEX="32" NAME="C_PORT_CONFIG" TYPE="STRING" VALUE="B32_B32_B32_B32"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="33" NAME="C_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="34" NAME="C_SKIP_IN_TERM_CAL_VALUE" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_MEMCLK_PERIOD" TYPE="INTEGER" VALUE="3333"/>
- <PARAMETER MPD_INDEX="36" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="ROW_BANK_COLUMN"/>
- <PARAMETER MPD_INDEX="37" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/>
- <PARAMETER MPD_INDEX="38" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
- <PARAMETER MPD_INDEX="39" NAME="C_SIMULATION" TYPE="STRING" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="40" NAME="C_MEM_DDR1_2_ODS" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="41" NAME="C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
- <PARAMETER MPD_INDEX="42" NAME="C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
- <PARAMETER MPD_INDEX="43" NAME="C_MEM_DDR2_RTT" TYPE="STRING" VALUE="150OHMS"/>
- <PARAMETER MPD_INDEX="44" NAME="C_MEM_DDR2_DIFF_DQS_EN" TYPE="STRING" VALUE="YES"/>
- <PARAMETER MPD_INDEX="45" NAME="C_MEM_DDR2_3_PA_SR" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="46" NAME="C_MEM_DDR2_3_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/>
- <PARAMETER MPD_INDEX="47" NAME="C_MEM_DDR3_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/>
- <PARAMETER MPD_INDEX="48" NAME="C_MEM_DDR3_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
- <PARAMETER MPD_INDEX="49" NAME="C_MEM_DDR3_ODS" TYPE="STRING" VALUE="DIV6"/>
- <PARAMETER MPD_INDEX="50" NAME="C_MEM_DDR3_RTT" TYPE="STRING" VALUE="DIV4"/>
- <PARAMETER MPD_INDEX="51" NAME="C_MEM_DDR3_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/>
- <PARAMETER MPD_INDEX="52" NAME="C_MEM_MOBILE_PA_SR" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="53" NAME="C_MEM_MDDR_ODS" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="54" NAME="C_ARB_ALGORITHM" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="55" NAME="C_ARB_NUM_TIME_SLOTS" TYPE="INTEGER" VALUE="12"/>
- <PARAMETER MPD_INDEX="56" NAME="C_ARB_TIME_SLOT_0" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="57" NAME="C_ARB_TIME_SLOT_1" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="58" NAME="C_ARB_TIME_SLOT_2" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="59" NAME="C_ARB_TIME_SLOT_3" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER MPD_INDEX="60" NAME="C_ARB_TIME_SLOT_4" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="61" NAME="C_ARB_TIME_SLOT_5" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="62" NAME="C_ARB_TIME_SLOT_6" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="63" NAME="C_ARB_TIME_SLOT_7" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER MPD_INDEX="64" NAME="C_ARB_TIME_SLOT_8" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="65" NAME="C_ARB_TIME_SLOT_9" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="66" NAME="C_ARB_TIME_SLOT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="67" NAME="C_ARB_TIME_SLOT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="68" NAME="C_S0_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="69" NAME="C_S0_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="70" NAME="C_S0_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="71" NAME="C_S0_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="72" NAME="C_S0_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="73" NAME="C_S0_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="74" NAME="C_S0_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="75" NAME="C_S0_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="76" NAME="C_S0_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
- <PARAMETER MPD_INDEX="77" NAME="C_S0_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="78" NAME="C_S0_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="79" NAME="C_S0_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="80" NAME="C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="81" NAME="C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="82" NAME="C_S1_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="83" NAME="C_S1_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="84" NAME="C_S1_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="85" NAME="C_S1_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="86" NAME="C_S1_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="87" NAME="C_S1_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="88" NAME="C_S1_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="89" NAME="C_S1_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="90" NAME="C_S1_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="91" NAME="C_S1_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="92" NAME="C_S1_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="93" NAME="C_S1_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="94" NAME="C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="95" NAME="C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="96" NAME="C_S2_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="97" NAME="C_S2_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="98" NAME="C_S2_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="99" NAME="C_S2_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="100" NAME="C_S2_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="101" NAME="C_S2_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="102" NAME="C_S2_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="103" NAME="C_S2_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="104" NAME="C_S2_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="105" NAME="C_S2_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="106" NAME="C_S2_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="107" NAME="C_S2_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="108" NAME="C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="109" NAME="C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="110" NAME="C_S3_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="111" NAME="C_S3_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="112" NAME="C_S3_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="113" NAME="C_S3_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="114" NAME="C_S3_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="115" NAME="C_S3_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="116" NAME="C_S3_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="117" NAME="C_S3_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="118" NAME="C_S3_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="119" NAME="C_S3_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="120" NAME="C_S3_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="121" NAME="C_S3_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="122" NAME="C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="123" NAME="C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="124" NAME="C_S4_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="125" NAME="C_S4_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="126" NAME="C_S4_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="127" NAME="C_S4_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="128" NAME="C_S4_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="129" NAME="C_S4_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="130" NAME="C_S4_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="131" NAME="C_S4_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="132" NAME="C_S4_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="133" NAME="C_S4_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="134" NAME="C_S4_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="135" NAME="C_S4_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="136" NAME="C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="137" NAME="C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="138" NAME="C_S5_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="139" NAME="C_S5_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="140" NAME="C_S5_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="141" NAME="C_S5_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="142" NAME="C_S5_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="143" NAME="C_S5_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_S5_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="145" NAME="C_S5_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="146" NAME="C_S5_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="147" NAME="C_S5_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="148" NAME="C_S5_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="149" NAME="C_S5_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="150" NAME="C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="151" NAME="C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="152" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="153" NAME="C_SYS_RST_PRESENT" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S0_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" NAME="C_INTERCONNECT_S0_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" NAME="C_INTERCONNECT_S0_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" NAME="C_INTERCONNECT_S0_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S0_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S0_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="17" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="18" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="16" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="26" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="9" MPD_INDEX="12" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="10" MPD_INDEX="11" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="27" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="15" LSB="0" MHS_INDEX="12" MPD_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq" VECFORMULA="[C_NUM_DQ_PINS-1:0]"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="13" MPD_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="14" MPD_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="15" MPD_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="16" MPD_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="17" MPD_INDEX="28" NAME="rzq" SIGNAME="rzq"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="18" MPD_INDEX="29" NAME="zio" SIGNAME="zio"/>
- <PORT BUS="S0_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="32" NAME="s0_axi_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="30" NAME="ui_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="0" NAME="sysclk_2x" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
- <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="1" NAME="sysclk_2x_180" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="10" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="4" NAME="PLL_LOCK" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="2" NAME="pll_ce_0" SIGNAME="__NOC__"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="pll_ce_90" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="5" NAME="pll_lock_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="6" NAME="sysclk_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="7" NAME="sysclk_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="8" NAME="pll_ce_0_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="9" NAME="pll_ce_90_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="31" NAME="uo_done_cal" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_aresetn" DIR="I" MPD_INDEX="33" NAME="s0_axi_aresetn" SIGIS="RST" SIGNAME="axi4_0_M_aresetn"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awid" DIR="I" MPD_INDEX="34" NAME="s0_axi_awid" SIGNAME="axi4_0_M_awid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="35" MSB="31" NAME="s0_axi_awaddr" RIGHT="0" SIGNAME="axi4_0_M_awaddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="36" MSB="7" NAME="s0_axi_awlen" RIGHT="0" SIGNAME="axi4_0_M_awlen" VECFORMULA="[7:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="s0_axi_awsize" RIGHT="0" SIGNAME="axi4_0_M_awsize" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="s0_axi_awburst" RIGHT="0" SIGNAME="axi4_0_M_awburst" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlock" DIR="I" MPD_INDEX="39" NAME="s0_axi_awlock" SIGNAME="axi4_0_M_awlock" VECFORMULA="[0:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="40" MSB="3" NAME="s0_axi_awcache" RIGHT="0" SIGNAME="axi4_0_M_awcache" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="s0_axi_awprot" RIGHT="0" SIGNAME="axi4_0_M_awprot" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s0_axi_awqos" RIGHT="0" SIGNAME="axi4_0_M_awqos" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awvalid" DIR="I" MPD_INDEX="43" NAME="s0_axi_awvalid" SIGNAME="axi4_0_M_awvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awready" DIR="O" MPD_INDEX="44" NAME="s0_axi_awready" SIGNAME="axi4_0_M_awready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="s0_axi_wdata" RIGHT="0" SIGNAME="axi4_0_M_wdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s0_axi_wstrb" RIGHT="0" SIGNAME="axi4_0_M_wstrb" VECFORMULA="[((C_S0_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wlast" DIR="I" MPD_INDEX="47" NAME="s0_axi_wlast" SIGNAME="axi4_0_M_wlast"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wvalid" DIR="I" MPD_INDEX="48" NAME="s0_axi_wvalid" SIGNAME="axi4_0_M_wvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wready" DIR="O" MPD_INDEX="49" NAME="s0_axi_wready" SIGNAME="axi4_0_M_wready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bid" DIR="O" MPD_INDEX="50" NAME="s0_axi_bid" SIGNAME="axi4_0_M_bid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="51" MSB="1" NAME="s0_axi_bresp" RIGHT="0" SIGNAME="axi4_0_M_bresp" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bvalid" DIR="O" MPD_INDEX="52" NAME="s0_axi_bvalid" SIGNAME="axi4_0_M_bvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bready" DIR="I" MPD_INDEX="53" NAME="s0_axi_bready" SIGNAME="axi4_0_M_bready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arid" DIR="I" MPD_INDEX="54" NAME="s0_axi_arid" SIGNAME="axi4_0_M_arid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="55" MSB="31" NAME="s0_axi_araddr" RIGHT="0" SIGNAME="axi4_0_M_araddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="56" MSB="7" NAME="s0_axi_arlen" RIGHT="0" SIGNAME="axi4_0_M_arlen" VECFORMULA="[7:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="57" MSB="2" NAME="s0_axi_arsize" RIGHT="0" SIGNAME="axi4_0_M_arsize" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="58" MSB="1" NAME="s0_axi_arburst" RIGHT="0" SIGNAME="axi4_0_M_arburst" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlock" DIR="I" MPD_INDEX="59" NAME="s0_axi_arlock" SIGNAME="axi4_0_M_arlock" VECFORMULA="[0:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="60" MSB="3" NAME="s0_axi_arcache" RIGHT="0" SIGNAME="axi4_0_M_arcache" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="s0_axi_arprot" RIGHT="0" SIGNAME="axi4_0_M_arprot" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="62" MSB="3" NAME="s0_axi_arqos" RIGHT="0" SIGNAME="axi4_0_M_arqos" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arvalid" DIR="I" MPD_INDEX="63" NAME="s0_axi_arvalid" SIGNAME="axi4_0_M_arvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arready" DIR="O" MPD_INDEX="64" NAME="s0_axi_arready" SIGNAME="axi4_0_M_arready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rid" DIR="O" MPD_INDEX="65" NAME="s0_axi_rid" SIGNAME="axi4_0_M_rid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="s0_axi_rdata" RIGHT="0" SIGNAME="axi4_0_M_rdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="67" MSB="1" NAME="s0_axi_rresp" RIGHT="0" SIGNAME="axi4_0_M_rresp" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rlast" DIR="O" MPD_INDEX="68" NAME="s0_axi_rlast" SIGNAME="axi4_0_M_rlast"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rvalid" DIR="O" MPD_INDEX="69" NAME="s0_axi_rvalid" SIGNAME="axi4_0_M_rvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rready" DIR="I" MPD_INDEX="70" NAME="s0_axi_rready" SIGNAME="axi4_0_M_rready"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="71" NAME="s1_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="s1_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="73" MSB="3" NAME="s1_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="74" MSB="31" NAME="s1_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="75" MSB="7" NAME="s1_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="76" MSB="2" NAME="s1_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="s1_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="s1_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="s1_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="80" MSB="2" NAME="s1_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="s1_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="s1_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="83" NAME="s1_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="84" MSB="31" NAME="s1_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="85" MSB="3" NAME="s1_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S1_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="86" NAME="s1_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="s1_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="s1_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="89" MSB="3" NAME="s1_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="90" MSB="1" NAME="s1_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="s1_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="92" NAME="s1_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="s1_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="s1_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="95" MSB="7" NAME="s1_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="96" MSB="2" NAME="s1_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="97" MSB="1" NAME="s1_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="s1_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="s1_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="100" MSB="2" NAME="s1_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="101" MSB="3" NAME="s1_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="s1_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="s1_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="104" MSB="3" NAME="s1_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="105" MSB="31" NAME="s1_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="106" MSB="1" NAME="s1_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="s1_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="s1_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="s1_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="110" NAME="s2_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="111" NAME="s2_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="112" MSB="3" NAME="s2_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="113" MSB="31" NAME="s2_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="s2_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="s2_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="116" MSB="1" NAME="s2_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="117" NAME="s2_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="118" MSB="3" NAME="s2_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="119" MSB="2" NAME="s2_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="120" MSB="3" NAME="s2_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="121" NAME="s2_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="s2_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="123" MSB="31" NAME="s2_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="124" MSB="3" NAME="s2_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S2_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="125" NAME="s2_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="126" NAME="s2_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="s2_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="128" MSB="3" NAME="s2_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="s2_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="130" NAME="s2_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="131" NAME="s2_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="132" MSB="3" NAME="s2_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="133" MSB="31" NAME="s2_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="s2_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="135" MSB="2" NAME="s2_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="136" MSB="1" NAME="s2_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="137" NAME="s2_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="138" MSB="3" NAME="s2_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="139" MSB="2" NAME="s2_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="140" MSB="3" NAME="s2_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="141" NAME="s2_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="s2_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="143" MSB="3" NAME="s2_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="144" MSB="31" NAME="s2_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="145" MSB="1" NAME="s2_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="146" NAME="s2_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="147" NAME="s2_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="148" NAME="s2_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="149" NAME="s3_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="150" NAME="s3_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="s3_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="s3_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="153" MSB="7" NAME="s3_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="154" MSB="2" NAME="s3_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="155" MSB="1" NAME="s3_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="156" NAME="s3_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="157" MSB="3" NAME="s3_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="158" MSB="2" NAME="s3_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="159" MSB="3" NAME="s3_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="160" NAME="s3_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="161" NAME="s3_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="162" MSB="31" NAME="s3_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="163" MSB="3" NAME="s3_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S3_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="164" NAME="s3_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="165" NAME="s3_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="166" NAME="s3_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="167" MSB="3" NAME="s3_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="168" MSB="1" NAME="s3_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="169" NAME="s3_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="170" NAME="s3_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="171" MSB="3" NAME="s3_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="s3_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="173" MSB="7" NAME="s3_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="174" MSB="2" NAME="s3_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="175" MSB="1" NAME="s3_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="176" NAME="s3_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="177" MSB="3" NAME="s3_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="178" MSB="2" NAME="s3_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="179" MSB="3" NAME="s3_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="180" NAME="s3_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="181" NAME="s3_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="182" MSB="3" NAME="s3_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="s3_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="184" MSB="1" NAME="s3_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="185" NAME="s3_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="186" NAME="s3_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="187" NAME="s3_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="188" NAME="s4_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="189" NAME="s4_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="190" MSB="3" NAME="s4_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="s4_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="192" MSB="7" NAME="s4_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="193" MSB="2" NAME="s4_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="194" MSB="1" NAME="s4_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="195" NAME="s4_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="196" MSB="3" NAME="s4_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="197" MSB="2" NAME="s4_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="198" MSB="3" NAME="s4_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="199" NAME="s4_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="200" NAME="s4_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="s4_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="202" MSB="3" NAME="s4_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S4_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="203" NAME="s4_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="204" NAME="s4_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="205" NAME="s4_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="206" MSB="3" NAME="s4_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="207" MSB="1" NAME="s4_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="208" NAME="s4_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="209" NAME="s4_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="s4_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="211" MSB="31" NAME="s4_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="212" MSB="7" NAME="s4_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="213" MSB="2" NAME="s4_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="214" MSB="1" NAME="s4_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="215" NAME="s4_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="216" MSB="3" NAME="s4_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="217" MSB="2" NAME="s4_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="218" MSB="3" NAME="s4_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="219" NAME="s4_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="220" NAME="s4_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="221" MSB="3" NAME="s4_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="222" MSB="31" NAME="s4_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="s4_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="224" NAME="s4_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="225" NAME="s4_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="226" NAME="s4_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="227" NAME="s5_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="228" NAME="s5_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="229" MSB="3" NAME="s5_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="230" MSB="31" NAME="s5_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="231" MSB="7" NAME="s5_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="232" MSB="2" NAME="s5_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="233" MSB="1" NAME="s5_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="234" NAME="s5_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="s5_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="236" MSB="2" NAME="s5_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="237" MSB="3" NAME="s5_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="238" NAME="s5_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="239" NAME="s5_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="s5_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="241" MSB="3" NAME="s5_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S5_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="242" NAME="s5_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="243" NAME="s5_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="244" NAME="s5_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="245" MSB="3" NAME="s5_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="246" MSB="1" NAME="s5_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="247" NAME="s5_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="248" NAME="s5_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="249" MSB="3" NAME="s5_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="250" MSB="31" NAME="s5_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="251" MSB="7" NAME="s5_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="252" MSB="2" NAME="s5_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="253" MSB="1" NAME="s5_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="s5_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="255" MSB="3" NAME="s5_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="256" MSB="2" NAME="s5_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="257" MSB="3" NAME="s5_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="s5_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="259" NAME="s5_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="260" MSB="3" NAME="s5_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="261" MSB="31" NAME="s5_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="262" MSB="1" NAME="s5_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="s5_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="s5_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="265" NAME="s5_axi_rready" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S0_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_rready"/>
- </PORTMAPS>
- <MASTERS>
- <MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
- <MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
- </MASTERS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S1_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="2" NAME="S2_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S3_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="4" NAME="S4_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="5" NAME="S5_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/>
- <PORTMAP DIR="IO" PHYSICAL="rzq"/>
- <PORTMAP DIR="IO" PHYSICAL="zio"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M">
- <SLAVES>
- <SLAVE BUSINTERFACE="S0_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S1_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S1_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S1_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S2_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S2_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S2_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S3_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S3_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S3_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S4_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S4_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S4_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S5_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S5_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S5_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
- <DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE">
- <DESCRIPTION>AXI protocol selection </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40e00000">
- <DESCRIPTION>Ethernetlite Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x40e0ffff">
- <DESCRIPTION>Ethernetlite High Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_S_AXI_ACLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000">
- <DESCRIPTION>AXI System Clock Period </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Interface Addresses Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Interface Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="7" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Width of ID Bus on AXI4 </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_INCLUDE_MDIO" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Include MII Management Module</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_INCLUDE_GLOBAL_BUFFERS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Include Global Buffers for PHY clocks</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_INCLUDE_INTERNAL_LOOPBACK" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Include Internal Loopback</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_DUPLEX" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Duplex Mode </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="12" NAME="C_TX_PING_PONG" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Include Second Transmitter Buffer </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="13" NAME="C_RX_PING_PONG" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Include Second Receiver Buffer </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_INCLUDE_PHY_CONSTRAINTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Include PHY I/O Constraints </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Interconnect write acceptance </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_INTERCONNECT_S_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Interconnect read acceptance </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="17" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Support Narrow Burst on AXI4 </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="IO" IOS="ethernet_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="48" NAME="PHY_MDIO" SIGNAME="Ethernet_Lite_MDIO" TRI_I="PHY_MDIO_I" TRI_O="PHY_MDIO_O" TRI_T="PHY_MDIO_T">
- <DESCRIPTION>Ethernet PHY Management Data</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="44" NAME="PHY_MDC" SIGNAME="Ethernet_Lite_MDC">
- <DESCRIPTION>Ethernet PHY Management Clock</DESCRIPTION>
- </PORT>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="43" MSB="3" NAME="PHY_tx_data" RIGHT="0" SIGNAME="Ethernet_Lite_TXD" VECFORMULA="[3:0]">
- <DESCRIPTION>Ethernet Transmit Data Output</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="42" NAME="PHY_tx_en" SIGNAME="Ethernet_Lite_TX_EN">
- <DESCRIPTION>Ethernet Transmit Enable</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="34" NAME="PHY_tx_clk" SIGNAME="Ethernet_Lite_TX_CLK">
- <DESCRIPTION>Ethernet Transmit Clock Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="39" NAME="PHY_col" SIGNAME="Ethernet_Lite_COL">
- <DESCRIPTION>Ethernet Collision Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="6" MPD_INDEX="38" MSB="3" NAME="PHY_rx_data" RIGHT="0" SIGNAME="Ethernet_Lite_RXD" VECFORMULA="[3:0]">
- <DESCRIPTION>Ethernet Receive Data Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="40" NAME="PHY_rx_er" SIGNAME="Ethernet_Lite_RX_ER">
- <DESCRIPTION>Ethernet Receive Error Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="35" NAME="PHY_rx_clk" SIGNAME="Ethernet_Lite_RX_CLK">
- <DESCRIPTION>Ethernet Receive Clock Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="36" NAME="PHY_crs" SIGNAME="Ethernet_Lite_CRS">
- <DESCRIPTION>Ethernet Carrier Sense Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="37" NAME="PHY_dv" SIGNAME="Ethernet_Lite_RX_DV">
- <DESCRIPTION>Ethernet Receive Data Valid</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="41" NAME="PHY_rst_n" SIGNAME="Ethernet_Lite_PHY_RST_N">
- <DESCRIPTION>Ethernet PHY Reset</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="2" NAME="IP2INTC_Irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="5" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="6" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="10" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="11" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="I" MPD_INDEX="13" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_M_WLAST"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BID" DIR="O" MPD_INDEX="16" NAME="S_AXI_BID" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="26" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="27" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RID" DIR="O" MPD_INDEX="28" NAME="S_AXI_RID" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="O" MPD_INDEX="31" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_M_RLAST"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="32" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="33" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="I" IOS="ethernet_0" MPD_INDEX="45" NAME="PHY_MDIO_I" SIGNAME="__NOC__"/>
- <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="46" NAME="PHY_MDIO_O" SIGNAME="__NOC__"/>
- <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="47" NAME="PHY_MDIO_T" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="ethernet_0" TYPE="XIL_AXIETHERNET_V1">
- <PORTMAPS>
- <PORTMAP DIR="IO" PHYSICAL="PHY_MDIO"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDC"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_tx_data"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_tx_en"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_tx_clk"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_col"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_data"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_er"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_clk"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_crs"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_dv"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_rst_n"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_MDIO_I"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_O"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_T"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
- <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
- <DESCRIPTION>Count Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Only One Timer is present</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>GEN0 Active Level</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>GEN1 Active Level</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41c00000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x41c0ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_Interrupt"/>
- <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
- <DESCRIPTION>Capture Trig 0</DESCRIPTION>
- </PORT>
- <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
- <DESCRIPTION>Capture Trig 1</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
- <DESCRIPTION>Generate Out 0</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
- <DESCRIPTION>Generate Out 1</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
- <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
- </PORT>
- <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
- <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="4">
- <DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111110111">
- <DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
- <DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
- <DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Support IPR </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Support SIE </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Support CIE </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Support IVR </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>IRQ Output Use Level </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>The Sense of IRQ Output </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="20" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt">
- <DESCRIPTION>Interrupt Request Output</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="3" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
- <SIGNALS>
- <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <SIGNAL NAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <SIGNAL NAME="axi_timer_0_Interrupt"/>
- <SIGNAL NAME="RS232_Uart_1_Interrupt"/>
- </SIGNALS>
- <DESCRIPTION>Interrupt Inputs</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
- <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="0" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="1" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <SOURCE INSTANCE="axi_timer_0" PRIORITY="2" SIGNAME="axi_timer_0_Interrupt"/>
- <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="3" SIGNAME="RS232_Uart_1_Interrupt"/>
- <TARGET INSTANCE="microblaze_0"/>
- </INTERRUPTINFO>
- </MODULE>
- </MODULES>
-
-</EDKSYSTEM>
\ No newline at end of file
+++ /dev/null
-// BMM LOC annotation file.\r
-//\r
-// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010\r
-// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.\r
-\r
-\r
-///////////////////////////////////////////////////////////////////////////////\r
-//\r
-// Processor 'microblaze_0', ID 100, memory map.\r
-//\r
-///////////////////////////////////////////////////////////////////////////////\r
-\r
-ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100\r
-\r
-\r
- ///////////////////////////////////////////////////////////////////////////////\r
- //\r
- // Processor 'microblaze_0' address space 'microblaze_0_bram_block_combined' 0x00000000:0x00001FFF (8 KBytes).\r
- //\r
- ///////////////////////////////////////////////////////////////////////////////\r
-\r
- ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF]\r
- BUS_BLOCK\r
- microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X1Y30;\r
- microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X1Y32;\r
- microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X0Y30;\r
- microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X0Y32;\r
- END_BUS_BLOCK;\r
- END_ADDRESS_SPACE;\r
-\r
-END_ADDRESS_MAP;\r
-\r
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-
-<!--
-<xsl:output method="xml"
- version="1.0"
- encoding="UTF-8" indent="yes"
- doctype-public="-//W3C//DTD SVG Tiny 1.1//EN"
- doctype-system="http://www.w3.org/Graphics/SVG/1.1/DTD/svg11-tiny.dtd"/>
--->
-
-<!--
- ======================================================
- BUS INTERFACE DIMENSIONS
- ======================================================
--->
-
-<xsl:variable name="BLKD_BIF_H" select="16"/>
-<xsl:variable name="BLKD_BIF_W" select="32"/>
-
-<xsl:variable name="BLKD_BIFC_H" select="24"/>
-<xsl:variable name="BLKD_BIFC_W" select="24"/>
-
-<xsl:variable name="BLKD_BIFC_dx" select="ceiling($BLKD_BIFC_W div 5)"/>
-<xsl:variable name="BLKD_BIFC_dy" select="ceiling($BLKD_BIFC_H div 5)"/>
-<xsl:variable name="BLKD_BIFC_Hi" select="($BLKD_BIFC_H - ($BLKD_BIFC_dy * 2))"/>
-<xsl:variable name="BLKD_BIFC_Wi" select="($BLKD_BIFC_W - ($BLKD_BIFC_dx * 2))"/>
-
-<xsl:variable name="BLKD_BIF_TYPE_ONEWAY" select="'OneWay'"/>
-
-<!--
- ======================================================
- GLOLBAL BUS INTERFACE DIMENSIONS
- (Define for global MdtSVG_BifShapes.xsl which is used across all
- diagrams to define the shapes of bifs the same across all diagrams)
- ======================================================
--->
-
-<xsl:variable name="BIF_H" select="$BLKD_BIF_H"/>
-<xsl:variable name="BIF_W" select="$BLKD_BIF_W"/>
-
-<xsl:variable name="BIFC_H" select="$BLKD_BIFC_H"/>
-<xsl:variable name="BIFC_W" select="$BLKD_BIFC_W"/>
-
-<xsl:variable name="BIFC_dx" select="$BLKD_BIFC_dx"/>
-<xsl:variable name="BIFC_dy" select="$BLKD_BIFC_dy"/>
-
-<xsl:variable name="BIFC_Hi" select="$BLKD_BIFC_Hi"/>
-<xsl:variable name="BIFC_Wi" select="$BLKD_BIFC_Wi"/>
-
-
-<!--
- ======================================================
- BUS DIMENSIONS
- ======================================================
--->
-
-<xsl:variable name="BLKD_P2P_BUS_W" select="($BLKD_BUS_ARROW_H - ($BLKD_BUS_ARROW_G * 2))"/>
-<xsl:variable name="BLKD_SBS_LANE_H" select="($BLKD_MOD_H + ($BLKD_BIF_H * 2))"/>
-<xsl:variable name="BLKD_BUS_LANE_W" select="($BLKD_BIF_W + ($BLKD_MOD_BIF_GAP_H * 2))"/>
-<xsl:variable name="BLKD_BUS_ARROW_W" select="ceiling($BLKD_BIFC_W div 3)"/>
-<xsl:variable name="BLKD_BUS_ARROW_H" select="ceiling($BLKD_BIFC_H div 2)"/>
-<xsl:variable name="BLKD_BUS_ARROW_G" select="ceiling($BLKD_BIFC_W div 12)"/>
-
-
-<!--
- ======================================================
- IO PORT DIMENSIONS
- ======================================================
--->
-
-<xsl:variable name="BLKD_IOP_H" select="16"/>
-<xsl:variable name="BLKD_IOP_W" select="16"/>
-<xsl:variable name="BLKD_IOP_SPC" select="12"/>
-
-
-<!--
- ======================================================
- INTERRUPT NOTATION DIMENSIONS
- ======================================================
--->
-
-<xsl:variable name="BLKD_INTR_W" select="18"/>
-<xsl:variable name="BLKD_INTR_H" select="18"/>
-
-<!--
- ======================================================
- MODULE DIMENSIONS
- ======================================================
--->
-
-<xsl:variable name="BLKD_MOD_IO_GAP" select="8"/>
-
-<xsl:variable name="BLKD_MOD_W" select="( ($BLKD_BIF_W * 2) + ($BLKD_MOD_BIF_GAP_H * 1) + ($BLKD_MOD_LANE_W * 2))"/>
-<xsl:variable name="BLKD_MOD_H" select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * 1) + ($BLKD_MOD_BIF_GAP_V * 1) + ($BLKD_MOD_LANE_H * 2))"/>
-
-<xsl:variable name="BLKD_MOD_BIF_GAP_H" select="ceiling($BLKD_BIF_H div 4)"/>
-<xsl:variable name="BLKD_MOD_BIF_GAP_V" select="ceiling($BLKD_BIFC_H div 2)"/>
-
-<xsl:variable name="BLKD_MOD_LABEL_W" select="(($BLKD_BIF_W * 2) + $BLKD_MOD_BIF_GAP_H)"/>
-<xsl:variable name="BLKD_MOD_LABEL_H" select="(($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 3))"/>
-
-<xsl:variable name="BLKD_MOD_LANE_W" select="ceiling($BLKD_BIF_W div 3)"/>
-<xsl:variable name="BLKD_MOD_LANE_H" select="ceiling($BLKD_BIF_H div 4)"/>
-
-<xsl:variable name="BLKD_MOD_EDGE_W" select="ceiling($BLKD_MOD_LANE_W div 2)"/>
-<xsl:variable name="BLKD_MOD_SHAPES_G" select="($BLKD_BIF_W + $BLKD_BIF_W)"/>
-
-<xsl:variable name="BLKD_MOD_BKTLANE_H" select="$BLKD_BIF_H"/>
-<xsl:variable name="BLKD_MOD_BKTLANE_W" select="$BLKD_BIF_H"/>
-
-<xsl:variable name="BLKD_MOD_BUCKET_G" select="ceiling($BLKD_BIF_W div 2)"/>
-
-<xsl:variable name="BLKD_MPMC_MOD_H" select="(($BLKD_BIF_H * 1) + ($BLKD_MOD_BIF_GAP_V * 2) + ($BLKD_MOD_LANE_H * 2))"/>
-
-
-<!--
- ======================================================
- GLOBAL DIAGRAM DIMENSIONS
- ======================================================
--->
-
-<xsl:variable name="BLKD_IORCHAN_H" select="$BLKD_BIF_H"/>
-<xsl:variable name="BLKD_IORCHAN_W" select="$BLKD_BIF_H"/>
-
-<xsl:variable name="BLKD_PRTCHAN_H" select="($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 2)"/>
-<xsl:variable name="BLKD_PRTCHAN_W" select="($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 2) + 8"/>
-
-<xsl:variable name="BLKD_DRAWAREA_MIN_W" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * 3) + ($BLKD_MOD_BUCKET_G * 2)))"/>
-
-<xsl:variable name="BLKD_INNER_X" select="($BLKD_PRTCHAN_W + $BLKD_IORCHAN_W + $BLKD_INNER_GAP)"/>
-<xsl:variable name="BLKD_INNER_Y" select="($BLKD_PRTCHAN_H + $BLKD_IORCHAN_H + $BLKD_INNER_GAP)"/>
-<xsl:variable name="BLKD_INNER_GAP" select="ceiling($BLKD_MOD_W div 2)"/>
-
-<xsl:variable name="BLKD_SBS2IP_GAP" select="$BLKD_MOD_H"/>
-<xsl:variable name="BLKD_BRIDGE_GAP" select="($BLKD_BUS_LANE_W * 4)"/>
-<xsl:variable name="BLKD_IP2UNK_GAP" select="$BLKD_MOD_H"/>
-<xsl:variable name="BLKD_PROC2SBS_GAP" select="($BLKD_BIF_H * 2)"/>
-<xsl:variable name="BLKD_IOR2PROC_GAP" select="$BLKD_BIF_W"/>
-<xsl:variable name="BLKD_MPMC2PROC_GAP" select="($BLKD_BIF_H * 2)"/>
-<xsl:variable name="BLKD_SPECS2KEY_GAP" select="$BLKD_BIF_W"/>
-<xsl:variable name="BLKD_DRAWAREA2KEY_GAP" select="ceiling($BLKD_BIF_W div 3)"/>
-
-<xsl:variable name="BLKD_KEY_H" select="250"/>
-<xsl:variable name="BLKD_KEY_W" select="($BLKD_DRAWAREA_MIN_W + ceiling($BLKD_DRAWAREA_MIN_W div 2.5))"/>
-
-
-<xsl:variable name="BLKD_SPECS_H" select="100"/>
-<xsl:variable name="BLKD_SPECS_W" select="300"/>
-
-
-
-<xsl:variable name="BLKD_BKT_MODS_PER_ROW" select="3"/>
-
-<!--
-<xsl:template name="Print_Dimensions">
- <xsl:message>MOD_LABEL_W : <xsl:value-of select="$MOD_LABEL_W"/></xsl:message>
- <xsl:message>MOD_LABEL_H : <xsl:value-of select="$MOD_LABEL_H"/></xsl:message>
-
- <xsl:message>MOD_LANE_W : <xsl:value-of select="$MOD_LANE_W"/></xsl:message>
- <xsl:message>MOD_LANE_H : <xsl:value-of select="$MOD_LANE_H"/></xsl:message>
-
- <xsl:message>MOD_EDGE_W : <xsl:value-of select="$MOD_EDGE_W"/></xsl:message>
- <xsl:message>MOD_SHAPES_G : <xsl:value-of select="$MOD_SHAPES_G"/></xsl:message>
-
- <xsl:message>MOD_BKTLANE_W : <xsl:value-of select="$MOD_BKTLANE_W"/></xsl:message>
- <xsl:message>MOD_BKTLANE_H : <xsl:value-of select="$MOD_BKTLANE_H"/></xsl:message>
- <xsl:message>MOD_BUCKET_G : <xsl:value-of select="$MOD_BUCKET_G"/></xsl:message>
-
-</xsl:template>
--->
-
-</xsl:stylesheet>
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<!-- Generic colors, shared between modules like webpages diagrams and pdfs -->
-
-<xsl:variable name="COL_XLNX" select="'#AA0017'"/>
-
-<xsl:variable name="COL_BLACK" select="'#000000'"/>
-<xsl:variable name="COL_WHITE" select="'#FFFFFF'"/>
-
-<xsl:variable name="COL_GRAY" select="'#CECECE'"/>
-<xsl:variable name="COL_GRAY_LT" select="'#E1E1E1'"/>
-<xsl:variable name="COL_GRAY_DK" select="'#B1B1B1'"/>
-
-<xsl:variable name="COL_YELLOW" select="'#FFFFDD'"/>
-<xsl:variable name="COL_YELLOW_LT" select="'#FFFFEE'"/>
-
-<xsl:variable name="COL_RED" select="'#AA0000'"/>
-
-<xsl:variable name="COL_GREEN" select="'#33CC33'"/>
-
-<xsl:variable name="COL_BLUE_LT" select="'#AAAAFF'"/>
-
-<!-- Colors specific to the Diagrams -->
-<xsl:variable name="COL_BG" select="'#CCCCCC'"/>
-<xsl:variable name="COL_BG_LT" select="'#EEEEEE'"/>
-<xsl:variable name="COL_BG_UNK" select="'#DDDDDD'"/>
-
-<xsl:variable name="COL_PROC_BG" select="'#FFCCCC'"/>
-<xsl:variable name="COL_PROC_BG_MB" select="'#222222'"/>
-<xsl:variable name="COL_PROC_BG_PP" select="'#90001C'"/>
-<xsl:variable name="COL_PROC_BG_USR" select="'#666699'"/>
-
-<xsl:variable name="COL_MPMC_BG" select="'#8B0800'"/>
-
-<xsl:variable name="COL_MOD_BG" select="'#F0F0F0'"/>
-<xsl:variable name="COL_MOD_SPRT" select="'#888888'"/>
-<xsl:variable name="COL_MOD_MPRT" select="'#888888'"/>
-
-<xsl:variable name="COL_IORING" select="'#000088'"/>
-<xsl:variable name="COL_IORING_LT" select="'#CCCCFF'"/>
-<xsl:variable name="COL_SYSPRT" select="'#0000BB'"/>
-
-<xsl:variable name="COL_INTCS">
- <INTCCOLOR INDEX="0" RGB="#FF9900"/>
- <INTCCOLOR INDEX="1" RGB="#00CCCC"/>
- <INTCCOLOR INDEX="2" RGB="#33FF33"/>
- <INTCCOLOR INDEX="3" RGB="#FF00CC"/>
- <INTCCOLOR INDEX="4" RGB="#99FF33"/>
- <INTCCOLOR INDEX="5" RGB="#0066CC"/>
- <INTCCOLOR INDEX="6" RGB="#9933FF"/>
- <INTCCOLOR INDEX="7" RGB="#3300FF"/>
- <INTCCOLOR INDEX="8" RGB="#00FF33"/>
- <INTCCOLOR INDEX="9" RGB="#FF3333"/>
-</xsl:variable>
-
-<xsl:variable name="COL_BUSSTDS">
- <BUSCOLOR BUSSTD="AXI" RGB="#0084AB" RGB_LT="#D0E6EF" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="XIL" RGB="#990066" RGB_LT="#CC3399" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="OCM" RGB="#0000DD" RGB_LT="#9999DD" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="OPB" RGB="#339900" RGB_LT="#CCDDCC" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
-
- <BUSCOLOR BUSSTD="LMB" RGB="#7777FF" RGB_LT="#DDDDFF" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="FSL" RGB="#CC00CC" RGB_LT="#FFBBFF" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="DCR" RGB="#6699FF" RGB_LT="#BBDDFF" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="FCB" RGB="#8C00FF" RGB_LT="#CCCCFF" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
-
- <BUSCOLOR BUSSTD="PLB" RGB="#FF5500" RGB_LT="#FFBB00" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="PLBV34" RGB="#FF5500" RGB_LT="#FFBB00" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="PLBV46" RGB="#BB9955" RGB_LT="#FFFFDD" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="PLBV46_P2P" RGB="#BB9955" RGB_LT="#FFFFDD" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
-
- <BUSCOLOR BUSSTD="USER" RGB="#009999" RGB_LT="#00CCCC" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="KEY" RGB="#444444" RGB_LT="#888888" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
- <BUSCOLOR BUSSTD="GRAYSCALE" RGB="#444444" RGB_LT="#888888" RGB_DK="#85C3D9" RGB_TXT="#FFFFFF"/>
-</xsl:variable>
-<xsl:variable name = "COL_BUSSTDS_NUMOF" select="count(exsl:node-set($COL_BUSSTDS)/BUSCOLOR)"/>
-
-<xsl:template name="F_BusStd2RGB">
- <xsl:param name="iBusStd" select="'USER'"/>
-
- <xsl:choose>
- <xsl:when test="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB">
- <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = 'USER')]/@RGB"/>
- </xsl:otherwise>
- </xsl:choose>
-</xsl:template>
-
-<xsl:template name="F_BusStd2RGB_LT">
- <xsl:param name="iBusStd" select="'USER'"/>
-
- <xsl:choose>
- <xsl:when test="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_LT">
- <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_LT"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = 'USER')]/@RGB_LT"/>
- </xsl:otherwise>
- </xsl:choose>
-</xsl:template>
-
-<xsl:template name="F_BusStd2RGB_DK">
- <xsl:param name="iBusStd" select="'USER'"/>
- <xsl:choose>
- <xsl:when test="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_DK">
- <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_DK"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = 'USER')]/@RGB_DK"/>
- </xsl:otherwise>
- </xsl:choose>
-</xsl:template>
-
-<xsl:template name="F_BusStd2RGB_TXT">
- <xsl:param name="iBusStd" select="'USER'"/>
- <xsl:choose>
- <xsl:when test="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_TXT">
- <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_TXT"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = 'USER')]/@RGB_TXT"/>
- </xsl:otherwise>
- </xsl:choose>
-</xsl:template>
-
-<xsl:template name="F_IntcIdx2RGB">
- <xsl:param name="iIntcIdx" select="'0'"/>
-
- <xsl:variable name="index_" select="$iIntcIdx mod 9"/>
-
- <xsl:choose>
- <xsl:when test="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = $index_)]/@RGB">
- <xsl:value-of select="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = $index_)]/@RGB"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = '0')]/@RGB"/>
- </xsl:otherwise>
- </xsl:choose>
-</xsl:template>
-
-</xsl:stylesheet>
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-<!DOCTYPE stylesheet [
- <!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
- <!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
-
- <!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
- <!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
-
- <!ENTITY ALPHALOWER "ABCDEFxX0123456789">
- <!ENTITY HEXUPPER "ABCDEFxX0123456789">
- <!ENTITY HEXLOWER "abcdefxX0123456789">
- <!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
-
- <!ENTITY ALLMODS "MODULE[(@INSTANCE)]">
- <!ENTITY BUSMODS "MODULE[(@MODCLASS ='BUS')]">
- <!ENTITY CPUMODS "MODULE[(@MODCLASS ='PROCESSOR')]">
-
- <!ENTITY MODIOFS "MODULE/IOINTERFACES/IOINTERFACE">
- <!ENTITY ALLIOFS "&MODIOFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
-
- <!ENTITY V11MODBIFS "MODULE/BUSINTERFACE">
- <!ENTITY V12MODBIFS "MODULE/BUSINTERFACES/BUSINTERFACE">
- <!ENTITY V11ALLBIFS "&V11MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and @TYPE and @BUSSTD]">
- <!ENTITY V12ALLBIFS "&V12MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and @TYPE and @BUSSTD]">
-
- <!ENTITY V11MODPORTS "MODULE/PORT">
- <!ENTITY V12MODPORTS "MODULE/PORTS/PORT">
- <!ENTITY V11ALLPORTS "&V11MODPORTS;[ (not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <!ENTITY V12ALLPORTS "&V12MODPORTS;[ (not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <!ENTITY V11NDFPORTS "&V11MODPORTS;[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (not(@BUS) and not(@IOS)))]">
- <!ENTITY V12NDFPORTS "&V12MODPORTS;[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (not(@BUS) and not(@IOS)))]">
- <!ENTITY V11DEFPORTS "&V11MODPORTS;[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@BUS) or (@IOS)))]">
- <!ENTITY V12DEFPORTS "&V12MODPORTS;[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@BUS) or (@IOS)))]">
-]>
-
-<!--
- <!ENTITY MSTBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'MASTER')]">
- <!ENTITY SLVBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'SLAVE')]">
- <!ENTITY MOSBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@TYPE = 'MASTER') or (@TYPE = 'SLAVE'))]">
- <!ENTITY P2PBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR'))]">
--->
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math exsl dyn xlink">
-<!--
- ======================================================
- EDK SYSTEM (EDWARD) Globals.
- ======================================================
--->
-
-<xsl:variable name="G_SYS_ROOT" select="/"/>
-<!--
-<xsl:variable name="G_SYS_DOC" select="dyn:evaluate($G_SYS_ROOT)"/>
-<xsl:variable name="G_SYS_DOC" select="dyn:evaluate($G_SYS_ROOT)"/>
- -->
-<xsl:variable name="G_SYS" select="$G_SYS_ROOT/EDKSYSTEM"/>
-<xsl:variable name="G_SYS_TIMESTAMP" select="$G_SYS/@TIMESTAMP"/>
-<xsl:variable name="G_SYS_EDKVERSION" select="$G_SYS/@EDKVERSION"/>
-
-<xsl:variable name="G_SYS_INFO" select="$G_SYS/SYSTEMINFO"/>
-<xsl:variable name="G_SYS_INFO_PKG" select="$G_SYS_INFO/@PACKAGE"/>
-<xsl:variable name="G_SYS_INFO_DEV" select="$G_SYS_INFO/@DEVICE"/>
-<xsl:variable name="G_SYS_INFO_ARCH" select="$G_SYS_INFO/@ARCH"/>
-<xsl:variable name="G_SYS_INFO_SPEED" select="$G_SYS_INFO/@SPEEDGRADE"/>
-
-<xsl:variable name="G_SYS_MODS" select="$G_SYS/MODULES"/>
-<xsl:variable name="G_SYS_EXPS" select="$G_SYS/EXTERNALPORTS"/>
-
-<!-- INDEX KEYS FOR FAST ACCESS -->
-<xsl:key name="G_MAP_MODULES" match="&ALLMODS;" use="@INSTANCE"/>
-<xsl:key name="G_MAP_PROCESSORS" match="&CPUMODS;" use="@INSTANCE"/>
-
-<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@INSTANCE"/>
-<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@BUSSTD"/>
-<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@BUSSTD_PSF"/>
-
-<xsl:key name="G_MAP_ALL_IOFS" match="&ALLIOFS;" use="../../@INSTANCE"/>
-
-<xsl:key name="G_MAP_ALL_BIFS" match="&V11ALLBIFS;" use="@TYPE"/>
-<xsl:key name="G_MAP_ALL_BIFS" match="&V12ALLBIFS;" use="@TYPE"/>
-<xsl:key name="G_MAP_ALL_BIFS" match="&V11ALLBIFS;" use="@BUSSTD"/>
-<xsl:key name="G_MAP_ALL_BIFS" match="&V12ALLBIFS;" use="@BUSSTD"/>
-<xsl:key name="G_MAP_ALL_BIFS" match="&V11ALLBIFS;" use="@BUSSTD_PSF"/>
-<xsl:key name="G_MAP_ALL_BIFS" match="&V12ALLBIFS;" use="@BUSSTD_PSF"/>
-<xsl:key name="G_MAP_ALL_BIFS" match="&V11ALLBIFS;" use="../@INSTANCE"/>
-<xsl:key name="G_MAP_ALL_BIFS" match="&V12ALLBIFS;" use="../../@INSTANCE"/>
-
-<!--
-<xsl:key name="G_MAP_ALL_BIFS_BY_BUS" match="&ALLBIFS;" use="@BUSNAME"/>
-<xsl:key name="G_MAP_ALL_BIFS_BY_STD" match="&ALLBIFS;" use="@BUSSTD"/>
-<xsl:key name="G_MAP_ALL_BIFS_BY_STD" match="&ALLBIFS;" use="@BUSSTD_PSF"/>
-
-
-<xsl:key name="G_MAP_MST_BIFS" match="&MSTBIFS;" use="@BUSNAME"/>
-<xsl:key name="G_MAP_SLV_BIFS" match="&SLVBIFS;" use="@BUSNAME"/>
-<xsl:key name="G_MAP_MOS_BIFS" match="&MOSBIFS;" use="@BUSNAME"/>
-
-<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSNAME"/>
-<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSSTD"/>
-<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSSTD_PSF"/>
--->
-
-<xsl:key name="G_MAP_ALL_PORTS" match="&V11ALLPORTS;" use="../@INSTANCE"/>
-<xsl:key name="G_MAP_ALL_PORTS" match="&V12ALLPORTS;" use="../../@INSTANCE"/>
-<xsl:key name="G_MAP_DEF_PORTS" match="&V11DEFPORTS;" use="../@INSTANCE"/> <!-- Default ports -->
-<xsl:key name="G_MAP_DEF_PORTS" match="&V12DEFPORTS;" use="../../@INSTANCE"/> <!-- Default ports -->
-<xsl:key name="G_MAP_NDF_PORTS" match="&V11NDFPORTS;" use="../@INSTANCE"/> <!-- Non Default ports -->
-<xsl:key name="G_MAP_NDF_PORTS" match="&V12NDFPORTS;" use="../../@INSTANCE"/> <!-- Non Default ports -->
-
-<xsl:variable name="G_BIFTYPES">
-
- <BIFTYPE TYPE="SLAVE"/>
- <BIFTYPE TYPE="MASTER"/>
- <BIFTYPE TYPE="MASTER_SLAVE"/>
-
- <BIFTYPE TYPE="TARGET"/>
- <BIFTYPE TYPE="INITIATOR"/>
-
- <BIFTYPE TYPE="MONITOR"/>
-
- <BIFTYPE TYPE="USER"/>
- <BIFTYPE TYPE="TRANSPARENT"/>
-
-</xsl:variable>
-<xsl:variable name="G_BIFTYPES_NUMOF" select="count(exsl:node-set($G_BIFTYPES)/BIFTYPE)"/>
-
-<xsl:variable name="G_IFTYPES">
- <IFTYPE TYPE="SLAVE"/>
- <IFTYPE TYPE="MASTER"/>
- <IFTYPE TYPE="MASTER_SLAVE"/>
-
- <IFTYPE TYPE="TARGET"/>
- <IFTYPE TYPE="INITIATOR"/>
-
- <IFTYPE TYPE="MONITOR"/>
-
- <IFTYPE TYPE="USER"/>
-<!--
- <IFTYPE TYPE="TRANSPARENT"/>
--->
-</xsl:variable>
-<xsl:variable name="G_IFTYPES_NUMOF" select="count(exsl:node-set($G_IFTYPES)/IFTYPE)"/>
-
-<xsl:variable name="G_BUSSTDS">
-
- <BUSSTD NAME="AXI"/>
- <BUSSTD NAME="XIL"/>
- <BUSSTD NAME="OCM"/>
- <BUSSTD NAME="OPB"/>
- <BUSSTD NAME="LMB"/>
- <BUSSTD NAME="FSL"/>
- <BUSSTD NAME="DCR"/>
- <BUSSTD NAME="FCB"/>
- <BUSSTD NAME="PLB"/>
- <BUSSTD NAME="PLB34"/>
- <BUSSTD NAME="PLBV46"/>
- <BUSSTD NAME="PLBV46_P2P"/>
-
- <BUSSTD NAME="USER"/>
- <BUSSTD NAME="KEY"/>
-</xsl:variable>
-<xsl:variable name="G_BUSSTDS_NUMOF" select="count(exsl:node-set($G_BUSSTDS)/BUSSTD)"/>
-
-</xsl:stylesheet>
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<!--
-<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
- doctype-public="-//W3C//DTD SVG 1.0//EN"
- doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
--->
-
-<!--
- ======================================================
- Function to put TEXT CSS and other Internal
- Styling properties directly into the output
- svg. The Qt 4.3 Renderer
- cannot handle separate CSS StyleSheets
- ======================================================
--->
-<xsl:template name="F_WriteText">
-
- <xsl:param name="iClass" select="'_UNKNOWN_'"/>
- <xsl:param name="iText" select="' '"/>
- <xsl:param name="iX" select="'0'"/>
- <xsl:param name="iY" select="'0'"/>
-
-<!--
- <xsl:message>TEXT <xsl:value-of select="$iText"/></xsl:message>
- <xsl:message>CLASS <xsl:value-of select="$iClass"/></xsl:message>
--->
-
- <xsl:element name="text">
- <xsl:attribute name="x"><xsl:value-of select="$iX"/></xsl:attribute>
- <xsl:attribute name="y"><xsl:value-of select="$iY"/></xsl:attribute>
-
- <xsl:choose>
-
- <xsl:when test="$iClass = 'sharedbus_label'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'12pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'p2pbus_label'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'p2pbus_label_horiz'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'12pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="writing-mode"><xsl:value-of select="'tb'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
-
- <xsl:when test="$iClass = 'bif_label'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'bc_ipinst'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'bc_iptype'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'iogrp_label'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_IORING"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'mpmc_title'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_WHITE"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'16pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'oblique'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'mpmc_biflabel'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_WHITE"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'intr_symbol'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'bkt_label'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'9pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'ipclass_label'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'9pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'key_header'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'key_title'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'14pt'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'key_label'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'key_label_small'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
-
- <xsl:when test="$iClass = 'key_label_ul'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="text-decoration"><xsl:value-of select="'underline'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
-
- <xsl:when test="$iClass = 'ipd_portlabel'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'ipd_biflabel'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'ipd_iptype'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'ipd_ipname'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'blkd_spec_name'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:when test="$iClass = 'blkd_spec_value_mid'">
- <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
- <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
- <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
- <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
- <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
- <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
- <xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute>
- </xsl:when>
-
- <xsl:otherwise><xsl:message>UNKNOWN Text style class <xsl:value-of select="$iClass"/></xsl:message></xsl:otherwise>
- </xsl:choose>
-
- <xsl:value-of select="$iText"/>
- </xsl:element>
-
-</xsl:template>
-
-</xsl:stylesheet>
-
-<!--
- text.ioplblgrp {
- fill: #000088;
- stroke: none;
- font-size: 10pt;
- font-style: normal;
- font-weight: 900;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
- text.iplabel {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-style: italic;
- font-weight: 800;
- text-anchor: middle;
- font-family: Courier Arial Helvetica sans-serif;
- }
-
- text.iptype {
- fill: #AA0017;
- stroke: none;
- font-size: 8pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.busintlabel {
- fill: #810017;
- stroke: none;
- font-size: 7pt;
- font-style: italic;
- font-weight: 900;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.mpmcbiflabel {
- fill: #FFFFFF;
- stroke: none;
- font-size: 6pt;
- font-style: normal;
- font-weight: 900;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.buslabel {
- fill: #CC3333;
- stroke: none;
- font-size: 8pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
-
-
- text.ipclass {
- fill: #000000;
- stroke: none;
- font-size: 7pt;
- font-style: normal;
- font-weight: bold;
- text-anchor: start;
- font-family: Times Arial Helvetica sans-serif;
- }
-
- text.procclass {
- fill: #000000;
- stroke: none;
- font-size: 7pt;
- font-style: normal;
- font-weight: bold;
- text-anchor: middle;
- font-family: Times Arial Helvetica sans-serif;
- }
-
-
- text.portlabel {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-style: normal;
- font-weight: bold;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.ipdbiflbl {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-style: normal;
- font-weight: bold;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.mmMHeader {
- fill: #FFFFFF;
- stroke: none;
- font-size: 10pt;
- font-style: normal;
- font-weight: bold;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.mmSHeader {
- fill: #810017;
- stroke: none;
- font-size: 10pt;
- font-style: normal;
- font-weight: bold;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
-
-
- text.dbglabel {
- fill: #555555;
- stroke: none;
- font-size: 8pt;
- font-style: normal;
- font-weight: 900;
- text-anchor: middle;
- font-family: Times Arial Helvetica sans-serif;
- }
-
- text.iopnumb {
- fill: #555555;
- stroke: none;
- font-size: 10pt;
- font-style: normal;
- font-weight: 900;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
-
-
- tspan.iopgrp {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-style: normal;
- font-weight: 900;
- text-anchor: middle;
- baseline-shift:super;
- font-family: Arial Courier san-serif;
- }
-
-
- text.biflabel {
- fill: #000000;
- stroke: none;
- font-size: 6pt;
- font-style: normal;
- font-weight: 900;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
-
- }
-
- text.p2pbuslabel {
- fill: #000000;
- stroke: none;
- font-size: 10pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: start;
- writing-mode: tb;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.mpbuslabel {
- fill: #000000;
- stroke: none;
- font-size: 6pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: start;
- writing-mode: tb;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
-
- text.sharedbuslabel {
- fill: #000000;
- stroke: none;
- font-size: 10pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: start;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
-
- text.splitbustxt {
- fill: #000000;
- stroke: none;
- font-size: 6pt;
- font-style: normal;
- font-weight: bold;
- text-anchor: middle;
- font-family: sans-serif;
- }
-
- text.horizp2pbuslabel {
- fill: #000000;
- stroke: none;
- font-size: 6pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: start;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
-
-
- text.keytitle {
- fill: #AA0017;
- stroke: none;
- font-size: 12pt;
- font-weight: bold;
- text-anchor: middle;
- font-family: Arial Helvetica sans-serif;
- }
-
- text.keyheader {
- fill: #000000;
- stroke: none;
- font-size: 10pt;
- font-weight: bold;
- text-anchor: middle;
- font-family: Arial Helvetica sans-serif;
- }
-
- text.keylabel {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: start;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.keylblul {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: start;
- text-decoration: underline;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.specsheader {
- fill: #000000;
- stroke: none;
- font-size: 10pt;
- font-weight: bold;
- text-anchor: start;
- font-family: Arial Helvetica sans-serif;
- }
-
- text.specsvalue {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: start;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.specsvaluemid {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-style: italic;
- font-weight: bold;
- text-anchor: middle;
- font-family: Verdana Arial Helvetica sans-serif;
- }
-
- text.intrsymbol {
- fill: #000000;
- stroke: none;
- font-size: 8pt;
- font-weight: bold;
- text-anchor: start;
- font-family: Arial Helvetica sans-serif;
- }
-
--->
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<!--
-<xsl:output method="xml"
- version="1.0"
- encoding="UTF-8"
- indent="yes"
- doctype-public="-//W3C//DTD SVG 1.0//EN"
- doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
--->
-
-<!--
- ===========================================================
- Handle Bucket connections to the shared busses./
-
- ===========================================================
--->
-
-<xsl:template name="BCLaneSpace_BucketToSharedBus">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
- <xsl:param name="iSpaceSharedBus_Y" select="0"/>
-
-<!--
- <xsl:message>Stack To East <xsl:value-of select="$iStackToEast"/></xsl:message>
- <xsl:message>Stack to West <xsl:value-of select="$iStackToWest"/></xsl:message>
- <xsl:message>Stack to East Width <xsl:value-of select="$iStackToEast_W"/></xsl:message>
- <xsl:message>Stack to West Width <xsl:value-of select="$iStackToWest_W"/></xsl:message>
- <xsl:message>Shared Bus Y <xsl:value-of select="$iSpaceSharedBus_Y"/></xsl:message>
- <xsl:message>Lane in space X <xsl:value-of select="$iLaneInSpace_X"/></xsl:message>
--->
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="sbs_idx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE= $iBusName)]/@BUS_INDEX"/>
- <xsl:variable name="sbs_name_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $sbs_idx_)]/@BUSNAME"/>
-
- <xsl:variable name="sbs_bc_y_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H))"/>
-
- <xsl:variable name="bktshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $sbs_idx_)]/@STACK_HORIZ_INDEX"/>
- <xsl:variable name="bktshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $sbs_idx_)]/@SHAPE_VERTI_INDEX"/>
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
-<!--
- <xsl:message>Ext Shape to West <xsl:value-of select="$extSpaceWest_W_"/></xsl:message>
- <xsl:message>Ext Shape to East <xsl:value-of select="$extSpaceEast_W_"/></xsl:message>
--->
- <xsl:variable name="bktshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$bktshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$bktshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="sbsStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:if test="($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_)">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:if>
-
- <xsl:if test="not($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_)">0</xsl:if>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="vert_line_x_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="vert_line_y1_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="vert_line_y2_" select="($bktshp_Y_ + ceiling($BLKD_MOD_W div 2) + $sbsStack_H_diff_)"/>
- <xsl:variable name="bcInSpace_X_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/>
-
-
-<!--
- <xsl:message>Shared Bus Y <xsl:value-of select="$G_SharedBus_Y"/></xsl:message>
- <xsl:message>Vert Bus Y <xsl:value-of select="$vert_line_y1_"/></xsl:message>
- <xsl:message>vert y1 <xsl:value-of select="$vert_line_y1_"/></xsl:message>
- <xsl:message>vert y2 <xsl:value-of select="$vert_line_y2_"/></xsl:message>
--->
-
- <xsl:variable name="horz_line_y_" select="$vert_line_y2_"/>
- <xsl:variable name="horz_line_x1_" select="$vert_line_x_"/>
- <xsl:variable name="horz_line_x2_" select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_)"/>
-
- <xsl:variable name="v_bus_ul_x_" select="$vert_line_x_"/>
- <xsl:variable name="v_bus_ul_y_" select="$vert_line_y1_"/>
- <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/>
-
- <xsl:variable name="v_bus_height_" select="(($vert_line_y2_ - $vert_line_y1_) - ceiling($BLKD_BIFC_H div 2))"/>
-
- <xsl:variable name="h_bus_ul_x_" select="$v_bus_ul_x_"/>
- <xsl:variable name="h_bus_ul_y_" select="$vert_line_y2_ - $BLKD_BIFC_H + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
- <xsl:variable name="h_bus_width_" select="ceiling($space_W_ div 2) + $extSpaceEast_W_"/>
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
-
-<!--
- <xsl:variable name="h_bus_width_" select="($space_W_ + ceiling(($extSpaceWest_W_ + $extSpaceEast_W_) div 2) - $BLKD_BIFC_W)"/>
- <xsl:message>v bus x <xsl:value-of select="$v_bus_ul_x_"/></xsl:message>
- <xsl:message>v bus y <xsl:value-of select="$v_bus_ul_y_"/></xsl:message>
- <xsl:message>v bus w <xsl:value-of select="$v_bus_width_"/></xsl:message>
- <xsl:message>v bus y1 <xsl:value-of select="$vert_line_y1_"/></xsl:message>
- <xsl:message>v bus y2 <xsl:value-of select="$vert_line_y2_"/></xsl:message>
- <xsl:message>v bus h <xsl:value-of select="$v_bus_height_"/></xsl:message>
- <xsl:message>h bus w <xsl:value-of select="$h_bus_width_"/></xsl:message>
--->
-
-
- <!-- Draw rectangular parts of the bus -->
- <rect x="{$v_bus_ul_x_}"
- y="{$v_bus_ul_y_ - 2}"
- width= "{$v_bus_width_}"
- height="{$v_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-
- <rect x="{$h_bus_ul_x_}"
- y="{$h_bus_ul_y_ - 5}"
- width= "{$h_bus_width_}"
- height="{$h_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-<!--
--->
-
-</xsl:template>
-
-<!--
- ===========================================================
- Handle Processor's Shared bus connections.
- ===========================================================
--->
-
-<xsl:template name="BCLaneSpace_ProcBifToSharedBus">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
- <xsl:param name="iSpaceSharedBus_Y" select="0"/>
-
-<!--
- <xsl:message>Proc Bus Std <xsl:value-of select="$iBusStd"/></xsl:message>
- <xsl:message>Proc Bus Name <xsl:value-of select="$iBusName"/></xsl:message>
- <xsl:message>Proc Bif Type <xsl:value-of select="$iBifType"/></xsl:message>
--->
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="sbs_idx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE= $iBusName)]/@BUS_INDEX"/>
- <xsl:variable name="sbs_bc_y_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H))"/>
- <xsl:variable name="procInst_" select="BUSCONN/@INSTANCE"/>
-
-
-<!--
- <xsl:message>Shared Bus Idx <xsl:value-of select="$sbs_idx_"/></xsl:message>
- <xsl:message>Proc inst <xsl:value-of select="$procInst_"/></xsl:message>
--->
-
- <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * BUSCONN/@BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
- <xsl:variable name="procBifName_" select="BUSCONN/@BUSINTERFACE"/>
- <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInst_)]/BUSINTERFACE[(@NAME = $procBifName_)]/@BIF_X"/>
- <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInst_)]/BUSINTERFACE[(@NAME = $procBifName_)]/@TYPE"/>
-
- <xsl:variable name="procshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInst_)]/@STACK_HORIZ_INDEX"/>
- <xsl:variable name="procshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInst_)]/@SHAPE_VERTI_INDEX"/>
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
-
-<!--
- <xsl:message>Ext Space to West <xsl:value-of select="$extSpaceWest_W_"/></xsl:message>
- <xsl:message>Ext Space to East <xsl:value-of select="$extSpaceEast_W_"/></xsl:message>
-
- <xsl:message>Ext Space to East <xsl:value-of select="$extSpaceEast_W_"/></xsl:message>
- <xsl:message>Stack horiz <xsl:value-of select="$procshp_hori_idx_"/></xsl:message>
- <xsl:message>Stack verti <xsl:value-of select="$procshp_vert_idx_"/></xsl:message>
- <xsl:message>Proc Bif Y <xsl:value-of select="$procBif_Y_"/></xsl:message>
--->
-
- <xsl:variable name="procshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$procshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$procshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <xsl:variable name="procStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($procshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($procshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bc_Y_" select="($procshp_Y_ + $procBif_Y_ + ceiling($BIF_H div 2) + $procStack_H_diff_) - ceiling($BLKD_BIFC_H div 2)"/>
-<!--
- <xsl:variable name="bc_x_" select="($laneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="bc_x_" select="0"/>
- <xsl:message>Test</xsl:message>
--->
-
- <xsl:variable name="bc_X_">
- <xsl:choose>
- <xsl:when test="$procBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
-<!--
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_)"/>
- <xsl:value-of select="($space_W_ - ceiling($BLKD_MOD_W div 2))"/>
- <xsl:value-of select="$space_W_ + $extSpaceEast_W_"/>
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
--->
- </xsl:when>
- <xsl:when test="$procBifSide_ = '1'">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <!-- Place the bus connectijon -->
- <use x="{$bc_X_}" y="{$bc_Y_}" xlink:href="#{$iBusStd}_busconn_{$procBifType_}"/>
-<!--
--->
- <xsl:variable name="vert_line_x_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="vert_line_y1_" select="($procshp_Y_ + $procBif_Y_ + ceiling($BLKD_BIF_H div 2) + $procStack_H_diff_)"/>
- <xsl:variable name="vert_line_y2_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_BIFC_W div 2))"/>
-
-<!--
- <xsl:message>Vert line Y1 <xsl:value-of select="$vert_line_y1_"/></xsl:message>
- <xsl:message>Vert line Y2 <xsl:value-of select="$vert_line_y2_"/></xsl:message>
--->
-
- <xsl:variable name="v_bus_ul_y_">
- <xsl:choose>
- <xsl:when test="$vert_line_y1_ > $vert_line_y2_">
- <xsl:value-of select="$vert_line_y2_"/>
- </xsl:when>
- <xsl:when test="$vert_line_y2_ > $vert_line_y1_">
- <xsl:value-of select="$vert_line_y1_"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="v_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="($vert_line_x_ + $BLKD_MOD_BIF_GAP_H)"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="($vert_line_x_ - $BLKD_MOD_BIF_GAP_H)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="v_bus_height_">
- <xsl:choose>
- <xsl:when test="$vert_line_y1_ > $vert_line_y2_">
- <xsl:value-of select="($vert_line_y1_ - $vert_line_y2_) - $BLKD_P2P_BUS_W"/>
- </xsl:when>
- <xsl:when test="$vert_line_y2_ > $vert_line_y1_">
- <xsl:value-of select="($vert_line_y2_ - $vert_line_y1_) - $BLKD_P2P_BUS_W"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="($bc_X_ + $BLKD_BIFC_W - ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2))"/>
-<!--
- <xsl:value-of select="$v_bus_ul_x_"/>
--->
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="$v_bus_ul_x_"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_y_">
- <xsl:choose>
- <xsl:when test="$vert_line_y1_ > $vert_line_y2_">
- <xsl:value-of select="$vert_line_y2_ - ceiling($BLKD_P2P_BUS_W div 2)"/>
- </xsl:when>
- <xsl:when test="$vert_line_y2_ > $vert_line_y1_">
- <xsl:value-of select="$vert_line_y1_ - ceiling($BLKD_P2P_BUS_W div 2)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="h_bus_width_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="$v_bus_ul_x_ - $h_bus_ul_x_ + $BLKD_P2P_BUS_W"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="($bc_X_ - $v_bus_ul_x_) + ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2) + 1"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:if test="(@ORIENTED = 'WEST')">
- </xsl:if>
-
- <xsl:message>bc_X_ <xsl:value-of select="$bc_X_"/></xsl:message>
- <xsl:message>v_bus_ul_x <xsl:value-of select="$v_bus_ul_x_"/></xsl:message>
- <xsl:message>h_bus_width <xsl:value-of select="$h_bus_width_"/></xsl:message>
- <xsl:message>h_bus_ul_y <xsl:value-of select="$h_bus_ul_y_"/></xsl:message>
--->
-
- <rect x="{$v_bus_ul_x_}"
- y="{$v_bus_ul_y_ + 2}"
- width= "{$v_bus_width_}"
- height="{$v_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-
- <rect x="{$h_bus_ul_x_}"
- y="{$h_bus_ul_y_}"
- width= "{$h_bus_width_}"
- height="{$h_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-</xsl:template>
-
-<!--
- ===========================================================
- Handle non Processor Sharedebus connections.
- ===========================================================
--->
-
-<xsl:template name="BCLaneSpace_NonProcBifToSharedBus">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
- <xsl:param name="iSpaceSharedBus_Y" select="0"/>
-
-
- <xsl:variable name="sbs_idx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE= $iBusName)]/@BUS_INDEX"/>
- <xsl:variable name="sbs_bc_y_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H))"/>
-<!--
- <xsl:variable name="sbs_bc_y_" select="($G_SharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H))"/>
--->
-
- <xsl:variable name="cmplxInst_" select="BUSCONN/@INSTANCE"/>
-
- <xsl:variable name="cmplxBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * BUSCONN/@BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
- <xsl:variable name="cmplxBifName_" select="BUSCONN/@BUSINTERFACE"/>
- <xsl:variable name="cmplxBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $cmplxInst_)]/BUSINTERFACE[(@NAME = $cmplxBifName_)]/@BIF_X"/>
- <xsl:variable name="cmplxBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $cmplxInst_)]/BUSINTERFACE[(@NAME = $cmplxBifName_)]/@TYPE"/>
-
- <xsl:variable name="cmplxshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $cmplxInst_)])]/@STACK_HORIZ_INDEX"/>
- <xsl:variable name="cmplxshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $cmplxInst_)])]/@SHAPE_VERTI_INDEX"/>
-
- <xsl:variable name="is_abvSbs_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $cmplxInst_)]]/@IS_ABVSBS)"/>
- <xsl:variable name="is_blwSbs_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $cmplxInst_)]]/@IS_BLWSBS)"/>
-
-<!--
- <xsl:message>iStackToEast <xsl:value-of select="$iStackToEast"/></xsl:message>
- <xsl:message>iStackToWest <xsl:value-of select="$iStackToWest"/></xsl:message>
- <xsl:message><xsl:value-of select="$cmplxInst_"/> : <xsl:value-of select="$is_blwSbs_"/></xsl:message>
- <xsl:message><xsl:value-of select="$cmplxInst_"/> : <xsl:value-of select="$is_abvSbs_"/></xsl:message>
- <xsl:message><xsl:value-of select="$cmplxInst_"/> : <xsl:value-of select="$is_blwSbs_"/></xsl:message>
- <xsl:message><xsl:value-of select="$cmplxInst_"/> : <xsl:value-of select="$is_abvSbs_"/></xsl:message>
- <xsl:message>Stack horiz <xsl:value-of select="$cmplxshp_hori_idx_"/></xsl:message>
- <xsl:message>Stack verti <xsl:value-of select="$cmplxshp_vert_idx_"/></xsl:message>
- <xsl:message>Proc Bif Y <xsl:value-of select="$procBif_Y_"/></xsl:message>
--->
-
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
- <xsl:variable name="cmplxshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$cmplxshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$cmplxshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Complex shape Y <xsl:value-of select="$cmplxshp_Y_"/></xsl:message>
--->
-
- <xsl:variable name="stackToEast_">
- <xsl:choose>
- <xsl:when test="not($iStackToEast = 'NONE')"><xsl:value-of select="$iStackToEast"/></xsl:when>
- <xsl:otherwise>NONE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="stackToWest_">
- <xsl:choose>
- <xsl:when test=" not($iStackToWest = 'NONE')"><xsl:value-of select="$iStackToWest"/></xsl:when>
- <xsl:when test="(not($iStackToEast = 'NONE') and not($iStackToEast = '0'))"><xsl:value-of select="($iStackToEast - 1)"/></xsl:when>
- <xsl:otherwise>NONE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="cmplxStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($stackToEast_ = 'NONE') or ($stackToWest_ = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($stackToEast_ = 'NONE') or ($stackToWest_ = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$stackToWest_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$stackToEast_"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($cmplxshp_hori_idx_ = $stackToEast_) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($cmplxshp_hori_idx_ = $stackToWest_) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="bc_Y_" select="($cmplxshp_Y_ + $cmplxBif_Y_ + ceiling($BIF_H div 2) + $cmplxStack_H_diff_) - ceiling($BLKD_BIFC_H div 2)"/>
-
-
-<!--
- <xsl:message>Sstack H Diff <xsl:value-of select="$cmplxStack_H_diff_"/></xsl:message>
- <xsl:message>BC Y <xsl:value-of select="$bc_Y_"/></xsl:message>
- <xsl:variable name="bc_x_" select="($laneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="bc_x_" select="0"/>
--->
- <xsl:variable name="bc_X_">
- <xsl:choose>
- <xsl:when test="$cmplxBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
- </xsl:when>
- <xsl:when test="$cmplxBifSide_ = '1'">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <use x="{$bc_X_}" y="{$bc_Y_}" xlink:href="#{$iBusStd}_busconn_{$cmplxBifType_}"/>
-
- <xsl:variable name="vert_line_x_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="vert_line_y1_" select="($cmplxshp_Y_ + $cmplxBif_Y_ + ceiling($BLKD_BIF_H div 2) + $cmplxStack_H_diff_)"/>
- <xsl:variable name="vert_line_y2_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_BIFC_W div 2))"/>
-
- <xsl:variable name="v_bus_ul_y_">
- <xsl:choose>
- <xsl:when test="$vert_line_y1_ > $vert_line_y2_">
- <xsl:value-of select="$vert_line_y2_"/>
- </xsl:when>
- <xsl:when test="$vert_line_y2_ > $vert_line_y1_">
- <xsl:value-of select="$vert_line_y1_"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="v_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="($vert_line_x_ + $BLKD_MOD_BIF_GAP_H)"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="($vert_line_x_ - $BLKD_MOD_BIF_GAP_H)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="v_bus_height_">
- <xsl:choose>
- <xsl:when test="$vert_line_y1_ > $vert_line_y2_">
- <xsl:value-of select="($vert_line_y1_ - $vert_line_y2_) - $BLKD_P2P_BUS_W + 8"/>
- </xsl:when>
- <xsl:when test="$vert_line_y2_ > $vert_line_y1_">
- <xsl:value-of select="($vert_line_y2_ - $vert_line_y1_) - $BLKD_P2P_BUS_W + 8"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="($bc_X_ + $BLKD_BIFC_W - ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2))"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="$v_bus_ul_x_"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_y_">
- <xsl:choose>
-
- <xsl:when test="($is_blwSbs_ = 'TRUE') and ($vert_line_y1_ > $vert_line_y2_)">
- <xsl:value-of select="$vert_line_y1_ - ceiling($BLKD_P2P_BUS_W div 2)"/>
- </xsl:when>
- <xsl:when test="($is_blwSbs_ = 'TRUE') and ($vert_line_y2_ > $vert_line_y1_)">
- <xsl:value-of select="$vert_line_y2_ - ceiling($BLKD_P2P_BUS_W div 2)"/>
- </xsl:when>
-
- <xsl:when test="($is_abvSbs_ = 'TRUE') and ($vert_line_y1_ > $vert_line_y2_)">
- <xsl:value-of select="$vert_line_y2_ - ceiling($BLKD_P2P_BUS_W div 2)"/>
- </xsl:when>
- <xsl:when test="($is_abvSbs_ = 'TRUE') and ($vert_line_y2_ > $vert_line_y1_)">
- <xsl:value-of select="$vert_line_y1_ - ceiling($BLKD_P2P_BUS_W div 2)"/>
- </xsl:when>
-
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="h_bus_width_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="$v_bus_ul_x_ - $h_bus_ul_x_ + $BLKD_P2P_BUS_W"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="($bc_X_ - $v_bus_ul_x_) + ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2) + 1"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <rect x="{$v_bus_ul_x_}"
- y="{$v_bus_ul_y_ - 2}"
- width= "{$v_bus_width_}"
- height="{$v_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-
- <rect x="{$h_bus_ul_x_}"
- y="{$h_bus_ul_y_}"
- width= "{$h_bus_width_}"
- height="{$h_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-
-</xsl:template>
-
-<!--
- ===========================================================
- Handle connections from processors to Memory UNITs
- ===========================================================
--->
-
-
-<xsl:template name="BCLaneSpace_ProcBifToMemoryUnit">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
-
- <xsl:variable name="bcInSpace_X_" select="$iLaneInSpace_X"/>
- <xsl:variable name="procInstance_" select="BUSCONN[@IS_PROCCONN]/@INSTANCE"/>
- <xsl:variable name="mem_procshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@STACK_HORIZ_INDEX"/>
- <xsl:variable name="mem_procshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@SHAPE_VERTI_INDEX"/>
-
- <xsl:variable name="mem_procshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$mem_procshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$mem_procshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
- <xsl:variable name="cmplxStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($mem_procshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($mem_procshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="mem_procStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($mem_procshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($mem_procshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <!-- Store the conns in a variable -->
- <xsl:variable name="memConn_heights_">
-
- <xsl:for-each select="BUSCONN">
-
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
-
-
- <xsl:choose>
- <xsl:when test="@IS_PROCCONN and @BIF_Y">
-
- <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
- <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="procBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/>
- <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
- <xsl:variable name="bcProc_Y_" select="($mem_procshp_Y_ + $procBif_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $mem_procStack_H_diff_)"/>
- <xsl:variable name="bcProc_X_">
- <xsl:choose>
- <xsl:when test="$procBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
- </xsl:when>
- <xsl:when test="$procBifSide_ = '1'">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <MEMCONN X="{$bcProc_X_}" Y="{$bcProc_Y_}" BUSNAME="{$procBusName_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}"/>
-
- </xsl:when>
-
- <xsl:otherwise>
-
- <xsl:variable name="memcInstance_" select="@INSTANCE"/>
- <xsl:variable name="memcshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $memcInstance_)]]/@SHAPE_VERTI_INDEX"/>
- <xsl:variable name="memcBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $memcInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
- <xsl:variable name="memcBif_Y_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $memcInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_Y"/>
-
- <xsl:variable name="memshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$mem_procshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$memcshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="memcMOD_W_" select="(($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $memcInstance_)]]/@MODS_W) * $BLKD_MOD_W)"/>
-
- <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
-
- <xsl:variable name="memcConn_Y_">
- <xsl:choose>
- <xsl:when test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $memcInstance_)]]/@MODS_H = 1)">
- <xsl:value-of select="($memshp_Y_ + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V) + ($memcBif_Y_ * ($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V)) + ceiling($BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="($memshp_Y_ + $BLKD_MOD_H + $BLKD_MOD_LANE_H + ($memcBif_Y_ * ($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V)) + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="memcConn_X_">
- <xsl:choose>
- <xsl:when test="$memcBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($memcMOD_W_ div 2) + $BLKD_BIFC_W))"/>
- </xsl:when>
- <xsl:when test="$memcBifSide_ = '1'">
- <xsl:value-of select="ceiling($memcMOD_W_ div 2)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="memcBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $memcInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="memcBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $memcInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/>
-
- <MEMCONN X="{$memcConn_X_}" Y="{$memcConn_Y_}" BUSNAME="{$memcBusName_}" BUSSTD="{$iBusStd}" TYPE="{$memcBifType_}" BIFSIDE="{$memcBifSide_}"/>
-
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:variable>
-
-
- <!-- Draw the busconnection and horizontal lines.-->
- <xsl:for-each select="exsl:node-set($memConn_heights_)/MEMCONN">
-
- <xsl:variable name="bus_x_" select="($bcInSpace_X_ + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="bus_y_" select="@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
-
- <xsl:variable name="adjusted_X_">
- <xsl:choose>
- <xsl:when test="((@X < ($bus_x_ + $BLKD_BUS_ARROW_W)) and (@BIFSIDE ='0'))">
- <xsl:value-of select="(@X + $BLKD_P2P_BUS_W)"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="@X"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_x_dx_">
- <xsl:choose>
- <xsl:when test="((@X < ($bus_x_ + $BLKD_BUS_ARROW_W)) and (@BIFSIDE='0'))">
- <xsl:value-of select="$BLKD_P2P_BUS_W"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0'">
- <xsl:value-of select="($bus_x_ - $h_bus_ul_x_dx_)"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1'">
- <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_y_" select="$bus_y_"/>
-
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="h_bus_width_">
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0'">
- <xsl:value-of select="($adjusted_X_ - $bus_x_ - $BLKD_BUS_ARROW_W)"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1'">
- <xsl:value-of select="$bus_x_ - $h_bus_ul_x_"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <!-- Place the bus connection -->
- <use x="{@X}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/>
-
- <!-- Draw the arrow -->
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0'">
- <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowEast"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1'">
- <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowWest"/>
- </xsl:when>
- </xsl:choose>
-
-
- <!-- Draw the horizontal part of the bus -->
- <rect x="{$h_bus_ul_x_}"
- y="{$h_bus_ul_y_}"
- width= "{$h_bus_width_}"
- height="{$h_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
- </xsl:for-each>
-
- <xsl:variable name="busTop_" select="math:min(exsl:node-set($memConn_heights_)/MEMCONN/@Y)"/>
- <xsl:variable name="busBot_" select="math:max(exsl:node-set($memConn_heights_)/MEMCONN/@Y)"/>
- <xsl:variable name="busName_" select="exsl:node-set($memConn_heights_)/MEMCONN/@BUSNAME"/>
- <xsl:variable name="busSide_" select="exsl:node-set($memConn_heights_)/MEMCONN/@BIFSIDE"/>
- <xsl:variable name="leftmost_x_" select="math:min(exsl:node-set($memConn_heights_)/MEMCONN/@X)"/>
-
-<!-- Hack to fix CR473515 -->
- <xsl:variable name="v_bus_x_dx_">
- <xsl:choose>
- <xsl:when test="(($busSide_ = '0') and (($leftmost_x_ - ($bcInSpace_X_ + $BLKD_P2P_BUS_W)) <= $BLKD_P2P_BUS_W))">-4</xsl:when>
- <xsl:otherwise><xsl:value-of select="$BLKD_P2P_BUS_W"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
- <xsl:variable name="v_bus_x_">
- <xsl:choose>
- <xsl:when test="$busSide_ ='0'">
- <xsl:value-of select="($bcInSpace_X_ + $v_bus_x_dx_)"/>
- </xsl:when>
- <xsl:when test="$busSide_ ='1'">
- <xsl:value-of select="($bcInSpace_X_ + $BLKD_P2P_BUS_W)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <!-- Draw the vertical part of the bus -->
- <rect x="{$v_bus_x_}"
- y="{$v_bus_y_}"
- width= "{$BLKD_P2P_BUS_W}"
- height="{($busBot_ - $busTop_) + $BLKD_P2P_BUS_W}"
- style="stroke:none; fill:{$busColor_}"/>
-
-<!-- Hack to fix CR473515 -->
- <xsl:if test="($busSide_ ='0')">
- <rect x="{$v_bus_x_}"
- y="{$v_bus_y_ + ($busBot_ - $busTop_)}"
- width= "{$BLKD_P2P_BUS_W * 2}"
- height="{$BLKD_P2P_BUS_W}"
- style="stroke:none; fill:{$busColor_}"/>
- </xsl:if>
-
-<!--
- <xsl:message>v_bus_x <xsl:value-of select="$v_bus_x_"/></xsl:message>
--->
-
- <!-- Place the bus label.-->
-<!--
- <text class="p2pbuslabel"
- x="{$bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}"
- y="{$busTop_ + ($BLKD_BUS_ARROW_H * 3)}">
- <xsl:value-of select="$busName_"/>
- </text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/>
- <xsl:with-param name="iY" select="($busTop_ + ($BLKD_BUS_ARROW_H * 3))"/>
- <xsl:with-param name="iText" select="$busName_"/>
- <xsl:with-param name="iClass" select="'p2pbus_label'"/>
- </xsl:call-template>
-
-</xsl:template>
-
-
-<!--
- ===========================================================
- Handle generic Point to Point connections
- ===========================================================
--->
-
-<xsl:template name="BCLaneSpace_PointToPoint">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="busColor_lt_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
- <xsl:variable name="bcInSpace_X_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/>
- <xsl:variable name="p2pInstance_" select="BUSCONN[(@BIF_Y)]/@INSTANCE"/>
-
- <xsl:variable name="p2pshp_hori_idx_">
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]/@STACK_HORIZ_INDEX"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $p2pInstance_)])]/@STACK_HORIZ_INDEX"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="p2pshp_vert_idx_">
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]/@SHAPE_VERTI_INDEX"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $p2pInstance_)])]/@SHAPE_VERTI_INDEX"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:variable name="p2pshp_hori_idx_" select="/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@STACK_HORIZ_INDEX"/>
- <xsl:variable name="p2pshp_vert_idx_" select="/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@SHAPE_VERTI_INDEX"/>
--->
-
- <xsl:variable name="p2pshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$p2pshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$p2pshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="cmplxStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($p2pshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($p2pshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="procStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($p2pshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($p2pshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
-
- <!-- Store the conns in a variable -->
- <xsl:variable name="p2pConn_heights_">
-
- <xsl:for-each select="BUSCONN">
-
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
-
- <xsl:choose>
- <xsl:when test="@IS_PROCCONN and @BIF_Y">
-
-<!--
- <xsl:message>Proc <xsl:value-of select="$procInstance_"/></xsl:message>
--->
- <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
- <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="procBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/>
- <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
-
- <xsl:variable name="bcProc_Y_" select="($p2pshp_Y_ + $procBif_Y_ + ceiling($BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $procStack_H_diff_)"/>
- <xsl:variable name="bcProc_X_">
- <xsl:choose>
- <xsl:when test="$procBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
- </xsl:when>
- <xsl:when test="$procBifSide_ = '1'">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <P2PCONN X="{$bcProc_X_}" Y="{$bcProc_Y_}" BUSNAME= "{$procBusName_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}"/>
-
-<!--
- <xsl:message>bcProc_X_ <xsl:value-of select="$bcProc_X_"/></xsl:message>
- <xsl:message>bcProc_Y_ <xsl:value-of select="$bcProc_Y_"/></xsl:message>
- <P2PCONN X="{$bcInSpace_X_}" Y="{$bcProc_Y_}" BUSSTD="{$busStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}" STACK_ID=""/>
--->
- </xsl:when>
-
- <xsl:otherwise>
-
- <xsl:variable name="modInstance_" select="@INSTANCE"/>
- <xsl:variable name="modshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $modInstance_)]]/@SHAPE_VERTI_INDEX"/>
- <xsl:variable name="modBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
- <xsl:variable name="modBif_Y_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_Y"/>
- <xsl:variable name="modBc_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $modBif_Y_) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
-
-<!--
- <xsl:message>Memory Instance <xsl:value-of select="$procInstance_"/></xsl:message>
--->
-
- <xsl:variable name="modshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$p2pshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$modshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="modBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="modBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/>
- <xsl:variable name="bcMod_Y_" select="($modshp_Y_ + $modBc_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/>
- <xsl:variable name="bcMod_X_">
- <xsl:choose>
- <xsl:when test="$modBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
- </xsl:when>
- <xsl:when test="$modBifSide_ = '1'">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>Bc Bif Y <xsl:value-of select="$modBif_Y_"/></xsl:message>
- <xsl:message>Bc Mod Y <xsl:value-of select="$modBc_Y_"/></xsl:message>
- <xsl:message>Bc Mod X <xsl:value-of select="$bcMod_X_"/></xsl:message>
- <P2PCONN X="{$bcInSpace_X_}" Y="{$bcMod_Y_}" BUSSTD="{$busStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}"/>
--->
- <P2PCONN X="{$bcMod_X_}" Y="{$bcMod_Y_}" BUSNAME="{$modBusName_}" BUSSTD="{$iBusStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}"/>
-
- </xsl:otherwise>
-
- </xsl:choose>
- </xsl:for-each>
- </xsl:variable>
-
-
- <xsl:variable name="busTop_" select="math:min(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/>
- <xsl:variable name="busBot_" select="math:max(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/>
- <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
- <xsl:variable name="busName_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSNAME"/>
- <xsl:variable name="busStd_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSSTD"/>
-<!--
--->
- <!-- Draw the vertical part of the bus -->
- <xsl:if test="$busStd_ = 'PLBV46_P2P'">
- <rect x="{$bcInSpace_X_ + $BLKD_P2P_BUS_W}"
- y="{$v_bus_y_}"
- width= "{$BLKD_P2P_BUS_W}"
- height="{($busBot_ - $busTop_) + $BLKD_P2P_BUS_W}"
- style="stroke:{$COL_WHITE};stroke-width:1.5;fill:{$busColor_}"/>
- </xsl:if>
-
- <xsl:if test="not($busStd_ = 'PLBV46_P2P')">
- <rect x="{$bcInSpace_X_ + $BLKD_P2P_BUS_W}"
- y="{$v_bus_y_}"
- width= "{$BLKD_P2P_BUS_W}"
- height="{($busBot_ - $busTop_) + $BLKD_P2P_BUS_W}"
- style="stroke:none;fill:{$busColor_}"/>
- </xsl:if>
-
-<!-- -->
-
-<!--
- style="stroke:{$busColor_lt_};stroke-width:1;stroke-opacity:0.9;fill-opacity:2.0;fill:{$busColor_}"/>
--->
-
- <!-- Place the bus label.-->
-<!--
- <text class="p2pbuslabel"
- x="{$bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}"
- y="{$busTop_ + ($BLKD_BUS_ARROW_H * 3)}">
- <xsl:value-of select="$busName_"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/>
- <xsl:with-param name="iY" select="($busTop_ + ($BLKD_BUS_ARROW_H * 3))"/>
- <xsl:with-param name="iText" select="$busName_"/>
- <xsl:with-param name="iClass" select="'p2pbus_label'"/>
- </xsl:call-template>
-
- <!-- Draw the busconnection and horizontal lines.-->
- <xsl:for-each select="exsl:node-set($p2pConn_heights_)/P2PCONN">
-
- <xsl:variable name="bus_x_" select="($bcInSpace_X_ + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="bus_y_" select="@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
-
- <xsl:variable name="h_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0'">
- <xsl:value-of select="$bus_x_"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1'">
- <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W) - 1"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_y_" select="$bus_y_"/>
-
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="h_bus_width_">
-<!--
- <xsl:message>BIFSIDE <xsl:value-of select="@BIFSIDE"/></xsl:message>
- <xsl:message>BUSSTD <xsl:value-of select="@BUSSTD"/></xsl:message>
- <xsl:message>TYPE <xsl:value-of select="@TYPE"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0'">
- <xsl:value-of select="(@X - $bus_x_ - $BLKD_BUS_ARROW_W)"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1'">
- <xsl:value-of select="$bus_x_ - $h_bus_ul_x_ + 1"/>
- </xsl:when>
-
- </xsl:choose>
- </xsl:variable>
-
- <!-- Draw Bus connection-->
- <use x="{@X}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/>
-
- <!-- Draw the arrow -->
- <xsl:choose>
- <xsl:when test="((@BIFSIDE='0') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowEast"/>
- </xsl:when>
- <xsl:when test="((@BIFSIDE='1') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowWest"/>
- </xsl:when>
-
- <xsl:when test="((@BIFSIDE='0') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/>
- </xsl:when>
-
- <xsl:when test="((@BIFSIDE='1') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/>
- </xsl:when>
-
- </xsl:choose>
-
- <!-- Draw the horizontal part of the bus -->
- <rect x="{$h_bus_ul_x_}"
- y="{$h_bus_ul_y_}"
- width= "{$h_bus_width_}"
- height="{$h_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-
- </xsl:for-each>
-
-<!--
- <xsl:variable name="busTop_" select="math:min(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/>
- <xsl:variable name="busBot_" select="math:max(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/>
- <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($P2P_BUS_W div 2)"/>
- <xsl:variable name="busName_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSNAME"/>
--->
- <!-- Draw the vertical part of the bus -->
-<!--
- <rect x="{$bcInSpace_X_ + $P2P_BUS_W}"
- y="{$v_bus_y_}"
- width= "{$P2P_BUS_W}"
- height="{($busBot_ - $busTop_) + $P2P_BUS_W}"
- style="stroke:{$COL_WHITE};stroke-width:1;stroke-opacity:0.9;fill-opacity:2.0;fill:{$busColor_}"/>
--->
-
-<!--
- style="stroke:{$busColor_lt_};stroke-width:1;stroke-opacity:0.9;fill-opacity:2.0;fill:{$busColor_}"/>
--->
- <!-- Place the bus label.-->
-<!--
- <text class="p2pbuslabel"
- x="{$bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}"
- y="{$busTop_ + ($BLKD_BUS_ARROW_H * 3)}">
- <xsl:value-of select="$busName_"/>
- </text>
--->
-
-
-</xsl:template>
-
-
-
-<!--
- ===========================================================
- Handle MultiStack Point to Point connections
- ===========================================================
--->
-
-<xsl:template name="BCLaneSpace_MultiStack_PointToPoint">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
-
-<!--
- <xsl:message>Stack To East <xsl:value-of select="$iStackToEast"/></xsl:message>
- <xsl:message>Stack to West <xsl:value-of select="$iStackToWest"/></xsl:message>
- <xsl:message>Stack to East Width <xsl:value-of select="$iStackToEast_W"/></xsl:message>
- <xsl:message>Stack to West Width <xsl:value-of select="$iStackToWest_W"/></xsl:message>
- <xsl:message>Lane in space X <xsl:value-of select="$iLaneInSpace_X"/></xsl:message>
- <xsl:message>Shared Bus Y <xsl:value-of select="$iSpaceSharedBus_Y"/></xsl:message>
--->
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
- <!-- Store the connections in a variable -->
- <xsl:variable name="bcInSpace_X_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/>
-
- <xsl:variable name="multiConns_">
-
- <xsl:for-each select="BUSCONN">
-
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
- <xsl:variable name="multiInstance_" select="@INSTANCE"/>
- <xsl:variable name="mulshp_hori_idx_">
- <xsl:choose>
- <xsl:when test="@IS_PROCCONN">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $multiInstance_)]/@STACK_HORIZ_INDEX"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $multiInstance_)])]/@STACK_HORIZ_INDEX"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="mulshp_vert_idx_">
- <xsl:choose>
- <xsl:when test="@IS_PROCCONN">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $multiInstance_)]/@SHAPE_VERTI_INDEX"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $multiInstance_)])]/@SHAPE_VERTI_INDEX"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>Shape Horiz <xsl:value-of select="$mulshp_hori_idx_"/></xsl:message>
- <xsl:message>Shape Verti <xsl:value-of select="$mulshp_vert_idx_"/></xsl:message>
--->
-
- <xsl:variable name="mulshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$mulshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$mulshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="cmplxStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($mulshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($mulshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="procStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($mulshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($mulshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:choose>
-
- <xsl:when test="@IS_PROCCONN and @BIF_Y">
-
- <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
-
- <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="procBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/>
- <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
-
- <xsl:variable name="bcProc_Y_" select="($mulshp_Y_ + $procBif_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $procStack_H_diff_)"/>
-
- <xsl:variable name="bcProc_X_">
- <xsl:choose>
- <xsl:when test="$procBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
-<!--
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - ceiling($BLKD_MOD_W div 2))"/>
--->
- </xsl:when>
- <xsl:when test="$procBifSide_ = '1'">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <MULTICONN X="{$bcProc_X_}" Y="{$bcProc_Y_}" BUSNAME="{$procBusName_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}" IS_PROC="TRUE"/>
- </xsl:when>
-
- <xsl:otherwise>
-
- <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/@MODCLASS"/>
- <xsl:variable name="modBif_Y_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_Y"/>
- <xsl:variable name="modBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
- <xsl:variable name="modBusStd_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSSTD"/>
- <xsl:variable name="memcMOD_W_" select="(($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $multiInstance_)]]/@MODS_W) * $BLKD_MOD_W)"/>
-
- <xsl:variable name="modBc_Y_">
- <xsl:choose>
- <xsl:when test="($modType_ = 'MEMORY_CNTLR') and (($modBusStd_ = 'LMB') or ($modBusStd_= 'OCM'))">
- <xsl:value-of select="$BLKD_MOD_H + $BLKD_MOD_LANE_H + ((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $modBif_Y_))"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $modBif_Y_) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-<!--
- <xsl:message><xsl:value-of select="$multiInstance_"/>.<xsl:value-of select="$bifName_"/>:Y = <xsl:value-of select="$modBif_Y_"/></xsl:message>
- <xsl:message><xsl:value-of select="$multiInstance_"/>.<xsl:value-of select="$bifName_"/>:BcY = <xsl:value-of select="$modBc_Y_"/></xsl:message>
- <xsl:message><xsl:value-of select="$multiInstance_"/>.<xsl:value-of select="$bifName_"/>:TcY = <xsl:value-of select="($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V)"/></xsl:message>
--->
-
- <xsl:variable name="modBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="modBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/>
-
-<!--
- <xsl:variable name="bcMod_Y_" select="($mulshp_Y_ + $modBc_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2))"/>
--->
- <xsl:variable name="bcMod_Y_" select="($mulshp_Y_ + $modBc_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/>
-
- <xsl:variable name="bcMod_X_">
- <xsl:choose>
- <xsl:when test="$modBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($memcMOD_W_ div 2) + $BLKD_BIFC_W))"/>
-<!--
- -->
- </xsl:when>
- <xsl:when test="$modBifSide_ = '1'">
- <xsl:value-of select="ceiling($memcMOD_W_ div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <MULTICONN X="{$bcMod_X_}" Y="{$bcMod_Y_}" BUSNAME="{$modBusName_}" BUSSTD="{$iBusStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}" IS_MOD="TRUE"/>
-<!--
- <MULTICONN X="{$bcInSpace_X_}" Y="{$bcMod_Y_}" BUSSTD="{$busStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}"/>
--->
-
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:variable>
-
- <!-- Draw the busconnection and horizontal lines.-->
- <xsl:for-each select="exsl:node-set($multiConns_)/MULTICONN">
-
- <xsl:variable name="bus_x_" select="($bcInSpace_X_ + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="bus_y_" select="@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
-
-<!--
- <xsl:value-of select="$bus_x_"/>
--->
- <xsl:variable name="h_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0' and (@IS_PROC)">
- <xsl:value-of select="$bus_x_ - $BLKD_P2P_BUS_W"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='0' and (@IS_MOD)">
- <xsl:value-of select="$bus_x_ - $BLKD_P2P_BUS_W"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1' and (@IS_PROC)">
- <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1' and (@IS_MOD)">
- <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_y_" select="$bus_y_"/>
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="h_bus_width_">
-<!--
- <xsl:message>BUSSTD <xsl:value-of select="@BUSSTD"/></xsl:message>
- <xsl:message>BIFSIDE <xsl:value-of select="@BIFSIDE"/></xsl:message>
- <xsl:message>TYPE <xsl:value-of select="@TYPE"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0' and (@IS_PROC)">
- <xsl:value-of select="(@X - $bus_x_ - $BLKD_P2P_BUS_W)"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='0' and (@IS_MOD)">
- <xsl:value-of select="(@X - $bus_x_ - $BLKD_BUS_ARROW_W)"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1' and (@IS_PROC)">
- <xsl:value-of select="$bus_x_ - $h_bus_ul_x_ - $BLKD_BUS_ARROW_W - $BLKD_P2P_BUS_W"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1' and (@IS_MOD)">
- <xsl:value-of select="$BLKD_P2P_BUS_W + $BLKD_BUS_ARROW_W "/>
-<!--
- <xsl:value-of select="$bus_x_ - $h_bus_ul_x_"/>
- -->
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
-<!--
- <xsl:message>h_bus_x_ <xsl:value-of select="$h_bus_ul_x_"/></xsl:message>
- <xsl:message>BIFSIDE <xsl:value-of select="@BIFSIDE"/></xsl:message>
- <xsl:message>h_bus_width_ <xsl:value-of select="$h_bus_width_"/></xsl:message>
- -->
-
- <!-- Draw the horizontal part of the bus -->
- <xsl:if test="($h_bus_width_ > 0)">
- <rect x="{$h_bus_ul_x_}"
- y="{$h_bus_ul_y_}"
- width= "{$h_bus_width_}"
- height="{$h_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
- </xsl:if>
-
-
- <!-- Draw the arrow -->
- <xsl:choose>
- <xsl:when test="((@BIFSIDE='0') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowEast"/>
- </xsl:when>
- <xsl:when test="((@BIFSIDE='1') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowWest"/>
- </xsl:when>
-
- <xsl:when test="((@BIFSIDE='0') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/>
- </xsl:when>
-
- <xsl:when test="((@BIFSIDE='1') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/>
- </xsl:when>
-
- </xsl:choose>
-
- <use x="{@X}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/>
- </xsl:for-each>
-
- <xsl:variable name="busTop_" select="math:min(exsl:node-set($multiConns_)/MULTICONN/@Y)"/>
- <xsl:variable name="busBot_" select="math:max(exsl:node-set($multiConns_)/MULTICONN/@Y)"/>
- <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
- <xsl:variable name="busName_" select="exsl:node-set($multiConns_)/MULTICONN/@BUSNAME"/>
-
-<!--
--->
- <!-- Draw the vertical part of the bus -->
- <rect x="{$bcInSpace_X_ - $BLKD_P2P_BUS_W}"
- y="{$v_bus_y_}"
- width= "{$BLKD_P2P_BUS_W}"
- height="{($busBot_ - $busTop_) + $BLKD_P2P_BUS_W}"
- style="stroke:none; fill:{$busColor_}"/>
-<!--
- <xsl:message>v_bus_x_ <xsl:value-of select="($bcInSpace_X_ + $BLKD_P2P_BUS_W)"/></xsl:message>
- -->
-
- <!-- Place the bus label.-->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/>
- <xsl:with-param name="iY" select="($busTop_ + ($BLKD_BUS_ARROW_H * 3))"/>
- <xsl:with-param name="iText" select="$busName_"/>
- <xsl:with-param name="iClass" select="'p2pbus_label'"/>
- </xsl:call-template>
-
-</xsl:template>
-
-
-<!--
- ===========================================================
- Handle Processor to processor connections
- ===========================================================
--->
-<xsl:template name="BCLaneSpace_ProcToProc">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
- <xsl:variable name="pr2pr_StackToWest_" select="math:min(BUSCONN/@STACK_HORIZ_INDEX)"/>
- <xsl:variable name="pr2pr_StackToEast_" select="math:max(BUSCONN/@STACK_HORIZ_INDEX)"/>
- <xsl:variable name="proc2procConn_heights_">
-
- <xsl:for-each select="BUSCONN">
-
- <xsl:variable name="procInstance_" select="@INSTANCE"/>
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
- <xsl:variable name="procshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@STACK_HORIZ_INDEX"/>
- <xsl:variable name="procshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@SHAPE_VERTI_INDEX"/>
- <xsl:variable name="procshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$procshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$procshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="procStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($pr2pr_StackToEast_ = 'NONE') or ($pr2pr_StackToWest_ = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($pr2pr_StackToEast_ = 'NONE') or ($pr2pr_StackToWest_ = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$pr2pr_StackToWest_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$pr2pr_StackToEast_"/>
- </xsl:call-template>
- </xsl:variable>
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($procshp_hori_idx_ = $pr2pr_StackToEast_) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($procshp_hori_idx_ = $pr2pr_StackToWest_) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <!-- Store the conns in a variable -->
- <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
-
- <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
-
- <xsl:variable name="bcInSpace_X_">
- <xsl:choose>
- <xsl:when test="$procBifSide_ = '1'"><xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/></xsl:when>
- <xsl:when test="$procBifSide_ = '0'"><xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/></xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bcProc_Y_" select="($procshp_Y_ + $procBif_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $procStack_H_diff_)"/>
-<!--
- <xsl:message>Conn X <xsl:value-of select="$bcInSpace_X_"/></xsl:message>
- <xsl:message>Conn Y <xsl:value-of select="$bcProc_Y_"/></xsl:message>
--->
-
- <PR2PRCONN X="{$bcInSpace_X_}" Y="{$bcProc_Y_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}" SHAPE_ID="{$procshp_hori_idx_}"/>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:variable name="pr2prLeft_" select="math:min(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@SHAPE_ID)"/>
- <xsl:variable name="pr2prRght_" select="math:max(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@SHAPE_ID)"/>
-
- <xsl:variable name="pr2pr_stack_Left_X_">
- <xsl:call-template name="F_Calc_Stack_X">
- <xsl:with-param name="iStackIdx" select="$pr2prLeft_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="pr2pr_stack_Rght_X_">
- <xsl:call-template name="F_Calc_Stack_X">
- <xsl:with-param name="iStackIdx" select="$pr2prRght_"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Left stack X <xsl:value-of select="$pr2pr_stack_Left_X_"/></xsl:message>
- <xsl:message>Rght stack X <xsl:value-of select="$pr2pr_stack_Rght_X_"/></xsl:message>
--->
- <xsl:variable name="pr2pr_space_W_" select="($pr2pr_stack_Rght_X_ - $pr2pr_stack_Left_X_)"/>
-
-
- <xsl:variable name="pr2pr_extStackEast_W_">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="$pr2prRght_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="pr2pr_extStackWest_W_">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="$pr2prLeft_"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Space W <xsl:value-of select="$pr2pr_space_W_"/></xsl:message>
- <xsl:message>Rght stack <xsl:value-of select="$pr2pr_extStackEast_W_"/></xsl:message>
- <xsl:message>Left stack <xsl:value-of select="$pr2pr_extStackWest_W_"/></xsl:message>
--->
-
- <xsl:variable name="connLeft_X_" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:variable name="connRght_X_" select="($pr2pr_space_W_ - ceiling($pr2pr_extStackWest_W_ div 2) + ceiling($pr2pr_extStackEast_W_ div 2) - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/>
-
- <!-- Draw the busconnections .-->
- <xsl:for-each select="exsl:node-set($proc2procConn_heights_)/PR2PRCONN">
- <xsl:variable name="conn_X_">
- <xsl:choose>
- <xsl:when test="@BIFSIDE = '1'"><xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/></xsl:when>
- <xsl:when test="@BIFSIDE = '0'"><xsl:value-of select="($pr2pr_space_W_ - ceiling($pr2pr_extStackWest_W_ div 2) + ceiling($pr2pr_extStackEast_W_ div 2) - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/></xsl:when>
-<!--
- <xsl:when test="@BIFSIDE = '0'"><xsl:value-of select="($pr2pr_space_W_ + $pr2pr_extStackWest_W_ + $pr2pr_extStackEast_W_ - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/></xsl:when>
--->
- </xsl:choose>
- </xsl:variable>
-
- <use x="{$conn_X_}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/>
- </xsl:for-each>
-
- <xsl:variable name="bc_Y_" select="math:min(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@Y)"/>
- <xsl:variable name="bcLeft_" select="math:min(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@X)"/>
- <xsl:variable name="bcRght_" select="math:max(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@X)"/>
-
- <xsl:variable name="leftType_" select="(exsl:node-set($proc2procConn_heights_)/PR2PRCONN[(@X = $bcLeft_)]/@TYPE)"/>
- <xsl:variable name="rghtType_" select="(exsl:node-set($proc2procConn_heights_)/PR2PRCONN[(@X = $bcRght_)]/@TYPE)"/>
-
- <xsl:call-template name="Draw_Proc2ProcBus">
- <xsl:with-param name="iBc_Y" select="$bc_Y_"/>
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- <xsl:with-param name="iBusName" select="$iBusName"/>
- <xsl:with-param name="iLeftType" select="$leftType_"/>
- <xsl:with-param name="iRghtType" select="$rghtType_"/>
- <xsl:with-param name="iBcLeft_X" select="$connLeft_X_ + $BLKD_BIFC_W"/>
- <xsl:with-param name="iBcRght_X" select="$connRght_X_"/>
- </xsl:call-template>
-
-</xsl:template>
-
-<!--
- ===========================================================
- Handle connections to the MPMC
- ===========================================================
--->
-<xsl:template name="BCLaneSpace_ToStandAloneMPMC">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="busColor_lt_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
- <xsl:variable name="bcInSpace_X_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/>
- <xsl:variable name="p2pInstance_" select="BUSCONN[(@BIF_Y)]/@INSTANCE"/>
-
- <xsl:variable name="p2pshp_hori_idx_">
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]/@STACK_HORIZ_INDEX"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $p2pInstance_)])]/@STACK_HORIZ_INDEX"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="p2pshp_vert_idx_">
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]/@SHAPE_VERTI_INDEX"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $p2pInstance_)])]/@SHAPE_VERTI_INDEX"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="p2pshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$p2pshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$p2pshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="cmplxStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
-
- <xsl:choose>
- <xsl:when test="(($p2pshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($p2pshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="procStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message>
- <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message>
--->
- <xsl:choose>
- <xsl:when test="(($p2pshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($p2pshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
-
- <!-- Store the conns in a variable -->
- <xsl:variable name="p2pConn_heights_">
-
- <xsl:for-each select="BUSCONN">
-
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
-
- <xsl:choose>
- <xsl:when test="@IS_PROCCONN and @BIF_Y">
-
-<!--
- <xsl:message>Proc <xsl:value-of select="$procInstance_"/></xsl:message>
--->
- <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
- <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="procBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/>
- <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
-
- <xsl:variable name="bcProc_Y_" select="($p2pshp_Y_ + $procBif_Y_ + ceiling($BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $procStack_H_diff_)"/>
- <xsl:variable name="bcProc_X_">
- <xsl:choose>
- <xsl:when test="$procBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
- </xsl:when>
- <xsl:when test="$procBifSide_ = '1'">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <P2PCONN X="{$bcProc_X_}" Y="{$bcProc_Y_}" BUSNAME= "{$procBusName_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}"/>
-
- </xsl:when>
-
- <xsl:otherwise>
-
- <xsl:variable name="modInstance_" select="@INSTANCE"/>
- <xsl:variable name="modshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $modInstance_)]]/@SHAPE_VERTI_INDEX"/>
- <xsl:variable name="modBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
- <xsl:variable name="modBif_Y_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_Y"/>
- <xsl:variable name="modBc_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $modBif_Y_) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
-
-<!--
- <xsl:message>Memory Instance <xsl:value-of select="$procInstance_"/></xsl:message>
--->
-
- <xsl:variable name="modshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$p2pshp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$modshp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="modBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="modBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/>
- <xsl:variable name="bcMod_Y_" select="($modshp_Y_ + $modBc_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/>
- <xsl:variable name="bcMod_X_">
- <xsl:choose>
- <xsl:when test="$modBifSide_ = '0'">
- <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/>
- </xsl:when>
- <xsl:when test="$modBifSide_ = '1'">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <P2PCONN X="{$bcMod_X_}" Y="{$bcMod_Y_}" BUSNAME="{$modBusName_}" BUSSTD="{$iBusStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}"/>
-
- </xsl:otherwise>
-
- </xsl:choose>
- </xsl:for-each>
- </xsl:variable>
-
-
- <xsl:variable name="busTop_" select="math:min(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/>
- <xsl:variable name="busBot_" select="math:max(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/>
- <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
-
- <xsl:variable name="busName_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSNAME"/>
- <xsl:variable name="busStd_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSSTD"/>
-
- <!-- Draw the vertical part of the bus -->
- <!-- Place the bus label.-->
- <!-- Draw the busconnection and horizontal lines.-->
- <xsl:for-each select="exsl:node-set($p2pConn_heights_)/P2PCONN">
-
- <xsl:variable name="bus_x_" select="($bcInSpace_X_ + ceiling($BLKD_BIFC_W div 2))"/>
- <xsl:variable name="bus_y_" select="@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
-
- <xsl:variable name="h_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0'">
- <xsl:value-of select="$bus_x_"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1'">
- <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W) - 1"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_y_" select="$bus_y_"/>
-
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="h_bus_width_">
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0'">
- <xsl:value-of select="(@X - $bus_x_ - $BLKD_BUS_ARROW_W)"/>
- </xsl:when>
- <xsl:when test="@BIFSIDE='1'">
- <xsl:value-of select="$bus_x_ - $h_bus_ul_x_ + 1"/>
- </xsl:when>
-
- </xsl:choose>
- </xsl:variable>
-
- <!-- Draw Bus connection-->
- <use x="{@X}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/>
-
- <!-- Draw the arrow -->
- <xsl:choose>
- <xsl:when test="((@BIFSIDE='0') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowEast"/>
- </xsl:when>
- <xsl:when test="((@BIFSIDE='1') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowWest"/>
- </xsl:when>
-
- <xsl:when test="((@BIFSIDE='0') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/>
- </xsl:when>
-
- <xsl:when test="((@BIFSIDE='1') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))">
- <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/>
- </xsl:when>
-
- </xsl:choose>
-
- <!-- Draw the horizontal part of the bus -->
- <rect x="{$h_bus_ul_x_}"
- y="{$h_bus_ul_y_}"
- width= "{$h_bus_width_}"
- height="{$h_bus_height_}"
-
- style="stroke:none; fill:{$busColor_}"/>
-
- <!--
- Draw the vertical part of the bus. The MPMC BIF and the top arrow will
- be added later when the main drawing happens.
- -->
- <xsl:variable name="v_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@BIFSIDE='0'"><xsl:value-of select="($h_bus_ul_x_)"/></xsl:when>
- <xsl:when test="@BIFSIDE='1'"><xsl:value-of select="($h_bus_ul_x_ + $h_bus_width_ - $BLKD_P2P_BUS_W)"/></xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <rect x="{$v_bus_ul_x_}"
- y="0"
- width= "{$BLKD_P2P_BUS_W}"
- height="{$h_bus_ul_y_}"
- style="stroke:none; fill:{$busColor_}"/>
- </xsl:for-each>
-
-</xsl:template>
-
-
-
-<!--
- ======================================================================
- Handle Split connections, (connections that go between adjacent stacks)
- ======================================================================
--->
-
-<xsl:template name="BCLaneSpace_SplitConn">
-
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:param name="iBusName" select="'NONE'"/>
- <xsl:param name="iBifType" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast_W" select="0"/>
- <xsl:param name="iStackToWest_W" select="0"/>
- <xsl:param name="iLaneInSpace_X" select="0"/>
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/>
-
-
- <xsl:variable name="bifName_" select="BUSCONN/@BUSINTERFACE"/>
- <xsl:variable name="shpInstance_" select="BUSCONN/@INSTANCE"/>
-
-<!--
- <xsl:message>Found a split connection on <xsl:value-of select="$shpInstance_"/></xsl:message>
--->
-
-
- <xsl:variable name="shp_hori_idx_">
-
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]">
- <xsl:value-of select="/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]/@STACK_HORIZ_INDEX"/>
- </xsl:when>
-
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]/@STACK_HORIZ_INDEX"/>
- </xsl:when>
- <xsl:otherwise>_unknown_</xsl:otherwise>
- </xsl:choose>
-
- </xsl:variable>
-
- <xsl:variable name="shp_vert_idx_">
-
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]">
- <xsl:value-of select="/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]/@SHAPE_VERTI_INDEX"/>
- </xsl:when>
-
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]/@SHAPE_VERTI_INDEX"/>
- </xsl:when>
- <xsl:otherwise>_unknown_</xsl:otherwise>
- </xsl:choose>
-
- </xsl:variable>
-
- <xsl:variable name="splitshp_Width_">
-
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]">
- <xsl:value-of select="$BLKD_MOD_W"/>
- </xsl:when>
-
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]/@MODS_W">
-<!--
- <xsl:message>Using mods width on <xsl:value-of select="$shpInstance_"/></xsl:message>
--->
- <xsl:value-of select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]/@MODS_W * $BLKD_MOD_W)"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$BLKD_MOD_W"/>
- </xsl:otherwise>
- </xsl:choose>
-
- </xsl:variable>
-
-<!--
- <xsl:message>Found width of <xsl:value-of select="$splitshp_Width_"/></xsl:message>
--->
-
-
- <xsl:variable name="splitshp_Y_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$shp_hori_idx_"/>
- <xsl:with-param name="iVertiIdx" select="$shp_vert_idx_"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <xsl:variable name="splitStack_H_diff_">
- <xsl:choose>
- <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">
-
- <xsl:variable name="stackToWest_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackToEast_AbvSbs_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:choose>
- <xsl:when test="(($shp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))">
- <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:when test="(($shp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))">
- <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="splitBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * BUSCONN/@BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
- <xsl:variable name="splitBusStd_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $shpInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSSTD"/>
- <xsl:variable name="splitBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $shpInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/>
- <xsl:variable name="splitBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $shpInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/>
-
- <xsl:variable name="bcInSpace_X_">
- <xsl:choose>
- <xsl:when test="$splitBifSide_ = '1'"><xsl:value-of select="ceiling($splitshp_Width_ div 2)"/></xsl:when>
- <xsl:when test="$splitBifSide_ = '0'"><xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - ceiling($splitshp_Width_ div 2) - $BLKD_BIFC_W)"/></xsl:when>
- </xsl:choose>
-
- </xsl:variable>
-
- <xsl:variable name="bcBus_X_">
- <xsl:choose>
- <xsl:when test="$splitBifSide_ = '1'"><xsl:value-of select="$bcInSpace_X_"/></xsl:when>
- <xsl:when test="$splitBifSide_ = '0'"><xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/></xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bcSplit_Y_">
- <xsl:choose>
- <xsl:when test="(BUSCONN/@IS_MEMCONN) and (($splitBusStd_ = 'LMB') or ($splitBusStd_ = 'OCM'))">
-<!--
- <xsl:message>Found memory conn split connection on <xsl:value-of select="$shpInstance_"/> </xsl:message>
--->
- <xsl:value-of select="($splitshp_Y_ + $BLKD_MOD_H + $BLKD_MOD_BIF_GAP_V + (BUSCONN/@BIF_Y * ($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V)) + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $splitStack_H_diff_)"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="($splitshp_Y_ + $splitBif_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $splitStack_H_diff_)"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <use x="{$bcInSpace_X_}" y="{$bcSplit_Y_}" xlink:href="#{@BUSSTD}_busconn_{$splitBifType_}"/>
-
-
- <xsl:call-template name="Draw_SplitConnBus">
- <xsl:with-param name="iBc_Y" select="$bcSplit_Y_"/>
- <xsl:with-param name="iBc_X" select="$bcInSpace_X_"/>
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- <xsl:with-param name="iBc_Type" select="$splitBifType_"/>
- <xsl:with-param name="iBc_Side" select="$splitBifSide_"/>
- <xsl:with-param name="iBusName" select="$iBusName"/>
- </xsl:call-template>
-
-
-</xsl:template>
-
-
-<xsl:template name="Define_BusLaneSpace">
-
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
-
-<!--
- <xsl:message>Input Stack to West <xsl:value-of select="$iStackToWest"/></xsl:message>
- <xsl:message>Input Stack to East <xsl:value-of select="$iStackToEast"/></xsl:message>
--->
-
- <xsl:variable name="stackToEast_">
- <xsl:choose>
- <xsl:when test="not($iStackToEast = 'NONE')"><xsl:value-of select="$iStackToEast"/></xsl:when>
- <xsl:otherwise>NONE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="stackToWest_">
- <xsl:choose>
- <xsl:when test=" not($iStackToWest = 'NONE')"><xsl:value-of select="$iStackToWest"/></xsl:when>
- <xsl:when test="(not($iStackToEast = 'NONE') and not($iStackToEast = '0'))"><xsl:value-of select="($iStackToEast - 1)"/></xsl:when>
- <xsl:otherwise>NONE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="spaceAbvSbs_H_">
- <xsl:call-template name="F_Calc_Space_AbvSbs_Height">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="spaceBlwSbs_H_">
- <xsl:call-template name="F_Calc_Space_BlwSbs_Height">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <xsl:variable name="space_H_" select="($spaceAbvSbs_H_ + $BLKD_PROC2SBS_GAP + $G_Total_SharedBus_H + $spaceBlwSbs_H_)"/>
- <xsl:variable name="space_W_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="spaceSharedBus_Y_" select="$spaceAbvSbs_H_ + $BLKD_PROC2SBS_GAP"/>
-
- <xsl:variable name="space_name_">
- <xsl:call-template name="F_generate_Space_Name">
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name = "stackToWest_W_">
- <xsl:choose>
- <xsl:when test="(($iStackToEast = '0') and ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="(($iStackToEast = 'NONE') and not($iStackToWest = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:when test="(not($iStackToEast = '0') and not($iStackToEast = 'NONE') and ($iStackToWest = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="($iStackToEast - 1)"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name = "stackToEast_W_">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($stackToWest_W_ div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($stackToEast_W_ div 2)"/>
-
- <g id="{$space_name_}">
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[((@EAST = $iStackToEast) or (($iStackToEast = 'NONE') and (@WEST = $iStackToWest)))]/BUSCONNLANE[@BUSSTD and @BUSNAME]">
-
- <xsl:variable name="busStd_" select="@BUSSTD"/>
- <xsl:variable name="busName_" select="@BUSNAME"/>
- <xsl:variable name="busLane_X_" select="@BUSLANE_X"/>
-
-<!--
- <xsl:variable name="eastBusLane_X_">
- <xsl:choose>
- <xsl:when test="(@BUSLANE_X = 0)"><xsl:value-of select="@BUSLANE_X"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="(@BUSLANE_X - 1)"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
--->
- <xsl:variable name="eastBusLane_X_" select="@BUSLANE_X"/>
- <xsl:variable name="laneInSpace_X_">
- <xsl:choose>
- <xsl:when test="(@ORIENTED = 'EAST')">
- <xsl:value-of select="($extSpaceWest_W_ + ($eastBusLane_X_ * $BLKD_BUS_LANE_W) - $BLKD_BUS_ARROW_W - $BLKD_P2P_BUS_W)"/>
- </xsl:when>
- <xsl:otherwise><xsl:value-of select="($extSpaceWest_W_ + (@BUSLANE_X * $BLKD_BUS_LANE_W))"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:choose>
-<!--
- ===========================================================
- Handle Bucket connections to the shared busses.
- ===========================================================
--->
- <xsl:when test="@BUSLANE_X and @IS_BKTCONN and BUSCONN[@TYPE] and $G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/@BUS_INDEX">
- <xsl:call-template name="BCLaneSpace_BucketToSharedBus">
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBifType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/BUSINTERFACE/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- <xsl:with-param name="iSpaceSharedBus_Y" select="$spaceSharedBus_Y_"/>
- </xsl:call-template>
- </xsl:when>
-
-<!--
- ===========================================================
- Handle Processor's Shared bus connections.
- ===========================================================
--->
- <xsl:when test="@BUSLANE_X and @IS_SBSCONN and not(@IS_MPMCCONN) and BUSCONN[@BIF_Y and @IS_PROCCONN and @INSTANCE and @BUSINTERFACE] and $G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/@BUS_INDEX">
- <xsl:call-template name="BCLaneSpace_ProcBifToSharedBus">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBifType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/BUSINTERFACE/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- <xsl:with-param name="iSpaceSharedBus_Y" select="$spaceSharedBus_Y_"/>
- </xsl:call-template>
-<!--
--->
- </xsl:when>
-
-<!--
- ===========================================================
- Handle non Processor Shared Bus connections.
- ===========================================================
--->
- <xsl:when test="@BUSLANE_X and @IS_SBSCONN and not(@IS_MPMCCONN) and BUSCONN[@BIF_Y and not(@IS_PROCCONN) and @INSTANCE and @BUSINTERFACE] and /EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/@BUS_INDEX">
- <xsl:call-template name="BCLaneSpace_NonProcBifToSharedBus">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBifType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/BUSINTERFACE/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- <xsl:with-param name="iSpaceSharedBus_Y" select="$spaceSharedBus_Y_"/>
- </xsl:call-template>
-<!--
--->
- </xsl:when>
-
-<!--
- ===========================================================
- Handle connections from processors to Memory UNITs
- ===========================================================
--->
- <xsl:when test="@BUSLANE_X and @IS_MEMCONN and not(@IS_MULTISTK) and BUSCONN[@BIF_Y and @IS_PROCCONN and not(@IS_SPLITCONN) and @INSTANCE and @BUSINTERFACE]">
- <xsl:call-template name="BCLaneSpace_ProcBifToMemoryUnit">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- </xsl:call-template>
-<!--
--->
- </xsl:when>
-
-
-<!--
- ===========================================================
- Handle generic Point to Point connections
- ===========================================================
--->
- <xsl:when test="@BUSLANE_X and not(@IS_MULTISTK) and not(@IS_MPMCCONN) and not(@IS_MEMCONN) and not(@IS_SBSCONN) and BUSCONN[@BIF_Y and @INSTANCE and @BUSINTERFACE and not(@IS_SPLITCONN)]">
- <xsl:call-template name="BCLaneSpace_PointToPoint">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- </xsl:call-template>
-<!--
--->
- </xsl:when>
-
-<!--
- ===========================================================
- Handle MultiStack Point to Point connections
- ===========================================================
--->
- <xsl:when test="@BUSLANE_X and (@IS_MULTISTK) and not(@IS_SBSCONN) and BUSCONN[@BIF_Y and @IS_PROCCONN and @INSTANCE and @BUSINTERFACE]">
- <xsl:call-template name="BCLaneSpace_MultiStack_PointToPoint">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- </xsl:call-template>
- </xsl:when>
-
-<!--
- ===========================================================
- Handle Processor to processor connections
- ===========================================================
--->
- <xsl:when test="(@IS_PROC2PROC and (count(BUSCONN[@BIF_Y and @INSTANCE and @BUSINTERFACE]) = 2))">
- <xsl:call-template name="BCLaneSpace_ProcToProc">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- </xsl:call-template>
- </xsl:when>
-<!--
- ===========================================================
- Handle connections to the StandAlone MPMC
- ===========================================================
--->
- <xsl:when test="@BUSLANE_X and (@IS_MPMCCONN) and not(@IS_SBSCONN) and BUSCONN[(@BIF_Y and @INSTANCE and @BUSINTERFACE)]">
-<!--
--->
- <xsl:call-template name="BCLaneSpace_ToStandAloneMPMC">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- </xsl:call-template>
- </xsl:when>
-
-<!--
- ===========================================================
- Handle Split connections, (connections that go between non adjacent stacks)
- ===========================================================
--->
- <xsl:when test="(BUSCONN[@BIF_Y and @INSTANCE and @BUSINTERFACE and @IS_SPLITCONN])">
- <xsl:call-template name="BCLaneSpace_SplitConn">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBusName" select="$busName_"/>
- <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/>
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/>
- <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/>
- <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/>
- </xsl:call-template>
-<!--
--->
- </xsl:when>
-
- </xsl:choose>
-
- </xsl:for-each>
- </g>
-
-</xsl:template>
-
-<xsl:template name="Define_BusLaneSpaces">
-
- <xsl:variable name="lastStack_" select="(/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH) - 1"/>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[@EAST]">
- <xsl:sort select="@EAST" data-type="number"/>
-
- <xsl:call-template name="Define_BusLaneSpace">
- <xsl:with-param name="iStackToEast" select="@EAST"/>
- </xsl:call-template>
- </xsl:for-each>
-
-<!--
- <xsl:message>Last Stack <xsl:value-of select="$lastStack_"/></xsl:message>
--->
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@WEST = $lastStack_)]">
- <xsl:call-template name="Define_BusLaneSpace">
- <xsl:with-param name="iStackToWest" select="$lastStack_"/>
- </xsl:call-template>
- </xsl:for-each>
-
-</xsl:template>
-
-</xsl:stylesheet>
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
- <xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<!--
-<xsl:output method="xml"
- version="1.0"
- encoding="UTF-8"
- indent="yes"
- doctype-public="-//W3C//DTD SVG 1.0//EN"
- doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
--->
-
-<xsl:template name="Define_Busses">
-<!--
- <xsl:param name="drawarea_w" select="500"/>
- <xsl:param name="drawarea_h" select="500"/>
--->
-
- <xsl:for-each select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR">
-
- <xsl:call-template name="Define_BusArrowsEastWest">
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
-
- <xsl:call-template name="Define_BusArrowsNorthSouth">
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
-
- <xsl:call-template name="Define_SplitBusses">
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
- <xsl:call-template name="Define_SharedBus">
- <xsl:with-param name="iBusStd" select="'AXI'"/>
- </xsl:call-template>
-
- <xsl:call-template name="Define_SharedBus">
- <xsl:with-param name="iBusStd" select="'OPB'"/>
- </xsl:call-template>
-
- <xsl:call-template name="Define_SharedBus">
- <xsl:with-param name="iBusStd" select="'PLB'"/>
- </xsl:call-template>
-
- <xsl:call-template name="Define_SharedBus">
- <xsl:with-param name="iBusStd" select="'PLBV46'"/>
- </xsl:call-template>
-
- <xsl:call-template name="Define_SharedBus_Group"/>
-
-</xsl:template>
-
-<xsl:template name="Define_BusArrowsEastWest">
- <xsl:param name="iBusStd" select="'PLB'"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="busStdColor_lt_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <g id="{$iBusStd}_BusArrowEast">
- <path class="bus"
- d="M 0,0
- L {$BLKD_BUS_ARROW_W}, {ceiling($BLKD_BUS_ARROW_H div 2)}
- L 0,{$BLKD_BUS_ARROW_H},
- Z" style="stroke:none; fill:{$busStdColor_}"/>
- </g>
-
- <g id="{$iBusStd}_BusArrowWest">
- <use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowEast" transform="scale(-1,1) translate({$BLKD_BUS_ARROW_W * -1},0)"/>
- </g>
-
- <g id="{$iBusStd}_BusArrowHInitiator">
- <rect x="0"
- y="{$BLKD_BUS_ARROW_G}"
- width= "{$BLKD_BUS_ARROW_W}"
- height="{$BLKD_P2P_BUS_W}"
- style="stroke:none; fill:{$busStdColor_}"/>
- </g>
-
-</xsl:template>
-
-<!--
- <xsl:param name="bus_col" select="'OPB'"/>
--->
-
-<xsl:template name="Define_BusArrowsNorthSouth">
- <xsl:param name="iBusStd" select="'PLB'"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="busStdColor_lt_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <g id="{$iBusStd}_BusArrowSouth">
- <path class="bus"
- d="M 0,0
- L {$BLKD_BUS_ARROW_H},0
- L {ceiling($BLKD_BUS_ARROW_H div 2)}, {$BLKD_BUS_ARROW_W}
- Z" style="stroke:none; fill:{$busStdColor_}"/>
- </g>
-
- <g id="{$iBusStd}_BusArrowNorth">
- <use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowSouth" transform="scale(1,-1) translate(0,{$BLKD_BUS_ARROW_H * -1})"/>
- </g>
-
- <g id="{$iBusStd}_BusArrowInitiator">
- <rect x="{$BLKD_BUS_ARROW_G}"
- y="0"
- width= "{$BLKD_BUS_ARROW_W - ($BLKD_BUS_ARROW_G * 2)}"
- height="{$BLKD_BUS_ARROW_H}"
- style="stroke:none; fill:{$busStdColor_}"/>
- </g>
-
-</xsl:template>
-
-
-<xsl:template name="Draw_P2PBus">
-
- <xsl:param name="iBusX" select="0"/>
- <xsl:param name="iBusTop" select="0"/>
- <xsl:param name="iBusBot" select="0"/>
- <xsl:param name="iBusStd" select="'_bstd_'"/>
- <xsl:param name="iBusName" select="'_p2pbus_'"/>
- <xsl:param name="iBotBifType" select="'_unk_'"/>
- <xsl:param name="iTopBifType" select="'_unk_'"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:choose>
-
- <xsl:when test="@BUSSTD">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="not($iBusStd = '_bstd_')">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'TRS'"/>
- </xsl:call-template>
- </xsl:otherwise>
-
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="p2pH_" select="($iBusBot - $iBusTop) - ($BLKD_BUS_ARROW_H * 2)"/>
-
- <xsl:variable name="botArrow_">
- <xsl:choose>
- <xsl:when test="((($iBotBifType = 'INITIATOR') or ($iBotBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowInitiator</xsl:when>
- <xsl:otherwise>BusArrowSouth</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="topArrow_">
- <xsl:choose>
- <xsl:when test="((($iTopBifType = 'INITIATOR') or ($iTopBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowInitiator</xsl:when>
- <xsl:otherwise>BusArrowNorth</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="@BUSSTD">
- <use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}"
- y="{$iBusTop + ($BLKD_BIFC_H - $BLKD_BUS_ARROW_H) + $BLKD_BUS_ARROW_H}"
- xlink:href="#{@BUSSTD}_{$topArrow_}"/>
-
- <use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}"
- y="{$iBusBot - $BLKD_BUS_ARROW_H}"
- xlink:href="#{@BUSSTD}_{$botArrow_}"/>
- </xsl:if>
-
- <xsl:if test="(not(@BUSSTD) and not($iBusStd = '_bstd_'))">
- <use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}"
- y="{$iBusTop + ($BLKD_BIFC_H - $BLKD_BUS_ARROW_H) + $BLKD_BUS_ARROW_H}"
- xlink:href="#{$iBusStd}_{$topArrow_}"/>
-
- <use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}"
- y="{$iBusBot - $BLKD_BUS_ARROW_H}"
- xlink:href="#{$iBusStd}_{$botArrow_}"/>
- </xsl:if>
-
-
- <rect x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2) + $BLKD_BUS_ARROW_G}"
- y="{$iBusTop + $BLKD_BIFC_H + $BLKD_BUS_ARROW_H}"
- height= "{$p2pH_ - ($BLKD_BUS_ARROW_H * 2)}"
- width="{$BLKD_BUS_ARROW_W - ($BLKD_BUS_ARROW_G * 2)}"
- style="stroke:none; fill:{$busStdColor_}"/>
-
-<!--
- <text class="p2pbuslabel"
- x="{$iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4}"
- y="{$iBusTop + ($BLKD_BUS_ARROW_H * 3)}">
- <xsl:value-of select="$iBusName"/>
- </text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4)"/>
- <xsl:with-param name="iY" select="($iBusTop + ($BLKD_BUS_ARROW_H * 3))"/>
- <xsl:with-param name="iText" select="$iBusName"/>
- <xsl:with-param name="iClass" select="'p2pbus_label'"/>
- </xsl:call-template>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP">
-<!--
- <text class="ioplblgrp"
- x="{$iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}"
- y="{$iBusTop + ($BLKD_BUS_ARROW_H * 10)}">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/>
- <xsl:with-param name="iY" select="($iBusTop + ($BLKD_BUS_ARROW_H * 10))"/>
- <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP"/>
- <xsl:with-param name="iClass" select="'iogrp_label'"/>
- </xsl:call-template>
-
- </xsl:if>
-
-</xsl:template>
-
-
-<xsl:template name="Draw_Proc2ProcBus">
-
- <xsl:param name="iBc_Y" select="0"/>
- <xsl:param name="iBusStd" select="'_bstd_'"/>
- <xsl:param name="iBusName" select="'_p2pbus_'"/>
- <xsl:param name="iBcLeft_X" select="0"/>
- <xsl:param name="iBcRght_X" select="0"/>
- <xsl:param name="iLeftBifType" select="'_unk_'"/>
- <xsl:param name="iRghtBifType" select="'_unk_'"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="pr2pr_W_" select="($iBcRght_X - $iBcLeft_X)"/>
-
- <xsl:variable name="leftArrow_">
- <xsl:choose>
- <xsl:when test="((($iLeftBifType = 'INITIATOR') or ($iLeftBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when>
- <xsl:otherwise>BusArrowWest</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="rghtArrow_">
- <xsl:choose>
- <xsl:when test="((($iRghtBifType = 'INITIATOR') or ($iRghtBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when>
- <xsl:otherwise>BusArrowEast</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="bus_Y_" select="($iBc_Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2))"/>
-
- <use x="{$iBcLeft_X}" y="{$bus_Y_}" xlink:href="#{$iBusStd}_{$leftArrow_}"/>
- <use x="{$iBcRght_X - $BLKD_BUS_ARROW_W}" y="{$bus_Y_}" xlink:href="#{$iBusStd}_{$rghtArrow_}"/>
-
- <rect x="{$iBcLeft_X + $BLKD_BUS_ARROW_W}"
- y="{$bus_Y_ + $BLKD_BUS_ARROW_G}"
- width= "{$pr2pr_W_ - (2 * $BLKD_BUS_ARROW_W)}"
- height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/>
-
-<!--
- <text class="horizp2pbuslabel"
- x="{$iBcLeft_X + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4}"
- y="{($bus_Y_)}"><xsl:value-of select="$iBusName"/></text>
-
- <text class="horizp2pbuslabel"
- x="{$iBcRght_X - (string-length($iBusName) * 8)}"
- y="{($bus_Y_)}"><xsl:value-of select="$iBusName"/></text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($iBcLeft_X + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4)"/>
- <xsl:with-param name="iY" select="$bus_Y_"/>
- <xsl:with-param name="iText" select="$iBusName"/>
- <xsl:with-param name="iClass" select="'p2pbus_label'"/>
- </xsl:call-template>
-
-<!--
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(iBcRght_X - (string-length($iBusName) * 8))"/>
- <xsl:with-param name="iY" select="$bus_Y_"/>
- <xsl:with-param name="iText" select="$iBusName"/>
- <xsl:with-param name="iClass" select="'p2pbus_label'"/>
- </xsl:call-template>
-
--->
-
-</xsl:template>
-
-
-<xsl:template name="Draw_SplitConnBus">
-
- <xsl:param name="iBc_X" select="0"/>
- <xsl:param name="iBc_Y" select="0"/>
- <xsl:param name="iBc_Type" select="'_unk_'"/>
- <xsl:param name="iBc_Side" select="'_unk_'"/>
- <xsl:param name="iBusStd" select="'_bstd_'"/>
- <xsl:param name="iBusName" select="'_p2pbus_'"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="connArrow_">
- <xsl:choose>
- <xsl:when test="((($iBc_Type = 'INITIATOR') or ($iBc_Type = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when>
- <xsl:otherwise>BusArrowEast</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="arrow_Y_" select="($iBc_Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2))"/>
-
- <xsl:variable name="bus_X_">
- <xsl:choose>
- <xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($iBc_X - ($BLKD_BUS_ARROW_W * 2))"/></xsl:when>
- <xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($iBc_X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/></xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$busStd}_BusArrowHInitiator"/>
--->
-
- <xsl:variable name="arrow_X_">
- <xsl:choose>
- <xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($iBc_X - $BLKD_BUS_ARROW_W)"/></xsl:when>
- <xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($iBc_X + $BLKD_BIFC_W)"/></xsl:when>
- </xsl:choose>
- </xsl:variable>
- <xsl:choose>
- <xsl:when test="(($iBusStd = 'FSL') and (($iBc_Type = 'MASTER') or ($iBc_Type = 'INITIATOR')))">
- <use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_{$connArrow_}"/>
- <use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_BusArrowHInitiator"/>
- </xsl:when>
- <xsl:when test="(($iBc_Side = '1') and not($iBusStd = 'FSL') and (($iBc_Type = 'MASTER') or ($iBc_Type = 'INITIATOR')))">
- <use x="{$arrow_X_ - $BLKD_BIFC_W}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_SplitBus_WEST"/>
- </xsl:when>
- <xsl:when test="(($iBc_Side = '1') and (($iBc_Type = 'SLAVE') or ($iBc_Type = 'TARGET') or ($iBc_Type = 'USER')))">
- <use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_SplitBus_EAST"/>
- </xsl:when>
- <xsl:otherwise>
- <use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_{$connArrow_}"/>
- <use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_BusArrowHInitiator"/>
- </xsl:otherwise>
- </xsl:choose>
-
- <xsl:variable name="text_X_">
- <xsl:choose>
- <xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($bus_X_ - $BLKD_BUS_ARROW_W - (string-length($iBusName) * 5))"/></xsl:when>
- <xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($bus_X_ + $BLKD_BUS_ARROW_W)"/></xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
-<!--
- <text class="horizp2pbuslabel"
- x="{$text_X_}"
- y="{($arrow_Y_)}">
- <xsl:value-of select="$iBusName"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="$text_X_"/>
- <xsl:with-param name="iY" select="$arrow_Y_"/>
- <xsl:with-param name="iText" select="$iBusName"/>
- <xsl:with-param name="iClass" select="'p2pbus_label'"/>
- </xsl:call-template>
-
-</xsl:template>
-
-
-<xsl:template name="Define_SharedBus">
-
- <xsl:param name="iBusStd" select="'PLB46'"/>
-
- <xsl:variable name="sharedbus_w_" select="($G_Total_DrawArea_W - ($BLKD_INNER_GAP * 2))"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="busStdColor_lt_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <g id="{$iBusStd}_SharedBus">
- <use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowWest"/>
- <use x="{$sharedbus_w_ - $BLKD_BUS_ARROW_W}" y="0" xlink:href="#{$iBusStd}_BusArrowEast"/>
-
- <rect x="{$BLKD_BUS_ARROW_W}"
- y="{$BLKD_BUS_ARROW_G}"
- width= "{$sharedbus_w_ - ($BLKD_BUS_ARROW_W * 2)}"
- height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/>
- </g>
-</xsl:template>
-
-
-<xsl:template name="Define_SplitBusses">
-
- <xsl:param name="iBusStd" select="'FSL'"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="bifc_r_" select="ceiling($BLKD_BIFC_W div 3)"/>
-
- <g id="{$iBusStd}_SplitBus_EAST">
- <use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowWest"/>
-
- <rect x="{$BLKD_BUS_ARROW_W}"
- y="{$BLKD_BUS_ARROW_G}"
- width= "{$BLKD_BIFC_W}"
- height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/>
-
- </g>
-
- <xsl:variable name="splbus_w_" select="($BLKD_BUS_ARROW_W + $BLKD_BIFC_W + $BLKD_BIFC_Wi)"/>
-
- <g id="{$iBusStd}_SplitBus_WEST">
- <use x="0" y="0" xlink:href="#{$iBusStd}_SplitBus_EAST" transform="scale(-1,1) translate({$splbus_w_ * -1},0)"/>
- </g>
-
- <g id="{$iBusStd}_SplitBus_OneWay">
-
- <rect x="0"
- y="{$BLKD_BUS_ARROW_G}"
- width= "{($BLKD_BUS_ARROW_W * 2)}"
- height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/>
-
- <rect x="{($BLKD_BUS_ARROW_W * 2)}"
- y="0"
- width= "{$BLKD_BUS_ARROW_H}"
- height="{$BLKD_BUS_ARROW_H}" style="stroke:none; fill:{$busStdColor_}"/>
-
- </g>
-</xsl:template>
-
-
-<xsl:template name="Define_SharedBus_Group">
-
-<!-- The Bridges go into the shared bus shape -->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE">
-
- <xsl:variable name="modInst_" select="@INSTANCE"/>
- <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/>
-
- <xsl:call-template name="Define_Peripheral">
- <xsl:with-param name="iModVori" select="'normal'"/>
- <xsl:with-param name="iModInst" select="$modInst_"/>
- <xsl:with-param name="iModType" select="$modType_"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
-<g id="group_sharedBusses">
-
- <!-- Draw the shared bus shapes first -->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE">
- <xsl:variable name="instance_" select="@INSTANCE"/>
-
- <xsl:variable name="busStd_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $instance_)]/@BUSSTD"/>
- <xsl:variable name="busIndex_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $instance_)]/@BUS_INDEX"/>
-
- <xsl:variable name="busY_" select="($busIndex_ * $BLKD_SBS_LANE_H)"/>
-
- <use x="0" y="{$busY_}" xlink:href="#{$busStd_}_SharedBus"/>
-
-<!--
- <text class="sharedbuslabel"
- x="8"
- y="{$busY_ + $BLKD_BUS_ARROW_H + 10}">
- <xsl:value-of select="$instance_"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'8'"/>
- <xsl:with-param name="iY" select="($busY_ + $BLKD_BUS_ARROW_H + 10)"/>
- <xsl:with-param name="iText" select="$instance_"/>
- <xsl:with-param name="iClass" select="'sharedbus_label'"/>
- </xsl:call-template>
- </xsl:for-each>
-
-</g>
-
-<g id="KEY_SharedBus">
- <use x="0" y="0" xlink:href="#KEY_BusArrowWest"/>
- <use x="30" y="0" xlink:href="#KEY_BusArrowEast"/>
-
- <xsl:variable name="key_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'KEY'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect x="{$BLKD_BUS_ARROW_W}"
- y="{$BLKD_BUS_ARROW_G}"
- width= "{30 - $BLKD_BUS_ARROW_W}"
- height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$key_col_}"/>
-</g>
-
-</xsl:template>
-
-</xsl:stylesheet>
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- extension-element-prefixes="math dyn exsl xlink">
-<!--
-xmlns:svg="http://www.w3.org/2000/svg"
-<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
- doctype-public="-//W3C//DTD SVG 1.0//EN"
- doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
--->
-
-<xsl:template name="F_Calc_Proc_Height">
- <xsl:param name="iProcInst" select="_processor_"/>
-
- <xsl:variable name="tot_bifs_h_">
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iProcInst)]/@BIFS_H)">0</xsl:if>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iProcInst)]/@BIFS_H">
- <xsl:variable name="bifs_h_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iProcInst)]/@BIFS_H)"/>
- <xsl:value-of select="(($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_H) * $bifs_h_)"/>
- </xsl:if>
- </xsl:variable>
-
- <xsl:value-of select="(($BLKD_MOD_LANE_H * 2) + $tot_bifs_h_ + ($BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_H))"/>
-</xsl:template>
-
-<xsl:template name="F_Calc_Max_Proc_Height">
-
- <!-- Store the heights in a variable -->
- <xsl:variable name="proc_heights_">
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE)">
- <PROC HEIGHT="0"/>
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE">
- <xsl:variable name="procInst_" select="@INSTANCE"/>
- <xsl:variable name="proc_height_">
- <xsl:call-template name="F_Calc_Proc_Height">
- <xsl:with-param name="iProcInst" select="$procInst_"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Found Proc height as <xsl:value-of select="$proc_height_"/></xsl:message>
--->
- <PROC HEIGHT="{$proc_height_}"/>
- </xsl:for-each>
- </xsl:variable>
-
- <!-- Return the max of them -->
-<!--
- <xsl:message>Found Proc ax as <xsl:value-of select="math:max(exsl:node-set($proc_heights_)/PROC/@HEIGHT)"/></xsl:message>
--->
-
- <xsl:value-of select="math:max(exsl:node-set($proc_heights_)/PROC/@HEIGHT)"/>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Proc_MemoryUnits_Height">
- <xsl:param name="iProcInst" select="_processor_"/>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and (@MODCLASS = 'MEMORY_UNIT'))])">0</xsl:if>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and (@MODCLASS='MEMORY_UNIT'))]">
-
- <xsl:variable name="peri_gap_">
- <xsl:choose>
- <xsl:when test="not(@CSTACK_INDEX)">
- <xsl:value-of select="$BLKD_BIF_H"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <!-- Store the all memory unit heights in a variable -->
- <xsl:variable name="memU_heights_">
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and (@MODCLASS='MEMORY_UNIT'))]">
-<!--
- <xsl:variable name="unitId_" select="@PSTACK_MODS_Y"/>
--->
- <xsl:variable name="unitHeight_">
- <xsl:call-template name="F_Calc_MemoryUnit_Height">
- <xsl:with-param name="iShapeId" select="@SHAPE_ID"/>
- </xsl:call-template>
- </xsl:variable>
-
- <MEM_UNIT HEIGHT="{$unitHeight_ + $peri_gap_}"/>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:value-of select="sum(exsl:node-set($memU_heights_)/MEM_UNIT/@HEIGHT)"/>
- </xsl:if>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Proc_Peripherals_Height">
- <xsl:param name="iProcInst" select="_processor_"/>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and not(@MODCLASS = 'MEMORY_UNIT'))])">0</xsl:if>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and not(@MODCLASS='MEMORY_UNIT'))]">
-
- <xsl:variable name="peri_gap_">
- <xsl:if test="@CSTACK_INDEX">
- <xsl:value-of select="$BLKD_BIF_H"/>
- </xsl:if>
- <xsl:if test="not(@IS_CSTACK)">0</xsl:if>
- </xsl:variable>
-
- <!-- Store the all peripheral heights in a variable -->
- <xsl:variable name="peri_heights_">
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and not(@MODCLASS='MEMORY_UNIT'))]">
- <xsl:for-each select="MODULE">
-<!--
- <xsl:message><xsl:value-of select="@INSTANCE"/></xsl:message>
--->
- <xsl:variable name="peri_height_">
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="@INSTANCE"/>
- </xsl:call-template>
- </xsl:variable>
- <PERI HEIGHT="{$peri_height_ + $peri_gap_}"/>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:value-of select="sum(exsl:node-set($peri_heights_)/PERI/@HEIGHT)"/>
- </xsl:if>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Space_AbvSbs_Height">
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
-
-
- <xsl:variable name = "stackAbvSbs_West_H_">
- <xsl:choose>
- <xsl:when test="(($iStackToEast = '0') and ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="(($iStackToEast = 'NONE') and not($iStackToWest = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:when test="(not($iStackToEast = '0') and ($iStackToWest = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="($iStackToEast - 1)"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name = "stackAbvSbs_East_H_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackAbvSbs_heights_">
- <STACK HEIGHT="{$stackAbvSbs_East_H_}"/>
- <STACK HEIGHT="{$stackAbvSbs_West_H_}"/>
- </xsl:variable>
-
- <xsl:value-of select="math:max(exsl:node-set($stackAbvSbs_heights_)/STACK/@HEIGHT)"/>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Space_BlwSbs_Height">
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
-
- <xsl:variable name = "stackBlwSbs_West_H_">
- <xsl:choose>
- <xsl:when test="(($iStackToEast = '0') and ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="(($iStackToEast = 'NONE') and not($iStackToWest = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_BlwSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:when test="(not($iStackToEast = '0') and ($iStackToWest = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_BlwSbs_Height">
- <xsl:with-param name="iStackIdx" select="($iStackToEast - 1)"/>
- </xsl:call-template>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name = "stackBlwSbs_East_H_">
- <xsl:call-template name="F_Calc_Stack_BlwSbs_Height">
- <xsl:with-param name="iStackIdx" select="$iStackToEast"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stackBlwSbs_heights_">
- <STACK HEIGHT="{$stackBlwSbs_East_H_}"/>
- <STACK HEIGHT="{$stackBlwSbs_West_H_}"/>
- </xsl:variable>
-
- <xsl:value-of select="math:max(exsl:node-set($stackBlwSbs_heights_)/STACK/@HEIGHT)"/>
-</xsl:template>
-
-
-
-<xsl:template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:param name="iStackIdx" select="100"/>
-<!--
- <xsl:message>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^</xsl:message>
--->
-
- <xsl:if test="(not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_ABVSBS))]) and
- not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $iStackIdx)]))"><xsl:value-of select="$BLKD_PROC2SBS_GAP"/></xsl:if>
-
- <xsl:if test="(($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_ABVSBS))]) or
- ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[ (@STACK_HORIZ_INDEX = $iStackIdx)]))">
-
-<!--
- <xsl:variable name="peri_gap_">
- <xsl:value-of select="$BLKD_BIF_H"/>
- <xsl:choose>
- <xsl:when test="(@SHAPE_VERTI_INDEX)">
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
--->
-
-<!--
- <xsl:message>The gap is <xsl:value-of select="$peri_gap_"/></xsl:message>
- <xsl:message>The gap is <xsl:value-of select="$peri_gap_"/></xsl:message>
- <xsl:message>================================</xsl:message>
- <xsl:message>================================</xsl:message>
- <xsl:message>This is above <xsl:value-of select="@INSTANCE"/></xsl:message>
- <xsl:message><xsl:value-of select="@INSTANCE"/> : <xsl:value-of select="$peri_height_"/></xsl:message>
--->
-
-
- <!-- Store the all peripheral heights in a variable -->
- <xsl:variable name="peri_heights_">
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and not(@MODCLASS = 'MEMORY_UNIT') and (@IS_ABVSBS))]">
- <xsl:for-each select="MODULE">
-<!--
- <xsl:message>This is above <xsl:value-of select="@INSTANCE"/></xsl:message>
--->
-
- <xsl:variable name="peri_height_">
-<!--
- <xsl:call-template name="F_Calc_Shape_Height">
- <xsl:with-param name="shapeId" select="@SHAPE_ID"/>
- </xsl:call-template>
--->
-
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="@INSTANCE"/>
- </xsl:call-template>
- </xsl:variable>
-
- <PERI HEIGHT="{$peri_height_ + $BLKD_BIF_H}"/>
- </xsl:for-each>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@MODCLASS = 'MEMORY_UNIT') and (@IS_ABVSBS))]">
-
- <xsl:variable name="memu_height_">
- <xsl:call-template name="F_Calc_MemoryUnit_Height">
- <xsl:with-param name="iShapeId" select="@SHAPE_ID"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Mem_Unit : <xsl:value-of select="@SHAPE_ID"/> : <xsl:value-of select="$memu_height_ + $peri_gap_"/></xsl:message>
--->
- <PERI HEIGHT="{$memu_height_ + $BLKD_BIF_H}"/>
-
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_ABVSBS))]">
-
- <xsl:variable name="proc_height_">
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="@INSTANCE"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>===================================</xsl:message>
- <xsl:message>Processor : <xsl:value-of select="@INSTANCE"/> : <xsl:value-of select="$peri_height_ + $peri_gap_"/></xsl:message>
- <PERI HEIGHT="{$proc_height_ + $BLKD_PROC2SBS_GAP }"/>
--->
- <PERI HEIGHT="{$proc_height_ + $BLKD_BIF_H}"/>
-
- </xsl:for-each>
-
- </xsl:variable>
-
-<!--
- <xsl:message><xsl:value-of select="@INSTANCE"/> : <xsl:value-of select="$peri_height_ + $peri_gap_"/></xsl:message>
- <xsl:message>================================</xsl:message>
--->
-
-<!--
- <xsl:message>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^</xsl:message>
--->
- <xsl:value-of select="sum(exsl:node-set($peri_heights_)/PERI/@HEIGHT)"/>
- </xsl:if>
-
-</xsl:template>
-
-<xsl:template name="F_Calc_Stack_BlwSbs_Height">
- <xsl:param name="iStackIdx" select="100"/>
-
- <!-- Store the all peripheral heights in a variable -->
- <xsl:variable name="stack_heights_">
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_BLWSBS))])">
- <STACKSHAPE HEIGHT="0"/>
- </xsl:if>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_BLWSBS))]">
-
- <xsl:variable name="peri_gap_">
- <xsl:choose>
- <xsl:when test="(@SHAPE_VERTI_INDEX)">
- <xsl:value-of select="$BLKD_BIF_H"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and not(@MODCLASS = 'MEMORY_UNIT') and (@IS_BLWSBS))]">
- <xsl:for-each select="MODULE">
-<!--
- <xsl:message>This is below <xsl:value-of select="@INSTANCE"/></xsl:message>
--->
- <xsl:variable name="peri_height_">
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="@INSTANCE"/>
- </xsl:call-template>
- </xsl:variable>
-
- <STACKSHAPE HEIGHT="{$peri_height_ + $peri_gap_}"/>
- </xsl:for-each>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@MODCLASS = 'MEMORY_UNIT') and (@IS_BLWSBS))]">
-
- <xsl:variable name="memu_height_">
- <xsl:call-template name="F_Calc_MemoryUnit_Height">
- <xsl:with-param name="iShapeId" select="@SHAPE_ID"/>
- </xsl:call-template>
- </xsl:variable>
-
- <STACKSHAPE HEIGHT="{$memu_height_ + $peri_gap_}"/>
-
-<!--
- <xsl:message>Mem_Unit : <xsl:value-of select="@SHAPE_ID"/> : <xsl:value-of select="$memu_height_ + $peri_gap_"/></xsl:message>
--->
-
- </xsl:for-each>
- </xsl:if>
-
- <xsl:variable name="sbsBuckets_H_">
- <xsl:call-template name="F_Calc_Stack_SbsBuckets_Height">
- <xsl:with-param name="iStackIdx" select="$iStackIdx"/>
- </xsl:call-template>
- </xsl:variable>
-
- <STACKSHAPE HEIGHT="{$sbsBuckets_H_}"/>
-<!--
- <xsl:message>Sbs Bucket H : <xsl:value-of select="$sbsBuckets_H_"/></xsl:message>
--->
- </xsl:variable>
-
-<!--
- <xsl:message>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv</xsl:message>
--->
- <xsl:value-of select="sum(exsl:node-set($stack_heights_)/STACKSHAPE/@HEIGHT)"/>
-
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Stack_SbsBuckets_Height">
- <xsl:param name="iStackIdx" select="1000"/>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)])">0</xsl:if>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]">
-
- <!-- Store the all buckets heights in a variable -->
- <xsl:variable name="bkt_heights_">
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]">
-
- <xsl:variable name="bkt_height_">
- <xsl:call-template name="F_Calc_SbsBucket_Height">
- <xsl:with-param name="iBucketId" select="@BUS_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-<!--
- <xsl:message>Found shared buckets height as <xsl:value-of select="$bkt_height_"/></xsl:message>
--->
- <BKT HEIGHT="{$bkt_height_ + $BLKD_BIF_H}"/>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:value-of select="sum(exsl:node-set($bkt_heights_)/BKT/@HEIGHT)"/>
- </xsl:if>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Max_Stack_BlwSbs_Height">
-
- <!-- Store the heights in a variable -->
- <xsl:variable name="blwSbs_heights_">
-
- <!-- Default, in case there are no modules or ports -->
- <BLW HEIGHT="0"/>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST < $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]">
-
-<!--
- <xsl:message>Found a space of index <xsl:value-of select="@EAST"/></xsl:message>
--->
-
- <xsl:variable name="stack_height_">
- <xsl:call-template name="F_Calc_Stack_BlwSbs_Height">
- <xsl:with-param name="iStackIdx" select="@EAST"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <BLW HEIGHT="{$stack_height_}"/>
-
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@WEST = ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH -1))]">
-
-<!--
- <xsl:message>Last stack of index <xsl:value-of select="@WEST"/></xsl:message>
--->
-
- <xsl:variable name="stack_height_">
- <xsl:call-template name="F_Calc_Stack_BlwSbs_Height">
- <xsl:with-param name="iStackIdx" select="@WEST"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <BLW HEIGHT="{$stack_height_}"/>
-
- </xsl:for-each>
-
-
- </xsl:variable>
-
-<!--
- <xsl:message>Found Blw Sbs max as <xsl:value-of select="math:max(exsl:node-set($blwSbs_heights_)/BLW/@HEIGHT)"/></xsl:message>
--->
- <!-- Return the max of them -->
- <xsl:value-of select="math:max(exsl:node-set($blwSbs_heights_)/BLW/@HEIGHT)"/>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Max_Stack_AbvSbs_Height">
-
- <!-- Store the heights in a variable -->
- <xsl:variable name="abvSbs_heights_">
-
- <!-- Default, in case there are no modules or ports -->
- <ABV HEIGHT="0"/>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST < $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]">
-
-<!--
- <xsl:message>Found a space of index <xsl:value-of select="@EAST"/></xsl:message>
--->
-
- <xsl:variable name="stack_height_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="@EAST"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Found stack of width <xsl:value-of select="$stack_width_"/></xsl:message>
- <xsl:message>==============================</xsl:message>
--->
-
- <ABV HEIGHT="{$stack_height_}"/>
-
- </xsl:for-each>
-
-
- </xsl:variable>
-
-<!--
- <xsl:message>Found Blw Sbs max as <xsl:value-of select="math:max(exsl:node-set($blwSbs_heights_)/BLW/@HEIGHT)"/></xsl:message>
--->
- <!-- Return the max of them -->
- <xsl:value-of select="math:max(exsl:node-set($abvSbs_heights_)/ABV/@HEIGHT)"/>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_MultiProc_Stack_Height">
- <xsl:param name="iMPStack_Blkd_X" select="100"/>
-
- <xsl:variable name="mpStk_ShpHeights_">
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@HAS_MULTIPROCCONNS) and (@PSTACK_BLKD_X = $iMPStack_Blkd_X))])">
- <MPSHAPE HEIGHT="0"/>
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@HAS_MULTIPROCCONNS) and (@PSTACK_BLKD_X = $iMPStack_Blkd_X))]">
- <xsl:variable name="shpClass_" select="@MODCLASS"/>
- <xsl:variable name="shpHeight_">
- <xsl:choose>
- <xsl:when test="$shpClass_ = 'PERIPHERAL'">
-<!--
- <xsl:message>Found Multi Proc Peripheral</xsl:message>
--->
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="MODULE/@INSTANCE"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:when test="$shpClass_ = 'MEMORY_UNIT'">
-<!--
- <xsl:message>Found Multi Proc Memory Unit</xsl:message>
--->
- <xsl:call-template name="F_Calc_MemoryUnit_Height">
- <xsl:with-param name="iShapeIndex" select="@CSHAPE_INDEX"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>Found <xsl:value-of select="$shpHeight_"/></xsl:message>
--->
-
- <MPSHAPE HEIGHT="{$shpHeight_}"/>
- </xsl:for-each>
- </xsl:variable>
-
-<!--
- <xsl:message>Found stack of height <xsl:value-of select="sum(exsl:node-set($mpStk_ShpHeights_)/MPSHAPE/@HEIGHT)"/></xsl:message>
--->
-
- <xsl:value-of select="sum(exsl:node-set($mpStk_ShpHeights_)/MPSHAPE/@HEIGHT)"/>
-</xsl:template>
-
-<xsl:template name="F_Calc_Max_MultiProc_Stack_Height">
-
- <!-- Store the heights in a variable -->
-
- <xsl:variable name="mpStks_Heights_">
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE)">
- <MPSTK HEIGHT="0"/>
- </xsl:if>
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@PSTACK_BLKD_X)]">
- <xsl:variable name="mpstack_height_">
- <xsl:call-template name="F_Calc_MultiProc_Stack_Height">
- <xsl:with-param name="iMPStack_Blkd_X" select="(@PSTACK_BLKD_X + 1)"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Found <xsl:value-of select="$mpstack_height_"/></xsl:message>
--->
- <MPSTK HEIGHT="{$mpstack_height_}"/>
- </xsl:for-each>
-
- </xsl:variable>
-
- <!-- Return the max of them -->
- <xsl:value-of select="math:max(exsl:node-set($mpStks_Heights_)/MPSTK/@HEIGHT)"/>
-
-</xsl:template>
-
-
-
-<xsl:template name="F_Calc_Stack_Shape_Y">
-
- <xsl:param name="iHorizIdx" select="100"/>
- <xsl:param name="iVertiIdx" select="100"/>
-
-
-<!--
- <xsl:param name="sbsGap" select="0"/>
- <xsl:variable name="numSBSs_" select="count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE)"/>
- <xsl:variable name="sbs_LANE_H_" select="($numSBSs_ * $BLKD_SBS_LANE_H)"/>
- <xsl:variable name="sbsGap_" select="($BLKD_PROC2SBS_GAP + $sbs_LANE_H_)"/>
--->
-
- <xsl:variable name="sbsGap_" select="((count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE) * $BLKD_SBS_LANE_H) + $BLKD_PROC2SBS_GAP)"/>
-
- <xsl:if test="(not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) and
- not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) and
- not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]))">0</xsl:if>
-
-
-<!--
- <xsl:if test="(not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) and
- not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) and
- not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]))">
- <xsl:message>Something is missing </xsl:message>
- </xsl:if>
--->
-
- <xsl:if test="(($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) or
- ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) or
- ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]))">
- <!-- Store the spaces above this one in a variable -->
- <xsl:variable name="spaces_above_">
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX < $iVertiIdx))])">
- <SPACE HEIGHT="0"/>
- </xsl:if>
-
- <!-- Store the height of all peripherals and memory units above this one-->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX < $iVertiIdx))]">
-
- <xsl:if test="not(@MODCLASS='MEMORY_UNIT')">
- <xsl:variable name="peri_height_">
- <xsl:call-template name="F_Calc_Shape_Height">
- <xsl:with-param name="iShapeId" select="@SHAPE_ID"/>
- </xsl:call-template>
- </xsl:variable>
-<!--
- <xsl:message>Found peri height <xsl:value-of select="$peri_height_"/></xsl:message>
--->
- <SPACE HEIGHT="{$peri_height_ + $BLKD_BIF_H}"/>
- </xsl:if>
-
- <xsl:if test="(@MODCLASS='MEMORY_UNIT')">
- <xsl:variable name="memu_height_">
- <xsl:call-template name="F_Calc_MemoryUnit_Height">
- <xsl:with-param name="iShapeId" select="@SHAPE_ID"/>
- </xsl:call-template>
- </xsl:variable>
-<!--
- <xsl:message>Found unit height <xsl:value-of select="$memu_height_"/></xsl:message>
--->
- <SPACE HEIGHT="{$memu_height_ + $BLKD_BIF_H}"/>
- </xsl:if>
-
- </xsl:for-each>
-
- <!-- Store the height of all the processors above this one-->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX < $iVertiIdx))]">
- <xsl:variable name="proc_height_">
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="@INSTANCE"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Found Proc height <xsl:value-of select="$proc_height_ + $BLKD_BIF_H"/></xsl:message>
--->
- <SPACE HEIGHT="{$proc_height_ + $BLKD_BIF_H}"/>
- </xsl:for-each>
-
- <!-- If its a peripheral that is below the shared busses, or its a shared bus bucket -->
- <!-- add the height of the shared busses and the processor. -->
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX = $iVertiIdx))]/@IS_BLWSBS)">
- <SPACE HEIGHT="{$sbsGap_}"/>
- </xsl:if>
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX = $iVertiIdx))])">
- <SPACE HEIGHT="{$sbsGap_}"/>
- </xsl:if>
-
- <!-- Store the height of all shared bus buckets above this one-->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX < $iVertiIdx))]">
- <xsl:variable name="bkt_height_">
- <xsl:call-template name="F_Calc_SbsBucket_Height">
- <xsl:with-param name="iBucketId" select="@BUS_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Found bucket height <xsl:value-of select="$bkt_height_ + $BLKD_BIF_H"/></xsl:message>
--->
-
- <SPACE HEIGHT="{$bkt_height_ + $BLKD_BIF_H}"/>
- </xsl:for-each>
-
- </xsl:variable>
-
- <xsl:value-of select="sum(exsl:node-set($spaces_above_)/SPACE/@HEIGHT)"/>
- </xsl:if>
-
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Max_BusConnLane_BifY">
-
- <xsl:param name="iBusName" select="'_busname_'"/>
-
- <!-- Store the heights in a variable -->
- <xsl:variable name="busConnYs_">
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/BUSCONNS/BUSCONNLANE/BUSCONN)">
- <BUSCONNY HEIGHT="0"/>
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/BUSCONNS/BUSCONNLANE[(@BUSNAME = $iBusName)]/BUSCONN">
-
- <xsl:variable name="peri_cstk_y_">
- <xsl:call-template name="F_Calc_CStackShapesAbv_Height">
- <xsl:with-param name="iCStackIndex" select="../@CSTACK_INDEX"/>
- <xsl:with-param name="ICStackModY" select="@CSTACK_MODS_Y"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="peri_bif_dy_">
- <xsl:value-of select="(($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_H) * @BIF_Y)"/>
- </xsl:variable>
-
- <xsl:variable name="peri_bc_y_">
- <xsl:value-of select="($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_H + $peri_bif_dy_ + ceiling($BLKD_BIF_H div 2)) - ceiling($BLKD_BIFC_H div 2)"/>
- </xsl:variable>
-
-<!--
- <xsl:message>Found a busconn lane</xsl:message>
--->
- <BUSCONNY HEIGHT="{$peri_cstk_y_ + $peri_bif_dy_ + $peri_bc_y_}"/>
- </xsl:for-each>
-
- </xsl:variable>
-
- <!-- Return the max of them -->
- <xsl:value-of select="math:max(exsl:node-set($busConnYs_)/BUSCONNY/@HEIGHT)"/>
-
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Min_BusConnLane_BifY">
-
- <xsl:param name="iBusName" select="'_busname_'"/>
-
- <!-- Store the heights in a variable -->
- <xsl:variable name="busConnYs_">
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/BUSCONNS/BUSCONNLANE/BUSCONN)">
- <BUSCONNY HEIGHT="0"/>
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/BUSCONNS/BUSCONNLANE[(@BUSNAME = $iBusName)]/BUSCONN">
-
- <xsl:variable name="peri_cstk_y_">
- <xsl:call-template name="F_Calc_CStackShapesAbv_Height">
- <xsl:with-param name="iCStackIndex" select="../@CSTACK_INDEX"/>
- <xsl:with-param name="iCStackModY" select="@CSTACK_MODS_Y"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="peri_bif_dy_">
- <xsl:value-of select="(($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_H) * @BIF_Y)"/>
- </xsl:variable>
-
- <xsl:variable name="peri_bc_y_">
- <xsl:value-of select="($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_H + $peri_bif_dy_ + ceiling($BLKD_BIF_H div 2)) - ceiling($BLKD_BIFC_H div 2)"/>
- </xsl:variable>
-
-<!--
- <xsl:message>Found a busconn lane</xsl:message>
--->
- <BUSCONNY HEIGHT="{$peri_cstk_y_ + $peri_bc_y_}"/>
- </xsl:for-each>
-
- </xsl:variable>
-
- <!-- Return the min of them -->
- <xsl:value-of select="math:min(exsl:node-set($busConnYs_)/BUSCONNY/@HEIGHT)"/>
-
-</xsl:template>
-
-<xsl:template name="F_Calc_Stack_Height">
- <xsl:param name="iStackIdx" select="100"/>
-
-<!--
- <xsl:message>Calculating height for Stack Index <xsl:value-of select="$iStackIdx"/></xsl:message>
--->
-
-
- <xsl:variable name="stack_height_">
- <!-- if this is called with no vert index of a shape
- it defaults to the total height of the stack -->
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="$iStackIdx"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Calculated height for Stack as <xsl:value-of select="$stack_height_"/></xsl:message>
--->
- <xsl:value-of select="$stack_height_"/>
-</xsl:template>
-
-<!--
--->
-
-
-<xsl:template name="F_Calc_Stack_Width">
- <xsl:param name="iStackIdx" select="100"/>
-
-<!--
- <xsl:message>=============Stack Idx <xsl:value-of select="$iStackIdx"/>====</xsl:message>
--->
- <xsl:variable name="shape_widths_">
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[@STACK_HORIZ_INDEX = $iStackIdx])">
- <SHAPE WIDTH="0"/>
- </xsl:if>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[@STACK_HORIZ_INDEX = $iStackIdx])">
- <SHAPE WIDTH="0"/>
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $iStackIdx)]">
-<!--
- <xsl:variable name="proc_w_">
- <xsl:value-of select="$BLKD_MOD_W"/>
- </xsl:variable>
- <xsl:message>Found processor of width <xsl:value-of select="$proc_w_"/></xsl:message>
--->
- <SHAPE WIDTH="{$BLKD_MOD_W}"/>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@STACK_HORIZ_INDEX = $iStackIdx)]">
-
- <xsl:variable name="shpClass_" select="@MODCLASS"/>
- <xsl:variable name="shape_w_">
- <xsl:choose>
-
- <xsl:when test="$shpClass_ = 'PERIPHERAL'">
- <xsl:value-of select="$BLKD_MOD_W"/>
- </xsl:when>
-
- <xsl:when test="$shpClass_ = 'MEMORY_UNIT'">
- <xsl:value-of select="($BLKD_MOD_W * @MODS_W)"/>
- </xsl:when>
-
- <xsl:otherwise>0</xsl:otherwise>
-
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>Found shape width <xsl:value-of select="$shape_w_"/></xsl:message>
--->
-
- <SHAPE WIDTH="{$shape_w_}"/>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]">
- <xsl:variable name="bucket_w_">
- <xsl:value-of select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/>
- </xsl:variable>
-
-<!--
- <xsl:message>Found bucket of width <xsl:value-of select="$bucket_w_"/></xsl:message>
--->
- <SHAPE WIDTH="{$bucket_w_}"/>
- </xsl:for-each>
-
- </xsl:variable>
-
- <xsl:value-of select="math:max(exsl:node-set($shape_widths_)/SHAPE/@WIDTH)"/>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Stack_X">
- <xsl:param name="iStackIdx" select="0"/>
-<!--
- <xsl:message>Looking for stack indexes less than <xsl:value-of select="$iStackIdx"/></xsl:message>
--->
-
- <!-- Store the stack widths in a variable -->
- <xsl:variable name="stackspace_widths_">
-
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH = $iStackIdx)">
- <STACKSPACE WIDTH="{$BLKD_BUS_LANE_W}"/>
- </xsl:if>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES[(@STACK_HORIZ_INDEX < $iStackIdx)])">
- <STACKSPACE WIDTH="0"/>
- </xsl:if>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES[(@STACK_HORIZ_INDEX < $iStackIdx)])">
- <STACKSPACE WIDTH="0"/>
- </xsl:if>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX < $iStackIdx)])">
- <STACKSPACE WIDTH="0"/>
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST <= $iStackIdx)]">
-
-<!--
- <xsl:message>==============================</xsl:message>
- <xsl:message>Found a space of index <xsl:value-of select="@EAST"/></xsl:message>
- <xsl:message>Bus lane space width <xsl:value-of select="@BUSLANES_W"/></xsl:message>
- <xsl:message>Bus lane space is <xsl:value-of select="$space_width_"/></xsl:message>
- <xsl:variable name="space_width_" select="($BLKD_BUS_LANE_W * @BUSLANES_W)"/>
--->
-
- <xsl:variable name="East_">
- <xsl:choose>
- <xsl:when test="@EAST"><xsl:value-of select="@EAST"/></xsl:when>
- <xsl:otherwise>'NONE'</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="West_">
- <xsl:choose>
- <xsl:when test="@WEST"><xsl:value-of select="@WEST"/></xsl:when>
- <xsl:otherwise>NONE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>1 - West_ <xsl:value-of select="$West_"/></xsl:message>
- <xsl:message>1 - East_ <xsl:value-of select="$East_"/></xsl:message>
--->
- <xsl:variable name="space_width_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToWest" select="$West_"/>
- <xsl:with-param name="iStackToEast" select="$East_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stack_width_">
- <xsl:if test="not(@EAST = $iStackIdx)">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="@EAST"/>
- </xsl:call-template>
- </xsl:if>
- <xsl:if test="(@EAST = $iStackIdx)">0</xsl:if>
- </xsl:variable>
-<!--
- <xsl:message>Found stack of width <xsl:value-of select="$stack_width_"/></xsl:message>
- <xsl:message>==============================</xsl:message>
--->
- <STACKSPACE WIDTH="{$stack_width_ + $space_width_}"/>
-
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(not(@EAST) and (@WEST = ($iStackIdx -1)))]">
- <xsl:variable name="space_width_" select="($BLKD_BUS_LANE_W * @BUSLANES_W)"/>
-<!--
- <xsl:message>Found end space of <xsl:value-of select="$space_width_"/></xsl:message>
--->
- <STACKSPACE WIDTH="{$space_width_}"/>
- </xsl:for-each>
-
-
- </xsl:variable>
-
- <xsl:value-of select="sum(exsl:node-set($stackspace_widths_)/STACKSPACE/@WIDTH)"/>
-
-</xsl:template>
-
-<xsl:template name="F_Calc_Space_Width">
-
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
-
-<!--
- <xsl:message>Stack to West <xsl:value-of select="$stackToWest"/></xsl:message>
- <xsl:message>Stack to East <xsl:value-of select="$stackToEast"/></xsl:message>
--->
-
- <xsl:variable name="spaceWidth_">
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[((@EAST = $iStackToEast) or (not($iStackToWest = 'NONE') and (@WEST = $iStackToWest)))]">
- <xsl:value-of select="((($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[((@EAST = $iStackToEast) or (not($iStackToWest = 'NONE') and (@WEST = $iStackToWest)))]/@BUSLANES_W) + 1) * $BLKD_BUS_LANE_W)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>Space width <xsl:value-of select="$spaceWidth_"/></xsl:message>
--->
-
- <xsl:value-of select="$spaceWidth_"/>
-</xsl:template>
-
-
-<xsl:template name="F_Calc_Space_X">
-
- <xsl:param name="iStackToWest" select="'NONE'"/>
- <xsl:param name="iStackToEast" select="'NONE'"/>
-
-<!--
- <xsl:message>Stack East <xsl:value-of select="$stackToEast"/></xsl:message>
- <xsl:message>Stack West <xsl:value-of select="$stackToWest"/></xsl:message>
--->
-
- <!-- Store the stack widths in a variable -->
-
-<!--
- <xsl:message>Looking for stack indexes less than <xsl:value-of select="$stackIdx"/></xsl:message>
--->
-
- <xsl:variable name="stackspace_widths_">
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES[(@STACK_HORIZ_INDEX < $iStackToEast)])">
- <STACKSPACE WIDTH="0"/>
- </xsl:if>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES[(@STACK_HORIZ_INDEX < $iStackToEast)])">
- <STACKSPACE WIDTH="0"/>
- </xsl:if>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX < $iStackToEast)])">
- <STACKSPACE WIDTH="0"/>
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[((@EAST < $iStackToEast) or (not($iStackToWest = 'NONE') and (@EAST <= $iStackToWest)))]">
-
-<!--
- <xsl:message>==============================</xsl:message>
- <xsl:message>Found a space of index <xsl:value-of select="@EAST"/></xsl:message>
--->
-
- <xsl:variable name="East_">
- <xsl:choose>
- <xsl:when test="@EAST"><xsl:value-of select="@EAST"/></xsl:when>
- <xsl:otherwise>'NONE'</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="West_">
- <xsl:choose>
- <xsl:when test="@WEST"><xsl:value-of select="@WEST"/></xsl:when>
- <xsl:otherwise>NONE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-<!--
- <xsl:message>2 - West_ <xsl:value-of select="$West_"/></xsl:message>
- <xsl:message>2 - East_ <xsl:value-of select="$East_"/></xsl:message>
- -->
- <xsl:variable name="space_width_">
- <xsl:call-template name="F_Calc_Space_Width">
- <xsl:with-param name="iStackToWest" select="$West_"/>
- <xsl:with-param name="iStackToEast" select="$East_"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:variable name="space_width_" select="($BLKD_BUS_LANE_W * @BUSLANES_W)"/>
- <xsl:message>Bus lane space width <xsl:value-of select="@BUSLANES_W"/></xsl:message>
- <xsl:message>Bus lane space is <xsl:value-of select="$space_width_"/></xsl:message>
--->
-
- <xsl:variable name="stack_width_">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="@EAST"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Found stack of width <xsl:value-of select="$stack_width_"/></xsl:message>
- <xsl:message>==============================</xsl:message>
--->
-
- <STACKSPACE WIDTH="{$stack_width_ + $space_width_}"/>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:variable name = "stackToWest_W_">
- <xsl:choose>
- <xsl:when test="(($iStackToEast = '0') and ($iStackToWest = 'NONE'))">0</xsl:when>
- <xsl:when test="(($iStackToEast = 'NONE') and not($iStackToWest = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:when test="(not($iStackToEast = '0') and ($iStackToWest = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="($iStackToEast - 1)"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:variable name = "stackToEast_W_">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="stackIdx" select="$stackToEast"/>
- </xsl:call-template>
- </xsl:variable>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($stackToEast_W_ div 2)"/>
--->
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($stackToWest_W_ div 2)"/>
-
- <xsl:value-of select="sum(exsl:node-set($stackspace_widths_)/STACKSPACE/@WIDTH) - $extSpaceWest_W_"/>
-</xsl:template>
-
-</xsl:stylesheet>
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<xsl:variable name="G_ROOT" select="/"/>
-
-<!--
- ===========================================================================
- CALCULATE GLOBAL VARIABLES BASED ON BLKDIAGRAM DEF IN INPUT XML
- ===========================================================================
--->
-
-<xsl:variable name="G_Total_StandAloneMpmc_H">
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE">
- <xsl:value-of select="($BLKD_MPMC_MOD_H + $BLKD_MPMC2PROC_GAP)"/>
- </xsl:if>
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE)">0</xsl:if>
-</xsl:variable>
-
-<xsl:variable name="G_Max_Stack_BlwSbs_H">
- <xsl:call-template name="F_Calc_Max_Stack_BlwSbs_Height"/>
-</xsl:variable>
-
-<xsl:variable name="G_Max_Stack_AbvSbs_H">
- <xsl:call-template name="F_Calc_Max_Stack_AbvSbs_Height"/>
-</xsl:variable>
-
-<xsl:variable name="G_Total_Stacks_W">
- <xsl:call-template name="F_Calc_Stack_X">
- <xsl:with-param name="iStackIdx" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)"/>
- </xsl:call-template>
-</xsl:variable>
-
-<xsl:variable name="G_NumOfSharedBusses" select="count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE)"/>
-<xsl:variable name="G_Total_SharedBus_H" select="($G_NumOfSharedBusses * $BLKD_SBS_LANE_H)"/>
-
-<xsl:variable name="G_NumOfBridges" select="count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE)"/>
-<xsl:variable name="G_Total_Bridges_W" select="(($G_NumOfBridges * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))) + $BLKD_BRIDGE_GAP)"/>
-
-<xsl:variable name="G_Total_DrawArea_CLC" select="($G_Total_Stacks_W + $G_Total_Bridges_W + ($BLKD_INNER_GAP * 2))"/>
-
-<xsl:variable name="G_Total_DrawArea_W">
- <xsl:if test="$G_Total_DrawArea_CLC > ($BLKD_KEY_W + $BLKD_SPECS_W + $BLKD_SPECS2KEY_GAP)">
- <xsl:value-of select="$G_Total_DrawArea_CLC"/>
- </xsl:if>
- <xsl:if test="not($G_Total_DrawArea_CLC > ($BLKD_KEY_W + $BLKD_SPECS2KEY_GAP + $BLKD_SPECS_W))">
- <xsl:value-of select="($BLKD_KEY_W + $BLKD_SPECS_W + $BLKD_SPECS2KEY_GAP)"/>
- </xsl:if>
-</xsl:variable>
-
-<xsl:variable name="G_IpBucketMods_H">
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H"><xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H"/></xsl:if>
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H)">0</xsl:if>
-</xsl:variable>
-<xsl:variable name="G_Total_IpBucket_H" select="($G_IpBucketMods_H * ($BLKD_MOD_H + $BLKD_BIF_H))"/>
-
-<xsl:variable name="G_Total_UnkBucket_H">
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET">
-
- <xsl:variable name="unkBucketMods_H_">
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H"><xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H"/></xsl:if>
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H)">0</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="total_UnkMod_H_" select="($unkBucketMods_H_ * ($BLKD_MOD_H + $BLKD_BIF_H))"/>
-
- <xsl:variable name="unkBucketBifs_H_">
- <xsl:if test="/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H"><xsl:value-of select="/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H"/></xsl:if>
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H)">0</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="total_UnkBif_H_" select="($unkBucketBifs_H_ * ($BLKD_MOD_H + $BLKD_BIF_H))"/>
-
- <xsl:value-of select="($total_UnkBif_H_ + $total_UnkMod_H_)"/>
- </xsl:if>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET)">0</xsl:if>
-</xsl:variable>
-
-<xsl:variable name="G_SharedBus_Y" select="($BLKD_INNER_Y + $G_Total_StandAloneMpmc_H + $G_Max_Stack_AbvSbs_H + $BLKD_PROC2SBS_GAP)"/>
-
-<!-- ===========================================================================
- Calculate the width of the Block Diagram based on the total number of
- buslanes and modules in the design. If there are no buslanes or modules,
- a default width, just wide enough to display the KEY and SPECS is used
- =========================================================================== -->
-<xsl:variable name="G_Total_Blkd_W" select="($G_Total_DrawArea_W + (($BLKD_PRTCHAN_W + $BLKD_IORCHAN_W)* 2))"/>
-<xsl:variable name="G_Total_Diag_W" select="$G_Total_Blkd_W"/>
-
-<!-- =========================================================================== -->
-<!-- Calculate the height of the Block Diagram based on the total number of -->
-<!-- buslanes and modules in the design. Take into account special shapes such -->
-<!-- as MultiProc shapes. -->
-<!-- =========================================================================== -->
-
-
-<xsl:variable name="G_Total_DrawArea_H" select="($G_Total_StandAloneMpmc_H + $G_Max_Stack_AbvSbs_H + $BLKD_PROC2SBS_GAP + $G_Total_SharedBus_H + $G_Max_Stack_BlwSbs_H + $BLKD_SBS2IP_GAP + $G_Total_IpBucket_H + $BLKD_IP2UNK_GAP + $G_Total_UnkBucket_H + ($BLKD_INNER_GAP * 2))"/>
-<xsl:variable name="G_Total_Blkd_H" select="($G_Total_DrawArea_H + (($BLKD_PRTCHAN_H + $BLKD_IORCHAN_H)* 2))"/>
-
-<xsl:variable name="G_Total_Diag_H">
- <xsl:if test="($IN_TESTMODE = 'TRUE')">
- <xsl:message>Generating Blkdiagram in TestMode </xsl:message>
- <xsl:value-of select="$G_Total_Blkd_H"/>
- </xsl:if>
- <xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))">
- <xsl:value-of select="($G_Total_Blkd_H + $BLKD_DRAWAREA2KEY_GAP + $BLKD_KEY_H)"/>
- </xsl:if>
-</xsl:variable>
-
-</xsl:stylesheet>
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-<xsl:stylesheet version="1.0"
- xmlns:svg="http://www.w3.org/2000/svg"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-<!--
-<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
- doctype-public="-//W3C//DTD SVG Tiny 1.1//EN"
- doctype-system="http://www.w3.org/Graphics/SVG/1.1/DTD/svg11-tiny.dtd"/>
--->
-
-<!-- ======================= DEF BLOCK =============================== -->
-<xsl:template name="Define_IOPorts">
-
- <xsl:variable name="key_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'KEY'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="key_lt_col_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="'KEY'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <g id="G_IOPort">
- <rect
- x="0"
- y="0"
- width= "{$BLKD_IOP_W}"
- height="{$BLKD_IOP_H}"
- fill="{$COL_IORING_LT}"
- stroke="{$COL_IORING}"
- stroke-width="1"/>
-
- <path d="M 0,0
- L {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
- L 0,{$BLKD_IOP_H}
- Z"
- stroke="none"
- fill="{$COL_SYSPRT}"/>
- </g>
-
- <g id="G_BIPort">
- <rect
- x="0"
- y="0"
- width= "{$BLKD_IOP_W}"
- height="{$BLKD_IOP_H}" style="fill:{$COL_IORING_LT}; stroke:{$COL_IORING}; stroke-width:1"/>
-
- <path class="btop"
- d="M 0,{ceiling($BLKD_IOP_H div 2)}
- {ceiling($BLKD_IOP_W div 2)},0
- {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
- Z" style="stroke:none; fill:{$COL_SYSPRT}"/>
-
- <path class="bbot"
- d="M 0,{ceiling($BLKD_IOP_H div 2)}
- {ceiling($BLKD_IOP_W div 2)},{$BLKD_IOP_H}
- {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
- Z" style="stroke:none; fill:{$COL_SYSPRT}"/>
-
- </g>
-
- <g id="KEY_IOPort">
- <rect
- x="0"
- y="0"
- width= "{$BLKD_IOP_W}"
- height="{$BLKD_IOP_H}" style="fill:{$key_lt_col_}; stroke:none;"/>
-
- <path class="ioport"
- d="M 0,0
- L {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
- L 0,{$BLKD_IOP_H}
- Z" style="stroke:none; fill:{$key_col_}"/>
- </g>
-
- <g id="KEY_BIPort">
- <rect
- x="0"
- y="0"
- width= "{$BLKD_IOP_W}"
- height="{$BLKD_IOP_H}" style="fill:{$key_lt_col_}; stroke:none;"/>
-
- <path class="btop"
- d="M 0,{ceiling($BLKD_IOP_H div 2)}
- {ceiling($BLKD_IOP_W div 2)},0
- {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
- Z" style="stroke:none; fill:{$key_col_}"/>
-
- <path class="bbot"
- d="M 0,{ceiling($BLKD_IOP_H div 2)}
- {ceiling($BLKD_IOP_W div 2)},{$BLKD_IOP_H}
- {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
- Z" style="stroke:none; fill:{$key_col_}"/>
- </g>
-
- <g id="KEY_INPort">
- <use x="0" y="0" xlink:href="#KEY_IOPort"/>
- <rect
- x="{$BLKD_IOP_W}"
- y="0"
- width= "{ceiling($BLKD_IOP_W div 2)}"
- height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/>
- </g>
-
- <g id="KEY_OUTPort">
- <use x="0" y="0" xlink:href="#KEY_IOPort" transform="scale(-1,1) translate({$BLKD_IOP_W * -1},0)"/>
- <rect
- x="{$BLKD_IOP_W}"
- y="0"
- width= "{ceiling($BLKD_IOP_W div 2)}"
- height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/>
- </g>
-
- <g id="KEY_INOUTPort">
- <use x="0" y="0" xlink:href="#KEY_BIPort"/>
- <rect
- x="{$BLKD_IOP_W}"
- y="0"
- width= "{ceiling($BLKD_IOP_W div 2)}"
- height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/>
- </g>
-</xsl:template>
-
-<!-- ======================= DRAW BLOCK =============================== -->
-
-<xsl:template name="Draw_IOPorts">
-
- <xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/>
-
- <xsl:if test="($ports_count_ > 30)">
- <xsl:call-template name="Draw_IOPorts_4Sides"/>
- </xsl:if>
-
- <xsl:if test="($ports_count_ <= 30)">
- <xsl:call-template name="Draw_IOPorts_2Sides"/>
- </xsl:if>
-</xsl:template>
-
-<xsl:template name="Draw_IOPorts_2Sides">
-
- <xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/>
- <xsl:variable name="ports_per_side_" select="ceiling($ports_count_ div 2)"/>
-
- <xsl:variable name="h_ofs_">
- <xsl:value-of select="$BLKD_PRTCHAN_W + ceiling(($G_Total_DrawArea_W - (($ports_per_side_ * $BLKD_IOP_W) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/>
- </xsl:variable>
-
- <xsl:variable name="v_ofs_">
- <xsl:value-of select="$BLKD_PRTCHAN_H + ceiling(($G_Total_DrawArea_H - (($ports_per_side_ * $BLKD_IOP_H) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/>
- </xsl:variable>
-
-
- <xsl:for-each select="EXTERNALPORTS/PORT">
- <xsl:sort data-type="number" select="@INDEX" order="ascending"/>
-
- <xsl:variable name="poffset_" select="0"/>
- <xsl:variable name="pcount_" select="$poffset_ + (position() -1)"/>
-
- <xsl:variable name="pdir_">
- <xsl:choose>
- <xsl:when test="(@DIR='I' or @DIR='IN' or @DIR='INPUT')">I</xsl:when>
- <xsl:when test="(@DIR='O' or @DIR='OUT' or @DIR='OUTPUT')">O</xsl:when>
- <xsl:when test="(@DIR='IO' or @DIR='INOUT')">B</xsl:when>
- <xsl:otherwise>I</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="pside_">
- <xsl:choose>
- <xsl:when test="($pcount_ >= ($ports_per_side_ * 0) and ($pcount_ < ($ports_per_side_ * 1)))">W</xsl:when>
- <xsl:when test="($pcount_ >= ($ports_per_side_ * 1) and ($pcount_ < ($ports_per_side_ * 2)))">E</xsl:when>
- <xsl:otherwise>D</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="pdec_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($ports_per_side_ * 0)"/></xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($ports_per_side_ * 1)"/></xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="px_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($BLKD_PRTCHAN_W - $BLKD_IOP_W)"/></xsl:when>
- <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)) - 2)"/></xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($BLKD_PRTCHAN_W + ($BLKD_IORCHAN_W * 2) + $G_Total_DrawArea_W)"/></xsl:when>
- <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)))"/></xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="py_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when>
- <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_PRTCHAN_H + ($BLKD_IORCHAN_H * 2) + $G_Total_DrawArea_H)"/></xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when>
- <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($BLKD_PRTCHAN_H - $BLKD_IOP_H)"/></xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="prot_">
- <xsl:choose>
- <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'I'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'I'))">-90</xsl:when>
- <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'I'))">180</xsl:when>
- <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'I'))">90</xsl:when>
-
- <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'O'))">180</xsl:when>
- <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'O'))">90</xsl:when>
- <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'O'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'O'))">-90</xsl:when>
-
- <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'B'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'B'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'B'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'B'))">0</xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="txo_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')">-10</xsl:when>
- <xsl:when test="($pside_ = 'S')">6</xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="(($BLKD_IOP_W * 2) - 4)"/></xsl:when>
- <xsl:when test="($pside_ = 'N')">6</xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="tyo_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when>
- <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_IOP_H * 2) + 4"/></xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when>
- <xsl:when test="($pside_ = 'N')">-2</xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="$pdir_ = 'B'">
- <use x="{$px_}"
- y="{$py_}"
- id="{@NAME}"
- xlink:href="#G_BIPort"
- transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/>
- </xsl:if>
-
- <xsl:if test="(($pside_ = 'S') and not($pdir_ = 'B'))">
- <rect
- x="{$px_}"
- y="{$py_}"
- width= "{$BLKD_IOP_W}"
- height="{$BLKD_IOP_H}" style="stroke:{$COL_IORING}; stroke-width:1"/>
- </xsl:if>
-
- <xsl:if test="not($pdir_ = 'B')">
- <use x="{$px_}"
- y="{$py_}"
- id="{@NAME}"
- xlink:href="#G_IOPort"
- transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/>
- </xsl:if>
-
- <text class="iopnumb"
- x="{$px_ + $txo_}"
- y="{$py_ + $tyo_}">
- <xsl:value-of select="@INDEX"/><tspan class="iopgrp"><xsl:value-of select="@GROUP"/></tspan>
- </text>
-
- </xsl:for-each>
-
-</xsl:template>
-
-
-<xsl:template name="Draw_IOPorts_4Sides">
-
- <xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/>
- <xsl:variable name="ports_per_side_" select="ceiling($ports_count_ div 4)"/>
-
- <xsl:variable name="h_ofs_">
- <xsl:value-of select="$BLKD_PRTCHAN_W + ceiling(($G_Total_DrawArea_W - (($ports_per_side_ * $BLKD_IOP_W) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/>
- </xsl:variable>
-
- <xsl:variable name="v_ofs_">
- <xsl:value-of select="$BLKD_PRTCHAN_H + ceiling(($G_Total_DrawArea_H - (($ports_per_side_ * $BLKD_IOP_H) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/>
- </xsl:variable>
-
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT">
- <xsl:sort data-type="number" select="@INDEX" order="ascending"/>
-
- <xsl:variable name="poffset_" select="0"/>
- <xsl:variable name="pcount_" select="$poffset_ + (position() -1)"/>
-
- <xsl:variable name="pdir_">
- <xsl:choose>
- <xsl:when test="(@DIR='I' or @DIR='IN' or @DIR='INPUT')">I</xsl:when>
- <xsl:when test="(@DIR='O' or @DIR='OUT' or @DIR='OUTPUT')">O</xsl:when>
- <xsl:when test="(@DIR='IO' or @DIR='INOUT')">B</xsl:when>
- <xsl:otherwise>I</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="pside_">
- <xsl:choose>
- <xsl:when test="($pcount_ >= ($ports_per_side_ * 0) and ($pcount_ < ($ports_per_side_ * 1)))">W</xsl:when>
- <xsl:when test="($pcount_ >= ($ports_per_side_ * 1) and ($pcount_ < ($ports_per_side_ * 2)))">S</xsl:when>
- <xsl:when test="($pcount_ >= ($ports_per_side_ * 2) and ($pcount_ < ($ports_per_side_ * 3)))">E</xsl:when>
- <xsl:when test="($pcount_ >= ($ports_per_side_ * 3) and ($pcount_ < ($ports_per_side_ * 4)))">N</xsl:when>
- <xsl:otherwise>D</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="pdec_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($ports_per_side_ * 0)"/></xsl:when>
- <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($ports_per_side_ * 1)"/></xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($ports_per_side_ * 2)"/></xsl:when>
- <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($ports_per_side_ * 3)"/></xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="px_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($BLKD_PRTCHAN_W - $BLKD_IOP_W)"/></xsl:when>
- <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)) - 2)"/></xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($BLKD_PRTCHAN_W + ($BLKD_IORCHAN_W * 2) + $G_Total_DrawArea_W)"/></xsl:when>
- <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)))"/></xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="py_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when>
- <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_PRTCHAN_H + ($BLKD_IORCHAN_H * 2) + $G_Total_DrawArea_H)"/></xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when>
- <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($BLKD_PRTCHAN_H - $BLKD_IOP_H)"/></xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="prot_">
- <xsl:choose>
- <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'I'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'I'))">-90</xsl:when>
- <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'I'))">180</xsl:when>
- <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'I'))">90</xsl:when>
-
- <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'O'))">180</xsl:when>
- <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'O'))">90</xsl:when>
- <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'O'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'O'))">-90</xsl:when>
-
- <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'B'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'B'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'B'))">0</xsl:when>
- <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'B'))">0</xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="txo_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')">-14</xsl:when>
- <xsl:when test="($pside_ = 'S')">8</xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="(($BLKD_IOP_W * 2) - 4)"/></xsl:when>
- <xsl:when test="($pside_ = 'N')">8</xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="tyo_">
- <xsl:choose>
- <xsl:when test="($pside_ = 'W')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when>
- <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_IOP_H * 2) + 4"/></xsl:when>
- <xsl:when test="($pside_ = 'E')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when>
- <xsl:when test="($pside_ = 'N')">-2</xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="$pdir_ = 'B'">
- <use x="{$px_}"
- y="{$py_}"
- id="{@NAME}"
- xlink:href="#G_BIPort"
- transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/>
- </xsl:if>
-
- <xsl:if test="(($pside_ = 'S') and not($pdir_ = 'B'))">
- <rect
- x="{$px_}"
- y="{$py_}"
- width= "{$BLKD_IOP_W}"
- height="{$BLKD_IOP_H}" style="stroke:{$COL_IORING}; stroke-width:1"/>
- </xsl:if>
-
- <xsl:if test="not($pdir_ = 'B')">
- <use x="{$px_}"
- y="{$py_}"
- id="{@NAME}"
- xlink:href="#G_IOPort"
- transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/>
- </xsl:if>
-
- <text class="iopnumb"
- x="{$px_ + $txo_}"
- y="{$py_ + $tyo_}"><xsl:value-of select="@INDEX"/><tspan class="iopgrp"><xsl:value-of select="@GROUP"/></tspan>
- </text>
-
- </xsl:for-each>
-
-</xsl:template>
-
-<xsl:template name="Define_ExtPortsTable">
-
-<!--
- <xsl:if test="$oriented_= 'WEST'"><xsl:value-of select="$proc2procX_ - (string-length(@BUSNAME) * 6)"/></xsl:if>
- <xsl:variable name="max_name_" select="math:max(string-length($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT/@NAME))"/>
- <xsl:variable name="max_sgnm_" select="math:max(string-length($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT/@SIGNAME))"/>
-
- <xsl:message>MAX NAME <xsl:value-of select="$max_name_"/></xsl:message>
- <xsl:message>MAX SIG <xsl:value-of select="$max_sgnm_"/></xsl:message>
--->
-
- <xsl:variable name="ext_ports_">
- <xsl:if test="not($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)">
- <EXTPORT NAME="__none__" SIGNAME="__none_" NAMELEN="0" SIGLEN="0"/>
- </xsl:if>
- <xsl:if test="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT">
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT">
- <EXTPORT NAME="{@NAME}" SIGNAME="{@SIGNAME}" NAMELEN="{string-length(@NAME)}" SIGLEN="{string-length(@SIGNAME)}"/>
- </xsl:for-each>
- </xsl:if>
- </xsl:variable>
-
- <xsl:variable name="max_name_" select="math:max(exsl:node-set($ext_ports_)/EXTPORT/@NAMELEN)"/>
- <xsl:variable name="max_sign_" select="math:max(exsl:node-set($ext_ports_)/EXTPORT/@SIGLEN)"/>
-
- <xsl:variable name="h_font_" select="12"/>
- <xsl:variable name="w_font_" select="12"/>
-
- <xsl:variable name="w_num_" select="($w_font_ * 5)"/>
- <xsl:variable name="w_dir_" select="($w_font_ * 3)"/>
- <xsl:variable name="w_lsbmsb_" select="($w_font_ * 9)"/>
- <xsl:variable name="w_attr_" select="($w_font_ * 4)"/>
- <xsl:variable name="w_name_" select="($w_font_ * $max_name_)"/>
- <xsl:variable name="w_sign_" select="($w_font_ * $max_sign_)"/>
-
- <xsl:variable name="w_table_" select="($w_num_ + $w_name_ + $w_dir_ + $w_sign_ + $w_attr_)"/>
-
-<!--
- <xsl:message>MAX NAME <xsl:value-of select="$max_name_"/></xsl:message>
- <xsl:message>MAX SIG <xsl:value-of select="$max_sign_"/></xsl:message>
-
- <xsl:message>W NUM <xsl:value-of select="$w_num_"/></xsl:message>
- <xsl:message>W DIR <xsl:value-of select="$w_dir_"/></xsl:message>
- <xsl:message>W NAM <xsl:value-of select="$w_name_"/></xsl:message>
- <xsl:message>W SIG <xsl:value-of select="$w_sign_"/></xsl:message>
- <xsl:message>W ATT <xsl:value-of select="$w_attr_"/></xsl:message>
-
- <xsl:message>W TABLE <xsl:value-of select="$w_table_"/></xsl:message>
--->
-
- <g id="BlkDiagram_ExtPortsTable">
- <rect
- x="0"
- y="0"
- width= "{$w_table_}"
- height="{$h_font_}" style="fill:{$COL_RED}; stroke:none; stroke-width:1"/>
- </g>
-
-
-
-</xsl:template>
-
-<!-- ======================= END MAIN BLOCK =========================== -->
-
-</xsl:stylesheet>
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-
-<!--
- xmlns:svg="http://www.w3.org/2000/svg"
- ===============================================
- INCLUDES
- ===============================================
- -->
-<xsl:include href="MdtSvgBLKD_Dimensions.xsl"/>
-
-<xsl:include href="MdtSvgDiag_Colors.xsl"/>
-<xsl:include href="MdtSvgDiag_Globals.xsl"/>
-<xsl:include href="MdtSvgDiag_StyleDefs.xsl"/>
-
-<xsl:include href="MdtTinySvgDiag_BifShapes.xsl"/>
-
-<xsl:include href="MdtTinySvgBLKD_IOPorts.xsl"/>
-<xsl:include href="MdtTinySvgBLKD_Busses.xsl"/>
-<xsl:include href="MdtTinySvgBLKD_Globals.xsl"/>
-<xsl:include href="MdtTinySvgBLKD_Functions.xsl"/>
-<xsl:include href="MdtTinySvgBLKD_Peripherals.xsl"/>
-<xsl:include href="MdtTinySvgBLKD_Processors.xsl"/>
-<xsl:include href="MdtTinySvgBLKD_BusLaneSpaces.xsl"/>
-
-<xsl:output method="xml"
- version="1.0"
- indent="yes"
- encoding="UTF-8"
- doctype-public="-//W3C//DTD SVG 1.1//EN"
- doctype-system="http://www.w3.org/Graphics/SVG/1.1/svg11-tiny.dtd"/>
-
-<!--
- ===============================================
- PARAMETERS
- ===============================================
- -->
-
-<xsl:param name="ADD_VIEWBOX" select="'FALSE'"/>
-<xsl:param name="IN_TESTMODE" select="'FALSE'"/>
-
-
-<!--
-<xsl:param name="CSS_SVG_DIAGRAMS" select="'MdtSvgDiag_StyleDefs.css'"/>
-<xsl:param name="CSS_SVG_DIAGRAMS" select="'__INTERNAL__'"/>
- -->
-
-<!--
- ======================================================
- MAIN BLOCKDIAGRAM TEMPLATE
- ======================================================
--->
-<xsl:template match="EDKSYSTEM[not(BLKDIAGRAM)]">
- <xsl:message>ERROT: Project is missing BLKDIAGRAM Element. Cannot generate.</xsl:message>
-</xsl:template>
-
-<xsl:template match="EDKSYSTEM[BLKDIAGRAM]">
-
-<!--
-<xsl:message>STCK_W is <xsl:value-of select="$G_Total_Stacks_W"/></xsl:message>
-<xsl:message>BRDG_W is <xsl:value-of select="$G_Total_Bridges_W"/></xsl:message>
-<xsl:message>MPMC is <xsl:value-of select="$G_Total_StandAloneMpmc_H"/></xsl:message>
-<xsl:message>MPMC is <xsl:value-of select="$G_Total_StandAloneMpmc_H"/></xsl:message>
-<xsl:message>MABV is <xsl:value-of select="$G_Max_Stack_AbvSbs_H"/></xsl:message>
-<xsl:message>MBLW is <xsl:value-of select="$G_Max_Stack_BlwSbs_H"/></xsl:message>
-<xsl:message>IPBK is <xsl:value-of select="$G_Total_IpBucket_H"/></xsl:message>
-<xsl:message>Blkd Total is <xsl:value-of select="$blkd_H_"/></xsl:message>
-<xsl:message>max abv is <xsl:value-of select="$max_Stack_AbvSbs_H_"/></xsl:message>
-<xsl:message>max blw is <xsl:value-of select="$max_Stack_BlwSbs_H_"/></xsl:message>
-<xsl:message>Ip Bkt is <xsl:value-of select="$totalIpBkt_H_"/></xsl:message>
-<xsl:message>Sbs is <xsl:value-of select="$totalSbs_H_"/></xsl:message>
-<xsl:message>Unk Bkt is <xsl:value-of select="$totalUnkBkt_H_"/></xsl:message>
-<xsl:message>Blkd DrawArea height as <xsl:value-of select="$total_DrawArea_H_"/></xsl:message>
--->
-
-<!--specify a css for the file -->
-<!--
-<xsl:processing-instruction name="xml-stylesheet">href="<xsl:value-of select="$CSS_SVG_DIAGRAMS"/>" type="text/css"</xsl:processing-instruction>
-<xsl:variable name="BLKD_ZOOM_Y">
- <xsl:choose>
- <xsl:when test="($ADD_VIEWBOX = 'TRUE')">
- <xsl:value-of select="($G_Total_Diag_H * 2)"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
-</xsl:variable>
-<xsl:message>EDWVERSION is <xsl:value-of select="$G_ROOT/EDKSYSTEM/@EDWVERSION"/></xsl:message>
- -->
-
-<xsl:text> </xsl:text>
-<!--
-<svg width="{$G_Total_Diag_W}" height="{$G_Total_Diag_H}" viewBox="0 0 0 {$BLKD_ZOOM_Y}">
--->
-<svg width="{$G_Total_Diag_W}" height="{$G_Total_Diag_H}">
-<!--
- ===============================================
- Layout All the various definitions
- ===============================================
--->
- <defs>
-
- <!-- IO Port Defs -->
- <xsl:call-template name="Define_IOPorts"/>
-
- <!-- BIF Defs -->
- <xsl:call-template name="Define_ConnectedBifTypes"/>
-
- <!-- Bus Defs -->
- <xsl:call-template name="Define_Busses"/>
-
- <!-- Shared Bus Buckets Defs -->
- <xsl:call-template name="Define_SBSBuckets"/>
-
- <!-- IP Bucket Defs -->
- <xsl:call-template name="Define_IPBucket"/>
-
- <!-- Stack Defs -->
- <xsl:call-template name="Define_AllStacks"/>
-
- <!-- Space Defs -->
- <xsl:call-template name="Define_BusLaneSpaces"/>
-
- <!-- Main MPMC Defs -->
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE">
- <xsl:call-template name="Define_StandAlone_MPMC"/>
- </xsl:if>
-
- <!-- Diagram Key Definition -->
- <xsl:call-template name="Define_BlkDiagram_Key"/>
-
- <!-- Diagram Specs Definition -->
- <xsl:call-template name="Define_BlkDiagram_Specs">
- <xsl:with-param name="iArch" select="SYSTEMINFO/@ARCH"/>
- <xsl:with-param name="iPart" select="SYSTEMINFO/@PART"/>
- <xsl:with-param name="iTimeStamp" select="@TIMESTAMP"/>
- <xsl:with-param name="iEdkVersion" select="@EDKVERSION"/>
- </xsl:call-template>
-
- </defs>
-
-<!-- =============================================== -->
-<!-- Draw Outlines -->
-<!-- =============================================== -->
-
- <!-- The surrounding black liner -->
- <rect x="0"
- y="0"
- width ="{$G_Total_Diag_W}"
- height="{$G_Total_Diag_H}"
- fill="{$COL_WHITE}"
- stroke="{$COL_BLACK}"
- stroke-width="4"/>
-
- <!-- The outer IO channel -->
- <rect x="{$BLKD_PRTCHAN_W}"
- y="{$BLKD_PRTCHAN_H}"
- width= "{$G_Total_Blkd_W - ($BLKD_PRTCHAN_W * 2)}"
- height="{$G_Total_Blkd_H - ($BLKD_PRTCHAN_H * 2)}" style="fill:{$COL_IORING}"/>
-
- <!-- The Diagram's drawing area -->
- <rect x="{$BLKD_PRTCHAN_W + $BLKD_IORCHAN_W}"
- y="{$BLKD_PRTCHAN_H + $BLKD_IORCHAN_H}"
- rx="8"
- ry="8"
- width= "{$G_Total_DrawArea_W}"
- height="{$G_Total_DrawArea_H}"
- fill="{$COL_BG}"/>
-
-<!-- =============================================== -->
-<!-- Draw All the various components -->
-<!-- =============================================== -->
-
- <!-- Layout the IO Ports -->
-<!--
- <xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))">
- <xsl:call-template name="Draw_IOPorts"/>
- </xsl:if>
- -->
-
- <!-- Layout the Shapes -->
- <xsl:call-template name="Draw_BlkDiagram_Shapes"/>
-
-</svg>
-
-<!-- ======================= END MAIN SVG BLOCK =============================== -->
-</xsl:template>
-
-<xsl:template name="Draw_BlkDiagram_Shapes">
-
- <!--
- ************************************************************
- *************** BEGIN DRAWING BLOCK DIAGRAM *************
- ************************************************************
- -->
-
- <!--
- ===========================================================
- Draw the Stand Alone MPMC, (if any)
- ===========================================================
- -->
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE">
-
- <xsl:variable name="mpmc_inst_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE/@INSTANCE"/>
-
- <use x="{$BLKD_INNER_X}" y="{$BLKD_INNER_Y}" xlink:href="#mpmcmodule_{$mpmc_inst_}"/>
- <!--
- ===========================================================
- Draw the connections to the Stand Alone MPMC
- ===========================================================
- -->
- <xsl:call-template name="Draw_BlkDiagram_StandAloneMpmcConnections"/>
- </xsl:if>
-
- <!--
- ===========================================================
- Draw the Stacks
- ===========================================================
- -->
- <xsl:call-template name="Draw_BlkDiagram_Stacks"/>
-
- <!--
- ===========================================================
- Draw the Bus Lane Spaces
- ===========================================================
- -->
- <xsl:call-template name="Draw_BlkDiagram_BusLaneSpaces"/>
-
- <!--
- ===========================================================
- Draw the shared busses
- ===========================================================
- -->
- <use x="{$BLKD_INNER_X}" y="{$G_SharedBus_Y}" xlink:href="#group_sharedBusses"/>
-
- <!--
- ===========================================================
- Draw the Bridges
- ===========================================================
- -->
- <xsl:call-template name="Draw_BlkDiagram_Bridges"/>
-
-
- <!--
- ===========================================================
- Draw the Ip Bucket
- ===========================================================
- -->
- <xsl:call-template name="Draw_BlkDiagram_IPBucket"/>
-
- <!--
- ===========================================================
- Draw the Key
- ===========================================================
- -->
- <xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))">
- <use x="{$G_Total_Blkd_W - $BLKD_KEY_W - $BLKD_PRTCHAN_W}" y="{$G_Total_Blkd_H + $BLKD_DRAWAREA2KEY_GAP - 8}" xlink:href="#BlkDiagram_Key"/>
- </xsl:if>
-
- <!--
- ===========================================================
- Draw the Specs
- ===========================================================
- -->
- <xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))">
- <use x="{$BLKD_PRTCHAN_W}" y="{$G_Total_Blkd_H + $BLKD_DRAWAREA2KEY_GAP - 8}" xlink:href="#BlkDiagram_Specs"/>
- </xsl:if>
-
- <!--
- ************************************************************
- *************** DONE DRAWING BLOCK DIAGRAM **************
- ************************************************************
- -->
-
-</xsl:template>
-
-
-<!-- ======================================================================= -->
-<!-- FUNCTION TEMPLATE -->
-<!-- -->
-<!-- Draw stacks on the Block Diagram -->
-<!-- ======================================================================= -->
-<xsl:template name="Draw_BlkDiagram_Stacks">
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST < $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]">
-
- <xsl:variable name="stack_line_x_">
- <xsl:call-template name="F_Calc_Stack_X">
- <xsl:with-param name="iStackIdx" select="@EAST"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stack_abv_sbs_">
- <xsl:call-template name="F_Calc_Stack_AbvSbs_Height">
- <xsl:with-param name="iStackIdx" select="@EAST"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="bridges_w_" select="(($G_NumOfBridges * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))) + $BLKD_BRIDGE_GAP)"/>
-
- <xsl:variable name="stack_y_" select="($G_SharedBus_Y - $stack_abv_sbs_ - $BLKD_PROC2SBS_GAP)"/>
- <xsl:variable name="stack_x_" select="($BLKD_INNER_X + $stack_line_x_ + $bridges_w_)"/>
-
- <xsl:variable name="stack_name_">
- <xsl:call-template name="F_generate_Stack_Name">
- <xsl:with-param name="iHorizIdx" select="@EAST"/>
- </xsl:call-template>
- </xsl:variable>
-
- <use x="{$stack_x_}" y="{$stack_y_}" xlink:href="#{$stack_name_}"/>
-
- </xsl:for-each>
-
-</xsl:template>
-
-<xsl:template name="Draw_BlkDiagram_StandAloneMpmcConnections">
-
- <xsl:variable name="mpmcInst_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE/@INSTANCE"/>
- <xsl:variable name="lastStack_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH) - 1"/>
-
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE">
- <xsl:variable name="currentLane_" select="position()"/>
-<!--
- <xsl:message>Current lane <xsl:value-of select="$currentLane_"/></xsl:message>
--->
- <xsl:variable name="stackToEast_">
- <xsl:choose>
- <xsl:when test="not(@WEST = $lastStack_)"><xsl:value-of select="@EAST"/></xsl:when>
- <xsl:when test=" (@WEST = $lastStack_)"><xsl:value-of select="'NONE'"/></xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="stackToWest_">
- <xsl:choose>
- <xsl:when test="not(@WEST = $lastStack_)"><xsl:value-of select="'NONE'"/></xsl:when>
- <xsl:when test=" (@WEST = $lastStack_)"><xsl:value-of select="@WEST"/></xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="spaceAbvSbs_H_">
- <xsl:call-template name="F_Calc_Space_AbvSbs_Height">
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_y_" select="($G_SharedBus_Y - $spaceAbvSbs_H_ - $BLKD_PROC2SBS_GAP)"/>
-
-<!--
- <xsl:message>Stack To East <xsl:value-of select="$stackToEast_"/></xsl:message>
- <xsl:message>Stack To West <xsl:value-of select="$stackToWest_"/></xsl:message>
- <xsl:variable name="space_X_">
- <xsl:call-template name="F_Calc_Space_X">
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- </xsl:call-template>
- </xsl:variable>
- <xsl:variable name="space_y_" select="($G_SharedBus_Y - $spaceAbvSbs_H_ - $BLKD_PROC2SBS_GAP)"/>
- <xsl:variable name="space_x_" select="($BLKD_INNER_X + $G_Total_Bridges_W + $space_line_x_)"/>
--->
-
-
- <xsl:for-each select="BUSCONNLANE[@IS_MPMCCONN]">
-
-<!--
- <xsl:variable name="bifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = BUSCONN/@INSTANCE)]/BUSINTERFACE[(@BUSNAME = @BUSNAME)]/@BIF_X"/>
--->
- <xsl:variable name="bifInst_" select="BUSCONN/@INSTANCE"/>
- <xsl:variable name="busName_" select="@BUSNAME"/>
- <xsl:variable name="bifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $bifInst_)]/BUSINTERFACE[(@BUSNAME = $busName_)]/@BIF_X"/>
-
- <xsl:variable name="mpmcBifName_">
- <xsl:choose>
- <xsl:when test=" (@IS_SBSCONN)"><xsl:value-of select="BUSCONN/@BUSINTERFACE"/></xsl:when>
- <xsl:when test="not(@IS_SBSCONN)"><xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $mpmcInst_)]/BUSINTERFACE[(@BUSNAME = $busName_)]/@NAME"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $mpmcInst_)]/BUSINTERFACE[(@BUSNAME = $busName_)]/@NAME"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>MPMC Bif Name <xsl:value-of select="$mpmcBifName_"/></xsl:message>
- <xsl:message>Bif Side <xsl:value-of select="$bifSide_"/></xsl:message>
- <xsl:message>Bus Name <xsl:value-of select="@BUSNAME"/></xsl:message>
- <xsl:message>Instance <xsl:value-of select="$bifInst_"/></xsl:message>
- <xsl:message>Space line x <xsl:value-of select="$space_line_X_"/></xsl:message>
--->
- <xsl:variable name="space_line_X_">
- <xsl:call-template name="F_Calc_Space_X">
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_X_" select="($BLKD_INNER_X + $G_Total_Bridges_W + $space_line_X_)"/>
-
- <xsl:variable name = "stackToWest_W_">
- <xsl:choose>
- <xsl:when test="(($stackToEast_ = '0') and ($stackToWest_ = 'NONE'))">0</xsl:when>
- <xsl:when test="(($stackToEast_ = 'NONE') and not($stackToWest_ = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="$stackToWest_"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:when test="(not($stackToEast_ = '0') and not($stackToEast_ = 'NONE') and ($stackToWest_ = 'NONE'))">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="($stackToEast_ - 1)"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name = "stackToEast_W_">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="$stackToEast_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name ="extSpaceWest_W_" select="ceiling($stackToWest_W_ div 2)"/>
- <xsl:variable name ="extSpaceEast_W_" select="ceiling($stackToEast_W_ div 2)"/>
- <xsl:variable name="laneInSpace_X_">
- <xsl:choose>
- <xsl:when test="(@ORIENTED = 'EAST')">
- <xsl:value-of select="($extSpaceWest_W_ + (@BUSLANE_X * $BLKD_BUS_LANE_W) - $BLKD_BUS_ARROW_W - $BLKD_P2P_BUS_W)"/>
-<!--
- <xsl:value-of select="($extSpaceWest_W_ + (@BUSLANE_X * $BLKD_BUS_LANE_W) - $BLKD_BUS_LANE_W - $BLKD_BUS_ARROW_W - $BLKD_P2P_BUS_W)"/>
--->
- </xsl:when>
- <xsl:otherwise><xsl:value-of select="($extSpaceWest_W_ + (@BUSLANE_X * $BLKD_BUS_LANE_W))"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="lane_X_" select="($space_X_ + $laneInSpace_X_)"/>
-
- <xsl:variable name="mpmcBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $mpmcInst_)]/BUSINTERFACE[(@NAME = $mpmcBifName_)]/@TYPE"/>
-
- <!--
- <xsl:variable name="bc_X_" select="($lane_X_ + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/>
- <xsl:variable name="bc_X_" select="($lane_X_ + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/>
- <xsl:variable name="bc_X_" select="($lane_X_ + ceiling($BLKD_BIFC_W div 2))"/>
- -->
-
- <xsl:variable name="bc_Y_" select="($BLKD_INNER_Y + $BLKD_MPMC_MOD_H)"/>
- <xsl:variable name="bc_X_" >
- <xsl:choose>
- <xsl:when test="($bifSide_ = '0')"><xsl:value-of select="($lane_X_ + ceiling($BLKD_BIFC_W div 2))"/></xsl:when>
- <xsl:when test="($bifSide_ = '1')"><xsl:value-of select="($lane_X_ + $BLKD_BIFC_dx)"/></xsl:when>
- <xsl:otherwise> <xsl:value-of select="($lane_X_ + ceiling($BLKD_BIFC_W div 2))"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
- </xsl:variable>
-
- <!-- Place the MPMC bif label -->
- <xsl:variable name="bcl_X_" select="($bc_X_ + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BIF_W div 2))"/>
- <xsl:variable name="bcl_Y_" select="($bc_Y_ - $BLKD_BIF_H - $BLKD_MOD_BIF_GAP_H)"/>
- <use x="{$bcl_X_}" y="{$bcl_Y_}" xlink:href="#{@BUSSTD}_BifLabel"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($bcl_X_ + ceiling($BLKD_BIF_W div 2))"/>
- <xsl:with-param name="iY" select="($bcl_Y_ + ceiling($BLKD_BIF_H div 2) + 3)"/>
- <xsl:with-param name="iText" select="$mpmcBifName_"/>
- <xsl:with-param name="iClass" select="'mpmc_biflabel'"/>
- </xsl:call-template>
-
- <!-- Place the MPMC bif -->
- <use x="{$bc_X_}" y="{$bc_Y_}" xlink:href="#{@BUSSTD}_busconn_{$mpmcBifType_}"/>
-<!--
--->
-
- <xsl:variable name="bcArrow_X_" select="($bc_X_ + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_H div 2))"/>
- <xsl:variable name="bcArrow_Y_" select="($bc_Y_ + $BLKD_BIFC_H - 3)"/>
-
- <!-- Place the MPMC Arrow -->
- <use x="{$bcArrow_X_}" y="{$bcArrow_Y_}" xlink:href="#{@BUSSTD}_BusArrowNorth"/>
-
- <!--
- Place a block to cover the gap btw MPMC and top of Bus Lane Space, or to the correct SBS
- For non SBS connections a vertical block will already have been drawn to the top of the
- space.
- -->
-
- <xsl:variable name="sbsDy_">
- <xsl:choose>
- <xsl:when test="@IS_SBSCONN"><xsl:value-of select="2 + ($G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/@BUS_INDEX * $BLKD_SBS_LANE_H)"/></xsl:when>
- <xsl:when test="not(@IS_SBSCONN)">0</xsl:when>
- <xsl:otherwise>0></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="mpmcBusHeight_">
- <xsl:choose>
- <xsl:when test="(@IS_SBSCONN)"><xsl:value-of select="($G_SharedBus_Y - ($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4) + $sbsDy_)"/></xsl:when>
- <xsl:when test="not(@IS_SBSCONN)">
- <xsl:choose>
- <xsl:when test="($space_y_ >= ($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4 + $sbsDy_))">
- <xsl:value-of select="($space_y_ - ($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4 + $sbsDy_))"/>
- </xsl:when>
- <xsl:when test="($space_y_ < ($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4 + $sbsDy_))">
- <xsl:value-of select="(($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4 + $sbsDy_) - $space_y_)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:when>
- <xsl:otherwise><xsl:value-of select="$BLKD_BIFC_H"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <rect x="{$bcArrow_X_ + $BLKD_BUS_ARROW_G}"
- y="{$bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4}"
- width= "{$BLKD_P2P_BUS_W}"
- height="{$mpmcBusHeight_}"
- style="stroke:none; fill:{$busColor_}"/>
-
- <!-- place the bus label here -->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($bcArrow_X_ + $BLKD_BUS_ARROW_W + 6)"/>
- <xsl:with-param name="iY" select="($bcArrow_Y_ + ceiling($mpmcBusHeight_ div 2) + 6)"/>
- <xsl:with-param name="iText" select="$busName_"/>
- <xsl:with-param name="iClass" select="'p2pbus_label'"/>
- </xsl:call-template>
-
- </xsl:for-each>
- </xsl:for-each>
-
-</xsl:template>
-
-
-<!-- ======================================================================= -->
-<!-- FUNCTION TEMPLATE -->
-<!-- -->
-<!-- Draw bus lane spaces on the Block Diagram -->
-<!-- ======================================================================= -->
-<xsl:template name="Draw_BlkDiagram_BusLaneSpaces">
-
- <xsl:variable name="lastStack_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH) - 1"/>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[@EAST]">
- <xsl:sort select="@EAST" data-type="number"/>
-
- <xsl:call-template name="Draw_BlkDiagram_BusLaneSpace">
- <xsl:with-param name="iStackToEast" select="@EAST"/>
- </xsl:call-template>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@WEST = $lastStack_)]">
- <xsl:call-template name="Draw_BlkDiagram_BusLaneSpace">
- <xsl:with-param name="iStackToWest" select="$lastStack_"/>
- </xsl:call-template>
- </xsl:for-each>
-
-</xsl:template>
-
-<xsl:template name="Draw_BlkDiagram_BusLaneSpace">
-
- <xsl:param name="iStackToEast" select="'NONE'"/>
- <xsl:param name="iStackToWest" select="'NONE'"/>
-
- <xsl:variable name="spaceAbvSbs_H_">
- <xsl:call-template name="F_Calc_Space_AbvSbs_Height">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="spaceBlwSbs_H_">
- <xsl:call-template name="F_Calc_Space_BlwSbs_Height">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_line_x_">
- <xsl:call-template name="F_Calc_Space_X">
- <xsl:with-param name="iStackToEast" select="$iStackToEast"/>
- <xsl:with-param name="iStackToWest" select="$iStackToWest"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="space_y_" select="($G_SharedBus_Y - $spaceAbvSbs_H_ - $BLKD_PROC2SBS_GAP)"/>
- <xsl:variable name="space_x_" select="($BLKD_INNER_X + $G_Total_Bridges_W + $space_line_x_)"/>
-
- <xsl:variable name="stackToEast_">
- <xsl:choose>
- <xsl:when test="not($iStackToEast = 'NONE')"><xsl:value-of select="$iStackToEast"/></xsl:when>
- <xsl:otherwise>NONE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="stackToWest_">
- <xsl:choose>
- <xsl:when test=" not($iStackToWest = 'NONE')"><xsl:value-of select="$iStackToWest"/></xsl:when>
- <xsl:when test="(not($iStackToEast = 'NONE') and not($iStackToEast = '0'))"><xsl:value-of select="($iStackToEast - 1)"/></xsl:when>
- <xsl:otherwise>NONE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="space_Name_">
- <xsl:call-template name="F_generate_Space_Name">
- <xsl:with-param name="iStackToEast" select="$stackToEast_"/>
- <xsl:with-param name="iStackToWest" select="$stackToWest_"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>StackToEast is <xsl:value-of select="$iStackToEast"/></xsl:message>
- <xsl:message>StackToWest is <xsl:value-of select="$iStackToWest"/></xsl:message>
- <xsl:message>SpaceName is <xsl:value-of select="$space_Name_"/></xsl:message>
--->
-
- <use x="{$space_x_}" y="{$space_y_}" xlink:href="#{$space_Name_}"/>
-
-</xsl:template>
-
-
-<!-- =========================================================================== -->
-<!-- FUNCTION TEMPLATE -->
-<!-- -->
-<!-- Draw Bridges on the Block Diagram -->
-<!-- =========================================================================== -->
-<xsl:template name="Draw_BlkDiagram_Bridges">
-
- <!-- First save all the bridge indexs in a variable -->
- <xsl:variable name="bridgeShapes_">
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE/BUSCONNS[(@ORIENTED = 'WEST')]/BUSCONN">
- <BRIDGE BUS_INDEX="{@BUS_INDEX}" INSTANCE="{../../@INSTANCE}" POSITION="{(position() -1)}"/>
- <BRIDGECONN BUS_INDEX="{@BUS_INDEX}" INSTANCE="{../../@INSTANCE}" ORIENTED="{../@ORIENTED}" POSITION="{(position() - 1)}" BUSSTD="{@BUSSTD}" TYPE="{@TYPE}"/>
- <!-- So both bus conns have same position.... -->
- <xsl:if test="../../BUSCONNS[(@ORIENTED = 'EAST')]">
- <BRIDGECONN BUS_INDEX="{../../BUSCONNS[(@ORIENTED ='EAST')]/BUSCONN/@BUS_INDEX}" INSTANCE="{../../@INSTANCE}" ORIENTED="EAST" POSITION="{(position() - 1)}" BUSSTD="{../../BUSCONNS[(@ORIENTED = 'EAST')]/BUSCONN/@BUSSTD}" TYPE="{../../BUSCONNS[(@ORIENTED = 'EAST')]/BUSCONN/@TYPE}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:variable>
-<!--
- <xsl:message>Found an east connection on <xsl:value-of select="../../@INSTANCE"/></xsl:message>
--->
- <!-- Now layout the bridge shapes between the shared busses -->
- <xsl:for-each select="exsl:node-set($bridgeShapes_)/BRIDGE">
- <xsl:sort select="@POSITION" data-type="number"/>
-
- <xsl:variable name="brdgPosition_" select="@POSITION"/>
- <xsl:variable name="brdgInstance_" select="@INSTANCE"/>
-
- <xsl:variable name="min_bus_idx_" select="math:min(exsl:node-set($bridgeShapes_)/BRIDGECONN[(@POSITION = $brdgPosition_)]/@BUS_INDEX)"/>
-<!--
- <xsl:variable name="max_bus_idx_" select="math:max(exsl:node-set($bridgeShapes_)/BRIDGECONN[(@POSITION = $brdgPosition_)]/@BUS_INDEX)"/>
-
- <xsl:message>Maximum index <xsl:value-of select="$max_bus_idx_"/></xsl:message>
- <xsl:message>Minimum index <xsl:value-of select="$min_bus_idx_"/></xsl:message>
--->
-
-
- <xsl:variable name="brdg_X_" select="($BLKD_INNER_X + $BLKD_BRIDGE_GAP + $BLKD_BUS_LANE_W + (@POSITION * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))))"/>
- <xsl:variable name="brdg_Y_" select="($G_SharedBus_Y + ($min_bus_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_SBS_LANE_H div 2) - ceiling($BLKD_MOD_H div 2))"/>
-
- <use x="{$brdg_X_}" y="{$brdg_Y_}" xlink:href="#symbol_{$brdgInstance_}"/>
- </xsl:for-each>
-
-
-
-<!--
- <xsl:message>Found <xsl:value-of select="count(exsl:node-set($bridgeShapes_)/BRIDGECONN)"/> busconns </xsl:message>
- <xsl:message>Drawing connection for bridge <xsl:value-of select="$brdgInstance_"/> at <xsl:value-of select="@POSITION"/> </xsl:message>
--->
-
- <xsl:for-each select="exsl:node-set($bridgeShapes_)/BRIDGECONN">
- <xsl:sort select="@POSITION" data-type="number"/>
-
- <xsl:variable name="brdgInstance_" select="@INSTANCE"/>
- <xsl:variable name="brdgPosition_" select="@POSITION"/>
-
- <xsl:variable name="busColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="min_bus_idx_" select="math:min(exsl:node-set($bridgeShapes_)/BRIDGECONN[(@POSITION = $brdgPosition_)]/@BUS_INDEX)"/>
- <xsl:variable name="brdg_Y1_" select="($G_SharedBus_Y + ($min_bus_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_SBS_LANE_H div 2) - ceiling($BLKD_MOD_H div 2))"/>
- <xsl:variable name="brdg_X_" select="($BLKD_INNER_X + $BLKD_BRIDGE_GAP + $BLKD_BUS_LANE_W + (@POSITION * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))))"/>
-
- <xsl:variable name="bc_Y_" select="$brdg_Y1_ + $BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2)"/>
- <xsl:variable name="bc_X_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="($brdg_X_ - $BLKD_BIFC_W)"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="($brdg_X_ + $BLKD_MOD_W)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <!-- Layout the bus conn -->
- <use x="{$bc_X_}" y="{$bc_Y_}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/>
-
- <!-- Figure out the positions of the lines -->
-
-<!--
- <xsl:variable name="vert_line_x_" select="$bc_X_ + ceiling($BLKD_BIFC_W div 2)"/>
- <xsl:message>vert line x <xsl:value-of select="$vert_line_x_"/></xsl:message>
- <xsl:message>bus index <xsl:value-of select="@BUS_INDEX"/></xsl:message>
--->
-
- <xsl:variable name="vert_line_x_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="($bc_X_ - ($BLKD_BUS_LANE_W - $BLKD_BIFC_W))"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="($bc_X_ + ($BLKD_BUS_LANE_W - $BLKD_P2P_BUS_W))"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <!-- At least one of the points is going to be the bus -->
-<!--
- <xsl:variable name="vert_line_y1_" select="($G_SharedBus_Y + $BLKD_PROC2SBS_GAP + (@BUS_INDEX * $BLKD_SBS_LANE_H))"/>
--->
- <xsl:variable name="vert_line_y1_" select="($G_SharedBus_Y + (@BUS_INDEX * $BLKD_SBS_LANE_H))"/>
- <xsl:variable name="vert_line_y2_" select="$bc_Y_ + ceiling($BLKD_BIFC_H div 2)"/>
-
- <xsl:variable name="v_bus_ul_y_">
- <xsl:choose>
- <xsl:when test="$vert_line_y1_ > $vert_line_y2_">
- <xsl:value-of select="$vert_line_y2_"/>
- </xsl:when>
- <xsl:when test="$vert_line_y2_ > $vert_line_y1_">
- <xsl:value-of select="$vert_line_y1_"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-<!--
- <xsl:variable name="v_bus_ul_x_" select="$vert_line_x_"/>
--->
- <xsl:variable name="v_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="($vert_line_x_ + $BLKD_MOD_BIF_GAP_H)"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="($vert_line_x_ - $BLKD_MOD_BIF_GAP_H)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="v_bus_height_">
- <xsl:choose>
- <xsl:when test="$vert_line_y1_ > $vert_line_y2_">
- <xsl:value-of select="($vert_line_y1_ - $vert_line_y2_)"/>
- </xsl:when>
- <xsl:when test="$vert_line_y2_ > $vert_line_y1_">
- <xsl:value-of select="($vert_line_y2_ - $vert_line_y1_)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_x_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="($bc_X_ - ($BLKD_BUS_LANE_W - $BLKD_BIFC_W) + $BLKD_MOD_BIF_GAP_H)"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="($bc_X_ + $BLKD_BIFC_W - ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2))"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="h_bus_ul_y_" select="$bc_Y_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
-
- <xsl:variable name="h_bus_width_">
- <xsl:choose>
- <xsl:when test="@ORIENTED='WEST'">
- <xsl:value-of select="(($bc_X_ + ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2)) - $h_bus_ul_x_ + 1)"/>
- </xsl:when>
- <xsl:when test="@ORIENTED='EAST'">
- <xsl:value-of select="(($v_bus_ul_x_ + $BLKD_P2P_BUS_W) - $h_bus_ul_x_)"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-
-<!--
- <xsl:message>vert line y1 <xsl:value-of select="$vert_line_y1_"/></xsl:message>
--->
-
- <rect x="{$v_bus_ul_x_}"
- y="{$v_bus_ul_y_ + 2}"
- width= "{$v_bus_width_}"
- height="{$v_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-
- <rect x="{$h_bus_ul_x_}"
- y="{$h_bus_ul_y_}"
- width= "{$h_bus_width_}"
- height="{$h_bus_height_}"
- style="stroke:none; fill:{$busColor_}"/>
-
- </xsl:for-each>
-
-</xsl:template>
-
-
-
-
-<!-- =========================================================================== -->
-<!-- FUNCTION TEMPLATE -->
-<!-- -->
-<!-- Draw the IP Bucket -->
-<!-- =========================================================================== -->
-<xsl:template name="Draw_BlkDiagram_IPBucket">
-
- <!-- Draw IP Bucket -->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET">
-
- <xsl:variable name="bucket_w_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/>
- <xsl:variable name="bucket_h_" select="(($BLKD_MOD_BKTLANE_H * 2) + (($BLKD_MOD_H * @MODS_H) + ($BLKD_MOD_BUCKET_G * (@MODS_H - 1))))"/>
-
- <xsl:variable name="bucket_x_" select="(ceiling($G_Total_Blkd_W div 2) - ceiling($bucket_w_ div 2))"/>
- <xsl:variable name="bucket_y_" select="($G_SharedBus_Y + $G_Total_SharedBus_H + $G_Max_Stack_BlwSbs_H + $BLKD_SBS2IP_GAP)"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="$bucket_x_"/>
- <xsl:with-param name="iY" select="($bucket_y_ - 4)"/>
- <xsl:with-param name="iText" select="'IP'"/>
- <xsl:with-param name="iClass" select="'bkt_label'"/>
- </xsl:call-template>
-
- <use x="{$bucket_x_}" y="{$bucket_y_}" xlink:href="#ipbucket"/>
-
- </xsl:for-each>
-
-</xsl:template>
-
-
-<xsl:template name="Draw_BlkDiagram_Key">
- <use x="{ceiling($G_Total_Blkd_W div 2) - ceiling($BLKD_KEY_W div 2)}" y="0" xlink:href="#BlkDiagram_Key"/>
-</xsl:template>
-
-<xsl:template name="Define_BlkDiagram_Key">
-
- <xsl:variable name="key_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'KEY'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="key_lt_col_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="'KEY'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <g id="KEY_IntrCntrl">
- <rect
- x="0"
- y="0"
- rx="3"
- ry="3"
- width= "{ceiling($BLKD_INTR_W div 2)}"
- height="{$BLKD_INTR_H}" style="fill:{$key_lt_col_}; stroke:none; stroke-width:1"/>
-
- <line x1="0"
- y1="{ceiling($BLKD_INTR_H div 4)}"
- x2="{ceiling($BLKD_INTR_W div 2)}"
- y2="{ceiling($BLKD_INTR_H div 4)}"
- style="stroke:{$COL_BLACK};stroke-width:2"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="1.5"/>
- <xsl:with-param name="iY" select="(7 + ceiling($BLKD_INTR_H div 2))"/>
- <xsl:with-param name="iText" select="'x'"/>
- <xsl:with-param name="iClass" select="'intr_symbol'"/>
- </xsl:call-template>
-
- </g>
-
- <g id="KEY_IntrdProc">
- <rect
- x="0"
- y="0"
- rx="3"
- ry="3"
- width= "{ceiling($BLKD_INTR_W div 2)}"
- height="{$BLKD_INTR_H}" style="fill:{$key_lt_col_}; stroke:none; stroke-width:1"/>
-
- <line x1="0"
- y1="{ceiling($BLKD_INTR_H div 4) - 2}"
- x2="{ceiling($BLKD_INTR_W div 2)}"
- y2="{ceiling($BLKD_INTR_H div 4) - 2}"
- style="stroke:{$COL_BLACK};stroke-width:1"/>
-
- <line x1="0"
- y1="{ceiling($BLKD_INTR_H div 4) + 2}"
- x2="{ceiling($BLKD_INTR_W div 2)}"
- y2="{ceiling($BLKD_INTR_H div 4) + 2}"
- style="stroke:{$COL_BLACK};stroke-width:1"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="1.5"/>
- <xsl:with-param name="iY" select="(7 + ceiling($BLKD_INTR_H div 2))"/>
- <xsl:with-param name="iText" select="'x'"/>
- <xsl:with-param name="iClass" select="'intr_symbol'"/>
- </xsl:call-template>
- </g>
-
- <g id="KEY_IntrSrc">
- <rect
- x="0"
- y="0"
- rx="3"
- ry="3"
- width= "{$BLKD_INTR_W}"
- height="{ceiling($BLKD_INTR_H div 2)}" style="fill:{$key_lt_col_}; stroke:none; stroke-width:1"/>
-
- <line x1="{ceiling($BLKD_INTR_W div 2)}"
- y1="0"
- x2="{ceiling($BLKD_INTR_W div 2)}"
- y2="{ceiling($BLKD_INTR_H div 2)}"
- style="stroke:{$COL_BLACK};stroke-width:1"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'2'"/>
- <xsl:with-param name="iY" select="'7'"/>
- <xsl:with-param name="iText" select="'y'"/>
- <xsl:with-param name="iClass" select="'intr_symbol'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(2 + ceiling($BLKD_INTR_W div 2))"/>
- <xsl:with-param name="iY" select="'7'"/>
- <xsl:with-param name="iText" select="'x'"/>
- <xsl:with-param name="iClass" select="'intr_symbol'"/>
- </xsl:call-template>
- </g>
-
-
- <g id="BlkDiagram_Key">
- <rect
- x="0"
- y="0"
- width= "{$BLKD_KEY_W}"
- height="{$BLKD_KEY_H}"
- style="fill:{$COL_BG}; stroke:none;"/>
-
- <rect x="0"
- y="0"
- width= "{$BLKD_KEY_W}"
- height="16"
- style="fill:{$COL_BG}; stroke:none;"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_KEY_W div 2)"/>
- <xsl:with-param name="iY" select="'14'"/>
- <xsl:with-param name="iText" select="'KEY'"/>
- <xsl:with-param name="iClass" select="'key_title'"/>
- </xsl:call-template>
-
- <rect x="0"
- y="16"
- width= "{$BLKD_KEY_W}"
- height="16"
- style="fill:{$COL_BG_LT}; stroke:none;"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_KEY_W div 2)"/>
- <xsl:with-param name="iY" select="'30'"/>
- <xsl:with-param name="iText" select="'SYMBOLS'"/>
- <xsl:with-param name="iClass" select="'key_header'"/>
- </xsl:call-template>
-
- <use x="32" y="47" xlink:href="#KEY_BifLabel" transform="scale(0.75)"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'12'"/>
- <xsl:with-param name="iY" select="'60'"/>
- <xsl:with-param name="iText" select="'bus interface'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <use x="20" y="68" xlink:href="#KEY_SharedBus"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'12'"/>
- <xsl:with-param name="iY" select="'89'"/>
- <xsl:with-param name="iText" select="'shared bus'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
-
-<!--
- ==================================
- BUS CONNECTIONS
- ==================================
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'110'"/>
- <xsl:with-param name="iY" select="'47'"/>
- <xsl:with-param name="iText" select="'Bus connections'"/>
- <xsl:with-param name="iClass" select="'key_label_ul'"/>
- </xsl:call-template>
-
- <use x="110" y="58" xlink:href="#KEY_busconn_MASTER"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'140'"/>
- <xsl:with-param name="iY" select="'72'"/>
- <xsl:with-param name="iText" select="'master or initiator'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <use x="110" y="{58 + (($BLKD_BIFC_H + 4) * 1)}" xlink:href="#KEY_busconn_SLAVE"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'140'"/>
- <xsl:with-param name="iY" select="(72 + (($BLKD_BIFC_H + 4) * 1))"/>
- <xsl:with-param name="iText" select="'slave or target'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <use x="110" y="{58 + (($BLKD_BIFC_H + 4) * 2)}" xlink:href="#KEY_busconn_MASTER_SLAVE"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'140'"/>
- <xsl:with-param name="iY" select="(72 + (($BLKD_BIFC_H + 4) * 2))"/>
- <xsl:with-param name="iText" select="'master slave'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
-
- <use x="110" y="{58 + (($BLKD_BIFC_H + 4) * 3)}" xlink:href="#KEY_busconn_MONITOR"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'140'"/>
- <xsl:with-param name="iY" select="(72 + (($BLKD_BIFC_H + 4) * 3))"/>
- <xsl:with-param name="iText" select="'monitor'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
-<!--
- ==================================
- EXTERNAL PORTS
- ==================================
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'258'"/>
- <xsl:with-param name="iY" select="'47'"/>
- <xsl:with-param name="iText" select="'External Ports'"/>
- <xsl:with-param name="iClass" select="'key_label_ul'"/>
- </xsl:call-template>
-
- <use x="258" y="58" xlink:href="#KEY_INPort"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'288'"/>
- <xsl:with-param name="iY" select="'72'"/>
- <xsl:with-param name="iText" select="'input'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <use x="258" y="{58 + ($BLKD_IOP_H * 1) + 4}" xlink:href="#KEY_OUTPort"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'288'"/>
- <xsl:with-param name="iY" select="(72 + ($BLKD_IOP_H * 1) + 4)"/>
- <xsl:with-param name="iText" select="'output'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <use x="258" y="{58 + ($BLKD_IOP_H * 2) + 8}" xlink:href="#KEY_INOUTPort"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'288'"/>
- <xsl:with-param name="iY" select="(72 + ($BLKD_IOP_H * 2) + 8)"/>
- <xsl:with-param name="iText" select="'inout'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
-
-<!--
- ==================================
- INTERRUPTS
- ==================================
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'380'"/>
- <xsl:with-param name="iY" select="'47'"/>
- <xsl:with-param name="iText" select="'Interrupts'"/>
- <xsl:with-param name="iClass" select="'key_label_ul'"/>
- </xsl:call-template>
-
- <use x="380" y="58" xlink:href="#KEY_IntrCntrl"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'396'"/>
- <xsl:with-param name="iY" select="'64'"/>
- <xsl:with-param name="iText" select="'Interrupt'"/>
- <xsl:with-param name="iClass" select="'key_label_small'"/>
- </xsl:call-template>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'396'"/>
- <xsl:with-param name="iY" select="'74'"/>
- <xsl:with-param name="iText" select="'Controller'"/>
- <xsl:with-param name="iClass" select="'key_label_small'"/>
- </xsl:call-template>
-
-
- <use x="380" y="88" xlink:href="#KEY_IntrdProc"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'396'"/>
- <xsl:with-param name="iY" select="'94'"/>
- <xsl:with-param name="iText" select="'Interrupt'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'396'"/>
- <xsl:with-param name="iY" select="'104'"/>
- <xsl:with-param name="iText" select="'Target'"/>
- <xsl:with-param name="iClass" select="'key_label_small'"/>
- </xsl:call-template>
-
-
- <use x="380" y="118" xlink:href="#KEY_IntrSrc"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'400'"/>
- <xsl:with-param name="iY" select="'124'"/>
- <xsl:with-param name="iText" select="'Interrupt'"/>
- <xsl:with-param name="iClass" select="'key_label_small'"/>
- </xsl:call-template>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'400'"/>
- <xsl:with-param name="iY" select="'134'"/>
- <xsl:with-param name="iText" select="'Source'"/>
- <xsl:with-param name="iClass" select="'key_label_small'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'360'"/>
- <xsl:with-param name="iY" select="'146'"/>
- <xsl:with-param name="iText" select="'X = Controller ID'"/>
- <xsl:with-param name="iClass" select="'key_label_small'"/>
- </xsl:call-template>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'360'"/>
- <xsl:with-param name="iY" select="'156'"/>
- <xsl:with-param name="iText" select="'Y = Interrupt Priority'"/>
- <xsl:with-param name="iClass" select="'key_label_small'"/>
- </xsl:call-template>
-
-<!--
- ==================================
- COLORS
- ==================================
--->
- <rect x="0"
- y="160"
- width= "{$BLKD_KEY_W}"
- height="16"
- style="fill:{$COL_BG_LT}; stroke:none;"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_KEY_W div 2)"/>
- <xsl:with-param name="iY" select="'172'"/>
- <xsl:with-param name="iText" select="'COLORS'"/>
- <xsl:with-param name="iClass" select="'key_header'"/>
- </xsl:call-template>
-
-<!--
- <text class="keylblul"
- x="110"
- y="190">Bus Standards</text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="'110'"/>
- <xsl:with-param name="iY" select="'190'"/>
- <xsl:with-param name="iText" select="'Bus Standard'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <xsl:variable name="dcr_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'DCR'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 0)}"
- y="200"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$dcr_col_}; stroke:none;"/>
-
-<!--
- <text class="keylabel"
- x="{12 + $BLKD_BIFC_W + 4}"
- y="{200 + (($BLKD_BIF_H + 4) * 1)}">DCR</text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + $BLKD_BIFC_W + 4)"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/>
- <xsl:with-param name="iText" select="'DCR'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <xsl:variable name="fcb_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'FCB'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 0)}"
- y="{200 + (($BLKD_BIFC_H + 4) * 1)}"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$fcb_col_}; stroke:none;"/>
-
-<!--
- <text class="keylabel"
- x="{12 + $BLKD_BIFC_W + 4}"
- y="{200 + (($BLKD_BIF_H + 4) * 2)}">FCB</text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + $BLKD_BIFC_W + 4)"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 2))"/>
- <xsl:with-param name="iText" select="'FCB'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <xsl:variable name="fsl_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'FSL'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 1)}"
- y="200"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$fsl_col_}; stroke:none;"/>
-<!--
- <text class="keylabel"
- x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 1)}"
- y="{200 + (($BLKD_BIF_H + 4) * 1)}">FSL</text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 1))"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/>
- <xsl:with-param name="iText" select="'FSL'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <xsl:variable name="col_lmb_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'LMB'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 1)}"
- y="{200 + (($BLKD_BIFC_H + 4) * 1)}"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$col_lmb_}; stroke:none;"/>
-<!--
- <text class="keylabel"
- x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 1)}"
- y="{200 + (($BLKD_BIF_H + 4) * 2)}">LMB</text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 1))"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 2))"/>
- <xsl:with-param name="iText" select="'LMB'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <xsl:variable name="opb_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'OPB'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect
- x="{12 + ((12 + $BLKD_BIFC_W + 36) * 2)}"
- y="200"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$opb_col_}; stroke:none;"/>
-<!--
- <text class="keylabel"
- x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 2)}"
- y="{200 + (($BLKD_BIF_H + 4) * 1)}">OPB</text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 2))"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/>
- <xsl:with-param name="iText" select="'OPB'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
- <xsl:variable name="plb_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'PLB'"/>
- </xsl:call-template>
- </xsl:variable>
- <rect
- x="{12 + ((12 + $BLKD_BIFC_W + 36) * 2)}"
- y="{200 + (($BLKD_BIFC_H + 4) * 1)}"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$plb_col_}; stroke:none;"/>
-<!--
- <text class="keylabel"
- x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 2)}"
- y="{200 + (($BLKD_BIF_H + 4) * 2)}">PLB</text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 2))"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 2))"/>
- <xsl:with-param name="iText" select="'PLB'"/>
- <xsl:with-param name="iClass" select="'key_header'"/>
- </xsl:call-template>
-
-
- <xsl:variable name="ocm_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'OCM'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect
- x="{12 + ((12 + $BLKD_BIFC_W + 36) * 3)}"
- y="200"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$ocm_col_}; stroke:none;"/>
-<!--
- <text class="keylabel"
- x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 3)}"
- y="{200 + (($BLKD_BIF_H + 4) * 1)}">SOCM</text>
- -->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 3))"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/>
- <xsl:with-param name="iText" select="'SOCM'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
-
- <xsl:variable name="xil_p2p_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'XIL'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect
- x="{12 + ((12 + $BLKD_BIFC_W + 36) * 3)}"
- y="{200 + (($BLKD_BIFC_H + 4) * 1)}"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$xil_p2p_col_}; stroke:none;"/>
-<!--
- <text class="keylabel"
- x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 3)}"
- y="{200 + (($BLKD_BIF_H + 4) * 2)}">Xilinx P2P</text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 3))"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 2))"/>
- <xsl:with-param name="iText" select="'Xilinx P2P'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
-
- <xsl:variable name="user_p2p_col_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'USER'"/>
- </xsl:call-template>
- </xsl:variable>
-
- <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 4)}"
- y="200"
- width= "{$BLKD_BIFC_H}"
- height="{$BLKD_BIFC_W}"
- style="fill:{$user_p2p_col_}; stroke:none;"/>
-<!--
- <text class="keylabel"
- x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 4)}"
- y="{200 + (($BLKD_BIF_H + 4) * 1)}">USER P2P</text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 4))"/>
- <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/>
- <xsl:with-param name="iText" select="'USER P2P'"/>
- <xsl:with-param name="iClass" select="'key_label'"/>
- </xsl:call-template>
-
-
-</g>
-</xsl:template>
-
-<xsl:template name="Define_BlkDiagram_Specs">
-
- <xsl:param name="iArch" select="'NA'"/>
- <xsl:param name="iPart" select="'NA'"/>
- <xsl:param name="iTimeStamp" select="'NA'"/>
- <xsl:param name="iEdkVersion" select="'NA'"/>
-
- <g id="BlkDiagram_Specs">
- <rect
- x="0"
- y="0"
- width= "{$BLKD_SPECS_W}"
- height="{$BLKD_SPECS_H}"
- style="fill:{$COL_BG}; stroke:none;"/>
-
- <rect
- x="0"
- y="0"
- width= "{$BLKD_SPECS_W}"
- height="16"
- style="fill:{$COL_BG}; stroke:none;"/>
-<!--
- ==================================
- SPEC HEADER
- ==================================
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'key_title'"/>
- <xsl:with-param name="iX" select="ceiling($BLKD_SPECS_W div 2)"/>
- <xsl:with-param name="iY" select="'14'"/>
- <xsl:with-param name="iText" select="'SPECS'"/>
- </xsl:call-template>
-<!--
- <text class="keytitle"
- x="{ceiling($BLKD_SPECS_W div 2)} "
- y="14">SPECS</text>
--->
-
-<!--
- ==================================
- EDK VERSION
- ==================================
--->
- <rect x="0"
- y="20"
- width= "{$BLKD_SPECS_W}"
- height="16"
- style="fill:{$COL_BG_LT}; stroke:none;"/>
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'blkd_spec_name'"/>
- <xsl:with-param name="iX" select="'4'"/>
- <xsl:with-param name="iY" select="'32'"/>
- <xsl:with-param name="iText" select="'EDK VERSION'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'blkd_spec_value_mid'"/>
- <xsl:with-param name="iX" select="($BLKD_SPECS_W + 1) - ceiling($BLKD_SPECS_W div 5)"/>
- <xsl:with-param name="iY" select="'32'"/>
- <xsl:with-param name="iText" select="$iEdkVersion"/>
- </xsl:call-template>
-
-<!--
- ==================================
- ARCH
- ==================================
--->
- <rect x="0"
- y="40"
- width= "{$BLKD_SPECS_W}"
- height="16"
- style="fill:{$COL_BG_LT}; stroke:none;"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'blkd_spec_name'"/>
- <xsl:with-param name="iX" select="'4'"/>
- <xsl:with-param name="iY" select="'52'"/>
- <xsl:with-param name="iText" select="'ARCH'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'blkd_spec_value_mid'"/>
- <xsl:with-param name="iX" select="($BLKD_SPECS_W + 1) - ceiling($BLKD_SPECS_W div 5)"/>
- <xsl:with-param name="iY" select="'52'"/>
- <xsl:with-param name="iText" select="$iArch"/>
- </xsl:call-template>
-
-<!--
- <text class="specsvalue"
- x="{($BLKD_SPECS_W + 1) - (string-length($blkd_arch) * 6.5)}"
- y="52"><xsl:value-of select="$blkd_arch"/></text>
- <text class="specsvaluemid"
- x="{($BLKD_SPECS_W + 1) - ceiling($BLKD_SPECS_W div 5)}"
- y="52"><xsl:value-of select="$iArch"/></text>
--->
-
-<!--
- ==================================
- PART
- ==================================
--->
- <rect x="0"
- y="60"
- width= "{$BLKD_SPECS_W}"
- height="16"
- style="fill:{$COL_BG_LT}; stroke:none;"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'blkd_spec_name'"/>
- <xsl:with-param name="iX" select="'4'"/>
- <xsl:with-param name="iY" select="'72'"/>
- <xsl:with-param name="iText" select="'PART'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'blkd_spec_value_mid'"/>
- <xsl:with-param name="iX" select="($BLKD_SPECS_W + 1) - ceiling($BLKD_SPECS_W div 5)"/>
- <xsl:with-param name="iY" select="'72'"/>
- <xsl:with-param name="iText" select="$iPart"/>
- </xsl:call-template>
-
-<!--
- ==================================
- TIMESTAMP
- ==================================
--->
-
- <rect x="0"
- y="80"
- width= "{$BLKD_SPECS_W}"
- height="16"
- style="fill:{$COL_BG_LT}; stroke:none;"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'blkd_spec_name'"/>
- <xsl:with-param name="iX" select="'4'"/>
- <xsl:with-param name="iY" select="'92'"/>
- <xsl:with-param name="iText" select="'GENERATED'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iClass" select="'blkd_spec_value_mid'"/>
- <xsl:with-param name="iX" select="($BLKD_SPECS_W + 1) - (string-length($iTimeStamp) * 3.5)"/>
- <xsl:with-param name="iY" select="'92'"/>
- <xsl:with-param name="iText" select="$iTimeStamp"/>
- </xsl:call-template>
- </g>
-</xsl:template>
-
-
-</xsl:stylesheet>
-
-<!-- =========================================================================== -->
-<!-- FUNCTION TEMPLATE -->
-<!-- -->
-<!-- =========================================================================== -->
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<!--
-<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
- doctype-public="-//W3C//DTD SVG 1.0//EN"
- doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
-
-<xsl:variable name="INF_H" select="$BIF_H + ceiling($BIF_H div 2)"/>
-<xsl:variable name="INF_W" select="($BIF_W * 2) + $BIF_GAP"/>
--->
-
-
-<!-- ======================= DEF FUNCTIONS =================================== -->
-<xsl:template name="Define_IPBucket">
-
- <xsl:for-each select="BLKDIAGRAM/IPBUCKET">
-
- <xsl:for-each select="MODULE">
- <xsl:sort data-type="text" select="@MODTYPE" order="ascending"/>
-
- <xsl:call-template name="Define_IPBucketModule">
- <xsl:with-param name="iIPType" select="@MODTYPE"/>
- <xsl:with-param name="iIPName" select="@INSTANCE"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
- <g id="ipbucket">
- <xsl:variable name="bucket_w_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/>
- <xsl:variable name="bucket_h_" select="(($BLKD_MOD_BKTLANE_H * 2) + (($BLKD_MOD_H * @MODS_H) + ($BLKD_MOD_BUCKET_G * (@MODS_H - 1))))"/>
-
- <rect x="0"
- y="0"
- rx="4"
- ry="4"
- width= "{$bucket_w_}"
- height="{$bucket_h_}"
- style="stroke-width:2; stroke:{$COL_BLACK}; fill:{$COL_IORING_LT}"/>
-
- <xsl:variable name="bkt_mods_w_" select="@MODS_W"/>
-
- <xsl:for-each select="MODULE">
-
- <xsl:variable name="clm_" select="(( position() - 1) mod $bkt_mods_w_)"/>
- <xsl:variable name="row_" select="floor((position() - 1) div $bkt_mods_w_)"/>
-
- <xsl:variable name="bk_x_" select="$BLKD_MOD_BKTLANE_W + ($clm_ * ($BLKD_MOD_W + $BLKD_MOD_BUCKET_G))"/>
- <xsl:variable name="bk_y_" select="$BLKD_MOD_BKTLANE_H + ($row_ * ($BLKD_MOD_H + $BLKD_MOD_BUCKET_G))"/>
-
-
- <use x="{$bk_x_}"
- y="{$bk_y_}"
- xlink:href="#ipbktmodule_{@INSTANCE}"/>
-
-
- </xsl:for-each>
-
- </g>
-
-</xsl:for-each>
-</xsl:template>
-
-
-<xsl:template name="Define_UNKBucket">
-
- <xsl:for-each select="BLKDIAGRAM/UNKBUCKET">
-
- <g id="unkbucket">
- <xsl:variable name="bucket_w_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/>
- <xsl:variable name="bucket_h_" select="(($BLKD_MOD_BKTLANE_H * 2) + (($BLKD_MOD_H * @MODS_H) + ($BLKD_MOD_BUCKET_G * (@MODS_H - 1))))"/>
-
- <rect x="0"
- y="0"
- rx="4"
- ry="4"
- width= "{$bucket_w_}"
- height="{$bucket_h_}"
- style="stroke-width:2; stroke:{$COL_BLACK}; fill:{$COL_BG_UNK}"/>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@IS_PROMOTED and @IS_PENALIZED)]">
-
- <xsl:variable name="bkt_mods_w_" select="@MODS_W"/>
-
- <xsl:variable name="mod_row_" select="@BKTROW"/>
- <xsl:variable name="row_mods_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/BKTROW[(@INDEX = $mod_row_)]/@MODS_H"/>
-
-<!--
- <xsl:message>The row module is <xsl:value-of select="@BKTROW"/></xsl:message>
- <xsl:message>The height of the module is <xsl:value-of select="$row_mods_h_"/></xsl:message>
--->
-
- <xsl:variable name="bk_x_" select="$BLKD_MOD_BKTLANE_W + (@MODS_X * ($BLKD_MOD_W + $BLKD_MOD_BUCKET_G))"/>
- <xsl:variable name="bk_y_" select="$BLKD_MOD_BKTLANE_H + ($row_mods_h_ * ($BLKD_MOD_H + $BLKD_MOD_BUCKET_G))"/>
-
- <use x="{$bk_x_}"
- y="{$bk_y_}"
- xlink:href="#symbol_unkmodule_{@BKTROW}_{@MODS_X}"/>
-<!--
--->
-
- </xsl:for-each>
-
-
- </g>
-
- </xsl:for-each>
-</xsl:template>
-
-
-<xsl:template name="Define_SBSBuckets">
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET">
-
- <xsl:variable name="busStd_" select="@BUSSTD"/>
- <xsl:variable name="busName_" select="@BUSNAME"/>
-<!--
- <xsl:variable name="busStd_" select="BUSCONNS/BUSCONN/@BUSSTD"/>
--->
- <xsl:variable name="bus_conn_w_" select="BUSCONNS/@BUSLANE_W"/>
-
-
- <xsl:variable name="bktColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="bktBgColor_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <xsl:for-each select="MODULE">
-
- <xsl:sort data-type="text" select="@MODTYPE" order="ascending"/>
-
- <xsl:call-template name="Define_SBSBucketModule">
- <xsl:with-param name="iBifType" select="$busStd_"/>
- <xsl:with-param name="iIPType" select="@MODTYPE"/>
- <xsl:with-param name="iIPName" select="@INSTANCE"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
- <g id="sbsbucket_{$busName_}">
- <xsl:variable name="bucket_w_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/>
- <xsl:variable name="bucket_h_" select="(($BLKD_MOD_BKTLANE_H * 2) + ((($BLKD_MOD_H + $BLKD_BIFC_H) * @MODS_H) + ($BLKD_MOD_BUCKET_G * (@MODS_H - 1))))"/>
-
- <rect x="0"
- y="0"
- rx="4"
- ry="4"
- width= "{$bucket_w_}"
- height="{$bucket_h_}"
- style="stroke-width:2; stroke:{$bktColor_}; fill:{$bktBgColor_}"/>
-
- <xsl:variable name="bkt_mods_w_" select="@MODS_W"/>
-
- <xsl:for-each select="MODULE">
-
- <xsl:sort data-type="text" select="@MODTYPE" order="ascending"/>
-
- <xsl:variable name="clm_" select="(( position() - 1) mod $bkt_mods_w_)"/>
- <xsl:variable name="row_" select="floor((position() - 1) div $bkt_mods_w_)"/>
-
- <xsl:variable name="bk_x_" select="$BLKD_MOD_BKTLANE_W + ($clm_ * ($BLKD_MOD_W + $BLKD_MOD_BUCKET_G))"/>
- <xsl:variable name="bk_y_" select="$BLKD_MOD_BKTLANE_H + ($row_ * ($BLKD_MOD_H + $BLKD_BIFC_H + $BLKD_MOD_BUCKET_G))"/>
-
- <!-- Lay out the module in the bucket -->
- <use x="{$bk_x_}" y="{$bk_y_}" xlink:href="#sbsbktmodule_{@INSTANCE}"/>
-
- <!-- Add its connection to the piece shared bus -->
- <xsl:variable name="h_bus_y_" select="$bk_y_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
-
-<!--
- <xsl:variable name="h_bus_x_" select="$bk_x_ - ($BLKD_MOD_BUCKET_G + ceiling($BLKD_MOD_W div 2))"/>
--->
- <xsl:variable name="h_bus_x_">
- <xsl:choose>
- <xsl:when test="($clm_ = '0')">0</xsl:when>
-
- <xsl:when test="not($clm_ = '0')">
- <xsl:value-of select="$bk_x_ - ($BLKD_MOD_BUCKET_G + ceiling($BLKD_MOD_W div 2))"/>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:variable name="h_bus_y_" select="$bk_y_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W)"/>
- <xsl:message>h bus x <xsl:value-of select="$h_bus_x_"/></xsl:message>
- <xsl:message>h bus y <xsl:value-of select="$h_bus_y_"/></xsl:message>
--->
- <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="h_bus_width_" select="($bk_x_ - $h_bus_x_ + ceiling($BLKD_MOD_W div 2))"/>
-
- <rect x="{$h_bus_x_}"
- y="{$h_bus_y_}"
- width= "{$h_bus_width_}"
- height="{$BLKD_P2P_BUS_W}"
- style="fill:{$bktColor_}"/>
-
- </xsl:for-each>
-
- <xsl:variable name="num_sbsbktmods_" select="count(MODULE)"/>
- <xsl:variable name="num_sbsbktrows_" select="ceiling($num_sbsbktmods_ div $BLKD_BKT_MODS_PER_ROW)"/>
-
- <!-- If there is more than one row, connect the rows with a vertical bar -->
- <xsl:if test="($num_sbsbktrows_ > 1)">
-
- <xsl:variable name="v_bus_x_" select="$BLKD_MOD_BKTLANE_W + ($BLKD_MOD_W + $BLKD_MOD_BUCKET_G)"/>
-
- <xsl:variable name="bkt_top_" select="$BLKD_MOD_BKTLANE_H + (0 * ($BLKD_MOD_H + $BLKD_BIFC_H + $BLKD_MOD_BUCKET_G))"/>
- <xsl:variable name="bkt_bot_" select="$BLKD_MOD_BKTLANE_H + (($num_sbsbktrows_ - 1) * ($BLKD_MOD_H + $BLKD_BIFC_H + $BLKD_MOD_BUCKET_G))"/>
-
- <xsl:variable name="v_bus_y_top_" select="$bkt_top_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
- <xsl:variable name="v_bus_y_bot_" select="$bkt_bot_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/>
-
- <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/>
- <xsl:variable name="v_bus_height_" select="($v_bus_y_bot_ - $v_bus_y_top_)"/>
- <rect x="0"
- y="{$v_bus_y_top_}"
- width= "{$v_bus_width_}"
- height="{$v_bus_height_}"
- style="fill:{$bktColor_}"/>
- </xsl:if>
-
- </g>
-
- </xsl:for-each>
-
-</xsl:template>
-
-
-<xsl:template name="Define_SBSBucketModule">
-
- <xsl:param name="iBusStd" select="'PLB46'"/>
- <xsl:param name="iIPName" select="'_ipType_'"/>
- <xsl:param name="iIPType" select="'_ipName_'"/>
-
-<!--
- <xsl:message>The IPType is <xsl:value-of select="$iIPType"/> </xsl:message>
--->
- <xsl:variable name="bif_y_">
- <xsl:value-of select="$BLKD_MOD_LANE_H + $BLKD_BIFC_H"/>
- </xsl:variable>
-
- <xsl:variable name="label_y_">
- <xsl:value-of select="$BLKD_MOD_LANE_H + $BLKD_BIF_H + $BLKD_BIFC_H + $BLKD_MOD_BIF_GAP_V"/>
- </xsl:variable>
-
- <xsl:variable name="modBgColor_">
- <xsl:choose>
- <xsl:when test="$iIPType = 'mpmc'"><xsl:value-of select="$COL_MPMC_BG"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="$COL_BG"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <g id="sbsbktmodule_{$iIPName}">
-
- <rect x="0"
- y="{$BLKD_BIFC_H}"
- rx="6"
- ry="6"
- width = "{$BLKD_MOD_W}"
- height= "{$BLKD_MOD_H}"
- style="fill:{$modBgColor_}; stroke:{$COL_WHITE}; stroke-width:2"/>
-
- <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
- y="{$label_y_}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_MOD_LABEL_H}"
- style="fill:{$COL_WHITE}; stroke:none;"/>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE=$iIPName)]/@GROUP">
-
- <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
- y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) - 2}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_BIF_H}"
- style="fill:{$COL_IORING_LT}; stroke:none;"/>
-
-<!--
- <text class="ioplblgrp"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12}">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"/>
- </text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12)"/>
- <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"/>
- <xsl:with-param name="iClass" select="'iogrp_label'"/>
- </xsl:call-template>
-
- </xsl:if>
-
-<!--
- <text class="bciptype"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + 8}">
- <xsl:value-of select="$iIPType"/>
- </text>
-
- <text class="bciplabel"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + 16}">
- <xsl:value-of select="$iIPName"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + 8)"/>
- <xsl:with-param name="iText" select="$iIPType"/>
- <xsl:with-param name="iClass" select="'bc_iptype'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + 18)"/>
- <xsl:with-param name="iText" select="$iIPName"/>
- <xsl:with-param name="iClass" select="'bc_ipinst'"/>
- </xsl:call-template>
-
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/BUSINTERFACE[(@IS_INMHS = 'TRUE')]">
-
- <xsl:variable name="bifBusStd_">
- <xsl:choose>
- <xsl:when test="@BUSSTD">
- <xsl:value-of select="@BUSSTD"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="'USER'"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bifName_">
- <xsl:choose>
- <xsl:when test="string-length(@NAME) <= 5">
- <xsl:value-of select="@NAME"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="substring(@NAME,0,5)"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bif_x_" select="ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_BIF_W div 2)"/>
-
- <!-- Draw the BIF -->
- <use x="{$bif_x_}" y="{$bif_y_}" xlink:href="#{$bifBusStd_}_BifLabel"/>
-
-
- <!-- Draw the BIF connection -->
- <use x="{$bif_x_ + ceiling($BLKD_BIF_W div 2) - ceiling($BLKD_BIFC_W div 2)}" y="{$bif_y_ - $BLKD_BIFC_H - $BLKD_MOD_LANE_H}" xlink:href="#{$bifBusStd_}_busconn_{@TYPE}"/>
-
-<!--
- <text class="bif_label"
- x="{$bif_x_ + ceiling($BLKD_BIF_W div 2)}"
- y="{$bif_y_ + ceiling($BLKD_BIF_H div 2) + 3}">
- <xsl:value-of select="$bifName_"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($bif_x_ + ceiling($BLKD_BIF_W div 2))"/>
- <xsl:with-param name="iY" select="($bif_y_ + ceiling($BLKD_BIF_H div 2) + 3)"/>
- <xsl:with-param name="iText" select="$bifName_"/>
- <xsl:with-param name="iClass" select="'bif_label'"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/INTERRUPTINFO[(@TYPE = 'CONTROLLER')]">
-
- <xsl:variable name="intcIdx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE=$iIPName)]/INTERRUPTINFO[(@TYPE = 'CONTROLLER')]/@INTC_INDEX"/>
-
- <xsl:variable name="intrColor_">
- <xsl:call-template name="F_IntcIdx2RGB">
- <xsl:with-param name="iIntcIdx" select="$intcIdx_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:call-template name="F_draw_InterruptCntrl">
- <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/>
- <xsl:with-param name="iIntr_Y" select="3 + $BLKD_BIFC_H"/>
- <xsl:with-param name="iIntr_COL" select="$intrColor_"/>
- <xsl:with-param name="iIntr_IDX" select="$intcIdx_"/>
- </xsl:call-template>
- </xsl:if>
-
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/INTERRUPTINFO[(@TYPE = 'SOURCE')]/TARGET">
-<!--
- <xsl:variable name="intcIdx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE=$iIPName)]/INTERRUPTINFO[(@TYPE = 'SOURCE')]/@INTC_INDEX"/>
--->
- <xsl:variable name="intrColor_">
- <xsl:call-template name="F_IntcIdx2RGB">
- <xsl:with-param name="iIntcIdx" select="@INTC_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:call-template name="F_draw_InterruptSource">
- <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - $BLKD_INTR_W)"/>
- <xsl:with-param name="iIntr_Y" select="((position() - 1) * (ceiling($BLKD_INTR_H div 2) + 3)) + $BLKD_BIFC_H"/>
- <xsl:with-param name="iIntr_COL" select="$intrColor_"/>
- <xsl:with-param name="iIntr_PRI" select="@PRIORITY"/>
- <xsl:with-param name="iIntr_IDX" select="@INTC_INDEX"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
- </g>
-
-</xsl:template>
-
-<xsl:template name="Define_IPBucketModule">
-
- <xsl:param name="iIPType" select="'_ip_type_'"/>
- <xsl:param name="iIPName" select="'_ip_name_'"/>
-
- <xsl:variable name="bif_y_">
- <xsl:value-of select="$BLKD_MOD_LANE_H"/>
- </xsl:variable>
-
- <xsl:variable name="label_y_">
- <xsl:value-of select="(ceiling($BLKD_MOD_H div 2) - ceiling($BLKD_MOD_LABEL_H div 2))"/>
- </xsl:variable>
-
- <g id="ipbktmodule_{$iIPName}">
-
- <rect x="0"
- y="0"
- rx="6"
- ry="6"
- width = "{$BLKD_MOD_W}"
- height= "{$BLKD_MOD_H}"
- style="fill:{$COL_BG}; stroke:{$COL_BLACK}; stroke-width:2"/>
-
- <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
- y="{$label_y_}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_MOD_LABEL_H}"
- style="fill:{$COL_WHITE}; stroke:none;"/>
-<!--
- y="{$label_y_ + ceiling($BLKD_MOD_LABEL_H div 2) - 4}"
- y="{$label_y_ + ceiling($BLKD_MOD_LABEL_H div 2) + 4}"
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + 8)"/>
- <xsl:with-param name="iText" select="$iIPType"/>
- <xsl:with-param name="iClass" select="'bc_iptype'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + 20)"/>
- <xsl:with-param name="iText" select="$iIPName"/>
- <xsl:with-param name="iClass" select="'bc_ipinst'"/>
- </xsl:call-template>
-
-<!--
- <text class="bc_iptype"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + 8}">
- <xsl:value-of select="$iIPType"/>
- </text>
-
- <text class="bc_ipinst"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + 16}">
- <xsl:value-of select="$iIPName"/>
- </text>
--->
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP">
-
- <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
- y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) - 2}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_BIF_H}"
- style="fill:{$COL_IORING_LT}; stroke:none;"/>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12)"/>
- <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"/>
- <xsl:with-param name="iClass" select="'iogrp_label'"/>
- </xsl:call-template>
-
- <!--
- <text class="iogrp_label"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12}">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"/>
- </text>
- -->
-
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/INTERRUPTINFO[(@TYPE = 'SOURCE')]">
-
- <xsl:variable name="intrColor_">
- <xsl:call-template name="F_IntcIdx2RGB">
- <xsl:with-param name="iIntcIdx" select="@INTC_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:call-template name="F_draw_InterruptSource">
- <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - $BLKD_INTR_W)"/>
- <xsl:with-param name="iIntr_Y" select="((position() - 1) * (ceiling($BLKD_INTR_H div 2) + 3))"/>
- <xsl:with-param name="iIntr_COL" select="$intrColor_"/>
- <xsl:with-param name="iIntr_PRI" select="@PRIORITY"/>
- <xsl:with-param name="iIntr_IDX" select="@INTC_INDEX"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
- </g>
-
-</xsl:template>
-
-
-<xsl:template name="Define_Peripheral">
-<!--
- when the module is oriented normal its label goes above the bifs
- when the module is oriented rot180, (part of a processor memory
- controller for example) its label goes below the bifs
--->
-
- <xsl:param name="iModVori" select="'normal'"/>
- <xsl:param name="iModInst" select="'_instance_'"/>
- <xsl:param name="iModType" select="'_modtype_'"/>
- <xsl:param name="iUnkInst" select="'_unknown_'"/>
- <xsl:param name="iHorizIdx" select="'_unknown_'"/>
- <xsl:param name="iVertiIdx" select="'_unknown_'"/>
-
-<!--
- <xsl:message>Stack Y <xsl:value-of select="$cstkMods_Y"/></xsl:message>
- <xsl:message>Stack Index Y <xsl:value-of select="$cstkIndex"/></xsl:message>
--->
-
- <xsl:variable name="modName_">
- <xsl:choose>
- <xsl:when test="$iUnkInst = '_unknown_'">
- <xsl:value-of select="$iModInst"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$iUnkInst"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="modSymbolName_">
- <xsl:choose>
- <xsl:when test="(not($iHorizIdx = '_unknown_') and not($iVertiIdx = '_unknown_'))">
- <xsl:call-template name="F_generate_Stack_SymbolName">
- <xsl:with-param name="iHorizIdx" select="$iHorizIdx"/>
- <xsl:with-param name="iVertiIdx" select="$iVertiIdx"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:otherwise>symbol_<xsl:value-of select="$modName_"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="modTypeName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@MODTYPE"/>
-
-<!--
- <xsl:message>The symbol type of the module is <xsl:value-of select="$modTypeName_"/></xsl:message>
- <xsl:message>The symbol name of the module is <xsl:value-of select="$modSymbolName_"/></xsl:message>
--->
-
- <xsl:variable name="bifs_h_">
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H) and not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H)">0</xsl:if>
-
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H)">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H"/>
- </xsl:if>
-
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H)">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H"/>
- </xsl:if>
- </xsl:variable>
-
- <xsl:variable name="label_y_">
- <xsl:choose>
- <xsl:when test="$iModVori = 'rot180'">
- <xsl:value-of select="($BLKD_MOD_LANE_H + (($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $bifs_h_))"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$BLKD_MOD_LANE_H"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bif_dy_">
- <xsl:choose>
- <xsl:when test="$iModVori = 'rot180'">
- <xsl:value-of select="$BLKD_MOD_LANE_H"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V)"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="peri_stroke_col_">
- <xsl:choose>
- <xsl:when test="((@MODCLASS = 'MASTER_SLAVE') or (@MODCLASS = 'MONITOR')) and BUSCONNS/BUSCONN">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="BUSCONNS/BUSCONN/@BUSSTD"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:value-of select="$COL_WHITE"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="modHeight_">
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="$modName_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <g id="{$modSymbolName_}">
-
- <xsl:if test="$modTypeName_ = 'mpmc'">
- <rect x="0"
- y="0"
- rx="6"
- ry="6"
- width = "{$BLKD_MOD_W}"
- height= "{$modHeight_}"
- style="fill:{$COL_MPMC_BG}; stroke:{$peri_stroke_col_}; stroke-width:2"/>
- </xsl:if>
-
- <xsl:if test="not($modTypeName_ = 'mpmc')">
- <rect x="0"
- y="0"
- rx="6"
- ry="6"
- width = "{$BLKD_MOD_W}"
- height= "{$modHeight_}"
- style="fill:{$COL_BG}; stroke:{$peri_stroke_col_}; stroke-width:2"/>
- </xsl:if>
-
-
- <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
- y="{$label_y_}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_MOD_LABEL_H}"
- style="fill:{$COL_WHITE}; stroke:none;"/>
-
-<!--
- y="{$label_y_ + ceiling($BLKD_MOD_LABEL_H div 2) - 4}">
- y="{$label_y_ + ceiling($BLKD_MOD_LABEL_H div 2) + 4}">
--->
-<!--
- <text class="bc_iptype"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + 8}">
- <xsl:value-of select="$iModType"/>
- </text>
-
- <text class="bc_ipinst"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + 16}">
- <xsl:value-of select="$iModInst"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + 8)"/>
- <xsl:with-param name="iText" select="$iModType"/>
- <xsl:with-param name="iClass" select="'bc_iptype'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + 16)"/>
- <xsl:with-param name="iText" select="$iModInst"/>
- <xsl:with-param name="iClass" select="'bc_ipinst'"/>
- </xsl:call-template>
-
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[@INSTANCE=$iModInst]/@GROUP">
-
- <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
- y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) - 2}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_BIF_H}"
- style="fill:{$COL_IORING_LT}; stroke:none;"/>
-
-<!--
- <text class="iogrp_label"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12}">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[@INSTANCE=$iModInst]/@GROUP"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12)"/>
- <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@GROUP"/>
- <xsl:with-param name="iClass" select="'iogrp_label'"/>
- </xsl:call-template>
-
-
- </xsl:if>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/BUSINTERFACE[(@BIF_X and @BIF_Y and not(@BUSNAME = '__NOC__'))]">
-
- <xsl:variable name="bifBusStd_">
- <xsl:choose>
- <xsl:when test="@BUSSTD">
- <xsl:value-of select="@BUSSTD"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="'TRS'"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bif_y_">
- <xsl:value-of select="(($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y)"/>
- </xsl:variable>
-
- <xsl:variable name="bif_buscol_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$bifBusStd_"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <xsl:variable name="bifName_">
- <xsl:choose>
- <xsl:when test="not(@NAME)">'UNK'</xsl:when>
- <xsl:when test="string-length(@NAME) <= 5">
- <xsl:value-of select="@NAME"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="substring(@NAME,0,5)"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bif_x_" >
- <xsl:if test="not(@ORIENTED='CENTER')">
- <xsl:value-of select="(($BLKD_BIF_W * @BIF_X) + ($BLKD_MOD_BIF_GAP_H * @BIF_X) + ($BLKD_MOD_LANE_W * 1))"/>
- </xsl:if>
- <xsl:if test="(@ORIENTED='CENTER')">
- <xsl:value-of select="ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_BIF_W div 2)"/>
- </xsl:if>
- </xsl:variable>
-
- <xsl:if test="not(@IS_INTCONN)">
- <xsl:variable name="horz_line_y_" select="($bif_y_ + $bif_dy_ + ceiling($BLKD_BIFC_H div 2))"/>
-
- <xsl:variable name="horz_line_x1_">
- <xsl:choose>
- <xsl:when test="@BIF_X = '0'">0</xsl:when>
- <xsl:otherwise><xsl:value-of select="($BLKD_MOD_W - $BLKD_MOD_LANE_W)"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="horz_line_x2_">
- <xsl:choose>
- <xsl:when test="@BIF_X = '0'"><xsl:value-of select="$BLKD_MOD_LANE_W"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="$BLKD_MOD_W + 1"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <line x1="{$horz_line_x1_}"
- y1="{$horz_line_y_ - 2}"
- x2="{$horz_line_x2_}"
- y2="{$horz_line_y_ - 2}"
- style="stroke:{$bif_buscol_};stroke-width:1"/>
-
- </xsl:if>
-
- <use x="{$bif_x_}" y="{$bif_y_ + $bif_dy_}" xlink:href="#{$bifBusStd_}_BifLabel"/>
-<!--
- <text class="bif_label"
- x="{$bif_x_ + ceiling($BLKD_BIF_W div 2)}"
- y="{$bif_y_ + $bif_dy_ + ceiling($BLKD_BIF_H div 2) + 3}">
- <xsl:value-of select="$bifName_"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($bif_x_ + ceiling($BLKD_BIF_W div 2))"/>
- <xsl:with-param name="iY" select="($bif_y_ + $bif_dy_ + ceiling($BLKD_BIF_H div 2) + 3)"/>
-
- <xsl:with-param name="iText" select="$bifName_"/>
- <xsl:with-param name="iClass" select="'bif_label'"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
-<!--
- <xsl:if test="@INTC_INDEX">
- <xsl:variable name="intrColor_">
- <xsl:call-template name="F_IntcIdx2RGB">
- <xsl:with-param name="intcIdx" select="@INTC_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:call-template name="F_draw_InterruptCntrl">
- <xsl:with-param name="intr_col" select="$intrColor_"/>
- <xsl:with-param name="intr_x" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/>
- <xsl:with-param name="intr_y" select="3"/>
- <xsl:with-param name="intr_idx" select="@INTC_INDEX"/>
- </xsl:call-template>
- </xsl:if>
--->
- <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@INTC_INDEX">
- <xsl:variable name="intrColor_">
- <xsl:call-template name="F_IntcIdx2RGB">
- <xsl:with-param name="iIntcIdx" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@INTC_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:call-template name="F_draw_InterruptCntrl">
- <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/>
- <xsl:with-param name="iIntr_Y" select="3"/>
- <xsl:with-param name="iIntr_COL" select="$intrColor_"/>
- <xsl:with-param name="iIntr_IDX" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@INTC_INDEX"/>
- </xsl:call-template>
- </xsl:if>
-
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/INTERRUPTINFO[@TYPE ='TARGET']">
-
- <xsl:variable name="intrColor_">
- <xsl:call-template name="F_IntcIdx2RGB">
- <xsl:with-param name="iIntcIdx" select="@INTC_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:call-template name="F_draw_InterruptSource">
- <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - $BLKD_INTR_W)"/>
- <xsl:with-param name="iIntr_Y" select="((position() - 1) * (ceiling($BLKD_INTR_H div 2) + 3))"/>
- <xsl:with-param name="iIntr_COL" select="$intrColor_"/>
- <xsl:with-param name="iIntr_PRI" select="@PRIORITY"/>
- <xsl:with-param name="iIntr_IDX" select="@INTC_INDEX"/>
- </xsl:call-template>
-
- </xsl:for-each>
- </g>
-</xsl:template>
-
-<xsl:template name="Define_MemoryUnit">
- <xsl:param name="iShapeId" select="1000"/>
-
- <xsl:variable name="horiz_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/@STACK_HORIZ_INDEX"/>
- <xsl:variable name="is_multistk_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/@IS_MULTISTK"/>
-
- <xsl:choose>
- <xsl:when test="(($is_multistk_ = 'TRUE') or ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $horiz_idx_)]))">
- <xsl:call-template name="Define_Processor_MemoryUnit">
- <xsl:with-param name="iShapeId" select="$iShapeId"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:call-template name="Define_StandAlone_MemoryUnit">
- <xsl:with-param name="iShapeId" select="$iShapeId"/>
- </xsl:call-template>
- </xsl:otherwise>
-
- </xsl:choose>
-
-</xsl:template>
-
-
-<xsl:template name="Define_Processor_MemoryUnit">
- <xsl:param name="iShapeId" select="1000"/>
-
-<!--
- <xsl:param name="cstkIndex" select="'_processor_'"/>
--->
-
- <xsl:variable name="mods_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/@MODS_H"/>
- <xsl:variable name="mods_w_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/@MODS_W"/>
- <xsl:variable name="memW_" select="($BLKD_MOD_W * $mods_w_)"/>
- <xsl:variable name="memH_" select="($BLKD_MOD_H * $mods_h_)"/>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]">
-
- <!-- first define its symbols as individual modules -->
- <xsl:for-each select="MODULE[(@MODCLASS = 'MEMORY')]">
-
- <xsl:variable name="modInst_" select="@INSTANCE"/>
- <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/>
-
- <xsl:call-template name="Define_Peripheral">
- <xsl:with-param name="iModVori" select="'normal'"/>
- <xsl:with-param name="iModInst" select="$modInst_"/>
- <xsl:with-param name="iModType" select="$modType_"/>
- </xsl:call-template>
- </xsl:for-each>
-
- <xsl:for-each select="MODULE[@MODCLASS='MEMORY_CNTLR']">
-
- <xsl:variable name="modInst_" select="@INSTANCE"/>
- <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/>
-
- <xsl:call-template name="Define_Peripheral">
- <xsl:with-param name="iModVori" select="'rot180'"/>
- <xsl:with-param name="iModInst" select="$modInst_"/>
- <xsl:with-param name="iModType" select="$modType_"/>
- </xsl:call-template>
- </xsl:for-each>
- </xsl:for-each>
-
-<!--
--->
-
- <xsl:variable name="symbol_name_">
- <xsl:call-template name="F_generate_Stack_SymbolName">
- <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>The mp stack name is <xsl:value-of select="$mp_stack_name_"/></xsl:message>
--->
-
- <g id="{$symbol_name_}">
-
- <rect x="0"
- y="0"
- rx="6"
- ry="6"
- width = "{$memW_}"
- height= "{$memH_}"
- style="fill:{$COL_BG}; stroke:{$COL_WHITE}; stroke-width:2"/>
-
- <!-- Draw the memory block-->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY')]">
-
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="{ceiling($memW_ div 2) - ($BLKD_MOD_W div 2)}"
- y="0"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[((@MODCLASS='MEMORY_CNTLR') and (@ORIENTED = 'WEST'))]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="0"
- y="{$BLKD_MOD_H}"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[((@MODCLASS='MEMORY_CNTLR') and (@ORIENTED = 'EAST'))]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="{$BLKD_MOD_W}"
- y="{$BLKD_MOD_H}"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[((@MODCLASS='MEMORY_CNTLR') and (@ORIENTED = 'CENTER'))]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="{ceiling($memW_ div 2) - ($BLKD_MOD_W div 2)}"
- y="{$BLKD_MOD_H}"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
- </g>
-
-</xsl:template>
-
-
-<xsl:template name="Define_StandAlone_MemoryUnit">
-
- <xsl:param name="iShapeId" select="0"/>
-
- <xsl:variable name="mods_h_" select="@MODS_H"/>
- <xsl:variable name="mods_w_" select="@MODS_W"/>
-
- <xsl:variable name="memcName_" select="MODULE[not(@MODCLASS = 'MEMORY')]/@INSTANCE"/>
- <xsl:variable name="memcBusStd_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE/BUSCONNLANE[(BUSCONN[(@INSTANCE = $memcName_)])]/@BUSSTD"/>
-
-<!--
- <xsl:variable name="memcBusStd_" select="/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE/BUSCONNLANE/@BUSSTD"/>
- <xsl:variable name="memcBusStd_" select="/EDKSYSTEM/BCLANESPACES/BCLANESPACE/BUSCONNLANE[(BUSCONN[(@INSTANCE)])]/@BUSSTD"/>
- <xsl:message>Memory cntlr name <xsl:value-of select="$memcName_"/></xsl:message>
- <xsl:message>Memory cntlr name <xsl:value-of select="$memcName_"/></xsl:message>
- <xsl:message>Memory cntlr busstd <xsl:value-of select="$memcBusStd_"/></xsl:message>
--->
-
- <xsl:variable name="peri_col_">
-
- <xsl:choose>
- <xsl:when test="$mods_w_ > 1">
- <xsl:value-of select="$COL_BG"/>
- </xsl:when>
-
- <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE/BUSCONNLANE[(BUSCONN[(@INSTANCE = $memcName_)])]/@BUSSTD">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$memcBusStd_"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="'TRS'"/>
- </xsl:call-template>
- </xsl:otherwise>
- </xsl:choose>
-
- </xsl:variable>
-
- <!-- first define its symbols as individual modules -->
- <xsl:for-each select="MODULE[(@MODCLASS = 'MEMORY')]">
-
- <xsl:variable name="modInst_" select="@INSTANCE"/>
- <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/>
-
- <xsl:call-template name="Define_Peripheral">
- <xsl:with-param name="iModVori" select="'rot180'"/>
- <xsl:with-param name="iModInst" select="$modInst_"/>
- <xsl:with-param name="iModType" select="$modType_"/>
- </xsl:call-template>
- </xsl:for-each>
-
- <xsl:for-each select="MODULE[not(@MODCLASS='MEMORY')]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
- <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/>
-
-<!--
- <xsl:message>Memory cntlr inst <xsl:value-of select="$modInst_"/></xsl:message>
--->
- <xsl:call-template name="Define_Peripheral">
- <xsl:with-param name="iModVori" select="'normal'"/>
- <xsl:with-param name="iModInst" select="$modInst_"/>
- <xsl:with-param name="iModType" select="$modType_"/>
- </xsl:call-template>
- </xsl:for-each>
-
- <xsl:variable name="memW_" select="($BLKD_MOD_W * $mods_w_)"/>
- <xsl:variable name="memH_" select="($BLKD_MOD_H * $mods_h_)"/>
-
- <xsl:variable name="symbol_name_">
- <xsl:call-template name="F_generate_Stack_SymbolName">
- <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <g id="{$symbol_name_}">
-
- <rect x="0"
- y="0"
- rx="6"
- ry="6"
- width = "{$memW_ + 4}"
- height= "{$memH_ + 4}"
- style="fill:{$peri_col_}; stroke:{$peri_col_}; stroke-width:2"/>
-
-
- <!-- Draw the memory block-->
- <xsl:choose>
-
- <xsl:when test="$mods_w_ = 1">
-
- <xsl:for-each select="MODULE[(@MODCLASS='MEMORY')]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="2"
- y="{$BLKD_MOD_H + 2}"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
-
- <!-- Draw the memory controllers-->
- <xsl:for-each select="MODULE[not(@MODCLASS='MEMORY')]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="2"
- y="0"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
- </xsl:when>
-
- <xsl:when test="$mods_w_ > 1">
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY')]">
-
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="{ceiling($memW_ div 2) - ($BLKD_MOD_W div 2)}"
- y="{$BLKD_MOD_H + 2}"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(not(@MODCLASS='MEMORY') and (@ORIENTED = 'WEST'))]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="0"
- y="0"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(not(@MODCLASS='MEMORY') and (@ORIENTED = 'EAST'))]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="{$BLKD_MOD_W}"
- y="0"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(not(@MODCLASS='MEMORY') and (@ORIENTED = 'CENTER'))]">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
-
- <use x="{ceiling($memW_ div 2) - ($BLKD_MOD_W div 2)}"
- y="0"
- xlink:href="#symbol_{$modInst_}"/>
- </xsl:for-each>
-
- </xsl:when>
- </xsl:choose>
-
- </g>
-
-</xsl:template>
-
-
-<xsl:template name="Define_StandAlone_MPMC">
-
-<!--
- <xsl:param name="drawarea_w" select="500"/>
- <xsl:param name="drawarea_h" select="500"/>
--->
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE">
-
- <xsl:variable name="mpmcInst_" select="@INSTANCE"/>
- <xsl:variable name="mpmcType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[@INSTANCE=$mpmcInst_]/@MODTYPE"/>
-<!--
- <xsl:message>Drawing instance <xsl:value-of select="$mpmcInst_"/></xsl:message>
--->
-
- <xsl:variable name="mpmc_w_" select="($G_Total_DrawArea_W - ($BLKD_INNER_GAP * 2))"/>
- <xsl:variable name="label_y_" select="ceiling($BLKD_MPMC_MOD_H div 2) - ceiling($BLKD_MOD_LABEL_H div 2)"/>
-
- <g id="mpmcmodule_{$mpmcInst_}">
- <rect x="0"
- y="0"
- width = "{$mpmc_w_}"
- height= "{$BLKD_MPMC_MOD_H}"
- style="fill:{$COL_MPMC_BG}; stroke:{$COL_BLACK}; stroke-width:2"/>
-
- <rect x="{$BLKD_MOD_LANE_H}"
- y="{$label_y_}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_MOD_LABEL_H}"
- style="fill:{$COL_WHITE}; stroke:none;"/>
-<!--
- <text class="bc_iptype"
- x="{ceiling(($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_W) div 2)}"
- y="{$label_y_ + 8}">
- <xsl:value-of select="$mpmcType_"/>
- </text>
-
- <text class="bc_ipinst"
- x="{ceiling(($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_W) div 2)}"
- y="{$label_y_ + 16}">
- <xsl:value-of select="$mpmcInst_"/>
- </text>
-
- <text class="mpmc_title"
- x="{ceiling($mpmc_w_ div 2)}"
- y="{$label_y_ + 16}">MPMC Module Interface</text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(ceiling(($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_W) div 2))"/>
- <xsl:with-param name="iY" select="($label_y_ + 8)"/>
- <xsl:with-param name="iText" select="$mpmcType_"/>
- <xsl:with-param name="iClass" select="'bc_iptype'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="(ceiling(($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_W) div 2))"/>
- <xsl:with-param name="iY" select="($label_y_ + 16)"/>
- <xsl:with-param name="iText" select="$mpmcInst_"/>
- <xsl:with-param name="iClass" select="'bc_ipinst'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($mpmc_w_ div 2)"/>
- <xsl:with-param name="iY" select="($label_y_ + 16)"/>
- <xsl:with-param name="iText" select="'MPMC Module Interface'"/>
- <xsl:with-param name="iClass" select="'mpmc_title'"/>
- </xsl:call-template>
-
-
- </g>
-
- </xsl:for-each>
-
-</xsl:template>
-
-
-<!-- ======================= END DEF FUNCTIONS ============================ -->
-
-<!-- ======================= UTILITY FUNCTIONS ============================ -->
-
-<xsl:template name="F_draw_InterruptSource">
-
- <xsl:param name="iIntr_X" select="0"/>
- <xsl:param name="iIntr_Y" select="0"/>
- <xsl:param name="iIntr_PRI" select="0"/>
- <xsl:param name="iIntr_IDX" select="0"/>
- <xsl:param name="iIntr_COL" select="$COL_INTR_0"/>
-
- <rect
- x="{$iIntr_X}"
- y="{$iIntr_Y}"
- rx="3"
- ry="3"
- width= "{$BLKD_INTR_W}"
- height="{ceiling($BLKD_INTR_H div 2)}" style="fill:{$iIntr_COL}; stroke:none; stroke-width:1"/>
-
- <line x1="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}"
- y1="{$iIntr_Y}"
- x2="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}"
- y2="{$iIntr_Y + ceiling($BLKD_INTR_H div 2)}"
- style="stroke:{$COL_BLACK};stroke-width:1"/>
-
- <xsl:variable name="txt_ofs_">
- <xsl:if test="($iIntr_PRI > 9)">4.5</xsl:if>
- <xsl:if test="not($iIntr_PRI > 9)">0</xsl:if>
- </xsl:variable>
-
-<!--
- <text class="intrsymbol"
- x="{$iIntr_X + 2 - $txt_ofs_}"
- y="{$iIntr_Y + 8}">
- <xsl:value-of select="$iIntr_PRI"/>
- </text>
-
- <text class="intrsymbol"
- x="{$iIntr_X + 2 + ceiling($BLKD_INTR_W div 2)}"
- y="{$iIntr_Y + 8}">
- <xsl:value-of select="$iIntr_IDX"/>
- </text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($iIntr_X + 2 - $txt_ofs_)"/>
- <xsl:with-param name="iY" select="($iIntr_Y + 8)"/>
- <xsl:with-param name="iText" select="$iIntr_PRI"/>
- <xsl:with-param name="iClass" select="'intr_symbol'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($iIntr_X + 2 + ceiling($BLKD_INTR_W div 2))"/>
- <xsl:with-param name="iY" select="($iIntr_Y + 8)"/>
- <xsl:with-param name="iText" select="$iIntr_IDX"/>
- <xsl:with-param name="iClass" select="'intr_symbol'"/>
- </xsl:call-template>
-
-</xsl:template>
-
-<xsl:template name="F_draw_InterruptCntrl">
-
- <xsl:param name="iIntr_X" select="0"/>
- <xsl:param name="iIntr_Y" select="0"/>
- <xsl:param name="iIntr_IDX" select="0"/>
- <xsl:param name="iIntr_COL" select="$COL_INTR_0"/>
-
- <rect
- x="{$iIntr_X}"
- y="{$iIntr_Y}"
- rx="3"
- ry="3"
- width= "{ceiling($BLKD_INTR_W div 2)}"
- height="{$BLKD_INTR_H}" style="fill:{$iIntr_COL}; stroke:none; stroke-width:1"/>
-
- <line x1="{$iIntr_X}"
- y1="{$iIntr_Y + ceiling($BLKD_INTR_H div 4)}"
- x2="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}"
- y2="{$iIntr_Y + ceiling($BLKD_INTR_H div 4)}"
- style="stroke:{$COL_BLACK};stroke-width:2"/>
-<!--
- <text class="intrsymbol"
- x="{$iIntr_X + 2}"
- y="{$iIntr_Y + 8 + ceiling($BLKD_INTR_H div 2)}">
- <xsl:value-of select="$iIntr_IDX"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($iIntr_X + 2)"/>
- <xsl:with-param name="iY" select="($iIntr_Y + 8 + ceiling($BLKD_INTR_H div 2))"/>
- <xsl:with-param name="iText" select="$iIntr_IDX"/>
- <xsl:with-param name="iClass" select="'intr_symbol'"/>
- </xsl:call-template>
-
-</xsl:template>
-
-
-<xsl:template name="F_draw_InterruptedProc">
-
- <xsl:param name="iIntr_X" select="0"/>
- <xsl:param name="iIntr_Y" select="0"/>
- <xsl:param name="iIntr_IDX" select="0"/>
- <xsl:param name="iIntr_COL" select="$COL_INTR_0"/>
-
- <rect
- x="{$iIntr_X}"
- y="{$iIntr_Y}"
- rx="3"
- ry="3"
- width= "{ceiling($BLKD_INTR_W div 2)}"
- height="{$BLKD_INTR_H}" style="fill:{$iIntr_COL}; stroke:none; stroke-width:1"/>
-
- <line x1="{$iIntr_X}"
- y1="{$iIntr_Y + ceiling($BLKD_INTR_H div 4) - 2}"
- x2="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}"
- y2="{$iIntr_Y + ceiling($BLKD_INTR_H div 4) - 2}"
- style="stroke:{$COL_BLACK};stroke-width:1"/>
-
- <line x1="{$iIntr_X}"
- y1="{$iIntr_Y + ceiling($BLKD_INTR_H div 4) + 2}"
- x2="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}"
- y2="{$iIntr_Y + ceiling($BLKD_INTR_H div 4) + 2}"
- style="stroke:{$COL_BLACK};stroke-width:1"/>
-
-<!--
- <text class="intrsymbol"
- x="{$iIntr_X + 2}"
- y="{$iIntr_Y + 8 + ceiling($BLKD_INTR_H div 2)}">
- <xsl:value-of select="$iIntr_IDX"/>
- </text>
- -->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($iIntr_X + 2)"/>
- <xsl:with-param name="iY" select="($iIntr_Y + 8 + ceiling($BLKD_INTR_H div 2))"/>
- <xsl:with-param name="iText" select="$iIntr_IDX"/>
- <xsl:with-param name="iClass" select="'intr_symbol'"/>
- </xsl:call-template>
-
-</xsl:template>
-
-<xsl:template name="F_Calc_CStackShapesAbv_Height">
- <xsl:param name="iCStackIndex" select="100"/>
- <xsl:param name="iCStackMods_Y" select="1000"/>
-
-<!--
- <xsl:message>Stack Index <xsl:value-of select="$cstackIndex"/></xsl:message>
-
- <xsl:message>Stack Y <xsl:value-of select="$cstackModY"/></xsl:message>
--->
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@CSTACK_INDEX = $iCStackIndex)])">0</xsl:if>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@CSTACK_INDEX = $iCStackIndex)]">
-
- <xsl:variable name="shapesAbv_Heights_">
- <CSTACK_MOD HEIGHT="0"/>
-
- <!-- Store the heights of all the peripherals above this one heights in a variable -->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@CSTACK_INDEX = $iCStackIndex) and (@CSTACK_MODS_Y < $iCStackMods_Y))]">
-
- <xsl:variable name="shapeHeight_">
-
- <xsl:choose>
-
- <xsl:when test="@MODCLASS = 'PERIPHERAL'">
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="MODULE/@INSTANCE"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="@MODCLASS = 'MEMORY_UNIT'">
- <xsl:call-template name="F_Calc_MemoryUnit_Height">
- <xsl:with-param name="iShapeId" select="@SHAPE_ID"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>Calculated height of cstack shape of type <xsl:value-of select="@MODCLASS"/> as <xsl:value-of select="$shapeHeight_"/></xsl:message>
--->
-
- <CSTACK_MOD HEIGHT="{$shapeHeight_ + $BLKD_BIF_H}"/>
- </xsl:for-each>
- </xsl:variable>
-
-<!--
- <xsl:message>Calculated height of cstack as <xsl:value-of select="sum(exsl:node-set($shapesAbv_Heights_)/CSTACK_MOD/@HEIGHT)"/></xsl:message>
--->
-
- <xsl:value-of select="sum(exsl:node-set($shapesAbv_Heights_)/CSTACK_MOD/@HEIGHT)"/>
- </xsl:if>
-
-</xsl:template>
-
-
-<xsl:template name="F_Calc_PeriShape_Height">
- <xsl:param name="iShapeInst" select="'_shape_'"/>
-
-<!--
- <xsl:message>Calculating height of <xsl:value-of select="$iShapeInst"/></xsl:message>
--->
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H) and
- not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H) and
- not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H)">0</xsl:if>
-
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H)">
- <xsl:variable name="bifs_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H"/>
-
- <xsl:value-of select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * $bifs_h_) + ($BLKD_MOD_BIF_GAP_V * $bifs_h_) + ($BLKD_MOD_LANE_H * 2))"/>
- </xsl:if>
-
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H)">
- <xsl:variable name="bifs_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H"/>
-
- <xsl:value-of select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * $bifs_h_) + ($BLKD_MOD_BIF_GAP_V * $bifs_h_) + ($BLKD_MOD_LANE_H * 2))"/>
- </xsl:if>
-
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H)">
- <xsl:variable name="bifs_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H"/>
-
- <xsl:value-of select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * $bifs_h_) + ($BLKD_MOD_BIF_GAP_V * $bifs_h_) + ($BLKD_MOD_LANE_H * 2))"/>
- </xsl:if>
-
-</xsl:template>
-
-<xsl:template name="F_Calc_Shape_Height">
- <xsl:param name="iShapeId" select="_shape_"/>
-
-<!--
- <xsl:message>Calculating height of <xsl:value-of select="$shapeId"/></xsl:message>
--->
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)])">0</xsl:if>
-
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE/@BIFS_H)">
- <xsl:variable name="bifs_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE/@BIFS_H"/>
-
- <xsl:value-of select="($BLKD_MOD_LABEL_H + ($BIF_H * $bifs_h_) + ($BLKD_MOD_BIF_GAP_V * $bifs_h_) + ($BLKD_MOD_LANE_H * 2))"/>
- </xsl:if>
-
-</xsl:template>
-
-
-<xsl:template name="F_Calc_MemoryUnit_Height">
- <xsl:param name="iShapeId" select="1000"/>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)])">0</xsl:if>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]">
-
- <!-- Store the memory controller heights in a variable -->
- <xsl:variable name="memC_heights_">
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY_CNTLR')])">
- <MEM_CNTLR INSTANCE="{@INSTANCE}" HEIGHT="0"/>
- </xsl:if>
-
- <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY_CNTLR')])">
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY_CNTLR')]">
- <xsl:variable name="memC_height_">
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="@INSTANCE"/>
- </xsl:call-template>
- </xsl:variable>
- <MEM_CNTLR INSTANCE="{@INSTANCE}" HEIGHT="{$memC_height_}"/>
- </xsl:for-each>
- </xsl:if>
- </xsl:variable>
-
- <!-- Store the bram heights in a variable -->
- <xsl:variable name="bram_heights_">
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[not(@MODCLASS = 'MEMORY_CNTLR')])">
- <BRAM INSTANCE="{@INSTANCE}" HEIGHT="0"/>
- </xsl:if>
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[not(@MODCLASS = 'MEMORY_CNTLR')]">
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[not(@MODCLASS = 'MEMORY_CNTLR')]">
- <xsl:variable name="bram_height_">
- <xsl:call-template name="F_Calc_PeriShape_Height">
- <xsl:with-param name="iShapeInst" select="@INSTANCE"/>
- </xsl:call-template>
- </xsl:variable>
- <BRAM INSTANCE="{@INSTANCE}" HEIGHT="{$bram_height_}"/>
- </xsl:for-each>
- </xsl:if>
- </xsl:variable>
-
- <!-- Select the maximum of them -->
- <xsl:variable name="max_bram_height_" select="math:max(exsl:node-set($bram_heights_)/BRAM/@HEIGHT)"/>
- <xsl:variable name="max_memC_height_" select="math:max(exsl:node-set($memC_heights_)/MEM_CNTLR/@HEIGHT)"/>
-
- <xsl:value-of select="$max_bram_height_ + $max_memC_height_"/>
- </xsl:if>
-
-</xsl:template>
-
-
-<xsl:template name="F_Calc_SbsBucket_Height">
- <xsl:param name="iBucketId" select="100"/>
-
-<!--
- <xsl:message>Looking of height of bucket <xsl:value-of select="$iBucketId"/></xsl:message>
--->
- <xsl:variable name="bkt_gap_" select="$BLKD_BIF_H"/>
-
- <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $iBucketId)])">0</xsl:if>
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $iBucketId)]">
- <xsl:variable name="mods_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $iBucketId)]/@MODS_H"/>
- <xsl:value-of select="((($BLKD_MOD_BKTLANE_H * 2) + ((($BLKD_MOD_H + $BLKD_BIFC_H) * $mods_h_) + ($BLKD_MOD_BUCKET_G * ($mods_h_ - 1)))) + $bkt_gap_)"/>
- </xsl:if>
-</xsl:template>
-
-<!--
- ===============================================
-
- Symbol Naming Functions
-
- ===============================================
--->
-
-
-<xsl:template name="F_generate_Proc_StackName">
-<xsl:param name="iProcInst" select="'_unknown_'"/>
-symbol_STACK_<xsl:value-of select="$iProcInst"/>
-</xsl:template>
-
-<xsl:template name="F_generate_Proc_GroupName">
-<xsl:param name="iProcInst" select="'_unknown_'"/>
-symbol_GROUP_<xsl:value-of select="$iProcInst"/>
-</xsl:template>
-
-
-<xsl:template name="F_generate_Space_Name"><xsl:param name="iStackToEast" select="'NONE'"/><xsl:param name="iStackToWest" select="'NONE'"/>symbol_SPACE_WEST_<xsl:value-of select="$iStackToWest"/>_EAST_<xsl:value-of select="$iStackToEast"/></xsl:template>
-<xsl:template name="F_generate_Stack_Name"><xsl:param name="iHorizIdx" select="'_unknown_'"/>symbol_STACK_<xsl:value-of select="$iHorizIdx"/></xsl:template>
-<xsl:template name="F_generate_Stack_SymbolName"><xsl:param name="iHorizIdx" select="'_unknown_'"/><xsl:param name="iVertiIdx" select="'_unknown_'"/>symbol_STACK_<xsl:value-of select="$iHorizIdx"/>_SHAPE_<xsl:value-of select="$iVertiIdx"/></xsl:template>
-
-
-<!-- ======================= END UTILITY FUNCTIONS ======================= -->
-</xsl:stylesheet>
-
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<!--
-<xsl:output method="xml"
- version="1.0"
- encoding="UTF-8"
- indent="yes"
- doctype-public="-//W3C//DTD SVG Tiny 1.1//EN"
- doctype-system="http://www.w3.org/Graphics/SVG/1.1/DTD/svg11-tiny.dtd"/>
--->
-
-
-<!-- ======================= DEF BLOCK =================================== -->
-<xsl:template name="Define_AllStacks">
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST < $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]">
-
- <xsl:call-template name="Define_Stack">
- <xsl:with-param name="iStackIdx" select="@EAST"/>
- </xsl:call-template>
-
- </xsl:for-each>
-</xsl:template>
-
-
-<xsl:template name="Define_Stack">
- <xsl:param name="iStackIdx" select="100"/>
-
- <!-- Define the stack's peripheral shapes-->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and not(@MODCLASS = 'MEMORY_UNIT'))]">
-
- <xsl:for-each select="MODULE">
- <xsl:variable name="modInst_" select="@INSTANCE"/>
- <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/>
- <xsl:call-template name="Define_Peripheral">
- <xsl:with-param name="iModInst" select="$modInst_"/>
- <xsl:with-param name="iModType" select="$modType_"/>
- <xsl:with-param name="iShapeId" select="../@SHAPE_ID"/>
- <xsl:with-param name="iHorizIdx" select="../@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="../@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:for-each>
-
- </xsl:for-each>
-
- <!-- Define the stack's memory shapes-->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@MODCLASS='MEMORY_UNIT'))]">
- <xsl:call-template name="Define_MemoryUnit">
- <xsl:with-param name="iShapeId" select="@SHAPE_ID"/>
- </xsl:call-template>
- </xsl:for-each>
-
-
- <!-- Define the stack's processors-->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[@INSTANCE and @BIFS_W and @BIFS_H and (@STACK_HORIZ_INDEX = $iStackIdx)]">
- <xsl:call-template name="Define_Processor"/>
- </xsl:for-each>
-
- <!-- Make an inventory of all the things in this processor's stack -->
- <xsl:variable name="pstackW_">
- <xsl:call-template name="F_Calc_Stack_Width">
- <xsl:with-param name="iStackIdx" select="$iStackIdx"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="pstackH_">
- <xsl:call-template name="F_Calc_Stack_Height">
- <xsl:with-param name="iStackIdx" select="$iStackIdx"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Proc Stack Height <xsl:value-of select="$pstackH_"/></xsl:message>
- <xsl:message>Proc Stack Height <xsl:value-of select="$pstackH_"/></xsl:message>
--->
-
- <xsl:variable name="procW_" select="$BLKD_MOD_W"/>
- <xsl:variable name="procX_" select="(ceiling($pstackW_ div 2) - ceiling($procW_ div 2))"/>
-
- <xsl:variable name="sbsGap_" select="($BLKD_PROC2SBS_GAP + $G_Total_SharedBus_H)"/>
-
- <xsl:variable name="stack_name_">
- <xsl:call-template name="F_generate_Stack_Name">
- <xsl:with-param name="iHorizIdx" select="$iStackIdx"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Horiz index<xsl:value-of select="$stackIdx"/></xsl:message>
- <xsl:message>Drawing stack <xsl:value-of select="$stack_name_"/></xsl:message>
--->
-
- <!-- Now use all this stuff to draw the stack-->
- <g id="{$stack_name_}">
- <rect x="0"
- y="0"
- rx="6"
- ry="6"
- width = "{$pstackW_}"
- height= "{$pstackH_}"
- style="fill:{$COL_BG}; stroke:none;"/>
-
-
- <!-- First draw the the processor's peripherals-->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@STACK_HORIZ_INDEX = $iStackIdx)]">
- <xsl:sort select="@STACK_VERTI_INDEX" data-type="number"/>
-
-
- <xsl:variable name="shapeW_" select="(@MODS_W * $BLKD_MOD_W)"/>
- <xsl:variable name="shapeX_" select="(ceiling($pstackW_ div 2) - ceiling($shapeW_ div 2))"/>
-
- <xsl:variable name="stack_SymName_">
- <xsl:call-template name="F_generate_Stack_SymbolName">
- <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>Drawing stack peripheral <xsl:value-of select="$stack_SymName_"/></xsl:message>
--->
- <xsl:variable name="shapeY_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
- <use x="{$shapeX_}" y="{$shapeY_}" xlink:href="#{$stack_SymName_}"/>
-
- </xsl:for-each>
-
-
- <!-- Then draw the slave buckets for the shared busses that this processor is master to -->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]">
- <xsl:sort select="@SHAPE_VERTI_INDEX" data-type="number"/>
-
- <xsl:variable name="bucketW_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/>
- <xsl:variable name="bucketX_" select="(ceiling($pstackW_ div 2) - ceiling($bucketW_ div 2))"/>
-
- <xsl:variable name="bucketY_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>SBS Bucket Y <xsl:value-of select="$bucketY_"/></xsl:message>
--->
-
- <use x="{$bucketX_}" y="{$bucketY_}" xlink:href="#sbsbucket_{@BUSNAME}"/>
-
- <xsl:variable name="slavesOfTxt_">SLAVES OF <xsl:value-of select="@BUSNAME"/></xsl:variable>
-<!--
- <text class="bkt_label"
- x="{$bucketX_}"
- y="{$bucketY_ - 4}"><xsl:value-of select="$slavesOfTxt_"/></text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="$bucketX_"/>
- <xsl:with-param name="iY" select="($bucketY_ - 4)"/>
- <xsl:with-param name="iText" select="$slavesOfTxt_"/>
- <xsl:with-param name="iClass" select="'bkt_label'"/>
- </xsl:call-template>
-
-
- </xsl:for-each>
-
- <!-- Then draw the the processor itself -->
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $iStackIdx)]">
- <xsl:sort select="@SHAPE_VERTI_INDEX" data-type="number"/>
-
- <xsl:variable name="procY_">
- <xsl:call-template name="F_Calc_Stack_Shape_Y">
- <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="stack_SymName_">
- <xsl:call-template name="F_generate_Stack_SymbolName">
- <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
- <use x="{$procX_}" y="{$procY_}" xlink:href="#{$stack_SymName_}"/>
-
-
-<!--
- <xsl:if test = "not(@IS_LIKEPROC)">
- <text class="ipclass_label"
- x="{$procX_}"
- y="{$procY_ - 4}">PROCESSOR</text>
- </xsl:if>
-
- <xsl:if test = "@IS_LIKEPROC = 'TRUE'">
-
- <text class="ipclass_label"
- x="{$procX_}"
- y="{$procY_ - 4}">USER MODULE</text>
- </xsl:if>
-
--->
-
- <xsl:if test = "not(@IS_LIKEPROC)">
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="$procX_"/>
- <xsl:with-param name="iY" select="($procY_ - 4)"/>
- <xsl:with-param name="iText" select="'PROCESSOR'"/>
- <xsl:with-param name="iClass" select="'ipclass_label'"/>
- </xsl:call-template>
- </xsl:if>
-
- <xsl:if test = "@IS_LIKEPROC = 'TRUE'">
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="$procX_"/>
- <xsl:with-param name="iY" select="($procY_ - 4)"/>
- <xsl:with-param name="iText" select="'USER MODULE'"/>
- <xsl:with-param name="iClass" select="'ipclass_label'"/>
- </xsl:call-template>
- </xsl:if>
-
- </xsl:for-each>
- </g>
-
-</xsl:template>
-
-
-<xsl:template name="Define_Processor">
- <xsl:param name="iProcInst" select="@INSTANCE"/>
- <xsl:param name="iModType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@MODTYPE"/>
-
- <xsl:variable name="label_y_">
- <xsl:value-of select="$BLKD_MOD_LANE_H"/>
- </xsl:variable>
-
-<!--
- <xsl:message>The proctype is <xsl:value-of select="$procType"/></xsl:message>
--->
-
- <xsl:variable name="procH_" select="(($BLKD_MOD_LANE_H * 2) + (($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIFS_H) + ($BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
- <xsl:variable name="procW_" select="(($BLKD_MOD_LANE_W * 2) + (($BLKD_BIF_W * @BIFS_W) + $BLKD_MOD_BIF_GAP_H))"/>
-
- <xsl:variable name="procColor_">
- <xsl:choose>
- <xsl:when test="contains($iModType,'microblaze')"><xsl:value-of select="$COL_PROC_BG_MB"/></xsl:when>
- <xsl:when test="contains($iModType,'ppc')"><xsl:value-of select="$COL_PROC_BG_PP"/></xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$COL_PROC_BG_USR"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message>The proc color is <xsl:value-of select="$procColor"/></xsl:message>
--->
-
- <xsl:variable name="procName_">
- <xsl:call-template name="F_generate_Stack_SymbolName">
- <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
- <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
- </xsl:call-template>
- </xsl:variable>
-
-<!--
- <xsl:message>The proc name is <xsl:value-of select="$procName_"/></xsl:message>
--->
-
- <g id="{$procName_}">
-
- <rect x="0"
- y="0"
- rx="6"
- ry="6"
- width = "{$procW_}"
- height= "{$procH_}"
- style="fill:{$procColor_}; stroke:{$COL_WHITE}; stroke-width:2"/>
-
-
- <rect x="{ceiling($procW_ div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
- y="{$BLKD_MOD_LANE_H}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_MOD_LABEL_H}"
- style="fill:{$COL_WHITE}; stroke:none;"/>
-<!--
- <text class="bciptype"
- x="{ceiling($procW_ div 2)}"
- y="{$BLKD_MOD_LANE_H + 8}">
- <xsl:value-of select="$iModType"/>
- </text>
-
- <text class="bciplabel"
- x="{ceiling($procW_ div 2)}"
- y="{$BLKD_MOD_LANE_H + 16}">
- <xsl:value-of select="$iProcInst"/>
- </text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($procW_ div 2)"/>
- <xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + 8)"/>
- <xsl:with-param name="iText" select="$iModType"/>
- <xsl:with-param name="iClass" select="'bc_iptype'"/>
- </xsl:call-template>
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($procW_ div 2)"/>
- <xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + 16)"/>
- <xsl:with-param name="iText" select="$iProcInst"/>
- <xsl:with-param name="iClass" select="'bc_ipinst'"/>
- </xsl:call-template>
-
-
-
- <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP">
-
- <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
- y="{$BLKD_MOD_LANE_H + $BIF_H + ceiling($BLKD_BIF_H div 3) - 2}"
- rx="3"
- ry="3"
- width= "{$BLKD_MOD_LABEL_W}"
- height="{$BLKD_BIF_H}"
- style="fill:{$COL_IORING_LT}; stroke:none;"/>
-<!--
- <text class="ioplblgrp"
- x="{ceiling($BLKD_MOD_W div 2)}"
- y="{$BLKD_MOD_LANE_H + $BIF_H + ceiling($BIF_H div 3) + 12}">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP"/>
- </text>
--->
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
- <xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + $BIF_H + ceiling($BIF_H div 3) + 12)"/>
- <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP"/>
- <xsl:with-param name="iClass" select="'iogrp_label'"/>
- </xsl:call-template>
-
- </xsl:if>
-
-
- <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/BUSINTERFACE[(@BIF_X and @BIF_Y)]">
-
- <xsl:variable name="bifBusStd_">
- <xsl:choose>
- <xsl:when test="@BUSSTD">
- <xsl:value-of select="@BUSSTD"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="'TRS'"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bifBusColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$bifBusStd_"/>
- </xsl:call-template>
- </xsl:variable>
-
-
- <xsl:variable name="bifName_">
- <xsl:choose>
- <xsl:when test="string-length(@NAME) <= 5">
- <xsl:value-of select="@NAME"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="substring(@NAME,0,5)"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bif_x_" select="(( $BLKD_BIF_W * @BIF_X) + ($BLKD_MOD_BIF_GAP_H * @BIF_X) + ($BLKD_MOD_LANE_W * 1))"/>
- <xsl:variable name="bif_y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
-
- <xsl:variable name="horz_line_y_" select="($bif_y_ + ceiling($BLKD_BIFC_H div 2))"/>
-
- <xsl:variable name="horz_line_x1_">
- <xsl:choose>
- <xsl:when test="@BIF_X = '0'">0</xsl:when>
- <xsl:otherwise><xsl:value-of select="($BLKD_MOD_W - $BLKD_MOD_LANE_W)"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="horz_line_x2_">
- <xsl:choose>
- <xsl:when test="@BIF_X = '0'"><xsl:value-of select="$BLKD_MOD_LANE_W"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="$BLKD_MOD_W + 1"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <line x1="{$horz_line_x1_}"
- y1="{$horz_line_y_ - 2}"
- x2="{$horz_line_x2_}"
- y2="{$horz_line_y_ - 2}"
- style="stroke:{$bifBusColor_};stroke-width:1"/>
-
- <use x="{$bif_x_}" y="{$bif_y_}" xlink:href="#{$bifBusStd_}_BifLabel"/>
-
-<!--
- <text class="bif_label"
- x="{$bif_x_ + ceiling($BIF_W div 2)}"
- y="{$bif_y_ + ceiling($BIF_H div 2) + 3}">
- <xsl:value-of select="$bifName_"/>
- </text>
--->
-
- <xsl:call-template name="F_WriteText">
- <xsl:with-param name="iX" select="($bif_x_ + ceiling($BIF_W div 2))"/>
- <xsl:with-param name="iY" select="($bif_y_ + ceiling($BIF_H div 2) + 3)"/>
- <xsl:with-param name="iText" select="$bifName_"/>
- <xsl:with-param name="iClass" select="'bif_label'"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
- <xsl:variable name="intcIdx_">
- <xsl:choose>
- <xsl:when test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/INTERRUPTINFO/@INTC_INDEX">
- <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/INTERRUPTINFO/@INTC_INDEX"/>
- </xsl:when>
- <xsl:otherwise>"_no_interrupt_cntlr_"</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-<!--
- <xsl:message> The intc index should <xsl:value-of select="$interrupt_cntlr_"/></xsl:message>
- <xsl:message> The intc index is <xsl:value-of select="/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $interrupt_cntlr_)]/@INTC_INDEX"/></xsl:message>
--->
- <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(INTERRUPTINFO[(@INTC_INDEX = $intcIdx_)])]">
-
- <xsl:variable name="intrColor_">
- <xsl:call-template name="F_IntcIdx2RGB">
- <xsl:with-param name="iIntcIdx" select="$intcIdx_"/>
-<!--
- <xsl:with-param name="iIntcIdx" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $interrupt_cntlr_)]/INTERRUPTINFO/@INTC_INDEX"/>
- -->
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:call-template name="F_draw_InterruptedProc">
- <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/>
- <xsl:with-param name="iIntr_Y" select="3"/>
- <xsl:with-param name="iIntr_COL" select="$intrColor_"/>
- <xsl:with-param name="iIntr_IDX" select="$intcIdx_"/>
- </xsl:call-template>
- </xsl:if>
- </g>
-
-</xsl:template>
-
-</xsl:stylesheet>
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<!--
-<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
- doctype-public="-//W3C//DTD SVG 1.0//EN"
- doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
--->
-
-<!-- ======================= DEF BLOCK =================================== -->
-
-<xsl:template name="Define_ConnectedBifTypes">
-
- <xsl:for-each select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR">
- <xsl:variable name="busStd_" select="@BUSSTD"/>
- <xsl:variable name="psfStd_" select="@BUSSTD_PSF"/>
- <xsl:for-each select="$G_SYS_MODS">
- <xsl:variable name="bif_by_busStd_" select="key('G_MAP_ALL_BIFS',$busStd_)[((@IS_INSTANTIATED = 'TRUE') or (@IS_INMHS = 'TRUE'))]"/>
- <xsl:variable name="num_of_busStd_" select="count($bif_by_busStd_)"/>
-
- <xsl:variable name="bif_by_psfStd_" select="key('G_MAP_ALL_BIFS',$psfStd_)[((@IS_INSTANTIATED = 'TRUE') or (@IS_INMHS = 'TRUE'))]"/>
- <xsl:variable name="num_of_psfStd_" select="count($bif_by_psfStd_)"/>
- <!--
- <xsl:message>DEBUG : <xsl:value-of select="$busStd_"/> : <xsl:value-of select="$num_of_busStd_"/> : <xsl:value-of select="$num_of_psfStd_"/></xsl:message>
- <xsl:variable name="bif_by_busStd_" select="key('G_MAP_ALL_BIFS',$busStd_)[(@IS_INSTANTIATED = 'TRUE')]"/>
- <xsl:variable name="num_of_busStd_" select="count($bif_by_busStd_)"/>
- -->
- <xsl:if test="(($num_of_busStd_ > 0) or ($num_of_psfStd_ > 0))">
- <xsl:if test="($num_of_busStd_ > 0)">
- <xsl:call-template name="Define_BifLabel">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- </xsl:call-template>
- </xsl:if>
- <xsl:if test="($num_of_psfStd_ > 0)">
- <xsl:call-template name="Define_BifLabel">
- <xsl:with-param name="iBusStd" select="$psfStd_"/>
- </xsl:call-template>
- </xsl:if>
- <xsl:for-each select="exsl:node-set($G_BIFTYPES)/BIFTYPE">
- <xsl:variable name="bifType_" select="@TYPE"/>
-
- <xsl:variable name="num_of_bifType_" select="count($bif_by_busStd_[(@TYPE = $bifType_)])"/>
- <!--
- <xsl:message>DEBUG : <xsl:value-of select="$bifType_"/> : <xsl:value-of select="$num_of_bifType_"/></xsl:message>
- -->
-
- <xsl:if test="($num_of_bifType_ > 0)">
- <xsl:if test="($num_of_busStd_ > 0)">
- <xsl:call-template name="Define_BifTypeConnector">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBifType" select="$bifType_"/>
- </xsl:call-template>
- </xsl:if>
- <xsl:if test="($num_of_psfStd_ > 0)">
- <xsl:call-template name="Define_BifTypeConnector">
- <xsl:with-param name="iBusStd" select="$busStd_"/>
- <xsl:with-param name="iBifType" select="$bifType_"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:if>
- </xsl:for-each>
- </xsl:if>
- </xsl:for-each>
- </xsl:for-each>
-
- <xsl:call-template name="Define_BifLabel">
- <xsl:with-param name="iBusStd" select="'KEY'"/>
- </xsl:call-template>
-
- <xsl:for-each select="exsl:node-set($G_BIFTYPES)/BIFTYPE">
- <xsl:variable name="bifType_" select="@TYPE"/>
-
- <xsl:call-template name="Define_BifTypeConnector">
- <xsl:with-param name="iBusStd" select="'KEY'"/>
- <xsl:with-param name="iBifType" select="$bifType_"/>
- </xsl:call-template>
-
- </xsl:for-each>
-
-</xsl:template>
-
-<xsl:template name="Define_BifLabel">
-
- <xsl:param name="iBusStd" select="'USER'"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <g id="{$iBusStd}_BifLabel">
- <rect x="0"
- y="0"
- rx="3"
- ry="3"
- width= "{$BIF_W}"
- height="{$BIF_H}"
- style="fill:{$busStdColor_}; stroke:black; stroke-width:1"/>
- </g>
-
-</xsl:template>
-
-
-<xsl:template name="Define_BifTypeConnector">
-
- <xsl:param name="iBusStd" select="'USER'"/>
- <xsl:param name="iBifType" select="'USER'"/>
-
- <xsl:variable name="busStdColor_">
- <xsl:call-template name="F_BusStd2RGB">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="busStdColor_lt_">
- <xsl:call-template name="F_BusStd2RGB_LT">
- <xsl:with-param name="iBusStd" select="$iBusStd"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="bifc_wi_" select="ceiling($BIFC_W div 3)"/>
- <xsl:variable name="bifc_hi_" select="ceiling($BIFC_H div 3)"/>
-
- <xsl:choose>
-
- <xsl:when test="$iBifType = 'SLAVE'">
- <g id="{$iBusStd}_busconn_{$iBifType}">
- <circle
- cx="{ceiling($BIFC_W div 2)}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_W div 2)}"
- style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
- <circle
- cx="{ceiling($BIFC_W div 2) + 0.5}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_Wi div 2)}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- </g>
- </xsl:when>
-
- <xsl:when test="$iBifType = 'MASTER'">
- <g id="{$iBusStd}_busconn_{$iBifType}">
- <rect x="0"
- y="0"
- width= "{$BIFC_W}"
- height="{$BIFC_H}"
- style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
- <rect x="{$BIFC_dx + 0.5}"
- y="{$BIFC_dy}"
- width= "{$BIFC_Wi}"
- height="{$BIFC_Hi}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- </g>
- </xsl:when>
-
- <xsl:when test="$iBifType = 'INITIATOR'">
- <g id="{$iBusStd}_busconn_{$iBifType}">
- <rect x="0"
- y="0"
- width= "{$BIFC_W}"
- height="{$BIFC_H}"
- style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
- <rect x="{$BIFC_dx + 0.5}"
- y="{$BIFC_dy}"
- width= "{$BIFC_Wi}"
- height="{$BIFC_Hi}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- </g>
- </xsl:when>
-
- <xsl:when test="$iBifType = 'TARGET'">
- <g id="{$iBusStd}_busconn_{$iBifType}">
- <circle
- cx="{ceiling($BIFC_W div 2)}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_W div 2)}"
- style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
- <circle
- cx="{ceiling($BIFC_W div 2) + 0.5}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_Wi div 2)}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- </g>
- </xsl:when>
-
- <xsl:when test="$iBifType = 'MASTER_SLAVE'">
- <g id="{$iBusStd}_busconn_{$iBifType}">
- <circle
- cx="{ceiling($BIFC_W div 2)}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_W div 2)}"
- style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
- <circle
- cx="{ceiling($BIFC_W div 2) + 0.5}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_Wi div 2)}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- <rect
- x="0"
- y="{ceiling($BIFC_H div 2)}"
- width= "{$BIFC_W}"
- height="{ceiling($BIFC_H div 2)}"
- style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
- <rect
- x="{$BIFC_dx + 0.5}"
- y="{ceiling($BIFC_H div 2)}"
- width= "{$BIFC_Wi}"
- height="{ceiling($BIFC_Hi div 2)}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- </g>
- </xsl:when>
-
- <xsl:when test="$iBifType = 'MONITOR'">
- <g id="{$iBusStd}_busconn_{$iBifType}">
- <rect
- x="0"
- y="0.5"
- width= "{$BIFC_W}"
- height="{ceiling($BIFC_Hi div 2)}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- <rect
- x="0"
- y="{ceiling($BIFC_H div 2) + 4}"
- width= "{$BIFC_W}"
- height="{ceiling($BIFC_Hi div 2)}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- </g>
- </xsl:when>
-
- <xsl:when test="$iBifType = 'USER'">
- <g id="{$iBusStd}_busconn_USER">
- <circle
- cx="{ceiling($BIFC_W div 2)}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_W div 2)}"
- style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
- <circle
- cx="{ceiling($BIFC_W div 2) + 0.5}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_Wi div 2)}"
- style="fill:{$busStdColor_}; stroke:none;"/>
- </g>
- </xsl:when>
-
- <xsl:otherwise>
- <g id="{$iBusStd}_busconn_{$iBifType}">
- <circle
- cx="{ceiling($BIFC_W div 2)}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_W div 2)}"
- style="fill:{$COL_WHITE}; stroke:{$busStdColor_}; stroke-width:1"/>
- <circle
- cx="{ceiling($BIFC_W div 2) + 0.5}"
- cy="{ceiling($BIFC_H div 2)}"
- r="{ceiling($BIFC_Wi div 2)}"
- style="fill:{$COL_WHITE}; stroke:none;"/>
- </g>
- </xsl:otherwise>
- </xsl:choose>
-
-</xsl:template>
-
-
-</xsl:stylesheet>
+++ /dev/null
- -p xc6slx45tfgg484-3\r
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<!DOCTYPE stylesheet [
- <!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
- <!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
-
- <!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
- <!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
-
- <!ENTITY ALPHALOWER "ABCDEFxX0123456789">
- <!ENTITY HEXUPPER "ABCDEFxX0123456789">
- <!ENTITY HEXLOWER "abcdefxX0123456789">
- <!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
-
- <!ENTITY ALLMODS "MODULE[(@INSTANCE)]">
- <!ENTITY BUSMODS "MODULE[(@MODCLASS ='BUS')]">
- <!ENTITY CPUMODS "MODULE[(@MODCLASS ='PROCESSOR')]">
-
- <!ENTITY MODIOFS "MODULE/IOINTERFACES/IOINTERFACE">
- <!ENTITY ALLIOFS "&MODIOFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
-
- <!ENTITY MODBIFS "MODULE/BUSINTERFACES/BUSINTERFACE">
- <!ENTITY ALLBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <!ENTITY MSTBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'MASTER')]">
- <!ENTITY SLVBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'SLAVE')]">
- <!ENTITY MOSBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@TYPE = 'MASTER') or (@TYPE = 'SLAVE'))]">
- <!ENTITY P2PBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR'))]">
-
- <!ENTITY MODPORTS "MODULE/PORTS/PORT">
- <!ENTITY ALLPORTS "&MODPORTS;[ (not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <!ENTITY NDFPORTS "&MODPORTS;[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (not(@BUS) and not(@IOS)))]">
- <!ENTITY DEFPORTS "&MODPORTS;[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@BUS) or (@IOS)))]">
-]>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<xsl:variable name="G_ROOT" select="/"/>
-
-
-
-<!--
- ======================================================
- EDK SYSTEM (EDWARD) Globals.
- ======================================================
--->
-<xsl:variable name="G_SYS_EVAL">
- <xsl:choose>
- <xsl:when test="not($P_SYSTEM_XML = '__UNDEF__')"><xsl:text>document($P_SYSTEM_XML)</xsl:text></xsl:when>
- <xsl:otherwise><xsl:text>/</xsl:text></xsl:otherwise>
- </xsl:choose>
-</xsl:variable>
-
-<xsl:variable name="G_SYS_DOC" select="dyn:evaluate($G_SYS_EVAL)"/>
-<xsl:variable name="G_SYS" select="$G_SYS_DOC/EDKSYSTEM"/>
-<xsl:variable name="G_SYS_TIMESTAMP" select="$G_SYS/@TIMESTAMP"/>
-<xsl:variable name="G_SYS_EDKVERSION" select="$G_SYS/@EDKVERSION"/>
-
-<xsl:variable name="G_SYS_INFO" select="$G_SYS/SYSTEMINFO"/>
-<xsl:variable name="G_SYS_INFO_PKG" select="$G_SYS_INFO/@PACKAGE"/>
-<xsl:variable name="G_SYS_INFO_DEV" select="$G_SYS_INFO/@DEVICE"/>
-<xsl:variable name="G_SYS_INFO_ARCH" select="$G_SYS_INFO/@ARCH"/>
-<xsl:variable name="G_SYS_INFO_SPEED" select="$G_SYS_INFO/@SPEEDGRADE"/>
-
-<xsl:variable name="G_SYS_MODS" select="$G_SYS/MODULES"/>
-<xsl:variable name="G_SYS_EXPS" select="$G_SYS/EXTERNALPORTS"/>
-
-<xsl:variable name="COL_FOCUSED_MASTER" select="'AAAAFF'"/>
-<xsl:variable name="COL_BG_OUTOF_FOCUS_CONNECTIONS" select="'AA7711'"/>
-
-<!-- INDEX KEYS FOR FAST ACCESS -->
-<xsl:key name="G_MAP_MODULES" match="&ALLMODS;" use="@INSTANCE"/>
-<xsl:key name="G_MAP_PROCESSORS" match="&CPUMODS;" use="@INSTANCE"/>
-
-<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@INSTANCE"/>
-<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@BUSSTD"/>
-<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@BUSSTD_PSF"/>
-
-<xsl:key name="G_MAP_ALL_IOFS" match="&ALLIOFS;" use="../../@INSTANCE"/>
-<xsl:key name="G_MAP_ALL_BIFS" match="&ALLBIFS;" use="../../@INSTANCE"/>
-
-<xsl:key name="G_MAP_ALL_BIFS_BY_BUS" match="&ALLBIFS;" use="@BUSNAME"/>
-<!--
- -->
-
-<xsl:key name="G_MAP_MST_BIFS" match="&MSTBIFS;" use="@BUSNAME"/>
-<xsl:key name="G_MAP_SLV_BIFS" match="&SLVBIFS;" use="@BUSNAME"/>
-<xsl:key name="G_MAP_MOS_BIFS" match="&MOSBIFS;" use="@BUSNAME"/>
-
-<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSNAME"/>
-<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSSTD"/>
-<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSSTD_PSF"/>
-
-<xsl:key name="G_MAP_ALL_PORTS" match="&ALLPORTS;" use="../../@INSTANCE"/>
-<xsl:key name="G_MAP_DEF_PORTS" match="&DEFPORTS;" use="../../@INSTANCE"/> <!-- Default ports -->
-<xsl:key name="G_MAP_NDF_PORTS" match="&NDFPORTS;" use="../../@INSTANCE"/> <!-- Non Default ports -->
-
-<!--
-<xsl:key name="G_MAP_MASTER_BIFS" match="&MSTBIFS;" use="@BUSNAME"/>
-<xsl:key name="G_MAP_MASTER_BIFS" match="MODULE[not(@MODCLASS ='BUS')]/BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'MASTER')]" use="../../@INSTANCE.@NAME"/>
-<xsl:key name="G_MAP_BUSSES_BY_INSTANCE" match="MODULE[(@MODCLASS ='BUS')]" use="@INSTANCE"/>
-<xsl:key name="G_MAP_XB_BUSSES" match="MODULE[(@MODCASS ='BUS')and (@IS_CROSSBAR)]" use="@INSTANCE"/>
- -->
-<!--
- ======================================================
- Groups.xml (BLOCKS) Globals
- ======================================================
--->
-<xsl:variable name="G_GRP_EVAL">
- <xsl:choose>
- <xsl:when test="not($P_GROUPS_XML = '__UNDEF__')"><xsl:text>document($P_GROUPS_XML)</xsl:text></xsl:when>
- <xsl:otherwise><xsl:text>/</xsl:text></xsl:otherwise>
- </xsl:choose>
-</xsl:variable>
-
-<xsl:variable name="G_GRPS_DOC" select="dyn:evaluate($G_GRP_EVAL)"/>
-<xsl:variable name="G_GROUPS" select="$G_GRPS_DOC/BLOCKS"/>
-
-<xsl:variable name="G_NUM_OF_PROCS" select="count($G_SYS/MODULES/MODULE[(@MODCLASS = 'PROCESSOR')])"/>
-<xsl:variable name="G_NUM_OF_PROCS_W_ADDRS" select="count($G_SYS/MODULES/MODULE[(@MODCLASS = 'PROCESSOR') and MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]])"/>
-
-<xsl:variable name="G_FOCUSED_SCOPE">
- <xsl:choose>
-
- <!-- FOCUSING ON SPECIFIC SELECTIONS-->
- <xsl:when test="$G_ROOT/SAV/SELECTION">
- </xsl:when>
-
- <!-- FOCUSING ON PROCESSOR -->
- <xsl:when test="$G_ROOT/SAV/MASTER">
- <xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message>FOCUSED MASTERS SPECIFIED</xsl:message></xsl:if>
- <xsl:for-each select="$G_ROOT/SAV/MASTER">
- <xsl:variable name="m_inst_" select="@INSTANCE"/>
- <xsl:variable name="m_mod_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $m_inst_)]"/>
- <xsl:for-each select="$m_mod_/BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and not(@BUSNAME = '__NOC__') and ((@TYPE = 'MASTER') or (@TYPE = 'SLAVE') or (@TYPE = 'INITIATOR') or (@TYPE = 'TARGET'))]">
- <xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED MASTER BIF <xsl:value-of select="$m_inst_"/>.<xsl:value-of select="@NAME"/> = <xsl:value-of select="@BUSNAME"/></xsl:message></xsl:if>
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
- <BUS NAME="{@BUSNAME}" BUSSTD="{@BUSSTD}"/>
- <xsl:for-each select="$G_SYS_MODS/MODULE[(not(@INSTANCE = $m_inst_) and (@MODCLASS = 'BUS_BRIDGE'))]/BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'SLAVE') and (@BUSNAME = $b_bus_)]">
- <xsl:variable name="b_inst_" select="../../@INSTANCE"/>
- <xsl:choose>
- <xsl:when test="MASTERS/MASTER">
- <xsl:for-each select="MASTERS/MASTER">
- <xsl:variable name="sm_inst_" select="@INSTANCE"/>
- <xsl:if test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $sm_inst_)]) > 0">
- <xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED PERIPHERAL BRIDGE <xsl:value-of select="$b_inst_"/></xsl:message></xsl:if>
- <PERIPHERAL NAME="{$b_inst_}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED PERIPHERAL BRIDGE <xsl:value-of select="$b_inst_"/></xsl:message></xsl:if>
- <PERIPHERAL NAME="{$b_inst_}"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:for-each>
- <xsl:for-each select="$m_mod_/PERIPHERALS/PERIPHERAL">
- <xsl:variable name="p_id_" select="@INSTANCE"/>
- <xsl:variable name="p_mod_" select="$G_SYS_MODS/MODULE[@INSTANCE = $p_id_]"/>
- <PERIPHERAL NAME="{@INSTANCE}"/>
- <xsl:variable name="p_mr_cnt_" select="count($m_mod_/MEMORYMAP/MEMRANGE[(@INSTANCE = $p_id_)])"/>
- <xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED PERIPHERAL <xsl:value-of select="$p_id_"/> has <xsl:value-of select="$p_mr_cnt_"/> memory ranges</xsl:message></xsl:if>
- <xsl:for-each select="$m_mod_/MEMORYMAP/MEMRANGE[(@INSTANCE = $p_id_)]/ACCESSROUTE/ROUTEPNT">
- <xsl:variable name="b_id_" select="@INSTANCE"/>
- <xsl:for-each select="$G_SYS_MODS/MODULE[((@INSTANCE = $b_id_) and (@MODCLASS = 'BUS'))]">
- <xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED PERIPHERAL BUS <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
- <BUS NAME="{@INSTANCE}" BUSSTD="{@BUSSTD}"/>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:when>
-
- <!-- FOCUSING ON BUS -->
- <xsl:when test="$G_ROOT/SAV/BUS">
- <xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message>FOCUSED BUSSES SPECIFIED</xsl:message></xsl:if>
- <xsl:for-each select="$G_ROOT/SAV/BUS">
- <xsl:variable name="m_inst_" select="@INSTANCE"/>
- <xsl:variable name="m_mod_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $m_inst_)]"/>
- <xsl:variable name="m_bstd_" select="$m_mod_/@BUSSTD"/>
- <BUS NAME="{$m_inst_}" BUSSTD="{$m_bstd_}"/>
- <xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED BUS <xsl:value-of select="$m_inst_"/> <xsl:value-of select="$m_bstd_"/></xsl:message></xsl:if>
- </xsl:for-each>
- </xsl:when>
- </xsl:choose>
-</xsl:variable>
-
-<xsl:variable name="G_HAVE_XB_BUSSES">
- <xsl:choose>
- <xsl:when test="(count($G_SYS_MODS/MODULE[((@MODCLASS = 'BUS') and (@IS_CROSSBAR = 'TRUE'))]) > 0)">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
-</xsl:variable>
-
-<xsl:template name="F_ModClass_To_IpClassification">
- <xsl:param name="iModClass" select="'NONE'"/>
- <xsl:param name="iBusStd" select="'NONE'"/>
- <xsl:choose>
- <xsl:when test="$iModClass = 'BUS'"><xsl:value-of select="$iBusStd"/> Bus</xsl:when>
- <xsl:when test="$iModClass = 'DEBUG'">Debug</xsl:when>
- <xsl:when test="$iModClass = 'MEMORY'">Memory</xsl:when>
- <xsl:when test="$iModClass = 'MEMORY_CNTLR'">Memory Controller</xsl:when>
- <xsl:when test="$iModClass = 'INTERRUPT_CNTLR'">Interrupt Controller</xsl:when>
- <xsl:when test="$iModClass = 'PERIPHERAL'">Peripheral</xsl:when>
- <xsl:when test="$iModClass = 'PROCESSOR'">Processor</xsl:when>
- <xsl:when test="$iModClass = 'BUS_BRIDGE'">Bus Bridge</xsl:when>
- <xsl:otherwise><xsl:value-of select="$iModClass"/></xsl:otherwise>
- </xsl:choose>
-</xsl:template>
-
-<xsl:template name="F_Connection_To_AXI_SLAVE">
- <xsl:param name="iNameParam" select="''"/>
- <xsl:param name="iModuleRefParam" select="''"/>
-
- <xsl:variable name="FilName" select="$iModuleRefParam/PARAMETERS/PARAMETER[@NAME=concat('C_', $iNameParam, '_MASTERS')]/@VALUE"/>
- <!-- <xsl:message>FIL NAME WAS <xsl:value-of select="$FilName"/></xsl:message> -->
- <xsl:value-of select="$FilName"/>
-</xsl:template>
-
-<xsl:template name="F_IS_Interface_External">
- <xsl:param name="iInstRef"/> <!-- Instance reference -->
- <xsl:param name="iIntfRef"/> <!-- Interface reference -->
- <xsl:variable name="intfName_" select="$iIntfRef/@NAME"/>
- <xsl:variable name="instName_" select="$iInstRef/@INSTANCE"/>
-
- <!-- <xsl:message>NAME 1 <xsl:value-of select="$expName1_"/></xsl:message>-->
- <!-- <xsl:message>NAME 2 <xsl:value-of select="$expName2_"/></xsl:message>-->
-<!--
- <xsl:variable name="expName1_" select="concat($instName_,'_',$intfName_,'_',@PHYSICAL,'_pin')"/>
- <xsl:variable name="expName2_" select="concat($instName_,'_',@PHYSICAL,'_pin')"/>
- -->
-
- <!-- Store the number of physical ports connected externals in a variable -->
-
- <xsl:variable name="connected_externals_">
- <xsl:for-each select="$iIntfRef/PORTMAPS/PORTMAP">
- <xsl:variable name="portName_" select="@PHYSICAL"/>
- <xsl:if test="$iInstRef/PORTS/PORT[(@NAME = $portName_)]">
- <xsl:variable name="portNet_" select="$iInstRef/PORTS/PORT[(@NAME = $portName_)]/@SIGNAME"/>
- <xsl:if test="$G_SYS_EXPS/PORT[(@SIGNAME = $portNet_)]">
- <EXTP NAME="{@PHYSICAL}"/>
- </xsl:if>
- </xsl:if>
- </xsl:for-each>
- </xsl:variable>
-
- <!--
- <xsl:message><xsl:value-of select="$instName_"/>.<xsl:value-of select="$intfName_"/> has <xsl:value-of select="count(exsl:node-set($connected_externals_)/EXTP)"/> connected externals.</xsl:message>
- -->
- <xsl:choose>
- <xsl:when test="(count(exsl:node-set($connected_externals_)/EXTP) > 0)">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
-</xsl:template>
-
-</xsl:stylesheet>
-
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<!DOCTYPE stylesheet [
- <!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
- <!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
-
- <!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
- <!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
-
- <!ENTITY ALPHALOWER "ABCDEFxX0123456789">
- <!ENTITY HEXUPPER "ABCDEFxX0123456789">
- <!ENTITY HEXLOWER "abcdefxX0123456789">
- <!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
-]>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math exsl dyn xlink">
-
-<xsl:include href="edw2xtl_sav_globals.xsl"/>
-
-<xsl:include href="edw2xtl_sav_view_addr.xsl"/>
-<xsl:include href="edw2xtl_sav_view_busif.xsl"/>
-<xsl:include href="edw2xtl_sav_view_port.xsl"/>
-<xsl:include href="edw2xtl_sav_view_groups.xsl"/>
-
-<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"/>
-
-<xsl:param name="P_SYSTEM_XML" select= "'__UNDEF__'"/>
-<xsl:param name="P_GROUPS_XML" select= "'__UNDEF__'"/>
-
-<xsl:param name="G_DEBUG" select="'FALSE'"/>
-<xsl:param name="G_ADD_CHOICES" select="'TRUE'"/>
-
-<!--
-<xsl:param name="P_VIEW" select="'__UNDEF__'"/>
-<xsl:param name="P_MODE" select="'__UNDEF__'"/>
-<xsl:param name="P_SCOPE" select="'__UNDEF__'"/>
--->
-
-
-
-<!-- MAIN TEMPLATE -->
-
-<xsl:template match="SAV[@VIEW]">
- <xsl:if test="$G_DEBUG='TRUE'">
- <xsl:message>SAV VIEW <xsl:value-of select="@VIEW"/></xsl:message>
- <xsl:message>SAV MODE <xsl:value-of select="@MODE"/></xsl:message>
- <xsl:message>SAV SCOPE <xsl:value-of select="@SCOPE"/></xsl:message>
- </xsl:if>
-
- <xsl:choose>
- <xsl:when test="not(@VIEW = 'PORT') and not(@VIEW = 'BUSINTERFACE') and not(@VIEW = 'ADDRESS')">
- <xsl:message>EDW2SAV XTELLER ERROR: UNDEFINED VIEW <xsl:value-of select="@VIEW"/></xsl:message>
- </xsl:when>
-
- <xsl:when test="(@MODE and not(@MODE = 'FLAT') and not(@MODE = 'TREE') and not(@MODE = 'GROUPS'))">
- <xsl:message>EDW2SAV XTELLER ERROR: UNDEFINED MODE <xsl:value-of select="@MODE"/></xsl:message>
- </xsl:when>
-
- <xsl:when test="(@SCOPE and not(@SCOPE = 'FULL') and not(@SCOPE= 'FOCUS'))">
- <xsl:message>EDW2SAV XTELLER ERROR: UNDEFINED SCOPE <xsl:value-of select="@SCOPE"/></xsl:message>
- </xsl:when>
-
- <xsl:when test="$P_SYSTEM_XML ='__UNDEF__'">
- <xsl:message>EDW2SAV XTELLER ERROR: SYSTEM XML UNDEFINED</xsl:message>
- </xsl:when>
-
- <xsl:when test="not($G_SYS)" >
- <xsl:message>EDW2SAV XTELLER ERROR: EDKSYSTEM MISSING in SYSTEM XML <xsl:value-of select="$P_SYSTEM_XML"/></xsl:message>
- </xsl:when>
-
- <xsl:when test="($P_GROUPS_XML ='__UNDEF__') and (@MODE = 'GROUPS')" >
- <xsl:message>EDW2SAV XTELLER ERROR: GROUP XML UNDEFINED for FOCUS</xsl:message>
- </xsl:when>
-
- <xsl:when test="($P_GROUPS_XML ='__UNDEF__') and (@SCOPE = 'FOCUS') and (@VIEW = 'BUSINTERFACE')" >
- <xsl:message>EDW2SAV XTELLER ERROR: GROUP XML UNDEFINED for SCOPE</xsl:message>
- </xsl:when>
-
- <xsl:otherwise>
-
- <xsl:if test="$G_DEBUG='TRUE'">
- <xsl:message>SYSTEM XML <xsl:value-of select="$P_SYSTEM_XML"/></xsl:message>
- <xsl:message>GROUPS XML <xsl:value-of select="$P_GROUPS_XML"/></xsl:message>
- </xsl:if>
-
- <xsl:variable name="use_mode_">
- <xsl:choose>
- <xsl:when test="@MODE = 'GROUPS'">TREE</xsl:when>
- <xsl:otherwise><xsl:value-of select="@MODE"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="num_procs_focused_on_" select="count(MASTER)"/>
- <xsl:variable name="num_buses_focused_on_" select="count(BUS)"/>
-
- <xsl:element name="SET">
- <xsl:attribute name="CLASS">PROJECT</xsl:attribute>
- <xsl:attribute name="VIEW_ID"><xsl:value-of select="@VIEW"/></xsl:attribute>
- <xsl:attribute name="DISPLAYMODE"><xsl:value-of select="$use_mode_"/></xsl:attribute>
-
- <xsl:choose>
-
- <!-- ADDRESS TAB VIEW -->
- <xsl:when test="(@VIEW = 'ADDRESS')">
- <xsl:call-template name="WRITE_VIEW_ADDRESS"/>
- </xsl:when>
-
- <!-- BIF TAB VIEWS -->
- <xsl:when test="((@VIEW ='BUSINTERFACE') and (@SCOPE = 'FOCUS') and ($num_procs_focused_on_ > 0))">
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUS_ON_PROCS"/>
- </xsl:when>
-
- <!-- BIF TAB VIEWS -->
- <xsl:when test="((@VIEW ='BUSINTERFACE') and (@SCOPE = 'FOCUS') and ($num_buses_focused_on_ > 0))">
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUS_ON_BUSES"/>
- </xsl:when>
-
- <xsl:when test="((@VIEW ='BUSINTERFACE') and (@MODE = 'TREE') and not(@SCOPE))">
- <xsl:call-template name="WRITE_VIEW_BIF_TREE"/>
- </xsl:when>
-
- <xsl:when test="((@VIEW = 'BUSINTERFACE') and (@MODE = 'FLAT') and not(@SCOPE))">
- <xsl:call-template name="WRITE_VIEW_BIF_FLAT"/>
- </xsl:when>
-
- <xsl:when test="((@VIEW = 'BUSINTERFACE') and (@MODE = 'GROUPS'))">
- <xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:with-param name="iModules" select="$G_BLOCKS"/>
- </xsl:call-template>
- </xsl:when>
-
-
- <!-- PORT TAB VIEWS -->
- <xsl:when test="((@VIEW ='PORT') and (@SCOPE = 'FOCUS'))">
- <xsl:call-template name="WRITE_VIEW_PORT_FOCUSED"/>
- </xsl:when>
-
- <!-- Generate XTeller panel data for Ports using hierarchy -->
- <xsl:when test="((@VIEW = 'PORT') and (@MODE = 'TREE'))">
- <xsl:call-template name="WRITE_VIEW_PORT_TREE"/>
- </xsl:when>
-
- <!-- Generate XTeller panel data for Ports without hierarchy, (flat view) -->
- <xsl:when test="((@VIEW='PORT') and (@MODE = 'FLAT'))">
- <xsl:call-template name="WRITE_VIEW_PORT_FLAT"/>
- </xsl:when>
-
-
- <xsl:otherwise>
- <xsl:message>ERROR during SAV XTeller generation with panel <xsl:value-of select="@VIEW"/> and display mode <xsl:value-of select="@MODE"/></xsl:message>
- </xsl:otherwise>
-
- </xsl:choose>
- </xsl:element>
- </xsl:otherwise>
- </xsl:choose>
-</xsl:template>
-
-<xsl:template match="EDKSYSTEM">
-
-<!--
- <xsl:message>EDW VERSION <xsl:value-of select="$G_EDWVER"/></xsl:message>
- <xsl:message>VIEW <xsl:value-of select="$VIEW"/></xsl:message>
- <xsl:message>MODE <xsl:value-of select="$MODE"/></xsl:message>
--->
-
- <xsl:variable name="by_interface_">
- <xsl:choose>
- <!--
- Show interfaces or not
- -->
- <xsl:when test="(($SHOW_BUSIF ='TRUE') or ($SHOW_IOIF ='TRUE'))">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <!--
- <xsl:message>VIEW <xsl:value-of select="$VIEW"/></xsl:message>
- <xsl:message>MODE <xsl:value-of select="$MODE"/></xsl:message>
- <xsl:message>BY INTERFACE <xsl:value-of select="$by_interface_"/></xsl:message>
- -->
- <xsl:variable name="displayMode_">
- <xsl:choose>
- <!--
- Hard code view to view for address panel,
- always show view in what was formerly
- multiprocessor view. See below.
-
- <xsl:when test="(($G_NUM_OF_PROCS > 1) and ($VIEW='ADDRESS'))">TREE</xsl:when>
- <xsl:when test="(($G_NUM_OF_PROCS <= 1) and ($VIEW='ADDRESS'))">FLAT</xsl:when>
- -->
- <xsl:when test="($VIEW='ADDRESS')">TREE</xsl:when>
- <xsl:otherwise><xsl:value-of select="$MODE"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <SET CLASS="PROJECT" VIEW= "{$VIEW}" MODE="{$displayMode_}">
- <xsl:choose>
-
- <!-- Generate XTeller panel data for Bus Interfaces using hierarchy -->
- <xsl:when test="(($VIEW='BUSINTERFACE') and (not($MODE) or ($MODE = 'TREE')))">
- <xsl:call-template name="WRITE_VIEW_BIF_TREE"/>
- </xsl:when>
-
- <!-- Generate XTeller panel data for Bus Interfaces without hierarchy, (flat view) -->
- <xsl:when test="(($VIEW='BUSINTERFACE') and ($MODE = 'FLAT'))">
- <xsl:call-template name="WRITE_VIEW_BIF_FLAT"/>
- </xsl:when>
-
- <!-- Generate XTeller panel data for Ports using hierarchy -->
- <xsl:when test="(($VIEW='PORT') and (not($MODE) or ($MODE = 'TREE')))">
- <xsl:call-template name="WRITE_VIEW_PORT_TREE"/>
- </xsl:when>
-
- <!-- Generate XTeller panel data for Ports without hierarchy, (flat view) -->
- <xsl:when test="(($VIEW='PORT') and ($MODE = 'FLAT'))">
- <xsl:call-template name="WRITE_VIEW_PORT_FLAT"/>
- </xsl:when>
-
- <!--
- Hard code display of the address panel to always the the same.
- No more tree or flat mode, always show address panel
- in what was formerly the multiprocessor view.
- -->
- <xsl:when test="($VIEW='ADDRESS')">
- <xsl:call-template name="WRITE_VIEW_ADDRESS"/>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:message>ERROR during SAV XTeller generation with panel <xsl:value-of select="$VIEW"/> and display mode <xsl:value-of select="$MODE"/></xsl:message>
- </xsl:otherwise>
-
- </xsl:choose>
- </SET>
-
-</xsl:template>
-
-</xsl:stylesheet>
-
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<!DOCTYPE stylesheet [
- <!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
- <!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
-
- <!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
- <!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
-
- <!ENTITY ALPHALOWER "ABCDEFxX0123456789">
- <!ENTITY HEXUPPER "ABCDEFxX0123456789">
- <!ENTITY HEXLOWER "abcdefxX0123456789">
- <!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
-]>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="exsl dyn math xlink">
-
-<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"/>
-
-<!--
- ================================================================================
- Generate XTeller for ADDRESSES
- ================================================================================
--->
-
-<xsl:template name="WRITE_VIEW_ADDRESS">
-
- <xsl:for-each select="$G_SYS_MODS/MODULE[((@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE)]))]">
- <xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
-
- <xsl:variable name="procInst_" select="@INSTANCE"/>
- <xsl:variable name="procMod_" select="self::node()"/>
- <xsl:variable name="procModType" select="@MODTYPE"/>
- <xsl:variable name="procModClass_" select="@MODCLASS"/>
- <xsl:variable name="procInstHdrVal_"><xsl:value-of select="$procInst_"/>'s Address Map</xsl:variable>
- <xsl:variable name="procInstRowIdx_" select="position() - 1"/>
-
- <!-- <SET ID="{$procInst_}" CLASS="MODULE" ROW_INDEX="{$procInstRowIdx_}"> -->
-
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="$procInst_"/></xsl:attribute>
- <xsl:attribute name="CLASS">MODULE</xsl:attribute>
- <xsl:attribute name="ROW_INDEX"><xsl:value-of select="$procInstRowIdx_"/></xsl:attribute>
-
- <!-- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$procInstHdrVal_}"/> -->
-
- <xsl:element name="VARIABLE">
- <xsl:attribute name="NAME">INSTANCE</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$procInstHdrVal_"/></xsl:attribute>
- <xsl:attribute name="VIEWDISP">Instance</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- </xsl:element>
-
- <xsl:for-each select="$procMod_/MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (ACCESSROUTE or (@MEMTYPE = 'BRIDGE')))]">
- <xsl:sort data-type="number" select="@BASEDECIMAL" order="ascending"/>
-
- <xsl:variable name="addr_id_"><xsl:value-of select="@BASENAME"/>:<xsl:value-of select="@HIGHNAME"/></xsl:variable>
- <xsl:variable name="baseName_" select="@BASENAME"/>
- <xsl:variable name="highName_" select="@HIGHNAME"/>
-
- <!--
- <xsl:if test="$G_DEBUG='TRUE'">
- <xsl:message>ADDRESS ID <xsl:value-of select="$addr_id_"/></xsl:message>
- </xsl:if>
- -->
-
- <xsl:variable name="set_id_">
- <xsl:if test="(@INSTANCE)">
- <xsl:value-of select="$procInst_"/>.<xsl:value-of select="@INSTANCE"/>:<xsl:value-of select="$addr_id_"/>
- </xsl:if>
- <xsl:if test="not(@INSTANCE)">
- <xsl:value-of select="$procInst_"/>:<xsl:value-of select="$addr_id_"/>
- </xsl:if>
- </xsl:variable>
-
- <xsl:variable name="procAddrRowIdx_" select="position() - 1"/>
- <SET ID="{$set_id_}" CLASS="ADDRESS" ROW_INDEX="{$procAddrRowIdx_}">
-
- <xsl:if test="(@INSTANCE)">
- <xsl:variable name="periInst_" select="@INSTANCE"/>
- <xsl:variable name="periMod_" select="key('G_MAP_MODULES', $periInst_)"/>
- <!--
- <xsl:variable name="subInstance_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $instance_)]"/>
- <xsl:message>Count memrange slaves <xsl:value-of select="count($modMemMapSlvs_)"/> </xsl:message>
- <xsl:message>Count mod valid bifs <xsl:value-of select="count($modValidBifs_)"/> </xsl:message>
- -->
-
-
- <xsl:variable name="periModType_" select="$periMod_/@MODTYPE"/>
- <xsl:variable name="periViewIcon_" select="$periMod_/LICENSEINFO/@ICON_NAME"/>
- <xsl:variable name="periHwVersion_" select="$periMod_/@HWVERSION"/>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$periInst_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$periModType_}" VIEWICON="{$periViewIcon_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$periHwVersion_}"/>
- </xsl:if>
-
- <xsl:if test="not(@INSTANCE)">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$procInst_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$procModType}" VIEWICON="{$procMod_/LICENSEINFO/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$procHwVersion_}"/>
- </xsl:if>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Address Type" NAME="MEMTYPE" VALUE="{@MEMTYPE}"/>
-
- <xsl:variable name="instName_">
- <xsl:choose>
- <xsl:when test="@INSTANCE"><xsl:value-of select="@INSTANCE"/></xsl:when>
- <xsl:otherwise>Connected<xsl:value-of select="$procInst_"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <!--
- <xsl:message>INST : <xsl:value-of select="$set_id_"/></xsl:message>
- -->
-
- <xsl:variable name="is_locked_">
- <xsl:if test="@IS_LOCKED = 'TRUE'">TRUE</xsl:if>
- <xsl:if test="not(@IS_LOCKED) or not(@IS_LOCKED = 'TRUE')">FALSE</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="baseAddrViewType_">
- <xsl:choose>
- <xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
- <xsl:otherwise>TEXTBOX</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="(@SIZEABRV and not(@SIZEABRV = 'U'))">
- <xsl:variable name="baseAddr_"><xsl:value-of select="translate(@BASEVALUE,&HEXU2L;)"/></xsl:variable>
- <xsl:variable name="highAddr_"><xsl:value-of select="translate(@HIGHVALUE,&HEXU2L;)"/></xsl:variable>
- <VARIABLE VIEWTYPE="{$baseAddrViewType_}" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE="{$baseAddr_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="High Address" NAME="HIGHVALUE" VALUE="{$highAddr_}"/>
-
- <xsl:if test="not(@MEMTYPE) or not(@MEMTYPE = 'BRIDGE')">
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
- </xsl:if>
-
- <xsl:if test="@MEMTYPE and (@MEMTYPE = 'BRIDGE') and not(@BRIDGE_TO)">
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
- </xsl:if>
- </xsl:if>
-
- <xsl:if test="(@SIZEABRV and (@SIZEABRV = 'U'))">
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE=""/>
- </xsl:if>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Base Name" NAME="BASENAME" VALUE="{@BASENAME}"/>
-
- <xsl:variable name="sizeViewType_">
- <xsl:choose>
- <xsl:when test="(@SIZEABRV and (@SIZEABRV = 'U'))">DROPDOWN</xsl:when>
- <xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
- <xsl:otherwise>DROPDOWN</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="{$sizeViewType_}" VIEWDISP="Size" NAME="SIZEABRV" VALUE="{@SIZEABRV}"/>
-
- <xsl:variable name="periInst_" select="@INSTANCE"/>
- <xsl:variable name="periMod_" select="key('G_MAP_MODULES', $periInst_)"/>
- <xsl:variable name="periModClass_" select="$periMod_/@MODCLASS"/>
- <xsl:variable name="periValidBifs_" select="key('G_MAP_ALL_BIFS', $periInst_)[not(@BUSNAME = '__NOC__')]"/>
- <xsl:variable name="periMemMapSlvs_" select="$periMod_/MEMORYMAP/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE"/>
- <xsl:variable name="periMemMapBifs_">
- <xsl:for-each select="$periMemMapSlvs_">
- <xsl:variable name="periSlvBifName_" select="@BUSINTERFACE"/>
- <xsl:if test="$periValidBifs_[(@NAME = $periSlvBifName_)]">
- <xsl:variable name="periBif_" select="$periValidBifs_[(@NAME = $periSlvBifName_)]"/>
- <xsl:variable name="periBifName_" select="$periBif_/@NAME"/>
- <xsl:variable name="periBifBus_" select="$periBif_/@BUSNAME"/>
- <!--
- <xsl:message> Slv Bif <xsl:value-of select="$periBifName_"/> = <xsl:value-of select="$periBifBus_"/></xsl:message>
- -->
- <MMBIF NAME="{$periBifName_}" BUS="{$periBifBus_}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:variable name="num_of_periMemMapBifs_" select="count(exsl:node-set($periMemMapBifs_)/MMBIF)"/>
-
- <!--
- <xsl:message> Total num of slv bifs <xsl:value-of select="$num_of_periMemMapBifs_"/> </xsl:message>
- <xsl:message> </xsl:message>
- -->
-
- <xsl:variable name="valid_bifNames_">
- <xsl:for-each select="exsl:node-set($periMemMapBifs_)/MMBIF">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="$bifName_"/>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:variable name="valid_busNames_">
- <xsl:for-each select="exsl:node-set($periMemMapBifs_)/MMBIF">
- <xsl:variable name="busName_" select="@BUS"/>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="$busName_"/>
- </xsl:for-each>
- </xsl:variable>
-
- <!--
- <xsl:message> Mod Bif <xsl:value-of select="$bifName_"/> : <xsl:value-of select="position()"/></xsl:message>
- <xsl:message> Mod Bif <xsl:value-of select="$bifName_"/> : <xsl:value-of select="position()"/></xsl:message>
- <xsl:message>Slv Bif <xsl:value-of select="$bifName_"/> : <xsl:value-of select="position()"/></xsl:message>
- <xsl:variable name="modBifs_" select="$modInst_/BUSINTERFACES"/>
- <xsl:if test="$periValidBifs_[(@NAME = $bifName_)]">
- <xsl:variable name="busName_" select="$periValidBifs_[(@NAME = $bifName_)]/@BUSNAME"/>
- <xsl:message>Mod Bif <xsl:value-of select="$bifName_"/> : <xsl:value-of select="position()"/></xsl:message>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="$bifName_"/>
- </xsl:if>
- -->
- <!--
- <xsl:message>Module Instances <xsl:value-of select="$instName_"/> </xsl:message>
- <xsl:message>Base Name <xsl:value-of select="$baseName_"/> </xsl:message>
- <xsl:message>High Name <xsl:value-of select="$highName_"/> </xsl:message>
- <xsl:message>Valid bif names <xsl:value-of select="$valid_bifNames_"/> </xsl:message>
- <xsl:message>Valid bif names <xsl:value-of select="$valid_bifNames_"/> </xsl:message>
- <xsl:message>Valid bus names <xsl:value-of select="$valid_busNames_"/> </xsl:message>
- -->
-
-
- <xsl:variable name="var_bifNames_">
- <xsl:choose>
- <xsl:when test="string-length($valid_bifNames_) < 1">
- <xsl:choose>
- <xsl:when test="$periModClass_ = 'BUS'">Not Applicable</xsl:when>
- <xsl:otherwise>Not Connected</xsl:otherwise>
- </xsl:choose>
- </xsl:when>
- <xsl:otherwise><xsl:value-of select="$valid_bifNames_"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface(s)" NAME="BIFNAMES" VALUE="{$var_bifNames_}"/>
- <xsl:if test="(($num_of_periMemMapBifs_ > 0) and (string-length($valid_busNames_) > 0))">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$valid_busNames_}"/>
- </xsl:if>
- </SET> <!-- End of one processor memory range row -->
- </xsl:for-each> <!-- end of processor memory ranges loop -->
- </xsl:element><!-- End of Processor memory map set -->
- </xsl:for-each> <!-- end of processor module address space loop -->
-
- <!--
- Add branch for valid address that are not part of a processor's
- memory map. Usually modules that have just been added, but have
- not been connected to a bus yet.
- -->
-
- <xsl:variable name="nonProcAddresses_">
-
- <!-- Add a dummy non proc as a place holder. Otherwise the exsl:node-set test
- Below complains if the variable is completely empty
- -->
- <NONPROCADDRESS INSTANCE="__DUMMY__" BASENAME="__DUMMY__" HIGHNAME="__DUMMY__" BASEDECIMAL="__DUMMY__"/>
-
- <xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE)]))]">
- <xsl:variable name="nonProcInst_" select="@INSTANCE"/>
-
- <xsl:for-each select="MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
-
- <xsl:variable name="highName_" select="@HIGHNAME"/>
- <xsl:variable name="baseName_" select="@BASENAME"/>
- <xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
-
- <xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $nonProcInst_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])">
- <NONPROCADDRESS INSTANCE="{$nonProcInst_}" BASENAME="{$baseName_}" HIGHNAME="{$highName_}" BASEDECIMAL="{$baseDecimal_}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:for-each>
-
- </xsl:variable>
-
- <!-- Add unmapped addresses -->
- <xsl:variable name="hasUnMappedAddress">
- <xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]))]">
- <xsl:variable name="nonProcInst_" select="@INSTANCE"/>
- <xsl:for-each select="MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:variable name="highName_" select="@HIGHNAME"/>
- <xsl:variable name="baseName_" select="@BASENAME"/>
- <xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
- <xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $nonProcInst_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])"><xsl:value-of select="$nonProcInst_"/></xsl:if>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:if test="string-length($hasUnMappedAddress) > 1">
-
- <SET ID="Unmapped Addresses" CLASS="MODULE" ROW_INDEX="{$G_NUM_OF_PROCS_W_ADDRS}">
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="Unmapped Addresses"/>
-
- <xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]))]/MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
-
- <xsl:variable name="nonProcMod_" select="../.."/>
- <xsl:variable name="nonProcMMap_" select="$nonProcMod_/MEMORYMAP"/>
- <xsl:variable name="instance_" select="$nonProcMod_/@INSTANCE"/>
-
- <xsl:variable name="row_index_" select="position()"/>
- <xsl:variable name="instName_" select="$nonProcMod_/@INSTANCE"/>
- <xsl:variable name="highName_" select="@HIGHNAME"/>
- <xsl:variable name="baseName_" select="@BASENAME"/>
- <xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
-
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[((@BASENAME = $baseName_) and (@HIGHNAME = $highName_))]">
-
- <xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $instName_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])">
-
- <xsl:variable name="addr_id_"><xsl:value-of select="$baseName_"/>:<xsl:value-of select="$highName_"/></xsl:variable>
- <xsl:variable name="set_id_"><xsl:value-of select="$instName_"/>:<xsl:value-of select="$addr_id_"/></xsl:variable>
-
- <xsl:variable name="inst_modtype_" select="$nonProcMod_/@MODTYPE"/>
- <xsl:variable name="inst_viewicon_" select="$nonProcMod_/LICENSEINFO/@ICON_NAME"/>
- <xsl:variable name="inst_modclass_" select="$nonProcMod_/@MODCLASS"/>
- <xsl:variable name="inst_hwversion_" select="$nonProcMod_/@HWVERSION"/>
-
- <SET ID="{$set_id_}" CLASS="ADDRESS">
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$instance_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$inst_modtype_}" VIEWICON="{$inst_viewicon_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$inst_hwversion_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Address Type" NAME="MEMTYPE" VALUE="{@MEMTYPE}"/>
-
- <xsl:variable name="is_locked_">
- <xsl:if test="@IS_LOCKED = 'TRUE'">TRUE</xsl:if>
- <xsl:if test="not(@IS_LOCKED) or not(@IS_LOCKED = 'TRUE')">FALSE</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="baseAddrViewType_">
- <xsl:choose>
- <xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
- <xsl:otherwise>TEXTBOX</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="(@SIZEABRV and not(@SIZEABRV = 'U'))">
-
- <xsl:variable name="baseAddr_"><xsl:value-of select="translate(@BASEVALUE,&HEXU2L;)"/></xsl:variable>
- <xsl:variable name="highAddr_"><xsl:value-of select="translate(@HIGHVALUE,&HEXU2L;)"/></xsl:variable>
-
- <VARIABLE VIEWTYPE="{$baseAddrViewType_}" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE="{$baseAddr_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="High Address" NAME="HIGHVALUE" VALUE="{$highAddr_}"/>
-
- <xsl:if test="not(@MEMTYPE) or not(@MEMTYPE = 'BRIDGE')">
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
- </xsl:if>
-
- <xsl:if test="@MEMTYPE and (@MEMTYPE = 'BRIDGE') and not(@BRIDGE_TO)">
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
- </xsl:if>
-
- </xsl:if>
-
- <xsl:if test="(@SIZEABRV and (@SIZEABRV = 'U'))">
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE=""/>
- </xsl:if>
-
-
- <!--
- Lock, DCache and ICache removed in 11.1
-
- <xsl:if test="(@IS_CACHEABLE = 'TRUE')">
-
- <xsl:variable name="is_dcached_">
- <xsl:if test="(@IS_DCACHED = 'TRUE')">TRUE</xsl:if>
- <xsl:if test="(not(@IS_DCACHED) or not(@IS_DCACHED = 'TRUE'))">FALSE</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="is_icached_">
- <xsl:if test="(@IS_ICACHED = 'TRUE')">TRUE</xsl:if>
- <xsl:if test="(not(@IS_ICACHED) or not(@IS_ICACHED = 'TRUE'))">FALSE</xsl:if>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="DCache" NAME="IS_DCACHED" VALUE="{$is_dcached_}"/>
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="ICache" NAME="IS_ICACHED" VALUE="{$is_icached_}"/>
- </xsl:if>
- -->
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Base Name" NAME="BASENAME" VALUE="{@BASENAME}"/>
-
- <xsl:variable name="sizeViewType_">
- <xsl:choose>
- <xsl:when test="(@SIZEABRV and (@SIZEABRV = 'U'))">DROPDOWN</xsl:when>
- <xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
- <xsl:otherwise>DROPDOWN</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="{$sizeViewType_}" VIEWDISP="Size" NAME="SIZEABRV" VALUE="{@SIZEABRV}"/>
-
- <xsl:variable name="valid_bifNames_">
- <xsl:choose>
- <xsl:when test="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
- <!-- <xsl:message>Bif Name <xsl:value-of select="$bifName_"/> </xsl:message> -->
- <xsl:variable name="modBifs_" select="$nonProcMod_/BUSINTERFACES"/>
- <xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
- <xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="@BUSINTERFACE"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="modBifs_" select="$nonProcMod_"/>
- <xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
- <xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="@NAME"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="def_bifNames_">
- <xsl:choose>
- <xsl:when test="(string-length($valid_bifNames_) < 1) or ((string-length($valid_bifNames_) = 1) and ($valid_bifNames_ = ':'))">Not Connected</xsl:when>
- <xsl:when test="starts-with($valid_bifNames_,':')"><xsl:value-of select="substring-after($valid_bifNames_,':')"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="$valid_bifNames_"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface(s)" NAME="BIFNAMES" VALUE="{$def_bifNames_}"/>
-
- <xsl:choose>
- <xsl:when test="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
- <xsl:variable name="slvBifName_" select="@BUSINTERFACE"/>
- <xsl:variable name="modBifs_" select="$nonProcMod_/BUSINTERFACES"/>
- <xsl:if test="count($modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]) = 1">
- <xsl:variable name="slvBusName_" select="$modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$slvBusName_}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
- <xsl:variable name="slvBifName_" select="@NAME"/>
- <xsl:variable name="modBifs_" select="$nonProcMod_"/>
- <xsl:if test="count($modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]) = 1">
- <xsl:variable name="slvBusName_" select="$modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$slvBusName_}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:otherwise>
- </xsl:choose>
-
-
- </SET> <!-- End of one non processor memory range row -->
- </xsl:if>
-
- </xsl:for-each> <!-- end of non processor memory ranges loop -->
-
- </xsl:for-each> <!-- end of NONPROCADDRESS loop -->
-
- </SET> <!-- End of non processor tree branch -->
-
- </xsl:if> <!-- End of test to see if we have and non processor mapped address -->
-
-</xsl:template>
-
-
-<xsl:template name="__WRITE_VIEW_ADDRESS__">
-
-<!--
--->
- <xsl:for-each select="$G_SYS_MODS/MODULE[((@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE)]))]">
- <xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
-
- <xsl:variable name="procInst_" select="@INSTANCE"/>
- <xsl:variable name="modClass_" select="@MODCLASS"/>
-
- <xsl:variable name="procInstHdrVal_"><xsl:value-of select="$procInst_"/>'s Address Map</xsl:variable>
- <xsl:variable name="procInstRowIdx_" select="position() - 1"/>
- <xsl:variable name="modInstance_" select="self::node()"/>
-
- <SET ID="{$procInst_}" CLASS="MODULE" ROW_INDEX="{$procInstRowIdx_}">
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$procInstHdrVal_}"/>
-
- <xsl:for-each select="$modInstance_/MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (ACCESSROUTE or (@MEMTYPE = 'BRIDGE')))]">
- <xsl:sort data-type="number" select="@BASEDECIMAL" order="ascending"/>
-
- <xsl:variable name="addr_id_"><xsl:value-of select="@BASENAME"/>:<xsl:value-of select="@HIGHNAME"/></xsl:variable>
- <xsl:variable name="baseName_" select="@BASENAME"/>
- <xsl:variable name="highName_" select="@HIGHNAME"/>
-
- <xsl:if test="$G_DEBUG='TRUE'">
- <xsl:message>ADDRESS ID <xsl:value-of select="$addr_id_"/></xsl:message>
- </xsl:if>
-
- <xsl:variable name="set_id_">
- <xsl:if test="(@INSTANCE)">
- <xsl:value-of select="$procInst_"/>.<xsl:value-of select="@INSTANCE"/>:<xsl:value-of select="$addr_id_"/>
- </xsl:if>
- <xsl:if test="not(@INSTANCE)">
- <xsl:value-of select="$procInst_"/>:<xsl:value-of select="$addr_id_"/>
- </xsl:if>
- </xsl:variable>
-
- <xsl:variable name="procAddrRowIdx_" select="position() - 1"/>
- <SET ID="{$set_id_}" CLASS="ADDRESS" ROW_INDEX="{$procAddrRowIdx_}">
-
- <xsl:if test="(@INSTANCE)">
- <xsl:variable name="instance_" select="@INSTANCE"/>
- <xsl:variable name="subInstance_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $instance_)]"/>
-
- <xsl:variable name="inst_modtype_" select="$subInstance_/@MODTYPE"/>
- <xsl:variable name="inst_viewicon_" select="$subInstance_/LICENSEINFO/@ICON_NAME"/>
- <xsl:variable name="inst_hwversion_" select="$subInstance_/@HWVERSION"/>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$instance_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$inst_modtype_}" VIEWICON="{$inst_viewicon_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$inst_hwversion_}"/>
- </xsl:if>
-
- <xsl:if test="not(@INSTANCE)">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$modInstance_/@INSTANCE}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$modInstance_/@MODTYPE}" VIEWICON="{$modInstance_/LICENSEINFO/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$modInstance_/@HWVERSION}"/>
- </xsl:if>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Address Type" NAME="MEMTYPE" VALUE="{@MEMTYPE}"/>
-
- <xsl:variable name="instName_">
- <xsl:choose>
- <xsl:when test="@INSTANCE"><xsl:value-of select="@INSTANCE"/></xsl:when>
- <xsl:otherwise>Connected<xsl:value-of select="$modInstance_/@INSTANCE"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <!--
- <xsl:message>INST : <xsl:value-of select="$set_id_"/></xsl:message>
- -->
-
- <xsl:variable name="is_locked_">
- <xsl:if test="@IS_LOCKED = 'TRUE'">TRUE</xsl:if>
- <xsl:if test="not(@IS_LOCKED) or not(@IS_LOCKED = 'TRUE')">FALSE</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="baseAddrViewType_">
- <xsl:choose>
- <xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
- <xsl:otherwise>TEXTBOX</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="(@SIZEABRV and not(@SIZEABRV = 'U'))">
- <xsl:variable name="baseAddr_"><xsl:value-of select="translate(@BASEVALUE,&HEXU2L;)"/></xsl:variable>
- <xsl:variable name="highAddr_"><xsl:value-of select="translate(@HIGHVALUE,&HEXU2L;)"/></xsl:variable>
- <VARIABLE VIEWTYPE="{$baseAddrViewType_}" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE="{$baseAddr_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="High Address" NAME="HIGHVALUE" VALUE="{$highAddr_}"/>
-
- <xsl:if test="not(@MEMTYPE) or not(@MEMTYPE = 'BRIDGE')">
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
- </xsl:if>
-
- <xsl:if test="@MEMTYPE and (@MEMTYPE = 'BRIDGE') and not(@BRIDGE_TO)">
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
- </xsl:if>
-
- </xsl:if>
-
- <xsl:if test="(@SIZEABRV and (@SIZEABRV = 'U'))">
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE=""/>
- </xsl:if>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Base Name" NAME="BASENAME" VALUE="{@BASENAME}"/>
-
- <xsl:variable name="sizeViewType_">
- <xsl:choose>
- <xsl:when test="(@SIZEABRV and (@SIZEABRV = 'U'))">DROPDOWN</xsl:when>
- <xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
- <xsl:otherwise>DROPDOWN</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="{$sizeViewType_}" VIEWDISP="Size" NAME="SIZEABRV" VALUE="{@SIZEABRV}"/>
-
- <xsl:variable name="modInst_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $instName_)]"/>
- <xsl:variable name="modMemMap_" select="$modInst_/MEMORYMAP"/>
-
- <xsl:variable name="valid_bifNames_">
- <xsl:choose>
- <xsl:when test="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
- <xsl:for-each select="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
- <!-- <xsl:message>Bif Name <xsl:value-of select="$bifName_"/> </xsl:message> -->
- <xsl:variable name="modBifs_" select="$modInst_/BUSINTERFACES"/>
- <xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
- <xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="@BUSINTERFACE"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:for-each select="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="modBifs_" select="$modInst_"/>
- <xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
- <xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="@NAME"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <!--
- <xsl:message>Module Instances <xsl:value-of select="$instName_"/> </xsl:message>
- <xsl:message>Base Name <xsl:value-of select="$baseName_"/> </xsl:message>
- <xsl:message>High Name <xsl:value-of select="$highName_"/> </xsl:message>
- <xsl:message>Valid bif names <xsl:value-of select="$valid_bifNames_"/> </xsl:message>
- -->
-
-
- <xsl:variable name="def_bifNames_">
- <xsl:choose>
- <xsl:when test="string-length($valid_bifNames_) < 1">
- <xsl:choose>
- <xsl:when test="$modClass_ = 'BUS'">Not Applicable</xsl:when>
- <xsl:otherwise>Not Connected</xsl:otherwise>
- </xsl:choose>
- </xsl:when>
- <xsl:when test="starts-with($valid_bifNames_,':')"><xsl:value-of select="substring-after($valid_bifNames_,':')"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="$valid_bifNames_"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface(s)" NAME="BIFNAMES" VALUE="{$def_bifNames_}"/>
-
- <xsl:choose>
- <xsl:when test="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
- <xsl:for-each select="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
- <xsl:variable name="modBifs_" select="$modInst_/BUSINTERFACES"/>
- <xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
- <xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <xsl:variable name="numBifs_" select="count($modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))])"/>
- <xsl:if test="((position() = 1) or ($numBifs_ = 1))">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$busName_}"/>
- </xsl:if>
- </xsl:if>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:for-each select="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="modBifs_" select="$modInst_"/>
- <xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
- <xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <xsl:variable name="numBifs_" select="count($modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))])"/>
- <xsl:if test="((position() = 1) or ($numBifs_ = 1))">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$busName_}"/>
- </xsl:if>
- </xsl:if>
- </xsl:for-each>
- </xsl:otherwise>
- </xsl:choose>
-<!--
- -->
- </SET> <!-- End of one processor memory range row -->
- </xsl:for-each> <!-- end of processor memory ranges loop -->
- </SET>
- </xsl:for-each> <!-- end of processor module address space loop -->
-
- <!--
- Add branch for valid address that are not part of a processor's
- memory map. Usually modules that have just been added, but have
- not been connected to a bus yet.
- -->
-
- <xsl:variable name="nonProcAddresses_">
-
- <!-- Add a dummy non proc as a place holder. Otherwise the exsl:node-set test
- Below complains if the variable is completely empty
- -->
- <NONPROCADDRESS INSTANCE="__DUMMY__" BASENAME="__DUMMY__" HIGHNAME="__DUMMY__" BASEDECIMAL="__DUMMY__"/>
-
- <xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE)]))]">
- <xsl:variable name="nonProcInst_" select="@INSTANCE"/>
-
- <xsl:for-each select="MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
-
- <xsl:variable name="highName_" select="@HIGHNAME"/>
- <xsl:variable name="baseName_" select="@BASENAME"/>
- <xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
-
- <xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $nonProcInst_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])">
- <NONPROCADDRESS INSTANCE="{$nonProcInst_}" BASENAME="{$baseName_}" HIGHNAME="{$highName_}" BASEDECIMAL="{$baseDecimal_}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:for-each>
-
- </xsl:variable>
-
- <!-- Add unmapped addresses -->
- <xsl:variable name="hasUnMappedAddress">
- <xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]))]">
- <xsl:variable name="nonProcInst_" select="@INSTANCE"/>
- <xsl:for-each select="MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:variable name="highName_" select="@HIGHNAME"/>
- <xsl:variable name="baseName_" select="@BASENAME"/>
- <xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
- <xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $nonProcInst_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])"><xsl:value-of select="$nonProcInst_"/></xsl:if>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:if test="string-length($hasUnMappedAddress) > 1">
-
- <SET ID="Unmapped Addresses" CLASS="MODULE" ROW_INDEX="{$G_NUM_OF_PROCS_W_ADDRS}">
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="Unmapped Addresses"/>
-
- <xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]))]/MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
-
- <xsl:variable name="nonProcMod_" select="../.."/>
- <xsl:variable name="nonProcMMap_" select="$nonProcMod_/MEMORYMAP"/>
- <xsl:variable name="instance_" select="$nonProcMod_/@INSTANCE"/>
-
- <xsl:variable name="row_index_" select="position()"/>
- <xsl:variable name="instName_" select="$nonProcMod_/@INSTANCE"/>
- <xsl:variable name="highName_" select="@HIGHNAME"/>
- <xsl:variable name="baseName_" select="@BASENAME"/>
- <xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
-
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[((@BASENAME = $baseName_) and (@HIGHNAME = $highName_))]">
-
- <xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $instName_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])">
-
- <xsl:variable name="addr_id_"><xsl:value-of select="$baseName_"/>:<xsl:value-of select="$highName_"/></xsl:variable>
- <xsl:variable name="set_id_"><xsl:value-of select="$instName_"/>:<xsl:value-of select="$addr_id_"/></xsl:variable>
-
- <xsl:variable name="inst_modtype_" select="$nonProcMod_/@MODTYPE"/>
- <xsl:variable name="inst_viewicon_" select="$nonProcMod_/LICENSEINFO/@ICON_NAME"/>
- <xsl:variable name="inst_modclass_" select="$nonProcMod_/@MODCLASS"/>
- <xsl:variable name="inst_hwversion_" select="$nonProcMod_/@HWVERSION"/>
-
- <SET ID="{$set_id_}" CLASS="ADDRESS">
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$instance_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$inst_modtype_}" VIEWICON="{$inst_viewicon_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$inst_hwversion_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Address Type" NAME="MEMTYPE" VALUE="{@MEMTYPE}"/>
-
- <xsl:variable name="is_locked_">
- <xsl:if test="@IS_LOCKED = 'TRUE'">TRUE</xsl:if>
- <xsl:if test="not(@IS_LOCKED) or not(@IS_LOCKED = 'TRUE')">FALSE</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="baseAddrViewType_">
- <xsl:choose>
- <xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
- <xsl:otherwise>TEXTBOX</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="(@SIZEABRV and not(@SIZEABRV = 'U'))">
-
- <xsl:variable name="baseAddr_"><xsl:value-of select="translate(@BASEVALUE,&HEXU2L;)"/></xsl:variable>
- <xsl:variable name="highAddr_"><xsl:value-of select="translate(@HIGHVALUE,&HEXU2L;)"/></xsl:variable>
-
- <VARIABLE VIEWTYPE="{$baseAddrViewType_}" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE="{$baseAddr_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="High Address" NAME="HIGHVALUE" VALUE="{$highAddr_}"/>
-
- <xsl:if test="not(@MEMTYPE) or not(@MEMTYPE = 'BRIDGE')">
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
- </xsl:if>
-
- <xsl:if test="@MEMTYPE and (@MEMTYPE = 'BRIDGE') and not(@BRIDGE_TO)">
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
- </xsl:if>
-
- </xsl:if>
-
- <xsl:if test="(@SIZEABRV and (@SIZEABRV = 'U'))">
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE=""/>
- </xsl:if>
-
-
- <!--
- Lock, DCache and ICache removed in 11.1
-
- <xsl:if test="(@IS_CACHEABLE = 'TRUE')">
-
- <xsl:variable name="is_dcached_">
- <xsl:if test="(@IS_DCACHED = 'TRUE')">TRUE</xsl:if>
- <xsl:if test="(not(@IS_DCACHED) or not(@IS_DCACHED = 'TRUE'))">FALSE</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="is_icached_">
- <xsl:if test="(@IS_ICACHED = 'TRUE')">TRUE</xsl:if>
- <xsl:if test="(not(@IS_ICACHED) or not(@IS_ICACHED = 'TRUE'))">FALSE</xsl:if>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="DCache" NAME="IS_DCACHED" VALUE="{$is_dcached_}"/>
- <VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="ICache" NAME="IS_ICACHED" VALUE="{$is_icached_}"/>
- </xsl:if>
- -->
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Base Name" NAME="BASENAME" VALUE="{@BASENAME}"/>
-
- <xsl:variable name="sizeViewType_">
- <xsl:choose>
- <xsl:when test="(@SIZEABRV and (@SIZEABRV = 'U'))">DROPDOWN</xsl:when>
- <xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
- <xsl:otherwise>DROPDOWN</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="{$sizeViewType_}" VIEWDISP="Size" NAME="SIZEABRV" VALUE="{@SIZEABRV}"/>
-
- <xsl:variable name="valid_bifNames_">
- <xsl:choose>
- <xsl:when test="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
- <xsl:variable name="bifName_" select="@BUSINTERFACE"/>
- <!-- <xsl:message>Bif Name <xsl:value-of select="$bifName_"/> </xsl:message> -->
- <xsl:variable name="modBifs_" select="$nonProcMod_/BUSINTERFACES"/>
- <xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
- <xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="@BUSINTERFACE"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="modBifs_" select="$nonProcMod_"/>
- <xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
- <xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <xsl:if test="position() > 1">:</xsl:if><xsl:value-of select="@NAME"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="def_bifNames_">
- <xsl:choose>
- <xsl:when test="(string-length($valid_bifNames_) < 1) or ((string-length($valid_bifNames_) = 1) and ($valid_bifNames_ = ':'))">Not Connected</xsl:when>
- <xsl:when test="starts-with($valid_bifNames_,':')"><xsl:value-of select="substring-after($valid_bifNames_,':')"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="$valid_bifNames_"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface(s)" NAME="BIFNAMES" VALUE="{$def_bifNames_}"/>
-
- <xsl:choose>
- <xsl:when test="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
- <xsl:variable name="slvBifName_" select="@BUSINTERFACE"/>
- <xsl:variable name="modBifs_" select="$nonProcMod_/BUSINTERFACES"/>
- <xsl:if test="count($modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]) = 1">
- <xsl:variable name="slvBusName_" select="$modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$slvBusName_}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
- <xsl:variable name="slvBifName_" select="@NAME"/>
- <xsl:variable name="modBifs_" select="$nonProcMod_"/>
- <xsl:if test="count($modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]) = 1">
- <xsl:variable name="slvBusName_" select="$modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$slvBusName_}"/>
- </xsl:if>
- </xsl:for-each>
- </xsl:otherwise>
- </xsl:choose>
-
-
- </SET> <!-- End of one non processor memory range row -->
- </xsl:if>
-
- </xsl:for-each> <!-- end of non processor memory ranges loop -->
-
- </xsl:for-each> <!-- end of NONPROCADDRESS loop -->
-
- </SET> <!-- End of non processor tree branch -->
-
- </xsl:if> <!-- End of test to see if we have and non processor mapped address -->
-
-</xsl:template>
-
-</xsl:stylesheet>
-
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<!DOCTYPE stylesheet [
- <!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
- <!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
-
- <!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
- <!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
-
- <!ENTITY ALPHALOWER "ABCDEFxX0123456789">
- <!ENTITY HEXUPPER "ABCDEFxX0123456789">
- <!ENTITY HEXLOWER "abcdefxX0123456789">
- <!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
-]>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="exsl dyn math xlink">
-
-
-<!--
- ================================================================================
- Generate XTeller for BIFS
- ================================================================================
--->
-
-<xsl:template name="WRITE_VIEW_BIF_TREE">
-
- <xsl:for-each select="$G_SYS_MODS/MODULE">
-
- <xsl:variable name="modRef_" select="self::node()"/>
- <xsl:variable name="m_inst_" select="$modRef_/@INSTANCE"/>
-
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="@INSTANCE"/></xsl:attribute>
- <xsl:attribute name="CLASS">MODULE</xsl:attribute>
-
- <xsl:choose>
- <xsl:when test="$modRef_/@POTENTIAL_INDEX">
- <xsl:attribute name="POTENTIAL_INDEX"><xsl:value-of select="$modRef_/@POTENTIAL_INDEX"/></xsl:attribute>
- </xsl:when>
- <xsl:when test="$modRef_/@CONNECTED_INDEX">
- <xsl:attribute name="CONNECTED_INDEX"><xsl:value-of select="$modRef_/@CONNECTED_INDEX"/></xsl:attribute>
- </xsl:when>
- </xsl:choose>
-
- <!--
- CR452579
- Can only modify INSTANCE name in Hierarchal view.
- -->
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{@INSTANCE}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{@MODTYPE}" VIEWICON="{LICENSEINFO/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{@HWVERSION}"/>
-
- <xsl:variable name="ipClassification_">
- <xsl:call-template name="F_ModClass_To_IpClassification">
- <xsl:with-param name="iModClass" select="@MODCLASS"/>
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
-
- <!-- Write Bus Interfaces here -->
- <xsl:for-each select="$G_SYS_MODS"> <!-- To put things in the right scope for the keys below -->
- <xsl:variable name="m_bifs_all_" select="key('G_MAP_ALL_BIFS', $m_inst_)"/>
- <xsl:for-each select="$m_bifs_all_">
- <xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
- <xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
- <xsl:with-param name="iModRef" select="$modRef_"/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- </xsl:call-template>
- </xsl:for-each> <!-- End of bus interface loop -->
- </xsl:for-each>
- </xsl:element>
- </xsl:for-each> <!-- End module loop -->
-</xsl:template>
-
-
-<xsl:template name="WRITE_VIEW_BIF_TREE_SET">
- <xsl:param name="iModRef" select="'__NONE__'"/>
- <xsl:param name="iBifRef" select="'__NONE__'"/>
- <xsl:param name="iBifCol" select="'__NONE__'"/>
-
- <xsl:element name="SET">
- <xsl:if test="not($iBifCol = '__NONE__')">
- <xsl:attribute name="RGB_FG"><xsl:value-of select="$iBifCol"/></xsl:attribute>
- </xsl:if>
- <xsl:attribute name="ID"><xsl:value-of select="$iBifRef/@NAME"/></xsl:attribute>
- <xsl:attribute name="CLASS">BUSINTERFACE</xsl:attribute>
-
- <xsl:if test="($iBifRef/@TYPE = 'MONITOR')">
- <xsl:choose>
- <xsl:when test="($iBifRef/@IS_P2P)">
- <xsl:attribute name="IS_P2P_MONITOR">TRUE</xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="IS_SHARED_MONITOR">TRUE</xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:if>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="NAME" NAME="NAME" VALUE="{$iBifRef/@NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Type" NAME="TYPE" VALUE="{$iBifRef/@TYPE}"/>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
- <xsl:attribute name="NAME">BUSSTD</xsl:attribute>
- <xsl:choose>
- <xsl:when test="($iBifRef/@BUSSTD_PSF)">
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSSTD_PSF"/></xsl:attribute>
- </xsl:when>
- <xsl:when test="($iBifRef/@BUSSTD)">
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSSTD"/></xsl:attribute>
- </xsl:when>
- <xsl:when test="($iBifRef/@BUS_STD)">
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUS_STD"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VALUE">USER</xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:element>
-
- <xsl:choose>
- <xsl:when test="($iBifRef/@TYPE = 'INITIATOR')">
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWTYPE">TEXTBOX</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:choose>
- <xsl:when test="(($iBifRef/@BUSNAME = '__NOC__') or ($iBifRef/@BUSNAME = '') or not($iBifRef/@BUSNAME))">
- <xsl:variable name="def_noc_name_"><xsl:value-of select="$iModRef/@INSTANCE"/>_<xsl:value-of select="$iBifRef/@NAME"/></xsl:variable>
- <xsl:attribute name="VALUE"><xsl:value-of select="$def_noc_name_"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:choose>
- <xsl:when test="(($iBifRef/@BUSNAME = '__NOC__') or ($iBifRef/@BUSNAME = '') or not($iBifRef/@BUSNAME))">
- <xsl:element name="VARIABLE">
- <xsl:choose>
- <xsl:when test="(($iBifRef/@BUSSTD = 'AXI') and ($iBifRef/@TYPE = 'SLAVE') and ($G_HAVE_XB_BUSSES = 'TRUE'))">
- <xsl:attribute name="VIEWTYPE">BUTTON</xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE">No Connection</xsl:attribute>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:choose>
- <xsl:when test="(($iBifRef/@TYPE = 'MONITOR') and ($iBifRef/MONITORS/MONITOR))">
- <xsl:variable name="monitorBif_" select="$iBifRef/MONITORS/MONITOR"/>
- <xsl:variable name="p2pMonConn_" select="concat($monitorBif_/@INSTANCE,'.',$monitorBif_/@BUSINTERFACE)"/>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$p2pMonConn_"/></xsl:attribute>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:when>
-
- <xsl:when test="($iBifRef/@TYPE = 'SLAVE')">
- <xsl:element name="VARIABLE">
- <xsl:choose>
- <xsl:when test="(($iBifRef/@BUSSTD = 'AXI') and ($G_HAVE_XB_BUSSES ='TRUE'))">
- <xsl:attribute name="VIEWTYPE">BUTTON</xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:choose>
- <xsl:when test="$iBifRef/MASTERS/MASTER">
- <xsl:variable name="mastersList_"><xsl:for-each select="$iBifRef/MASTERS/MASTER"><xsl:if test="position() > 1"> & </xsl:if><xsl:value-of select="concat(@INSTANCE,'.',@BUSINTERFACE)"/></xsl:for-each></xsl:variable>
- <xsl:variable name="mastersConn_" select="concat($iBifRef/@BUSNAME,':',$mastersList_)"/>
- <xsl:attribute name="VALUE"><xsl:value-of select="$mastersConn_"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:element>
-</xsl:template>
-
-
-<xsl:template name="WRITE_VIEW_BIF_FLAT">
-
- <xsl:for-each select="$G_SYS_MODS/MODULE">
-
- <xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
- <xsl:variable name="moduleRef_" select="self::node()"/>
- <xsl:variable name="busifsRef_">
- <xsl:choose>
- <xsl:when test="self::node()/BUSINTERFACES"><xsl:text>$moduleRef_/BUSINTERFACES</xsl:text></xsl:when>
- <xsl:otherwise><xsl:text>$moduleRef_</xsl:text></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <xsl:for-each select="dyn:evaluate($busifsRef_)/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
- <xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
- <xsl:with-param name="iModRef" select="$moduleRef_"/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- </xsl:call-template>
- </xsl:for-each> <!-- End of Bus Interface Loop -->
- </xsl:for-each> <!-- End of Module loop -->
-</xsl:template>
-
-<xsl:template name="WRITE_VIEW_BIF_FLAT_SET">
-
- <xsl:param name="iModRef" select="'__NONE__'"/>
- <xsl:param name="iBifRef" select="'__NONE__'"/>
- <xsl:param name="iBifCol" select="'__NONE__'"/>
-
- <xsl:element name="SET">
- <xsl:if test="not($iBifCol = '__NONE__')">
- <xsl:attribute name="RGB_FG"><xsl:value-of select="$iBifCol"/></xsl:attribute>
- </xsl:if>
- <!--
- <xsl:attribute name="ID"><xsl:value-of select="$iModRef/@INSTANCE"/>.<xsl:value-of select="$iBifRef/@NAME"/></xsl:attribute>
- -->
- <xsl:attribute name="ID"><xsl:value-of select="$iBifRef/@NAME"/></xsl:attribute>
- <xsl:attribute name="CLASS">BUSINTERFACE</xsl:attribute>
-
- <xsl:if test="($iBifRef/@TYPE = 'MONITOR')">
- <xsl:choose>
- <xsl:when test="($iBifRef/@IS_P2P)">
- <xsl:attribute name="IS_P2P_MONITOR">TRUE</xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="IS_SHARED_MONITOR">TRUE</xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:if>
-
- <!-- CR452579 Can only modify INSTANCE name in Hierarchal view. -->
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$iModRef/@INSTANCE}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface" NAME="NAME" VALUE="{$iBifRef/@NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$iModRef/@MODTYPE}" VIEWICON="{$iModRef/LICENSEINFO/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$iModRef/@HWVERSION}"/>
-
- <xsl:variable name="ipClassification_">
- <xsl:call-template name="F_ModClass_To_IpClassification">
- <xsl:with-param name="iModClass" select="$iModRef/@MODCLASS"/>
- <xsl:with-param name="iBusStd" select="$iBifRef/@BUSSTD"/>
- </xsl:call-template>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Type" NAME="TYPE" VALUE="{$iBifRef/@TYPE}"/>
-
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
- <xsl:attribute name="NAME">BUSSTD</xsl:attribute>
- <xsl:choose>
- <xsl:when test="($iBifRef/@BUS_STD)">
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUS_STD"/></xsl:attribute>
- </xsl:when>
- <xsl:when test="($iBifRef/@BUSSTD)">
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSSTD"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VALUE">USER</xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:element>
-
- <xsl:choose>
- <xsl:when test="$iBifRef/@TYPE = 'INITIATOR'">
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWTYPE">TEXTBOX</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:choose>
- <xsl:when test="(($iBifRef/@BUSNAME = '__NOC__') or ($iBifRef/@BUSNAME = '') or not($iBifRef/@BUSNAME))">
- <xsl:variable name="def_noc_name_"><xsl:value-of select="$iModRef/@INSTANCE"/>_<xsl:value-of select="$iBifRef/@NAME"/></xsl:variable>
- <xsl:attribute name="VALUE"><xsl:value-of select="$def_noc_name_"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:when>
- <xsl:otherwise>
- <xsl:choose>
-
- <xsl:when test="(($iBifRef/@BUSNAME = '__NOC__') or ($iBifRef/@BUSNAME = '') or not($iBifRef/@BUSNAME))">
- <xsl:element name="VARIABLE">
- <xsl:choose>
- <xsl:when test="(($iBifRef/@BUSSTD = 'AXI') and ($iBifRef/@TYPE = 'SLAVE') and ($G_HAVE_XB_BUSSES = 'TRUE'))">
- <xsl:attribute name="VIEWTYPE">BUTTON</xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE">No Connection</xsl:attribute>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:choose>
- <xsl:when test="(($iBifRef/@TYPE = 'MONITOR') and ($iBifRef/MONITORS/MONITOR))">
- <xsl:variable name="monitorBif_" select="$iBifRef/MONITORS/MONITOR"/>
- <xsl:variable name="p2pMonConn_" select="concat($monitorBif_/@INSTANCE,'.',$monitorBif_/@BUSINTERFACE)"/>
- <!--
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$p2pMonConn_}"/>
- -->
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$p2pMonConn_"/></xsl:attribute>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:when>
-
- <xsl:when test="($iBifRef/@TYPE = 'SLAVE')">
- <xsl:element name="VARIABLE">
- <xsl:choose>
- <xsl:when test="$iBifRef/@BUSSTD = 'AXI' and $G_HAVE_XB_BUSSES ='TRUE'">
- <xsl:attribute name="VIEWTYPE">BUTTON</xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:choose>
- <xsl:when test="$iBifRef/MASTERS/MASTER">
- <xsl:variable name="mastersList_"><xsl:for-each select="$iBifRef/MASTERS/MASTER"><xsl:if test="position() > 1"> & </xsl:if><xsl:value-of select="concat(@INSTANCE,'.',@BUSINTERFACE)"/></xsl:for-each></xsl:variable>
- <xsl:variable name="mastersConn_" select="concat($iBifRef/@BUSNAME,':',$mastersList_)"/>
- <xsl:attribute name="VALUE"><xsl:value-of select="$mastersConn_"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:when>
- <xsl:otherwise>
- <!--
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$iBifRef/@BUSNAME}"/>
- -->
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
- <xsl:if test="$G_ADD_CHOICES = 'TRUE'">
- <xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
- <xsl:with-param name="iModRef" select="$iModRef"/>
- <xsl:with-param name="iBifRef" select="$iBifRef"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:element>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:element>
-</xsl:template>
-
-<xsl:template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
-
- <xsl:param name="iModRef" select="None"/>
- <xsl:param name="iBifRef" select="None"/>
-
- <xsl:variable name="b_bus_" select="$iBifRef/@BUSNAME"/>
- <xsl:variable name="b_name_" select="$iBifRef/@NAME"/>
- <xsl:variable name="b_type_" select="$iBifRef/@TYPE"/>
- <xsl:variable name="b_bstd_" select="$iBifRef/@BUSSTD"/>
- <xsl:variable name="b_bstd_psf_" select="$iBifRef/@BUSSTD_PSF"/>
- <xsl:variable name="b_protocol_" select="$iBifRef/@PROTOCOL"/>
-
- <xsl:element name="CHOICES">
- <xsl:choose>
- <xsl:when test="($b_type_ = 'INITIATOR')">
- <xsl:variable name="initiator_busName_">
- <xsl:choose>
- <xsl:when test="($b_bus_ = '__NOC__')"><xsl:value-of select="concat($iModRef/@INSTANCE,'_',$b_name_)"/></xsl:when>
- <xsl:otherwise><xsl:value-of select="$b_bus_"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <CHOICE NAME="{$initiator_busName_}"/>
- </xsl:when>
-
- <xsl:when test="(($b_type_ = 'MASTER') or ($b_type_ = 'SLAVE') or ($b_type_ = 'MASTER_SLAVE'))">
- <CHOICE NAME="No Connection"/>
- <xsl:for-each select="$G_SYS_MODS"> <!-- To set correct scope for KEY functions below -->
- <xsl:if test="not(($b_bstd_ = 'AXI') and ($b_type_ = 'SLAVE'))">
- <CHOICE NAME="New Connection"/>
- </xsl:if>
- <xsl:for-each select="key('G_MAP_BUSSES',$b_bstd_)">
- <xsl:variable name="busName_" select="@INSTANCE"/>
- <xsl:choose>
- <!-- CR#590473 This was setting wrong choices filled up-->
- <!--xsl:when test="(($b_type_ = 'SLAVE') and (@IS_CROSSBAR) and $iBifRef/@PROTOCOL)">
- <xsl:for-each select="key('G_MAP_MST_BIFS',$busName_)[(@PROTOCOL = $b_protocol_)]">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="insName_" select="../../@INSTANCE"/>
- <xsl:variable name="xb_slave_busName_" select="concat($busName_,':',$insName_,'.',$bifName_)"/>
- <CHOICE NAME="{$xb_slave_busName_}"/>
- </xsl:for-each>
- </xsl:when-->
- <xsl:when test="($b_type_ = 'SLAVE') and (@IS_CROSSBAR)">
- <xsl:for-each select="key('G_MAP_MST_BIFS',$busName_)">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="insName_" select="../../@INSTANCE"/>
- <xsl:variable name="xb_slave_busName_" select="concat($busName_,':',$insName_,'.',$bifName_)"/>
- <CHOICE NAME="{$xb_slave_busName_}"/>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <CHOICE NAME="{$busName_}"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:when>
-
- <xsl:when test="($b_type_ = 'TARGET')">
- <CHOICE NAME="No Connection"/>
- <xsl:for-each select="$G_SYS_MODS"> <!-- To set correct scope for KEY functions below -->
- <xsl:variable name="use_bstd_">
- <xsl:choose>
- <xsl:when test="(($b_bstd_ = 'AXIS') or ($b_bstd_ = 'XIL'))">
- <xsl:value-of select="$b_bstd_psf_"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$b_bstd_"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <xsl:choose>
- <xsl:when test="$iBifRef/@PROTOCOL">
- <xsl:for-each select="key('G_MAP_P2P_BIFS',$use_bstd_)[(@TYPE = 'INITIATOR') and (@PROTOCOL = $b_protocol_)]">
- <xsl:variable name="busName_" select="@BUSNAME"/>
- <xsl:choose>
- <xsl:when test="($busName_ = '__NOC__')">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="insName_" select="../../@INSTANCE"/>
- <xsl:variable name="initiator_busName_" select="concat($insName_,'_',$bifName_)"/>
- <CHOICE NAME="{$initiator_busName_}"/>
- </xsl:when>
- <xsl:otherwise>
- <CHOICE NAME="{$busName_}"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:for-each select="key('G_MAP_P2P_BIFS',$use_bstd_)[(@TYPE = 'INITIATOR')]">
- <xsl:variable name="busName_" select="@BUSNAME"/>
- <xsl:choose>
- <xsl:when test="($busName_ = '__NOC__')">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="insName_" select="../../@INSTANCE"/>
- <xsl:variable name="initiator_busName_" select="concat($insName_,'_',$bifName_)"/>
- <CHOICE NAME="{$initiator_busName_}"/>
- </xsl:when>
- <xsl:otherwise>
- <CHOICE NAME="{$busName_}"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:when>
-
- <xsl:when test="($b_type_ = 'MONITOR')">
- <CHOICE NAME="No Connection"/>
- <xsl:for-each select="$G_SYS_MODS"> <!-- To set correct scope for KEY functions below -->
- <xsl:choose>
- <xsl:when test="($iBifRef/@IS_P2P = 'TRUE')">
- <xsl:for-each select="$G_SYS_MODS"> <!-- To set correct scope for KEY functions below -->
- <xsl:variable name="use_bstd_">
- <xsl:choose>
- <xsl:when test="(($b_bstd_ = 'AXIS') or ($b_bstd_ = 'XIL'))">
- <xsl:value-of select="$b_bstd_psf_"/>
- </xsl:when>
- <xsl:otherwise>
- <xsl:value-of select="$b_bstd_"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <!-- <xsl:message>monitor p2p <xsl:value-of select="count(key('G_MAP_P2P_BIFS',$use_bstd_)[(@TYPE = 'INITIATOR')])"/> </xsl:message> -->
- <xsl:for-each select="key('G_MAP_P2P_BIFS',$use_bstd_)[(@TYPE = 'INITIATOR')]">
- <xsl:variable name="busName_" select="@BUSNAME"/>
- <xsl:choose>
- <xsl:when test="($busName_ = '__NOC__')">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="insName_" select="../../@INSTANCE"/>
- <xsl:variable name="initiator_busName_" select="concat($insName_,'_',$bifName_)"/>
- <CHOICE NAME="{$initiator_busName_}"/>
- </xsl:when>
- <xsl:otherwise>
- <CHOICE NAME="{$busName_}"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <xsl:for-each select="key('G_MAP_BUSSES',$b_bstd_)">
- <xsl:variable name="busName_" select="@INSTANCE"/>
- <xsl:choose>
- <xsl:when test="(@IS_CROSSBAR or ($b_bstd_ = 'AXI'))">
- <xsl:for-each select="key('G_MAP_MOS_BIFS',$busName_)">
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="insName_" select="../../@INSTANCE"/>
- <!--
- <xsl:variable name="xb_moni_busName_" select="concat($busName_,':',$insName_,'.',$bifName_)"/>
- -->
- <xsl:variable name="xb_moni_busName_" select="concat($insName_,'.',$bifName_)"/>
- <CHOICE NAME="{$xb_moni_busName_}"/>
- </xsl:for-each>
- </xsl:when>
- <xsl:otherwise>
- <CHOICE NAME="{$busName_}"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:otherwise>
-
- </xsl:choose>
- </xsl:for-each>
- </xsl:when>
- </xsl:choose>
- </xsl:element>
-
-</xsl:template>
-
-
-
-</xsl:stylesheet>
-
+++ /dev/null
-<!DOCTYPE stylesheet [
- <!ENTITY ALPUPRS "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
- <!ENTITY ALPLWRS "abcdefghijklmnopqrstuvwxyz">
- <!ENTITY UPR2LWS " '&ALPUPRS;' , '&ALPLWRS;' ">
-
- <!ENTITY HEXUPPER "ABCDEFxx0123456789">
- <!ENTITY HEXLOWER "abcdefxX0123456789">
- <!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
-
- <!ENTITY DIV2SLSH " 'div' , '/' ">
-
- <!ENTITY NOT_ELM_CONN "not(name() = 'PARAMETER') and not(name() = 'PORT') and not(name() = 'BUSINTERFACE')">
- <!ENTITY NOT_BEF_CONN "not(name() = 'DOCUMENT') and not(name() = 'DOCUMENTATION') and not(name() = 'DESCRIPTION') and not(name() = 'LICENSEINFO')">
- <!ENTITY NOT_AFT_CONN "not(name() = 'MEMORYMP') and not(name() = 'PERIPHERALS') and not(name() = 'INTERRUPTINFO')">
-]>
-
-<!-- ==============================================================
- This XSL file converts BLOCK xml to SAV XTeller
- ============================================================== -->
-<xsl:stylesheet
- version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math exsl dyn xlink">
-
-<xsl:output method="xml"
- version="1.0"
- indent="yes"
- encoding="UTF-8"/>
-<!--
- ===================================================
- THE MAIN TEMPLATE FOR PORT VIEW SELECTED FOCUS
- ===================================================
--->
-<xsl:template name="WRITE_VIEW_PORT_FOCUSED">
- <xsl:choose>
- <xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:call-template name="WRITE_VIEW_EXTP_TREE_SET"/>
- </xsl:when>
- <xsl:when test="$G_ROOT/SAV/@MODE = 'FLAT'">
- <xsl:call-template name="WRITE_VIEW_EXTP_FLAT_SET"/>
- </xsl:when>
- </xsl:choose>
- <xsl:apply-templates select="$G_SYS_MODS/MODULE" mode="_port_view_focusing_on_selected"/>
-</xsl:template>
-
-
-<!--
- ====================================================
- THE MAIN TEMPLATE FOR BIF VIEW BUS FOCUS
- ====================================================
--->
-<xsl:template name="WRITE_VIEW_BIF_FOCUS_ON_BUSES">
-
-<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message>Focusing on busses</xsl:message></xsl:if>
-<!--
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
- <xsl:with-param name="iModules" select="$G_GROUPS"/>
- </xsl:call-template>
- -->
- <xsl:apply-templates select="$G_SYS_MODS/MODULE" mode="_bif_view_focusing_on_buses"/>
- <xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'"> <!-- The separator -->
- <xsl:element name="SET">
-
- <xsl:attribute name="ID">MODULES WITH POTENTIAL CONNECTIONS TO FOCUSED BUS</xsl:attribute>
- <xsl:attribute name="CLASS">SEPARATOR</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Name</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">Name</xsl:attribute>
- <xsl:attribute name="VALUE">POTENTIAL MODULES BELOW HERE</xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Type</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">MODTYPE</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Version</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">HWVERSION</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Classification</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">IPCLASS</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="VIEWTYPE"></xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Type</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">TYPE</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">BUSSTD</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- </xsl:element>
- </xsl:if>
-</xsl:template>
-
-<!--
- ====================================================
- THE MAIN TEMPLATE FOR BIF VIEW PROCESSOR FOCUS
- ====================================================
--->
-<xsl:template name="WRITE_VIEW_BIF_FOCUS_ON_PROCS">
-
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
- <xsl:with-param name="iModules" select="$G_GROUPS"/>
- </xsl:call-template>
-
- <xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'"> <!-- The separator -->
- <xsl:element name="SET">
-
- <xsl:attribute name="ID">MODULES WITH POTENTIAL CONNECTIONS TO THIS SUBSYSTEM</xsl:attribute>
- <xsl:attribute name="CLASS">SEPARATOR</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Name</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">Name</xsl:attribute>
- <xsl:attribute name="VALUE">POTENTIAL MODULES BELOW HERE</xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Type</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">MODTYPE</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Version</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">HWVERSION</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Classification</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">IPCLASS</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="VIEWTYPE"></xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Type</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">TYPE</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
-
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">BUSSTD</xsl:attribute>
- <xsl:attribute name="VALUE"></xsl:attribute>
- </xsl:element>
- </xsl:element>
- </xsl:if>
-</xsl:template>
-
-<!--
- ===============================================
- COPY TRANSFORMS FOR FOCUSING IN BIF VIEW
- ===============================================
--->
-
-<!-- Root copy template for connected -->
-<xsl:template match="node() | @*" mode="_bif_view_focusing_on_connected">
- <xsl:copy>
- <xsl:apply-templates select="@* | node()" mode="_bif_view_focusing_on_connected"/>
- </xsl:copy>
-</xsl:template>
-
-<!-- Root copy template for potentials -->
-<xsl:template match="node() | @*" mode="_bif_view_focusing_on_potentials">
- <xsl:copy>
- <xsl:apply-templates select="@* | node()" mode="_bif_view_focusing_on_potentials"/>
- </xsl:copy>
-</xsl:template>
-
-
-<xsl:template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES"> <!-- Recursive !! -->
- <xsl:param name="iModules"/>
-
- <xsl:for-each select="$iModules/BLOCK[@ID and not(BLOCK) and not(@C)]">
- <xsl:variable name="m_id_" select="@ID"/>
- <xsl:if test="(count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $m_id_]) > 0)">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING BUS <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
- <xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_connected"/>
- </xsl:if>
- </xsl:for-each>
-
- <xsl:for-each select="$iModules/BLOCK[@ID and BLOCK]">
- <xsl:choose>
-
- <!-- An actual module that needs to be written -->
- <xsl:when test="not(starts-with(@ID,'__')) and BLOCK[@C] and (not(BLOCK/BLOCK) or BLOCK/BLOCK[@CP])">
-
- <xsl:variable name="m_id_" select="@ID"/>
- <xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
- <xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_connected"/>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_PROCESSOR__.') or starts-with(@ID,'__GROUP_MASTER__.')">
-
- <!--
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>MASTER GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- -->
-
- <xsl:variable name="master_id_">
- <xsl:choose>
- <xsl:when test="starts-with(@ID,'__GROUP_MASTER__.')"><xsl:value-of select="substring-after(@ID,'__GROUP_MASTER__.')"/> </xsl:when>
- <xsl:when test="starts-with(@ID,'__GROUP_PROCESSOR__.')"><xsl:value-of select="substring-after(@ID,'__GROUP_PROCESSOR__.')"/> </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="num_focused_on_" select="count($G_ROOT/SAV/MASTER[(@INSTANCE = $master_id_)])"/>
-
- <xsl:choose>
- <xsl:when test="$num_focused_on_ > 0">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>CONNECTED MASTER GROUP <xsl:value-of select="$master_id_"/></xsl:message></xsl:if>
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>POTENTIAL MASTER GROUP <xsl:value-of select="$master_id_"/></xsl:message></xsl:if>
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_SHARED__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>SHARED GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:variable name="p_id_" select="substring-after(@ID,'__GROUP_SHARED__')"/>
-
- <xsl:variable name="num_focused_on_" select="count($G_ROOT/SAV/MASTER[contains($p_id_,@INSTANCE)])"/>
-
- <xsl:choose>
- <xsl:when test="$num_focused_on_ > 0">
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_MEMORY__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> MEMORY GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-
- <xsl:variable name="m_id_" select="substring-after(@ID,'__GROUP_MEMORY__')"/>
-
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_PERIPHERAL__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PERIPHERAL GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_SLAVES__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>SLAVE GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="(starts-with(@ID,'__GROUP_IP__') and not($G_ROOT/SAV/@VIEW = 'BUSINTERFACE'))">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>IP GROUP<xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_FLOATING__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>FLOATING GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:otherwise>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> IGNORING <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
-</xsl:template>
-
-
-
-<!--
- ===============================================
- TRANSFORMS FOR FOCUSED POTENTIAL MODULES
- ===============================================
--->
-<xsl:template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES"> <!-- Recursive !! -->
- <xsl:param name="iModules"/>
-
- <!-- BUS -->
- <xsl:for-each select="$iModules/BLOCK[@ID and not(BLOCK) and not(@C)]">
- <xsl:variable name="m_id_" select="@ID"/>
- <xsl:if test="(count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $m_id_]) > 0)">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING BUS <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
- <xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_connected"/>
- </xsl:if>
- </xsl:for-each>
-
- <!-- GROUP -->
- <xsl:for-each select="$iModules/BLOCK[@ID and BLOCK]">
- <xsl:choose>
- <xsl:when test="not(starts-with(@ID,'__')) and BLOCK[@C] and (not(BLOCK/BLOCK) or BLOCK/BLOCK[@CP])">
-
- <xsl:variable name="m_id_" select="@ID"/>
- <xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
- <xsl:variable name="m_class_" select="$m_module_/@MODCLASS"/>
- <xsl:choose>
- <xsl:when test ="not($m_class_ = 'PROCESSOR')">
- <xsl:variable name="potential_bifs_">
- <xsl:for-each select="$m_module_/BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:variable name="b_std_" select="@BUSSTD"/>
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><CONNECTED/></xsl:if>
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) > 0"><POTENTIAL/></xsl:if>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:variable name="num_potential_" select="count(exsl:node-set($potential_bifs_)/POTENTIAL)"/>
- <xsl:variable name="num_connected_" select="count(exsl:node-set($potential_bifs_)/CONNECTED)"/>
-
- <xsl:if test=" ($num_potential_ > 0)">
- <xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_potentials"/>
- </xsl:if>
- </xsl:when>
- <xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_id_)]) > 0">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PERI PROCESSOR <xsl:value-of select="$m_id_"/></xsl:message></xsl:if>
- <xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_potentials"/>
- </xsl:when>
- </xsl:choose>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_MEMORY__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING MEMORY <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-
- <xsl:variable name="m_id_" select="substring-after(@ID,'__GROUP_MEMORY__')"/>
-
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_PERIPHERAL__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING POTENTIAL GROUP OF PERIPHERALS <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_SLAVES__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING POTENTIAL GROUP OF SLAVES <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-
- <xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
- <xsl:otherwise>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> IGNORING <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
-</xsl:template>
-
-<!--
- +++++++++++++++++++++++++++++++++++++++++++++++++++++
- MODULE TEMPLATES
- +++++++++++++++++++++++++++++++++++++++++++++++++++++
--->
-
-<!--
- ===================================================
- THE MODULE TEMPLATE FOR PORT VIEW SELECTED FOCUS
- ===================================================
--->
-
-<xsl:template match="MODULE" mode="_port_view_focusing_on_selected">
- <xsl:variable name="m_inst_" select="@INSTANCE"/>
-
- <xsl:if test="count($G_ROOT/SAV/SELECTED[(@INSTANCE = $m_inst_)]) > 0">
- <xsl:choose>
- <xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:call-template name="WRITE_VIEW_PORT_TREE_SET">
- <xsl:with-param name="iModRef" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="$G_ROOT/SAV/@MODE = 'FLAT'">
- <xsl:call-template name="WRITE_VIEW_PORT_FLAT_SET">
- <xsl:with-param name="iModRef" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
- </xsl:choose>
- </xsl:if>
-</xsl:template>
-
-<!--
- ===================================================
- THE MODULE TEMPLATE FOR BIF VIEW BUS FOCUS
- ===================================================
--->
-<xsl:template match="MODULE" mode="_bif_view_focusing_on_buses">
-
- <xsl:variable name="m_instance_" select="@INSTANCE"/>
- <xsl:variable name="m_modclass_" select="@MODCLASS"/>
-
- <xsl:variable name="is_focused_bus_" select="count($G_ROOT/SAV/BUS[(@INSTANCE = $m_instance_)])"/>
-
- <xsl:variable name="bif_scope_">
- <xsl:if test="$is_focused_bus_ = 0"> <!-- No need to waste time if we know its one of the focused bus -->
- <xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
- <xsl:variable name="b_bstd_" select="@BUSSTD"/>
- <xsl:variable name="b_on_focused_bus_" select="count($G_ROOT/SAV/BUS[(@INSTANCE = $b_bus_)])"/>
- <xsl:variable name="b_of_focused_bstd_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_bstd_])"/>
- <xsl:if test="$b_on_focused_bus_ > 0"><CONNECTED/></xsl:if>
- <xsl:if test="$b_of_focused_bstd_ > 0"><POTENTIAL/></xsl:if>
- </xsl:for-each>
- </xsl:if>
- </xsl:variable>
-
- <xsl:variable name="on_focused_bus_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
- <xsl:variable name="of_focused_bstd_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
-
- <xsl:if test="(($is_focused_bus_ + $on_focused_bus_ + $of_focused_bstd_) > 0)">
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING MODULE ON BUS <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
-
- <xsl:choose>
- <!-- TREE VIEW -->
- <xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="@INSTANCE"/></xsl:attribute>
- <xsl:attribute name="CLASS">MODULE</xsl:attribute>
-
- <xsl:if test="($is_focused_bus_ > 0)">
- <xsl:attribute name="RGB_BG"><xsl:value-of select="$COL_FOCUSED_MASTER"/></xsl:attribute>
- </xsl:if>
-
- <xsl:choose>
-
- <xsl:when test="(($is_focused_bus_ + $on_focused_bus_) > 0)">
- <xsl:attribute name="CONNECTED_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="POTENTIAL_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
-
-
-
- <!-- CR452579 Can only modify INSTANCE name in Hierarchal view. -->
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{@INSTANCE}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{@MODTYPE}" VIEWICON="{LICENSEINFO/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{@HWVERSION}"/>
-
- <xsl:variable name="ipClassification_">
- <xsl:call-template name="F_ModClass_To_IpClassification">
- <xsl:with-param name="iModClass" select="@MODCLASS"/>
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
-
- <xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
- <xsl:variable name="b_bstd_" select="@BUSSTD"/>
- <xsl:variable name="b_on_focused_bus_" select="count($G_ROOT/SAV/BUS[(@INSTANCE = $b_bus_)])"/>
- <xsl:variable name="b_of_focused_bstd_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_bstd_])"/>
- <xsl:variable name="bif_col_">
- <xsl:choose>
- <xsl:when test="(not($b_bus_ ='__NOC__') and ($b_on_focused_bus_ = 0) and ($b_of_focused_bstd_ > 0))"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <xsl:if test="(($b_on_focused_bus_ + $b_of_focused_bstd_) > 0)">
- <xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
- <xsl:with-param name="iModRef" select="../.."/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- <xsl:with-param name="iBifCol" select="$bif_col_"/>
- </xsl:call-template>
- </xsl:if>
- <xsl:if test="$G_ROOT/SAV/@MODE = 'FLAT'">
- <xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
- <xsl:with-param name="iModRef" select="../.."/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- <xsl:with-param name="iBifCol" select="$bif_col_"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:if>
- </xsl:for-each>
- </xsl:element>
- </xsl:when>
-
- <!-- FLAT VIEW -->
- <xsl:otherwise>
- <xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
- <xsl:variable name="b_on_focused_bus_" select="count($G_ROOT/SAV/BUS[(@INSTANCE = $b_bus_)])"/>
- <xsl:if test="($b_on_focused_bus_ > 0)">
- <xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
- <xsl:with-param name="iModRef" select="../.."/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- </xsl:call-template>
- </xsl:if>
- <xsl:if test="$G_ROOT/SAV/@MODE = 'FLAT'">
- <xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
- <xsl:with-param name="iModRef" select="../.."/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:if>
- </xsl:for-each>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:if>
-
-</xsl:template>
-
-<!--
- ===================================================
- THE MODULE TEMPLATE FOR CONNECTED MODULES
- IN BIF VIEW PROC FOCUS
- ===================================================
--->
-
-<xsl:template match="MODULE" mode="_bif_view_focusing_on_connected">
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>EXAMINING CONNECTED MODULE <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
-
- <xsl:variable name="m_instance_" select="@INSTANCE"/>
- <xsl:variable name="m_class_" select="@MODCLASS"/>
-
- <xsl:variable name="bif_scope_">
- <xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:variable name="b_std_" select="@BUSSTD"/>
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
- <xsl:variable name="b_name_" select="@NAME"/>
-
- <xsl:choose>
- <xsl:when test="($b_bus_ = '__NOC__')"><POTENTIAL/></xsl:when>
-
- <xsl:when test="((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and (count(key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]) > 0)">
-
- <xsl:variable name="p2p_scope_">
- <xsl:for-each select="$G_SYS_MODS">
- <xsl:for-each select="key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]">
- <xsl:variable name="b_instance_" select="../../@INSTANCE"/>
- <xsl:variable name="b_modclass_" select="../../@MODCLASS"/>
- <xsl:variable name="b_bifname_" select="@NAME"/>
- <xsl:if test="not(($b_bifname_ = $b_name_) and ($b_instance_ = $m_instance_))">
- <xsl:variable name="num_mast_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_])"/>
- <xsl:variable name="num_peri_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $b_instance_)])"/>
- <xsl:if test="(($num_mast_connections_ + $num_peri_connections_) > 0)"><INSCOPE/></xsl:if>
- <xsl:if test="(($num_mast_connections_ + $num_peri_connections_) = 0) and not($m_class_ = 'MEMORY') and not($m_class_ = 'MEMORY_CNTLR')"><UNFOCUSED/></xsl:if>
- </xsl:if>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:variable>
- <xsl:variable name="num_p2p_inscope_" select="count(exsl:node-set($p2p_scope_)/INSCOPE)"/>
- <xsl:variable name="num_p2p_unfocused_" select="count(exsl:node-set($p2p_scope_)/UNFOCUSED)"/>
- <xsl:if test="$num_p2p_inscope_ > 0"><CONNECTED/></xsl:if>
- <xsl:if test="$num_p2p_unfocused_ > 0"><UNFOCUSED/></xsl:if>
- </xsl:when>
-
- <!--
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> P2P <xsl:value-of select="$b_instance_"/> == <xsl:value-of select="$num_peri_connections_"/> UNFOCUSED</xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> P2P <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/> = <xsl:value-of select="$num_p2p_unfocused_"/> UNFOCUSED</xsl:message></xsl:if>
- -->
-
- <xsl:when test="((@TYPE = 'SLAVE') and not(MASTERS/MASTER)) or (@TYPE = 'MASTER')">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><CONNECTED/></xsl:if>
- <xsl:if test="($b_bus_ = '__NOC__') and count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) > 0"><POTENTIAL/></xsl:if>
- </xsl:when>
-
- <xsl:when test="(MASTERS/MASTER)">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><POTENTIAL/></xsl:if>
- <xsl:for-each select="MASTERS/MASTER">
- <xsl:variable name="m_inst_" select="@INSTANCE"/>
- <xsl:choose>
- <xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $m_inst_)]) > 0"><CONNECTED/></xsl:when>
- <xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_inst_)]) > 0"><CONNECTED/></xsl:when>
- <xsl:otherwise><UNFOCUSED/></xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:when>
- </xsl:choose>
- </xsl:for-each>
-
- <xsl:if test="$m_class_ = 'BUS'">
- <xsl:variable name="num_bifs_on_bus_" select="count(key('G_MAP_ALL_BIFS_BY_BUS',$m_instance_))"/>
- <!-- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>BBBBBB <xsl:value-of select="$m_instance_"/> has <xsl:value-of select="$num_bifs_on_bus_"/> bifs </xsl:message></xsl:if> -->
- <xsl:for-each select="key('G_MAP_ALL_BIFS_BY_BUS',$m_instance_)">
- <xsl:variable name="b_name_" select="@NAME"/>
- <xsl:variable name="b_type_" select="@TYPE"/>
- <xsl:variable name="b_inst_" select="../../@INSTANCE"/>
- <xsl:variable name="b_icls_" select="../../@MODCLASS"/>
- <xsl:variable name="is_mast_in_focus_" select="count($G_ROOT/SAV/MASTER[(@INSTANCE = $b_inst_)])"/>
- <xsl:variable name="is_peri_in_focus_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[@NAME = $b_inst_])"/>
- <xsl:if test="(($is_peri_in_focus_ + $is_mast_in_focus_) = 0)"><UNFOCUSED/></xsl:if>
- </xsl:for-each>
- </xsl:if>
- </xsl:variable>
-
- <xsl:variable name="mod_id_" select="@INSTANCE"/>
- <xsl:variable name="potential_masts_id_" select="concat('__GROUP_MASTER__.',@INSTANCE)"/>
- <xsl:variable name="is_master_" select="count($G_GROUPS/BLOCK[(@ID = $potential_masts_id_)])"/>
- <xsl:variable name="is_focused_on_" select="count($G_ROOT/SAV/MASTER[(@INSTANCE = $mod_id_)])"/>
- <xsl:variable name="is_peripheral_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[@NAME = $mod_id_])"/>
- <xsl:variable name="num_potential_bifs_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
- <xsl:variable name="num_connected_bifs_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
- <xsl:variable name="num_unfocused_bifs_" select="count(exsl:node-set($bif_scope_)/UNFOCUSED)"/>
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> CONNECTED BIFS <xsl:value-of select="$num_connected_bifs_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> POTENTIAL BIFS <xsl:value-of select="$num_potential_bifs_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> IS PERIPHERAL <xsl:value-of select="$is_peripheral_"/></xsl:message></xsl:if>
- <xsl:if test="((@MODCLASS = 'BUS') or ($num_connected_bifs_ + $is_focused_on_ + $num_potential_bifs_ + $is_peripheral_) > 0)">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PLACING MODULE <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
-
- <xsl:choose>
- <xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="@INSTANCE"/></xsl:attribute>
- <xsl:attribute name="CLASS">MODULE</xsl:attribute>
-
- <xsl:choose>
- <xsl:when test="((@MODCLASS = 'BUS') or (($num_connected_bifs_ + $is_peripheral_ + $is_focused_on_) > 0))">
- <xsl:attribute name="CONNECTED_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="POTENTIAL_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
-
-
- <xsl:choose>
- <xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $mod_id_)]) > 0">
- <xsl:attribute name="RGB_BG"><xsl:value-of select="$COL_FOCUSED_MASTER"/></xsl:attribute>
- </xsl:when>
- <xsl:when test="$num_unfocused_bifs_ > 0">
- <xsl:attribute name="RGB_FG"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:attribute>
- </xsl:when>
- </xsl:choose>
- <!--
- CR452579
- Can only modify INSTANCE name in Hierarchal view.
- -->
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{@INSTANCE}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{@MODTYPE}" VIEWICON="{LICENSEINFO/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{@HWVERSION}"/>
-
- <xsl:variable name="ipClassification_">
- <xsl:call-template name="F_ModClass_To_IpClassification">
- <xsl:with-param name="iModClass" select="@MODCLASS"/>
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
- </xsl:variable>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
-
- <xsl:apply-templates select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_connected"/>
- </xsl:element>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:apply-templates select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_connected"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:if>
-</xsl:template>
-
-
-<!--
- ===================================================
- THE MODULE TEMPLATE FOR POTENTIAL MODULES
- IN BIF VIEW PROC FOCUS
- ===================================================
--->
-
-<xsl:template match="MODULE" mode="_bif_view_focusing_on_potentials">
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>EXAMINING POTENTIAL MODULE <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
-
- <xsl:variable name="m_instance_" select="@INSTANCE"/>
- <xsl:variable name="m_modclass_" select="@MODCLASS"/>
-
- <xsl:variable name="bif_scope_">
- <xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:variable name="b_std_" select="@BUSSTD"/>
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
- <xsl:choose>
-
- <xsl:when test="($b_bus_ = '__NOC__')"><POTENTIAL/></xsl:when>
-
- <xsl:when test="((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and (count(key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]) > 0)">
- <xsl:variable name="p2p_scope_">
- <xsl:for-each select="$G_SYS_MODS"> <!-- To set the right scope for the keys -->
- <xsl:for-each select="key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]">
- <xsl:variable name="b_instance_" select="../../@INSTANCE"/>
- <xsl:variable name="b_modclass_" select="../../@MODCLASS"/>
- <xsl:variable name="num_mast_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_])"/>
- <xsl:variable name="num_peri_connections_">
- <xsl:choose>
- <xsl:when test="((($m_modclass_ = 'PROCESSOR') and ($b_modclass_ = 'PROCESSOR')) or not($b_modclass_ = 'PROCESSOR'))">
- <xsl:value-of select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $b_instance_)])"/>
- </xsl:when>
- <xsl:otherwise>0</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="(($num_mast_connections_ + $num_peri_connections_) > 0)"><INSCOPE/></xsl:if>
- <xsl:if test="(($num_mast_connections_ + $num_peri_connections_) = 0) and not($m_modclass_ = 'MEMORY') and not($m_modclass_ = 'MEMORY_CNTLR')"><UNFOCUSED/></xsl:if>
- </xsl:for-each>
- </xsl:for-each>
- </xsl:variable>
- <xsl:variable name="num_p2p_inscope_" select="count(exsl:node-set($p2p_scope_)/INSCOPE)"/>
- <xsl:variable name="num_p2p_unfocused_" select="count(exsl:node-set($p2p_scope_)/UNFOCUSED)"/>
- <xsl:if test="$num_p2p_inscope_ > 0"><CONNECTED/></xsl:if>
- <xsl:if test="$num_p2p_unfocused_ > 0"><UNFOCUSED/></xsl:if>
- </xsl:when>
-
- <xsl:when test="(@TYPE = 'SLAVE') and not(MASTERS/MASTER)">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><CONNECTED/></xsl:if>
- <xsl:if test="($b_bus_ = '__NOC__') and count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) > 0"><POTENTIAL/></xsl:if>
- </xsl:when>
-
- <xsl:when test="(MASTERS/MASTER)">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><POTENTIAL/></xsl:if>
- <xsl:for-each select="MASTERS/MASTER">
- <xsl:variable name="m_inst_" select="@INSTANCE"/>
- <xsl:choose>
- <xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $m_inst_)]) > 0"><CONNECTED/></xsl:when>
- <xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_inst_)]) > 0"><CONNECTED/></xsl:when>
- <xsl:otherwise><UNFOCUSED/></xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:when>
- </xsl:choose>
- </xsl:for-each>
-
- <xsl:if test="$m_modclass_ = 'BUS'">
- <xsl:variable name="num_bifs_on_bus_" select="count(key('G_MAP_ALL_BIFS_BY_BUS',$m_instance_))"/>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>BUS <xsl:value-of select="$m_instance_"/> has <xsl:value-of select="$num_bifs_on_bus_"/> bifs </xsl:message></xsl:if>
- <xsl:for-each select="key('G_MAP_ALL_BIFS_BY_BUS',$m_instance_)">
- <xsl:variable name="b_name_" select="@NAME"/>
- <xsl:variable name="b_type_" select="@TYPE"/>
- <xsl:variable name="b_inst_" select="../../@INSTANCE"/>
- <xsl:variable name="b_icls_" select="../../@MODCLASS"/>
- <xsl:variable name="is_mast_in_focus_" select="count($G_ROOT/SAV/MASTER[(@INSTANCE = $b_inst_)])"/>
- <xsl:variable name="is_peri_in_focus_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[@NAME = $b_inst_])"/>
- <xsl:if test="(($is_peri_in_focus_ + $is_mast_in_focus_) = 0)"><UNFOCUSED/></xsl:if>
- </xsl:for-each>
- </xsl:if>
- </xsl:variable>
-
- <xsl:variable name="mod_id_" select="@INSTANCE"/>
- <xsl:variable name="potential_masts_id_" select="concat('__GROUP_MASTER__.',@INSTANCE)"/>
- <xsl:variable name="is_master_" select="count($G_GROUPS/BLOCK[(@ID = $potential_masts_id_)])"/>
- <xsl:variable name="is_peripheral_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[@NAME = $mod_id_])"/>
- <xsl:variable name="num_potential_bifs_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
- <xsl:variable name="num_connected_bifs_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
- <xsl:variable name="num_unfocused_bifs_" select="count(exsl:node-set($bif_scope_)/UNFOCUSED)"/>
-<!--
--->
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$num_connected_bifs_"/> connected BIFS</xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$num_potential_bifs_"/> potential bifs </xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$num_unfocused_bifs_"/> unfocused bifs </xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$is_peripheral_"/> is a peripheral</xsl:message></xsl:if>
-
- <xsl:if test="(($num_connected_bifs_ + $num_potential_bifs_ + $is_peripheral_) > 0)">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING POTENTIAL MODULE <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
- <xsl:choose>
-
- <xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="@INSTANCE"/></xsl:attribute>
- <xsl:attribute name="CLASS">MODULE</xsl:attribute>
- <xsl:choose>
- <xsl:when test="(($is_peripheral_ > 0) or ($num_connected_bifs_ > 0))">
- <xsl:attribute name="CONNECTED_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
- </xsl:when>
- <xsl:otherwise>
- <xsl:attribute name="POTENTIAL_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
- </xsl:otherwise>
- </xsl:choose>
-
- <xsl:choose>
- <xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $mod_id_)]) > 0">
- <xsl:attribute name="RGB_BG"><xsl:value-of select="$COL_FOCUSED_MASTER"/></xsl:attribute>
- </xsl:when>
- <xsl:when test="$num_unfocused_bifs_ > 0">
- <xsl:attribute name="RGB_FG"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:attribute>
- </xsl:when>
- </xsl:choose>
-
- <!-- CR452579 Can only modify INSTANCE name in Hierarchal view. -->
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{@INSTANCE}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{@MODTYPE}" VIEWICON="{LICENSEINFO/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{@HWVERSION}"/>
-
- <xsl:variable name="ipClassification_">
- <xsl:call-template name="F_ModClass_To_IpClassification">
- <xsl:with-param name="iModClass" select="@MODCLASS"/>
- <xsl:with-param name="iBusStd" select="@BUSSTD"/>
- </xsl:call-template>
- </xsl:variable>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
-
- <xsl:apply-templates select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_potentials"/>
- </xsl:element>
- </xsl:when>
-
- <xsl:otherwise>
- <xsl:apply-templates select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_potentials"/>
- </xsl:otherwise>
- </xsl:choose>
- </xsl:if>
-</xsl:template>
-
-<!--
- +++++++++++++++++++++++++++++++++++++++++++++++++++++
- BUS INTERFACE TEMPLATES
- +++++++++++++++++++++++++++++++++++++++++++++++++++++
--->
-
-<!--
- ===================================================
- THE BIF TEMPLATE FOR CONNECTED MODULES
- IN BIF VIEW PROC FOCUS
- ===================================================
--->
-<xsl:template match="BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_connected">
- <xsl:variable name="m_instance_" select="../../@INSTANCE"/>
- <xsl:variable name="b_std_" select="@BUSSTD"/>
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
- <xsl:variable name="b_name_" select="@NAME"/>
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> EXAMINING CONNECTED INTERFACE <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
-
- <xsl:variable name="bif_scope_">
- <xsl:choose>
- <xsl:when test="($b_bus_ = '__NOC__')"><POTENTIAL/></xsl:when>
- <xsl:when test="((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and (count(key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]) > 0)">
- <xsl:variable name="p2p_scope_">
- <xsl:for-each select="$G_SYS_MODS"> <!-- to put in right scope for key below -->
- <xsl:for-each select="key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]">
- <xsl:variable name="p2p_bifname_" select="@NAME"/>
- <xsl:variable name="p2p_instance_" select="../../@INSTANCE"/>
-
- <xsl:variable name="num_proc_connections_" select="count(key('G_MAP_PROCESSORS',$p2p_instance_))"/>
- <xsl:variable name="num_mast_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_])"/>
- <xsl:variable name="num_peri_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $p2p_instance_)])"/>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$p2p_instance_"/>.<xsl:value-of select="$p2p_bifname_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PROC CONNECTIONS <xsl:value-of select="$num_proc_connections_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> MAST CONNECTIONS <xsl:value-of select="$num_mast_connections_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PERI CONNECTIONS <xsl:value-of select="$num_peri_connections_"/></xsl:message></xsl:if>
-
- <xsl:if test="($num_mast_connections_ = 0) and ($num_proc_connections_ > 0)"><OUTSCOPE/></xsl:if>
- <xsl:if test="($num_mast_connections_ > 0) or ($num_peri_connections_ > 0)"><INSCOPE/></xsl:if>
-
- </xsl:for-each>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:variable name="num_p2p_inscope_" select="count(exsl:node-set($p2p_scope_)/INSCOPE)"/>
- <xsl:variable name="num_p2p_outscope_" select="count(exsl:node-set($p2p_scope_)/OUTSCOPE)"/>
-
- <xsl:if test="(($num_p2p_inscope_ > 0) and ($num_p2p_outscope_ = 0))"><CONNECTED/></xsl:if>
- </xsl:when>
- <xsl:when test="(@TYPE = 'MASTER')">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><CONNECTED/></xsl:if>
- </xsl:when>
- <xsl:when test="(@TYPE = 'SLAVE') and not(MASTERS/MASTER)">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><CONNECTED/></xsl:if>
- <xsl:if test="($b_bus_ = '__NOC__') and count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) > 0"><POTENTIAL/></xsl:if>
- </xsl:when>
- <xsl:when test="(MASTERS/MASTER)">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><POTENTIAL/></xsl:if>
- <xsl:for-each select="MASTERS/MASTER">
- <xsl:variable name="m_inst_" select="@INSTANCE"/>
- <xsl:choose>
- <xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $m_inst_)]) > 0"><CONNECTED/></xsl:when>
- <xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_inst_)]) > 0"><CONNECTED/></xsl:when>
- <xsl:otherwise><UNFOCUSED/></xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="num_scope_unfocuseds_" select="count(exsl:node-set($bif_scope_)/UNFOCUSED)"/>
- <xsl:variable name="num_scope_potentials_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
- <xsl:variable name="num_scope_connecteds_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> CONNECTED SCOPE <xsl:value-of select="$num_scope_connecteds_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> POTENTIAL SCOPE <xsl:value-of select="$num_scope_potentials_"/></xsl:message></xsl:if>
-
- <xsl:variable name="include_bif_">
- <xsl:choose>
- <xsl:when test="($b_bus_ = '__NOC__')">TRUE</xsl:when>
- <xsl:when test="(((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and ($num_scope_connecteds_ > 0))">TRUE</xsl:when>
- <xsl:when test="((@TYPE = 'MASTER') or (@TYPE = 'SLAVE') or (@TYPE = 'MASTER_SLAVE')) and (($num_scope_potentials_ > 0) or ($num_scope_connecteds_ > 0))">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="($include_bif_ = 'TRUE')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PLACING CONNECTED INTERFACE <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
-
- <xsl:variable name="bif_col_">
- <xsl:choose>
- <xsl:when test="($num_scope_unfocuseds_ > 0)"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
- <xsl:with-param name="iModRef" select="../.."/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- <xsl:with-param name="iBifCol" select="$bif_col_"/>
- </xsl:call-template>
- </xsl:if>
-
- <xsl:if test="$G_ROOT/SAV/@MODE = 'FLAT'">
- <xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
- <xsl:with-param name="iModRef" select="../.."/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- <xsl:with-param name="iBifCol" select="$bif_col_"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:if>
-</xsl:template>
-
-<!--
- ===================================================
- THE BIF TEMPLATE FOR POTENTIAL MODULES
- IN BIF VIEW PROC FOCUS
- ===================================================
--->
-
-<xsl:template match="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_potentials">
- <xsl:variable name="m_instance_" select="../../@INSTANCE"/>
- <xsl:variable name="b_name_" select="@NAME"/>
- <xsl:variable name="b_std_" select="@BUSSTD"/>
- <xsl:variable name="b_bus_" select="@BUSNAME"/>
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> EXAMINING POTENTIAL INTERFACE <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
-
- <xsl:variable name="bif_scope_">
- <xsl:choose>
- <xsl:when test="($b_bus_ = '__NOC__')"><POTENTIAL/></xsl:when>
-
- <xsl:when test="((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and (count(key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]) > 0)">
- <xsl:variable name="p2p_scope_">
- <xsl:for-each select="$G_SYS_MODS">
- <xsl:for-each select="key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]">
- <xsl:variable name="b_instance_" select="../../@INSTANCE"/>
-
- <xsl:variable name="num_proc_connections_" select="count(key('G_MAP_PROCESSORS',$b_instance_))"/>
- <xsl:variable name="num_mast_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_])"/>
- <xsl:variable name="num_peri_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $b_instance_)])"/>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PROC CONNECTIONS <xsl:value-of select="$num_proc_connections_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> MAST CONNECTIONS <xsl:value-of select="$num_mast_connections_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PERI CONNECTIONS <xsl:value-of select="$num_peri_connections_"/></xsl:message></xsl:if>
-
- <xsl:if test="($num_mast_connections_ = 0) and ($num_proc_connections_ > 0)"><OUTSCOPE/></xsl:if>
- <xsl:if test="($num_mast_connections_ > 0) or ($num_peri_connections_ > 0)"><INSCOPE/></xsl:if>
-
- </xsl:for-each>
- </xsl:for-each>
- </xsl:variable>
-
- <xsl:variable name="num_p2p_inscope_" select="count(exsl:node-set($p2p_scope_)/INSCOPE)"/>
- <xsl:variable name="num_p2p_outscope_" select="count(exsl:node-set($p2p_scope_)/OUTSCOPE)"/>
-
- <xsl:if test="(($num_p2p_inscope_ > 0) and ($num_p2p_outscope_ = 0))"><CONNECTED/></xsl:if>
- </xsl:when>
- <xsl:when test="(((@TYPE = 'SLAVE') and not(MASTERS/MASTER)) or (@TYPE = 'MASTER'))">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><CONNECTED/></xsl:if>
- <xsl:if test="($b_bus_ = '__NOC__') and count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) > 0"><POTENTIAL/></xsl:if>
- </xsl:when>
- <xsl:when test="(MASTERS/MASTER)">
- <xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) > 0"><POTENTIAL/></xsl:if>
- <xsl:for-each select="MASTERS/MASTER">
- <xsl:variable name="m_inst_" select="@INSTANCE"/>
- <xsl:choose>
- <xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $m_inst_)]) > 0"><CONNECTED/></xsl:when>
- <xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_inst_)]) > 0"><CONNECTED/></xsl:when>
- <xsl:otherwise><UNFOCUSED/></xsl:otherwise>
- </xsl:choose>
- </xsl:for-each>
- </xsl:when>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="num_scope_potentials_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
- <xsl:variable name="num_scope_connecteds_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
- <xsl:variable name="num_scope_unfocuseds_" select="count(exsl:node-set($bif_scope_)/UNFOCUSED)"/>
-
- <xsl:variable name="include_bif_">
- <xsl:choose>
- <xsl:when test="($b_bus_ = '__NOC__')">TRUE</xsl:when>
- <xsl:when test="(((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and ($num_scope_connecteds_ > 0))">TRUE</xsl:when>
- <xsl:when test="((@TYPE = 'MASTER') or (@TYPE = 'SLAVE') or (@TYPE = 'MASTER_SLAVE')) and (($num_scope_potentials_ > 0) or ($num_scope_connecteds_ > 0))">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="bif_col_">
- <xsl:choose>
- <xsl:when test="($num_scope_unfocuseds_ > 0)"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="($include_bif_ = 'TRUE')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PLACING POTENTIAL INTERFACE <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
- <xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'">
- <xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
- <xsl:with-param name="iModRef" select="../.."/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- <xsl:with-param name="iBifCol" select="$bif_col_"/>
- </xsl:call-template>
- </xsl:if>
- <xsl:if test="$G_ROOT/SAV/@MODE = 'FLAT'">
- <xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
- <xsl:with-param name="iModRef" select="../.."/>
- <xsl:with-param name="iBifRef" select="self::node()"/>
- <xsl:with-param name="iBifCol" select="$bif_col_"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:if>
-
-</xsl:template>
-
-<!-- THINGS TO IGNORE -->
-<!-- Ignore all non valid bus interfaces -->
-<xsl:template match="MODULE/DESCRIPTION" mode="_bif_view_focusing_on_potentials">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/PARAMETERS" mode="_bif_view_focusing_on_potentials">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/DOCUMENTATION" mode="_bif_view_focusing_on_potentials">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/LICENSEINFO" mode="_bif_view_focusing_on_potentials">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<!-- Ignore all non valid bus interfaces -->
-<xsl:template match="BUSINTERFACES/BUSINTERFACE[(@IS_VALID = 'FALSE')]" mode="_bif_view_focusing_on_potentials">
-</xsl:template>
-
-<xsl:template match="MODULE/DESCRIPTION" mode="_bif_view_focusing_on_connected">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/PARAMETERS" mode="_bif_view_focusing_on_connected">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/DOCUMENTATION" mode="_bif_view_focusing_on_connected">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/LICENSEINFO" mode="_bif_view_focusing_on_connected">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="BUSINTERFACES/BUSINTERFACE[(@IS_VALID = 'FALSE')]" mode="_bif_view_focusing_on_connected">
-</xsl:template>
-
-<!-- Ignore all non valid bus interfaces -->
-<xsl:template match="SAV" mode="_port_view_focusing_on_selected">
-</xsl:template>
-
-<xsl:template match="MODULE/DESCRIPTION" mode="_port_view_focusing_on_selected">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/PARAMETERS" mode="_port_view_focusing_on_selected">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/DOCUMENTATION" mode="_port_view_focusing_on_selected">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<xsl:template match="MODULE/LICENSEINFO" mode="_port_view_focusing_on_selected">
-<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
-</xsl:template>
-
-<!-- Ignore all non valid bus interfaces -->
-<xsl:template match="BUSINTERFACES/BUSINTERFACE[(@IS_VALID = 'FALSE')]" mode="_port_view_focusing_on_selected">
-</xsl:template>
-
-<!--
- Only write bus interfaces that are valid for non point to point interfaces
- that have busstds the processor can see
--->
-
-<!--
- ===============================================
- GROUP VIEW TRANSFORMS
- ===============================================
--->
-
-<xsl:template name="WRITE_VIEW_GROUPS">
- <xsl:param name="iModules"/>
-
- <xsl:if test="$G_DEBUG='TRUE'">
- <!--
- <xsl:message>BLKD AREA = <xsl:value-of select="$blkd_full_w_"/> X <xsl:value-of select="$blkd_full_h_"/></xsl:message>
- <xsl:message>NUMOF BUSSTD COLORS = <xsl:value-of select="$COL_BUSSTDS_NUMOF"/></xsl:message>
- <xsl:message>NUMOF INTERFACE TYPES= <xsl:value-of select="$G_IFTYPES_NUMOF"/></xsl:message>
- <xsl:message>NUMOF DIRS = <xsl:value-of select="$G_BLKD_COMPASS_DIRS_NUMOF"/></xsl:message>
- <xsl:apply-templates select="$G_BLOCKS/node()" mode="_place_module_blocks_"/>
- -->
- </xsl:if>
-
- <xsl:element name="SET">
- <xsl:attribute name="CLASS">PROJECT</xsl:attribute>
- <xsl:attribute name="VIEW_ID">BUSINTERFACE</xsl:attribute>
- <xsl:attribute name="DISPLAYMODE">TREE</xsl:attribute>
- <xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:with-param name="iModules" select="$G_BLOCKS"/>
- </xsl:call-template>
- </xsl:element>
-</xsl:template>
-<xsl:template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:param name="iModules"/>
-
- <xsl:for-each select="$iModules/BLOCK[@ID and not(BLOCK) and not(@C)]">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING BUS <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-
- <xsl:variable name="m_id_" select="@ID"/>
- <xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
- <xsl:variable name="m_instance_" select="$m_module_/@INSTANCE"/>
- <xsl:variable name="m_version_" select="$m_module_/@HWVERSION"/>
- <xsl:variable name="m_type_" select="$m_module_/@MODTYPE"/>
- <xsl:variable name="m_class_" select="$m_module_/@MODCLASS"/>
- <xsl:variable name="m_busstd_" select="$m_module_/@BUSSTD"/>
-
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="@ID"/></xsl:attribute>
- <xsl:attribute name="CLASS">MODULE</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Name</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">TEXTBOX</xsl:attribute>
- <xsl:attribute name="NAME">INSTANCE</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$m_instance_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Type</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">MODTYPE</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$m_type_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Version</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">HWVERSION</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$m_version_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Classification</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">IPCLASS</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$m_busstd_"/> BUS</xsl:attribute>
- </xsl:element>
- </xsl:element>
- </xsl:for-each>
-
- <xsl:for-each select="$iModules/BLOCK[@ID and BLOCK]">
- <xsl:choose>
- <xsl:when test="not(starts-with(@ID,'__')) and BLOCK[@C] and (not(BLOCK/BLOCK) or BLOCK/BLOCK[@CP])">
- <!--
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING MODULE <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- -->
- <xsl:variable name="m_id_" select="@ID"/>
- <xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
- <xsl:variable name="m_instance_" select="$m_module_/@INSTANCE"/>
- <xsl:variable name="m_type_" select="$m_module_/@MODTYPE"/>
- <xsl:variable name="m_class_" select="$m_module_/@MODCLASS"/>
- <xsl:variable name="m_version_" select="$m_module_/@HWVERSION"/>
-
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="@ID"/></xsl:attribute>
- <xsl:attribute name="CLASS">MODULE</xsl:attribute>
-
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Name</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">TEXTBOX</xsl:attribute>
- <xsl:attribute name="NAME">INSTANCE</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$m_instance_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Type</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">MODTYPE</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$m_type_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Version</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">HWVERSION</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$m_version_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">IP Classification</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">IPCLASS</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$m_class_"/></xsl:attribute>
- </xsl:element>
-
- <xsl:for-each select="BLOCK[@C and @ID]">
- <xsl:variable name="b_bus_" select="@C"/>
- <xsl:variable name="b_name_" select="@ID"/>
- <xsl:variable name="b_if_" select="$m_module_/BUSINTERFACES/BUSINTERFACE[(@NAME = $b_name_)]"/>
- <xsl:variable name="b_type_" select="$b_if_/@TYPE"/>
- <xsl:variable name="b_busstd_" select="$b_if_/@BUSSTD"/>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING BIF <xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> TYPE <xsl:value-of select="$b_type_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> BUS <xsl:value-of select="$b_bus_"/></xsl:message></xsl:if>
-
- <xsl:variable name="b_busNameViewType_">
- <xsl:choose>
- <xsl:when test="$b_type_ = 'INITIATOR'">TEXTBOX</xsl:when>
- <xsl:when test="starts-with(@ID,'S_AXI')">BUTTON</xsl:when>
- <xsl:when test="starts-with(@ID,'S0_AXI')">BUTTON</xsl:when>
- <xsl:when test="starts-with(@ID,'S1_AXI')">BUTTON</xsl:when>
- <xsl:otherwise>DROPDOWN</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <xsl:variable name="b_busName_">
- <xsl:choose>
- <xsl:when test="$b_if_/MASTERS/MASTER">
- <xsl:variable name="mastersList_"><xsl:for-each select="$b_if_/MASTERS/MASTER"><xsl:if test="position() > 1"> & </xsl:if><xsl:value-of select="concat(@INSTANCE,'.',@BUSINTERFACE)"/></xsl:for-each></xsl:variable>
- <xsl:variable name="mastersConn_" select="concat($b_bus_,':',$mastersList_)"/>
- <xsl:value-of select="$mastersConn_"/>
- </xsl:when>
- <xsl:otherwise><xsl:value-of select="$b_bus_"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> VIEWTYPE <xsl:value-of select="$b_busNameViewType_"/></xsl:message></xsl:if>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message> BUSNAME <xsl:value-of select="$b_busName_"/></xsl:message></xsl:if>
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="@ID"/></xsl:attribute>
- <xsl:attribute name="CLASS">BUSINTERFACE</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">NAME</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$b_name_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
- <xsl:attribute name="VIEWTYPE"><xsl:value-of select="$b_busNameViewType_"/></xsl:attribute>
- <xsl:attribute name="NAME">BUSNAME</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$b_busName_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Type</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">TYPE</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$b_type_"/></xsl:attribute>
- </xsl:element>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">BUSSTD</xsl:attribute>
- <xsl:attribute name="VALUE"><xsl:value-of select="$b_busstd_"/></xsl:attribute>
- </xsl:element>
- </xsl:element>
- </xsl:for-each>
- </xsl:element>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_PROCESSOR__')">
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PROCESSOR GROUP<xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:variable name="p_id_" select="substring-after(@ID,'__GROUP_PROCESSOR__')"/>
- <xsl:variable name="m_id_" select="concat('PROCESSOR',$p_id_)"/>
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
- <xsl:attribute name="CLASS">GROUP</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">INSTANCE</xsl:attribute>
- <xsl:attribute name="VALUE">Subsystem of <xsl:value-of select="$p_id_"/></xsl:attribute>
- </xsl:element>
- <xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:element>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_MASTER__')">
-
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>MASTER GROUP<xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:variable name="p_id_" select="substring-after(@ID,'__GROUP_MASTER__')"/>
- <xsl:variable name="m_id_" select="concat('MASTER',$p_id_)"/>
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
- <xsl:attribute name="CLASS">GROUP</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">INSTANCE</xsl:attribute>
- <xsl:attribute name="VALUE">Subsystem of <xsl:value-of select="$p_id_"/></xsl:attribute>
- </xsl:element>
- <xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:element>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_SHARED__')">
- <xsl:variable name="s_id_" select="substring-after(@ID,'__GROUP_SHARED__')"/>
- <xsl:variable name="m_id_" select="concat('SHARED',$s_id_)"/>
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING SHARED PERIPHERALS <xsl:value-of select="$s_id_"/></xsl:message></xsl:if>
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
- <xsl:attribute name="CLASS">GROUP</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">INSTANCE</xsl:attribute>
- <xsl:attribute name="VALUE">Peripherals shared by <xsl:value-of select="$s_id_"/></xsl:attribute>
- </xsl:element>
- <xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:element>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_MEMORY__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING MEMORY <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:variable name="m_id_" select="substring-after(@ID,'__GROUP_MEMORY__')"/>
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
- <xsl:attribute name="CLASS">GROUP</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">INSTANCE</xsl:attribute>
- <xsl:attribute name="VALUE">(Memory) <xsl:value-of select="$m_id_"/></xsl:attribute>
- </xsl:element>
- <xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:element>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_PERIPHERAL__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING PERIPHERAL <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-
- <xsl:when test="starts-with(@ID,'__GROUP_SLAVES__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING SLAVES <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:when>
-<!--
- <xsl:when test="starts-with(@ID,'__GROUP_SLAVES__')">
- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING SLAVES GOUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
- <xsl:variable name="m_id_" select="substring-after(@ID,'__GROUP_SLAVES__')"/>
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
- <xsl:attribute name="CLASS">GROUP</xsl:attribute>
- <xsl:element name="VARIABLE">
- <xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- <xsl:attribute name="NAME">INSTANCE</xsl:attribute>
- <xsl:attribute name="VALUE">(Slaves of) <xsl:value-of select="$m_id_"/></xsl:attribute>
- </xsl:element>
- <xsl:call-template name="F_Write_XTeller_MODULES">
- <xsl:with-param name="iModules" select="self::node()"/>
- </xsl:call-template>
- </xsl:element>
- </xsl:when>
--->
-
- </xsl:choose>
- </xsl:for-each>
-</xsl:template>
-
-
-
-</xsl:stylesheet>
-
+++ /dev/null
-<?xml version="1.0" standalone="no"?>
-
-<!DOCTYPE stylesheet [
- <!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
- <!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
-
- <!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
- <!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
-
- <!ENTITY ALPHALOWER "ABCDEFxX0123456789">
- <!ENTITY HEXUPPER "ABCDEFxX0123456789">
- <!ENTITY HEXLOWER "abcdefxX0123456789">
- <!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
-]>
-
-<xsl:stylesheet version="1.0"
- xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
- xmlns:exsl="http://exslt.org/common"
- xmlns:dyn="http://exslt.org/dynamic"
- xmlns:math="http://exslt.org/math"
- xmlns:xlink="http://www.w3.org/1999/xlink"
- extension-element-prefixes="math dyn exsl xlink">
-
-<!--
- ================================================================================
- Generate XTeller for PORTS
- ================================================================================
--->
-<xsl:param name="SHOW_IOIF" select="'TRUE'"/>
-<xsl:param name="SHOW_BUSIF" select="'TRUE'"/>
-
-<xsl:template name="WRITE_VIEW_PORT_TREE">
-
- <xsl:variable name="num_of_ext_ports_" select="count($G_SYS_EXPS/PORT)"/>
-
- <xsl:if test="$G_DEBUG='TRUE'">
- <xsl:message>WRITING PORT in MODE :<xsl:value-of select="@MODE"/></xsl:message>
- <!--
- <xsl:message>EXTERNAL PORT <xsl:value-of select="$num_of_ext_ports_"/></xsl:message>
- -->
- </xsl:if>
-
-
- <xsl:if test="$num_of_ext_ports_ > 0">
- <xsl:call-template name="WRITE_VIEW_EXTP_TREE_SET"/>
- </xsl:if>
-
- <xsl:for-each select="$G_SYS_MODS/MODULE">
- <xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
- <xsl:variable name= "instName_" select="@INSTANCE"/>
- <xsl:variable name="moduleRef_" select="self::node()"/>
-
- <xsl:call-template name="WRITE_VIEW_PORT_TREE_SET">
- <xsl:with-param name="iModRef" select="$moduleRef_"/>
- </xsl:call-template>
-
- </xsl:for-each> <!-- End of MODULES loop -->
-</xsl:template>
-
-<xsl:template name="WRITE_VIEW_EXTP_TREE_SET">
-
- <xsl:element name="SET">
- <xsl:attribute name="ID">ExternalPorts</xsl:attribute>
- <xsl:attribute name="CLASS">MODULE</xsl:attribute>
-
- <xsl:for-each select="$G_SYS_EXPS">
-
- <xsl:element name="VARIABLE">
- <xsl:attribute name="NAME">Name</xsl:attribute>
- <xsl:attribute name="VALUE">External Ports</xsl:attribute>
- <xsl:attribute name="VIEWDISP">Name</xsl:attribute>
- <xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
- </xsl:element>
-
- <xsl:for-each select="PORT">
- <xsl:sort select="@NAME" order="ascending"/>
- <!--
- <xsl:sort data-type="number" select="@MHS_INDEX" order="ascending"/>
- -->
-
- <xsl:element name="SET">
- <xsl:attribute name="ID"><xsl:value-of select="@NAME"/></xsl:attribute>
- <xsl:attribute name="CLASS">PORT</xsl:attribute>
- <xsl:attribute name="ROW_INDEX"><xsl:value-of select="(position() - 1)"/></xsl:attribute>
-
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{@SIGNAME}" IS_EDITABLE="TRUE"/>
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="NAME" VALUE="{@NAME}"/>
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Direction" NAME="DIR" VALUE="{@DIR}"/>
-
- <xsl:if test="(@SIGIS)">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Class" NAME="SIGIS" VALUE="{@SIGIS}"/>
- </xsl:if>
- <xsl:if test="not(@SIGIS)">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Class" NAME="SIGIS" VALUE="NONE"/>
- </xsl:if>
-
- <xsl:choose>
- <xsl:when test="@LEFT and @RIGHT">
- <xsl:variable name="vecformula_txt_">[<xsl:value-of select="@LEFT"/>:<xsl:value-of select="@RIGHT"/>]</xsl:variable>
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$vecformula_txt_}"/>
- </xsl:when>
- <xsl:when test="@MSB and @LSB">
- <xsl:variable name="vecformula_txt_">[<xsl:value-of select="@MSB"/>:<xsl:value-of select="@LSB"/>]</xsl:variable>
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$vecformula_txt_}"/>
- </xsl:when>
- <xsl:when test="(not(@MSB) and not(@LSB) and not(@SIGIS = 'CLK') and not(@SIGIS = 'CLOCK') and not(@SIGIS = 'DCMCLK') and not(@SIGIS = 'RST') and not(@SIGIS = 'RESET'))">
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE=""/>
- </xsl:when>
- </xsl:choose>
-
- <xsl:if test="((@SIGIS = 'CLK') or (@SIGIS = 'CLOCK') or (@SIGIS = 'DCMCLK'))">
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Frequency(Hz)" NAME="CLKFREQUENCY" VALUE="{@CLKFREQUENCY}"/>
- </xsl:if>
-
- <xsl:if test="(@SIGIS = 'RST' or @SIGIS = 'RESET')">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Reset Polarity" NAME="RSTPOLARITY" VALUE="{@RSTPOLARITY}"/>
- </xsl:if>
-
- <xsl:if test="(@SIGIS = 'INTERRUPT')">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
- </xsl:if>
- </xsl:element>
- </xsl:for-each> <!-- End of EXTERNAL PORTS loop -->
- </xsl:for-each> <!-- End of EXTERNAL PORTS loop -->
- </xsl:element> <!-- End of EXTERNAL PORTS SET -->
-</xsl:template>
-
-<xsl:template name="WRITE_VIEW_PORT_TREE_SET">
- <xsl:param name="iModRef" select="'__NONE__'"/>
-
- <xsl:variable name="m_inst_" select="$iModRef/@INSTANCE"/>
- <xsl:variable name="m_class_" select="$iModRef/@MODCLASS"/>
- <xsl:variable name="m_type_" select="$iModRef/@MODTYPE"/>
- <xsl:variable name="m_type_lc_" select="translate($m_type_,&UPPER2LOWER;)"/>
- <xsl:variable name="m_version_" select="$iModRef/@HWVERSION"/>
- <xsl:variable name="m_licinfo_" select="$iModRef/LICENSEINFO"/>
- <xsl:variable name="m_ports_" select="$iModRef/PORTS"/>
-
- <xsl:variable name="is_axi_interconnect_">
- <xsl:choose>
- <xsl:when test="$m_type_ = 'axi_interconnect'">TRUE</xsl:when>
- <xsl:when test="$m_type_lc_ = 'axi_interconnect'">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:for-each select="$G_SYS_MODS"> <!-- To put things in the right scope for the keys below -->
-
- <xsl:variable name="m_iofs_all_" select="key('G_MAP_ALL_IOFS', $m_inst_)"/>
- <xsl:variable name="m_bifs_all_" select="key('G_MAP_ALL_BIFS', $m_inst_)"/>
-
- <xsl:variable name="m_ports_def_" select="key('G_MAP_DEF_PORTS',$m_inst_)"/>
- <xsl:variable name="m_ports_ndf_" select="key('G_MAP_NDF_PORTS',$m_inst_)"/>
-<!--
- <xsl:if test="$G_DEBUG = 'TRUE'">
- <xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_bifs_all_)"/> valid bifs </xsl:message>
- <xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_iofs_all_)"/> valid iofs </xsl:message>
- <xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_ports_def_)"/> default ports </xsl:message>
- <xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_ports_ndf_)"/> non default ports </xsl:message>
- <xsl:message></xsl:message>
- </xsl:if>
--->
-
- <SET ID="{$m_inst_}" CLASS="MODULE">
- <!-- CR452579
- Can only modify INSTANCE name in Hierarchal view.
- -->
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{$m_inst_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$m_type_}" VIEWICON="{$m_licinfo_/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$m_version_}"/>
-
- <!--
- CR582477,
- (among others) special case of axi_interconnect_aclk which is a member of
- a bus interface, but should be treated as a non interface port, (i.e. appear even
- if the bus interfaces its a member of is invalid.
- -->
- <xsl:if test="($is_axi_interconnect_ = 'TRUE')">
- <!-- do it this way so we also catch the lower-upper case mismatches -->
- <xsl:for-each select="key('G_MAP_ALL_PORTS',$m_inst_)[contains(@SIGIS,'CLK')]">
- <xsl:variable name="uc_portName_" select="translate(@NAME,&LOWER2UPPER;)"/>
- <xsl:if test="($uc_portName_= 'INTERCONNECT_ACLK')">
- <!--
- <xsl:message><xsl:value-of select="$m_inst_"/>.<xsl:value-of select="@NAME"/> = <xsl:value-of select="@SIGIS"/></xsl:message>
- -->
- <xsl:variable name="portName_" select="@NAME"/>
- <xsl:variable name="portDir_" select="@DIR"/>
- <xsl:variable name="portSig_" select="@SIGNAME"/>
-
- <xsl:variable name="portSigIs_">
- <xsl:choose>
- <xsl:when test="not(@SIGIS)">__NONE__</xsl:when>
- <xsl:otherwise><xsl:value-of select="@SIGIS"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="portSensi_">
- <xsl:choose>
- <xsl:when test="(@SENSITIVITY)"><xsl:value-of select="@SENSITIVIITY"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="portVecFormula_">
- <xsl:choose>
- <xsl:when test="@VECFORMULA"><xsl:value-of select="@VECFORMULA"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:call-template name="WRITE_PORT_SET">
- <xsl:with-param name="iName" select="$portName_"/>
- <xsl:with-param name="iDir" select="$portDir_"/>
- <xsl:with-param name="iSigName" select="$portSig_"/>
- <xsl:with-param name="iSigIs" select="$portSigIs_"/>
- <xsl:with-param name="iSensitivity" select="$portSensi_"/>
- <xsl:with-param name="iVecFormula" select="$portVecFormula_"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:for-each>
- </xsl:if>
-
- <!-- PORTS not part of an INTERFACE -->
- <xsl:for-each select="$m_ports_ndf_">
-
- <xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
- <xsl:variable name="uc_portName_" select="translate(@NAME,&LOWER2UPPER;)"/>
-
- <!--
- <xsl:if test="((not(@BUS) and not(@IOS)) or (($is_axi_interconnect_ = 'TRUE') and ($uc_portName_= 'INTERCONNECT_ACLK')))">
- </xsl:if>
- -->
-
-
- <xsl:variable name="portName_" select="@NAME"/>
- <xsl:variable name="portDir_" select="@DIR"/>
- <xsl:variable name="portSig_" select="@SIGNAME"/>
-
- <xsl:variable name="portSigIs_">
- <xsl:choose>
- <xsl:when test="not(@SIGIS)">__NONE__</xsl:when>
- <xsl:otherwise><xsl:value-of select="@SIGIS"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="portSensi_">
- <xsl:choose>
- <xsl:when test="(@SENSITIVITY)"><xsl:value-of select="@SENSITIVIITY"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="portVecFormula_">
- <xsl:choose>
- <xsl:when test="@VECFORMULA"><xsl:value-of select="@VECFORMULA"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
-
- <xsl:call-template name="WRITE_PORT_SET">
- <xsl:with-param name="iName" select="$portName_"/>
- <xsl:with-param name="iDir" select="$portDir_"/>
- <xsl:with-param name="iSigName" select="$portSig_"/>
- <xsl:with-param name="iSigIs" select="$portSigIs_"/>
- <xsl:with-param name="iSensitivity" select="$portSensi_"/>
- <xsl:with-param name="iVecFormula" select="$portVecFormula_"/>
- </xsl:call-template>
- </xsl:for-each> <!-- END of PORTS NOT OF INTERFACE -->
-
- <!-- PORTS part of a BUSINTERFACE -->
- <xsl:if test="$SHOW_BUSIF = 'TRUE'">
- <xsl:for-each select="$m_bifs_all_">
- <xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
-
- <xsl:variable name="bifName_" select="@NAME"/>
- <xsl:variable name="bifRef_" select="self::node()"/>
- <xsl:variable name="portmapsRef_" select="$bifRef_/PORTMAPS"/>
-
- <!--
- <xsl:variable name="bpmsCnt_" select="count($bpmsRef_/PORTMAP)"/>
- <xsl:message><xsl:value-of select="$instName_"/>.<xsl:value-of select="$bifName_"/>.<xsl:value-of select="$bpmsCnt_"/></xsl:message>
- -->
-
- <xsl:variable name="is_external_">
- <xsl:call-template name="F_IS_Interface_External">
- <xsl:with-param name="iInstRef" select="$iModRef"/>
- <xsl:with-param name="iIntfRef" select="$bifRef_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="bif_connection_">
- <xsl:choose>
- <xsl:when test="not(@BUSNAME = '__NOC__')">Connected to BUS <xsl:value-of select="@BUSNAME"/></xsl:when>
- <xsl:when test="($is_external_ = 'TRUE')">Connected to External Ports</xsl:when>
- <xsl:otherwise>Not connected to BUS or External Ports</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <!-- <SET ID="{@NAME}" CLASS="BUSINTERFACE.PORTS"/> -->
- <xsl:element name="SET">
-
- <xsl:attribute name="ID"><xsl:value-of select="@NAME"/></xsl:attribute>
- <xsl:attribute name="CLASS">BUSINTERFACE.PORTS</xsl:attribute>
-
- <xsl:if test="$is_external_ = 'TRUE'">
- <xsl:attribute name="IS_EXTERNAL">TRUE</xsl:attribute>
- </xsl:if>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="NAME" NAME="NAME" VALUE="(BUS_IF) {@NAME}"/>
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="BUSINTERFACE.CONNECTION" VALUE="{$bif_connection_}"/>
-
- <xsl:for-each select="$portmapsRef_/PORTMAP">
-
- <xsl:variable name="portDir_" select="@DIR"/>
- <xsl:variable name="portName_" select="@PHYSICAL"/>
-
- <xsl:if test="$m_ports_def_[(@NAME = $portName_)]"><!-- Only in map if port is valid -->
-
- <!--
- <xsl:if test="(not($portRef_/@IS_VALID) or ($portRef_/@IS_VALID = 'TRUE'))"/>
- <xsl:sort select="@MPD_INDEX" order="ascending"/>
- <xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
- -->
- <xsl:variable name="portRef_" select="$m_ports_def_[(@NAME = $portName_)]"/>
- <xsl:variable name="portSig_" select="$portRef_/@SIGNAME"/>
-
- <xsl:variable name="portSigIs_">
- <xsl:choose>
- <xsl:when test="not($portRef_/@SIGIS)">__NONE__</xsl:when>
- <xsl:otherwise><xsl:value-of select="$portRef_/@SIGIS"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="portSensi_">
- <xsl:choose>
- <xsl:when test="($portRef_/@SENSITIVITY)"><xsl:value-of select="$portRef_/@SENSITIVITY"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="portVecFormula_">
- <xsl:choose>
- <xsl:when test="$portRef_/@VECFORMULA"><xsl:value-of select="$portRef_/@VECFORMULA"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:call-template name="WRITE_PORT_SET">
- <xsl:with-param name="iName" select="$portName_"/>
- <xsl:with-param name="iDir" select="$portDir_"/>
- <xsl:with-param name="iSigName" select="$portSig_"/>
- <xsl:with-param name="iSigIs" select="$portSigIs_"/>
- <xsl:with-param name="iSensitivity" select="$portSensi_"/>
- <xsl:with-param name="iVecFormula" select="$portVecFormula_"/>
- </xsl:call-template>
- </xsl:if>
- </xsl:for-each> <!-- END BIF PORTMAPS LOOP -->
- </xsl:element>
- </xsl:for-each> <!-- END BIFS LOOP -->
- </xsl:if> <!-- END IF SHOW_BUSIFS -->
-
-
- <!-- PORTS part of a IOINTERFACE -->
- <xsl:if test="$SHOW_IOIF = 'TRUE'">
-
- <xsl:for-each select="$m_iofs_all_[PORTMAPS/PORTMAP]">
- <xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
-
- <xsl:variable name="iifName_" select="@NAME"/>
- <xsl:variable name="iifRef_" select="self::node()"/>
- <xsl:variable name="portmapsRef_" select="$iifRef_/PORTMAPS"/>
-
- <xsl:variable name="is_external_">
- <xsl:call-template name="F_IS_Interface_External">
- <xsl:with-param name="iInstRef" select="$iModRef"/>
- <xsl:with-param name="iIntfRef" select="$iifRef_"/>
- </xsl:call-template>
- </xsl:variable>
-
- <xsl:variable name="iif_connection_">
- <xsl:choose>
- <xsl:when test="($is_external_ ='TRUE')">Connected to External Ports</xsl:when>
- <xsl:otherwise>Not connected to External Ports</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:element name="SET">
-
- <xsl:attribute name="ID"><xsl:value-of select="@NAME"/></xsl:attribute>
- <xsl:attribute name="CLASS">IOINTERFACE.PORTS</xsl:attribute>
-
- <xsl:if test="$is_external_ = 'TRUE'">
- <xsl:attribute name="IS_EXTERNAL">TRUE</xsl:attribute>
- </xsl:if>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="NAME" NAME="NAME" VALUE="(IO_IF) {@NAME}"/>
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="IOINTERFACE.CONNECTION" VALUE="{$iif_connection_}"/>
-
- <xsl:for-each select="$portmapsRef_/PORTMAP">
-
- <xsl:variable name="portName_" select="@PHYSICAL"/>
- <xsl:variable name="portDir_" select="@DIR"/>
-
- <!--
- <xsl:variable name="port_is_valid_">
- <xsl:choose>
- <xsl:when test="$portRef_/@IS_VALID = 'FALSE'">FALSE</xsl:when>
- <xsl:otherwise>TRUE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
- <xsl:message><xsl:value-of select="$portName_"/> : <xsl:value-of select="$port_is_valid_"/> : <xsl:value-of select="$portRef_/@IS_VALID"/></xsl:message>
- -->
-
- <xsl:if test="$m_ports_def_[(@NAME = $portName_)]"> <!-- Only in map if port is valid -->
- <!--
- <xsl:message><xsl:value-of select="$portName_"/> </xsl:message>
- -->
-
- <xsl:variable name="portRef_" select="$m_ports_def_[(@NAME = $portName_)]"/>
- <xsl:variable name="portSig_" select="$portRef_/@SIGNAME"/>
-
- <xsl:variable name="portSigIs_">
- <xsl:choose>
- <xsl:when test="not($portRef_/@SIGIS)">__NONE__</xsl:when>
- <xsl:otherwise><xsl:value-of select="$portRef_/@SIGIS"/></xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="portSensi_">
- <xsl:choose>
- <xsl:when test="($portRef_/@SENSITIVITY)"><xsl:value-of select="$portRef_/@SENSITIVITY"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:variable name="portVecFormula_">
- <xsl:choose>
- <xsl:when test="$portRef_/@VECFORMULA"><xsl:value-of select="$portRef_/@VECFORMULA"/></xsl:when>
- <xsl:otherwise>__NONE__</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:call-template name="WRITE_PORT_SET">
- <xsl:with-param name="iName" select="$portName_"/>
- <xsl:with-param name="iDir" select="$portDir_"/>
- <xsl:with-param name="iSigName" select="$portSig_"/>
- <xsl:with-param name="iSigIs" select="$portSigIs_"/>
- <xsl:with-param name="iSensitivity" select="$portSensi_"/>
- <xsl:with-param name="iVecFormula" select="$portVecFormula_"/>
- </xsl:call-template>
- </xsl:if> <!-- End of port is valid check -->
- </xsl:for-each> <!-- END IO INTERFACE PORTMAPS LOOP -->
- </xsl:element>
- </xsl:for-each> <!-- END IIFS LOOP -->
- </xsl:if> <!-- END IF SHOW_IOIFS -->
- </SET>
-
- </xsl:for-each> <!-- End of the scoping for key functions-->
-</xsl:template>
-
-<xsl:template name="WRITE_VIEW_PORT_FLAT">
-
- <xsl:if test="$G_DEBUG='TRUE'">
- <xsl:message>WRITING PORT MODE <xsl:value-of select="@MODE"/></xsl:message>
- </xsl:if>
-
- <xsl:variable name="num_of_ext_ports_" select="count($G_SYS_EXPS/PORT)"/>
- <xsl:if test="$num_of_ext_ports_ > 0">
- <xsl:call-template name="WRITE_VIEW_EXTP_FLAT_SET"/>
- </xsl:if>
-
-
- <xsl:for-each select="$G_SYS_MODS/MODULE">
- <xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
- <xsl:variable name="instName_" select="@INSTANCE"/>
- <xsl:variable name="moduleRef_" select="self::node()"/>
-
- <xsl:call-template name="WRITE_VIEW_PORT_FLAT_SET">
- <xsl:with-param name="iModRef" select="$moduleRef_"/>
- </xsl:call-template>
-
- </xsl:for-each> <!-- End of Modules Loop -->
-</xsl:template>
-
-<xsl:template name="WRITE_VIEW_EXTP_FLAT_SET">
-
- <xsl:for-each select="$G_SYS_EXPS">
- <xsl:for-each select="PORT[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
- <xsl:sort data-type="number" select="@MHS_INDEX" order="ascending"/>
- <xsl:variable name="ext_is_interrupt_">
- <xsl:if test="@SIGIS = 'INTERRUPT'">TRUE</xsl:if>
- <xsl:if test="not(@SIGIS = 'INTERRUPT')">FALSE</xsl:if>
- </xsl:variable>
-
- <SET ID="{@NAME}" CLASS="PORT">
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="External Ports"/>
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Port Name" NAME="NAME" VALUE="{@NAME}"/>
-
- <xsl:choose>
- <xsl:when test="@LEFT and @RIGHT">
- <xsl:variable name="vecformula_txt_">[<xsl:value-of select="@LEFT"/>:<xsl:value-of select="@RIGHT"/>]</xsl:variable>
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$vecformula_txt_}"/>
- </xsl:when>
- <xsl:when test="@MSB and @LSB">
- <xsl:variable name="vecformula_txt_">[<xsl:value-of select="@MSB"/>:<xsl:value-of select="@LSB"/>]</xsl:variable>
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$vecformula_txt_}"/>
- </xsl:when>
- <xsl:when test="(not(@MSB) and not(@LSB) and not(@SIGIS = 'CLK') and not(@SIGIS = 'CLOCK') and not(@SIGIS = 'DCMCLK') and not(@SIGIS = 'RST') and not(@SIGIS = 'RESET'))">
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE=""/>
- </xsl:when>
- </xsl:choose>
-
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{@SIGNAME}" IS_EDITABLE="TRUE"/>
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Direction" NAME="DIR" VALUE="{@DIR}"/>
-
- <xsl:if test="(@SIGIS)">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Class" NAME="SIGIS" VALUE="{@SIGIS}"/>
- </xsl:if>
- <xsl:if test="not(@SIGIS)">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Class" NAME="SIGIS" VALUE="NONE"/>
- </xsl:if>
-
- <xsl:if test="(@SIGIS = 'RST' or @SIGIS = 'RESET')">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Reset Polarity" NAME="RSTPOLARITY" VALUE="{@RSTPOLARITY}"/>
- </xsl:if>
- <xsl:if test="((@SIGIS = 'CLK') or (@SIGIS = 'CLOCK') or (@SIGIS = 'DCMCLK'))">
- <VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Frequency(Hz)" NAME="CLKFREQUENCY" VALUE="{@CLKFREQUENCY}"/>
- </xsl:if>
-
- <!-- SENSITIVITY Settings on Interrupt ports -->
- <xsl:choose>
- <xsl:when test="((@SIGNAME = '__NOC__') and ($ext_is_interrupt_ = 'TRUE') and not(@SENSITIVITY))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE=""/>
- </xsl:when>
- <xsl:when test="((@SIGNAME = '__NOC__') and ($ext_is_interrupt_ = 'TRUE') and (@SENSITIVITY))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
- </xsl:when>
-
- <xsl:when test="((@SIGNAME = '__DEF__') and ($ext_is_interrupt_ = 'TRUE') and not(@SENSITIVITY))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE=""/>
- </xsl:when>
- <xsl:when test="((@SIGNAME = '__DEF__') and ($ext_is_interrupt_ = 'TRUE') and (@SENSITIVITY))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
- </xsl:when>
-
- <xsl:when test="(not(@SIGNAME = '__DEF__') and not(@SIGNAME = '__NOC__') and ($ext_is_interrupt_ = 'TRUE') and not(@SENSITIVITY))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE=""/>
- </xsl:when>
-
- <xsl:when test="(not(@SIGNAME = '__DEF__') and not(@SIGNAME = '__NOC__') and ($ext_is_interrupt_ = 'TRUE') and (@SENSITIVITY))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
- </xsl:when>
- </xsl:choose>
- </SET>
- </xsl:for-each>
- </xsl:for-each>
-</xsl:template>
-
-<xsl:template name="WRITE_VIEW_PORT_FLAT_SET">
-
- <xsl:param name="iModRef" select="'__NONE__'"/>
-
- <xsl:variable name="m_inst_" select="$iModRef/@INSTANCE"/>
- <xsl:variable name="m_class_" select="$iModRef/@MODCLASS"/>
- <xsl:variable name="m_type_" select="$iModRef/@MODTYPE"/>
- <xsl:variable name="m_type_lc_" select="translate($m_type_,&UPPER2LOWER;)"/>
- <xsl:variable name="m_version_" select="$iModRef/@HWVERSION"/>
- <xsl:variable name="m_licinfo_" select="$iModRef/LICENSEINFO"/>
-
- <xsl:variable name="is_axi_interconnect_">
- <xsl:choose>
- <xsl:when test="$m_type_ = 'axi_interconnect'">TRUE</xsl:when>
- <xsl:when test="$m_type_lc_ = 'axi_interconnect'">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:for-each select="$G_SYS_MODS"> <!-- To put things in the right scope for the keys below -->
-
- <xsl:variable name="m_bifs_all_" select="key('G_MAP_ALL_BIFS', $m_inst_)"/>
- <xsl:variable name="m_ports_all_" select="key('G_MAP_ALL_PORTS',$m_inst_)"/>
-
- <xsl:if test="$G_DEBUG = 'TRUE'">
- <xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_ports_all_)"/> valid ports </xsl:message>
- </xsl:if>
-
- <xsl:for-each select="$m_ports_all_">
- <xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
- <!-- <xsl:message>PORTNM : <xsl:value-of select="@NAME"/></xsl:message> -->
-
- <xsl:variable name="p_nm_uc_" select="translate(@NAME,&LOWER2UPPER;)"/>
- <xsl:variable name="p_bif_" select="@BUS"/>
-
- <xsl:variable name="port_is_valid_">
- <xsl:choose>
- <xsl:when test="@IS_VALID = 'FALSE'">FALSE</xsl:when>
- <xsl:when test="(($is_axi_interconnect_ = 'TRUE') and ($p_nm_uc_= 'INTERCONNECT_ACLK'))">TRUE</xsl:when>
- <xsl:when test="not(@BUS) or (@BUS and key('G_MAP_ALL_BIFS', $m_inst_)[(@NAME = $p_bif_)])">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:if test="$port_is_valid_ = 'TRUE'">
- <!--
- <xsl:message>PORT <xsl:value-of select="@BUS"/>.<xsl:value-of select="@NAME"/></xsl:message>
- -->
- <SET ID="{@NAME}" CLASS="PORT">
- <!--
- CR452579
- Can only modify INSTANCE name in Hierarchal view.
- -->
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$m_inst_}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$m_type_}" VIEWICON="{$m_licinfo_/@ICON_NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$m_version_}"/>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Port Name" NAME="NAME" VALUE="{@NAME}"/>
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Direction" NAME="DIR" VALUE="{@DIR}"/>
-
- <xsl:if test="@SIGIS">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Class" NAME="SIGIS" VALUE="{@SIGIS}"/>
- </xsl:if>
-
- <xsl:if test="@VECFORMULA">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{@VECFORMULA}"/>
- </xsl:if>
-
- <xsl:if test="@SENSITIVITY">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
- </xsl:if>
-
- <xsl:variable name="is_interrupt">
- <xsl:if test="@SIGIS = 'INTERRUPT'">TRUE</xsl:if>
- <xsl:if test="not(@SIGIS = 'INTERRUPT')">FALSE</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="is_input">
- <xsl:choose>
- <xsl:when test="(@DIR= 'I')">TRUE</xsl:when>
- <xsl:when test="(@DIR= 'IN')">TRUE</xsl:when>
- <xsl:when test="(@DIR= 'INPUT')">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <!-- VECFORMULA Settings if Interrupt settings -->
- <xsl:choose>
-
- <xsl:when test="((@SIGNAME = '__NOC__') and ($is_interrupt = 'TRUE') and ($is_input = 'TRUE') and not(@VECFORMULA))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_INTERRUPT="{$is_interrupt}"/>
- </xsl:when>
-
- <xsl:when test="((@SIGNAME = '__NOC__') and ($is_interrupt = 'TRUE') and ($is_input = 'TRUE') and (@VECFORMULA))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_INTERRUPT="{$is_interrupt}" IS_RANGE="TRUE"/>
- </xsl:when>
-
- <xsl:when test="@SIGNAME = '__NOC__'">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_EDITABLE="TRUE"/>
- </xsl:when>
-
- <xsl:when test="((@SIGNAME = '__DEF__') and ($is_interrupt = 'TRUE') and ($is_input = 'TRUE') and not(@VECFORMULA))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection" IS_INTERRUPT="{$is_interrupt}"/>
- </xsl:when>
- <xsl:when test="((@SIGNAME = '__DEF__') and ($is_interrupt = 'TRUE') and ($is_input = 'TRUE') and (@VECFORMULA))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection" IS_INTERRUPT="{$is_interrupt}" IS_RANGE="TRUE"/>
- </xsl:when>
- <xsl:when test="@SIGNAME = '__DEF__'">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection"/>
- </xsl:when>
-
- <xsl:when test="(not(@SIGNAME = '__DEF__') and not(@SIGNAME = '__NOC__') and ($is_input = 'TRUE') and ($is_interrupt = 'TRUE') and (@VECFORMULA))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{@SIGNAME}" IS_INTERRUPT="{$is_interrupt}" IS_RANGE="TRUE"/>
- </xsl:when>
- <xsl:when test="(not(@SIGNAME = '__DEF__') and not(@SIGNAME = '__NOC__') and ($is_input = 'TRUE') and ($is_interrupt = 'TRUE'))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{@SIGNAME}" IS_INTERRUPT="{$is_interrupt}"/>
- </xsl:when>
-
- <xsl:otherwise>
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{@SIGNAME}" IS_EDITABLE="TRUE"/>
- </xsl:otherwise>
- </xsl:choose>
- </SET>
- </xsl:if> <!-- End of port validity check -->
- </xsl:for-each> <!-- End of Ports Loop -->
- </xsl:for-each>
-</xsl:template>
-
-<xsl:template name="WRITE_PORT_SET">
-
-<xsl:param name="iName" select="'__NONE__'"/>
-<xsl:param name="iDir" select="'__NONE__'"/>
-<xsl:param name="iSigName" select="'__NONE__'"/>
-<xsl:param name="iSigIs" select="'__NONE__'"/>
-<xsl:param name="iVecFormula" select="'__NONE__'"/>
-<xsl:param name="iSensitivity" select="'__NONE__'"/>
-
-<SET ID="{$iName}" CLASS="PORT">
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="NAME" NAME="NAME" VALUE="{$iName}"/>
-
- <xsl:variable name="is_interrupt">
- <xsl:if test="$iSigIs = 'INTERRUPT'">TRUE</xsl:if>
- <xsl:if test="not($iSigIs = 'INTERRUPT')">FALSE</xsl:if>
- </xsl:variable>
-
- <xsl:variable name="is_input">
- <xsl:choose>
- <xsl:when test="($iDir = 'I')">TRUE</xsl:when>
- <xsl:when test="($iDir = 'IN')">TRUE</xsl:when>
- <xsl:when test="($iDir = 'INPUT')">TRUE</xsl:when>
- <xsl:otherwise>FALSE</xsl:otherwise>
- </xsl:choose>
- </xsl:variable>
-
- <xsl:choose>
-
- <xsl:when test="(($iSigName = '__NOC__') and ($is_input = 'TRUE') and ($is_interrupt = 'TRUE') and ($iVecFormula = '__NONE__'))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_INTERRUPT="{$is_interrupt}"/>
- </xsl:when>
- <xsl:when test="(($iSigName = '__NOC__') and ($is_input ='TRUE') and ($is_interrupt = 'TRUE') and not($iVecFormula = '__NONE__'))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_INTERRUPT="{$is_interrupt}" IS_RANGE="TRUE"/>
- </xsl:when>
- <xsl:when test="$iSigName = '__NOC__'">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_EDITABLE="TRUE"/>
- </xsl:when>
-
- <xsl:when test="(($iSigName = '__DEF__') and ($is_input = 'TRUE') and ($is_interrupt = 'TRUE') and ($iVecFormula = '__NONE__'))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection" IS_INTERRUPT="{$is_interrupt}"/>
- </xsl:when>
- <xsl:when test="(($iSigName = '__DEF__') and ($is_input = 'TRUE') and ($is_interrupt = 'TRUE') and not($iVecFormula = '__NONE__'))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection" IS_INTERRUPT="{$is_interrupt}" IS_RANGE="TRUE"/>
- </xsl:when>
-
- <xsl:when test="($iSigName = '__DEF__')">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection"/>
- </xsl:when>
-
- <xsl:when test="(not($iSigName = '__DEF__') and not($iSigName = '__NOC__') and ($is_input ='TRUE') and ($is_interrupt = 'TRUE') and not($iVecFormula = '__NONE__'))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{$iSigName}" IS_INTERRUPT="{$is_interrupt}" IS_RANGE="TRUE"/>
- </xsl:when>
-
- <xsl:when test="(not($iSigName = '__DEF__') and not($iSigName = '__NOC__') and ($is_input ='TRUE') and ($is_interrupt = 'TRUE'))">
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{$iSigName}" IS_INTERRUPT="{$is_interrupt}"/>
- </xsl:when>
-
- <xsl:otherwise>
- <VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{$iSigName}" IS_EDITABLE="TRUE"/>
- </xsl:otherwise>
- </xsl:choose>
-
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Direction" NAME="DIR" VALUE="{$iDir}"/>
-
- <xsl:if test="not($iSigIs = '__NONE__')">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Class" NAME="SIGIS" VALUE="{$iSigIs}"/>
- </xsl:if>
-
- <xsl:if test="not($iVecFormula = '__NONE__')">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$iVecFormula}"/>
- </xsl:if>
-
- <xsl:if test="not($iSensitivity = '__NONE__')">
- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{$iSensitivity}"/>
- </xsl:if>
-</SET>
-</xsl:template>
-
-
-</xsl:stylesheet>
-
-
+++ /dev/null
-
-<SAV MODE="TREE" VIEW="ADDRESS"/>
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>\r
-<!-- IMPORTANT: This is an internal file that has been generated\r
- by the Xilinx ISE software. Any direct editing or\r
- changes made to this file may result in unpredictable\r
- behavior or data corruption. It is strongly advised that\r
- users do not edit the contents of this file. -->\r
-<messages>
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_interconnect</arg>, INSTANCE:<arg fmt="%s" index="2">axi4_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_BASEFAMILY</arg> value to <arg fmt="%s" index="6">spartan6</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 69</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_interconnect</arg>, INSTANCE:<arg fmt="%s" index="2">axi4lite_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_BASEFAMILY</arg> value to <arg fmt="%s" index="6">spartan6</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 69</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_ENDIANNESS</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 183</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_ICACHE_USE_FSL</arg> value to <arg fmt="%s" index="6">0</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 322</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_DCACHE_USE_FSL</arg> value to <arg fmt="%s" index="6">0</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 352</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_SYS_RST_PRESENT</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 228</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="740" delta="old" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_i_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it. \r
-</msg>\r
-
-<msg type="info" file="EDK" num="740" delta="old" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_d_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it. \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_ethernetlite</arg>, INSTANCE: <arg fmt="%s" index="2">Ethernet_Lite</arg> - <arg fmt="%s" index="3">This design requires design constraints to guarantee performance.\r
-Please refer to the data sheet for details. \r
-The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet operation.</arg> - <arg fmt="%s" index="4">C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.mhs line 324</arg>\r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_v10</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_ilmb</arg> - <arg fmt="%s" index="3">tool</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_LMB_NUM_SLAVES</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_a\data\lmb_v10_v2_1_0.mpd line 70</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_v10</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_dlmb</arg> - <arg fmt="%s" index="3">tool</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_LMB_NUM_SLAVES</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_a\data\lmb_v10_v2_1_0.mpd line 70</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">bram_block</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_bram_block</arg> - <arg fmt="%s" index="3">tool</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_MEMSIZE</arg> value to <arg fmt="%s" index="6">0x2000</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 67</arg> \r
-</msg>\r
-
-<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_tdo1</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_tdo1</arg> - No driver found. Port will be driven to <arg fmt="%s" index="3">GND</arg> - <arg fmt="%s" index="4">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 230</arg> \r
-</msg>\r
-
-<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_tdi</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_tdi</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 223</arg> \r
-</msg>\r
-
-<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_reset</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_reset</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 224</arg> \r
-</msg>\r
-
-<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_shift</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_shift</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 225</arg> \r
-</msg>\r
-
-<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_update</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_update</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 226</arg> \r
-</msg>\r
-
-<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_capture</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_capture</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 227</arg> \r
-</msg>\r
-
-<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_sel1</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_sel1</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 228</arg> \r
-</msg>\r
-
-<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_drck1</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_drck1</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 229</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_interconnect</arg>, INSTANCE:<arg fmt="%s" index="2">axi4_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_RANGE_CHECK</arg> value to <arg fmt="%s" index="6">0</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 137</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_interconnect</arg>, INSTANCE:<arg fmt="%s" index="2">axi4lite_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_RANGE_CHECK</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 137</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_D_AXI</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 216</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_ADDR_TAG_BITS</arg> value to <arg fmt="%s" index="6">13</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 320</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_DCACHE_ADDR_TAG</arg> value to <arg fmt="%s" index="6">13</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 350</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_USE_INTERRUPT</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 384</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_USE_EXT_BRK</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 385</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_USE_EXT_NM_BRK</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 386</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_bram_if_cntlr</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_i_bram_ctrl</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_MASK</arg> value to <arg fmt="%s" index="6">0x40000000</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3_00_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 78</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_bram_if_cntlr</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_d_bram_ctrl</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_MASK</arg> value to <arg fmt="%s" index="6">0x40000000</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3_00_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 78</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_MEMCLK_PERIOD</arg> value to <arg fmt="%s" index="6">3333</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 110</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S0_AXI_STRICT_COHERENCY</arg> value to <arg fmt="%s" index="6">0</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 153</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S1_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 165</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S2_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 179</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S3_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 193</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S4_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 207</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S5_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 221</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_NUM_INTR_INPUTS</arg> value to <arg fmt="%s" index="6">4</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 71</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_INTR</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111110111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 72</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_EDGE</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 73</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_LVL</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 74</arg> \r
-</msg>\r
-
-<msg type="info" file="EDK" num="0" delta="new" >The following instances are synthesized with <arg fmt="%s" index="1">XST</arg>. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using <arg fmt="%s" index="2">XST</arg> synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. \r
-</msg>\r
-
-<msg type="info" file="EDK" num="3509" delta="old" >NCF files should not be modified as they will be regenerated.\r
-If any constraint needs to be overridden, this should be done by modifying the data/<arg fmt="%s" index="1">system</arg>.ucf file.\r
-</msg>\r
-
-</messages>
-\r
+++ /dev/null
-<?xml version='1.0' encoding='UTF-8'?>
-<report-views version="2.0" >
- <header>
- <DateModified>2011-07-27T13:20:02</DateModified>
- <ModuleName>system</ModuleName>
- <SummaryTimeStamp>2011-07-27T13:20:02</SummaryTimeStamp>
- <SavedFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport</SavedFilePath>
- <FilterFile>filter.filter</FilterFile>
- <SavedFilterFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise</SavedFilterFilePath>
- <DateInitialized>2011-05-30T21:44:59</DateInitialized>
- <EnableMessageFiltering>false</EnableMessageFiltering>
- </header>
- <body>
- <viewgroup label="Design Overview" >
- <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="implementation\system_summary.html" label="Summary" >
- <toc-item title="Design Overview" target="Design Overview" />
- <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
- <toc-item title="Performance Summary" target="Performance Summary" />
- <toc-item title="Failing Constraints" target="Failing Constraints" />
- <toc-item title="Detailed Reports" target="Detailed Reports" />
- </view>
- <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="implementation\system_envsettings.html" label="System Settings" />
- <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="implementation\system_map.xrpt" label="IOB Properties" />
- <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="implementation\system_map.xrpt" label="Control Set Information" />
- <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="implementation\system_map.xrpt" label="Module Level Utilization" />
- <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="implementation\system.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
- <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="implementation\system_par.xrpt" label="Pinout Report" />
- <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="implementation\system_par.xrpt" label="Clock Report" />
- <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="Timing_Analyzer" file="implementation\system.twx" label="Static Timing" />
- <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="implementation\system_html/fit/report.htm" label="CPLD Fitter Report" />
- <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="implementation\system_html/tim/report.htm" label="CPLD Timing Report" />
- </viewgroup>
- <viewgroup label="XPS Errors and Warnings" >
- <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
- <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
- <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
- <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
- </viewgroup>
- <viewgroup label="XPS Reports" >
- <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
- <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
- <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
- <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
- <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="system.log" label="System Log File" />
- </viewgroup>
- <viewgroup label="Errors and Warnings" >
- <view program="pn" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered, New" file="implementation\_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
- <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="synthesis\_xmsgs/xst.xmsgs" label="Synthesis Messages" />
- <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
- <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/map.xmsgs" label="Map Messages" />
- <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/par.xmsgs" label="Place and Route Messages" />
- <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/trce.xmsgs" label="Timing Messages" />
- <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/xpwr.xmsgs" label="Power Messages" />
- <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
- <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
- <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/*.xmsgs" label="All Implementation Messages" />
- <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="implementation\_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
- </viewgroup>
- <viewgroup label="Detailed Reports" >
- <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.syr" label="Synthesis Report" >
- <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
- <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
- <toc-item title="HDL Compilation" target=" HDL Compilation " />
- <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
- <toc-item title="HDL Analysis" target=" HDL Analysis " />
- <toc-item title="HDL Parsing" target=" HDL Parsing " />
- <toc-item title="HDL Elaboration" target=" HDL Elaboration " />
- <toc-item title="HDL Synthesis" target=" HDL Synthesis " />
- <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
- <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
- <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
- <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
- <toc-item title="Partition Report" target=" Partition Report " />
- <toc-item title="Final Report" target=" Final Report " />
- <toc-item title="Design Summary" target=" Design Summary " />
- <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
- <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
- <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
- <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
- <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
- <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
- <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
- <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
- <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
- </view>
- <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.srr" label="Synplify Report" />
- <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.prec_log" label="Precision Report" />
- <view inputState="Synthesized" program="ngdbuild" type="Report" file="implementation\system.bld" label="Translation Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- <toc-item title="Command Line" target="Command Line:" />
- <toc-item title="Partition Status" target="Partition Implementation Status" />
- <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
- </view>
- <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="implementation\system_map.mrp" label="Map Report" >
- <toc-item title="Top of Report" target="Release" searchDir="Forward" />
- <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
- <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
- <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
- <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
- <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
- <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
- <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
- <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
- <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
- <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
- <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
- <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
- <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
- </view>
- <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="implementation\system.par" label="Place and Route Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- <toc-item title="Device Utilization" target="Device Utilization Summary:" />
- <toc-item title="Router Information" target="Starting Router" />
- <toc-item title="Partition Status" target="Partition Implementation Status" />
- <toc-item title="Clock Report" target="Generating Clock Report" />
- <toc-item title="Timing Results" target="Timing Score:" />
- <toc-item title="Final Summary" target="Peak Memory Usage:" />
- </view>
- <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="implementation\system.twr" label="Post-PAR Static Timing Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- <toc-item title="Timing Report Description" target="Device,package,speed:" />
- <toc-item title="Informational Messages" target="INFO:" />
- <toc-item title="Warning Messages" target="WARNING:" />
- <toc-item title="Timing Constraints" target="Timing constraint:" />
- <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
- <toc-item title="Data Sheet Report" target="Data Sheet report:" />
- <toc-item title="Timing Summary" target="Timing summary:" />
- <toc-item title="Trace Settings" target="Trace Settings:" />
- </view>
- <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.rpt" label="CPLD Fitter Report (Text)" >
- <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
- <toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
- <toc-item title="Pin Resources" target="** Pin Resources **" />
- <toc-item title="Global Resources" target="** Global Control Resources **" />
- </view>
- <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.tim" label="CPLD Timing Report (Text)" >
- <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
- <toc-item title="Performance Summary" target="Performance Summary:" />
- </view>
- <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" hidden="true" type="Report" file="implementation\system.pwr" label="Power Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- <toc-item title="Power summary" target="Power summary" />
- <toc-item title="Thermal summary" target="Thermal summary" />
- </view>
- <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="implementation\system.bgn" label="Bitgen Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
- <toc-item title="Final Summary" target="DRC detected" />
- </view>
- </viewgroup>
- <viewgroup label="Secondary Reports" >
- <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="implementation\isim.log" label="ISIM Simulator Log" />
- <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/synthesis/system_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
- <toc-item title="Top of Report" target="Release" searchDir="Forward" />
- </view>
- <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/translate/system_translate.nlf" label="Post-Translate Simulation Model Report" >
- <toc-item title="Top of Report" target="Release" searchDir="Forward" />
- </view>
- <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
- <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="implementation\system_map.map" label="Map Log File" >
- <toc-item title="Top of Report" target="Release" searchDir="Forward" />
- <toc-item title="Design Information" target="Design Information" />
- <toc-item title="Design Summary" target="Design Summary" />
- </view>
- <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
- <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_preroute.twr" label="Post-Map Static Timing Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- <toc-item title="Timing Report Description" target="Device,package,speed:" />
- <toc-item title="Informational Messages" target="INFO:" />
- <toc-item title="Warning Messages" target="WARNING:" />
- <toc-item title="Timing Constraints" target="Timing constraint:" />
- <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
- <toc-item title="Data Sheet Report" target="Data Sheet report:" />
- <toc-item title="Timing Summary" target="Timing summary:" />
- <toc-item title="Trace Settings" target="Trace Settings:" />
- </view>
- <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/map/system_map.nlf" label="Post-Map Simulation Model Report" />
- <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_map.psr" label="Physical Synthesis Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- </view>
- <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="implementation\system_pad.txt" label="Pad Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- </view>
- <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="implementation\system.unroutes" label="Unroutes Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- </view>
- <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_preroute.tsi" label="Post-Map Constraints Interaction Report" >
- <toc-item title="Top of Report" target="Release" searchDir="Forward" />
- </view>
- <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.grf" label="Guide Results Report" />
- <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.dly" label="Asynchronous Delay Report" />
- <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.clk_rgn" label="Clock Region Report" />
- <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.tsi" label="Post-Place and Route Constraints Interaction Report" >
- <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
- </view>
- <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
- <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/par/system_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
- <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_sta.nlf" label="Primetime Netlist Report" >
- <toc-item title="Top of Report" target="Release" searchDir="Forward" />
- </view>
- <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="implementation\system.ibs" label="IBIS Model" >
- <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
- <toc-item title="Component" target="Component " />
- </view>
- <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.lck" label="Back-annotate Pin Report" >
- <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
- <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
- </view>
- <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.lpc" label="Locked Pin Constraints" >
- <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
- <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
- </view>
- <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Secondary_Report" file="implementation\netgen/fit/system_timesim.nlf" label="Post-Fit Simulation Model Report" />
- <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="implementation\usage_statistics_webtalk.html" label="WebTalk Report" />
- <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\webtalk.log" label="WebTalk Log File" />
- </viewgroup>
- </body>
-</report-views>
+++ /dev/null
-MessageCaptureEnabled: TRUE\r
-MessageFilteringEnabled: FALSE\r
-IncrementalMessagingEnabled: TRUE\r
+++ /dev/null
- -p xc6slx45tfgg484-3 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst
-\r
+++ /dev/null
- -p spartan6 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst -s isim\r
+++ /dev/null
-<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Wed Jul 27 13:20:01 2011">
-
- <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
-
- <EXTERNALPORTS>
- <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
- <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
- <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
- <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
- <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
- <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGNAME="mcbx_dram_clk"/>
- <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGNAME="mcbx_dram_clk_n"/>
- <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
- <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
- <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
- <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
- <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
- <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
- <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
- <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
- <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
- <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
- <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
- <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
- <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
- <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
- <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
- <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
- <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
- <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
- <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
- <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
- <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
- <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
- <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
- <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
- <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
- <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
- </EXTERNALPORTS>
-
- <MODULES>
- <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
- <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="2"/>
- <PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
- <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
- <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff00000000c0000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7ffffff"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000"/>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100"/>
- <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100"/>
- <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111101"/>
- <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5"/>
- <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003"/>
- <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000020"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000002"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004"/>
- <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/>
- <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="axi4_0_S_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi4_0_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="15" MSB="9" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi4_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi4_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi4_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi4_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi4_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi4_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi4_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi4_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="38" MSB="9" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi4_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi4_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi4_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi4_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi4_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi4_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ACLK" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="axi4_0_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="axi4_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="59" MSB="4" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="axi4_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi4_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi4_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi4_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi4_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="axi4_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi4_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi4_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi4_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="axi4_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="84" MSB="4" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="axi4_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi4_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi4_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi4_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi4_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
- <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="7"/>
- <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
- <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
- <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000002000000020000000200000002000000020000000200000002"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000074800000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041c0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040e0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007480ffff"/>
- <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100"/>
- <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000102faf08002faf08002faf08002faf08002faf08002faf08002faf080"/>
- <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000"/>
- <PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"/>
- <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111101111"/>
- <PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
- <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
- <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
- <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/>
- <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
- <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="3" MSB="6" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi4lite_0_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="48" MSB="6" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi4lite_0_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="49" MSB="6" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="50" MSB="223" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="51" MSB="55" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="52" MSB="20" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="53" MSB="13" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="54" MSB="13" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="55" MSB="27" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="56" MSB="20" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="57" MSB="27" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="58" MSB="27" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="59" MSB="6" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="60" MSB="6" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="61" MSB="6" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="62" MSB="6" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="63" MSB="223" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="64" MSB="27" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="65" MSB="6" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="66" MSB="6" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="67" MSB="6" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="68" MSB="6" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="69" MSB="6" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="70" MSB="13" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="71" MSB="6" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="72" MSB="6" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="73" MSB="6" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="74" MSB="6" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="75" MSB="223" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="76" MSB="55" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="77" MSB="20" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="78" MSB="13" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="79" MSB="13" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="80" MSB="27" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="81" MSB="20" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="82" MSB="27" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="83" MSB="27" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="84" MSB="6" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="85" MSB="6" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="86" MSB="6" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="87" MSB="6" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="88" MSB="223" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="89" MSB="13" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="90" MSB="6" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="91" MSB="6" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="92" MSB="6" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="93" MSB="6" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
- <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
- <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
- <PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2"/>
- <PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
- <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
- <PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="41" MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="40" MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="36" MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="37" MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="35" MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="34" MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0"/>
- <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00"/>
- <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="7"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="2"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="2"/>
- <PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="39" MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000"/>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="17"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="16384"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
- <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000"/>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="17"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="16384"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
- <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
- <PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4"/>
- <PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2"/>
- <PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3"/>
- <PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16"/>
- <PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_M_AXI_DP_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_DP_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_DP_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_DP_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_DP_B_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_IC_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_IC_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_IC_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_IC_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_IC_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
- <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"/>
- <PORT BUS="DLMB:ILMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
- <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
- <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:31]"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="IPLB_MRearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="IPLB_MTimeout" SIGNAME="__NOC__"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="86" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="89" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="92" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="95" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="96" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="99" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="100" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="109" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="110" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="111" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="114" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="116" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="118" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="119" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="120" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="121" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="124" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="125" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="126" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="128" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="130" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="131" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="132" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="134" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="135" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="136" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="137" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="139" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="140" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="141" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="142" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="144" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="145" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="147" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="148" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="149" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="150" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="152" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="153" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="154" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="155" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="156" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="158" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RLAST" SIGNAME="axi4lite_0_S_RLAST"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="I" MPD_INDEX="160" NAME="M_AXI_DP_RVALID" SIGNAME="axi4lite_0_S_RVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="O" MPD_INDEX="161" NAME="M_AXI_DP_RREADY" SIGNAME="axi4lite_0_S_RREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="162" NAME="M_AXI_IC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="164" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="165" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="166" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="167" NAME="M_AXI_IC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="168" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="169" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="170" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="171" NAME="M_AXI_IC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="172" NAME="M_AXI_IC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="173" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="175" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="176" NAME="M_AXI_IC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="177" NAME="M_AXI_IC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="178" NAME="M_AXI_IC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="180" NAME="M_AXI_IC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="182" NAME="M_AXI_IC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="183" NAME="M_AXI_IC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="184" NAME="M_AXI_IC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="185" NAME="M_AXI_IC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="187" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="188" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="189" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="190" NAME="M_AXI_IC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="192" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="194" NAME="M_AXI_IC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="195" NAME="M_AXI_IC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="196" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="197" NAME="M_AXI_IC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="198" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="199" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_IC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="202" NAME="M_AXI_IC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="204" NAME="M_AXI_DC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="205" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="206" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="207" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="208" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="209" NAME="M_AXI_DC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="211" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="212" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="213" NAME="M_AXI_DC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="214" NAME="M_AXI_DC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="215" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="216" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="217" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="218" NAME="M_AXI_DC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="219" NAME="M_AXI_DC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="220" NAME="M_AXI_DC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="222" NAME="M_AXI_DC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="224" NAME="M_AXI_DC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="225" NAME="M_AXI_DC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="226" NAME="M_AXI_DC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="227" NAME="M_AXI_DC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="229" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="230" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="231" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="232" NAME="M_AXI_DC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="234" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="236" NAME="M_AXI_DC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="237" NAME="M_AXI_DC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="238" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="239" NAME="M_AXI_DC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="241" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="243" NAME="M_AXI_DC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="244" NAME="M_AXI_DC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="I" MPD_INDEX="246" NAME="DBG_CLK" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="I" MPD_INDEX="247" NAME="DBG_TDI" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="O" MPD_INDEX="248" NAME="DBG_TDO" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="249" MSB="0" NAME="DBG_REG_EN" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="I" MPD_INDEX="250" NAME="DBG_SHIFT" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="I" MPD_INDEX="251" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="I" MPD_INDEX="252" NAME="DBG_UPDATE" SIGNAME="microblaze_0_debug_Dbg_Update"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="I" MPD_INDEX="253" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_debug_Debug_Rst"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="254" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="255" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="256" MSB="0" NAME="Trace_PC" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="257" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="258" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="259" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="260" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="261" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="262" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="263" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="266" MSB="0" NAME="Trace_Data_Address" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="Trace_Data_Access" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="268" NAME="Trace_Data_Read" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="269" NAME="Trace_Data_Write" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="270" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="271" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="272" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="273" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="274" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="275" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="276" NAME="Trace_ICache_Req" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="277" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="278" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="279" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="280" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="281" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="286" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="287" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="288" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="289" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="290" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="291" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="292" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="293" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="294" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="295" NAME="FSL1_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="296" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="297" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="298" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="299" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="300" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="301" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="302" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="303" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="304" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="FSL2_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="306" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="307" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="308" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="309" NAME="FSL2_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="310" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="311" MSB="0" NAME="FSL2_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="FSL2_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="313" NAME="FSL2_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="FSL3_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="FSL3_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="316" MSB="0" NAME="FSL3_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="317" NAME="FSL3_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="318" NAME="FSL3_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="319" NAME="FSL3_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="320" NAME="FSL3_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="321" MSB="0" NAME="FSL3_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="FSL3_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="323" NAME="FSL3_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="324" NAME="FSL4_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="325" NAME="FSL4_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="326" MSB="0" NAME="FSL4_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="327" NAME="FSL4_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="328" NAME="FSL4_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="329" NAME="FSL4_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="330" NAME="FSL4_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="331" MSB="0" NAME="FSL4_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="332" NAME="FSL4_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="333" NAME="FSL4_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="334" NAME="FSL5_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="335" NAME="FSL5_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="336" MSB="0" NAME="FSL5_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="337" NAME="FSL5_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="338" NAME="FSL5_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="339" NAME="FSL5_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="340" NAME="FSL5_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="341" MSB="0" NAME="FSL5_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="342" NAME="FSL5_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="343" NAME="FSL5_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="344" NAME="FSL6_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="345" NAME="FSL6_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="346" MSB="0" NAME="FSL6_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="347" NAME="FSL6_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="348" NAME="FSL6_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="349" NAME="FSL6_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="350" NAME="FSL6_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="351" MSB="0" NAME="FSL6_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="352" NAME="FSL6_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="353" NAME="FSL6_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="354" NAME="FSL7_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="355" NAME="FSL7_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="356" MSB="0" NAME="FSL7_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="357" NAME="FSL7_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="358" NAME="FSL7_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="359" NAME="FSL7_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="360" NAME="FSL7_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="361" MSB="0" NAME="FSL7_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="362" NAME="FSL7_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="363" NAME="FSL7_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="364" NAME="FSL8_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="365" NAME="FSL8_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="366" MSB="0" NAME="FSL8_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="367" NAME="FSL8_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="368" NAME="FSL8_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="369" NAME="FSL8_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="370" NAME="FSL8_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="371" MSB="0" NAME="FSL8_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="372" NAME="FSL8_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="373" NAME="FSL8_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="374" NAME="FSL9_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="375" NAME="FSL9_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="376" MSB="0" NAME="FSL9_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="377" NAME="FSL9_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="378" NAME="FSL9_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="379" NAME="FSL9_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="380" NAME="FSL9_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="381" MSB="0" NAME="FSL9_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="382" NAME="FSL9_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="383" NAME="FSL9_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="384" NAME="FSL10_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="385" NAME="FSL10_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="386" MSB="0" NAME="FSL10_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="387" NAME="FSL10_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="388" NAME="FSL10_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="389" NAME="FSL10_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="390" NAME="FSL10_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="391" MSB="0" NAME="FSL10_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="392" NAME="FSL10_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="393" NAME="FSL10_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="394" NAME="FSL11_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="395" NAME="FSL11_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="396" MSB="0" NAME="FSL11_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="397" NAME="FSL11_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="398" NAME="FSL11_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="399" NAME="FSL11_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="400" NAME="FSL11_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="401" MSB="0" NAME="FSL11_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="402" NAME="FSL11_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="403" NAME="FSL11_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="404" NAME="FSL12_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="405" NAME="FSL12_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="406" MSB="0" NAME="FSL12_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="407" NAME="FSL12_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="408" NAME="FSL12_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="409" NAME="FSL12_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="410" NAME="FSL12_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="411" MSB="0" NAME="FSL12_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="412" NAME="FSL12_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="413" NAME="FSL12_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="414" NAME="FSL13_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="415" NAME="FSL13_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="416" MSB="0" NAME="FSL13_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="417" NAME="FSL13_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="418" NAME="FSL13_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="419" NAME="FSL13_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="420" NAME="FSL13_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="421" MSB="0" NAME="FSL13_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="422" NAME="FSL13_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="423" NAME="FSL13_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="424" NAME="FSL14_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="425" NAME="FSL14_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="426" MSB="0" NAME="FSL14_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="427" NAME="FSL14_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="428" NAME="FSL14_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="429" NAME="FSL14_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="430" NAME="FSL14_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="431" MSB="0" NAME="FSL14_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="432" NAME="FSL14_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="433" NAME="FSL14_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="434" NAME="FSL15_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="435" NAME="FSL15_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="436" MSB="0" NAME="FSL15_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="437" NAME="FSL15_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="438" NAME="FSL15_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="439" NAME="FSL15_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="440" NAME="FSL15_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="441" MSB="0" NAME="FSL15_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="442" NAME="FSL15_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="443" NAME="FSL15_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="444" NAME="M0_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="445" MSB="31" NAME="M0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M0_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="446" NAME="M0_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="447" NAME="M0_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="448" NAME="S0_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="449" MSB="31" NAME="S0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S0_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="450" NAME="S0_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="451" NAME="S0_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="452" NAME="M1_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="453" MSB="31" NAME="M1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M1_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="454" NAME="M1_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="455" NAME="M1_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="456" NAME="S1_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="457" MSB="31" NAME="S1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S1_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="458" NAME="S1_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="459" NAME="S1_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="460" NAME="M2_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="461" MSB="31" NAME="M2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M2_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="462" NAME="M2_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="463" NAME="M2_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="464" NAME="S2_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="465" MSB="31" NAME="S2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S2_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="466" NAME="S2_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="467" NAME="S2_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="468" NAME="M3_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="469" MSB="31" NAME="M3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M3_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="470" NAME="M3_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="471" NAME="M3_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="472" NAME="S3_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="473" MSB="31" NAME="S3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S3_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="474" NAME="S3_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="475" NAME="S3_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="476" NAME="M4_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="477" MSB="31" NAME="M4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M4_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="478" NAME="M4_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="479" NAME="M4_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="480" NAME="S4_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="481" MSB="31" NAME="S4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S4_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="482" NAME="S4_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="483" NAME="S4_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="484" NAME="M5_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="485" MSB="31" NAME="M5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M5_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="486" NAME="M5_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="487" NAME="M5_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="488" NAME="S5_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="489" MSB="31" NAME="S5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S5_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="490" NAME="S5_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="491" NAME="S5_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="492" NAME="M6_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="493" MSB="31" NAME="M6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M6_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="494" NAME="M6_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="495" NAME="M6_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="496" NAME="S6_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="497" MSB="31" NAME="S6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S6_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="498" NAME="S6_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="499" NAME="S6_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="500" NAME="M7_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="501" MSB="31" NAME="M7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M7_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="502" NAME="M7_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="503" NAME="M7_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="504" NAME="S7_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="505" MSB="31" NAME="S7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S7_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="506" NAME="S7_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="507" NAME="S7_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="508" NAME="M8_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="509" MSB="31" NAME="M8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M8_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="510" NAME="M8_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="511" NAME="M8_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="512" NAME="S8_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="513" MSB="31" NAME="S8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S8_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="514" NAME="S8_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="515" NAME="S8_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="516" NAME="M9_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="517" MSB="31" NAME="M9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M9_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="518" NAME="M9_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="519" NAME="M9_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="520" NAME="S9_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="521" MSB="31" NAME="S9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S9_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="522" NAME="S9_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="523" NAME="S9_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="524" NAME="M10_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="525" MSB="31" NAME="M10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M10_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="526" NAME="M10_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="527" NAME="M10_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="528" NAME="S10_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="529" MSB="31" NAME="S10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S10_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="530" NAME="S10_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="531" NAME="S10_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="532" NAME="M11_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="533" MSB="31" NAME="M11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M11_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="534" NAME="M11_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="535" NAME="M11_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="536" NAME="S11_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="537" MSB="31" NAME="S11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S11_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="538" NAME="S11_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="539" NAME="S11_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="540" NAME="M12_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="541" MSB="31" NAME="M12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M12_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="542" NAME="M12_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="543" NAME="M12_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="544" NAME="S12_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="545" MSB="31" NAME="S12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S12_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="546" NAME="S12_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="547" NAME="S12_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="548" NAME="M13_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="549" MSB="31" NAME="M13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M13_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="550" NAME="M13_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="551" NAME="M13_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="552" NAME="S13_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="553" MSB="31" NAME="S13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S13_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="554" NAME="S13_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="555" NAME="S13_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="556" NAME="M14_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="557" MSB="31" NAME="M14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M14_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="558" NAME="M14_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="559" NAME="M14_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="560" NAME="S14_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="561" MSB="31" NAME="S14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S14_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="562" NAME="S14_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="563" NAME="S14_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="564" NAME="M15_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="565" MSB="31" NAME="M15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M15_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="566" NAME="M15_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="567" NAME="M15_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="568" NAME="S15_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="569" MSB="31" NAME="S15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S15_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="570" NAME="S15_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="571" NAME="S15_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="572" NAME="ICACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="573" NAME="ICACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="574" MSB="0" NAME="ICACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="575" NAME="ICACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="576" NAME="ICACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="577" NAME="ICACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="578" NAME="ICACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="579" MSB="0" NAME="ICACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="580" NAME="ICACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="581" NAME="ICACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="582" NAME="DCACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="583" NAME="DCACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="584" MSB="0" NAME="DCACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="585" NAME="DCACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="586" NAME="DCACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="587" NAME="DCACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="588" NAME="DCACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="589" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="590" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="591" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="I" PHYSICAL="RESET"/>
- <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
- <PORTMAP DIR="I" PHYSICAL="DREADY"/>
- <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
- <PORTMAP DIR="I" PHYSICAL="DCE"/>
- <PORTMAP DIR="I" PHYSICAL="DUE"/>
- <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
- <PORTMAP DIR="O" PHYSICAL="D_AS"/>
- <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
- <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
- <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="I" PHYSICAL="RESET"/>
- <PORTMAP DIR="I" PHYSICAL="INSTR"/>
- <PORTMAP DIR="I" PHYSICAL="IREADY"/>
- <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
- <PORTMAP DIR="I" PHYSICAL="ICE"/>
- <PORTMAP DIR="I" PHYSICAL="IUE"/>
- <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
- <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
- <PORTMAP DIR="O" PHYSICAL="I_AS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="2" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
- <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
- <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" INSTANCE="Ethernet_Lite" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="microblaze_0_intc" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" INSTANCE="MCB_DDR3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="134217728" SIZEABRV="128M">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- </MEMORYMAP>
- <PERIPHERALS>
- <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/>
- <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/>
- <PERIPHERAL INSTANCE="debug_module"/>
- <PERIPHERAL INSTANCE="RS232_Uart_1"/>
- <PERIPHERAL INSTANCE="LEDs_4Bits"/>
- <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/>
- <PERIPHERAL INSTANCE="Ethernet_Lite"/>
- <PERIPHERAL INSTANCE="axi_timer_0"/>
- <PERIPHERAL INSTANCE="microblaze_0_intc"/>
- <PERIPHERAL INSTANCE="MCB_DDR3"/>
- </PERIPHERALS>
- <INTERRUPTINFO TYPE="TARGET">
- <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
- <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- </PORTS>
- <BUSINTERFACES/>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
- <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- </PORTS>
- <BUSINTERFACES/>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
- <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x00800000"/>
- <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
- <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SLMB"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
- <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x00800000"/>
- <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
- <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SLMB"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
- <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000"/>
- <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
- <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t"/>
- <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"/>
- <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1"/>
- <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1"/>
- <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
- <PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
- <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
- <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
- <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
- <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
- <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
- <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
- <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="600000000"/>
- <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="600000000"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="100000000"/>
- <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0"/>
- <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="50000000"/>
- <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="PLL0"/>
- <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
- <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
- <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET"/>
- <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
- <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES/>
- </MODULE>
- <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
- <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x74800000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x7480ffff"/>
- <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3"/>
- <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8"/>
- <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
- <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
- <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_debug_Dbg_Update"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_debug_Debug_Rst"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
- <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/>
- <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/>
- <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/>
- <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/>
- <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
- <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
- <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
- <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB"/>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
- <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff"/>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout">
- <DESCRIPTION>Serial Data Out</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin">
- <DESCRIPTION>Serial Data In</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="TX"/>
- <PORTMAP DIR="I" PHYSICAL="RX"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
- <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff"/>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
- <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
- </PORT>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
- <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
- <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff"/>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/>
- <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
- <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
- </PORT>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
- <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
- <DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Spartan-6 memory controller</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="R7"/>
- <PARAMETER MPD_INDEX="3" NAME="C_MCB_PERFORMANCE" TYPE="STRING" VALUE="STANDARD"/>
- <PARAMETER MPD_INDEX="4" NAME="C_BYPASS_CORE_UCF" VALUE="0"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="5" NAME="C_S0_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc0000000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="6" NAME="C_S0_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc7ffffff"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="7" NAME="C_S1_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="8" NAME="C_S1_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="9" NAME="C_S2_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="10" NAME="C_S2_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="11" NAME="C_S3_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="12" NAME="C_S3_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="13" NAME="C_S4_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="14" NAME="C_S4_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="15" NAME="C_S5_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_S5_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="18" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT41J64M16XX-187E"/>
- <PARAMETER MPD_INDEX="19" NAME="C_MEM_BASEPARTNO" TYPE="STRING" VALUE="NOT_SET"/>
- <PARAMETER MPD_INDEX="20" NAME="C_NUM_DQ_PINS" TYPE="INTEGER" VALUE="16"/>
- <PARAMETER MPD_INDEX="21" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="22" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="23" NAME="C_MEM_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/>
- <PARAMETER MPD_INDEX="24" NAME="C_MEM_TRAS" TYPE="INTEGER" VALUE="-1"/>
- <PARAMETER MPD_INDEX="25" NAME="C_MEM_TRCD" TYPE="INTEGER" VALUE="-1"/>
- <PARAMETER MPD_INDEX="26" NAME="C_MEM_TREFI" TYPE="INTEGER" VALUE="-1"/>
- <PARAMETER MPD_INDEX="27" NAME="C_MEM_TRFC" TYPE="INTEGER" VALUE="-1"/>
- <PARAMETER MPD_INDEX="28" NAME="C_MEM_TRP" TYPE="INTEGER" VALUE="-1"/>
- <PARAMETER MPD_INDEX="29" NAME="C_MEM_TWR" TYPE="INTEGER" VALUE="-1"/>
- <PARAMETER MPD_INDEX="30" NAME="C_MEM_TRTP" TYPE="INTEGER" VALUE="-1"/>
- <PARAMETER MPD_INDEX="31" NAME="C_MEM_TWTR" TYPE="INTEGER" VALUE="-1"/>
- <PARAMETER MPD_INDEX="32" NAME="C_PORT_CONFIG" TYPE="STRING" VALUE="B32_B32_B32_B32"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="33" NAME="C_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="34" NAME="C_SKIP_IN_TERM_CAL_VALUE" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER MPD_INDEX="35" NAME="C_MEMCLK_PERIOD" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="36" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="ROW_BANK_COLUMN"/>
- <PARAMETER MPD_INDEX="37" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/>
- <PARAMETER MPD_INDEX="38" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
- <PARAMETER MPD_INDEX="39" NAME="C_SIMULATION" TYPE="STRING" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="40" NAME="C_MEM_DDR1_2_ODS" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="41" NAME="C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
- <PARAMETER MPD_INDEX="42" NAME="C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
- <PARAMETER MPD_INDEX="43" NAME="C_MEM_DDR2_RTT" TYPE="STRING" VALUE="150OHMS"/>
- <PARAMETER MPD_INDEX="44" NAME="C_MEM_DDR2_DIFF_DQS_EN" TYPE="STRING" VALUE="YES"/>
- <PARAMETER MPD_INDEX="45" NAME="C_MEM_DDR2_3_PA_SR" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="46" NAME="C_MEM_DDR2_3_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/>
- <PARAMETER MPD_INDEX="47" NAME="C_MEM_DDR3_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/>
- <PARAMETER MPD_INDEX="48" NAME="C_MEM_DDR3_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
- <PARAMETER MPD_INDEX="49" NAME="C_MEM_DDR3_ODS" TYPE="STRING" VALUE="DIV6"/>
- <PARAMETER MPD_INDEX="50" NAME="C_MEM_DDR3_RTT" TYPE="STRING" VALUE="DIV4"/>
- <PARAMETER MPD_INDEX="51" NAME="C_MEM_DDR3_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/>
- <PARAMETER MPD_INDEX="52" NAME="C_MEM_MOBILE_PA_SR" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="53" NAME="C_MEM_MDDR_ODS" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="54" NAME="C_ARB_ALGORITHM" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="55" NAME="C_ARB_NUM_TIME_SLOTS" TYPE="INTEGER" VALUE="12"/>
- <PARAMETER MPD_INDEX="56" NAME="C_ARB_TIME_SLOT_0" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="57" NAME="C_ARB_TIME_SLOT_1" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="58" NAME="C_ARB_TIME_SLOT_2" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="59" NAME="C_ARB_TIME_SLOT_3" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER MPD_INDEX="60" NAME="C_ARB_TIME_SLOT_4" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="61" NAME="C_ARB_TIME_SLOT_5" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="62" NAME="C_ARB_TIME_SLOT_6" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="63" NAME="C_ARB_TIME_SLOT_7" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER MPD_INDEX="64" NAME="C_ARB_TIME_SLOT_8" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="65" NAME="C_ARB_TIME_SLOT_9" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="66" NAME="C_ARB_TIME_SLOT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="67" NAME="C_ARB_TIME_SLOT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="68" NAME="C_S0_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="69" NAME="C_S0_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="70" NAME="C_S0_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="71" NAME="C_S0_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="72" NAME="C_S0_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="73" NAME="C_S0_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="74" NAME="C_S0_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="75" NAME="C_S0_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="76" NAME="C_S0_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
- <PARAMETER MPD_INDEX="77" NAME="C_S0_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="78" NAME="C_S0_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="79" NAME="C_S0_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="80" NAME="C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="81" NAME="C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="82" NAME="C_S1_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="83" NAME="C_S1_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="84" NAME="C_S1_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="85" NAME="C_S1_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="86" NAME="C_S1_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="87" NAME="C_S1_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="88" NAME="C_S1_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="89" NAME="C_S1_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="90" NAME="C_S1_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
- <PARAMETER MPD_INDEX="91" NAME="C_S1_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="92" NAME="C_S1_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="93" NAME="C_S1_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="94" NAME="C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="95" NAME="C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="96" NAME="C_S2_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="97" NAME="C_S2_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="98" NAME="C_S2_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="99" NAME="C_S2_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="100" NAME="C_S2_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="101" NAME="C_S2_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="102" NAME="C_S2_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="103" NAME="C_S2_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="104" NAME="C_S2_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
- <PARAMETER MPD_INDEX="105" NAME="C_S2_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="106" NAME="C_S2_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="107" NAME="C_S2_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="108" NAME="C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="109" NAME="C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="110" NAME="C_S3_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="111" NAME="C_S3_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="112" NAME="C_S3_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="113" NAME="C_S3_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="114" NAME="C_S3_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="115" NAME="C_S3_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="116" NAME="C_S3_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="117" NAME="C_S3_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="118" NAME="C_S3_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
- <PARAMETER MPD_INDEX="119" NAME="C_S3_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="120" NAME="C_S3_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="121" NAME="C_S3_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="122" NAME="C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="123" NAME="C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="124" NAME="C_S4_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="125" NAME="C_S4_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="126" NAME="C_S4_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="127" NAME="C_S4_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="128" NAME="C_S4_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="129" NAME="C_S4_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="130" NAME="C_S4_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="131" NAME="C_S4_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="132" NAME="C_S4_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
- <PARAMETER MPD_INDEX="133" NAME="C_S4_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="134" NAME="C_S4_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="135" NAME="C_S4_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="136" NAME="C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="137" NAME="C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="138" NAME="C_S5_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="139" NAME="C_S5_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="140" NAME="C_S5_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="141" NAME="C_S5_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="142" NAME="C_S5_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="143" NAME="C_S5_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="144" NAME="C_S5_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="145" NAME="C_S5_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="146" NAME="C_S5_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
- <PARAMETER MPD_INDEX="147" NAME="C_S5_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="148" NAME="C_S5_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="149" NAME="C_S5_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="150" NAME="C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="151" NAME="C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="152" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="153" NAME="C_SYS_RST_PRESENT" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S0_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" NAME="C_INTERCONNECT_S0_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" NAME="C_INTERCONNECT_S0_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" NAME="C_INTERCONNECT_S0_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S0_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S0_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="17" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="18" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="16" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="26" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="9" MPD_INDEX="12" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="10" MPD_INDEX="11" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="27" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="15" LSB="0" MHS_INDEX="12" MPD_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq" VECFORMULA="[C_NUM_DQ_PINS-1:0]"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="13" MPD_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="14" MPD_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="15" MPD_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="16" MPD_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="17" MPD_INDEX="28" NAME="rzq" SIGNAME="rzq"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="18" MPD_INDEX="29" NAME="zio" SIGNAME="zio"/>
- <PORT BUS="S0_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="32" NAME="s0_axi_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="30" NAME="ui_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="0" NAME="sysclk_2x" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
- <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="1" NAME="sysclk_2x_180" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="10" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="4" NAME="PLL_LOCK" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="2" NAME="pll_ce_0" SIGNAME="__NOC__"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="pll_ce_90" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="5" NAME="pll_lock_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="6" NAME="sysclk_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="7" NAME="sysclk_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="8" NAME="pll_ce_0_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="9" NAME="pll_ce_90_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="31" NAME="uo_done_cal" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_aresetn" DIR="I" MPD_INDEX="33" NAME="s0_axi_aresetn" SIGIS="RST" SIGNAME="axi4_0_M_aresetn"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awid" DIR="I" MPD_INDEX="34" NAME="s0_axi_awid" SIGNAME="axi4_0_M_awid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="35" MSB="31" NAME="s0_axi_awaddr" RIGHT="0" SIGNAME="axi4_0_M_awaddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="36" MSB="7" NAME="s0_axi_awlen" RIGHT="0" SIGNAME="axi4_0_M_awlen" VECFORMULA="[7:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="s0_axi_awsize" RIGHT="0" SIGNAME="axi4_0_M_awsize" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="s0_axi_awburst" RIGHT="0" SIGNAME="axi4_0_M_awburst" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlock" DIR="I" MPD_INDEX="39" NAME="s0_axi_awlock" SIGNAME="axi4_0_M_awlock" VECFORMULA="[0:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="40" MSB="3" NAME="s0_axi_awcache" RIGHT="0" SIGNAME="axi4_0_M_awcache" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="s0_axi_awprot" RIGHT="0" SIGNAME="axi4_0_M_awprot" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s0_axi_awqos" RIGHT="0" SIGNAME="axi4_0_M_awqos" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awvalid" DIR="I" MPD_INDEX="43" NAME="s0_axi_awvalid" SIGNAME="axi4_0_M_awvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awready" DIR="O" MPD_INDEX="44" NAME="s0_axi_awready" SIGNAME="axi4_0_M_awready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="s0_axi_wdata" RIGHT="0" SIGNAME="axi4_0_M_wdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s0_axi_wstrb" RIGHT="0" SIGNAME="axi4_0_M_wstrb" VECFORMULA="[((C_S0_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wlast" DIR="I" MPD_INDEX="47" NAME="s0_axi_wlast" SIGNAME="axi4_0_M_wlast"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wvalid" DIR="I" MPD_INDEX="48" NAME="s0_axi_wvalid" SIGNAME="axi4_0_M_wvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wready" DIR="O" MPD_INDEX="49" NAME="s0_axi_wready" SIGNAME="axi4_0_M_wready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bid" DIR="O" MPD_INDEX="50" NAME="s0_axi_bid" SIGNAME="axi4_0_M_bid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="51" MSB="1" NAME="s0_axi_bresp" RIGHT="0" SIGNAME="axi4_0_M_bresp" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bvalid" DIR="O" MPD_INDEX="52" NAME="s0_axi_bvalid" SIGNAME="axi4_0_M_bvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bready" DIR="I" MPD_INDEX="53" NAME="s0_axi_bready" SIGNAME="axi4_0_M_bready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arid" DIR="I" MPD_INDEX="54" NAME="s0_axi_arid" SIGNAME="axi4_0_M_arid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="55" MSB="31" NAME="s0_axi_araddr" RIGHT="0" SIGNAME="axi4_0_M_araddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="56" MSB="7" NAME="s0_axi_arlen" RIGHT="0" SIGNAME="axi4_0_M_arlen" VECFORMULA="[7:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="57" MSB="2" NAME="s0_axi_arsize" RIGHT="0" SIGNAME="axi4_0_M_arsize" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="58" MSB="1" NAME="s0_axi_arburst" RIGHT="0" SIGNAME="axi4_0_M_arburst" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlock" DIR="I" MPD_INDEX="59" NAME="s0_axi_arlock" SIGNAME="axi4_0_M_arlock" VECFORMULA="[0:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="60" MSB="3" NAME="s0_axi_arcache" RIGHT="0" SIGNAME="axi4_0_M_arcache" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="s0_axi_arprot" RIGHT="0" SIGNAME="axi4_0_M_arprot" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="62" MSB="3" NAME="s0_axi_arqos" RIGHT="0" SIGNAME="axi4_0_M_arqos" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arvalid" DIR="I" MPD_INDEX="63" NAME="s0_axi_arvalid" SIGNAME="axi4_0_M_arvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arready" DIR="O" MPD_INDEX="64" NAME="s0_axi_arready" SIGNAME="axi4_0_M_arready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rid" DIR="O" MPD_INDEX="65" NAME="s0_axi_rid" SIGNAME="axi4_0_M_rid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="s0_axi_rdata" RIGHT="0" SIGNAME="axi4_0_M_rdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="67" MSB="1" NAME="s0_axi_rresp" RIGHT="0" SIGNAME="axi4_0_M_rresp" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rlast" DIR="O" MPD_INDEX="68" NAME="s0_axi_rlast" SIGNAME="axi4_0_M_rlast"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rvalid" DIR="O" MPD_INDEX="69" NAME="s0_axi_rvalid" SIGNAME="axi4_0_M_rvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rready" DIR="I" MPD_INDEX="70" NAME="s0_axi_rready" SIGNAME="axi4_0_M_rready"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="71" NAME="s1_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="s1_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="73" MSB="3" NAME="s1_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="74" MSB="31" NAME="s1_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="75" MSB="7" NAME="s1_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="76" MSB="2" NAME="s1_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="s1_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="s1_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="s1_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="80" MSB="2" NAME="s1_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="s1_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="s1_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="83" NAME="s1_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="84" MSB="31" NAME="s1_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="85" MSB="3" NAME="s1_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S1_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="86" NAME="s1_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="s1_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="s1_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="89" MSB="3" NAME="s1_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="90" MSB="1" NAME="s1_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="s1_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="92" NAME="s1_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="s1_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="s1_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="95" MSB="7" NAME="s1_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="96" MSB="2" NAME="s1_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="97" MSB="1" NAME="s1_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="s1_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="s1_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="100" MSB="2" NAME="s1_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="101" MSB="3" NAME="s1_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="s1_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="s1_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="104" MSB="3" NAME="s1_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="105" MSB="31" NAME="s1_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="106" MSB="1" NAME="s1_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="s1_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="s1_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="s1_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="110" NAME="s2_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="111" NAME="s2_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="112" MSB="3" NAME="s2_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="113" MSB="31" NAME="s2_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="s2_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="s2_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="116" MSB="1" NAME="s2_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="117" NAME="s2_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="118" MSB="3" NAME="s2_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="119" MSB="2" NAME="s2_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="120" MSB="3" NAME="s2_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="121" NAME="s2_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="s2_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="123" MSB="31" NAME="s2_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="124" MSB="3" NAME="s2_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S2_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="125" NAME="s2_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="126" NAME="s2_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="s2_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="128" MSB="3" NAME="s2_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="s2_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="130" NAME="s2_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="131" NAME="s2_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="132" MSB="3" NAME="s2_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="133" MSB="31" NAME="s2_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="s2_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="135" MSB="2" NAME="s2_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="136" MSB="1" NAME="s2_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="137" NAME="s2_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="138" MSB="3" NAME="s2_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="139" MSB="2" NAME="s2_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="140" MSB="3" NAME="s2_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="141" NAME="s2_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="s2_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="143" MSB="3" NAME="s2_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="144" MSB="31" NAME="s2_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="145" MSB="1" NAME="s2_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="146" NAME="s2_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="147" NAME="s2_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="148" NAME="s2_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="149" NAME="s3_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="150" NAME="s3_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="s3_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="s3_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="153" MSB="7" NAME="s3_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="154" MSB="2" NAME="s3_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="155" MSB="1" NAME="s3_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="156" NAME="s3_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="157" MSB="3" NAME="s3_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="158" MSB="2" NAME="s3_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="159" MSB="3" NAME="s3_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="160" NAME="s3_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="161" NAME="s3_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="162" MSB="31" NAME="s3_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="163" MSB="3" NAME="s3_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S3_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="164" NAME="s3_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="165" NAME="s3_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="166" NAME="s3_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="167" MSB="3" NAME="s3_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="168" MSB="1" NAME="s3_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="169" NAME="s3_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="170" NAME="s3_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="171" MSB="3" NAME="s3_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="s3_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="173" MSB="7" NAME="s3_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="174" MSB="2" NAME="s3_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="175" MSB="1" NAME="s3_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="176" NAME="s3_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="177" MSB="3" NAME="s3_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="178" MSB="2" NAME="s3_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="179" MSB="3" NAME="s3_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="180" NAME="s3_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="181" NAME="s3_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="182" MSB="3" NAME="s3_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="s3_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="184" MSB="1" NAME="s3_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="185" NAME="s3_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="186" NAME="s3_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="187" NAME="s3_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="188" NAME="s4_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="189" NAME="s4_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="190" MSB="3" NAME="s4_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="s4_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="192" MSB="7" NAME="s4_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="193" MSB="2" NAME="s4_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="194" MSB="1" NAME="s4_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="195" NAME="s4_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="196" MSB="3" NAME="s4_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="197" MSB="2" NAME="s4_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="198" MSB="3" NAME="s4_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="199" NAME="s4_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="200" NAME="s4_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="s4_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="202" MSB="3" NAME="s4_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S4_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="203" NAME="s4_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="204" NAME="s4_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="205" NAME="s4_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="206" MSB="3" NAME="s4_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="207" MSB="1" NAME="s4_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="208" NAME="s4_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="209" NAME="s4_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="s4_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="211" MSB="31" NAME="s4_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="212" MSB="7" NAME="s4_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="213" MSB="2" NAME="s4_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="214" MSB="1" NAME="s4_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="215" NAME="s4_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="216" MSB="3" NAME="s4_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="217" MSB="2" NAME="s4_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="218" MSB="3" NAME="s4_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="219" NAME="s4_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="220" NAME="s4_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="221" MSB="3" NAME="s4_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="222" MSB="31" NAME="s4_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="s4_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="224" NAME="s4_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="225" NAME="s4_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="226" NAME="s4_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="227" NAME="s5_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="228" NAME="s5_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="229" MSB="3" NAME="s5_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="230" MSB="31" NAME="s5_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="231" MSB="7" NAME="s5_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="232" MSB="2" NAME="s5_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="233" MSB="1" NAME="s5_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="234" NAME="s5_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="s5_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="236" MSB="2" NAME="s5_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="237" MSB="3" NAME="s5_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="238" NAME="s5_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="239" NAME="s5_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="s5_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="241" MSB="3" NAME="s5_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S5_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="242" NAME="s5_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="243" NAME="s5_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="244" NAME="s5_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="245" MSB="3" NAME="s5_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="246" MSB="1" NAME="s5_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="247" NAME="s5_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="248" NAME="s5_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="249" MSB="3" NAME="s5_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="250" MSB="31" NAME="s5_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="251" MSB="7" NAME="s5_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="252" MSB="2" NAME="s5_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="253" MSB="1" NAME="s5_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="s5_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="255" MSB="3" NAME="s5_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="256" MSB="2" NAME="s5_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="257" MSB="3" NAME="s5_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="s5_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="259" NAME="s5_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="260" MSB="3" NAME="s5_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="261" MSB="31" NAME="s5_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="262" MSB="1" NAME="s5_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="s5_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="s5_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="265" NAME="s5_axi_rready" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S0_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_rready"/>
- </PORTMAPS>
- <MASTERS>
- <MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
- <MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
- </MASTERS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S1_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="2" NAME="S2_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S3_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="4" NAME="S4_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="5" NAME="S5_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/>
- <PORTMAP DIR="IO" PHYSICAL="rzq"/>
- <PORTMAP DIR="IO" PHYSICAL="zio"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M">
- <SLAVES>
- <SLAVE BUSINTERFACE="S0_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S1_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S1_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S1_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S2_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S2_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S2_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S3_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S3_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S3_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S4_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S4_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S4_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S5_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S5_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S5_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
- <DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40e00000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x40e0ffff"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_S_AXI_ACLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000"/>
- <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="6" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="7" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="8" NAME="C_INCLUDE_MDIO" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="9" NAME="C_INCLUDE_GLOBAL_BUFFERS" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="10" NAME="C_INCLUDE_INTERNAL_LOOPBACK" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="11" NAME="C_DUPLEX" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="12" NAME="C_TX_PING_PONG" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="13" NAME="C_RX_PING_PONG" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="14" NAME="C_INCLUDE_PHY_CONSTRAINTS" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="15" NAME="C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="16" NAME="C_INTERCONNECT_S_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="17" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="IO" IOS="ethernet_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="48" NAME="PHY_MDIO" SIGNAME="Ethernet_Lite_MDIO" TRI_I="PHY_MDIO_I" TRI_O="PHY_MDIO_O" TRI_T="PHY_MDIO_T">
- <DESCRIPTION>Ethernet PHY Management Data</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="44" NAME="PHY_MDC" SIGNAME="Ethernet_Lite_MDC">
- <DESCRIPTION>Ethernet PHY Management Clock</DESCRIPTION>
- </PORT>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="43" MSB="3" NAME="PHY_tx_data" RIGHT="0" SIGNAME="Ethernet_Lite_TXD" VECFORMULA="[3:0]">
- <DESCRIPTION>Ethernet Transmit Data Output</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="42" NAME="PHY_tx_en" SIGNAME="Ethernet_Lite_TX_EN">
- <DESCRIPTION>Ethernet Transmit Enable</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="34" NAME="PHY_tx_clk" SIGNAME="Ethernet_Lite_TX_CLK">
- <DESCRIPTION>Ethernet Transmit Clock Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="39" NAME="PHY_col" SIGNAME="Ethernet_Lite_COL">
- <DESCRIPTION>Ethernet Collision Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="6" MPD_INDEX="38" MSB="3" NAME="PHY_rx_data" RIGHT="0" SIGNAME="Ethernet_Lite_RXD" VECFORMULA="[3:0]">
- <DESCRIPTION>Ethernet Receive Data Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="40" NAME="PHY_rx_er" SIGNAME="Ethernet_Lite_RX_ER">
- <DESCRIPTION>Ethernet Receive Error Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="35" NAME="PHY_rx_clk" SIGNAME="Ethernet_Lite_RX_CLK">
- <DESCRIPTION>Ethernet Receive Clock Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="36" NAME="PHY_crs" SIGNAME="Ethernet_Lite_CRS">
- <DESCRIPTION>Ethernet Carrier Sense Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="37" NAME="PHY_dv" SIGNAME="Ethernet_Lite_RX_DV">
- <DESCRIPTION>Ethernet Receive Data Valid</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="41" NAME="PHY_rst_n" SIGNAME="Ethernet_Lite_PHY_RST_N">
- <DESCRIPTION>Ethernet PHY Reset</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="2" NAME="IP2INTC_Irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="5" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="6" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="10" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="11" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="I" MPD_INDEX="13" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_M_WLAST"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BID" DIR="O" MPD_INDEX="16" NAME="S_AXI_BID" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="26" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="27" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RID" DIR="O" MPD_INDEX="28" NAME="S_AXI_RID" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="O" MPD_INDEX="31" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_M_RLAST"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="32" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="33" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="I" IOS="ethernet_0" MPD_INDEX="45" NAME="PHY_MDIO_I" SIGNAME="__NOC__"/>
- <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="46" NAME="PHY_MDIO_O" SIGNAME="__NOC__"/>
- <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="47" NAME="PHY_MDIO_T" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="ethernet_0" TYPE="XIL_AXIETHERNET_V1">
- <PORTMAPS>
- <PORTMAP DIR="IO" PHYSICAL="PHY_MDIO"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDC"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_tx_data"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_tx_en"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_tx_clk"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_col"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_data"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_er"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_clk"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_crs"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_dv"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_rst_n"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_MDIO_I"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_O"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_T"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
- <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1"/>
- <PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1"/>
- <PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1"/>
- <PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41c00000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x41c0ffff"/>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_Interrupt"/>
- <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
- <DESCRIPTION>Capture Trig 0</DESCRIPTION>
- </PORT>
- <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
- <DESCRIPTION>Capture Trig 1</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
- <DESCRIPTION>Generate Out 0</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
- <DESCRIPTION>Generate Out 1</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
- <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
- </PORT>
- <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
- <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff"/>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="2"/>
- <PARAMETER MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0xffffffff"/>
- <PARAMETER MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0xffffffff"/>
- <PARAMETER MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0xffffffff"/>
- <PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"/>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="20" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt">
- <DESCRIPTION>Interrupt Request Output</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="1" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
- <SIGNALS>
- <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <SIGNAL NAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <SIGNAL NAME="axi_timer_0_Interrupt"/>
- <SIGNAL NAME="RS232_Uart_1_Interrupt"/>
- </SIGNALS>
- <DESCRIPTION>Interrupt Inputs</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
- <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="0" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="1" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <SOURCE INSTANCE="axi_timer_0" PRIORITY="2" SIGNAME="axi_timer_0_Interrupt"/>
- <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="3" SIGNAME="RS232_Uart_1_Interrupt"/>
- <TARGET INSTANCE="microblaze_0"/>
- </INTERRUPTINFO>
- </MODULE>
- </MODULES>
-
-</EDKSYSTEM>
\ No newline at end of file
+++ /dev/null
- -device xc6slx45tfgg484-3 data/system.ucf 7 0\r
+++ /dev/null
- -device xc6slx45tfgg484-3 data/system.ucf 0\r
+++ /dev/null
-#\r
-# pin constraints\r
-#\r
-NET CLK_N LOC = "K22" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";\r
-NET CLK_P LOC = "K21" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";\r
-NET Ethernet_Lite_COL LOC = "M16" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_CRS LOC = "N15" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_MDC LOC = "R19" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_MDIO LOC = "V20" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_PHY_RST_N LOC = "J22" | IOSTANDARD = "LVCMOS25" | TIG;\r
-NET Ethernet_Lite_RXD[0] LOC = "P19" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_RXD[1] LOC = "Y22" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_RXD[2] LOC = "Y21" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_RXD[3] LOC = "W22" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_RX_CLK LOC = "P20" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_RX_DV LOC = "T22" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_RX_ER LOC = "U20" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_TXD[0] LOC = "U10" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_TXD[1] LOC = "T10" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_TXD[2] LOC = "AB8" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_TXD[3] LOC = "AA8" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_TX_CLK LOC = "L20" | IOSTANDARD = "LVCMOS25";\r
-NET Ethernet_Lite_TX_EN LOC = "T8" | IOSTANDARD = "LVCMOS25";\r
-NET LEDs_4Bits_TRI_O[0] LOC = "D17" | IOSTANDARD = "LVCMOS25";\r
-NET LEDs_4Bits_TRI_O[1] LOC = "AB4" | IOSTANDARD = "LVCMOS25";\r
-NET LEDs_4Bits_TRI_O[2] LOC = "D21" | IOSTANDARD = "LVCMOS25";\r
-NET LEDs_4Bits_TRI_O[3] LOC = "W15" | IOSTANDARD = "LVCMOS25";\r
-NET Push_Buttons_4Bits_TRI_I[0] LOC = "F3" | IOSTANDARD = "LVCMOS25";\r
-NET Push_Buttons_4Bits_TRI_I[1] LOC = "G6" | IOSTANDARD = "LVCMOS25";\r
-NET Push_Buttons_4Bits_TRI_I[2] LOC = "F5" | IOSTANDARD = "LVCMOS25";\r
-NET Push_Buttons_4Bits_TRI_I[3] LOC = "C1" | IOSTANDARD = "LVCMOS25";\r
-NET RESET LOC = "H8" | IOSTANDARD = "LVCMOS15" | TIG;\r
-NET RS232_Uart_1_sin LOC = "H17" | IOSTANDARD = "LVCMOS25";\r
-NET RS232_Uart_1_sout LOC = "B21" | IOSTANDARD = "LVCMOS25";\r
-#\r
-# additional constraints\r
-#\r
-\r
-NET "CLK" TNM_NET = sys_clk_pin;\r
-TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;\r
-\r
+++ /dev/null
--g TdoPin:PULLNONE
--g StartUpClk:JTAGCLK
-#add other options here.
+++ /dev/null
-setMode -bscan\r
-setCable -p auto\r
-identify\r
-assignfile -p 2 -file implementation/download.bit\r
-program -p 2\r
-quit\r
+++ /dev/null
-FLOWTYPE = FPGA;
-###############################################################
-## Filename: fast_runtime.opt
-##
-## Option File For Xilinx FPGA Implementation Flow for Fast
-## Runtime.
-##
-## Version: 4.1.1
-###############################################################
-#
-# Options for Translator
-#
-# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
-#
-Program ngdbuild
--p <partname>; # Partname to use - picked from xflow commandline
--nt timestamp; # NGO File generation. Regenerate only when
- # source netlist is newer than existing
- # NGO file (default)
--bm <design>.bmm # Block RAM memory map file
-<userdesign>; # User design - pick from xflow command line
--uc <design>.ucf; # ucf constraints
-<design>.ngd; # Name of NGD file. Filebase same as design filebase
-End Program ngdbuild
-
-#
-# Options for Mapper
-#
-# Type "map -h <arch>" for a detailed list of map command line options
-#
-Program map
--o <design>_map.ncd; # Output Mapped ncd file
--w; # Overwrite output files.
--pr b; # Pack internal FF/latches into IOBs
-#-fp <design>.mfp; # Floorplan file
--ol high;
--timing;
--detail;
-<inputdir><design>.ngd; # Input NGD file
-<inputdir><design>.pcf; # Physical constraints file
-END Program map
-
-#
-# Options for Post Map Trace
-#
-# Type "trce -h" for a detailed list of trce command line options
-#
-Program post_map_trce
--e 3; # Produce error report limited to 3 items per constraint
-#-o <design>_map.twr; # Output trace report file
--xml <design>_map.twx; # Output XML version of the timing report
-#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
-<inputdir><design>_map.ncd; # Input mapped ncd
-<inputdir><design>.pcf; # Physical constraints file
-END Program post_map_trce
-
-#
-# Options for Place and Route
-#
-# Type "par -h" for a detailed list of par command line options
-#
-Program par
--w; # Overwrite existing placed and routed ncd
--ol high; # Overall effort level
-<inputdir><design>_map.ncd; # Input mapped NCD file
-<design>.ncd; # Output placed and routed NCD
-<inputdir><design>.pcf; # Input physical constraints file
-END Program par
-
-#
-# Options for Post Par Trace
-#
-# Type "trce -h" for a detailed list of trce command line options
-#
-Program post_par_trce
--e 3; # Produce error report limited to 3 items per constraint
-#-o <design>.twr; # Output trace report file
--xml <design>.twx; # Output XML version of the timing report
-#-tsi <design>.tsi; # Produce Timing Specification Interaction report
-<inputdir><design>.ncd; # Input placed and routed ncd
-<inputdir><design>.pcf; # Physical constraints file
-END Program post_par_trce
-
-
+++ /dev/null
-<FILTERS>
-
- <IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
-
- <SET CLASS="PROJECT" VIEW_ID="BUSINTERFACE">
- <HEADERS HSCROLL="0" VSCROLL="0">
- <VARIABLE COL_INDEX="0" COL_WIDTH="350" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
- <VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
- <SET CLASS="FILTER" ID="Connected" ROW_INDEX="0">
- <VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="1">
- <VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- </SET>
- <SET CLASS="FILTER_GROUP" ID="By Bus Standard" IS_EXPANDED="TRUE">
- <VARIABLE COL_INDEX="0" NAME="By Bus Standard" VALUE="By Bus Standard" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
- <SET CLASS="FILTER" ID="AXI" ROW_INDEX="0">
- <VARIABLE IS_LABELED="TRUE" NAME="AXI" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="AXIS" IS_VISIBLE="FALSE" ROW_INDEX="1">
- <VARIABLE IS_LABELED="TRUE" NAME="AXIS" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="OPB" IS_VISIBLE="FALSE" ROW_INDEX="2">
- <VARIABLE IS_LABELED="TRUE" NAME="OPB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="LMB" ROW_INDEX="3">
- <VARIABLE IS_LABELED="TRUE" NAME="LMB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="PLBV34" IS_VISIBLE="FALSE" ROW_INDEX="4">
- <VARIABLE IS_LABELED="TRUE" NAME="PLBV34" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="PLBV46" IS_VISIBLE="FALSE" ROW_INDEX="5">
- <VARIABLE IS_LABELED="TRUE" NAME="PLBV46" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="OCM" IS_VISIBLE="FALSE" ROW_INDEX="6">
- <VARIABLE IS_LABELED="TRUE" NAME="OCM" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="FSL" IS_VISIBLE="FALSE" ROW_INDEX="7">
- <VARIABLE IS_LABELED="TRUE" NAME="FSL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="DCR" IS_VISIBLE="FALSE" ROW_INDEX="8">
- <VARIABLE IS_LABELED="TRUE" NAME="DCR" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="FCB" IS_VISIBLE="FALSE" ROW_INDEX="9">
- <VARIABLE IS_LABELED="TRUE" NAME="FCB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="XIL" IS_EXPANDED="TRUE" ROW_INDEX="10">
- <VARIABLE IS_LABELED="TRUE" NAME="Xilinx Point To Point" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- <SET CLASS="SUB_FILTER" ID="XIL_BRAM" ROW_INDEX="0">
- <VARIABLE IS_LABELED="TRUE" NAME="XIL_BRAM" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="SUB_FILTER" ID="XIL_BSCAN" ROW_INDEX="1">
- <VARIABLE IS_LABELED="TRUE" NAME="XIL_BSCAN" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="SUB_FILTER" ID="XIL_MBDEBUG3" ROW_INDEX="2">
- <VARIABLE IS_LABELED="TRUE" NAME="XIL_MBDEBUG3" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="SUB_FILTER" ID="XIL_MBTRACE2" ROW_INDEX="3">
- <VARIABLE IS_LABELED="TRUE" NAME="XIL_MBTRACE2" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- </SET>
- <SET CLASS="FILTER" ID="USER" IS_VISIBLE="FALSE" ROW_INDEX="11">
- <VARIABLE IS_LABELED="TRUE" NAME="User Defined" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="XCL" IS_VISIBLE="FALSE" ROW_INDEX="12">
- <VARIABLE IS_LABELED="TRUE" NAME="XCL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- </SET>
- <SET CLASS="FILTER_GROUP" ID="By Interface Type" IS_EXPANDED="TRUE">
- <VARIABLE NAME="By Interface Type" VALUE="By Interface Type" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
- <SET CLASS="FILTER" ID="Slaves" ROW_INDEX="0">
- <VARIABLE IS_LABELED="TRUE" NAME="Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Masters" ROW_INDEX="1">
- <VARIABLE IS_LABELED="TRUE" NAME="Masters" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Master Slaves" ROW_INDEX="2">
- <VARIABLE IS_LABELED="TRUE" NAME="Master Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Monitors" ROW_INDEX="3">
- <VARIABLE IS_LABELED="TRUE" NAME="Monitors" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Targets" ROW_INDEX="4">
- <VARIABLE IS_LABELED="TRUE" NAME="Targets" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Initiators" ROW_INDEX="5">
- <VARIABLE IS_LABELED="TRUE" NAME="Initiators" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- </SET>
- </SET>
-
- <SET CLASS="PROJECT" VIEW_ID="PORT">
- <HEADERS HSCROLL="0" VSCROLL="0">
- <VARIABLE COL_INDEX="0" COL_WIDTH="400" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SET CLASS="FILTER_GROUP" ID="By Interface" IS_EXPANDED="TRUE">
- <VARIABLE NAME="By Interface" VALUE="By Interface" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
- <SET CLASS="FILTER" ID="BUS" ROW_INDEX="0">
- <VARIABLE IS_LABELED="TRUE" NAME="BUS" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="IO" ROW_INDEX="1">
- <VARIABLE IS_LABELED="TRUE" NAME="IO" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- </SET>
- <SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
- <VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
- <SET CLASS="FILTER" ID="Defaults" ROW_INDEX="0">
- <VARIABLE IS_LABELED="TRUE" NAME="Defaults" VALUE="FALSE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Connected" ROW_INDEX="1">
- <VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="2">
- <VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- </SET>
- <SET CLASS="FILTER_GROUP" ID="By Class" IS_EXPANDED="TRUE">
- <VARIABLE COL_INDEX="0" NAME="By Class" VALUE="By Class" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
- <SET CLASS="FILTER" ID="Clocks Only" ROW_INDEX="0">
- <VARIABLE NAME="Clocks Only" VALUE="Clocks Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
- </SET>
- <SET CLASS="FILTER" ID="Clocks" ROW_INDEX="1">
- <VARIABLE IS_LABELED="TRUE" NAME="Clocks" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Resets Only" ROW_INDEX="2">
- <VARIABLE NAME="Resets Only" VALUE="Resets Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
- </SET>
- <SET CLASS="FILTER" ID="Resets" ROW_INDEX="3">
- <VARIABLE IS_LABELED="TRUE" NAME="Resets" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Interrupts Only" ROW_INDEX="4">
- <VARIABLE NAME="Interrupts Only" VALUE="Interrupts Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
- </SET>
- <SET CLASS="FILTER" ID="Interrupts" ROW_INDEX="5">
- <VARIABLE IS_LABELED="TRUE" NAME="Interrupts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Others" ROW_INDEX="6">
- <VARIABLE IS_LABELED="TRUE" NAME="Others" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- </SET>
- <SET CLASS="FILTER_GROUP" ID="By Direction" IS_EXPANDED="TRUE">
- <VARIABLE NAME="By Direction" VALUE="By Direction" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
- <SET CLASS="FILTER" ID="Inputs" ROW_INDEX="0">
- <VARIABLE IS_LABELED="TRUE" NAME="Inputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="Outputs" ROW_INDEX="1">
- <VARIABLE IS_LABELED="TRUE" NAME="Outputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- <SET CLASS="FILTER" ID="InOuts" ROW_INDEX="2">
- <VARIABLE IS_LABELED="TRUE" NAME="InOuts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
- </SET>
- </SET>
- </SET>
-
-</FILTERS>
\ No newline at end of file
+++ /dev/null
-
-<SETTINGS>
-
- <IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
-
- <SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="BUSINTERFACE">
- <HEADERS HSCROLL="0" VSCROLL="0">
- <VARIABLE COL_INDEX="0" COL_WIDTH="237" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" COL_WIDTH="421" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
- <SET ID="RS232_Uart_1" IS_EXPANDED="TRUE"/>
- <SET ID="Ethernet_Lite" IS_EXPANDED="TRUE"/>
- <STATUS>
- <SELECTIONS>
- <VARIABLE ID="Ethernet_Lite"/>
- </SELECTIONS>
- </STATUS>
- <SEQUENCES IS_DEF_SEQUENCES="TRUE">
- <VARIABLE ID="axi4_0" ROW_INDEX="0"/>
- <VARIABLE ID="axi4lite_0" ROW_INDEX="1"/>
- <VARIABLE ID="microblaze_0" ROW_INDEX="4"/>
- <VARIABLE ID="microblaze_0_ilmb" ROW_INDEX="3"/>
- <VARIABLE ID="microblaze_0_dlmb" ROW_INDEX="2"/>
- <VARIABLE ID="microblaze_0_i_bram_ctrl" ROW_INDEX="7"/>
- <VARIABLE ID="microblaze_0_d_bram_ctrl" ROW_INDEX="6"/>
- <VARIABLE ID="microblaze_0_bram_block" ROW_INDEX="5"/>
- <VARIABLE ID="proc_sys_reset_0" ROW_INDEX="17"/>
- <VARIABLE ID="clock_generator_0" ROW_INDEX="16"/>
- <VARIABLE ID="debug_module" ROW_INDEX="9"/>
- <VARIABLE ID="RS232_Uart_1" IS_EXPANDED="TRUE" ROW_INDEX="15"/>
- <VARIABLE ID="LEDs_4Bits" ROW_INDEX="12"/>
- <VARIABLE ID="Push_Buttons_4Bits" ROW_INDEX="13"/>
- <VARIABLE ID="MCB_DDR3" ROW_INDEX="8"/>
- <VARIABLE ID="Ethernet_Lite" IS_EXPANDED="TRUE" ROW_INDEX="11"/>
- <VARIABLE ID="axi_timer_0" ROW_INDEX="14"/>
- <VARIABLE ID="microblaze_0_intc" ROW_INDEX="10"/>
- </SEQUENCES>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="BUSINTERFACE">
- <HEADERS>
- <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="BUSINTERFACE">
- <HEADERS>
- <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="FOCUS_FLAT" VIEW_ID="BUSINTERFACE">
- <HEADERS>
- <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
- <HEADERS HSCROLL="0" VSCROLL="144">
- <VARIABLE COL_INDEX="0" COL_WIDTH="217" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" COL_WIDTH="652" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="8" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
- <SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
- <SET ID="RS232_Uart_1" IS_EXPANDED="TRUE"/>
- <SET ID="Push_Buttons_4Bits" IS_EXPANDED="TRUE"/>
- <SET ID="Ethernet_Lite" IS_EXPANDED="TRUE">
- <SET ID="ethernet_0" IS_EXPANDED="TRUE"/>
- </SET>
- <SET ID="microblaze_0_intc" IS_EXPANDED="TRUE">
- <SET ID="S_AXI" IS_EXPANDED="TRUE"/>
- </SET>
- <STATUS>
- <SELECTIONS/>
- </STATUS>
- <SEQUENCES IS_DEF_SEQUENCES="TRUE">
- <VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
- <VARIABLE ID="axi4_0" ROW_INDEX="1"/>
- <VARIABLE ID="axi4lite_0" ROW_INDEX="2"/>
- <VARIABLE ID="microblaze_0" IS_EXPANDED="TRUE" ROW_INDEX="5"/>
- <VARIABLE ID="microblaze_0_ilmb" ROW_INDEX="4"/>
- <VARIABLE ID="microblaze_0_dlmb" ROW_INDEX="3"/>
- <VARIABLE ID="microblaze_0_i_bram_ctrl" ROW_INDEX="8"/>
- <VARIABLE ID="microblaze_0_d_bram_ctrl" ROW_INDEX="7"/>
- <VARIABLE ID="microblaze_0_bram_block" ROW_INDEX="6"/>
- <VARIABLE ID="proc_sys_reset_0" ROW_INDEX="18"/>
- <VARIABLE ID="clock_generator_0" ROW_INDEX="17"/>
- <VARIABLE ID="debug_module" ROW_INDEX="10"/>
- <VARIABLE ID="RS232_Uart_1" IS_EXPANDED="TRUE" ROW_INDEX="16"/>
- <VARIABLE ID="LEDs_4Bits" ROW_INDEX="13"/>
- <VARIABLE ID="Push_Buttons_4Bits" IS_EXPANDED="TRUE" ROW_INDEX="14"/>
- <VARIABLE ID="MCB_DDR3" ROW_INDEX="9"/>
- <VARIABLE ID="Ethernet_Lite" IS_EXPANDED="TRUE" ROW_INDEX="12"/>
- <VARIABLE ID="axi_timer_0" ROW_INDEX="15"/>
- <VARIABLE ID="microblaze_0_intc" IS_EXPANDED="TRUE" ROW_INDEX="11"/>
- </SEQUENCES>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="PORT">
- <HEADERS HSCROLL="0" VSCROLL="0">
- <VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" COL_WIDTH="192" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="8" COL_WIDTH="200" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
- <SET ID="microblaze_0_intc" IS_EXPANDED="TRUE"/>
- <STATUS>
- <SELECTIONS>
- <VARIABLE ID="microblaze_0_intc"/>
- </SELECTIONS>
- </STATUS>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="PORT">
- <HEADERS>
- <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Port Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="FOCUS_FLAT" VIEW_ID="PORT">
- <HEADERS>
- <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Port Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="ADDRESS">
- <HEADERS HSCROLL="0" VSCROLL="0">
- <VARIABLE COL_INDEX="0" COL_WIDTH="200" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" COL_WIDTH="105" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="9" COL_WIDTH="605" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
- </HEADERS>
- <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
- <SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
- <STATUS>
- <SELECTIONS/>
- </STATUS>
- </SET>
-
- <SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="ADDRESS">
- <HEADERS>
- <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="11" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
- <VARIABLE COL_INDEX="12" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
- </HEADERS>
- </SET>
-
-</SETTINGS>
\ No newline at end of file
+++ /dev/null
-\1d\84æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Dbb\b\`bDv*\84æÄ®Òôtt¦Êè\84ÞÂäÈ@DðÒØÒÜð\ÆÞÚD@Dæàl`jD@D\86Dv.\84æÄ®ÒôttªàÈÂèÊ\84ÞÂäÈ@D\82¤\86\90\92¨\8a\86¨ª¤\8aD@DæàÂäèÂÜlDv.\84æÄ®ÒôttªàÈÂèÊ\84ÞÂäÈ@D\88\8a¬\92\86\8a¾¦\92´\8aD@DðÆlæØðhjèDv'\84æÄ®ÒôttªàÈÂèÊ\84ÞÂäÈ@D \82\86\96\82\8e\8aD@DÌÎÎhphDv'\84æÄ®ÒôttªàÈÂèÊ\84ÞÂäÈ@D¤¦¨¾ \9e\98\82¤\92¨²D@DbDv&\84æÄ®ÒôttªàÈÂèÊ\84ÞÂäÈ@D¦ \8a\8a\88\8e¤\82\88\8aD@DZfDv%\84æÄ®Òôtt¦Êè¦òæèÊÚ@DÚľÂðÒ¾bêàD@Db\`Dv;\84æÄ®ÒôttªàÈÂèʦòæèÊÚ@D\86ØÖ¾\8cäÊâD@Dd````````D@DÚÒÆäÞÄØÂôʾ`Dv@\84æÄ®Òôtt\82ÈÈ äÞÆÊææÞä@DÚÒÆäÞÄØÂôʾ`D@DÚÒÆäÞÄØÂôÊD@DÚÒÆäÞÄØÂôʾ`DvH\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÈÂè¾ÆÂÆÐʾÚÊÚ¾ØÒæèD@D\9a\86\84¾\88\88¤fDvA\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÈÂè¾ÆÂÆÐʾæÒôÊD@DblfphDvI\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÒÜæèä¾ÆÂÆÐʾÚÊÚ¾ØÒæèD@D\9a\86\84¾\88\88¤fDvB\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÒÜæèä¾ÆÂÆÐʾæÒôÊD@DblfphDvH\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÚľÆØÞÆÖ¾ÌäÊâêÊÜÆòD@Db````````Dv>\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÚľÌàê¾ÊÜÂÄØÊD@D¨¤ª\8aDvE\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÚľØÞÆÂؾÚÊÚÞäò¾æÒôÊD@DpbrdDvH\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D\8aèÐÊäÜÊè¾\98ÒèÊD@DÂðÒ¾ÊèÐÊäÜÊèØÒèÊD@DÚÒÆäÞÄØÂôʾ`DvB\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D\8aèÐÊäÜÊè¾\98ÒèÊD@DêæʾÒÜèÊääêàè¾ÒÈD@D¨¤ª\8aDv=\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D\98\8a\88æ¾h\84ÒèæD@DÂðÒ¾ÎàÒÞD@DÚÒÆäÞÄØÂôʾ`Dv@\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D\98\8a\88æ¾h\84ÒèæD@DêæʾÒÜèÊääêàè¾ÒÈD@D\8c\82\98¦\8aDv>\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D\9a\86\84¾\88\88¤fD@DÂðÒ¾æl¾ÈÈäðD@DÚÒÆäÞÄØÂôʾ`DvE\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D êæо\84êèèÞÜæ¾h\84ÒèæD@DÂðÒ¾ÎàÒÞD@DÚÒÆäÞÄØÂôʾ`DvG\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D êæо\84êèèÞÜæ¾h\84ÒèæD@DêæʾÒÜèÊääêàè¾ÒÈD@D¨¤ª\8aDvC\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäè¾bD@DÂðÒ¾êÂäèØÒèÊD@DÚÒÆäÞÄØÂôʾ`DvC\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DêÂäè¾`¾ÄÂêȾäÂèÊD@Dbbjd``Dv>\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DêÂäè¾`¾ÈÂèÂîÒÈèÐD@DpDv>\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DêÂäè¾`¾àÂäÒèòD@DÜÞÜÊDvA\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DêæʾÒÜèÊääêàè¾ÒÈD@D¨¤ª\8aDv?\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@DÂðÒ¾èÒÚÊä¾`D@DÂðÒ¾èÒÚÊäD@DÚÒÆäÞÄØÂôʾ`Dv@\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÂðÒ¾èÒÚÊä¾`D@DêæʾÒÜèÊääêàè¾ÒÈD@D¨¤ª\8aDv
\ No newline at end of file
+++ /dev/null
-#################################################################\r
-# Makefile generated by Xilinx Platform Studio \r
-# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.xmp\r
-#\r
-# WARNING : This file will be re-generated every time a command\r
-# to run a make target is invoked. So, any changes made to this \r
-# file manually, will be lost when make is invoked next. \r
-#################################################################\r
-\r
-# Name of the Microprocessor system\r
-# The hardware specification of the system is in file :\r
-# C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.mhs\r
-\r
-include system_incl.make\r
-\r
-#################################################################\r
-# PHONY TARGETS\r
-#################################################################\r
-.PHONY: dummy\r
-.PHONY: netlistclean\r
-.PHONY: bitsclean\r
-.PHONY: simclean\r
-.PHONY: exporttosdk\r
-\r
-#################################################################\r
-# EXTERNAL TARGETS\r
-#################################################################\r
-all:\r
- @echo "Makefile to build a Microprocessor system :"\r
- @echo "Run make with any of the following targets"\r
- @echo " "\r
- @echo " netlist : Generates the netlist for the given MHS "\r
- @echo " bits : Runs Implementation tools to generate the bitstream"\r
- @echo " exporttosdk: Export files to SDK"\r
- @echo " "\r
- @echo " init_bram: Initializes bitstream with BRAM data"\r
- @echo " ace : Generate ace file from bitstream and elf"\r
- @echo " download : Downloads the bitstream onto the board"\r
- @echo " "\r
- @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"\r
- @echo " simmodel : Generates HDL simulation models for chosen simulation mode"\r
- @echo " "\r
- @echo " netlistclean: Deletes netlist"\r
- @echo " bitsclean: Deletes bit, ncd, bmm files"\r
- @echo " hwclean : Deletes implementation dir"\r
- @echo " simclean : Deletes simulation dir"\r
- @echo " clean : Deletes all generated files/directories"\r
- @echo " "\r
-\r
-bits: $(SYSTEM_BIT)\r
-\r
-ace: $(SYSTEM_ACE)\r
-\r
-exporttosdk: $(SYSTEM_HW_HANDOFF_DEP)\r
-\r
-netlist: $(POSTSYN_NETLIST)\r
-\r
-download: $(DOWNLOAD_BIT) dummy\r
- @echo "*********************************************"\r
- @echo "Downloading Bitstream onto the target board"\r
- @echo "*********************************************"\r
- impact -batch etc/download.cmd\r
-\r
-init_bram: $(DOWNLOAD_BIT)\r
-\r
-sim: $(DEFAULT_SIM_SCRIPT)\r
- cd simulation/behavioral & \\r
- system_fuse.cmd\r
- cd simulation/behavioral & \\r
- start /B $(SIM_CMD) -gui -tclbatch system_setup.tcl\r
-\r
-simmodel: $(DEFAULT_SIM_SCRIPT)\r
-\r
-behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)\r
-\r
-structural_model: $(STRUCTURAL_SIM_SCRIPT)\r
-\r
-clean: hwclean simclean\r
- rm -f _impact.cmd\r
-\r
-hwclean: netlistclean bitsclean\r
- rm -rf implementation synthesis xst hdl\r
- rm -rf xst.srp $(SYSTEM).srp\r
- rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
-\r
-netlistclean:\r
- rm -f $(POSTSYN_NETLIST)\r
- rm -f platgen.log\r
- rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
- rm -f $(BMM_FILE)\r
-\r
-bitsclean:\r
- rm -f $(SYSTEM_BIT)\r
- rm -f implementation/$(SYSTEM).ncd\r
- rm -f implementation/$(SYSTEM)_bd.bmm \r
- rm -f implementation/$(SYSTEM)_map.ncd \r
- rm -f implementation/download.bit \r
- rm -f __xps/$(SYSTEM)_routed\r
-\r
-simclean: \r
- rm -rf simulation/behavioral\r
- rm -f simgen.log\r
- rm -f __xps/ise/_xmsgs/simgen.xmsgs\r
-\r
-#################################################################\r
-# BOOTLOOP ELF FILES\r
-#################################################################\r
-\r
-\r
-$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP_LE)\r
- IF NOT EXIST "$(BOOTLOOP_DIR)" @mkdir "$(BOOTLOOP_DIR)"\r
- cp -f $(MICROBLAZE_BOOTLOOP_LE) $(MICROBLAZE_0_BOOTLOOP)\r
-\r
-#################################################################\r
-# HARDWARE IMPLEMENTATION FLOW\r
-#################################################################\r
-\r
-\r
-$(BMM_FILE) \\r
-$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \\r
- $(CORE_STATE_DEVELOPMENT_FILES)\r
- @echo "****************************************************"\r
- @echo "Creating system netlist for hardware specification.."\r
- @echo "****************************************************"\r
- platgen $(PLATGEN_OPTIONS) $(MHSFILE)\r
-\r
-$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)\r
- @echo "Running synthesis..."\r
- cd synthesis & synthesis.cmd\r
-\r
-__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)\r
- @echo "*********************************************"\r
- @echo "Running Xilinx Implementation tools.."\r
- @echo "*********************************************"\r
- @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf\r
- @cp -f etc/fast_runtime.opt implementation/xflow.opt\r
- xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc\r
- touch __xps/$(SYSTEM)_routed\r
-\r
-$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE)\r
- xilperl $(XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par\r
- @echo "*********************************************"\r
- @echo "Running Bitgen.."\r
- @echo "*********************************************"\r
- @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut\r
- cd implementation & bitgen -w -f bitgen.ut $(SYSTEM) & cd ..\r
-\r
-$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_IMP_FILES) __xps/bitinit.opt\r
- @cp -f implementation/$(SYSTEM)_bd.bmm .\r
- @echo "*********************************************"\r
- @echo "Initializing BRAM contents of the bitstream"\r
- @echo "*********************************************"\r
- bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_IMP_FILE_ARGS) \\r
- -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)\r
- @rm -f $(SYSTEM)_bd.bmm\r
-\r
-$(SYSTEM_ACE):\r
- @echo "In order to generate ace file, you must have:-"\r
- @echo "- exactly one processor."\r
- @echo "- opb_mdm, if using microblaze."\r
-\r
-#################################################################\r
-# EXPORT_TO_SDK FLOW\r
-#################################################################\r
-\r
-$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt\r
- IF NOT EXIST "$(SDK_EXPORT_DIR)" @mkdir "$(SDK_EXPORT_DIR)"\r
- psf2Edward -inp $(SYSTEM).xmp -exit_on_error -edwver 1.2 -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT)\r
- xdsgen -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(GLOBAL_SEARCHPATHOPT) -make_docs_local\r
-\r
-$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT)\r
- @rm -rf $(SYSTEM_HW_HANDOFF_BIT)\r
- @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR)\r
-\r
-$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm\r
- @rm -rf $(SYSTEM_HW_HANDOFF_BMM)\r
- @cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR)\r
-\r
-#################################################################\r
-# SIMULATION FLOW\r
-#################################################################\r
-\r
-\r
-################## BEHAVIORAL SIMULATION ##################\r
-\r
-$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \\r
- $(BRAMINIT_ELF_SIM_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating behavioral simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)\r
-\r
-################## STRUCTURAL SIMULATION ##################\r
-\r
-$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \\r
- $(BRAMINIT_ELF_SIM_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating structural simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)\r
-\r
-\r
-################## TIMING SIMULATION ##################\r
-\r
-implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed\r
-\r
-$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \\r
- $(BRAMINIT_ELF_SIM_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating timing simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)\r
-\r
-dummy:\r
- @echo ""\r
-\r
+++ /dev/null
-\r
-# ##############################################################################\r
-# Created by Base System Builder Wizard for Xilinx EDK 13.1 Build EDK_O.40d\r
-# Mon May 30 21:43:34 2011\r
-# Target Board: xilinx.com sp605 Rev C\r
-# Family: spartan6\r
-# Device: xc6slx45t\r
-# Package: fgg484\r
-# Speed Grade: -3\r
-# ##############################################################################\r
- PARAMETER VERSION = 2.1.0\r
-\r
-\r
- PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1\r
- PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000\r
- PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000\r
- PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O\r
- PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I\r
- PORT LEDs_4Bits_TRI_O = LEDs_4Bits_TRI_O, DIR = O, VEC = [0:3]\r
- PORT Push_Buttons_4Bits_TRI_I = Push_Buttons_4Bits_TRI_I, DIR = I, VEC = [3:0]\r
- PORT mcbx_dram_clk = mcbx_dram_clk, DIR = O\r
- PORT mcbx_dram_clk_n = mcbx_dram_clk_n, DIR = O\r
- PORT mcbx_dram_cke = mcbx_dram_cke, DIR = O\r
- PORT mcbx_dram_odt = mcbx_dram_odt, DIR = O\r
- PORT mcbx_dram_ras_n = mcbx_dram_ras_n, DIR = O\r
- PORT mcbx_dram_cas_n = mcbx_dram_cas_n, DIR = O\r
- PORT mcbx_dram_we_n = mcbx_dram_we_n, DIR = O\r
- PORT mcbx_dram_udm = mcbx_dram_udm, DIR = O\r
- PORT mcbx_dram_ldm = mcbx_dram_ldm, DIR = O\r
- PORT mcbx_dram_ba = mcbx_dram_ba, DIR = O, VEC = [2:0]\r
- PORT mcbx_dram_addr = mcbx_dram_addr, DIR = O, VEC = [12:0]\r
- PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst, DIR = O\r
- PORT mcbx_dram_dq = mcbx_dram_dq, DIR = IO, VEC = [15:0]\r
- PORT mcbx_dram_dqs = mcbx_dram_dqs, DIR = IO\r
- PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n, DIR = IO\r
- PORT mcbx_dram_udqs = mcbx_dram_udqs, DIR = IO\r
- PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n, DIR = IO\r
- PORT rzq = rzq, DIR = IO\r
- PORT zio = zio, DIR = IO\r
- PORT Ethernet_Lite_MDIO = Ethernet_Lite_MDIO, DIR = IO\r
- PORT Ethernet_Lite_MDC = Ethernet_Lite_MDC, DIR = O\r
- PORT Ethernet_Lite_TXD = Ethernet_Lite_TXD, DIR = O, VEC = [3:0]\r
- PORT Ethernet_Lite_TX_EN = Ethernet_Lite_TX_EN, DIR = O\r
- PORT Ethernet_Lite_TX_CLK = Ethernet_Lite_TX_CLK, DIR = I\r
- PORT Ethernet_Lite_COL = Ethernet_Lite_COL, DIR = I\r
- PORT Ethernet_Lite_RXD = Ethernet_Lite_RXD, DIR = I, VEC = [3:0]\r
- PORT Ethernet_Lite_RX_ER = Ethernet_Lite_RX_ER, DIR = I\r
- PORT Ethernet_Lite_RX_CLK = Ethernet_Lite_RX_CLK, DIR = I\r
- PORT Ethernet_Lite_CRS = Ethernet_Lite_CRS, DIR = I\r
- PORT Ethernet_Lite_RX_DV = Ethernet_Lite_RX_DV, DIR = I\r
- PORT Ethernet_Lite_PHY_RST_N = Ethernet_Lite_PHY_RST_N, DIR = O\r
-\r
-\r
-BEGIN axi_interconnect\r
- PARAMETER INSTANCE = axi4_0\r
- PARAMETER HW_VER = 1.02.a\r
- PORT interconnect_aclk = clk_100_0000MHzPLL0\r
- PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn\r
-END\r
-\r
-BEGIN axi_interconnect\r
- PARAMETER INSTANCE = axi4lite_0\r
- PARAMETER HW_VER = 1.02.a\r
- PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0\r
- PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn\r
- PORT INTERCONNECT_ACLK = clk_50_0000MHzPLL0\r
-END\r
-\r
-BEGIN microblaze\r
- PARAMETER INSTANCE = microblaze_0\r
- PARAMETER HW_VER = 8.10.a\r
- PARAMETER C_INTERCONNECT = 2\r
- PARAMETER C_USE_BARREL = 1\r
- PARAMETER C_USE_FPU = 1\r
- PARAMETER C_DEBUG_ENABLED = 1\r
- PARAMETER C_ICACHE_BASEADDR = 0xc0000000\r
- PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff\r
- PARAMETER C_USE_ICACHE = 1\r
- PARAMETER C_ICACHE_ALWAYS_USED = 1\r
- PARAMETER C_DCACHE_BASEADDR = 0xc0000000\r
- PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff\r
- PARAMETER C_USE_DCACHE = 1\r
- PARAMETER C_DCACHE_ALWAYS_USED = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1\r
- PARAMETER C_NUMBER_OF_PC_BRK = 7\r
- PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2\r
- PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2\r
- PARAMETER C_CACHE_BYTE_SIZE = 16384\r
- PARAMETER C_DCACHE_BYTE_SIZE = 16384\r
- PARAMETER C_FPU_EXCEPTION = 1\r
- PARAMETER C_DIV_ZERO_EXCEPTION = 1\r
- PARAMETER C_M_AXI_I_BUS_EXCEPTION = 1\r
- PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1\r
- PARAMETER C_ILL_OPCODE_EXCEPTION = 1\r
- PARAMETER C_OPCODE_0x0_ILLEGAL = 1\r
- PARAMETER C_UNALIGNED_EXCEPTIONS = 1\r
- PARAMETER C_USE_DIV = 1\r
- BUS_INTERFACE M_AXI_DP = axi4lite_0\r
- BUS_INTERFACE M_AXI_DC = axi4_0\r
- BUS_INTERFACE M_AXI_IC = axi4_0\r
- BUS_INTERFACE DEBUG = microblaze_0_debug\r
- BUS_INTERFACE DLMB = microblaze_0_dlmb\r
- BUS_INTERFACE ILMB = microblaze_0_ilmb\r
- PORT MB_RESET = proc_sys_reset_0_MB_Reset\r
- PORT CLK = clk_100_0000MHzPLL0\r
- PORT INTERRUPT = microblaze_0_interrupt\r
-END\r
-\r
-BEGIN lmb_v10\r
- PARAMETER INSTANCE = microblaze_0_ilmb\r
- PARAMETER HW_VER = 2.00.a\r
- PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET\r
- PORT LMB_CLK = clk_100_0000MHzPLL0\r
-END\r
-\r
-BEGIN lmb_v10\r
- PARAMETER INSTANCE = microblaze_0_dlmb\r
- PARAMETER HW_VER = 2.00.a\r
- PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET\r
- PORT LMB_CLK = clk_100_0000MHzPLL0\r
-END\r
-\r
-BEGIN lmb_bram_if_cntlr\r
- PARAMETER INSTANCE = microblaze_0_i_bram_ctrl\r
- PARAMETER HW_VER = 3.00.a\r
- PARAMETER C_BASEADDR = 0x00000000\r
- PARAMETER C_HIGHADDR = 0x00001fff\r
- BUS_INTERFACE SLMB = microblaze_0_ilmb\r
- BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block\r
-END\r
-\r
-BEGIN lmb_bram_if_cntlr\r
- PARAMETER INSTANCE = microblaze_0_d_bram_ctrl\r
- PARAMETER HW_VER = 3.00.a\r
- PARAMETER C_BASEADDR = 0x00000000\r
- PARAMETER C_HIGHADDR = 0x00001fff\r
- BUS_INTERFACE SLMB = microblaze_0_dlmb\r
- BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block\r
-END\r
-\r
-BEGIN bram_block\r
- PARAMETER INSTANCE = microblaze_0_bram_block\r
- PARAMETER HW_VER = 1.00.a\r
- BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block\r
- BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block\r
-END\r
-\r
-BEGIN proc_sys_reset\r
- PARAMETER INSTANCE = proc_sys_reset_0\r
- PARAMETER HW_VER = 3.00.a\r
- PARAMETER C_EXT_RESET_HIGH = 1\r
- PORT Ext_Reset_In = RESET\r
- PORT MB_Reset = proc_sys_reset_0_MB_Reset\r
- PORT Slowest_sync_clk = clk_50_0000MHzPLL0\r
- PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn\r
- PORT Dcm_locked = proc_sys_reset_0_Dcm_locked\r
- PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst\r
- PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET\r
-END\r
-\r
-BEGIN clock_generator\r
- PARAMETER INSTANCE = clock_generator_0\r
- PARAMETER HW_VER = 4.01.a\r
- PARAMETER C_CLKIN_FREQ = 200000000\r
- PARAMETER C_CLKOUT0_FREQ = 600000000\r
- PARAMETER C_CLKOUT0_GROUP = PLL0\r
- PARAMETER C_CLKOUT0_BUF = FALSE\r
- PARAMETER C_CLKOUT1_FREQ = 600000000\r
- PARAMETER C_CLKOUT1_PHASE = 180\r
- PARAMETER C_CLKOUT1_GROUP = PLL0\r
- PARAMETER C_CLKOUT1_BUF = FALSE\r
- PARAMETER C_CLKOUT2_FREQ = 100000000\r
- PARAMETER C_CLKOUT2_GROUP = PLL0\r
- PARAMETER C_CLKOUT3_FREQ = 50000000\r
- PARAMETER C_CLKOUT3_GROUP = PLL0\r
- PORT RST = RESET\r
- PORT CLKIN = CLK\r
- PORT CLKOUT2 = clk_100_0000MHzPLL0\r
- PORT CLKOUT3 = clk_50_0000MHzPLL0\r
- PORT CLKOUT0 = clk_600_0000MHzPLL0_nobuf\r
- PORT CLKOUT1 = clk_600_0000MHz180PLL0_nobuf\r
- PORT LOCKED = proc_sys_reset_0_Dcm_locked\r
-END\r
-\r
-BEGIN mdm\r
- PARAMETER INSTANCE = debug_module\r
- PARAMETER HW_VER = 2.00.b\r
- PARAMETER C_INTERCONNECT = 2\r
- PARAMETER C_USE_UART = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1\r
- PARAMETER C_BASEADDR = 0x74800000\r
- PARAMETER C_HIGHADDR = 0x7480ffff\r
- BUS_INTERFACE S_AXI = axi4lite_0\r
- BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug\r
- PORT S_AXI_ACLK = clk_50_0000MHzPLL0\r
- PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst\r
-END\r
-\r
-BEGIN axi_uartlite\r
- PARAMETER INSTANCE = RS232_Uart_1\r
- PARAMETER HW_VER = 1.01.a\r
- PARAMETER C_BAUDRATE = 115200\r
- PARAMETER C_DATA_BITS = 8\r
- PARAMETER C_USE_PARITY = 0\r
- PARAMETER C_ODD_PARITY = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1\r
- PARAMETER C_BASEADDR = 0x40600000\r
- PARAMETER C_HIGHADDR = 0x4060ffff\r
- BUS_INTERFACE S_AXI = axi4lite_0\r
- PORT TX = RS232_Uart_1_sout\r
- PORT RX = RS232_Uart_1_sin\r
- PORT S_AXI_ACLK = clk_50_0000MHzPLL0\r
- PORT Interrupt = RS232_Uart_1_Interrupt\r
-END\r
-\r
-BEGIN axi_gpio\r
- PARAMETER INSTANCE = LEDs_4Bits\r
- PARAMETER HW_VER = 1.01.a\r
- PARAMETER C_GPIO_WIDTH = 4\r
- PARAMETER C_ALL_INPUTS = 0\r
- PARAMETER C_INTERRUPT_PRESENT = 0\r
- PARAMETER C_IS_DUAL = 0\r
- PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1\r
- PARAMETER C_BASEADDR = 0x40020000\r
- PARAMETER C_HIGHADDR = 0x4002ffff\r
- BUS_INTERFACE S_AXI = axi4lite_0\r
- PORT GPIO_IO_O = LEDs_4Bits_TRI_O\r
- PORT S_AXI_ACLK = clk_50_0000MHzPLL0\r
-END\r
-\r
-BEGIN axi_gpio\r
- PARAMETER INSTANCE = Push_Buttons_4Bits\r
- PARAMETER HW_VER = 1.01.a\r
- PARAMETER C_GPIO_WIDTH = 4\r
- PARAMETER C_ALL_INPUTS = 1\r
- PARAMETER C_INTERRUPT_PRESENT = 1\r
- PARAMETER C_IS_DUAL = 0\r
- PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1\r
- PARAMETER C_BASEADDR = 0x40000000\r
- PARAMETER C_HIGHADDR = 0x4000ffff\r
- BUS_INTERFACE S_AXI = axi4lite_0\r
- PORT GPIO_IO_I = Push_Buttons_4Bits_TRI_I\r
- PORT S_AXI_ACLK = clk_50_0000MHzPLL0\r
- PORT IP2INTC_Irpt = Push_Buttons_4Bits_IP2INTC_Irpt\r
-END\r
-\r
-BEGIN axi_s6_ddrx\r
- PARAMETER INSTANCE = MCB_DDR3\r
- PARAMETER HW_VER = 1.02.a\r
- PARAMETER C_MCB_RZQ_LOC = K7\r
- PARAMETER C_MCB_ZIO_LOC = R7\r
- PARAMETER C_MEM_TYPE = DDR3\r
- PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E\r
- PARAMETER C_MEM_BANKADDR_WIDTH = 3\r
- PARAMETER C_MEM_NUM_COL_BITS = 10\r
- PARAMETER C_SKIP_IN_TERM_CAL = 0\r
- PARAMETER C_S0_AXI_ENABLE = 1\r
- PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC\r
- PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1\r
- PARAMETER C_S0_AXI_BASEADDR = 0xc0000000\r
- PARAMETER C_S0_AXI_HIGHADDR = 0xc7ffffff\r
- BUS_INTERFACE S0_AXI = axi4_0\r
- PORT mcbx_dram_clk = mcbx_dram_clk\r
- PORT mcbx_dram_clk_n = mcbx_dram_clk_n\r
- PORT mcbx_dram_cke = mcbx_dram_cke\r
- PORT mcbx_dram_odt = mcbx_dram_odt\r
- PORT mcbx_dram_ras_n = mcbx_dram_ras_n\r
- PORT mcbx_dram_cas_n = mcbx_dram_cas_n\r
- PORT mcbx_dram_we_n = mcbx_dram_we_n\r
- PORT mcbx_dram_udm = mcbx_dram_udm\r
- PORT mcbx_dram_ldm = mcbx_dram_ldm\r
- PORT mcbx_dram_ba = mcbx_dram_ba\r
- PORT mcbx_dram_addr = mcbx_dram_addr\r
- PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst\r
- PORT mcbx_dram_dq = mcbx_dram_dq\r
- PORT mcbx_dram_dqs = mcbx_dram_dqs\r
- PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n\r
- PORT mcbx_dram_udqs = mcbx_dram_udqs\r
- PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n\r
- PORT rzq = rzq\r
- PORT zio = zio\r
- PORT s0_axi_aclk = clk_100_0000MHzPLL0\r
- PORT ui_clk = clk_100_0000MHzPLL0\r
- PORT sysclk_2x = clk_600_0000MHzPLL0_nobuf\r
- PORT sysclk_2x_180 = clk_600_0000MHz180PLL0_nobuf\r
- PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET\r
- PORT PLL_LOCK = proc_sys_reset_0_Dcm_locked\r
-END\r
-\r
-BEGIN axi_ethernetlite\r
- PARAMETER INSTANCE = Ethernet_Lite\r
- PARAMETER HW_VER = 1.00.a\r
- PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1\r
- PARAMETER C_BASEADDR = 0x40e00000\r
- PARAMETER C_HIGHADDR = 0x40e0ffff\r
- PARAMETER C_S_AXI_PROTOCOL = AXI4LITE\r
- PARAMETER C_RX_PING_PONG = 1\r
- PARAMETER C_TX_PING_PONG = 1\r
- PARAMETER C_S_AXI_ID_WIDTH = 1\r
- BUS_INTERFACE S_AXI = axi4lite_0\r
- PORT PHY_MDIO = Ethernet_Lite_MDIO\r
- PORT PHY_MDC = Ethernet_Lite_MDC\r
- PORT PHY_tx_data = Ethernet_Lite_TXD\r
- PORT PHY_tx_en = Ethernet_Lite_TX_EN\r
- PORT PHY_tx_clk = Ethernet_Lite_TX_CLK\r
- PORT PHY_col = Ethernet_Lite_COL\r
- PORT PHY_rx_data = Ethernet_Lite_RXD\r
- PORT PHY_rx_er = Ethernet_Lite_RX_ER\r
- PORT PHY_rx_clk = Ethernet_Lite_RX_CLK\r
- PORT PHY_crs = Ethernet_Lite_CRS\r
- PORT PHY_dv = Ethernet_Lite_RX_DV\r
- PORT PHY_rst_n = Ethernet_Lite_PHY_RST_N\r
- PORT S_AXI_ACLK = clk_50_0000MHzPLL0\r
- PORT IP2INTC_Irpt = Ethernet_Lite_IP2INTC_Irpt\r
-END\r
-\r
-BEGIN axi_timer\r
- PARAMETER INSTANCE = axi_timer_0\r
- PARAMETER HW_VER = 1.01.a\r
- PARAMETER C_COUNT_WIDTH = 32\r
- PARAMETER C_ONE_TIMER_ONLY = 0\r
- PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1\r
- PARAMETER C_BASEADDR = 0x41c00000\r
- PARAMETER C_HIGHADDR = 0x41c0ffff\r
- BUS_INTERFACE S_AXI = axi4lite_0\r
- PORT S_AXI_ACLK = clk_50_0000MHzPLL0\r
- PORT Interrupt = axi_timer_0_Interrupt\r
-END\r
-\r
-BEGIN axi_intc\r
- PARAMETER INSTANCE = microblaze_0_intc\r
- PARAMETER HW_VER = 1.01.a\r
- PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1\r
- PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1\r
- PARAMETER C_BASEADDR = 0x41200000\r
- PARAMETER C_HIGHADDR = 0x4120ffff\r
- BUS_INTERFACE S_AXI = axi4lite_0\r
- PORT IRQ = microblaze_0_interrupt\r
- PORT S_AXI_ACLK = clk_50_0000MHzPLL0\r
- PORT INTR = Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt\r
-END\r
-\r
+++ /dev/null
-#Please do not modify this file by hand\r
-XmpVersion: 13.1\r
-VerMgmt: 13.1\r
-IntStyle: default\r
-MHS File: system.mhs\r
-Architecture: spartan6\r
-Device: xc6slx45t\r
-Package: fgg484\r
-SpeedGrade: -3\r
-UserCmd1: \r
-UserCmd1Type: 0\r
-UserCmd2: \r
-UserCmd2Type: 0\r
-GenSimTB: 0\r
-SdkExportBmmBit: 1\r
-SdkExportDir: SDK/SDK_Export\r
-InsertNoPads: 0\r
-WarnForEAArch: 1\r
-HdlLang: VHDL\r
-SimModel: BEHAVIORAL\r
-UcfFile: data/system.ucf\r
-EnableParTimingError: 1\r
-ShowLicenseDialog: 1\r
-ICacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR\r
-ICacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR\r
-ICacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR\r
-ICacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR\r
-ICacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR\r
-ICacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR\r
-DCacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR\r
-DCacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR\r
-DCacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR\r
-DCacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR\r
-DCacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR\r
-DCacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR\r
-Processor: microblaze_0\r
-ElfImp: \r
-ElfSim: \r
+++ /dev/null
-#################################################################\r
-# Makefile generated by Xilinx Platform Studio \r
-# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.xmp\r
-#\r
-# WARNING : This file will be re-generated every time a command\r
-# to run a make target is invoked. So, any changes made to this \r
-# file manually, will be lost when make is invoked next. \r
-#################################################################\r
-\r
-SHELL = CMD\r
-\r
-XILINX_EDK_DIR = C:/devtools/Xilinx/13.1/ISE_DS/EDK\r
-\r
-SYSTEM = system\r
-\r
-MHSFILE = system.mhs\r
-\r
-FPGA_ARCH = spartan6\r
-\r
-DEVICE = xc6slx45tfgg484-3\r
-\r
-LANGUAGE = vhdl\r
-GLOBAL_SEARCHPATHOPT = \r
-PROJECT_SEARCHPATHOPT = \r
-\r
-SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT)\r
-\r
-SUBMODULE_OPT = \r
-\r
-PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst\r
-\r
-OBSERVE_PAR_OPTIONS = -error yes\r
-\r
-MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf\r
-MICROBLAZE_BOOTLOOP_LE = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop_le.elf\r
-PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf\r
-PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf\r
-BOOTLOOP_DIR = bootloops\r
-\r
-MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf\r
-\r
-BRAMINIT_ELF_IMP_FILES = $(MICROBLAZE_0_BOOTLOOP)\r
-BRAMINIT_ELF_IMP_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP)\r
-\r
-BRAMINIT_ELF_SIM_FILES = $(MICROBLAZE_0_BOOTLOOP)\r
-BRAMINIT_ELF_SIM_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP)\r
-\r
-SIM_CMD = isim_system\r
-\r
-BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.tcl\r
-\r
-STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.tcl\r
-\r
-TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.tcl\r
-\r
-DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)\r
-\r
-MIX_LANG_SIM_OPT = -mixed yes\r
-\r
-SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_SIM_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s isim\r
-\r
-\r
-CORE_STATE_DEVELOPMENT_FILES = \r
-\r
-WRAPPER_NGC_FILES = implementation/axi4_0_wrapper.ngc \
-implementation/axi4lite_0_wrapper.ngc \
-implementation/microblaze_0_wrapper.ngc \
-implementation/microblaze_0_ilmb_wrapper.ngc \
-implementation/microblaze_0_dlmb_wrapper.ngc \
-implementation/microblaze_0_i_bram_ctrl_wrapper.ngc \
-implementation/microblaze_0_d_bram_ctrl_wrapper.ngc \
-implementation/microblaze_0_bram_block_wrapper.ngc \
-implementation/proc_sys_reset_0_wrapper.ngc \
-implementation/clock_generator_0_wrapper.ngc \
-implementation/debug_module_wrapper.ngc \
-implementation/rs232_uart_1_wrapper.ngc \
-implementation/leds_4bits_wrapper.ngc \
-implementation/push_buttons_4bits_wrapper.ngc \
-implementation/mcb_ddr3_wrapper.ngc \
-implementation/ethernet_lite_wrapper.ngc \
-implementation/axi_timer_0_wrapper.ngc \
-implementation/microblaze_0_intc_wrapper.ngc\r
-\r
-POSTSYN_NETLIST = implementation/$(SYSTEM).ngc\r
-\r
-SYSTEM_BIT = implementation/$(SYSTEM).bit\r
-\r
-DOWNLOAD_BIT = implementation/download.bit\r
-\r
-SYSTEM_ACE = implementation/$(SYSTEM).ace\r
-\r
-UCF_FILE = data/system.ucf\r
-\r
-BMM_FILE = implementation/$(SYSTEM).bmm\r
-\r
-BITGEN_UT_FILE = etc/bitgen.ut\r
-\r
-XFLOW_OPT_FILE = etc/fast_runtime.opt\r
-XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)\r
-\r
-XPLORER_DEPENDENCY = __xps/xplorer.opt\r
-XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7\r
-\r
-FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)\r
-\r
-SDK_EXPORT_DIR = SDK\SDK_Export\hw\r
-SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml\r
-SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit\r
-SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm\r
-SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM)\r
--- /dev/null
+The project from this directory has been superseded by the project documented\r
+on the following page: http://www.freertos.org/RTOS-Xilinx-Microblaze-KC705.html\r
+\r
+If you need the demo that used to be in this directory then download FreeRTOS V8.2.1\r
+from http://sourceforge.net/projects/freertos/files/FreeRTOS/\r
+\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>\r
-<projectDescription>\r
- <name>HardwareWithEthernetLite</name>\r
- <comment></comment>\r
- <projects>\r
- </projects>\r
- <buildSpec>\r
- </buildSpec>\r
- <natures>\r
- <nature>com.xilinx.sdk.hw.HwProject</nature>\r
- </natures>\r
-</projectDescription>\r
+++ /dev/null
-
-<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Wed Jul 27 11:49:37 2011">
-
- <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
-
- <EXTERNALPORTS>
- <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
- <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
- <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
- <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
- <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
- <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
- <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
- <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
- <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
- <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
- <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
- <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
- <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
- <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
- <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
- <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
- <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
- <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
- <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
- <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
- <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
- <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
- <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
- <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
- <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
- <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
- <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
- <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
- <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
- <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
- <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
- <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
- <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
- </EXTERNALPORTS>
-
- <MODULES>
- <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
- <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Base Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="2">
- <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of Master Slots </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
- <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
- <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>AXI Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff00000000c0000000">
- <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7ffffff">
- <DESCRIPTION>Master AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000">
- <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100">
- <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
- <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111101">
- <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5">
- <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5">
- <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003">
- <DESCRIPTION>AXI Connectivity</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100">
- <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
- <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000020">
- <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000002">
- <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
- <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
- <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Secure</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
- <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI W Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI R Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Master AXI B Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Generate Interrupts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
- <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
- <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Simulation debug</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="clk_100_0000MHzPLL0&clk_100_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0&clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
- <SIGNALS>
- <SIGNAL NAME="clk_100_0000MHzPLL0"/>
- <SIGNAL NAME="clk_100_0000MHzPLL0"/>
- </SIGNALS>
- </PORT>
- <PORT DEF_SIGNAME="axi4_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="15" MSB="9" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi4_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi4_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi4_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi4_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi4_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi4_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi4_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi4_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="38" MSB="9" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi4_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi4_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi4_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi4_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi4_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi4_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="axi4_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="59" MSB="4" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="axi4_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi4_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi4_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi4_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi4_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="axi4_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi4_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi4_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi4_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="axi4_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="84" MSB="4" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="axi4_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi4_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi4_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi4_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi4_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
- <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Base Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="7">
- <DESCRIPTION>Number of Master Slots </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
- <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
- <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002">
- <DESCRIPTION>AXI Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000002000000020000000200000002000000020000000200000002">
- <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000074800000">
- <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041c0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040e0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007480ffff">
- <DESCRIPTION>Master AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
- <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000102faf08002faf08002faf08002faf08002faf08002faf08002faf080">
- <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000">
- <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
- <DESCRIPTION>AXI Connectivity</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
- <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111101111">
- <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Secure</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
- <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
- <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
- <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
- <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI W Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI R Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
- <DESCRIPTION>Master AXI B Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Generate Interrupts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
- <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
- <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Simulation debug</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
- <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="3" MSB="6" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="48" MSB="6" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0&clk_50_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
- <SIGNALS>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- <SIGNAL NAME="clk_50_0000MHzPLL0"/>
- </SIGNALS>
- </PORT>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="49" MSB="6" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="50" MSB="223" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="51" MSB="55" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="52" MSB="20" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="53" MSB="13" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="54" MSB="13" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="55" MSB="27" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="56" MSB="20" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="57" MSB="27" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="58" MSB="27" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="59" MSB="6" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="60" MSB="6" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="61" MSB="6" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="62" MSB="6" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="63" MSB="223" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="64" MSB="27" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="65" MSB="6" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="66" MSB="6" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="67" MSB="6" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="68" MSB="6" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="69" MSB="6" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="70" MSB="13" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="71" MSB="6" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="72" MSB="6" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="73" MSB="6" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="74" MSB="6" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="75" MSB="223" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="76" MSB="55" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="77" MSB="20" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="78" MSB="13" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="79" MSB="13" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="80" MSB="27" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="81" MSB="20" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="82" MSB="27" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="83" MSB="27" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="84" MSB="6" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="85" MSB="6" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="86" MSB="6" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="87" MSB="6" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="88" MSB="223" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="89" MSB="13" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="90" MSB="6" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="91" MSB="6" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="92" MSB="6" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="93" MSB="6" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
- <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
- <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
- <PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Fault Tolerance Support</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0">
- <DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2">
- <DESCRIPTION>Select Bus Interfaces</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Select Stream Interfaces</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
- <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
- <PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Pattern Comparator</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Barrel Shifter</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="41" MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Integer Divider</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Integer Multiplier</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Floating Point Unit</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="40" MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="36" MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Instruction-side AXI Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="37" MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Data-side AXI Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="35" MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="34" MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Stream Exception</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0">
- <DESCRIPTION><qt>Enable stack protection</qt></DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0">
- <DESCRIPTION>Specifies Processor Version Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00">
- <DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="7">
- <DESCRIPTION>Number of PC Breakpoints </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="2">
- <DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="2">
- <DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0">
- <DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1">
- <DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="39" MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="1">
- <DESCRIPTION><qt>Generate Illegal Instruction Exception for NULL Instruction</qt></DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Number of Stream Links </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Additional Stream Instructions</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
- <PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
- <DESCRIPTION>I-Cache Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
- <DESCRIPTION>I-Cache High Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Instruction Cache </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable I-Cache Writes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="13"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
- <DESCRIPTION>Size of the I-Cache in Bytes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4">
- <DESCRIPTION>Instruction Cache Line Length</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
- <DESCRIPTION>Use Cache Links for All I-Cache Memory Accesses </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Number of I-Cache Victims</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Number of I-Cache Streams</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
- <DESCRIPTION>Use Distributed RAM for I-Cache Tags</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
- <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
- <DESCRIPTION>D-Cache Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
- <DESCRIPTION>D-Cache High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable Data Cache</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1">
- <DESCRIPTION>Enable D-Cache Writes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="13"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
- <DESCRIPTION>Size of D-Cache in Bytes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4">
- <DESCRIPTION>Data Cache Line Length</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
- <DESCRIPTION>Use Cache Links for All D-Cache Memory Accesses </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Number of D-Cache Victims</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
- <DESCRIPTION>Use Distributed RAM for D-Cache Tags</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
- <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
- <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
- <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
- <PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
- <PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0">
- <DESCRIPTION>Memory Management</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4">
- <DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2">
- <DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3">
- <DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16">
- <DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0">
- <DESCRIPTION>Privileged Instructions</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/>
- <PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0">
- <DESCRIPTION>Enable Branch Target Cache</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0">
- <DESCRIPTION>Branch Target Cache Size</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_M_AXI_DP_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_DP_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_DP_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_DP_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_DP_B_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_IC_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_IC_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_IC_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_IC_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_IC_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
- <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"/>
- <PORT BUS="DLMB:ILMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
- <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
- <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:31]"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
- <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="IPLB_MRearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="IPLB_MTimeout" SIGNAME="__NOC__"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:31]"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
- <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="86" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="89" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="92" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="95" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="96" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="99" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="100" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="109" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="110" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="111" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="114" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="116" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="118" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="119" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="120" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="121" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="124" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="125" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="126" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="128" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="130" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="131" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="132" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="134" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="135" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="136" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="137" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="139" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="140" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="141" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="142" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="144" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="145" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="147" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="148" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="149" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="150" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="152" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="153" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="154" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="155" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="156" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="158" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RLAST" SIGNAME="axi4lite_0_S_RLAST"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="I" MPD_INDEX="160" NAME="M_AXI_DP_RVALID" SIGNAME="axi4lite_0_S_RVALID"/>
- <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="O" MPD_INDEX="161" NAME="M_AXI_DP_RREADY" SIGNAME="axi4lite_0_S_RREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="162" NAME="M_AXI_IC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="164" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="165" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="166" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="167" NAME="M_AXI_IC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="168" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="169" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="170" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="171" NAME="M_AXI_IC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="172" NAME="M_AXI_IC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="173" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="175" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="176" NAME="M_AXI_IC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="177" NAME="M_AXI_IC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="178" NAME="M_AXI_IC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="180" NAME="M_AXI_IC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="182" NAME="M_AXI_IC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="183" NAME="M_AXI_IC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="184" NAME="M_AXI_IC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="185" NAME="M_AXI_IC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="187" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="188" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="189" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="190" NAME="M_AXI_IC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="192" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="194" NAME="M_AXI_IC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="195" NAME="M_AXI_IC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="196" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="197" NAME="M_AXI_IC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="198" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="199" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_IC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="202" NAME="M_AXI_IC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
- <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="204" NAME="M_AXI_DC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="205" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="206" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="207" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="208" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="209" NAME="M_AXI_DC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="211" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="212" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="213" NAME="M_AXI_DC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="214" NAME="M_AXI_DC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="215" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="216" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="217" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="218" NAME="M_AXI_DC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="219" NAME="M_AXI_DC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="220" NAME="M_AXI_DC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="222" NAME="M_AXI_DC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="224" NAME="M_AXI_DC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="225" NAME="M_AXI_DC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="226" NAME="M_AXI_DC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="227" NAME="M_AXI_DC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="229" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="230" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="231" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="232" NAME="M_AXI_DC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="234" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="236" NAME="M_AXI_DC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="237" NAME="M_AXI_DC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="238" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="239" NAME="M_AXI_DC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="241" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="243" NAME="M_AXI_DC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="244" NAME="M_AXI_DC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
- <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="I" MPD_INDEX="246" NAME="DBG_CLK" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="I" MPD_INDEX="247" NAME="DBG_TDI" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="O" MPD_INDEX="248" NAME="DBG_TDO" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="249" MSB="0" NAME="DBG_REG_EN" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="I" MPD_INDEX="250" NAME="DBG_SHIFT" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="I" MPD_INDEX="251" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="I" MPD_INDEX="252" NAME="DBG_UPDATE" SIGNAME="microblaze_0_debug_Dbg_Update"/>
- <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="I" MPD_INDEX="253" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_debug_Debug_Rst"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="254" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="255" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="256" MSB="0" NAME="Trace_PC" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="257" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="258" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="259" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="260" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="261" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="262" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="263" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="266" MSB="0" NAME="Trace_Data_Address" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="Trace_Data_Access" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="268" NAME="Trace_Data_Read" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="269" NAME="Trace_Data_Write" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="270" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="271" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="272" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="273" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="274" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="275" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="276" NAME="Trace_ICache_Req" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="277" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="278" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="279" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="280" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="281" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/>
- <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="286" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="287" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="288" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="289" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="290" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="291" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="292" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="293" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="294" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="295" NAME="FSL1_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="296" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="297" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="298" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="299" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="300" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="301" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="302" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="303" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="304" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="FSL2_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="306" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="307" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="308" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="309" NAME="FSL2_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="310" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="311" MSB="0" NAME="FSL2_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="FSL2_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="313" NAME="FSL2_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="FSL3_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="FSL3_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="316" MSB="0" NAME="FSL3_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="317" NAME="FSL3_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="318" NAME="FSL3_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="319" NAME="FSL3_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="320" NAME="FSL3_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="321" MSB="0" NAME="FSL3_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="FSL3_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="323" NAME="FSL3_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="324" NAME="FSL4_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="325" NAME="FSL4_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="326" MSB="0" NAME="FSL4_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="327" NAME="FSL4_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="328" NAME="FSL4_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="329" NAME="FSL4_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="330" NAME="FSL4_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="331" MSB="0" NAME="FSL4_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="332" NAME="FSL4_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="333" NAME="FSL4_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="334" NAME="FSL5_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="335" NAME="FSL5_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="336" MSB="0" NAME="FSL5_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="337" NAME="FSL5_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="338" NAME="FSL5_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="339" NAME="FSL5_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="340" NAME="FSL5_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="341" MSB="0" NAME="FSL5_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="342" NAME="FSL5_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="343" NAME="FSL5_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="344" NAME="FSL6_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="345" NAME="FSL6_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="346" MSB="0" NAME="FSL6_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="347" NAME="FSL6_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="348" NAME="FSL6_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="349" NAME="FSL6_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="350" NAME="FSL6_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="351" MSB="0" NAME="FSL6_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="352" NAME="FSL6_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="353" NAME="FSL6_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="354" NAME="FSL7_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="355" NAME="FSL7_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="356" MSB="0" NAME="FSL7_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="357" NAME="FSL7_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="358" NAME="FSL7_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="359" NAME="FSL7_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="360" NAME="FSL7_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="361" MSB="0" NAME="FSL7_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="362" NAME="FSL7_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="363" NAME="FSL7_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="364" NAME="FSL8_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="365" NAME="FSL8_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="366" MSB="0" NAME="FSL8_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="367" NAME="FSL8_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="368" NAME="FSL8_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="369" NAME="FSL8_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="370" NAME="FSL8_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="371" MSB="0" NAME="FSL8_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="372" NAME="FSL8_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="373" NAME="FSL8_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="374" NAME="FSL9_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="375" NAME="FSL9_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="376" MSB="0" NAME="FSL9_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="377" NAME="FSL9_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="378" NAME="FSL9_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="379" NAME="FSL9_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="380" NAME="FSL9_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="381" MSB="0" NAME="FSL9_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="382" NAME="FSL9_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="383" NAME="FSL9_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="384" NAME="FSL10_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="385" NAME="FSL10_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="386" MSB="0" NAME="FSL10_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="387" NAME="FSL10_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="388" NAME="FSL10_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="389" NAME="FSL10_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="390" NAME="FSL10_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="391" MSB="0" NAME="FSL10_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="392" NAME="FSL10_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="393" NAME="FSL10_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="394" NAME="FSL11_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="395" NAME="FSL11_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="396" MSB="0" NAME="FSL11_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="397" NAME="FSL11_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="398" NAME="FSL11_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="399" NAME="FSL11_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="400" NAME="FSL11_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="401" MSB="0" NAME="FSL11_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="402" NAME="FSL11_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="403" NAME="FSL11_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="404" NAME="FSL12_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="405" NAME="FSL12_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="406" MSB="0" NAME="FSL12_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="407" NAME="FSL12_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="408" NAME="FSL12_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="409" NAME="FSL12_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="410" NAME="FSL12_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="411" MSB="0" NAME="FSL12_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="412" NAME="FSL12_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="413" NAME="FSL12_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="414" NAME="FSL13_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="415" NAME="FSL13_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="416" MSB="0" NAME="FSL13_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="417" NAME="FSL13_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="418" NAME="FSL13_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="419" NAME="FSL13_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="420" NAME="FSL13_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="421" MSB="0" NAME="FSL13_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="422" NAME="FSL13_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="423" NAME="FSL13_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="424" NAME="FSL14_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="425" NAME="FSL14_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="426" MSB="0" NAME="FSL14_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="427" NAME="FSL14_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="428" NAME="FSL14_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="429" NAME="FSL14_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="430" NAME="FSL14_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="431" MSB="0" NAME="FSL14_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="432" NAME="FSL14_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="433" NAME="FSL14_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="434" NAME="FSL15_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="435" NAME="FSL15_S_READ" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="436" MSB="0" NAME="FSL15_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="437" NAME="FSL15_S_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="438" NAME="FSL15_S_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="439" NAME="FSL15_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="440" NAME="FSL15_M_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="441" MSB="0" NAME="FSL15_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="442" NAME="FSL15_M_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="443" NAME="FSL15_M_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="444" NAME="M0_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="445" MSB="31" NAME="M0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M0_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="446" NAME="M0_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="447" NAME="M0_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="448" NAME="S0_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="449" MSB="31" NAME="S0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S0_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="450" NAME="S0_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="451" NAME="S0_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="452" NAME="M1_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="453" MSB="31" NAME="M1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M1_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="454" NAME="M1_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="455" NAME="M1_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="456" NAME="S1_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="457" MSB="31" NAME="S1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S1_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="458" NAME="S1_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="459" NAME="S1_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="460" NAME="M2_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="461" MSB="31" NAME="M2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M2_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="462" NAME="M2_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="463" NAME="M2_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="464" NAME="S2_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="465" MSB="31" NAME="S2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S2_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="466" NAME="S2_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="467" NAME="S2_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="468" NAME="M3_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="469" MSB="31" NAME="M3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M3_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="470" NAME="M3_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="471" NAME="M3_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="472" NAME="S3_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="473" MSB="31" NAME="S3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S3_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="474" NAME="S3_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="475" NAME="S3_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="476" NAME="M4_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="477" MSB="31" NAME="M4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M4_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="478" NAME="M4_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="479" NAME="M4_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="480" NAME="S4_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="481" MSB="31" NAME="S4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S4_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="482" NAME="S4_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="483" NAME="S4_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="484" NAME="M5_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="485" MSB="31" NAME="M5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M5_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="486" NAME="M5_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="487" NAME="M5_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="488" NAME="S5_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="489" MSB="31" NAME="S5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S5_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="490" NAME="S5_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="491" NAME="S5_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="492" NAME="M6_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="493" MSB="31" NAME="M6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M6_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="494" NAME="M6_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="495" NAME="M6_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="496" NAME="S6_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="497" MSB="31" NAME="S6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S6_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="498" NAME="S6_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="499" NAME="S6_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="500" NAME="M7_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="501" MSB="31" NAME="M7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M7_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="502" NAME="M7_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="503" NAME="M7_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="504" NAME="S7_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="505" MSB="31" NAME="S7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S7_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="506" NAME="S7_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="507" NAME="S7_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="508" NAME="M8_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="509" MSB="31" NAME="M8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M8_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="510" NAME="M8_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="511" NAME="M8_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="512" NAME="S8_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="513" MSB="31" NAME="S8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S8_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="514" NAME="S8_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="515" NAME="S8_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="516" NAME="M9_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="517" MSB="31" NAME="M9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M9_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="518" NAME="M9_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="519" NAME="M9_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="520" NAME="S9_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="521" MSB="31" NAME="S9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S9_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="522" NAME="S9_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="523" NAME="S9_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="524" NAME="M10_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="525" MSB="31" NAME="M10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M10_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="526" NAME="M10_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="527" NAME="M10_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="528" NAME="S10_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="529" MSB="31" NAME="S10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S10_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="530" NAME="S10_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="531" NAME="S10_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="532" NAME="M11_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="533" MSB="31" NAME="M11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M11_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="534" NAME="M11_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="535" NAME="M11_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="536" NAME="S11_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="537" MSB="31" NAME="S11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S11_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="538" NAME="S11_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="539" NAME="S11_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="540" NAME="M12_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="541" MSB="31" NAME="M12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M12_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="542" NAME="M12_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="543" NAME="M12_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="544" NAME="S12_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="545" MSB="31" NAME="S12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S12_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="546" NAME="S12_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="547" NAME="S12_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="548" NAME="M13_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="549" MSB="31" NAME="M13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M13_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="550" NAME="M13_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="551" NAME="M13_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="552" NAME="S13_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="553" MSB="31" NAME="S13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S13_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="554" NAME="S13_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="555" NAME="S13_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="556" NAME="M14_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="557" MSB="31" NAME="M14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M14_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="558" NAME="M14_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="559" NAME="M14_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="560" NAME="S14_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="561" MSB="31" NAME="S14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S14_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="562" NAME="S14_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="563" NAME="S14_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="564" NAME="M15_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="565" MSB="31" NAME="M15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M15_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="566" NAME="M15_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="567" NAME="M15_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="568" NAME="S15_AXIS_TLAST" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="569" MSB="31" NAME="S15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S15_AXIS_DATA_WIDTH-1:0]"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="570" NAME="S15_AXIS_TVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="571" NAME="S15_AXIS_TREADY" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="572" NAME="ICACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="573" NAME="ICACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="574" MSB="0" NAME="ICACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="575" NAME="ICACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="576" NAME="ICACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="577" NAME="ICACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="578" NAME="ICACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="579" MSB="0" NAME="ICACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="580" NAME="ICACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="581" NAME="ICACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="582" NAME="DCACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="583" NAME="DCACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="584" MSB="0" NAME="DCACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="585" NAME="DCACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="586" NAME="DCACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="587" NAME="DCACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="588" NAME="DCACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="589" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="590" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
- <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="591" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
- <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
- <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
- <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
- <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="I" PHYSICAL="RESET"/>
- <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
- <PORTMAP DIR="I" PHYSICAL="DREADY"/>
- <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
- <PORTMAP DIR="I" PHYSICAL="DCE"/>
- <PORTMAP DIR="I" PHYSICAL="DUE"/>
- <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
- <PORTMAP DIR="O" PHYSICAL="D_AS"/>
- <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
- <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
- <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="I" PHYSICAL="RESET"/>
- <PORTMAP DIR="I" PHYSICAL="INSTR"/>
- <PORTMAP DIR="I" PHYSICAL="IREADY"/>
- <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
- <PORTMAP DIR="I" PHYSICAL="ICE"/>
- <PORTMAP DIR="I" PHYSICAL="IUE"/>
- <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
- <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
- <PORTMAP DIR="O" PHYSICAL="I_AS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="2" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="CLK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
- <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
- <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
- <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
- <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
- <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
- <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
- <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
- <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
- <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
- <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" INSTANCE="Ethernet_Lite" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="microblaze_0_intc" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" INSTANCE="MCB_DDR3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="134217728" SIZEABRV="128M">
- <ACCESSROUTE>
- <ROUTEPNT INDEX="0" INSTANCE="axi4_0"/>
- </ACCESSROUTE>
- </MEMRANGE>
- </MEMORYMAP>
- <PERIPHERALS>
- <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/>
- <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/>
- <PERIPHERAL INSTANCE="debug_module"/>
- <PERIPHERAL INSTANCE="RS232_Uart_1"/>
- <PERIPHERAL INSTANCE="LEDs_4Bits"/>
- <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/>
- <PERIPHERAL INSTANCE="Ethernet_Lite"/>
- <PERIPHERAL INSTANCE="axi_timer_0"/>
- <PERIPHERAL INSTANCE="microblaze_0_intc"/>
- <PERIPHERAL INSTANCE="MCB_DDR3"/>
- </PERIPHERALS>
- <INTERRUPTINFO TYPE="TARGET">
- <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
- <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
- <DESCRIPTION>Active High External Reset</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
- <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- </PORTS>
- <BUSINTERFACES/>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
- <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
- <DESCRIPTION>Active High External Reset</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
- <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
- </PORTS>
- <BUSINTERFACES/>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
- <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
- <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x40000000">
- <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
- <DESCRIPTION>Error Correction Code </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Select Interconnect </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
- <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
- <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
- <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
- <DESCRIPTION>Write Access setting </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
- <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
- <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SLMB"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
- <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
- <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
- <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x40000000">
- <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
- <DESCRIPTION>Error Correction Code </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Select Interconnect </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
- <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
- <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
- <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
- <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
- <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
- <DESCRIPTION>Write Access setting </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
- <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
- <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE"/>
- <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
- <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
- <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SLMB"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
- <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000">
- <DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
- <DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
- <DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
- <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
- <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
- <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t">
- <DESCRIPTION>Device Subfamily</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
- <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
- <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>External Reset Active High </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
- <DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
- <PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
- <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
- <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
- <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
- <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
- <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
- <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
- <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
- </IOINTERFACES>
- </MODULE>
- <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
- <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t">
- <DESCRIPTION>Device</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484">
- <DESCRIPTION>Package</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3">
- <DESCRIPTION>Speed Grade</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000">
- <DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="600000000">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Buffered </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="600000000">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0">
- <DESCRIPTION>Required Group </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="100000000">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0">
- <DESCRIPTION>Required Group </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Varaible Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="50000000">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="PLL0">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION> Varaible Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION> Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION> Variable Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Clock Deskew</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Required Phase</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Required Group</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
- <DESCRIPTION>Buffered</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
- <DESCRIPTION>Variable Phase Shift</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
- <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
- <DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET"/>
- <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
- <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
- <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES/>
- </MODULE>
- <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
- <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2">
- <DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2">
- <DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x74800000">
- <DESCRIPTION>Base Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x7480ffff">
- <DESCRIPTION>High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3">
- <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8">
- <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Enable JTAG UART </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocal</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
- <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
- <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_debug_Dbg_Update"/>
- <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_debug_Debug_Rst"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
- <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
- <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
- <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/>
- <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/>
- <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/>
- <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/>
- <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
- <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
- <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
- <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
- <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
- <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
- <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
- <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
- <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
- <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
- <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="SPLB"/>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
- <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
- <DESCRIPTION>AXI Clock Frequency </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200">
- <DESCRIPTION>UART Lite Baud Rate </DESCRIPTION>
- <DESCRIPTION>Baud Rate</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8">
- <DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION>
- <DESCRIPTION>Data Bits</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Use Parity </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Parity Type </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout">
- <DESCRIPTION>Serial Data Out</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin">
- <DESCRIPTION>Serial Data In</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="TX"/>
- <PORTMAP DIR="I" PHYSICAL="RX"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
- <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
- <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
- <DESCRIPTION>GPIO Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
- <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
- <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
- <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
- </PORT>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
- <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
- <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
- <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
- <DESCRIPTION>GPIO Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
- <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
- <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
- <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
- <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
- </PORT>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
- <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
- <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
- <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
- <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
- <DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Spartan-6 memory controller</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="R7"/>
- <PARAMETER MPD_INDEX="3" NAME="C_MCB_PERFORMANCE" TYPE="STRING" VALUE="STANDARD"/>
- <PARAMETER MPD_INDEX="4" NAME="C_BYPASS_CORE_UCF" VALUE="0"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="5" NAME="C_S0_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc0000000"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="6" NAME="C_S0_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc7ffffff"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="7" NAME="C_S1_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="8" NAME="C_S1_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="9" NAME="C_S2_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="10" NAME="C_S2_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="11" NAME="C_S3_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="12" NAME="C_S3_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="13" NAME="C_S4_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="14" NAME="C_S4_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="15" NAME="C_S5_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_S5_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="18" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT41J64M16XX-187E"/>
- <PARAMETER MPD_INDEX="19" NAME="C_MEM_BASEPARTNO" TYPE="STRING" VALUE="NOT_SET"/>
- <PARAMETER MPD_INDEX="20" NAME="C_NUM_DQ_PINS" TYPE="INTEGER" VALUE="16"/>
- <PARAMETER MPD_INDEX="21" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="22" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="23" NAME="C_MEM_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="24" NAME="C_MEM_TRAS" TYPE="INTEGER" VALUE="37500"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="25" NAME="C_MEM_TRCD" TYPE="INTEGER" VALUE="13130"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="26" NAME="C_MEM_TREFI" TYPE="INTEGER" VALUE="7800000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_MEM_TRFC" TYPE="INTEGER" VALUE="160000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_MEM_TRP" TYPE="INTEGER" VALUE="13130"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="29" NAME="C_MEM_TWR" TYPE="INTEGER" VALUE="15000"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="30" NAME="C_MEM_TRTP" TYPE="INTEGER" VALUE="7500"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="31" NAME="C_MEM_TWTR" TYPE="INTEGER" VALUE="7500"/>
- <PARAMETER MPD_INDEX="32" NAME="C_PORT_CONFIG" TYPE="STRING" VALUE="B32_B32_B32_B32"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="33" NAME="C_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="34" NAME="C_SKIP_IN_TERM_CAL_VALUE" TYPE="STRING" VALUE="NONE"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_MEMCLK_PERIOD" TYPE="INTEGER" VALUE="3333"/>
- <PARAMETER MPD_INDEX="36" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="ROW_BANK_COLUMN"/>
- <PARAMETER MPD_INDEX="37" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/>
- <PARAMETER MPD_INDEX="38" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
- <PARAMETER MPD_INDEX="39" NAME="C_SIMULATION" TYPE="STRING" VALUE="FALSE"/>
- <PARAMETER MPD_INDEX="40" NAME="C_MEM_DDR1_2_ODS" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="41" NAME="C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
- <PARAMETER MPD_INDEX="42" NAME="C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
- <PARAMETER MPD_INDEX="43" NAME="C_MEM_DDR2_RTT" TYPE="STRING" VALUE="150OHMS"/>
- <PARAMETER MPD_INDEX="44" NAME="C_MEM_DDR2_DIFF_DQS_EN" TYPE="STRING" VALUE="YES"/>
- <PARAMETER MPD_INDEX="45" NAME="C_MEM_DDR2_3_PA_SR" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="46" NAME="C_MEM_DDR2_3_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/>
- <PARAMETER MPD_INDEX="47" NAME="C_MEM_DDR3_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/>
- <PARAMETER MPD_INDEX="48" NAME="C_MEM_DDR3_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
- <PARAMETER MPD_INDEX="49" NAME="C_MEM_DDR3_ODS" TYPE="STRING" VALUE="DIV6"/>
- <PARAMETER MPD_INDEX="50" NAME="C_MEM_DDR3_RTT" TYPE="STRING" VALUE="DIV4"/>
- <PARAMETER MPD_INDEX="51" NAME="C_MEM_DDR3_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/>
- <PARAMETER MPD_INDEX="52" NAME="C_MEM_MOBILE_PA_SR" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="53" NAME="C_MEM_MDDR_ODS" TYPE="STRING" VALUE="FULL"/>
- <PARAMETER MPD_INDEX="54" NAME="C_ARB_ALGORITHM" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="55" NAME="C_ARB_NUM_TIME_SLOTS" TYPE="INTEGER" VALUE="12"/>
- <PARAMETER MPD_INDEX="56" NAME="C_ARB_TIME_SLOT_0" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="57" NAME="C_ARB_TIME_SLOT_1" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="58" NAME="C_ARB_TIME_SLOT_2" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="59" NAME="C_ARB_TIME_SLOT_3" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER MPD_INDEX="60" NAME="C_ARB_TIME_SLOT_4" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="61" NAME="C_ARB_TIME_SLOT_5" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="62" NAME="C_ARB_TIME_SLOT_6" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="63" NAME="C_ARB_TIME_SLOT_7" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER MPD_INDEX="64" NAME="C_ARB_TIME_SLOT_8" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
- <PARAMETER MPD_INDEX="65" NAME="C_ARB_TIME_SLOT_9" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
- <PARAMETER MPD_INDEX="66" NAME="C_ARB_TIME_SLOT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
- <PARAMETER MPD_INDEX="67" NAME="C_ARB_TIME_SLOT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="68" NAME="C_S0_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="69" NAME="C_S0_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="70" NAME="C_S0_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="71" NAME="C_S0_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="72" NAME="C_S0_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="73" NAME="C_S0_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="74" NAME="C_S0_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="75" NAME="C_S0_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="76" NAME="C_S0_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
- <PARAMETER MPD_INDEX="77" NAME="C_S0_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="78" NAME="C_S0_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="79" NAME="C_S0_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="80" NAME="C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="81" NAME="C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="82" NAME="C_S1_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="83" NAME="C_S1_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="84" NAME="C_S1_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="85" NAME="C_S1_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="86" NAME="C_S1_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="87" NAME="C_S1_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="88" NAME="C_S1_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="89" NAME="C_S1_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="90" NAME="C_S1_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="91" NAME="C_S1_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="92" NAME="C_S1_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="93" NAME="C_S1_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="94" NAME="C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="95" NAME="C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="96" NAME="C_S2_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="97" NAME="C_S2_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="98" NAME="C_S2_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="99" NAME="C_S2_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="100" NAME="C_S2_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="101" NAME="C_S2_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="102" NAME="C_S2_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="103" NAME="C_S2_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="104" NAME="C_S2_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="105" NAME="C_S2_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="106" NAME="C_S2_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="107" NAME="C_S2_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="108" NAME="C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="109" NAME="C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="110" NAME="C_S3_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="111" NAME="C_S3_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="112" NAME="C_S3_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="113" NAME="C_S3_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="114" NAME="C_S3_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="115" NAME="C_S3_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="116" NAME="C_S3_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="117" NAME="C_S3_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="118" NAME="C_S3_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="119" NAME="C_S3_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="120" NAME="C_S3_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="121" NAME="C_S3_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="122" NAME="C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="123" NAME="C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="124" NAME="C_S4_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="125" NAME="C_S4_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="126" NAME="C_S4_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="127" NAME="C_S4_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="128" NAME="C_S4_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="129" NAME="C_S4_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="130" NAME="C_S4_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="131" NAME="C_S4_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="132" NAME="C_S4_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="133" NAME="C_S4_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="134" NAME="C_S4_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="135" NAME="C_S4_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="136" NAME="C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="137" NAME="C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="138" NAME="C_S5_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="139" NAME="C_S5_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
- <PARAMETER MPD_INDEX="140" NAME="C_S5_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="141" NAME="C_S5_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER MPD_INDEX="142" NAME="C_S5_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="143" NAME="C_S5_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_S5_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="145" NAME="C_S5_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="146" NAME="C_S5_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
- <PARAMETER MPD_INDEX="147" NAME="C_S5_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
- <PARAMETER MPD_INDEX="148" NAME="C_S5_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER MPD_INDEX="149" NAME="C_S5_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER MPD_INDEX="150" NAME="C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="151" NAME="C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
- <PARAMETER MPD_INDEX="152" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="153" NAME="C_SYS_RST_PRESENT" TYPE="INTEGER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S0_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" NAME="C_INTERCONNECT_S0_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" NAME="C_INTERCONNECT_S0_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" NAME="C_INTERCONNECT_S0_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S0_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S0_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="17" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="18" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="16" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="26" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="9" MPD_INDEX="12" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="10" MPD_INDEX="11" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
- <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="27" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
- <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="15" LSB="0" MHS_INDEX="12" MPD_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq" VECFORMULA="[C_NUM_DQ_PINS-1:0]"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="13" MPD_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="14" MPD_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="15" MPD_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="16" MPD_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="17" MPD_INDEX="28" NAME="rzq" SIGNAME="rzq"/>
- <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="18" MPD_INDEX="29" NAME="zio" SIGNAME="zio"/>
- <PORT BUS="S0_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="32" NAME="s0_axi_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="30" NAME="ui_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
- <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="0" NAME="sysclk_2x" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
- <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="1" NAME="sysclk_2x_180" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="10" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
- <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="4" NAME="PLL_LOCK" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="2" NAME="pll_ce_0" SIGNAME="__NOC__"/>
- <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="pll_ce_90" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="5" NAME="pll_lock_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="6" NAME="sysclk_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="7" NAME="sysclk_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="8" NAME="pll_ce_0_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="9" NAME="pll_ce_90_bufpll_o" SIGNAME="__NOC__"/>
- <PORT DIR="O" MPD_INDEX="31" NAME="uo_done_cal" SIGNAME="__NOC__"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_aresetn" DIR="I" MPD_INDEX="33" NAME="s0_axi_aresetn" SIGIS="RST" SIGNAME="axi4_0_M_aresetn"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awid" DIR="I" MPD_INDEX="34" NAME="s0_axi_awid" SIGNAME="axi4_0_M_awid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="35" MSB="31" NAME="s0_axi_awaddr" RIGHT="0" SIGNAME="axi4_0_M_awaddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="36" MSB="7" NAME="s0_axi_awlen" RIGHT="0" SIGNAME="axi4_0_M_awlen" VECFORMULA="[7:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="s0_axi_awsize" RIGHT="0" SIGNAME="axi4_0_M_awsize" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="s0_axi_awburst" RIGHT="0" SIGNAME="axi4_0_M_awburst" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlock" DIR="I" MPD_INDEX="39" NAME="s0_axi_awlock" SIGNAME="axi4_0_M_awlock" VECFORMULA="[0:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="40" MSB="3" NAME="s0_axi_awcache" RIGHT="0" SIGNAME="axi4_0_M_awcache" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="s0_axi_awprot" RIGHT="0" SIGNAME="axi4_0_M_awprot" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s0_axi_awqos" RIGHT="0" SIGNAME="axi4_0_M_awqos" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awvalid" DIR="I" MPD_INDEX="43" NAME="s0_axi_awvalid" SIGNAME="axi4_0_M_awvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awready" DIR="O" MPD_INDEX="44" NAME="s0_axi_awready" SIGNAME="axi4_0_M_awready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="s0_axi_wdata" RIGHT="0" SIGNAME="axi4_0_M_wdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s0_axi_wstrb" RIGHT="0" SIGNAME="axi4_0_M_wstrb" VECFORMULA="[((C_S0_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wlast" DIR="I" MPD_INDEX="47" NAME="s0_axi_wlast" SIGNAME="axi4_0_M_wlast"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wvalid" DIR="I" MPD_INDEX="48" NAME="s0_axi_wvalid" SIGNAME="axi4_0_M_wvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wready" DIR="O" MPD_INDEX="49" NAME="s0_axi_wready" SIGNAME="axi4_0_M_wready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bid" DIR="O" MPD_INDEX="50" NAME="s0_axi_bid" SIGNAME="axi4_0_M_bid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="51" MSB="1" NAME="s0_axi_bresp" RIGHT="0" SIGNAME="axi4_0_M_bresp" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bvalid" DIR="O" MPD_INDEX="52" NAME="s0_axi_bvalid" SIGNAME="axi4_0_M_bvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bready" DIR="I" MPD_INDEX="53" NAME="s0_axi_bready" SIGNAME="axi4_0_M_bready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arid" DIR="I" MPD_INDEX="54" NAME="s0_axi_arid" SIGNAME="axi4_0_M_arid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="55" MSB="31" NAME="s0_axi_araddr" RIGHT="0" SIGNAME="axi4_0_M_araddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="56" MSB="7" NAME="s0_axi_arlen" RIGHT="0" SIGNAME="axi4_0_M_arlen" VECFORMULA="[7:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="57" MSB="2" NAME="s0_axi_arsize" RIGHT="0" SIGNAME="axi4_0_M_arsize" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="58" MSB="1" NAME="s0_axi_arburst" RIGHT="0" SIGNAME="axi4_0_M_arburst" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlock" DIR="I" MPD_INDEX="59" NAME="s0_axi_arlock" SIGNAME="axi4_0_M_arlock" VECFORMULA="[0:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="60" MSB="3" NAME="s0_axi_arcache" RIGHT="0" SIGNAME="axi4_0_M_arcache" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="s0_axi_arprot" RIGHT="0" SIGNAME="axi4_0_M_arprot" VECFORMULA="[2:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="62" MSB="3" NAME="s0_axi_arqos" RIGHT="0" SIGNAME="axi4_0_M_arqos" VECFORMULA="[3:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arvalid" DIR="I" MPD_INDEX="63" NAME="s0_axi_arvalid" SIGNAME="axi4_0_M_arvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arready" DIR="O" MPD_INDEX="64" NAME="s0_axi_arready" SIGNAME="axi4_0_M_arready"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rid" DIR="O" MPD_INDEX="65" NAME="s0_axi_rid" SIGNAME="axi4_0_M_rid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="s0_axi_rdata" RIGHT="0" SIGNAME="axi4_0_M_rdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="67" MSB="1" NAME="s0_axi_rresp" RIGHT="0" SIGNAME="axi4_0_M_rresp" VECFORMULA="[1:0]"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rlast" DIR="O" MPD_INDEX="68" NAME="s0_axi_rlast" SIGNAME="axi4_0_M_rlast"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rvalid" DIR="O" MPD_INDEX="69" NAME="s0_axi_rvalid" SIGNAME="axi4_0_M_rvalid"/>
- <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rready" DIR="I" MPD_INDEX="70" NAME="s0_axi_rready" SIGNAME="axi4_0_M_rready"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="71" NAME="s1_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="s1_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="73" MSB="3" NAME="s1_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="74" MSB="31" NAME="s1_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="75" MSB="7" NAME="s1_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="76" MSB="2" NAME="s1_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="s1_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="s1_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="s1_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="80" MSB="2" NAME="s1_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="s1_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="s1_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="83" NAME="s1_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="84" MSB="31" NAME="s1_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="85" MSB="3" NAME="s1_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S1_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="86" NAME="s1_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="s1_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="s1_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="89" MSB="3" NAME="s1_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="90" MSB="1" NAME="s1_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="s1_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="92" NAME="s1_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="s1_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="s1_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="95" MSB="7" NAME="s1_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="96" MSB="2" NAME="s1_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="97" MSB="1" NAME="s1_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="s1_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="s1_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="100" MSB="2" NAME="s1_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="101" MSB="3" NAME="s1_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="s1_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="s1_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="104" MSB="3" NAME="s1_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="105" MSB="31" NAME="s1_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="106" MSB="1" NAME="s1_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="s1_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="s1_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="s1_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="110" NAME="s2_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="111" NAME="s2_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="112" MSB="3" NAME="s2_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="113" MSB="31" NAME="s2_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="s2_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="s2_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="116" MSB="1" NAME="s2_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="117" NAME="s2_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="118" MSB="3" NAME="s2_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="119" MSB="2" NAME="s2_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="120" MSB="3" NAME="s2_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="121" NAME="s2_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="s2_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="123" MSB="31" NAME="s2_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="124" MSB="3" NAME="s2_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S2_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="125" NAME="s2_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="126" NAME="s2_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="s2_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="128" MSB="3" NAME="s2_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="s2_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="130" NAME="s2_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="131" NAME="s2_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="132" MSB="3" NAME="s2_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="133" MSB="31" NAME="s2_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="s2_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="135" MSB="2" NAME="s2_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="136" MSB="1" NAME="s2_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="137" NAME="s2_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="138" MSB="3" NAME="s2_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="139" MSB="2" NAME="s2_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="140" MSB="3" NAME="s2_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="141" NAME="s2_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="s2_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="143" MSB="3" NAME="s2_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="144" MSB="31" NAME="s2_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="145" MSB="1" NAME="s2_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="146" NAME="s2_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="147" NAME="s2_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="148" NAME="s2_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="149" NAME="s3_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="150" NAME="s3_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="s3_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="s3_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="153" MSB="7" NAME="s3_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="154" MSB="2" NAME="s3_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="155" MSB="1" NAME="s3_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="156" NAME="s3_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="157" MSB="3" NAME="s3_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="158" MSB="2" NAME="s3_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="159" MSB="3" NAME="s3_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="160" NAME="s3_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="161" NAME="s3_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="162" MSB="31" NAME="s3_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="163" MSB="3" NAME="s3_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S3_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="164" NAME="s3_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="165" NAME="s3_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="166" NAME="s3_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="167" MSB="3" NAME="s3_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="168" MSB="1" NAME="s3_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="169" NAME="s3_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="170" NAME="s3_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="171" MSB="3" NAME="s3_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="s3_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="173" MSB="7" NAME="s3_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="174" MSB="2" NAME="s3_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="175" MSB="1" NAME="s3_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="176" NAME="s3_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="177" MSB="3" NAME="s3_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="178" MSB="2" NAME="s3_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="179" MSB="3" NAME="s3_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="180" NAME="s3_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="181" NAME="s3_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="182" MSB="3" NAME="s3_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="s3_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="184" MSB="1" NAME="s3_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="185" NAME="s3_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="186" NAME="s3_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="187" NAME="s3_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="188" NAME="s4_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="189" NAME="s4_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="190" MSB="3" NAME="s4_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="s4_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="192" MSB="7" NAME="s4_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="193" MSB="2" NAME="s4_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="194" MSB="1" NAME="s4_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="195" NAME="s4_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="196" MSB="3" NAME="s4_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="197" MSB="2" NAME="s4_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="198" MSB="3" NAME="s4_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="199" NAME="s4_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="200" NAME="s4_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="s4_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="202" MSB="3" NAME="s4_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S4_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="203" NAME="s4_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="204" NAME="s4_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="205" NAME="s4_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="206" MSB="3" NAME="s4_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="207" MSB="1" NAME="s4_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="208" NAME="s4_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="209" NAME="s4_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="s4_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="211" MSB="31" NAME="s4_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="212" MSB="7" NAME="s4_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="213" MSB="2" NAME="s4_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="214" MSB="1" NAME="s4_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="215" NAME="s4_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="216" MSB="3" NAME="s4_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="217" MSB="2" NAME="s4_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="218" MSB="3" NAME="s4_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="219" NAME="s4_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="220" NAME="s4_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="221" MSB="3" NAME="s4_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="222" MSB="31" NAME="s4_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="s4_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="224" NAME="s4_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="225" NAME="s4_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="226" NAME="s4_axi_rready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="227" NAME="s5_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="228" NAME="s5_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="229" MSB="3" NAME="s5_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="230" MSB="31" NAME="s5_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="231" MSB="7" NAME="s5_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="232" MSB="2" NAME="s5_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="233" MSB="1" NAME="s5_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="234" NAME="s5_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="s5_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="236" MSB="2" NAME="s5_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="237" MSB="3" NAME="s5_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="238" NAME="s5_axi_awvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="239" NAME="s5_axi_awready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="s5_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="241" MSB="3" NAME="s5_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S5_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="242" NAME="s5_axi_wlast" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="243" NAME="s5_axi_wvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="244" NAME="s5_axi_wready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="245" MSB="3" NAME="s5_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="246" MSB="1" NAME="s5_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="247" NAME="s5_axi_bvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="248" NAME="s5_axi_bready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="249" MSB="3" NAME="s5_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="250" MSB="31" NAME="s5_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="251" MSB="7" NAME="s5_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="252" MSB="2" NAME="s5_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="253" MSB="1" NAME="s5_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="s5_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="255" MSB="3" NAME="s5_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="256" MSB="2" NAME="s5_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="257" MSB="3" NAME="s5_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="s5_axi_arvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="259" NAME="s5_axi_arready" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="260" MSB="3" NAME="s5_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="261" MSB="31" NAME="s5_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="262" MSB="1" NAME="s5_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="s5_axi_rlast" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="s5_axi_rvalid" SIGNAME="__NOC__"/>
- <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="265" NAME="s5_axi_rready" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S0_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s0_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s0_axi_rready"/>
- </PORTMAPS>
- <MASTERS>
- <MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
- <MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
- </MASTERS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S1_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s1_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s1_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="2" NAME="S2_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s2_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s2_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S3_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s3_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s3_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="4" NAME="S4_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s4_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s4_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="5" NAME="S5_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_aclk"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_aresetn"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awaddr"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awlen"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awsize"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awburst"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awlock"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awcache"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awprot"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awqos"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_awvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_awready"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wdata"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wstrb"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wlast"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_wvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_wready"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bresp"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_bvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_bready"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_araddr"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arlen"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arsize"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arburst"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arlock"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arcache"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arprot"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arqos"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_arvalid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_arready"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rid"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rdata"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rresp"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rlast"/>
- <PORTMAP DIR="O" PHYSICAL="s5_axi_rvalid"/>
- <PORTMAP DIR="I" PHYSICAL="s5_axi_rready"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
- <PORTMAPS>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/>
- <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/>
- <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/>
- <PORTMAP DIR="IO" PHYSICAL="rzq"/>
- <PORTMAP DIR="IO" PHYSICAL="zio"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M">
- <SLAVES>
- <SLAVE BUSINTERFACE="S0_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S1_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S1_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S1_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S2_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S2_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S2_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S3_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S3_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S3_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S4_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S4_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S4_AXI"/>
- </SLAVES>
- </MEMRANGE>
- <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S5_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S5_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
- <SLAVES>
- <SLAVE BUSINTERFACE="S5_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- </MODULE>
- <MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
- <DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE">
- <DESCRIPTION>AXI protocol selection </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40e00000">
- <DESCRIPTION>Ethernetlite Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x40e0ffff">
- <DESCRIPTION>Ethernetlite High Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_S_AXI_ACLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000">
- <DESCRIPTION>AXI System Clock Period </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Interface Addresses Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Interface Data Width </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="7" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Width of ID Bus on AXI4 </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="8" NAME="C_INCLUDE_MDIO" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Include MII Management Module</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_INCLUDE_GLOBAL_BUFFERS" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Include Global Buffers for PHY clocks</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_INCLUDE_INTERNAL_LOOPBACK" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Include Internal Loopback</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_DUPLEX" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Duplex Mode </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="12" NAME="C_TX_PING_PONG" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Include Second Transmitter Buffer </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="13" NAME="C_RX_PING_PONG" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Include Second Receiver Buffer </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_INCLUDE_PHY_CONSTRAINTS" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Include PHY I/O Constraints </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Interconnect write acceptance </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="16" NAME="C_INTERCONNECT_S_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Interconnect read acceptance </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="17" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Support Narrow Burst on AXI4 </DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="IO" IOS="ethernet_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="48" NAME="PHY_MDIO" SIGNAME="Ethernet_Lite_MDIO" TRI_I="PHY_MDIO_I" TRI_O="PHY_MDIO_O" TRI_T="PHY_MDIO_T">
- <DESCRIPTION>Ethernet PHY Management Data</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="44" NAME="PHY_MDC" SIGNAME="Ethernet_Lite_MDC">
- <DESCRIPTION>Ethernet PHY Management Clock</DESCRIPTION>
- </PORT>
- <PORT DIR="O" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="43" MSB="3" NAME="PHY_tx_data" RIGHT="0" SIGNAME="Ethernet_Lite_TXD" VECFORMULA="[3:0]">
- <DESCRIPTION>Ethernet Transmit Data Output</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="42" NAME="PHY_tx_en" SIGNAME="Ethernet_Lite_TX_EN">
- <DESCRIPTION>Ethernet Transmit Enable</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="34" NAME="PHY_tx_clk" SIGNAME="Ethernet_Lite_TX_CLK">
- <DESCRIPTION>Ethernet Transmit Clock Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="39" NAME="PHY_col" SIGNAME="Ethernet_Lite_COL">
- <DESCRIPTION>Ethernet Collision Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="6" MPD_INDEX="38" MSB="3" NAME="PHY_rx_data" RIGHT="0" SIGNAME="Ethernet_Lite_RXD" VECFORMULA="[3:0]">
- <DESCRIPTION>Ethernet Receive Data Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="40" NAME="PHY_rx_er" SIGNAME="Ethernet_Lite_RX_ER">
- <DESCRIPTION>Ethernet Receive Error Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="35" NAME="PHY_rx_clk" SIGNAME="Ethernet_Lite_RX_CLK">
- <DESCRIPTION>Ethernet Receive Clock Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="36" NAME="PHY_crs" SIGNAME="Ethernet_Lite_CRS">
- <DESCRIPTION>Ethernet Carrier Sense Input</DESCRIPTION>
- </PORT>
- <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="37" NAME="PHY_dv" SIGNAME="Ethernet_Lite_RX_DV">
- <DESCRIPTION>Ethernet Receive Data Valid</DESCRIPTION>
- </PORT>
- <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="41" NAME="PHY_rst_n" SIGNAME="Ethernet_Lite_PHY_RST_N">
- <DESCRIPTION>Ethernet PHY Reset</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="2" NAME="IP2INTC_Irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="5" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="6" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="10" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="11" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="I" MPD_INDEX="13" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_M_WLAST"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BID" DIR="O" MPD_INDEX="16" NAME="S_AXI_BID" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[7:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[2:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[3:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="26" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="27" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RID" DIR="O" MPD_INDEX="28" NAME="S_AXI_RID" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="O" MPD_INDEX="31" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_M_RLAST"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="32" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="33" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- <PORT DIR="I" IOS="ethernet_0" MPD_INDEX="45" NAME="PHY_MDIO_I" SIGNAME="__NOC__"/>
- <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="46" NAME="PHY_MDIO_O" SIGNAME="__NOC__"/>
- <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="47" NAME="PHY_MDIO_T" SIGNAME="__NOC__"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <IOINTERFACES>
- <IOINTERFACE MPD_INDEX="0" NAME="ethernet_0" TYPE="XIL_AXIETHERNET_V1">
- <PORTMAPS>
- <PORTMAP DIR="IO" PHYSICAL="PHY_MDIO"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDC"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_tx_data"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_tx_en"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_tx_clk"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_col"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_data"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_er"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_rx_clk"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_crs"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_dv"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_rst_n"/>
- <PORTMAP DIR="I" PHYSICAL="PHY_MDIO_I"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_O"/>
- <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_T"/>
- </PORTMAPS>
- </IOINTERFACE>
- </IOINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
- <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
- <DESCRIPTION>Count Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
- <DESCRIPTION>Only One Timer is present</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>GEN0 Active Level</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>GEN1 Active Level</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41c00000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x41c0ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_Interrupt"/>
- <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
- <DESCRIPTION>Capture Trig 0</DESCRIPTION>
- </PORT>
- <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
- <DESCRIPTION>Capture Trig 1</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
- <DESCRIPTION>Generate Out 0</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
- <DESCRIPTION>Generate Out 1</DESCRIPTION>
- </PORT>
- <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
- <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
- </PORT>
- <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
- <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
- <DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION>
- <DOCUMENTATION>
- <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
- </DOCUMENTATION>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
- <PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
- <DESCRIPTION>Device Family</DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000">
- <DESCRIPTION>AXI Base Address </DESCRIPTION>
- </PARAMETER>
- <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff">
- <DESCRIPTION>AXI High Address</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Address Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
- <DESCRIPTION>AXI Data Width</DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="4">
- <DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111110111">
- <DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
- <DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION>
- </PARAMETER>
- <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
- <DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Support IPR </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Support SIE </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Support CIE </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>Support IVR </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1">
- <DESCRIPTION>IRQ Output Use Level </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
- <DESCRIPTION>The Sense of IRQ Output </DESCRIPTION>
- </PARAMETER>
- <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
- <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
- </PARAMETER>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
- <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="20" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt">
- <DESCRIPTION>Interrupt Request Output</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
- <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="3" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
- <SIGNALS>
- <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <SIGNAL NAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <SIGNAL NAME="axi_timer_0_Interrupt"/>
- <SIGNAL NAME="RS232_Uart_1_Interrupt"/>
- </SIGNALS>
- <DESCRIPTION>Interrupt Inputs</DESCRIPTION>
- </PORT>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
- <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
- <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
- <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
- <SLAVES>
- <SLAVE BUSINTERFACE="S_AXI"/>
- </SLAVES>
- </MEMRANGE>
- </MEMORYMAP>
- <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
- <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="0" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="1" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <SOURCE INSTANCE="axi_timer_0" PRIORITY="2" SIGNAME="axi_timer_0_Interrupt"/>
- <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="3" SIGNAME="RS232_Uart_1_Interrupt"/>
- <TARGET INSTANCE="microblaze_0"/>
- </INTERRUPTINFO>
- </MODULE>
- </MODULES>
-
-</EDKSYSTEM>
\ No newline at end of file
+++ /dev/null
-// BMM LOC annotation file.\r
-//\r
-// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010\r
-// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.\r
-\r
-\r
-///////////////////////////////////////////////////////////////////////////////\r
-//\r
-// Processor 'microblaze_0', ID 100, memory map.\r
-//\r
-///////////////////////////////////////////////////////////////////////////////\r
-\r
-ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100\r
-\r
-\r
- ///////////////////////////////////////////////////////////////////////////////\r
- //\r
- // Processor 'microblaze_0' address space 'microblaze_0_bram_block_combined' 0x00000000:0x00001FFF (8 KBytes).\r
- //\r
- ///////////////////////////////////////////////////////////////////////////////\r
-\r
- ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF]\r
- BUS_BLOCK\r
- microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X1Y30;\r
- microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X1Y32;\r
- microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X0Y30;\r
- microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X0Y32;\r
- END_BUS_BLOCK;\r
- END_ADDRESS_SPACE;\r
-\r
-END_ADDRESS_MAP;\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
-<?fileVersion 4.0.0?>\r
-\r
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
- <storageModule moduleId="org.eclipse.cdt.core.settings">\r
- <cconfiguration id="xilinx.gnu.mb.exe.debug.1890710697.1551842913">\r
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.debug.1890710697.1551842913" moduleId="org.eclipse.cdt.core.settings" name="Blilnky">\r
- <externalSettings/>\r
- <extensions>\r
- <extension id="com.xilinx.sdk.managedbuilder.XELF.mb" point="org.eclipse.cdt.core.BinaryParser"/>\r
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
- </extensions>\r
- </storageModule>\r
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Very simple starter example" id="xilinx.gnu.mb.exe.debug.1890710697.1551842913" name="Blilnky" parent="xilinx.gnu.mb.exe.debug">\r
- <folderInfo id="xilinx.gnu.mb.exe.debug.1890710697.1551842913." name="/" resourcePath="">\r
- <toolChain id="xilinx.gnu.mb.exe.debug.toolchain.257341927" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.debug.toolchain">\r
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.debug.424447469" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.debug"/>\r
- <builder buildPath="${workspace_loc:/RTOSDemoSource/Debug}" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.debug.930852495" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.mb.toolchain.builder.debug"/>\r
- <tool id="xilinx.gnu.mb.c.toolchain.assembler.debug.978073207" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.debug">\r
- <option id="xilinx.gnu.mb.assembler.usele.2022235394" name="Produce little endian code (-mlittle-endian)" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>\r
- <inputType id="xilinx.gnu.assembler.input.278099745" superClass="xilinx.gnu.assembler.input"/>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.c.toolchain.compiler.debug.835271198" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.debug">\r
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.716987775" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>\r
- <option id="xilinx.gnu.compiler.option.debugging.level.1945788166" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.mbversion.96719191" name="MicroBlaze Version" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usele.706567309" name="Produce little endian code (-mlittle-endian)" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1579209203" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1892830682" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usediv.441061894" name="Use hardware divider (-mno-xl-soft-div)" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.fpu.889919540" name="FPU" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.mul.769937239" name="Hardware Multiplier" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.702422111" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
- <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/include"/>\r
- </option>\r
- <option id="xilinx.gnu.compiler.dircategory.includes.788537379" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/netif/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/lwIP_Apps/apps/httpserver_raw}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/lwIP_Apps}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/include/ipv4}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Demo_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/MicroBlazeV8}""/>\r
- </option>\r
- <option id="xilinx.gnu.compiler.symbols.defined.522894226" name="Defined symbols (-D)" superClass="xilinx.gnu.compiler.symbols.defined"/>\r
- <inputType id="xilinx.gnu.compiler.input.264309084" name="C source files" superClass="xilinx.gnu.compiler.input"/>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.cxx.toolchain.compiler.debug.1757864406" name="MicroBlaze g++ compiler" superClass="xilinx.gnu.mb.cxx.toolchain.compiler.debug">\r
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1341113404" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>\r
- <option id="xilinx.gnu.compiler.option.debugging.level.437017279" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.mbversion.73247828" name="MicroBlaze Version" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usele.1996765397" name="Produce little endian code (-mlittle-endian)" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1004904872" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.2102491479" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usediv.1878612258" name="Use hardware divider (-mno-xl-soft-div)" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.fpu.548710489" name="FPU" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.mul.901018577" name="Hardware Multiplier" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.579575146" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
- <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/include"/>\r
- </option>\r
- <option id="xilinx.gnu.compiler.dircategory.includes.877153321" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/netif/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/lwIP_Apps/apps/httpserver_raw}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/lwIP_Apps}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/include/ipv4}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Demo_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/MicroBlazeV8}""/>\r
- </option>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.toolchain.archiver.1048677661" name="MicroBlaze archiver" superClass="xilinx.gnu.mb.toolchain.archiver"/>\r
- <tool id="xilinx.gnu.mb.c.toolchain.linker.debug.1152738454" name="MicroBlaze gcc linker" superClass="xilinx.gnu.mb.c.toolchain.linker.debug">\r
- <option id="xilinx.gnu.mb.linker.inferred.mbversion.1959093628" name="MicroBlaze Version" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="8.10.a" valueType="string"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usele.1271633588" name="Produce little endian artifacts (-mlittle-endian)" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usebarrel.1223851799" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usepcmp.1132489905" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usediv.7712425" name="Use hardware divider (-mno-xl-soft-div)" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.fpu.563163194" name="FPU" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.mul.1195982521" name="Hardware Multiplier" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>\r
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.989668099" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">\r
- <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/lib"/>\r
- </option>\r
- <option id="xilinx.gnu.c.linker.option.lscript.176750025" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>\r
- <option id="xilinx.gnu.c.link.option.ldflags.1590675094" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value="" valueType="string"/>\r
- <inputType id="xilinx.gnu.linker.input.384537517" superClass="xilinx.gnu.linker.input">\r
- <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
- <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
- </inputType>\r
- <inputType id="xilinx.gnu.linker.input.lscript.728905130" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.cxx.toolchain.linker.debug.1026703573" name="MicroBlaze g++ linker" superClass="xilinx.gnu.mb.cxx.toolchain.linker.debug">\r
- <option id="xilinx.gnu.mb.linker.inferred.mbversion.1521662887" name="MicroBlaze Version" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="8.10.a" valueType="string"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usele.304488947" name="Produce little endian artifacts (-mlittle-endian)" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usebarrel.1307373804" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usepcmp.972908817" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usediv.1587557455" name="Use hardware divider (-mno-xl-soft-div)" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.fpu.186398214" name="FPU" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.mul.1765763083" name="Hardware Multiplier" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>\r
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.771165792" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">\r
- <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/lib"/>\r
- </option>\r
- <option id="xilinx.gnu.c.linker.option.lscript.664782973" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>\r
- <option id="xilinx.gnu.c.link.option.ldflags.1516959028" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value="" valueType="string"/>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.size.debug.778946449" name="MicroBlaze Print Size" superClass="xilinx.gnu.mb.size.debug"/>\r
- <tool id="xilinx.elfcheck.mb.debug.225695907" name="Xilinx ELF Check" superClass="xilinx.elfcheck.mb.debug">\r
- <option id="xilinx.elfcheck.option.hwspec.581017009" name="Hardware Specification" superClass="xilinx.elfcheck.option.hwspec" value="-hw ../../HardwareWithEthernetLite/system.xml" valueType="string"/>\r
- <option id="xilinx.elfcheck.option.procname.479774108" name="Processor Name" superClass="xilinx.elfcheck.option.procname" value="-pe microblaze_0" valueType="string"/>\r
- </tool>\r
- </toolChain>\r
- </folderInfo>\r
- <sourceEntries>\r
- <entry excluding="lwIP|lwIP/lwIP_Apps/apps/httpserver_raw/fsdata.c|serial.c|src/testperiph.c|ParTest.c|src/xuartlite_selftest_example.c|src/xtmrctr_selftest_example.c|src/xtmrctr_intr_example.c|src/xintc_tapp_example.c|src/xgpio_tapp_example.c|src/xgpio_intr_tapp_example.c|src/xemaclite_polled_example.c|src/xemaclite_intr_example.c|Demo_Source|RegisterTests.c|main-full.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
- </sourceEntries>\r
- </configuration>\r
- </storageModule>\r
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
- <storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>\r
- <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>\r
- <storageModule moduleId="scannerConfiguration">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1186286811;xilinx.gnu.mb.exe.release.1186286811.">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697;xilinx.gnu.mb.exe.debug.1890710697.">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697.1551842913;xilinx.gnu.mb.exe.debug.1890710697.1551842913.">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697.1551842913;xilinx.gnu.mb.exe.debug.1890710697.1551842913.;xilinx.gnu.mb.c.toolchain.compiler.debug.835271198;xilinx.gnu.compiler.input.264309084">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697;xilinx.gnu.mb.exe.debug.1890710697.;xilinx.gnu.mb.c.toolchain.compiler.debug.1867440614;xilinx.gnu.compiler.input.2107818916">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1186286811;xilinx.gnu.mb.exe.release.1186286811.;xilinx.gnu.mb.c.toolchain.compiler.release.1828722124;xilinx.gnu.compiler.input.690911521">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- </storageModule>\r
- </cconfiguration>\r
- <cconfiguration id="xilinx.gnu.mb.exe.debug.1890710697.1391169017">\r
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.debug.1890710697.1391169017" moduleId="org.eclipse.cdt.core.settings" name="Full">\r
- <externalSettings/>\r
- <extensions>\r
- <extension id="com.xilinx.sdk.managedbuilder.XELF.mb" point="org.eclipse.cdt.core.BinaryParser"/>\r
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
- </extensions>\r
- </storageModule>\r
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Comprehensive example" id="xilinx.gnu.mb.exe.debug.1890710697.1391169017" name="Full" parent="xilinx.gnu.mb.exe.debug">\r
- <folderInfo id="xilinx.gnu.mb.exe.debug.1890710697.1391169017." name="/" resourcePath="">\r
- <toolChain id="xilinx.gnu.mb.exe.debug.toolchain.1065681176" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.debug.toolchain">\r
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.debug.472412552" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.debug"/>\r
- <builder buildPath="${workspace_loc:/RTOSDemoSource/Debug}" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.debug.2034661333" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.mb.toolchain.builder.debug"/>\r
- <tool id="xilinx.gnu.mb.c.toolchain.assembler.debug.1663720311" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.debug">\r
- <option id="xilinx.gnu.mb.assembler.usele.787661810" name="Produce little endian code (-mlittle-endian)" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.both.asm.option.include.paths.67817492" name="Include Paths (-I)" superClass="xilinx.gnu.both.asm.option.include.paths" valueType="includePath">\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>\r
- </option>\r
- <inputType id="xilinx.gnu.assembler.input.828396103" superClass="xilinx.gnu.assembler.input"/>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.c.toolchain.compiler.debug.1610218702" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.debug">\r
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.116271748" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" value="gnu.c.optimization.level.none" valueType="enumerated"/>\r
- <option id="xilinx.gnu.compiler.option.debugging.level.171855055" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.mbversion.900759104" name="MicroBlaze Version" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usele.366091388" name="Produce little endian code (-mlittle-endian)" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1212298558" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1277381811" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usediv.192502540" name="Use hardware divider (-mno-xl-soft-div)" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.fpu.2033157740" name="FPU" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.mul.2087417140" name="Hardware Multiplier" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.729428302" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
- <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/include"/>\r
- </option>\r
- <option id="xilinx.gnu.compiler.dircategory.includes.1539819216" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/netif/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/lwIP_Apps/apps/httpserver_raw}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/lwIP_Apps}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/include/ipv4}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Demo_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/MicroBlazeV8}""/>\r
- </option>\r
- <option id="xilinx.gnu.compiler.misc.other.1660455181" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -fno-strict-aliasing -Wextra" valueType="string"/>\r
- <option id="xilinx.gnu.compiler.option.warnings.pedantic.86490975" name="Pedantic (-pedantic)" superClass="xilinx.gnu.compiler.option.warnings.pedantic" value="false" valueType="boolean"/>\r
- <inputType id="xilinx.gnu.compiler.input.505106416" name="C source files" superClass="xilinx.gnu.compiler.input"/>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.cxx.toolchain.compiler.debug.2087155544" name="MicroBlaze g++ compiler" superClass="xilinx.gnu.mb.cxx.toolchain.compiler.debug">\r
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.76035929" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>\r
- <option id="xilinx.gnu.compiler.option.debugging.level.830648985" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.mbversion.1609359386" name="MicroBlaze Version" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usele.777715972" name="Produce little endian code (-mlittle-endian)" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1922242390" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.75463556" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.usediv.1698265058" name="Use hardware divider (-mno-xl-soft-div)" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.fpu.1268286956" name="FPU" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.compiler.inferred.mul.147816156" name="Hardware Multiplier" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1260701076" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
- <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/include"/>\r
- </option>\r
- <option id="xilinx.gnu.compiler.dircategory.includes.747654423" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/netif/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/lwIP_Apps/apps/httpserver_raw}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/lwIP_Apps}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/lwIP/include/ipv4}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Demo_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/MicroBlazeV8}""/>\r
- </option>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.toolchain.archiver.1361288263" name="MicroBlaze archiver" superClass="xilinx.gnu.mb.toolchain.archiver"/>\r
- <tool id="xilinx.gnu.mb.c.toolchain.linker.debug.512205974" name="MicroBlaze gcc linker" superClass="xilinx.gnu.mb.c.toolchain.linker.debug">\r
- <option id="xilinx.gnu.mb.linker.inferred.mbversion.88071915" name="MicroBlaze Version" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="8.10.a" valueType="string"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usele.2098428761" name="Produce little endian artifacts (-mlittle-endian)" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usebarrel.337502401" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usepcmp.1186226796" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usediv.694766114" name="Use hardware divider (-mno-xl-soft-div)" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.fpu.1355435021" name="FPU" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.mul.1335029834" name="Hardware Multiplier" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>\r
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1334512887" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">\r
- <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/lib"/>\r
- </option>\r
- <option id="xilinx.gnu.c.linker.option.lscript.1073578867" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>\r
- <option id="xilinx.gnu.c.link.option.ldflags.471396681" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value="" valueType="string"/>\r
- <option id="xilinx.gnu.c.link.option.other.791541632" name="Other options (-XLinker [option])" superClass="xilinx.gnu.c.link.option.other"/>\r
- <inputType id="xilinx.gnu.linker.input.1399699093" superClass="xilinx.gnu.linker.input">\r
- <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
- <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
- </inputType>\r
- <inputType id="xilinx.gnu.linker.input.lscript.751524851" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.cxx.toolchain.linker.debug.2073868051" name="MicroBlaze g++ linker" superClass="xilinx.gnu.mb.cxx.toolchain.linker.debug">\r
- <option id="xilinx.gnu.mb.linker.inferred.mbversion.563798700" name="MicroBlaze Version" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="8.10.a" valueType="string"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usele.143230105" name="Produce little endian artifacts (-mlittle-endian)" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usebarrel.1356384257" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usepcmp.1766995151" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.usediv.1611022077" name="Use hardware divider (-mno-xl-soft-div)" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.fpu.484719747" name="FPU" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>\r
- <option id="xilinx.gnu.mb.linker.inferred.mul.494988599" name="Hardware Multiplier" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>\r
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1681875689" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">\r
- <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/lib"/>\r
- </option>\r
- <option id="xilinx.gnu.c.linker.option.lscript.480905448" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>\r
- <option id="xilinx.gnu.c.link.option.ldflags.548655668" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value="" valueType="string"/>\r
- </tool>\r
- <tool id="xilinx.gnu.mb.size.debug.536351174" name="MicroBlaze Print Size" superClass="xilinx.gnu.mb.size.debug"/>\r
- <tool id="xilinx.elfcheck.mb.debug.1281142255" name="Xilinx ELF Check" superClass="xilinx.elfcheck.mb.debug">\r
- <option id="xilinx.elfcheck.option.hwspec.1602098677" name="Hardware Specification" superClass="xilinx.elfcheck.option.hwspec" value="-hw ../../HardwareWithEthernetLite/system.xml" valueType="string"/>\r
- <option id="xilinx.elfcheck.option.procname.1990677201" name="Processor Name" superClass="xilinx.elfcheck.option.procname" value="-pe microblaze_0" valueType="string"/>\r
- </tool>\r
- </toolChain>\r
- </folderInfo>\r
- <sourceEntries>\r
- <entry excluding="lwIP/lwIP_Apps/apps/httpserver_raw/fsdata.c|src/xuartlite_selftest_example.c|src/xtmrctr_selftest_example.c|src/xtmrctr_intr_example.c|src/xintc_tapp_example.c|src/xgpio_tapp_example.c|src/xgpio_intr_tapp_example.c|src/xemaclite_polled_example.c|src/xemaclite_intr_example.c|src/testperiph.c|main-blinky.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
- </sourceEntries>\r
- </configuration>\r
- </storageModule>\r
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
- <storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>\r
- <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>\r
- <storageModule moduleId="scannerConfiguration">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1186286811;xilinx.gnu.mb.exe.release.1186286811.">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697;xilinx.gnu.mb.exe.debug.1890710697.">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697.1551842913;xilinx.gnu.mb.exe.debug.1890710697.1551842913.">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697.1551842913;xilinx.gnu.mb.exe.debug.1890710697.1551842913.;xilinx.gnu.mb.c.toolchain.compiler.debug.835271198;xilinx.gnu.compiler.input.264309084">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697;xilinx.gnu.mb.exe.debug.1890710697.;xilinx.gnu.mb.c.toolchain.compiler.debug.1867440614;xilinx.gnu.compiler.input.2107818916">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1186286811;xilinx.gnu.mb.exe.release.1186286811.;xilinx.gnu.mb.c.toolchain.compiler.release.1828722124;xilinx.gnu.compiler.input.690911521">\r
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
- <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="makefileGenerator">\r
- <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
- <buildOutputProvider>\r
- <openAction enabled="true" filePath=""/>\r
- <parser enabled="true"/>\r
- </buildOutputProvider>\r
- <scannerInfoProvider id="specsFile">\r
- <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
- <parser enabled="true"/>\r
- </scannerInfoProvider>\r
- </profile>\r
- </scannerConfigBuildInfo>\r
- </storageModule>\r
- </cconfiguration>\r
- </storageModule>\r
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
- <project id="RTOSDemoSource.xilinx.gnu.mb.exe.1831715756" name="Xilinx MicroBlaze Executable" projectType="xilinx.gnu.mb.exe"/>\r
- </storageModule>\r
-</cproject>\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>\r
-<projectDescription>\r
- <name>RTOSDemo</name>\r
- <comment></comment>\r
- <projects>\r
- <project>StandAloneBSP</project>\r
- <project>RTOSDemoBSP</project>\r
- </projects>\r
- <buildSpec>\r
- <buildCommand>\r
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
- <arguments>\r
- <dictionary>\r
- <key>?name?</key>\r
- <value></value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.append_environment</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
- <value>all</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.buildArguments</key>\r
- <value></value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.buildCommand</key>\r
- <value>make</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.buildLocation</key>\r
- <value>${workspace_loc:/RTOSDemoSource/Debug}</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
- <value>clean</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.contents</key>\r
- <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
- <value>all</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.stopOnError</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
- <value>true</value>\r
- </dictionary>\r
- </arguments>\r
- </buildCommand>\r
- <buildCommand>\r
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
- <triggers>full,incremental,</triggers>\r
- <arguments>\r
- </arguments>\r
- </buildCommand>\r
- </buildSpec>\r
- <natures>\r
- <nature>org.eclipse.cdt.core.cnature</nature>\r
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
- </natures>\r
-</projectDescription>\r
+++ /dev/null
-REM This file should be executed from the command line prior to the first\r
-REM build. It will be necessary to refresh the Eclipse project once the\r
-REM .bat file has been executed (normally just press F5 to refresh).\r
-\r
-REM Copies all the required files from their location within the standard\r
-REM FreeRTOS directory structure to under the Eclipse project directory.\r
-REM This permits the Eclipse project to be used in 'managed' mode and without\r
-REM having to setup any linked resources.\r
-\r
-REM Files will also be copied into the BSP directory, which can be used to\r
-REM generate FreeRTOS BSP packages directly from within the Xilinx SDK.\r
-SET BSP_SOURCE=..\..\KernelAwareBSPRepository\bsp\freertos_v2_00_a\src\Source\r
-\r
-REM Standard paths\r
-SET FREERTOS_SOURCE=..\..\..\..\Source\r
-SET COMMON_SOURCE=..\..\..\Common\minimal\r
-SET COMMON_INCLUDE=..\..\..\Common\include\r
-SET LWIP_SOURCE=..\..\..\Common\ethernet\lwip-1.4.0\r
-\r
-REM Have the files already been copied?\r
-IF EXIST FreeRTOS_Source Goto END\r
-\r
- REM Create the required directory structure.\r
- MD FreeRTOS_Source\r
- MD FreeRTOS_Source\include \r
- MD FreeRTOS_Source\portable\GCC\r
- MD FreeRTOS_Source\portable\GCC\MicroBlazeV8\r
- MD FreeRTOS_Source\portable\MemMang \r
- MD Demo_Source\r
- MD Demo_Source\include\r
- MD lwIP\api\r
- MD lwIP\core\r
- MD lwIP\core\ipv4\r
- MD lwIP\include\r
- MD lwIP\include\ipv4\r
- MD lwIP\include\ipv4\lwip\r
- MD lwIP\include\lwip\r
- MD lwIP\include\netif\r
- MD lwIP\netif\r
- MD lwIP\netif\include\r
- MD lwIP\netif\include\arch\r
- \r
- REM Copy the core kernel files into the SDK projects directory\r
- copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source\r
- copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source\r
- copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source\r
- copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source\r
-\r
- REM Copy the core kernel files into the BSP directory\r
- copy %FREERTOS_SOURCE%\tasks.c %BSP_SOURCE%\r
- copy %FREERTOS_SOURCE%\queue.c %BSP_SOURCE%\r
- copy %FREERTOS_SOURCE%\list.c %BSP_SOURCE%\r
- copy %FREERTOS_SOURCE%\timers.c %BSP_SOURCE%\r
- \r
- REM Copy the common header files into the SDK projects directory\r
- copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include\r
- \r
- REM Copy the common header files into the BSP directory\r
- copy %FREERTOS_SOURCE%\include\*.* %BSP_SOURCE%\include\r
-\r
- REM Copy the portable layer files into the SDK projects directory\r
- copy %FREERTOS_SOURCE%\portable\GCC\MicroBlazeV8\*.* FreeRTOS_Source\portable\GCC\MicroBlazeV8\r
- \r
- REM Copy the portable layer files into the BSP projects directory\r
- copy %FREERTOS_SOURCE%\portable\GCC\MicroBlazeV8\*.* %BSP_SOURCE%\portable\GCC\MicroBlazeV8\r
-\r
- REM Copy the basic memory allocation files into the SDK projects directory\r
- copy %FREERTOS_SOURCE%\portable\MemMang\heap_3.c FreeRTOS_Source\portable\MemMang\r
-\r
- REM Copy the basic memory allocation files into the BSP directory\r
- copy %FREERTOS_SOURCE%\portable\MemMang\heap_3.c %BSP_SOURCE%\portable\MemMang\r
-\r
- REM Copy the files that define the common demo tasks.\r
- copy %COMMON_SOURCE%\dynamic.c Demo_Source\r
- copy %COMMON_SOURCE%\BlockQ.c Demo_Source\r
- copy %COMMON_SOURCE%\death.c Demo_Source\r
- copy %COMMON_SOURCE%\blocktim.c Demo_Source\r
- copy %COMMON_SOURCE%\semtest.c Demo_Source\r
- copy %COMMON_SOURCE%\PollQ.c Demo_Source\r
- copy %COMMON_SOURCE%\GenQTest.c Demo_Source\r
- copy %COMMON_SOURCE%\QPeek.c Demo_Source\r
- copy %COMMON_SOURCE%\recmutex.c Demo_Source\r
- copy %COMMON_SOURCE%\sp_flop.c Demo_Source\r
- copy %COMMON_SOURCE%\flash.c Demo_Source\r
- copy %COMMON_SOURCE%\comtest_strings.c Demo_Source\r
- copy %COMMON_SOURCE%\TimerDemo.c Demo_Source\r
- \r
- REM Copy the common demo file headers.\r
- copy %COMMON_INCLUDE%\dynamic.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\partest.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\BlockQ.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\death.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\blocktim.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\semtest.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\PollQ.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\GenQTest.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\QPeek.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\recmutex.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\flop.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\flash.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\comtest_strings.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\serial.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\comtest.h Demo_Source\include\r
- copy %COMMON_INCLUDE%\TimerDemo.h Demo_Source\include\r
- \r
- REM Copy the required lwIP files\r
- copy %LWIP_SOURCE%\src\api\*.c lwIP\api\r
- copy %LWIP_SOURCE%\src\core\*.c lwIP\core\r
- copy %LWIP_SOURCE%\src\core\ipv4\*.c lwIP\core\ipv4\r
- copy %LWIP_SOURCE%\src\include\ipv4\lwip\*.h lwIP\include\ipv4\lwip\r
- copy %LWIP_SOURCE%\src\include\lwip\*.h lwIP\include\lwip\r
- copy %LWIP_SOURCE%\src\include\netif\*.h lwIP\include\netif\r
- copy %LWIP_SOURCE%\src\netif\etharp.c lwIP\netif\r
- copy %LWIP_SOURCE%\ports\MicroBlaze-Ethernet-Lite lwip\netif\r
- copy %LWIP_SOURCE%\ports\MicroBlaze-Ethernet-Lite\include\arch lwip\netif\include\arch\r
-\r
-: END\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-\r
-/* The following #error directive is to remind users that a batch file must be\r
- * executed prior to this project being built. The batch file *cannot* be \r
- * executed from within older versions of Eclipse, but probably can be executed\r
- * from within the Xilinx SDK. Once it has been executed, re-open or refresh \r
- * the Eclipse project and remove the #error line below.\r
- */\r
-#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
-\r
-\r
-#ifndef FREERTOS_CONFIG_H\r
-#define FREERTOS_CONFIG_H\r
-\r
-/*-----------------------------------------------------------\r
- * Application specific definitions.\r
- *\r
- * These definitions should be adjusted for your particular hardware and\r
- * application requirements.\r
- *\r
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
- *\r
- * See http://www.freertos.org/a00110.html.\r
- *----------------------------------------------------------*/\r
-#define configUSE_PREEMPTION 1\r
-#define configUSE_IDLE_HOOK 1\r
-#define configUSE_TICK_HOOK 0\r
-#define configCPU_CLOCK_HZ ( XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ ) /* Not actually used in this demo as the timer is set up in main() and uses the peripheral clock, not the CPU clock. */\r
-#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
-#define configMAX_PRIORITIES ( 7 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 64 * 1024 ) )\r
-#define configMAX_TASK_NAME_LEN ( 10 )\r
-#define configUSE_TRACE_FACILITY 1\r
-#define configUSE_16_BIT_TICKS 0\r
-#define configIDLE_SHOULD_YIELD 1\r
-#define configUSE_MUTEXES 1\r
-#define configQUEUE_REGISTRY_SIZE 10\r
-#define configCHECK_FOR_STACK_OVERFLOW 2\r
-#define configUSE_RECURSIVE_MUTEXES 1\r
-#define configUSE_MALLOC_FAILED_HOOK 1\r
-#define configUSE_APPLICATION_TASK_TAG 0\r
-#define configUSE_COUNTING_SEMAPHORES 1\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 )\r
-#define configINTERRUPT_STACK_SIZE configMINIMAL_STACK_SIZE\r
-\r
-/* If configINSTALL_EXCEPTION_HANDLERS is set to 1, then the kernel will\r
-automatically install its own exception handlers before the kernel is started,\r
-if the application writer has not already caused them to be installed using the \r
-vPortExceptionsInstallHandlers() API function. See the documentation page for\r
-this demo on the FreeRTOS.org web site for more information. */\r
-#define configINSTALL_EXCEPTION_HANDLERS 1\r
-\r
-/* configINTERRUPT_CONTROLLER_TO_USE must be set to the ID of the interrupt\r
-controller that is going to be used directly by FreeRTOS itself. Most hardware\r
-designs will only include on interrupt controller. */\r
-#define configINTERRUPT_CONTROLLER_TO_USE XPAR_INTC_SINGLE_DEVICE_ID\r
-\r
-/* Co-routine definitions. */\r
-#define configUSE_CO_ROUTINES 0\r
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
-\r
-/* Software timer definitions. */\r
-#define configUSE_TIMERS 1\r
-#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 4 )\r
-#define configTIMER_QUEUE_LENGTH 10\r
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
-\r
-/* Set the following definitions to 1 to include the API function, or zero\r
-to exclude the API function. */\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 0\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
-#define INCLUDE_pcTaskGetTaskName 1\r
-#define INCLUDE_pcTaskGetTaskName 1\r
-\r
-/* This demo makes use of one or more example stats formatting functions. These\r
-format the raw data provided by the uxTaskGetSystemState() function in to human\r
-readable ASCII form. See the notes in the implementation of vTaskList() within \r
-FreeRTOS/Source/tasks.c for limitations. */\r
-#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
-\r
-#define configASSERT( x ) if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); }\r
- \r
-\r
-/* Run time stats gathering definitions. The conditional compilation is to\r
-prevent the C syntax being included in assembly files. */\r
-#ifndef __ASSEMBLER__\r
- unsigned long ulMainGetRunTimeCounterValue( void );\r
- void vMainConfigureTimerForRunTimeStats( void );\r
-#endif\r
-#define configGENERATE_RUN_TIME_STATS 1\r
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vMainConfigureTimerForRunTimeStats()\r
-#define portGET_RUN_TIME_COUNTER_VALUE() ulMainGetRunTimeCounterValue()\r
-\r
-\r
-\r
-\r
-\r
-/* Networking configuration follows. */\r
-\r
-#define configLWIP_TASK_PRIORITY ( configMAX_PRIORITIES - 4 )\r
-\r
-/* MAC address configuration. */\r
-#define configMAC_ADDR0 0x00\r
-#define configMAC_ADDR1 0x12\r
-#define configMAC_ADDR2 0x13\r
-#define configMAC_ADDR3 0x10\r
-#define configMAC_ADDR4 0x15\r
-#define configMAC_ADDR5 0x11\r
-\r
-/* IP address configuration. */\r
-#define configIP_ADDR0 192\r
-#define configIP_ADDR1 168\r
-#define configIP_ADDR2 0\r
-#define configIP_ADDR3 200\r
-\r
-/* Gateway IP address configuration. */\r
-#define configGW_IP_ADDR0 192\r
-#define configGW_IP_ADDR1 168\r
-#define configGW_IP_ADDR2 0\r
-#define configGW_IP_ADDR3 3\r
-\r
-/* Netmask configuration. */\r
-#define configNET_MASK0 255\r
-#define configNET_MASK1 255\r
-#define configNET_MASK2 255\r
-#define configNET_MASK3 0\r
-\r
-#endif /* FREERTOS_CONFIG_H */\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*-----------------------------------------------------------\r
- * Simple digital IO routines.\r
- *-----------------------------------------------------------*/\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-\r
-/* Demo application includes. */\r
-#include "partest.h"\r
-\r
-/* Library includes. */\r
-#include "xgpio.h"\r
-\r
-/* The hardware design that accompanies this demo project has four LED \r
-outputs. */\r
-#define partstMAX_LED 4\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* A hardware specific constant required to use the Xilinx driver library. */\r
-static const unsigned portBASE_TYPE uxGPIOOutputChannel = 1UL;\r
-\r
-/* The current state of the output port. */\r
-static unsigned char ucGPIOState = 0U;\r
-\r
-/* Structure that hold the state of the ouptut peripheral used by this demo.\r
-This is used by the Xilinx peripheral driver API functions. */\r
-static XGpio xOutputGPIOInstance;\r
-\r
-/*\r
- * Setup the IO for the LED outputs.\r
- */\r
-void vParTestInitialise( void )\r
-{\r
-portBASE_TYPE xStatus;\r
-const unsigned char ucSetToOutput = 0U;\r
-\r
- /* Initialise the GPIO for the LEDs. */\r
- xStatus = XGpio_Initialize( &xOutputGPIOInstance, XPAR_LEDS_4BITS_DEVICE_ID );\r
- if( xStatus == XST_SUCCESS )\r
- {\r
- /* All bits on this channel are going to be outputs (LEDs). */\r
- XGpio_SetDataDirection( &xOutputGPIOInstance, uxGPIOOutputChannel, ucSetToOutput );\r
-\r
- /* Start with all LEDs off. */\r
- ucGPIOState = 0U;\r
- XGpio_DiscreteWrite( &xOutputGPIOInstance, uxGPIOOutputChannel, ucGPIOState );\r
- }\r
- \r
- configASSERT( xStatus == XST_SUCCESS );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
-{\r
-unsigned char ucLED = 1U;\r
-\r
- /* Only attempt to set the LED if it is in range. */\r
- if( uxLED < partstMAX_LED )\r
- {\r
- ucLED <<= ( unsigned char ) uxLED;\r
-\r
- portENTER_CRITICAL();\r
- {\r
- if( xValue == pdFALSE )\r
- {\r
- ucGPIOState &= ~ucLED;\r
- }\r
- else\r
- {\r
- ucGPIOState |= ucLED;\r
- }\r
- XGpio_DiscreteWrite( &xOutputGPIOInstance, uxGPIOOutputChannel, ucGPIOState );\r
- }\r
- portEXIT_CRITICAL();\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
-{\r
-unsigned char ucLED = 1U;\r
-\r
- /* Only attempt to toggle the LED if it is in range. */\r
- if( uxLED < partstMAX_LED )\r
- {\r
- ucLED <<= ( unsigned char ) uxLED;\r
-\r
- portENTER_CRITICAL();\r
- {\r
- if( ( ucGPIOState & ucLED ) != 0 )\r
- {\r
- ucGPIOState &= ~ucLED;\r
- }\r
- else\r
- {\r
- ucGPIOState |= ucLED;\r
- }\r
-\r
- XGpio_DiscreteWrite( &xOutputGPIOInstance, uxGPIOOutputChannel, ucGPIOState );\r
- }\r
- portEXIT_CRITICAL();\r
- }\r
-}\r
-\r
-\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/*\r
- * The register test task as described in the comments at the top of main-full.c.\r
- */\r
-void vRegisterTest1( void *pvParameters );\r
-void vRegisterTest2( void *pvParameters );\r
-\r
-/* Variables that are incremented on each iteration of the reg test tasks -\r
-provided the tasks have not reported any errors. The check timer inspects these\r
-variables to ensure they are still incrementing as expected. If a variable\r
-stops incrementing then it is likely that its associate task has stalled or\r
-detected an error. */\r
-volatile unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void vRegisterTest1( void *pvParameters )\r
-{\r
- /* This task uses an infinite loop that is implemented in the assembly \r
- code.\r
- \r
- First fill the relevant registers with known values. */\r
- asm volatile ( " addi r3, r0, 3 \n\t" \\r
- " addi r4, r0, 4 \n\t" \\r
- " addi r6, r0, 6 \n\t" \\r
- " addi r7, r0, 7 \n\t" \\r
- " addi r8, r0, 8 \n\t" \\r
- " addi r9, r0, 9 \n\t" \\r
- " addi r10, r0, 10 \n\t" \\r
- " addi r11, r0, 11 \n\t" \\r
- " addi r12, r0, 12 \n\t" \\r
- " addi r16, r0, 16 \n\t" \\r
- " addi r19, r0, 19 \n\t" \\r
- " addi r20, r0, 20 \n\t" \\r
- " addi r21, r0, 21 \n\t" \\r
- " addi r22, r0, 22 \n\t" \\r
- " addi r23, r0, 23 \n\t" \\r
- " addi r24, r0, 24 \n\t" \\r
- " addi r25, r0, 25 \n\t" \\r
- " addi r26, r0, 26 \n\t" \\r
- " addi r27, r0, 27 \n\t" \\r
- " addi r28, r0, 28 \n\t" \\r
- " addi r29, r0, 29 \n\t" \\r
- " addi r30, r0, 30 \n\t" \\r
- " addi r31, r0, 31 \n\t"\r
- );\r
-\r
- /* Now test the register values to ensure they contain the same value that\r
- was written to them above. This task will get preempted frequently so \r
- other tasks are likely to have executed since the register values were \r
- written. If any register contains an unexpected value then the task will\r
- branch to Error_Loop_1, which in turn prevents it from incrementing its\r
- loop counter, enabling the check timer to determine that all is not as it\r
- should be. */\r
-\r
- asm volatile ( "Loop_Start_1: \n\t" \\r
- " xori r18, r3, 3 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r4, 4 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r6, 6 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r7, 7 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r8, 8 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r9, 9 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r10, 10 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r11, 11 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r12, 12 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r16, 16 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r19, 19 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r20, 20 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r21, 21 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r22, 22 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r23, 23 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r24, 24 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r25, 25 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r26, 26 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r27, 27 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r28, 28 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r29, 29 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r30, 30 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t" \\r
- " xori r18, r31, 31 \n\t" \\r
- " bnei r18, Error_Loop_1 \n\t"\r
- );\r
-\r
- /* If this task has not branched to the error loop, then everything is ok,\r
- and the check variable can be incremented to indicate that this task\r
- is still running. Then, brach back to the top to check the register\r
- contents again. */\r
- asm volatile ( " lwi r18, r0, ulRegTest1CycleCount \n\t" \\r
- " addik r18, r18, 1 \n\t" \\r
- " swi r18, r0, ulRegTest1CycleCount \n\t" \\r
- " \n\t" \\r
- " bri Loop_Start_1 "\r
- );\r
-\r
- /* The test function will branch here if it discovers an error. This part\r
- of the code just sits in a NULL loop, which prevents the check variable\r
- incrementing any further to allow the check timer to recognize that this\r
- test has failed. */\r
- asm volatile ( "Error_Loop_1: \n\t" \\r
- " bri 0 \n\t" \\r
- " nop \n\t" \\r
- );\r
-\r
- ( void ) pvParameters;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vRegisterTest2( void *pvParameters )\r
-{\r
- /* This task uses an infinite loop that is implemented in the assembly \r
- code.\r
- \r
- First fill the registers with known values. */\r
- asm volatile ( " addi r16, r0, 1016 \n\t" \\r
- " addi r19, r0, 1019 \n\t" \\r
- " addi r20, r0, 1020 \n\t" \\r
- " addi r21, r0, 1021 \n\t" \\r
- " addi r22, r0, 1022 \n\t" \\r
- " addi r23, r0, 1023 \n\t" \\r
- " addi r24, r0, 1024 \n\t" \\r
- " addi r25, r0, 1025 \n\t" \\r
- " addi r26, r0, 1026 \n\t" \\r
- " addi r27, r0, 1027 \n\t" \\r
- " addi r28, r0, 1028 \n\t" \\r
- " addi r29, r0, 1029 \n\t" \\r
- " addi r30, r0, 1030 \n\t" \\r
- " addi r31, r0, 1031 \n\t" \\r
- " " \\r
- "Loop_Start_2: "\r
- );\r
-\r
- /* Unlike vRegisterTest1, vRegisterTest2 performs a yield. This increases\r
- the test coverage, but does mean volatile registers need re-loading with \r
- their exepcted values. */\r
- taskYIELD();\r
-\r
- /* taskYIELD() could have changed temporaries - set them back to those\r
- expected by the reg test task. */\r
- asm volatile ( " addi r3, r0, 103 \n\t" \\r
- " addi r4, r0, 104 \n\t" \\r
- " addi r6, r0, 106 \n\t" \\r
- " addi r7, r0, 107 \n\t" \\r
- " addi r8, r0, 108 \n\t" \\r
- " addi r9, r0, 109 \n\t" \\r
- " addi r10, r0, 1010 \n\t" \\r
- " addi r11, r0, 1011 \n\t" \\r
- " addi r12, r0, 1012 \n\t" \\r
- );\r
-\r
-\r
- /* Now test the register values to ensure they contain the same value that\r
- was written to them above. This task will get preempted frequently so \r
- other tasks are likely to have executed since the register values were \r
- written. */\r
- asm volatile ( " xori r18, r3, 103 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r4, 104 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r6, 106 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r7, 107 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r8, 108 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r9, 109 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r10, 1010 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r11, 1011 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r12, 1012 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r16, 1016 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r19, 1019 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r20, 1020 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r21, 1021 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r22, 1022 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r23, 1023 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r24, 1024 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r25, 1025 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r26, 1026 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r27, 1027 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r28, 1028 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r29, 1029 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r30, 1030 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t" \\r
- " xori r18, r31, 1031 \n\t" \\r
- " bnei r18, Error_Loop_2 \n\t"\r
- );\r
-\r
- /* If this task has not branched to the error loop, then everything is ok,\r
- and the check variable should be incremented to indicate that this task\r
- is still running. Then, brach back to the top to check the registers\r
- again. */\r
- asm volatile ( " lwi r18, r0, ulRegTest2CycleCount \n\t" \\r
- " addik r18, r18, 1 \n\t" \\r
- " swi r18, r0, ulRegTest2CycleCount \n\t" \\r
- " \n\t" \\r
- " bri Loop_Start_2 "\r
- );\r
-\r
- /* The test function will branch here if it discovers an error. This part\r
- of the code just sits in a NULL loop, which prevents the check variable\r
- incrementing any further to allow the check timer to recognize that this\r
- test has failed. */\r
- asm volatile ( "Error_Loop_2: \n\t" \\r
- " bri 0 \n\t" \\r
- " nop \n\t" \\r
- );\r
-\r
- ( void ) pvParameters;\r
-}\r
-\r
-\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "fs.h"
-#include "fsdata.h"
-#include <string.h>
-
-/** Set this to 1 to include "fsdata_custom.c" instead of "fsdata.c" for the
- * file system (to prevent changing the file included in CVS) */
-#ifndef HTTPD_USE_CUSTUM_FSDATA
-#define HTTPD_USE_CUSTUM_FSDATA 0
-#endif
-
-#if HTTPD_USE_CUSTUM_FSDATA
-#include "fsdata_custom.c"
-#else /* HTTPD_USE_CUSTUM_FSDATA */
-#include "fsdata.c"
-#endif /* HTTPD_USE_CUSTUM_FSDATA */
-
-/*-----------------------------------------------------------------------------------*/
-/* Define the number of open files that we can support. */
-#ifndef LWIP_MAX_OPEN_FILES
-#define LWIP_MAX_OPEN_FILES 10
-#endif
-
-/* Define the file system memory allocation structure. */
-struct fs_table {
- struct fs_file file;
- u8_t inuse;
-};
-
-/* Allocate file system memory */
-struct fs_table fs_memory[LWIP_MAX_OPEN_FILES];
-
-#if LWIP_HTTPD_CUSTOM_FILES
-int fs_open_custom(struct fs_file *file, const char *name);
-void fs_close_custom(struct fs_file *file);
-#endif /* LWIP_HTTPD_CUSTOM_FILES */
-
-/*-----------------------------------------------------------------------------------*/
-static struct fs_file *
-fs_malloc(void)
-{
- int i;
- for(i = 0; i < LWIP_MAX_OPEN_FILES; i++) {
- if(fs_memory[i].inuse == 0) {
- fs_memory[i].inuse = 1;
- return(&fs_memory[i].file);
- }
- }
- return(NULL);
-}
-
-/*-----------------------------------------------------------------------------------*/
-static void
-fs_free(struct fs_file *file)
-{
- int i;
- for(i = 0; i < LWIP_MAX_OPEN_FILES; i++) {
- if(&fs_memory[i].file == file) {
- fs_memory[i].inuse = 0;
- break;
- }
- }
- return;
-}
-
-/*-----------------------------------------------------------------------------------*/
-struct fs_file *
-fs_open(const char *name)
-{
- struct fs_file *file;
- const struct fsdata_file *f;
-
- file = fs_malloc();
- if(file == NULL) {
- return NULL;
- }
-
-#if LWIP_HTTPD_CUSTOM_FILES
- if(fs_open_custom(file, name)) {
- file->is_custom_file = 1;
- return file;
- }
- file->is_custom_file = 0;
-#endif /* LWIP_HTTPD_CUSTOM_FILES */
-
- for(f = FS_ROOT; f != NULL; f = f->next) {
- if (!strcmp(name, (char *)f->name)) {
- file->data = (const char *)f->data;
- file->len = f->len;
- file->index = f->len;
- file->pextension = NULL;
- file->http_header_included = f->http_header_included;
-#if HTTPD_PRECALCULATED_CHECKSUM
- file->chksum_count = f->chksum_count;
- file->chksum = f->chksum;
-#endif /* HTTPD_PRECALCULATED_CHECKSUM */
-#if LWIP_HTTPD_FILE_STATE
- file->state = fs_state_init(file, name);
-#endif /* #if LWIP_HTTPD_FILE_STATE */
- return file;
- }
- }
- fs_free(file);
- return NULL;
-}
-
-/*-----------------------------------------------------------------------------------*/
-void
-fs_close(struct fs_file *file)
-{
-#if LWIP_HTTPD_CUSTOM_FILES
- if (file->is_custom_file) {
- fs_close_custom(file);
- }
-#endif /* LWIP_HTTPD_CUSTOM_FILES */
-#if LWIP_HTTPD_FILE_STATE
- fs_state_free(file, file->state);
-#endif /* #if LWIP_HTTPD_FILE_STATE */
- fs_free(file);
-}
-/*-----------------------------------------------------------------------------------*/
-int
-fs_read(struct fs_file *file, char *buffer, int count)
-{
- int read;
-
- if(file->index == file->len) {
- return -1;
- }
-
- read = file->len - file->index;
- if(read > count) {
- read = count;
- }
-
- MEMCPY(buffer, (file->data + file->index), read);
- file->index += read;
-
- return(read);
-}
-/*-----------------------------------------------------------------------------------*/
-int fs_bytes_left(struct fs_file *file)
-{
- return file->len - file->index;
-}
+++ /dev/null
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef __FS_H__
-#define __FS_H__
-
-#include "lwip/opt.h"
-
-/** Set this to 1 and provide the functions:
- * - "int fs_open_custom(struct fs_file *file, const char *name)"
- * Called first for every opened file to allow opening files
- * that are not included in fsdata(_custom).c
- * - "void fs_close_custom(struct fs_file *file)"
- * Called to free resources allocated by fs_open_custom().
- */
-#ifndef LWIP_HTTPD_CUSTOM_FILES
-#define LWIP_HTTPD_CUSTOM_FILES 0
-#endif
-
-/** Set this to 1 to include an application state argument per file
- * that is opened. This allows to keep a state per connection/file.
- */
-#ifndef LWIP_HTTPD_FILE_STATE
-#define LWIP_HTTPD_FILE_STATE 0
-#endif
-
-/** HTTPD_PRECALCULATED_CHECKSUM==1: include precompiled checksums for
- * predefined (MSS-sized) chunks of the files to prevent having to calculate
- * the checksums at runtime. */
-#ifndef HTTPD_PRECALCULATED_CHECKSUM
-#define HTTPD_PRECALCULATED_CHECKSUM 0
-#endif
-
-#if HTTPD_PRECALCULATED_CHECKSUM
-struct fsdata_chksum {
- u32_t offset;
- u16_t chksum;
- u16_t len;
-};
-#endif /* HTTPD_PRECALCULATED_CHECKSUM */
-
-struct fs_file {
- const char *data;
- int len;
- int index;
- void *pextension;
-#if HTTPD_PRECALCULATED_CHECKSUM
- const struct fsdata_chksum *chksum;
- u16_t chksum_count;
-#endif /* HTTPD_PRECALCULATED_CHECKSUM */
- u8_t http_header_included;
-#if LWIP_HTTPD_CUSTOM_FILES
- u8_t is_custom_file;
-#endif /* LWIP_HTTPD_CUSTOM_FILES */
-#if LWIP_HTTPD_FILE_STATE
- void *state;
-#endif /* LWIP_HTTPD_FILE_STATE */
-};
-
-struct fs_file *fs_open(const char *name);
-void fs_close(struct fs_file *file);
-int fs_read(struct fs_file *file, char *buffer, int count);
-int fs_bytes_left(struct fs_file *file);
-
-#if LWIP_HTTPD_FILE_STATE
-/** This user-defined function is called when a file is opened. */
-void *fs_state_init(struct fs_file *file, const char *name);
-/** This user-defined function is called when a file is closed. */
-void fs_state_free(struct fs_file *file, void *state);
-#endif /* #if LWIP_HTTPD_FILE_STATE */
-
-#endif /* __FS_H__ */
+++ /dev/null
-#include "fs.h"\r
-#include "lwip/def.h"\r
-#include "fsdata.h"\r
-\r
-\r
-#define file_NULL (struct fsdata_file *) NULL\r
-\r
-\r
-static const unsigned int dummy_align__404_html = 0;\r
-static const unsigned char data__404_html[] = {\r
-/* /404.html (10 chars) */\r
-0x2f,0x34,0x30,0x34,0x2e,0x68,0x74,0x6d,0x6c,0x00,0x00,0x00,\r
-\r
-/* HTTP header */\r
-/* "HTTP/1.0 404 File not found\r
-" (29 bytes) */\r
-0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x34,0x30,0x34,0x20,0x46,0x69,0x6c,\r
-0x65,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e,0x64,0x0d,0x0a,\r
-/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)\r
-" (63 bytes) */\r
-0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33,\r
-0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e,\r
-0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70,\r
-0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a,\r
-/* "Content-type: text/html\r
-\r
-" (27 bytes) */\r
-0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65,\r
-0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x0d,0x0a,\r
-/* raw file data (544 bytes) */\r
-0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0a,0x3c,0x68,0x65,0x61,0x64,0x3e,0x3c,0x74,0x69,\r
-0x74,0x6c,0x65,0x3e,0x6c,0x77,0x49,0x50,0x20,0x2d,0x20,0x41,0x20,0x4c,0x69,0x67,\r
-0x68,0x74,0x77,0x65,0x69,0x67,0x68,0x74,0x20,0x54,0x43,0x50,0x2f,0x49,0x50,0x20,\r
-0x53,0x74,0x61,0x63,0x6b,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x3c,0x2f,0x68,\r
-0x65,0x61,0x64,0x3e,0x0a,0x3c,0x62,0x6f,0x64,0x79,0x20,0x62,0x67,0x63,0x6f,0x6c,\r
-0x6f,0x72,0x3d,0x22,0x77,0x68,0x69,0x74,0x65,0x22,0x20,0x74,0x65,0x78,0x74,0x3d,\r
-0x22,0x62,0x6c,0x61,0x63,0x6b,0x22,0x3e,0x0a,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74,\r
-0x61,0x62,0x6c,0x65,0x20,0x77,0x69,0x64,0x74,0x68,0x3d,0x22,0x31,0x30,0x30,0x25,\r
-0x22,0x3e,0x0a,0x20,0x20,0x20,0x20,0x20,0x20,0x3c,0x74,0x72,0x20,0x76,0x61,0x6c,\r
-0x69,0x67,0x6e,0x3d,0x22,0x74,0x6f,0x70,0x22,0x3e,0x3c,0x74,0x64,0x20,0x77,0x69,\r
-0x64,0x74,0x68,0x3d,0x22,0x38,0x30,0x22,0x3e,0x09,0x20,0x20,0x0a,0x09,0x20,0x20,\r
-0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,\r
-0x77,0x77,0x77,0x2e,0x73,0x69,0x63,0x73,0x2e,0x73,0x65,0x2f,0x22,0x3e,0x3c,0x69,\r
-0x6d,0x67,0x20,0x73,0x72,0x63,0x3d,0x22,0x2f,0x69,0x6d,0x67,0x2f,0x73,0x69,0x63,\r
-0x73,0x2e,0x67,0x69,0x66,0x22,0x0a,0x09,0x20,0x20,0x62,0x6f,0x72,0x64,0x65,0x72,\r
-0x3d,0x22,0x30,0x22,0x20,0x61,0x6c,0x74,0x3d,0x22,0x53,0x49,0x43,0x53,0x20,0x6c,\r
-0x6f,0x67,0x6f,0x22,0x20,0x74,0x69,0x74,0x6c,0x65,0x3d,0x22,0x53,0x49,0x43,0x53,\r
-0x20,0x6c,0x6f,0x67,0x6f,0x22,0x3e,0x3c,0x2f,0x61,0x3e,0x0a,0x09,0x3c,0x2f,0x74,\r
-0x64,0x3e,0x3c,0x74,0x64,0x20,0x77,0x69,0x64,0x74,0x68,0x3d,0x22,0x35,0x30,0x30,\r
-0x22,0x3e,0x09,0x20,0x20,0x0a,0x09,0x20,0x20,0x3c,0x68,0x31,0x3e,0x6c,0x77,0x49,\r
-0x50,0x20,0x2d,0x20,0x41,0x20,0x4c,0x69,0x67,0x68,0x74,0x77,0x65,0x69,0x67,0x68,\r
-0x74,0x20,0x54,0x43,0x50,0x2f,0x49,0x50,0x20,0x53,0x74,0x61,0x63,0x6b,0x3c,0x2f,\r
-0x68,0x31,0x3e,0x0a,0x09,0x20,0x20,0x3c,0x68,0x32,0x3e,0x34,0x30,0x34,0x20,0x2d,\r
-0x20,0x50,0x61,0x67,0x65,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e,0x64,0x3c,\r
-0x2f,0x68,0x32,0x3e,0x0a,0x09,0x20,0x20,0x3c,0x70,0x3e,0x0a,0x09,0x20,0x20,0x20,\r
-0x20,0x53,0x6f,0x72,0x72,0x79,0x2c,0x20,0x74,0x68,0x65,0x20,0x70,0x61,0x67,0x65,\r
-0x20,0x79,0x6f,0x75,0x20,0x61,0x72,0x65,0x20,0x72,0x65,0x71,0x75,0x65,0x73,0x74,\r
-0x69,0x6e,0x67,0x20,0x77,0x61,0x73,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e,\r
-0x64,0x20,0x6f,0x6e,0x20,0x74,0x68,0x69,0x73,0x0a,0x09,0x20,0x20,0x20,0x20,0x73,\r
-0x65,0x72,0x76,0x65,0x72,0x2e,0x20,0x0a,0x09,0x20,0x20,0x3c,0x2f,0x70,0x3e,0x0a,\r
-0x09,0x3c,0x2f,0x74,0x64,0x3e,0x3c,0x74,0x64,0x3e,0x0a,0x09,0x20,0x20,0x26,0x6e,\r
-0x62,0x73,0x70,0x3b,0x0a,0x09,0x3c,0x2f,0x74,0x64,0x3e,0x3c,0x2f,0x74,0x72,0x3e,\r
-0x0a,0x20,0x20,0x20,0x20,0x20,0x20,0x3c,0x2f,0x74,0x61,0x62,0x6c,0x65,0x3e,0x0a,\r
-0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0a,0x3c,0x2f,0x68,0x74,0x6d,0x6c,0x3e,0x0a,\r
-};\r
-\r
-static const unsigned int dummy_align__index_shtml = 1;\r
-static const unsigned char data__index_shtml[] = {\r
-/* /index.shtml (13 chars) */\r
-0x2f,0x69,0x6e,0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x00,0x00,0x00,0x00,\r
-\r
-/* HTTP header */\r
-/* "HTTP/1.0 200 OK\r
-" (17 bytes) */\r
-0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d,\r
-0x0a,\r
-/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)\r
-" (63 bytes) */\r
-0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33,\r
-0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e,\r
-0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70,\r
-0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a,\r
-/* "Content-type: text/html\r
-Expires: Fri, 10 Apr 2008 14:00:00 GMT\r
-Pragma: no-cache\r
-\r
-" (85 bytes) */\r
-0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65,\r
-0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x45,0x78,0x70,0x69,0x72,0x65,0x73,\r
-0x3a,0x20,0x46,0x72,0x69,0x2c,0x20,0x31,0x30,0x20,0x41,0x70,0x72,0x20,0x32,0x30,\r
-0x30,0x38,0x20,0x31,0x34,0x3a,0x30,0x30,0x3a,0x30,0x30,0x20,0x47,0x4d,0x54,0x0d,\r
-0x0a,0x50,0x72,0x61,0x67,0x6d,0x61,0x3a,0x20,0x6e,0x6f,0x2d,0x63,0x61,0x63,0x68,\r
-0x65,0x0d,0x0a,0x0d,0x0a,\r
-/* raw file data (762 bytes) */\r
-0x3c,0x21,0x44,0x4f,0x43,0x54,0x59,0x50,0x45,0x20,0x48,0x54,0x4d,0x4c,0x20,0x50,\r
-0x55,0x42,0x4c,0x49,0x43,0x20,0x22,0x2d,0x2f,0x2f,0x57,0x33,0x43,0x2f,0x2f,0x44,\r
-0x54,0x44,0x20,0x48,0x54,0x4d,0x4c,0x20,0x34,0x2e,0x30,0x31,0x20,0x54,0x72,0x61,\r
-0x6e,0x73,0x69,0x74,0x69,0x6f,0x6e,0x61,0x6c,0x2f,0x2f,0x45,0x4e,0x22,0x20,0x22,\r
-0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x77,0x33,0x2e,0x6f,0x72,\r
-0x67,0x2f,0x54,0x52,0x2f,0x68,0x74,0x6d,0x6c,0x34,0x2f,0x6c,0x6f,0x6f,0x73,0x65,\r
-0x2e,0x64,0x74,0x64,0x22,0x3e,0x0d,0x0a,0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a,\r
-0x20,0x20,0x3c,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74,\r
-0x69,0x74,0x6c,0x65,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53,0x2e,0x6f,0x72,\r
-0x67,0x20,0x6c,0x77,0x49,0x50,0x20,0x57,0x45,0x42,0x20,0x73,0x65,0x72,0x76,0x65,\r
-0x72,0x20,0x64,0x65,0x6d,0x6f,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x0d,0x0a,\r
-0x20,0x20,0x3c,0x2f,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x3c,0x42,0x4f,\r
-0x44,0x59,0x20,0x6f,0x6e,0x4c,0x6f,0x61,0x64,0x3d,0x22,0x77,0x69,0x6e,0x64,0x6f,\r
-0x77,0x2e,0x73,0x65,0x74,0x54,0x69,0x6d,0x65,0x6f,0x75,0x74,0x28,0x26,0x71,0x75,\r
-0x6f,0x74,0x3b,0x6c,0x6f,0x63,0x61,0x74,0x69,0x6f,0x6e,0x2e,0x68,0x72,0x65,0x66,\r
-0x3d,0x27,0x69,0x6e,0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x27,0x26,0x71,\r
-0x75,0x6f,0x74,0x3b,0x2c,0x32,0x30,0x30,0x30,0x29,0x22,0x3e,0x0d,0x0a,0x3c,0x66,\r
-0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x61,0x72,0x69,0x61,0x6c,0x22,\r
-0x3e,0x0d,0x0a,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x69,0x6e,0x64,0x65,\r
-0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x54,0x61,0x73,0x6b,0x20,0x53,0x74,\r
-0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c,0x3c,0x2f,0x62,0x3e,\r
-0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x72,0x75,0x6e,0x74,0x69,0x6d,\r
-0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x52,0x75,0x6e,0x20,0x54,0x69,0x6d,\r
-0x65,0x20,0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c,\r
-0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x68,0x74,\r
-0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x66,0x72,0x65,0x65,0x72,0x74,0x6f,\r
-0x73,0x2e,0x6f,0x72,0x67,0x2f,0x22,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53,\r
-0x20,0x48,0x6f,0x6d,0x65,0x70,0x61,0x67,0x65,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,\r
-0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,\r
-0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x22,0x3e,0x33,0x37,0x4b,0x20,0x6a,0x70,\r
-0x67,0x3c,0x2f,0x61,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d,0x0a,\r
-0x3c,0x68,0x72,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d,0x0a,0x3c,\r
-0x68,0x32,0x3e,0x54,0x61,0x73,0x6b,0x20,0x73,0x74,0x61,0x74,0x69,0x73,0x74,0x69,\r
-0x63,0x73,0x3c,0x2f,0x68,0x32,0x3e,0x0d,0x0a,0x50,0x61,0x67,0x65,0x20,0x77,0x69,\r
-0x6c,0x6c,0x20,0x72,0x65,0x66,0x72,0x65,0x73,0x68,0x20,0x65,0x76,0x65,0x72,0x79,\r
-0x20,0x32,0x20,0x73,0x65,0x63,0x6f,0x6e,0x64,0x73,0x2e,0x3c,0x70,0x3e,0x0d,0x0a,\r
-0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x63,0x6f,0x75,0x72,\r
-0x69,0x65,0x72,0x22,0x3e,0x3c,0x70,0x72,0x65,0x3e,0x54,0x61,0x73,0x6b,0x20,0x20,\r
-0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x53,0x74,0x61,0x74,0x65,0x20,0x20,0x50,\r
-0x72,0x69,0x6f,0x72,0x69,0x74,0x79,0x20,0x20,0x53,0x74,0x61,0x63,0x6b,0x09,0x23,\r
-0x3c,0x62,0x72,0x3e,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
-0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
-0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
-0x2a,0x2a,0x2a,0x2a,0x3c,0x62,0x72,0x3e,0x0d,0x0a,0x3c,0x21,0x2d,0x2d,0x23,0x72,\r
-0x74,0x6f,0x73,0x5f,0x73,0x74,0x61,0x74,0x73,0x2d,0x2d,0x3e,0x0d,0x0a,0x3c,0x2f,\r
-0x70,0x72,0x65,0x3e,0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x66,\r
-0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0d,0x0a,0x3c,\r
-0x2f,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a,0x0d,0x0a,};\r
-\r
-static const unsigned int dummy_align__logo_jpg = 2;\r
-static const unsigned char data__logo_jpg[] = {\r
-/* /logo.jpg (10 chars) */\r
-0x2f,0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x00,0x00,0x00,\r
-\r
-/* HTTP header */\r
-/* "HTTP/1.0 200 OK\r
-" (17 bytes) */\r
-0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d,\r
-0x0a,\r
-/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)\r
-" (63 bytes) */\r
-0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33,\r
-0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e,\r
-0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70,\r
-0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a,\r
-/* "Content-type: image/jpeg\r
-\r
-" (28 bytes) */\r
-0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x69,0x6d,\r
-0x61,0x67,0x65,0x2f,0x6a,0x70,0x65,0x67,0x0d,0x0a,0x0d,0x0a,\r
-/* raw file data (28602 bytes) */\r
-0xff,0xd8,0xff,0xe0,0x00,0x10,0x4a,0x46,0x49,0x46,0x00,0x01,0x01,0x00,0x00,0x01,\r
-0x00,0x01,0x00,0x00,0xff,0xdb,0x00,0x43,0x00,0x03,0x02,0x02,0x03,0x02,0x02,0x03,\r
-0x03,0x03,0x03,0x04,0x03,0x03,0x04,0x05,0x08,0x05,0x05,0x04,0x04,0x05,0x0a,0x07,\r
-0x07,0x06,0x08,0x0c,0x0a,0x0c,0x0c,0x0b,0x0a,0x0b,0x0b,0x0d,0x0e,0x12,0x10,0x0d,\r
-0x0e,0x11,0x0e,0x0b,0x0b,0x10,0x16,0x10,0x11,0x13,0x14,0x15,0x15,0x15,0x0c,0x0f,\r
-0x17,0x18,0x16,0x14,0x18,0x12,0x14,0x15,0x14,0xff,0xdb,0x00,0x43,0x01,0x03,0x04,\r
-0x04,0x05,0x04,0x05,0x09,0x05,0x05,0x09,0x14,0x0d,0x0b,0x0d,0x14,0x14,0x14,0x14,\r
-0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,\r
-0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,\r
-0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0xff,0xc0,\r
-0x00,0x11,0x08,0x00,0xea,0x02,0x71,0x03,0x01,0x22,0x00,0x02,0x11,0x01,0x03,0x11,\r
-0x01,0xff,0xc4,0x00,0x1f,0x00,0x00,0x01,0x05,0x01,0x01,0x01,0x01,0x01,0x01,0x00,\r
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,\r
-0x0a,0x0b,0xff,0xc4,0x00,0xb5,0x10,0x00,0x02,0x01,0x03,0x03,0x02,0x04,0x03,0x05,\r
-0x05,0x04,0x04,0x00,0x00,0x01,0x7d,0x01,0x02,0x03,0x00,0x04,0x11,0x05,0x12,0x21,\r
-0x31,0x41,0x06,0x13,0x51,0x61,0x07,0x22,0x71,0x14,0x32,0x81,0x91,0xa1,0x08,0x23,\r
-0x42,0xb1,0xc1,0x15,0x52,0xd1,0xf0,0x24,0x33,0x62,0x72,0x82,0x09,0x0a,0x16,0x17,\r
-0x18,0x19,0x1a,0x25,0x26,0x27,0x28,0x29,0x2a,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,\r
-0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,\r
-0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,\r
-0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,\r
-0x9a,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,\r
-0xb8,0xb9,0xba,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5,\r
-0xd6,0xd7,0xd8,0xd9,0xda,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf1,\r
-0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xff,0xc4,0x00,0x1f,0x01,0x00,0x03,\r
-0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,\r
-0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0xff,0xc4,0x00,0xb5,0x11,0x00,\r
-0x02,0x01,0x02,0x04,0x04,0x03,0x04,0x07,0x05,0x04,0x04,0x00,0x01,0x02,0x77,0x00,\r
-0x01,0x02,0x03,0x11,0x04,0x05,0x21,0x31,0x06,0x12,0x41,0x51,0x07,0x61,0x71,0x13,\r
-0x22,0x32,0x81,0x08,0x14,0x42,0x91,0xa1,0xb1,0xc1,0x09,0x23,0x33,0x52,0xf0,0x15,\r
-0x62,0x72,0xd1,0x0a,0x16,0x24,0x34,0xe1,0x25,0xf1,0x17,0x18,0x19,0x1a,0x26,0x27,\r
-0x28,0x29,0x2a,0x35,0x36,0x37,0x38,0x39,0x3a,0x43,0x44,0x45,0x46,0x47,0x48,0x49,\r
-0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,0x63,0x64,0x65,0x66,0x67,0x68,0x69,\r
-0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,0x82,0x83,0x84,0x85,0x86,0x87,0x88,\r
-0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9a,0xa2,0xa3,0xa4,0xa5,0xa6,\r
-0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0xb8,0xb9,0xba,0xc2,0xc3,0xc4,\r
-0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7,0xd8,0xd9,0xda,0xe2,\r
-0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,\r
-0xfa,0xff,0xda,0x00,0x0c,0x03,0x01,0x00,0x02,0x11,0x03,0x11,0x00,0x3f,0x00,0xfd,\r
-0x53,0xa2,0x8a,0x28,0x00,0xa2,0x8a,0x28,0x00,0xa2,0x8a,0x28,0x00,0xa4,0x34,0x8e,\r
-0x70,0x09,0xaf,0x0b,0xf1,0xbf,0xc6,0x4b,0x8f,0x13,0x78,0xc2,0xdb,0xc1,0x7e,0x0f,\r
-0xb8,0x2b,0x24,0x93,0x08,0xae,0xf5,0x48,0x88,0x3b,0x47,0xf1,0x2c,0x7f,0x4e,0x72,\r
-0xdf,0x97,0xad,0x72,0x62,0x71,0x54,0xf0,0xb1,0xe6,0x9e,0xef,0x44,0xba,0xb6,0x73,\r
-0x57,0xc4,0x43,0x0e,0x93,0x9e,0xef,0x44,0xba,0xb6,0x77,0xbe,0x3b,0xf8,0xb9,0xa1,\r
-0xf8,0x16,0x39,0x23,0x9d,0xe4,0xd4,0x35,0x05,0x1c,0x58,0x59,0x2e,0xf9,0x3d,0xb7,\r
-0x76,0x51,0xf5,0xfc,0x8d,0x78,0x07,0x8a,0xff,0x00,0x69,0x3f,0x1b,0x6a,0xb3,0x3a,\r
-0x69,0x3a,0x7f,0xf6,0x2d,0xb7,0xf0,0x81,0x09,0x96,0x5f,0xc5,0x98,0x63,0xf2,0x15,\r
-0xf4,0xde,0x83,0xe0,0xdd,0x27,0xc3,0xf6,0x62,0x0b,0x6b,0x38,0xc9,0x3f,0x33,0xcb,\r
-0x20,0xde,0xf2,0x37,0x76,0x66,0x3c,0x92,0x6b,0x40,0xe9,0x16,0x47,0xad,0x9c,0x1f,\r
-0xf7,0xec,0x57,0x9d,0x88,0xc2,0xe3,0x31,0x2b,0xf8,0xbc,0x8b,0xb2,0x5f,0xad,0xce,\r
-0x3c,0x46,0x1b,0x13,0x88,0x56,0x8d,0x5e,0x45,0xe4,0xbf,0x53,0xe0,0x8d,0x4f,0xc6,\r
-0xfe,0x33,0xd5,0x18,0x9b,0xcd,0x5f,0x56,0x90,0x93,0x9c,0x19,0xa4,0x0b,0xf9,0x0e,\r
-0x2b,0x35,0x75,0xff,0x00,0x10,0xc7,0x9c,0x6a,0x3a,0x82,0xfa,0xfe,0xfa,0x41,0xfd,\r
-0x6b,0xf4,0x19,0xb4,0x2d,0x39,0xba,0xd8,0x5b,0x7f,0xdf,0xa1,0xfe,0x15,0x19,0xf0,\r
-0xce,0x94,0xff,0x00,0x7b,0x4d,0xb5,0x3f,0xf6,0xc5,0x7f,0xc2,0xbc,0x79,0x64,0x15,\r
-0xa4,0xef,0xed,0xaf,0xf2,0x7f,0xe6,0x78,0x72,0xc8,0x6a,0x49,0xdd,0xd7,0x7f,0xd7,\r
-0xcc,0xf8,0x0d,0x3c,0x5f,0xe2,0x68,0x94,0x05,0xd6,0x35,0x45,0x03,0xa0,0x17,0x32,\r
-0x0f,0xeb,0x53,0x27,0x8f,0xbc,0x59,0x11,0x25,0x75,0xfd,0x59,0x33,0xe9,0x77,0x28,\r
-0xfe,0xb5,0xf7,0x8b,0x78,0x3b,0x44,0x7e,0xba,0x4d,0x99,0xff,0x00,0xb6,0x2b,0x51,\r
-0x37,0x81,0x7c,0x3c,0xf9,0xce,0x8d,0x66,0x73,0xff,0x00,0x4c,0x56,0xa5,0x64,0x58,\r
-0x85,0xb5,0x6f,0xcc,0x9f,0xec,0x2a,0xeb,0x6a,0xef,0xf1,0xff,0x00,0x33,0xe1,0x6f,\r
-0xf8,0x59,0x3e,0x2f,0x5f,0xf9,0x98,0xb5,0x7f,0xfc,0x0c,0x93,0xfc,0x69,0xeb,0xf1,\r
-0x4f,0xc6,0x51,0x9c,0xaf,0x89,0x35,0x5c,0xfb,0xdd,0x3f,0xf8,0xd7,0xdc,0x0d,0xf0,\r
-0xf3,0xc3,0x6f,0xd7,0x44,0xb2,0x3f,0xf6,0xc8,0x54,0x4f,0xf0,0xcb,0xc2,0xaf,0xf7,\r
-0xb4,0x2b,0x23,0xff,0x00,0x6c,0x85,0x2f,0xec,0x4c,0x5f,0xfc,0xfe,0xfc,0xc5,0xfd,\r
-0x89,0x8a,0x5b,0x57,0x7f,0x89,0xf1,0x54,0x7f,0x17,0xfc,0x6b,0x1f,0xfc,0xcc,0x9a,\r
-0x99,0xfa,0xdc,0x35,0x58,0x8b,0xe3,0x87,0x8e,0xe1,0x6c,0xaf,0x89,0x2f,0x73,0xd3,\r
-0xe6,0x21,0x87,0xe4,0x45,0x7d,0x8e,0xff,0x00,0x09,0x7c,0x20,0xfd,0x74,0x0b,0x3f,\r
-0xc2,0x3c,0x54,0x2f,0xf0,0x6b,0xc1,0xaf,0xd7,0x41,0xb5,0x1f,0x45,0xa4,0xb2,0x7c,\r
-0x72,0xda,0xb7,0xe2,0xc7,0xfd,0x8f,0x8d,0x5b,0x62,0x1f,0xe2,0x7c,0x8a,0x9f,0x1f,\r
-0xbc,0x7e,0x83,0x1f,0xf0,0x91,0x5c,0x7d,0x4c,0x71,0x9f,0xfd,0x96,0xa6,0x1f,0xb4,\r
-0x37,0x8f,0xc7,0xfc,0xcc,0x12,0xfe,0x30,0x45,0xff,0x00,0xc4,0x57,0xd5,0xaf,0xf0,\r
-0x43,0xc1,0x4e,0x0f,0xfc,0x48,0xa0,0x1f,0x4a,0x89,0xbe,0x03,0xf8,0x21,0xf3,0xff,\r
-0x00,0x12,0x48,0x86,0x7d,0x09,0xa7,0xfd,0x95,0x98,0xad,0xab,0x7e,0x2c,0x3f,0xb2,\r
-0xb3,0x15,0xb6,0x21,0xfd,0xec,0xf9,0x69,0x7f,0x68,0xaf,0x1f,0x8f,0xf9,0x8f,0x39,\r
-0xfa,0xdb,0xc5,0xff,0x00,0xc4,0xd4,0x89,0xfb,0x48,0x78,0xf9,0x08,0x3f,0xdb,0x59,\r
-0xc7,0xad,0xb4,0x47,0xff,0x00,0x65,0xaf,0xa6,0x9f,0xf6,0x7d,0xf0,0x33,0x8e,0x74,\r
-0x75,0x1e,0xe1,0x8d,0x42,0xff,0x00,0xb3,0x9f,0x81,0x9c,0x7f,0xc8,0x2d,0x97,0xe9,\r
-0x21,0xa3,0xfb,0x33,0x34,0x5b,0x56,0xff,0x00,0xc9,0x98,0xbf,0xb3,0x33,0x35,0xb5,\r
-0x7f,0xc5,0x9f,0x39,0xc7,0xfb,0x4d,0xf8,0xf1,0x17,0x07,0x52,0x85,0xcf,0xab,0x5a,\r
-0xa6,0x7f,0x95,0x58,0x4f,0xda,0x9b,0xc7,0x49,0x8f,0xf4,0x9b,0x36,0xc7,0xad,0xaa,\r
-0xf3,0xfa,0xd7,0xbe,0xbf,0xec,0xd5,0xe0,0x86,0xc9,0x16,0x32,0xaf,0xd2,0x43,0x50,\r
-0x3f,0xec,0xc5,0xe0,0xa6,0xe9,0x6f,0x3a,0xff,0x00,0xdb,0x4a,0x5f,0xd9,0xf9,0xb2,\r
-0xda,0xaf,0xfe,0x4c,0xc3,0xfb,0x3f,0x36,0x5b,0x57,0xfc,0x59,0xe2,0x0b,0xfb,0x57,\r
-0x78,0xdd,0x7a,0x9d,0x39,0xbe,0xb6,0xc7,0xfa,0x35,0x3d,0x7f,0x6b,0x0f,0x1a,0x82,\r
-0x32,0x9a,0x61,0xff,0x00,0xb7,0x66,0xff,0x00,0xe2,0xeb,0xd9,0xdb,0xf6,0x5a,0xf0,\r
-0x63,0x0e,0x12,0xe5,0x7f,0xed,0xa5,0x42,0xff,0x00,0xb2,0xa7,0x83,0xcf,0x47,0xbb,\r
-0x5f,0xfb,0x69,0x43,0xc1,0xe7,0x0b,0x6a,0x9f,0xf9,0x30,0x7d,0x4b,0x37,0x5b,0x56,\r
-0xfc,0x4f,0x23,0x5f,0xda,0xd7,0xc6,0x43,0xad,0xbe,0x96,0xdf,0xf6,0xc1,0xff,0x00,\r
-0xf8,0xba,0x91,0x3f,0x6b,0x8f,0x16,0x82,0x37,0x59,0x69,0x6d,0xeb,0xfb,0xa7,0xff,\r
-0x00,0xe2,0xeb,0xd4,0x24,0xfd,0x93,0xbc,0x2a,0xd8,0xdb,0x75,0x78,0xbf,0xf0,0x20,\r
-0x6a,0x07,0xfd,0x92,0x3c,0x34,0x73,0x8b,0xfb,0xb5,0xf4,0xe9,0x4b,0xea,0xb9,0xca,\r
-0xfb,0x7f,0x88,0x7d,0x53,0x39,0x5b,0x55,0xfc,0x4f,0x3d,0x8b,0xf6,0xbe,0xf1,0x32,\r
-0xe7,0xcc,0xd2,0xb4,0xc7,0xf4,0xc2,0xc8,0x3f,0xf6,0x6a,0xb0,0x9f,0xb6,0x16,0xbc,\r
-0x31,0xbb,0x43,0xd3,0x5b,0xd7,0x0d,0x20,0xfe,0xb5,0xda,0xc9,0xfb,0x22,0xe8,0x19,\r
-0xf9,0x75,0x3b,0xa0,0x3d,0xd4,0x54,0x0f,0xfb,0x21,0x68,0xe4,0x7c,0xba,0xbd,0xcf,\r
-0xe2,0x82,0x9f,0xb1,0xce,0x97,0xda,0xfc,0x50,0x7b,0x0c,0xe9,0x7d,0xbf,0xc8,0xe6,\r
-0x07,0xed,0x89,0xaa,0xf7,0xf0,0xf5,0x99,0xfa,0x4e,0xdf,0xe1,0x4f,0x5f,0xdb,0x1b,\r
-0x50,0x1f,0x7b,0xc3,0x96,0xa7,0xe9,0x72,0xdf,0xfc,0x4d,0x6f,0x3f,0xec,0x7f,0xa6,\r
-0x1c,0xed,0xd6,0xe7,0x5f,0xac,0x60,0xd4,0x12,0x7e,0xc7,0xb6,0x99,0x1b,0x35,0xd9,\r
-0x31,0xef,0x17,0xff,0x00,0x5e,0x8e,0x4c,0xed,0x75,0xfc,0x85,0xec,0xf3,0xb5,0xf6,\r
-0xbf,0x23,0x35,0x7f,0x6c,0x7b,0xc3,0xf7,0xbc,0x35,0x01,0x1e,0xd7,0x67,0xff,0x00,\r
-0x89,0xa9,0x93,0xf6,0xc8,0x70,0x06,0xef,0x0b,0xa9,0x3d,0xf1,0x7b,0xff,0x00,0xd8,\r
-0x54,0xaf,0xfb,0x1e,0xa0,0x5f,0x97,0x5d,0xe7,0xde,0x2a,0x85,0xbf,0x63,0xe9,0x32,\r
-0x76,0xeb,0xa9,0xed,0x98,0x8d,0x2f,0xf8,0x5b,0x5d,0xff,0x00,0xf2,0x50,0xb6,0x76,\r
-0xba,0xfe,0x44,0xeb,0xfb,0x64,0xc4,0x7e,0xf7,0x85,0xdf,0x1e,0xd7,0xa3,0xff,0x00,\r
-0x8d,0xd4,0xcb,0xfb,0x63,0xda,0x63,0xe6,0xf0,0xcc,0xc0,0xfb,0x5e,0x03,0xff,0x00,\r
-0xb2,0x56,0x63,0xfe,0xc7,0xd7,0x7d,0xb5,0xc8,0x4f,0xd5,0x0d,0x40,0xff,0x00,0xb2,\r
-0x06,0xa6,0x01,0xdb,0xad,0x5b,0x13,0xee,0x84,0x53,0xf6,0x99,0xda,0xe8,0xfe,0xe8,\r
-0x87,0x3e,0x78,0xbf,0xa4,0x6f,0x27,0xed,0x8b,0xa7,0x13,0xcf,0x87,0x2e,0x40,0xff,\r
-0x00,0xaf,0x95,0x3f,0xfb,0x2d,0x48,0x3f,0x6c,0x3d,0x27,0x1f,0x37,0x87,0xaf,0x01,\r
-0xf6,0x9d,0x0f,0xf4,0xae,0x59,0xbf,0x64,0x2d,0x68,0x1e,0x35,0x6b,0x53,0xef,0x83,\r
-0x50,0x37,0xec,0x8d,0xe2,0x11,0xf7,0x75,0x0b,0x46,0xfc,0x4d,0x4f,0xb7,0xce,0x97,\r
-0xd9,0x7f,0x72,0x17,0xb5,0xce,0xd7,0xd9,0xfc,0x11,0xdd,0x45,0xfb,0x5f,0xf8,0x74,\r
-0xb7,0xcf,0xa3,0x6a,0x4a,0x3d,0x54,0xc6,0x7f,0xf6,0x6a,0xb3,0x1f,0xed,0x75,0xe1,\r
-0x36,0x5c,0xbe,0x9b,0xab,0x2b,0x7a,0x08,0xe3,0x3f,0xfb,0x3d,0x79,0xb4,0x9f,0xb2,\r
-0x67,0x89,0x54,0x1c,0x5e,0x5a,0x13,0xfe,0xf1,0xa8,0x1b,0xf6,0x50,0xf1,0x5f,0x69,\r
-0xad,0x1b,0xfe,0x07,0x42,0xc5,0x67,0x0b,0xec,0x3f,0xb9,0x0f,0xeb,0x39,0xd2,0xfb,\r
-0x1f,0x82,0x3d,0x54,0x7e,0xd6,0xfe,0x0e,0xce,0x0d,0x96,0xae,0x07,0xaf,0x93,0x1f,\r
-0xff,0x00,0x17,0x4f,0x1f,0xb5,0xaf,0x83,0x31,0xff,0x00,0x1e,0xba,0xb7,0xfd,0xf8,\r
-0x4f,0xfe,0x2e,0xbc,0x85,0xbf,0x65,0x4f,0x18,0x0f,0xbb,0xf6,0x46,0xff,0x00,0xb6,\r
-0xb5,0x03,0xfe,0xcb,0xbe,0x34,0x4c,0xe2,0x0b,0x76,0x03,0xd2,0x51,0x43,0xc7,0x66,\r
-0xeb,0x7a,0x7f,0xf9,0x28,0x7d,0x73,0x39,0x5f,0xf2,0xeb,0xf0,0x3d,0xa9,0x7f,0x6a,\r
-0xff,0x00,0x05,0x36,0x3f,0x75,0xa9,0xaf,0xd6,0xdd,0x7f,0xf8,0xaa,0x91,0x7f,0x6a,\r
-0xaf,0x04,0x11,0xc9,0xd4,0x53,0xeb,0x6c,0x3f,0xf8,0xaa,0xf0,0xb6,0xfd,0x99,0x7c,\r
-0x6c,0xbd,0x2c,0xe2,0x3f,0x49,0x45,0x42,0xff,0x00,0xb3,0x67,0x8d,0xd4,0x7f,0xc8,\r
-0x3d,0x4f,0xd1,0xc5,0x2f,0xed,0x1c,0xd5,0x7f,0xcb,0xbf,0xfc,0x95,0x8b,0xeb,0xf9,\r
-0xba,0xff,0x00,0x97,0x5f,0x87,0xfc,0x13,0xe8,0x48,0xbf,0x69,0xef,0x01,0xc8,0xe0,\r
-0x1b,0xeb,0xa8,0xc1,0xfe,0x26,0xb5,0x6c,0x0f,0xca,0xad,0x2f,0xed,0x27,0xf0,0xfd,\r
-0x81,0x3f,0xdb,0x2e,0xbe,0xc6,0xd6,0x5f,0xfe,0x26,0xbe,0x6b,0x6f,0xd9,0xd7,0xc7,\r
-0x0a,0x78,0xd2,0xc9,0xc7,0xa3,0x8a,0x81,0xff,0x00,0x67,0xef,0x1c,0xa9,0xff,0x00,\r
-0x90,0x34,0x87,0xe8,0xc0,0xff,0x00,0x5a,0x7f,0xda,0x99,0x9c,0x77,0xa5,0xff,0x00,\r
-0x92,0xb0,0xfe,0xd2,0xcd,0x56,0xf4,0x7f,0x06,0x7d,0x42,0x3f,0x68,0x9f,0x87,0xcd,\r
-0xff,0x00,0x33,0x02,0x8f,0xad,0xb4,0xdf,0xfc,0x45,0x38,0x7e,0xd0,0x9f,0x0f,0xcf,\r
-0x4f,0x11,0x47,0xff,0x00,0x80,0xf2,0x8f,0xfd,0x92,0xbe,0x55,0x6f,0x81,0x3e,0x37,\r
-0x43,0xce,0x89,0x37,0xe1,0x51,0x3f,0xc1,0x4f,0x1a,0x27,0x5d,0x0e,0xe7,0x8f,0x6a,\r
-0x6f,0x38,0xcc,0x16,0xf4,0xbf,0xf2,0x59,0x07,0xf6,0xae,0x64,0xb7,0xa1,0xf8,0x3f,\r
-0xf3,0x3e,0xb2,0x1f,0x1f,0xfc,0x00,0xd8,0xff,0x00,0x8a,0x8e,0x1e,0x7d,0x62,0x93,\r
-0xff,0x00,0x89,0xa9,0xd3,0xe3,0xaf,0x80,0xdc,0x64,0x78,0x92,0xd4,0x7d,0x43,0x8f,\r
-0xe9,0x5f,0x1f,0xbf,0xc1,0xff,0x00,0x18,0xa0,0xe7,0x42,0xba,0xe7,0xfd,0x9a,0x85,\r
-0xbe,0x14,0xf8,0xb9,0x3a,0xe8,0x77,0x7f,0xf7,0xc5,0x2f,0xed,0xac,0x72,0xff,0x00,\r
-0x97,0x4b,0xee,0x62,0xfe,0xd8,0xc7,0xad,0xe8,0x7e,0x0c,0xfb,0x3d,0x3e,0x32,0xf8,\r
-0x21,0xc0,0xc7,0x89,0xb4,0xfe,0x7d,0x65,0xc5,0x48,0x9f,0x17,0x7c,0x14,0xf9,0xc7,\r
-0x89,0xf4,0xce,0x3d,0x6e,0x14,0x57,0xc4,0xef,0xf0,0xd3,0xc5,0x51,0x9f,0x9b,0x44,\r
-0xbd,0x1f,0xf6,0xc8,0xd4,0x0d,0xe0,0x0f,0x12,0x27,0x5d,0x1e,0xf0,0x7f,0xdb,0x23,\r
-0x47,0xf6,0xee,0x29,0x6f,0x49,0x7e,0x23,0xfe,0xdb,0xc6,0x2d,0xe8,0x7e,0x67,0xdc,\r
-0x63,0xe2,0xbf,0x83,0x4f,0x4f,0x13,0xe9,0x7f,0xf8,0x16,0x9f,0xe3,0x52,0x2f,0xc4,\r
-0xef,0x09,0x36,0x71,0xe2,0x5d,0x2f,0x8f,0xfa,0x7b,0x4f,0xf1,0xaf,0x85,0x1b,0xc1,\r
-0x5e,0x20,0x5e,0xba,0x55,0xd0,0xff,0x00,0xb6,0x46,0xa2,0x6f,0x0a,0x6b,0x69,0xd7,\r
-0x4c,0xba,0x1f,0xf6,0xc8,0xd1,0xfd,0xbf,0x89,0xeb,0x49,0x7e,0x22,0xfe,0xdd,0xc5,\r
-0x2d,0xe8,0x7e,0x67,0xde,0xc9,0xf1,0x07,0xc2,0xf2,0x80,0x57,0xc4,0x3a,0x59,0x07,\r
-0xa7,0xfa,0x64,0x7f,0xe3,0x56,0x13,0xc6,0x5a,0x04,0x9f,0x77,0x5a,0xd3,0x9b,0x1e,\r
-0x97,0x49,0xfe,0x35,0xf9,0xfa,0xde,0x1c,0xd5,0xd7,0xae,0x9f,0x72,0x3f,0xed,0x91,\r
-0xa8,0xce,0x89,0xa9,0x27,0x06,0xca,0xe0,0x7d,0x63,0x34,0xd7,0x10,0xd6,0x5b,0xd3,\r
-0x5f,0x8f,0xf9,0x0f,0xfb,0x7e,0xbf,0x5a,0x1f,0x99,0xfa,0x1a,0x9e,0x23,0xd2,0x64,\r
-0x50,0x57,0x54,0xb3,0x60,0x7a,0x62,0xe1,0x3f,0xc6,0x9f,0xfd,0xbb,0xa6,0x9e,0x9a,\r
-0x8d,0xa9,0xff,0x00,0xb6,0xeb,0xfe,0x35,0xf9,0xd8,0x74,0xbb,0xe1,0xd6,0xd6,0x61,\r
-0xff,0x00,0x00,0x34,0xc3,0x61,0x78,0xbd,0x60,0x90,0x7d,0x54,0xd3,0xff,0x00,0x58,\r
-0xe7,0xd6,0x97,0xe3,0xff,0x00,0x00,0x7f,0xeb,0x0d,0x45,0xff,0x00,0x2e,0x7f,0x1f,\r
-0xf8,0x07,0xe8,0xca,0x6a,0xf6,0x2e,0x32,0x2f,0x2d,0xd8,0x7a,0x89,0x54,0xff,0x00,\r
-0x5a,0x78,0xd4,0x6d,0x49,0xe2,0xe6,0x03,0xf4,0x90,0x7f,0x8d,0x7e,0x71,0x7d,0x9e,\r
-0xed,0x7f,0xe5,0x9c,0xa3,0xf0,0x34,0xb9,0xbb,0x43,0xff,0x00,0x2d,0x47,0xe7,0x47,\r
-0xfa,0xc7,0x2f,0xf9,0xf5,0xf8,0xff,0x00,0xc0,0x0f,0xf5,0x8a,0x56,0xd6,0x8b,0xfb,\r
-0xff,0x00,0xe0,0x1f,0xa4,0x0b,0x75,0x13,0x8c,0xac,0xa8,0xc3,0xd4,0x30,0x34,0xf1,\r
-0x20,0x3d,0xc1,0xfc,0x6b,0xf3,0x78,0x5e,0x5e,0xa7,0x49,0x66,0x51,0xec,0xcd,0x53,\r
-0x2e,0xb5,0xaa,0xc6,0xc0,0xad,0xf5,0xda,0x9f,0x51,0x33,0x83,0xfc,0xea,0xd7,0x11,\r
-0xf7,0xa5,0xf8,0xff,0x00,0xc0,0x29,0x71,0x1a,0xeb,0x49,0xfd,0xff,0x00,0xf0,0x0f,\r
-0xd1,0xb0,0xc3,0xd6,0x97,0x75,0x7e,0x74,0x0f,0x13,0x6b,0x4a,0x30,0x35,0x4b,0xe5,\r
-0xfa,0x5c,0x3f,0xf8,0xd2,0x8f,0x16,0x6b,0x8a,0x72,0x35,0x7d,0x40,0x1f,0xfa,0xfa,\r
-0x93,0xfc,0x6a,0xff,0x00,0xd6,0x38,0xff,0x00,0xcf,0xbf,0xc7,0xfe,0x00,0xff,0x00,\r
-0xd6,0x48,0x75,0xa4,0xfe,0xf3,0xf4,0x58,0x36,0x69,0x6b,0xf3,0xb1,0x7c,0x6b,0xe2,\r
-0x04,0x04,0x0d,0x6b,0x51,0x1f,0xf6,0xf5,0x27,0xf8,0xd5,0x88,0xfe,0x23,0x78,0xa2,\r
-0x10,0x36,0x78,0x83,0x54,0x5c,0x70,0x31,0x79,0x27,0xf8,0xd3,0x5c,0x45,0x0e,0xb4,\r
-0xdf,0xde,0x52,0xe2,0x4a,0x5d,0x69,0xb3,0xf4,0x32,0x8a,0xfc,0xf9,0x5f,0x8a,0x5e,\r
-0x2e,0x41,0x81,0xe2,0x4d,0x54,0x0f,0xfa,0xfb,0x73,0xfd,0x6a,0xc2,0x7c,0x62,0xf1,\r
-0xaa,0x63,0x1e,0x26,0xd4,0xb8,0xe9,0xfb,0xf2,0x6a,0xd7,0x11,0x52,0xeb,0x4d,0xfe,\r
-0x05,0x7f,0xac,0x94,0x3a,0xc1,0xfe,0x07,0xdf,0xd4,0x57,0xc0,0xa3,0xe3,0x57,0x8d,\r
-0xd7,0xfe,0x66,0x6d,0x43,0xf1,0x97,0xff,0x00,0xad,0x4f,0x4f,0x8d,0xfe,0x38,0x5c,\r
-0x7f,0xc5,0x4b,0x7c,0x71,0xea,0xe0,0xff,0x00,0x4a,0xaf,0xf5,0x8a,0x87,0xf2,0x3f,\r
-0xc0,0xaf,0xf5,0x8f,0x0d,0xfc,0x8f,0xf0,0x3e,0xf7,0xa2,0xbe,0x0c,0x5f,0x8e,0xde,\r
-0x3a,0x5e,0x9e,0x24,0xbc,0xfc,0x76,0x9f,0xe9,0x56,0x53,0xf6,0x84,0xf1,0xea,0x63,\r
-0xfe,0x2a,0x19,0x8e,0x3d,0x61,0x8c,0xff,0x00,0xec,0xb4,0xd7,0x11,0x61,0xdf,0xd8,\r
-0x97,0xe1,0xfe,0x65,0x2e,0x22,0xc2,0xf5,0x8c,0xbf,0x0f,0xf3,0x3e,0xea,0xa2,0xbe,\r
-0x1c,0x8b,0xf6,0x8e,0xf1,0xf4,0x44,0x9f,0xed,0xc2,0xd9,0xfe,0xf5,0xbc,0x47,0xff,\r
-0x00,0x65,0xab,0xf6,0x3f,0xb5,0x17,0x8e,0xed,0x26,0x57,0x96,0xee,0xd2,0xed,0x07,\r
-0x54,0x9a,0xd5,0x40,0x3f,0xf7,0xce,0x0d,0x68,0xb8,0x83,0x0a,0xf7,0x4f,0xf0,0xff,\r
-0x00,0x32,0xd7,0x10,0xe0,0xde,0xe9,0xaf,0x97,0xfc,0x13,0xed,0x4a,0x2b,0xe6,0x2f,\r
-0x0c,0xfe,0xd8,0x52,0x06,0x58,0xfc,0x41,0xa1,0x86,0x5e,0xf3,0xe9,0xcf,0x83,0xed,\r
-0xf2,0x39,0xff,0x00,0xd9,0xab,0xda,0xbc,0x15,0xf1,0x6f,0xc2,0xfe,0x3f,0x5d,0xba,\r
-0x46,0xa9,0x1c,0x97,0x40,0x65,0xad,0x26,0xfd,0xdc,0xcb,0xff,0x00,0x01,0x3d,0x7e,\r
-0xa3,0x22,0xbd,0x6c,0x3e,0x63,0x86,0xc4,0xe9,0x4e,0x7a,0xf6,0xd9,0x9e,0xa6,0x1f,\r
-0x32,0xc2,0xe2,0x9d,0xa9,0xcd,0x5f,0xb6,0xcc,0xec,0xe8,0xa6,0xa9,0xcd,0x3a,0xbd,\r
-0x13,0xd3,0x0a,0x28,0xa2,0x80,0x0a,0x28,0xa2,0x80,0x0a,0x28,0xa2,0x80,0x0a,0x42,\r
-0x69,0x6a,0xbd,0xe5,0xd4,0x56,0x56,0xd3,0x5c,0x4f,0x22,0xc5,0x04,0x48,0x5d,0xdd,\r
-0xce,0x02,0xa8,0x19,0x24,0x9a,0x4f,0x45,0x71,0x37,0x65,0x76,0x78,0x6f,0xed,0x35,\r
-0xf1,0x65,0xfc,0x33,0xa6,0x2f,0x86,0xb4,0xb9,0xb6,0x6a,0x57,0xd1,0xee,0xb8,0x95,\r
-0x1b,0x0d,0x0c,0x3d,0x30,0x3d,0x0b,0x72,0x3e,0x80,0xfa,0x8a,0xe4,0xbf,0x64,0xbf,\r
-0x08,0xfd,0xa7,0x55,0xbe,0xd7,0x66,0x43,0xb6,0xdd,0x7c,0xa8,0x8f,0x6d,0xc7,0xad,\r
-0x78,0x9f,0x8c,0xbc,0x4d,0x71,0xe3,0x9f,0x17,0xea,0x3a,0xbc,0xdb,0x8b,0xde,0x4e,\r
-0x5a,0x34,0x3d,0x51,0x33,0x84,0x5f,0xc0,0x00,0x2b,0xed,0x7f,0x82,0x9e,0x13,0x1e,\r
-0x11,0xf8,0x7d,0xa6,0xdb,0x15,0xdb,0x3c,0xa9,0xe7,0xcb,0x91,0x83,0xb9,0xb9,0xaf,\r
-0x89,0xc3,0x4e,0x59,0x96,0x64,0xea,0xbf,0x86,0x1b,0x7e,0x9f,0xe6,0x7c,0x56,0x0a,\r
-0xa4,0xb3,0x3c,0xc1,0xd7,0x97,0xc3,0x0d,0xbf,0x4f,0xf3,0x3b,0xb0,0x31,0x4b,0x45,\r
-0x15,0xf6,0xe7,0xdb,0x09,0x4b,0x45,0x14,0x00,0x53,0x43,0x83,0xd2,0x9d,0x5e,0x0f,\r
-0xf1,0xcb,0xf6,0xdc,0xf8,0x3b,0xfb,0x3e,0x5c,0xc9,0x61,0xe2,0xaf,0x16,0xc2,0xfa,\r
-0xda,0x02,0x7f,0xb1,0xf4,0xc4,0x6b,0xbb,0xa0,0x47,0x66,0x54,0xc8,0x8c,0x9e,0xde,\r
-0x61,0x5c,0xd0,0x07,0xba,0x89,0x01,0x6d,0xbc,0xe7,0xdc,0x1a,0x7d,0x7e,0x71,0xeb,\r
-0xdf,0xf0,0x5a,0xdf,0x00,0x5b,0xb3,0x0d,0x1b,0xe1,0xf7,0x89,0x2f,0x80,0xe8,0xd7,\r
-0xd3,0xdb,0xdb,0xe7,0xf0,0x56,0x92,0xbe,0x9f,0xfd,0x94,0x7f,0x6a,0xb8,0xbf,0x69,\r
-0x8f,0x85,0xfa,0xaf,0x8f,0x2e,0x7c,0x36,0xfe,0x0b,0xd0,0xac,0xae,0x64,0xb7,0x59,\r
-0xef,0xef,0x92,0x44,0x91,0x63,0x40,0xd2,0xca,0x5b,0x6a,0x85,0x45,0xce,0x32,0x7d,\r
-0x1b,0xa6,0x28,0x11,0xef,0xb4,0x57,0x17,0x6d,0xf1,0xb3,0xe1,0xe5,0xeb,0x2a,0xdb,\r
-0xf8,0xf3,0xc3,0x33,0xb3,0x1c,0x05,0x8b,0x58,0xb7,0x62,0x4f,0xe0,0xf5,0xd9,0x83,\r
-0x9e,0x94,0x0c,0x5a,0x2b,0x33,0x5f,0xf1,0x1e,0x9f,0xe1,0x7d,0x3d,0xaf,0xb5,0x3b,\r
-0x91,0x6b,0x6a,0xac,0x14,0xb9,0x52,0xdc,0x93,0x80,0x30,0x01,0x35,0x81,0x17,0xc5,\r
-0xff,0x00,0x07,0xcd,0xd3,0x5d,0x80,0x7f,0xbe,0xae,0xbf,0xcc,0x57,0x34,0xf1,0x34,\r
-0x69,0x4b,0x96,0xa4,0xd2,0x7e,0x6d,0x22,0x1c,0xe1,0x17,0x66,0xd2,0x3b,0x1a,0x31,\r
-0x5c,0xcc,0x7f,0x12,0xfc,0x2b,0x26,0x31,0xe2,0x0b,0x01,0x9f,0xef,0x4e,0xa3,0xf9,\r
-0xd4,0xc3,0xe2,0x0f,0x86,0x0f,0x4f,0x10,0xe9,0x9f,0xf8,0x16,0x9f,0xe3,0x49,0x62,\r
-0xb0,0xef,0x6a,0x8b,0xef,0x42,0xf6,0x90,0xfe,0x64,0x74,0x34,0x56,0x12,0xf8,0xe7,\r
-0xc3,0x8e,0x78,0xd7,0xf4,0xc3,0xff,0x00,0x6f,0x91,0xff,0x00,0x8d,0x58,0x8b,0xc5,\r
-0x3a,0x34,0xe3,0xf7,0x7a,0xb5,0x8c,0x9f,0xee,0xdc,0x21,0xfe,0xb5,0xa2,0xad,0x4d,\r
-0xed,0x25,0xf7,0x8f,0x9a,0x2f,0x66,0x6a,0xd1,0x55,0x13,0x55,0xb2,0x97,0x95,0xbb,\r
-0x81,0xbf,0xdd,0x95,0x4f,0xf5,0xa9,0x96,0x78,0xa4,0xfb,0xb2,0x2b,0x7d,0x1a,0xaf,\r
-0x9e,0x2f,0x66,0x55,0xd1,0x2d,0x14,0xdd,0xdd,0xc1,0xa5,0x07,0x35,0x43,0x16,0x8a,\r
-0x28,0xa6,0x01,0x45,0x21,0xe9,0x49,0x9a,0x00,0x75,0x26,0x29,0x32,0x3d,0x69,0x73,\r
-0x48,0x05,0xa4,0xc5,0x18,0xf7,0xa5,0xa6,0x02,0x62,0x96,0x8a,0x28,0x00,0xa2,0x8a,\r
-0x28,0x01,0x29,0x68,0xa2,0x80,0x12,0x8c,0x52,0xd1,0x40,0x05,0x14,0x51,0x40,0x05,\r
-0x26,0x29,0x68,0xa0,0x04,0xc5,0x18,0x1e,0x94,0xb4,0x50,0x02,0x6d,0x1e,0x82,0x93,\r
-0xcb,0x53,0xfc,0x23,0xf2,0xa0,0x92,0x3f,0x87,0x3f,0x8d,0x28,0xcf,0x71,0x8a,0x00,\r
-0x69,0x82,0x33,0xd6,0x35,0x3f,0x80,0xa6,0x9b,0x58,0x5b,0xac,0x48,0x7f,0xe0,0x22,\r
-0xa5,0xa2,0x95,0x97,0x61,0x59,0x10,0x1b,0x1b,0x73,0xd6,0x08,0xff,0x00,0xef,0x91,\r
-0x4d,0x3a,0x6d,0xa3,0x75,0xb6,0x84,0xfd,0x50,0x55,0x9a,0x29,0x72,0xc7,0xb0,0x59,\r
-0x14,0x9b,0x46,0xb0,0x6e,0xb6,0x56,0xe7,0xfe,0xd9,0x8f,0xf0,0xa8,0xdb,0xc3,0xba,\r
-0x5b,0x75,0xd3,0xed,0x8f,0xfd,0xb2,0x5f,0xf0,0xad,0x1a,0x29,0x7b,0x38,0x76,0x17,\r
-0x2a,0xec,0x64,0xb7,0x85,0x74,0x76,0xeb,0xa6,0x5a,0x9f,0xfb,0x64,0xbf,0xe1,0x51,\r
-0xb7,0x83,0x74,0x36,0xeb,0xa4,0xda,0x1f,0xac,0x23,0xfc,0x2b,0x6a,0x8a,0x9f,0x65,\r
-0x4f,0xf9,0x57,0xdc,0x2e,0x48,0x76,0x30,0x1f,0xc0,0x9e,0x1e,0x93,0xef,0x68,0xd6,\r
-0x67,0xfe,0xd8,0x8a,0x89,0xbe,0x1c,0xf8,0x65,0xba,0xe8,0x96,0x7f,0xf7,0xec,0x57,\r
-0x49,0x45,0x4b,0xc3,0xd2,0x7b,0xc1,0x7d,0xc4,0xfb,0x28,0x3f,0xb2,0x8e,0x55,0xbe,\r
-0x17,0xf8,0x55,0xfa,0xe8,0x96,0x9f,0xf7,0xc5,0x42,0xdf,0x09,0x3c,0x22,0xdd,0x74,\r
-0x3b,0x5f,0xfb,0xe6,0xba,0xfa,0x5a,0x8f,0xaa,0xd0,0xfe,0x45,0xf7,0x21,0x7b,0x1a,\r
-0x5f,0xca,0xbe,0xe3,0x89,0x7f,0x83,0x7e,0x0e,0x7e,0xba,0x1d,0xb7,0xe5,0x50,0x3f,\r
-0xc0,0xff,0x00,0x05,0x3f,0xfc,0xc0,0xe0,0x1f,0x4c,0xd7,0x7b,0x45,0x4b,0xc1,0xe1,\r
-0xdf,0xfc,0xbb,0x5f,0x72,0x27,0xea,0xf4,0x7f,0x91,0x7d,0xc7,0x9e,0x3f,0xc0,0x5f,\r
-0x04,0xbf,0xfc,0xc1,0xa3,0x1f,0x46,0x35,0x0b,0xfe,0xcf,0x7e,0x09,0x7f,0xf9,0x85,\r
-0x63,0xe8,0xe6,0xbd,0x23,0x34,0x64,0x7a,0xd4,0x7d,0x47,0x0b,0xff,0x00,0x3e,0xd7,\r
-0xdc,0x88,0xfa,0xa5,0x0f,0xe4,0x5f,0x71,0xe6,0x0f,0xfb,0x39,0x78,0x25,0xff,0x00,\r
-0xe6,0x1c,0xc3,0xe8,0xf5,0x0b,0xfe,0xcd,0x5e,0x09,0x7f,0xf9,0x72,0x90,0x7d,0x24,\r
-0xaf,0x55,0xa2,0xa7,0xfb,0x3f,0x08,0xff,0x00,0xe5,0xda,0xfb,0x89,0xfa,0x96,0x19,\r
-0xef,0x4d,0x7d,0xc7,0x92,0x3f,0xec,0xc5,0xe0,0xb6,0xe9,0x05,0xc2,0xff,0x00,0xdb,\r
-0x4a,0x81,0xff,0x00,0x65,0xcf,0x07,0xb7,0x41,0x72,0xbf,0xf6,0xd2,0xbd,0x8e,0x8a,\r
-0x9f,0xec,0xcc,0x1b,0xff,0x00,0x97,0x4b,0xee,0x27,0xea,0x18,0x57,0xff,0x00,0x2e,\r
-0xd7,0xdc,0x78,0xb3,0xfe,0xca,0xbe,0x12,0x6e,0x92,0x5d,0x2f,0xfc,0x08,0x54,0x2f,\r
-0xfb,0x27,0xf8,0x5d,0xba,0x5c,0xdd,0x0f,0xc4,0x57,0xb7,0xd1,0x51,0xfd,0x95,0x82,\r
-0xff,0x00,0x9f,0x48,0x97,0x97,0x61,0x1f,0xfc,0xbb,0x47,0x84,0xbf,0xec,0x95,0xe1,\r
-0xb6,0xe9,0x7d,0x76,0x3f,0x2a,0xa5,0x77,0xfb,0x24,0x69,0xd0,0x95,0x9f,0x4e,0xd6,\r
-0x6e,0xed,0xae,0xe3,0x21,0xe2,0x90,0x60,0x15,0x61,0xd0,0x82,0x39,0x06,0xbe,0x83,\r
-0xa4,0x3d,0x29,0x7f,0x64,0xe0,0xf7,0x54,0xed,0xf7,0x99,0xbc,0xaf,0x07,0x2f,0xf9,\r
-0x76,0x8f,0x01,0xf0,0x97,0xc6,0x3d,0x4f,0xe1,0xff,0x00,0x89,0xd3,0xc2,0x5e,0x3e,\r
-0xb9,0x59,0xa1,0x77,0x10,0xda,0x6b,0xa4,0x6d,0xcb,0x67,0x01,0x66,0xed,0xcf,0x1f,\r
-0x3f,0xe7,0xeb,0x5e,0xfa,0x8c,0x18,0x70,0x72,0x3d,0x6b,0xe3,0x1f,0xda,0x88,0xa5,\r
-0xee,0xbb,0x24,0x4c,0x01,0x05,0x88,0xc7,0xad,0x77,0x1f,0xb1,0xff,0x00,0xc6,0x49,\r
-0xbc,0x47,0x65,0x79,0xe0,0x6d,0x66,0xe9,0xa6,0xd5,0xf4,0xa8,0x84,0xd6,0x53,0x4a,\r
-0xd9,0x79,0xed,0x72,0x06,0x09,0xee,0x63,0x25,0x47,0xd1,0x97,0xd2,0xb9,0x70,0x18,\r
-0xde,0x6a,0xd3,0xc3,0x4d,0xdf,0x95,0xe8,0xcf,0x23,0x07,0x98,0xfb,0x2c,0x6b,0xcb,\r
-0xea,0xbb,0xaf,0xb2,0xdf,0xe4,0xff,0x00,0x43,0xe9,0x8a,0x29,0x9b,0xbd,0xff,0x00,\r
-0x5a,0x2b,0xe8,0x8f,0xaa,0xe6,0x43,0xe8,0xa2,0x8a,0x45,0x05,0x14,0x51,0x40,0x05,\r
-0x79,0x0f,0xed,0x3d,0xe2,0xdf,0xf8,0x46,0xfe,0x1a,0xdc,0x5a,0x45,0x26,0xcb,0xad,\r
-0x55,0xc5,0xa2,0x60,0xf3,0xb3,0xac,0x9f,0xf8,0xe8,0x23,0xfe,0x05,0x5e,0xb8,0x49,\r
-0xed,0x5f,0x1b,0x7e,0xd4,0xbe,0x30,0x3a,0xff,0x00,0xc4,0x4f,0xec,0xb8,0xdf,0x75,\r
-0xae,0x93,0x10,0x8b,0x00,0x82,0x0c,0xad,0x86,0x73,0xf8,0x0d,0xa3,0xea,0x0d,0x78,\r
-0xf9,0xb6,0x23,0xea,0xf8,0x59,0x35,0xbb,0xd1,0x7c,0xcf,0x13,0x38,0xc4,0xfd,0x5b,\r
-0x07,0x26,0xb7,0x96,0x8b,0xe6,0x72,0x5f,0x06,0x7c,0x26,0x7c,0x5d,0xe3,0xed,0x32,\r
-0xd3,0x6e,0xe8,0x52,0x41,0x2c,0xb9,0xfe,0xe8,0xe6,0xbe,0xf6,0x8d,0x04,0x68,0xa8,\r
-0xa3,0x0a,0xa3,0x00,0x0f,0x4a,0xf9,0xd3,0xf6,0x49,0xf0,0x8f,0xd9,0xf4,0xfb,0xfd,\r
-0x7a,0x68,0xfe,0x79,0x4f,0x93,0x13,0x1f,0x4e,0xf5,0xf4,0x60,0xae,0x3c,0x8b,0x0f,\r
-0xec,0xb0,0xde,0xd1,0xef,0x2d,0x7e,0x5d,0x0c,0x32,0x2c,0x37,0xb0,0xc2,0x29,0x3d,\r
-0xe5,0xa8,0xb4,0x51,0x45,0x7d,0x21,0xf4,0x41,0x48,0x4e,0x29,0x6b,0x95,0xf8,0xad,\r
-0xe3,0x88,0x3e,0x19,0xfc,0x32,0xf1,0x5f,0x8b,0x6e,0x81,0x68,0x34,0x4d,0x2e,0xe7,\r
-0x50,0x65,0x03,0x39,0xf2,0xa3,0x67,0xc7,0xe3,0x8a,0x00,0xfc,0xfb,0xff,0x00,0x82,\r
-0x96,0x7f,0xc1,0x41,0x75,0x2f,0x01,0x6a,0xd7,0xbf,0x09,0xbe,0x1b,0x6a,0x06,0xcf,\r
-0x59,0x8e,0x30,0x35,0xcd,0x72,0x03,0x87,0xb6,0xdc,0x33,0xf6,0x68,0x5b,0xb3,0xed,\r
-0x20,0xb3,0x8f,0xbb,0xb8,0x01,0xce,0xec,0x7c,0x27,0xf0,0x53,0xf6,0x29,0xf8,0xcd,\r
-0xfb,0x4a,0x59,0xcb,0xaf,0x78,0x6b,0xc3,0xb2,0x4d,0xa4,0xc9,0x21,0x27,0x5a,0xd5,\r
-0xee,0x45,0xbc,0x33,0xbe,0x4e,0xe2,0xae,0xe7,0x32,0x1c,0x83,0x92,0xa0,0xe0,0xf5,\r
-0x35,0xe5,0x9a,0x76,0xab,0x1f,0x8f,0xbe,0x29,0xda,0x6a,0x3e,0x2e,0xbf,0x2b,0x0e,\r
-0xb3,0xac,0xa4,0xfa,0xb5,0xfb,0xb6,0xd2,0xa9,0x2c,0xe0,0xcf,0x21,0x3d,0xb0,0x19,\r
-0x8f,0xb5,0x7f,0x40,0x9f,0x1c,0x3e,0x24,0xe8,0x3f,0xb3,0x97,0xec,0xbf,0xae,0xf8,\r
-0x9b,0x43,0x5b,0x5b,0x7d,0x2b,0x46,0xd1,0x44,0x7a,0x34,0x36,0xa5,0x44,0x4c,0xcc,\r
-0xa2,0x3b,0x61,0x1e,0x38,0x20,0xb3,0x27,0x4e,0xdc,0xd3,0x25,0x6a,0x7f,0x3e,0x1e,\r
-0x2f,0xf0,0x4e,0xa1,0xe0,0xef,0x1d,0x6a,0xbe,0x13,0x9d,0xa1,0xbe,0xd5,0x74,0xeb,\r
-0xe7,0xd3,0xa4,0xfb,0x03,0x99,0x63,0x92,0x64,0x7d,0x85,0x50,0xe0,0x6e,0xf9,0x81,\r
-0x03,0x8e,0x71,0x5f,0xbd,0xbe,0x1c,0xf8,0x6b,0xa7,0x7e,0xce,0x7f,0xb0,0xcd,0xef,\r
-0x86,0x2e,0x84,0x51,0xc7,0xa3,0x78,0x42,0xed,0xf5,0x07,0xc6,0x16,0x4b,0x86,0xb7,\r
-0x91,0xe7,0x27,0xeb,0x23,0x30,0xfc,0xab,0xf2,0x6b,0xfe,0x09,0xd5,0xf0,0x92,0x7f,\r
-0x8e,0x9f,0xb5,0xbf,0x87,0xae,0x75,0x24,0x6b,0xed,0x3f,0x45,0x95,0xfc,0x45,0xa9,\r
-0xcb,0x29,0xfb,0xcd,0x11,0x06,0x32,0x4f,0x72,0xd3,0xb4,0x59,0xf5,0x19,0xaf,0xb2,\r
-0xff,0x00,0xe0,0xac,0x1f,0xb6,0x06,0x8d,0xa5,0x78,0x12,0xe7,0xe0,0xdf,0x85,0xb5,\r
-0x38,0x6f,0xf5,0xfd,0x52,0x44,0xfe,0xde,0x6b,0x67,0x0e,0xb6,0x56,0xc8,0x43,0x08,\r
-0x19,0x81,0xe2,0x47,0x60,0x99,0x5e,0x48,0x50,0x72,0x06,0xe1,0x40,0x2d,0x35,0x3f,\r
-0x2c,0xfe,0x17,0x78,0x72,0xe3,0xc6,0x1f,0x12,0xfc,0x27,0xa0,0xd9,0x0c,0xdd,0xea,\r
-0x7a,0xb5,0xa5,0x9c,0x5c,0xe3,0xe6,0x92,0x64,0x51,0xfc,0xeb,0xfa,0x6e,0x8d,0x3c,\r
-0xb4,0x55,0xeb,0x80,0x06,0x6b,0xf1,0x1f,0xfe,0x09,0x3f,0xf0,0x0e,0xe3,0xe2,0x67,\r
-0xed,0x0b,0x17,0x8c,0xaf,0x2d,0x0b,0xf8,0x7b,0xc1,0xa9,0xf6,0xb6,0x92,0x45,0x3b,\r
-0x1e,0xf1,0x81,0x10,0x20,0x3e,0xaa,0x73,0x27,0xb6,0xc1,0xeb,0x5f,0xb7,0x2c,0xc1,\r
-0x14,0x92,0x70,0x00,0xcd,0x0c,0x16,0xc7,0x81,0xfe,0xd2,0x7e,0x22,0x12,0xdd,0x69,\r
-0x9a,0x24,0x6d,0x91,0x18,0x37,0x52,0x8f,0x73,0x95,0x4f,0xd3,0x77,0xe6,0x2b,0xc4,\r
-0xab,0x7b,0xc7,0x5e,0x20,0x3e,0x28,0xf1,0x6e,0xa7,0xa9,0x64,0x98,0xe5,0x98,0x88,\r
-0xb3,0xd9,0x07,0x0b,0xfa,0x01,0x58,0x35,0xf8,0x96,0x67,0x89,0xfa,0xde,0x2e,0x75,\r
-0x56,0xd7,0xb2,0xf4,0x5a,0x1f,0x29,0x88,0xa9,0xed,0x6a,0xb9,0x06,0x68,0xa2,0x8c,\r
-0xd7,0x98,0x73,0x85,0x14,0x51,0x48,0x00,0x71,0x4e,0x49,0x5e,0x33,0x95,0x76,0x52,\r
-0x3b,0x83,0x8a,0x6d,0x14,0xd3,0x6b,0x60,0xb9,0xb5,0xa6,0xf8,0xd7,0x5f,0xd2,0x0a,\r
-0xfd,0x93,0x58,0xbd,0x84,0x2f,0x45,0x13,0x31,0x5f,0xc8,0xf1,0x5e,0x89,0xe1,0x6f,\r
-0xda,0x2b,0x56,0xb0,0x91,0x22,0xd6,0xed,0xd3,0x51,0xb7,0xef,0x2c,0x2a,0x12,0x51,\r
-0xf8,0x7d,0xd3,0xfa,0x7d,0x6b,0xc8,0x68,0xaf,0x43,0x0f,0x98,0xe2,0xb0,0xb2,0xbd,\r
-0x2a,0x8f,0xf4,0xfb,0x8d,0xe1,0x5e,0xa5,0x37,0x78,0xc8,0xfb,0x57,0xc3,0x5e,0x28,\r
-0xd3,0xbc,0x59,0xa6,0xa5,0xf6,0x9b,0x72,0xb7,0x10,0x31,0xc1,0xec,0xc8,0xdd,0xd5,\r
-0x87,0x63,0x5a,0xd5,0xf2,0x47,0xc2,0x6f,0x18,0x4f,0xe1,0x2f,0x17,0xda,0x10,0xe7,\r
-0xec,0x57,0x6e,0xb0,0x5c,0xc7,0x9e,0x08,0x27,0x01,0xbe,0xaa,0x4e,0x7f,0x3f,0x5a,\r
-0xfa,0xd9,0x4e,0x46,0x6b,0xf5,0x3c,0xa7,0x31,0x59,0x8d,0x0e,0x76,0xad,0x25,0xa3,\r
-0x3e,0x8b,0x0d,0x5f,0xdb,0xc2,0xfd,0x50,0x37,0x00,0xd7,0xcd,0x1f,0x15,0x3e,0x26,\r
-0xeb,0x51,0x78,0xeb,0x51,0xb7,0xd2,0xf5,0x5b,0x9b,0x5b,0x4b,0x56,0x10,0x04,0x89,\r
-0xf0,0xa5,0x94,0x7c,0xc7,0x1f,0xef,0x64,0x7e,0x15,0xf4,0x4e,0xbb,0xaa,0xc7,0xa1,\r
-0xe8,0xd7,0xda,0x84,0xdc,0xc5,0x6b,0x0b,0xcc,0xc0,0x75,0x21,0x41,0x38,0xfd,0x2b,\r
-0xe2,0x8b,0xbb,0xa9,0x2f,0x6e,0xa6,0xb8,0x95,0xb7,0xcb,0x33,0xb4,0x8e,0xc7,0xbb,\r
-0x13,0x92,0x6b,0xc6,0xe2,0x5c,0x64,0xe8,0xd3,0xa7,0x4a,0x9c,0xac,0xdb,0xbe,0x9d,\r
-0x8e,0x6c,0x7d,0x57,0x08,0xa8,0xc5,0xd8,0xea,0x13,0xe2,0xc7,0x8b,0xa3,0xe9,0xae,\r
-0xdd,0x7e,0x3b,0x4f,0xf3,0x15,0x32,0x7c,0x64,0xf1,0x94,0x7d,0x35,0xb9,0x0f,0xfb,\r
-0xd1,0x46,0x7f,0xf6,0x5a,0xe3,0x28,0xaf,0x82,0x58,0xec,0x52,0xda,0xac,0xbe,0xf6,\r
-0x78,0x9e,0xda,0xa7,0xf3,0x3f,0xbc,0xef,0x13,0xe3,0x8f,0x8c,0xd3,0xfe,0x62,0xc1,\r
-0xbf,0xde,0xb7,0x8b,0xff,0x00,0x89,0xab,0x09,0xf1,0xef,0xc6,0x0b,0xd6,0xf6,0x06,\r
-0xfa,0xdb,0xaf,0xf8,0x57,0x9d,0xd1,0x5a,0x2c,0xcb,0x1a,0xb6,0xad,0x2f,0xbd,0x97,\r
-0xf5,0x8a,0xbf,0xcc,0xcf,0x4a,0x5f,0xda,0x0b,0xc5,0xca,0x79,0x96,0xd1,0xff,0x00,\r
-0xde,0xb7,0xff,0x00,0x03,0x53,0xa7,0xed,0x17,0xe2,0xa4,0xeb,0x16,0x9c,0xff,0x00,\r
-0x58,0x1b,0xff,0x00,0x8b,0xaf,0x2e,0xa2,0xb4,0x59,0xb6,0x39,0x6d,0x59,0xfd,0xe3,\r
-0x58,0x9a,0xcb,0xed,0x33,0xd6,0x23,0xfd,0xa4,0xbc,0x48,0xbf,0x7a,0xcb,0x4e,0x6f,\r
-0xfb,0x66,0xe3,0xff,0x00,0x67,0xab,0x09,0xfb,0x4b,0x6b,0x60,0x7c,0xda,0x5d,0x8b,\r
-0x1f,0x6d,0xe3,0xfa,0xd7,0x8f,0xd1,0x56,0xb3,0x9c,0x7a,0xff,0x00,0x97,0xac,0x7f,\r
-0x5a,0xaf,0xfc,0xc7,0xb3,0x27,0xed,0x33,0xaa,0x0f,0xbd,0xa2,0xda,0xb7,0xd2,0x56,\r
-0x1f,0xd2,0xa7,0x5f,0xda,0x6e,0xef,0xf8,0xb4,0x08,0x7f,0x0b,0xa3,0xff,0x00,0xc4,\r
-0xd7,0x89,0x51,0xfa,0xd6,0xab,0x3c,0xcc,0x3a,0x55,0xfc,0x17,0xf9,0x14,0xb1,0x95,\r
-0xff,0x00,0x98,0xfb,0x1b,0xe1,0xef,0x8b,0x26,0xf1,0xb7,0x86,0x61,0xd5,0xa5,0xb3,\r
-0x16,0x42,0x67,0x75,0x48,0xc3,0xee,0xc8,0x52,0x57,0x39,0xc0,0xee,0x0d,0x74,0xb5,\r
-0x89,0xe0,0xad,0x23,0xfb,0x03,0xc2,0x9a,0x56,0x9e,0x7e,0xf4,0x16,0xe8,0xaf,0xee,\r
-0xd8,0xcb,0x1f,0xcf,0x35,0xb4,0x6b,0xf5,0xac,0x3f,0x3f,0xb1,0x87,0xb5,0x77,0x95,\r
-0x95,0xfd,0x4f,0xa5,0x85,0xf9,0x17,0x36,0xe2,0xd2,0x13,0x8a,0xaf,0x7b,0x7f,0x6f,\r
-0xa7,0x5a,0x49,0x73,0x75,0x3c,0x76,0xf6,0xf1,0x8d,0xcf,0x2c,0xac,0x15,0x54,0x7a,\r
-0x92,0x6b,0xc7,0x3c,0x65,0xfb,0x45,0xdb,0xda,0xb3,0xdb,0x78,0x7a,0xdf,0xed,0x72,\r
-0x0e,0x3e,0xd9,0x70,0x08,0x8f,0xea,0xab,0xd4,0xfe,0x38,0xfc,0x6b,0x0c,0x5e,0x3b,\r
-0x0f,0x82,0x8f,0x35,0x69,0x5b,0xcb,0xaf,0xdc,0x4d,0x5a,0xd0,0xa4,0xaf,0x36,0x7b,\r
-0x51,0x70,0xa3,0x24,0xe0,0x7a,0x9a,0xe5,0xf5,0x8f,0x8a,0x3e,0x16,0xd0,0xb7,0x0b,\r
-0x9d,0x6a,0xd8,0xba,0x9c,0x18,0xe0,0x6f,0x39,0x81,0xf7,0x09,0x92,0x2b,0xe5,0xbf,\r
-0x10,0xf8,0xe3,0x5d,0xf1,0x4c,0x8c,0xda,0x96,0xa5,0x34,0xe8,0x4e,0x7c,0xa0,0xdb,\r
-0x63,0x1f,0x45,0x18,0x15,0x85,0xd2,0xbe,0x33,0x11,0xc5,0x2f,0x6c,0x3d,0x3f,0x9b,\r
-0xff,0x00,0x25,0xfe,0x67,0x95,0x3c,0xc7,0xf9,0x23,0xf7,0x9f,0x4b,0xdf,0xfe,0xd1,\r
-0x7e,0x19,0xb6,0x72,0xb0,0x45,0x7d,0x79,0xe8,0xd1,0xc4,0x15,0x7f,0xf1,0xe6,0x07,\r
-0xf4,0xac,0xb9,0xbf,0x69,0x9d,0x31,0x4f,0xee,0x74,0x6b,0xb7,0x1f,0xed,0xc8,0xab,\r
-0xfc,0xb3,0x5f,0x3e,0x51,0x5e,0x44,0xb8,0x8f,0x1f,0x2d,0x9a,0x5f,0x2f,0xf3,0x39,\r
-0x5e,0x3a,0xb3,0xea,0x7b,0xfa,0xfe,0xd3,0x76,0x64,0xfc,0xda,0x14,0xe0,0x7b,0x4e,\r
-0xa7,0xfa,0x55,0xb8,0xbf,0x69,0x6d,0x10,0xe3,0xcc,0xd2,0xf5,0x04,0xf5,0xda,0x23,\r
-0x6f,0xfd,0x98,0x57,0xce,0xb4,0x54,0xae,0x21,0xcc,0x17,0xda,0x4f,0xe4,0x84,0xb1,\r
-0xd5,0xfb,0x9f,0x53,0x58,0x7c,0x7b,0xf0,0x85,0xe8,0x4f,0x32,0xf2,0x6b,0x36,0x6f,\r
-0xe1,0x9e,0xdd,0xb8,0xfa,0x95,0x04,0x7e,0xb5,0xd8,0xe9,0x3e,0x25,0xd2,0xb5,0xe0,\r
-0x4e,0x9d,0xa9,0x5a,0xde,0xe0,0x64,0x88,0x25,0x56,0x23,0xea,0x07,0x4a,0xf8,0xa2,\r
-0x9d,0x14,0xaf,0x04,0x8a,0xf1,0xbb,0x46,0xeb,0xca,0xb2,0x1c,0x11,0xf4,0x22,0xbd,\r
-0x0a,0x3c,0x51,0x88,0x8b,0xfd,0xf4,0x13,0x5e,0x5a,0x3f,0xd4,0xde,0x19,0x8c,0xd7,\r
-0xc4,0xae,0x7d,0xcf,0x9c,0x9e,0xb4,0xb5,0xf2,0xcf,0x84,0xfe,0x39,0x78,0x8b,0xc3,\r
-0xae,0x91,0xdd,0x4d,0xfd,0xaf,0x68,0x3a,0xc7,0x72,0x7e,0x70,0x3d,0x9f,0xaf,0xe7,\r
-0x9a,0xf7,0xbf,0x04,0x7c,0x49,0xd1,0xfc,0x75,0x6e,0x4d,0x94,0xde,0x55,0xda,0x0c,\r
-0xc9,0x69,0x36,0x04,0x8b,0xee,0x3d,0x47,0xb8,0xaf,0xaf,0xc0,0xe7,0x18,0x5c,0x73,\r
-0xe5,0x83,0xb4,0xbb,0x3f,0xd0,0xf4,0xe8,0xe2,0xa9,0xd6,0xd1,0x3b,0x33,0xac,0xa2,\r
-0x90,0x1c,0x8a,0x5a,0xf7,0x0e,0xc0,0xa2,0x8a,0x28,0x00,0xa2,0x90,0x9c,0x57,0x3b,\r
-0xe2,0x9f,0x88,0x1a,0x1f,0x83,0x93,0x3a,0x9d,0xfc,0x71,0x4a,0x46,0x44,0x09,0xf3,\r
-0xc8,0xdf,0xf0,0x11,0xce,0x3d,0xcf,0x15,0x95,0x4a,0xb0,0xa5,0x1e,0x6a,0x92,0xb2,\r
-0xf3,0x26,0x52,0x51,0x57,0x93,0x3a,0x3a,0x4c,0xd7,0x84,0x6b,0xdf,0xb4,0xb3,0x1d,\r
-0xc9,0xa3,0xe9,0x20,0x0e,0xd2,0xde,0x3f,0x3f,0xf7,0xc2,0xff,0x00,0xf1,0x55,0xc3,\r
-0xea,0x7f,0x1b,0x7c,0x5f,0xa9,0x13,0xff,0x00,0x13,0x31,0x68,0xa7,0xf8,0x6d,0xa2,\r
-0x55,0xc7,0xe3,0x82,0x7f,0x5a,0xf9,0xca,0xfc,0x45,0x81,0xa5,0xa4,0x5b,0x97,0xa2,\r
-0xff,0x00,0x33,0x82,0x78,0xea,0x31,0xd1,0x6a,0x7d,0x5d,0x9f,0xca,0x8d,0xc3,0xd6,\r
-0xbe,0x30,0xba,0xf1,0xaf,0x88,0x2f,0x73,0xe7,0xeb,0x7a,0x84,0x80,0xf5,0x06,0xe5,\r
-0xf1,0xf9,0x66,0xb3,0x1e,0xfa,0xe6,0x43,0x96,0xb8,0x95,0x89,0xee,0xce,0x4d,0x79,\r
-0x92,0xe2,0xaa,0x6b,0xe1,0xa4,0xfe,0xff,0x00,0xf8,0x07,0x3b,0xcc,0xa3,0xd2,0x27,\r
-0xdc,0x04,0x2b,0x1f,0x9b,0x69,0xfa,0xd3,0x86,0xd0,0x30,0x00,0xfc,0x2b,0xe1,0xbf,\r
-0xb5,0xcf,0xff,0x00,0x3d,0xa4,0xff,0x00,0xbe,0x8d,0x58,0xb6,0xd7,0x35,0x2b,0x33,\r
-0x9b,0x7d,0x42,0xea,0x03,0xeb,0x1c,0xcc,0xbf,0xc8,0xd4,0xae,0x2a,0x87,0x5a,0x3f,\r
-0x8f,0xfc,0x01,0x7f,0x69,0x2e,0xb1,0xfc,0x4f,0xb6,0xb6,0xa9,0x3d,0x06,0x69,0xd9,\r
-0xe3,0x8a,0xf8,0xe6,0xd3,0xe2,0x37,0x8a,0x2c,0xbf,0xd5,0x6b,0xd7,0xff,0x00,0x47,\r
-0x9d,0x9c,0x7f,0xe3,0xd9,0xae,0x82,0xc3,0xe3,0xcf,0x8b,0xec,0x48,0xdf,0x75,0x05,\r
-0xea,0x8e,0xd3,0xc0,0xbf,0xcd,0x71,0x5d,0x74,0xf8,0x9f,0x0b,0x2f,0x8e,0x2d,0x7d,\r
-0xcc,0xda,0x39,0x85,0x37,0xba,0x68,0xfa,0xa2,0x90,0xf1,0x5e,0x27,0xe1,0x2f,0xda,\r
-0x22,0x6d,0x5f,0x53,0xb3,0xd3,0xef,0xb4,0x61,0xe6,0xdc,0xca,0x90,0xac,0x96,0xb2,\r
-0x7f,0x13,0x10,0x07,0xca,0xdf,0x5f,0x5a,0xf6,0xc1,0xc8,0x15,0xf4,0x78,0x4c,0x75,\r
-0x0c,0x74,0x5c,0xa8,0x4a,0xf6,0x3b,0xa9,0x56,0x85,0x65,0x78,0x30,0x56,0x0e,0xa0,\r
-0x8e,0x86,0x96,0x9a,0xab,0xb4,0x60,0x74,0xa7,0x57,0x79,0xb0,0x53,0x5c,0xe1,0x49,\r
-0xf4,0x14,0xea,0x8a,0xe9,0xfc,0xbb,0x69,0x5b,0xd1,0x09,0xfd,0x29,0x3d,0x80,0xf8,\r
-0x93,0xf6,0x80,0xb9,0xfb,0x47,0x8a,0xe4,0x5c,0xe7,0x04,0xd7,0x87,0xe8,0xfe,0x3c,\r
-0x97,0xe1,0x5f,0xc5,0x4f,0x09,0x78,0xaa,0x10,0x0a,0x5a,0x5f,0x24,0x57,0x0a,0x4e,\r
-0x03,0x41,0x27,0xee,0xe4,0x07,0xfe,0x02,0xc4,0x8f,0x70,0x3d,0x2b,0xd6,0xbe,0x33,\r
-0x5c,0x79,0xde,0x2d,0xb8,0x39,0xce,0x33,0x5f,0x2e,0x7c,0x77,0xba,0x30,0xe8,0x72,\r
-0xed,0x38,0x60,0xa4,0x8c,0x7a,0xd7,0xe7,0x18,0x29,0x37,0x8e,0x94,0x97,0x76,0x7e,\r
-0x39,0x8f,0xa9,0x25,0x9a,0x53,0x9c,0x77,0xe7,0x47,0xec,0x77,0xdb,0x61,0xff,0x00,\r
-0x9e,0xc9,0xf9,0xd1,0x5e,0x03,0xfd,0x91,0x7b,0xff,0x00,0x3f,0x72,0xff,0x00,0xdf,\r
-0x46,0x8a,0xfd,0x0f,0x9d,0x9f,0xaf,0x73,0x79,0x1f,0x44,0xd1,0x45,0x15,0xa9,0xa8,\r
-0x51,0x45,0x14,0x01,0x93,0xe2,0x9d,0x7a,0x1f,0x0b,0xf8,0x77,0x53,0xd5,0xae,0x48,\r
-0xf2,0x6c,0xed,0xde,0x76,0x1e,0xbb,0x41,0x38,0xfc,0x4f,0x15,0xf9,0xe8,0xf3,0x5d,\r
-0x78,0x97,0x5b,0x92,0x79,0x4b,0x4d,0x79,0x7d,0x39,0x76,0x3d,0x49,0x66,0x6c,0xff,\r
-0x00,0x5a,0xfa,0x97,0xf6,0xb9,0xf1,0x6b,0x69,0x9e,0x11,0xb1,0xd0,0xa0,0x90,0x2c,\r
-0xba,0x9c,0xdb,0xe5,0x51,0x8c,0xf9,0x51,0xf3,0xfa,0xb1,0x5f,0xc8,0xd7,0x8e,0x7e,\r
-0xce,0xde,0x11,0xff,0x00,0x84,0xa3,0xe2,0x15,0xa3,0xc8,0xbb,0xad,0xac,0xff,0x00,\r
-0x7e,0xfc,0x71,0xc7,0x41,0xf9,0xd7,0xc3,0xe7,0x33,0x78,0xac,0x54,0x30,0x90,0xfe,\r
-0x9b,0xff,0x00,0x80,0x7c,0x26,0x6f,0x27,0x8c,0xc7,0x53,0xc2,0x47,0x65,0xbf,0xab,\r
-0xff,0x00,0x80,0x7d,0x75,0xf0,0xeb,0xc3,0x51,0xf8,0x4f,0xc1,0xba,0x5e,0x9a,0x8b,\r
-0xb5,0xa2,0x84,0x17,0xf7,0x62,0x32,0x6b,0xa4,0x03,0x14,0x2f,0x02,0x96,0xbe,0xd2,\r
-0x9c,0x15,0x38,0x28,0x47,0x64,0x7d,0xc4,0x22,0xa1,0x15,0x15,0xb2,0x0a,0x28,0xa2,\r
-0xb4,0x2c,0x2b,0x88,0xf8,0xe1,0xe0,0x17,0xf8,0xa9,0xf0,0x77,0xc6,0xbe,0x0f,0x8e,\r
-0x5f,0x22,0x5d,0x73,0x48,0xba,0xb0,0x8e,0x53,0xfc,0x0f,0x24,0x4c,0xaa,0x7f,0x02,\r
-0x45,0x76,0xf4,0x84,0x66,0x80,0x3f,0x97,0xbf,0x12,0xf8,0x6f,0x53,0xf0,0x77,0x88,\r
-0x75,0x2d,0x0f,0x59,0xb3,0x97,0x4f,0xd5,0x74,0xeb,0x87,0xb5,0xba,0xb5,0x9d,0x70,\r
-0xf1,0x48,0xa4,0x86,0x52,0x3e,0xa2,0xb4,0xa7,0xf8,0x99,0xe2,0xdb,0x9f,0x06,0x0f,\r
-0x08,0x4d,0xe2,0x5d,0x56,0x6f,0x0b,0x09,0x56,0x71,0xa3,0x49,0x79,0x23,0x5a,0xac,\r
-0x8b,0x9d,0xac,0x23,0x27,0x68,0x23,0x27,0xa0,0xef,0x5f,0xbd,0xff,0x00,0xb4,0x67,\r
-0xec,0x2b,0xf0,0x9f,0xf6,0x99,0xb8,0x6d,0x4b,0xc4,0xba,0x3c,0xba,0x77,0x88,0xf6,\r
-0x04,0x1a,0xee,0x8f,0x20,0x82,0xe9,0x80,0x18,0x01,0xf8,0x29,0x26,0x07,0x03,0x7a,\r
-0x92,0x07,0x00,0x81,0x5f,0x2a,0x6a,0xbf,0xf0,0x44,0xcf,0x0c,0x49,0x76,0x0e,0x99,\r
-0xf1,0x3b,0x56,0xb6,0xb5,0xef,0x1d,0xde,0x9b,0x14,0xcf,0x8f,0xf7,0x95,0x90,0x7e,\r
-0x95,0x57,0x22,0xcf,0xa1,0xf9,0x77,0xe0,0xff,0x00,0x89,0x7e,0x2c,0xf8,0x7d,0x0e,\r
-0xa7,0x17,0x86,0x3c,0x45,0xa9,0x78,0x7d,0x75,0x38,0x84,0x17,0x9f,0xd9,0xb7,0x2f,\r
-0x03,0x4f,0x18,0x24,0x84,0x62,0xa4,0x12,0x32,0x4f,0x15,0xdb,0xfe,0xcf,0x3f,0xb3,\r
-0x4f,0x8e,0xff,0x00,0x6a,0x2f,0x1c,0x47,0xa3,0x78,0x5a,0xc6,0x49,0x63,0xf3,0x03,\r
-0x6a,0x1a,0xcd,0xc8,0x3f,0x66,0xb3,0x42,0x79,0x79,0x1f,0xb9,0xeb,0x85,0x19,0x66,\r
-0x3d,0x2b,0xf5,0x27,0xe1,0xef,0xfc,0x11,0xd7,0xe0,0xf7,0x86,0x2f,0xe1,0xbb,0xf1,\r
-0x1e,0xad,0xe2,0x0f,0x18,0x98,0xf9,0x36,0x97,0x17,0x0b,0x6b,0x6e,0xc7,0xdc,0x44,\r
-0xa1,0xff,0x00,0x0d,0xf5,0xf6,0xa7,0x82,0x3c,0x03,0xe1,0xcf,0x86,0xbe,0x1e,0xb6,\r
-0xd0,0x7c,0x2b,0xa2,0x58,0xf8,0x7f,0x47,0xb7,0x1f,0xbb,0xb3,0xd3,0xe0,0x58,0xa3,\r
-0x07,0xb9,0x20,0x0e,0x58,0xf7,0x63,0xc9,0xee,0x69,0x5c,0x12,0xee,0x71,0xdf,0xb3,\r
-0x97,0xec,0xfd,0xe1,0xbf,0xd9,0xab,0xe1,0x7e,0x9d,0xe0,0xcf,0x0d,0xc6,0x5a,0x38,\r
-0x7f,0x7b,0x77,0x7d,0x22,0x81,0x35,0xed,0xc3,0x01,0xbe,0x67,0x3e,0xa7,0x00,0x01,\r
-0xd8,0x00,0x07,0x02,0xb6,0x7e,0x30,0xf8,0x8c,0x78,0x6f,0xc0,0x7a,0x8c,0x8a,0xc1,\r
-0x6e,0x2e,0x57,0xec,0xb0,0xf3,0x83,0xb9,0xf8,0x24,0x7b,0x85,0xdc,0x7f,0x0a,0xed,\r
-0xeb,0xe7,0x8f,0xda,0x43,0xc4,0x5f,0x6b,0xd6,0x6c,0x34,0x68,0xdf,0x29,0x6b,0x19,\r
-0x9e,0x50,0x3a,0x6f,0x6e,0x07,0xe4,0x07,0xfe,0x3d,0x5e,0x2e,0x6f,0x89,0xfa,0xae,\r
-0x0e,0x73,0x5b,0xbd,0x17,0xab,0xd0,0xe7,0xc5,0x54,0xf6,0x74,0x9b,0x3c,0x6e,0x8a,\r
-0x28,0xaf,0xc6,0x0f,0x95,0x0a,0xf6,0xff,0x00,0xd9,0xcf,0xc2,0x90,0x5e,0xc5,0xaa,\r
-0xea,0xf7,0x76,0xf1,0x4e,0x99,0x16,0xd1,0x09,0x50,0x30,0xc8,0xf9,0x98,0xe0,0xfd,\r
-0x57,0xf5,0xaf,0x10,0xaf,0xb0,0xbe,0x1a,0x78,0x74,0xf8,0x63,0xc1,0x1a,0x4d,0x8b,\r
-0xa9,0x59,0xc4,0x5e,0x64,0xc0,0x8c,0x10,0xee,0x77,0x30,0xfc,0x09,0xc7,0xe1,0x5f,\r
-0x57,0xc3,0xb8,0x5f,0x6f,0x8b,0xf6,0x92,0x5a,0x45,0x7e,0x2f,0x44,0x7a,0x58,0x0a,\r
-0x7c,0xf5,0x79,0x9f,0x43,0x4e,0x4f,0x09,0xe8,0x93,0x0f,0xde,0x69,0x16,0x2f,0xf5,\r
-0xb6,0x43,0xfd,0x2b,0x36,0xf3,0xe1,0x87,0x85,0x2f,0x91,0x96,0x4d,0x02,0xc5,0x41,\r
-0xea,0x62,0x84,0x46,0x7f,0x35,0xc1,0xae,0x9c,0x0c,0x51,0x5f,0xa6,0xcb,0x0f,0x46,\r
-0x5f,0x14,0x13,0xf9,0x23,0xe8,0x1d,0x38,0x3d,0xd2,0x3c,0x33,0xe2,0x17,0xc0,0x1b,\r
-0x3b,0x6d,0x3a,0xe3,0x50,0xf0,0xf3,0xcb,0x1c,0x90,0xa1,0x76,0xb3,0x95,0xb7,0x87,\r
-0x03,0x93,0xb5,0x8f,0x39,0xfa,0x93,0x9f,0x6a,0xf0,0x8a,0xfb,0x2b,0xc7,0x7e,0x21,\r
-0x83,0xc3,0x3e,0x14,0xd4,0x6f,0xe6,0x20,0x6c,0x89,0x95,0x14,0xff,0x00,0x1b,0x91,\r
-0x85,0x1f,0x99,0xaf,0x8d,0x40,0xc0,0x02,0xbf,0x34,0xe2,0x2c,0x2e,0x1b,0x0d,0x5a,\r
-0x1e,0xc1,0x59,0xb5,0xaa,0x5f,0x81,0xe0,0x63,0xa9,0xc2,0x9c,0xd7,0x26,0x81,0x45,\r
-0x14,0x57,0xc9,0x1e,0x61,0x6f,0x49,0xb5,0x7b,0xed,0x56,0xce,0xde,0x21,0x99,0x25,\r
-0x99,0x23,0x5c,0x7a,0x96,0x00,0x7f,0x3a,0xfb,0x79,0x38,0x50,0x2b,0xe5,0xdf,0x81,\r
-0x3e,0x13,0x6f,0x10,0x78,0xce,0x2b,0xc9,0x13,0x75,0xa6,0x9a,0x3c,0xf7,0x24,0x70,\r
-0x64,0xe8,0x83,0xeb,0x9f,0x9b,0xfe,0x03,0x5f,0x51,0x81,0x5f,0xa5,0xf0,0xc5,0x09,\r
-0x53,0xc3,0xce,0xab,0xfb,0x4f,0x4f,0x91,0xef,0xe5,0xd0,0x71,0x83,0x93,0xea,0x61,\r
-0x78,0xdb,0xc3,0x4f,0xe2,0xff,0x00,0x0e,0x5d,0xe9,0x2b,0x78,0xf6,0x22,0xe3,0x68,\r
-0x69,0x91,0x37,0x10,0x03,0x02,0x46,0x32,0x3a,0xe3,0x15,0xe4,0xf2,0x7e,0xcc,0x63,\r
-0xf8,0x3c,0x40,0x7f,0xe0,0x56,0x9f,0xfd,0x9d,0x7b,0xb5,0x26,0x2b,0xe8,0x71,0x59,\r
-0x6e,0x17,0x19,0x25,0x3a,0xf0,0xbb,0xf5,0x67,0x75,0x4c,0x3d,0x3a,0xae,0xf3,0x57,\r
-0x3c,0x09,0xff,0x00,0x66,0x4b,0xaf,0xe0,0xd7,0xa1,0x3f,0xef,0x5b,0x11,0xff,0x00,\r
-0xb3,0x55,0x77,0xfd,0x99,0xf5,0x31,0xf7,0x35,0xab,0x46,0xfa,0xc4,0xc2,0xbe,0x85,\r
-0xc5,0x52,0xd6,0x35,0x38,0xb4,0x7d,0x2a,0xf2,0xfa,0x63,0x88,0xad,0xa2,0x79,0x58,\r
-0xfb,0x28,0x26,0xbc,0xe9,0xe4,0x39,0x72,0x4d,0xb8,0x5b,0xe6,0xff,0x00,0xcc,0xc1,\r
-0xe0,0xa8,0x2d,0x6c,0x7c,0x65,0xe2,0x0d,0x20,0xe8,0x1a,0xdd,0xee,0x9a,0xd7,0x11,\r
-0xdc,0xbd,0xac,0x86,0x26,0x92,0x20,0x42,0x96,0x1d,0x40,0xcf,0xa1,0xc8,0xfc,0x2b,\r
-0x3e,0xa6,0xbc,0xba,0x96,0xfe,0xee,0x6b,0x99,0xdb,0x7c,0xf3,0x3b,0x49,0x23,0x7a,\r
-0xb1,0x39,0x27,0xf3,0x35,0x0d,0x7e,0x51,0x53,0x95,0xcd,0xb8,0x2d,0x2f,0xa1,0xf3,\r
-0x4e,0xd7,0x76,0x0a,0x28,0xad,0x2f,0x0d,0xe9,0x2d,0xaf,0x78,0x83,0x4d,0xd3,0xd4,\r
-0x13,0xf6,0x9b,0x84,0x8c,0xe3,0xb2,0x93,0xc9,0xfc,0xb3,0x4a,0x10,0x75,0x24,0xa0,\r
-0xb7,0x6e,0xc1,0x15,0x76,0x91,0xd2,0xda,0xfc,0x17,0xf1,0x7d,0xe5,0xa4,0x37,0x30,\r
-0xe9,0x41,0xe2,0x99,0x04,0x88,0x7c,0xf8,0xc1,0xc1,0x19,0x19,0x05,0xb8,0xa4,0x93,\r
-0xe0,0xb7,0x8c,0xe3,0xeb,0xa2,0x39,0xff,0x00,0x76,0x68,0x8f,0xfe,0xcd,0x5f,0x59,\r
-0x43,0x1a,0xc5,0x12,0x22,0x8d,0xaa,0xa0,0x00,0x07,0x61,0x4e,0xc7,0xbd,0x7e,0x99,\r
-0xfe,0xac,0x61,0x1a,0x5e,0xf4,0xaf,0xea,0xbf,0xc8,0xf7,0xff,0x00,0xb3,0xa9,0xf7,\r
-0x67,0xc8,0x12,0x7c,0x2a,0xf1,0x6c,0x47,0xe6,0xd0,0x6e,0xcf,0xfb,0xaa,0x0f,0xf2,\r
-0x35,0xa1,0xe1,0x2f,0x86,0x1e,0x20,0x9b,0xc5,0x3a,0x52,0x5e,0xe8,0xb7,0x50,0x5a,\r
-0x7d,0xa5,0x1a,0x67,0x9a,0x22,0x10,0x20,0x39,0x6c,0x9f,0x70,0x31,0x5f,0x57,0x8a,\r
-0x31,0x44,0x38,0x67,0x0d,0x09,0xa9,0x29,0xbd,0x3d,0x06,0xb2,0xfa,0x69,0xde,0xec,\r
-0x07,0x02,0xb1,0x7c,0x59,0xe2,0xed,0x3f,0xc1,0xba,0x3c,0x9a,0x86,0xa1,0x2e,0xc8,\r
-0xc7,0xca,0x91,0xaf,0xdf,0x95,0xbb,0x2a,0x8e,0xe7,0xf9,0x75,0x35,0x7f,0x56,0xd5,\r
-0x6d,0xb4,0x4d,0x36,0xe6,0xfa,0xf2,0x51,0x0d,0xb4,0x08,0x64,0x91,0xcf,0x60,0x3f,\r
-0xcf,0x4a,0xf9,0x1b,0xe2,0x07,0x8e,0x6e,0xfc,0x77,0xae,0xbd,0xe4,0xe5,0xa3,0xb6,\r
-0x8c,0x95,0xb6,0xb7,0xcf,0x11,0x27,0xf8,0x9e,0xe7,0xfa,0x62,0xbd,0x1c,0xdb,0x34,\r
-0x8e,0x5d,0x4a,0xd1,0xd6,0x6f,0x65,0xfa,0xb3,0x7c,0x4e,0x21,0x50,0x8e,0x9b,0xb2,\r
-0x6f,0x1e,0x7c,0x48,0xd5,0x3c,0x79,0x78,0x5a,0xe5,0xcd,0xbd,0x8a,0x1c,0xc5,0x67,\r
-0x1b,0x1d,0x8b,0xe8,0x4f,0xf7,0x9b,0xdc,0xfe,0x18,0xae,0x4e,0x8a,0x2b,0xf2,0x5a,\r
-0xd5,0xaa,0x62,0x26,0xea,0x55,0x77,0x6c,0xf9,0x99,0x4e,0x53,0x7c,0xd2,0x7a,0x85,\r
-0x14,0x57,0x5d,0xe0,0x0f,0x86,0x9a,0xa7,0x8f,0xae,0x8f,0xd9,0x80,0xb7,0xb1,0x8d,\r
-0xb1,0x2d,0xe4,0x83,0xe5,0x1f,0xec,0x81,0xfc,0x4d,0xed,0xf9,0xd3,0xa3,0x46,0xa6,\r
-0x22,0x6a,0x9d,0x25,0x76,0xc7,0x08,0x4a,0xa4,0xb9,0x62,0xae,0xce,0x46,0xa7,0xb7,\r
-0xb1,0xb9,0xbc,0xff,0x00,0x51,0x6f,0x2c,0xf8,0xeb,0xe5,0xa1,0x6f,0xe5,0x5f,0x55,\r
-0xf8,0x5f,0xe0,0xe7,0x86,0x7c,0x35,0x12,0x11,0x60,0x97,0xf7,0x23,0x19,0x9e,0xf0,\r
-0x09,0x0e,0x7d,0x40,0x3f,0x28,0xfc,0x05,0x76,0xc9,0x0a,0x46,0x00,0x55,0x0a,0x07,\r
-0x18,0x03,0x02,0xbe,0xce,0x87,0x0b,0x54,0x94,0x6f,0x5a,0xa2,0x4f,0xb2,0x57,0xfc,\r
-0x74,0x3d,0x58,0x65,0xd2,0x7f,0x1c,0xac,0x7c,0x3f,0x71,0xa7,0x5d,0xda,0x0c,0xcf,\r
-0x6b,0x34,0x23,0xd6,0x48,0xca,0xff,0x00,0x31,0x55,0xeb,0xee,0x96,0x8d,0x5d,0x48,\r
-0x60,0x08,0x3d,0x8d,0x71,0xde,0x29,0xf8,0x4d,0xe1,0xcf,0x15,0x42,0xfe,0x6d,0x8a,\r
-0x59,0xdd,0x31,0x2c,0x2e,0xad,0x00,0x8d,0xf7,0x7a,0x9c,0x70,0xdf,0x88,0x34,0xeb,\r
-0xf0,0xb5,0x48,0xc6,0xf4,0x6a,0x5d,0xf6,0x6a,0xc1,0x3c,0xb9,0xa5,0xee,0x4a,0xe7,\r
-0xc8,0xf4,0x57,0x4b,0xe3,0xbf,0x02,0x5f,0xf8,0x0f,0x56,0xfb,0x25,0xd8,0xf3,0x61,\r
-0x93,0x2d,0x05,0xca,0x8c,0x2c,0x8b,0xfd,0x08,0xee,0x3d,0xeb,0x9a,0xaf,0x89,0xab,\r
-0x4a,0x74,0x26,0xe9,0xd4,0x56,0x68,0xf2,0x65,0x17,0x07,0xcb,0x2d,0xc2,0xac,0x69,\r
-0xfa,0x85,0xce,0x95,0x7b,0x0d,0xdd,0x9c,0xef,0x6d,0x73,0x0b,0x6e,0x8e,0x58,0xdb,\r
-0x05,0x4d,0x57,0xa2,0xb3,0x4d,0xc5,0xa7,0x1d,0x1a,0x25,0x3b,0x6a,0x8f,0xaa,0xfe,\r
-0x13,0xfc,0x4d,0x8f,0xc7,0x9a,0x61,0x86,0xe3,0x6c,0x5a,0xb5,0xb2,0x8f,0x3a,0x31,\r
-0xc0,0x91,0x7f,0xbe,0xbe,0xde,0xa3,0xb1,0xfa,0x8a,0xef,0xc5,0x7c,0x59,0xe1,0x3f,\r
-0x12,0xdc,0x78,0x47,0xc4,0x16,0x7a,0xad,0xb1,0x25,0xe0,0x6f,0x99,0x33,0xfe,0xb1,\r
-0x0f,0xde,0x53,0xf5,0x19,0xaf,0xb2,0xf4,0xeb,0xd8,0x75,0x2b,0x0b,0x7b,0xbb,0x77,\r
-0x12,0x41,0x3c,0x6b,0x24,0x6c,0x3a,0x15,0x23,0x20,0xd7,0xeb,0x39,0x16,0x64,0xf1,\r
-0xd4,0x5c,0x2a,0x3f,0x7e,0x3b,0xf9,0xae,0x8c,0xfa,0x5c,0x1d,0x77,0x5a,0x16,0x96,\r
-0xe8,0xb3,0x48,0x4e,0xd1,0x93,0x41,0xaf,0x29,0xf8,0xf9,0xe3,0x99,0x3c,0x3f,0xa2,\r
-0x45,0xa4,0xd9,0xc8,0x52,0xf3,0x50,0x07,0x7b,0x29,0xe5,0x22,0x1d,0x7f,0x3e,0x9f,\r
-0x4c,0xd7,0xb5,0x8b,0xc4,0xc3,0x07,0x46,0x55,0xa7,0xb2,0x3a,0xea,0xd4,0x54,0xa0,\r
-0xe6,0xfa,0x1c,0xff,0x00,0xc5,0x1f,0x8e,0xb2,0x2c,0xb3,0x69,0x5e,0x1b,0x94,0x2e,\r
-0xdc,0xa4,0xba,0x82,0xf3,0xcf,0x71,0x1f,0xff,0x00,0x15,0xf9,0x7a,0xd7,0x87,0x4f,\r
-0x3c,0xb7,0x33,0x3c,0xb3,0x48,0xf2,0xca,0xec,0x59,0x9d,0xd8,0xb3,0x31,0x3d,0x49,\r
-0x26,0x99,0x45,0x7e,0x39,0x8d,0xc7,0xd7,0xc7,0xd4,0xe7,0xaa,0xfd,0x17,0x44,0x7c,\r
-0xb5,0x5a,0xd3,0xac,0xef,0x20,0xa2,0x8a,0x2b,0xce,0x30,0x0a,0x2b,0xba,0xf0,0xbf,\r
-0xc1,0x8f,0x13,0x78,0xa2,0x14,0xb8,0x4b,0x64,0xb0,0xb5,0x7e,0x56,0x5b,0xc6,0x29,\r
-0xb8,0x7a,0x85,0x00,0x9f,0xd2,0xbb,0x28,0x3f,0x66,0x5b,0xb6,0x51,0xe7,0xeb,0xd1,\r
-0x21,0xee,0x23,0xb6,0x2d,0xfa,0x96,0x15,0xeb,0xd1,0xca,0x31,0xd5,0xd7,0x34,0x29,\r
-0xbb,0x79,0xe9,0xf9,0x9d,0x31,0xc3,0x56,0x9a,0xba,0x89,0xe2,0x74,0x57,0xb9,0x37,\r
-0xec,0xc6,0xf8,0xf9,0x7c,0x42,0x3f,0x1b,0x4f,0xfe,0xce,0xaa,0x5c,0x7e,0xcc,0xfa,\r
-0x8a,0xa9,0xf2,0x35,0xab,0x59,0x0f,0x61,0x24,0x2c,0x9f,0xc8,0x9a,0xdd,0xe4,0x59,\r
-0x82,0xff,0x00,0x97,0x7f,0x8a,0xff,0x00,0x32,0xfe,0xa7,0x5d,0x7d,0x93,0xc6,0x28,\r
-0xaf,0x47,0xd4,0xbe,0x01,0x78,0xb2,0xc4,0x33,0x43,0x05,0xb5,0xf2,0x8f,0xf9,0xe1,\r
-0x38,0xcf,0xe4,0xc0,0x57,0x15,0xac,0x78,0x6b,0x56,0xf0,0xfb,0xed,0xd4,0xb4,0xdb,\r
-0x9b,0x2e,0x70,0x1a,0x68,0xc8,0x53,0xf4,0x3d,0x0d,0x79,0xd5,0xb0,0x58,0x9c,0x3e,\r
-0xb5,0x69,0xb5,0xf2,0x30,0x95,0x2a,0x90,0xf8,0xa3,0x63,0xac,0xf8,0x1d,0xa4,0x0d,\r
-0x57,0xe2,0x25,0x83,0x32,0x6e,0x8e,0xd5,0x5e,0xe1,0xbd,0xb0,0x30,0xa7,0xfe,0xfa,\r
-0x65,0xaf,0xab,0x07,0x4a,0xf0,0x8f,0xd9,0x9f,0x48,0x05,0xb5,0x9d,0x51,0x97,0xfb,\r
-0x96,0xc8,0x7f,0xf1,0xe6,0xff,0x00,0xd9,0x6b,0xde,0x2b,0xf4,0xce,0x1d,0xa3,0xec,\r
-0xb0,0x2a,0x5f,0xcc,0xdb,0xfd,0x3f,0x43,0xe8,0x30,0x30,0xe5,0xa3,0x7e,0xe1,0x45,\r
-0x14,0x57,0xd3,0x9e,0x80,0x55,0x2d,0x66,0x4f,0x2b,0x4a,0xbb,0x6f,0x48,0xcd,0x5d,\r
-0xac,0x7f,0x16,0xcb,0xe4,0x78,0x7a,0xf9,0xff,0x00,0xe9,0x99,0xac,0xea,0x3b,0x41,\r
-0xb2,0x64,0xed,0x16,0xcf,0x83,0x7e,0x27,0xcf,0xe7,0x78,0xa6,0xf4,0x83,0x9c,0x12,\r
-0x3f,0x5a,0xf9,0xc3,0xe2,0xbc,0x5f,0xda,0x1a,0xa6,0x95,0x65,0xb7,0x79,0xb8,0xbd,\r
-0x82,0x1d,0x9d,0x77,0x6e,0x91,0x57,0x1f,0xad,0x7d,0x01,0xe3,0xa9,0xbc,0xdd,0x7a,\r
-0xf5,0xb3,0x9f,0x9c,0x8a,0xf1,0x3b,0xa8,0x3f,0xb4,0xfe,0x36,0xfc,0x3b,0xb2,0xed,\r
-0x37,0x88,0xf4,0xe4,0xfa,0x8f,0xb4,0xc7,0xfe,0x15,0xf9,0xde,0x54,0xb9,0xb1,0x2d,\r
-0xf9,0xfe,0xa7,0xe3,0x33,0x5e,0xd7,0x36,0xa4,0xbf,0xbc,0x7e,0xb6,0xff,0x00,0x61,\r
-0x5a,0xff,0x00,0xcf,0xba,0xfe,0x54,0x56,0xad,0x15,0xfa,0x2f,0x2a,0x3f,0x66,0xb2,\r
-0x1f,0x45,0x14,0x55,0x94,0x14,0xd2,0x69,0xd5,0xc8,0xfc,0x55,0xf1,0x6f,0xfc,0x21,\r
-0x1e,0x01,0xd6,0xb5,0x75,0x60,0xb3,0xc3,0x09,0x48,0x33,0x8f,0xf5,0xad,0xf2,0xa7,\r
-0x07,0xaf,0x24,0x1c,0x7b,0x56,0x75,0x26,0xa9,0xc1,0xce,0x5b,0x23,0x3a,0x93,0x54,\r
-0xa0,0xe7,0x2d,0x96,0xa7,0xc8,0x5f,0x1f,0xbc,0x5f,0xff,0x00,0x09,0x8f,0xc4,0xfd,\r
-0x4e,0x48,0xa4,0x2f,0x69,0x64,0x45,0x94,0x18,0x24,0x8c,0x26,0x77,0x11,0xf5,0x62,\r
-0xdf,0xa5,0x7b,0xc7,0xec,0xaf,0xe1,0x1f,0xec,0x7f,0x08,0x4d,0xab,0x4a,0x98,0x9a,\r
-0xf9,0xfe,0x52,0x47,0x3b,0x05,0x7c,0xa9,0xa0,0x69,0x73,0xf8,0x83,0x5d,0xb5,0xb3,\r
-0x8c,0x19,0x66,0xb9,0x98,0x2f,0xa9,0x24,0x9e,0x4d,0x7e,0x85,0x78,0x67,0x45,0x8b,\r
-0xc3,0xfa,0x0d,0x8e,0x9f,0x12,0x85,0x4b,0x78,0x95,0x30,0x3d,0x40,0xe6,0xbe,0x27,\r
-0x28,0x83,0xc5,0xe3,0x27,0x8a,0x9f,0x4f,0xcd,0xff,0x00,0xc0,0x3e,0x27,0x23,0x84,\r
-0xb1,0x58,0x9a,0x98,0xc9,0xff,0x00,0x57,0x34,0xc5,0x2d,0x14,0x57,0xdd,0x1f,0x74,\r
-0x14,0x51,0x45,0x00,0x32,0x49,0x16,0x18,0xd9,0xdd,0x82,0x22,0x82,0x59,0x98,0xe0,\r
-0x01,0xea,0x6b,0xe0,0x7f,0xda,0x6b,0xfe,0x0a,0xd3,0xe0,0xaf,0x85,0x9a,0x95,0xe7,\r
-0x87,0xbe,0x1e,0x69,0xc9,0xe3,0xcd,0x72,0xdd,0x8c,0x73,0x5f,0xb4,0xa6,0x3d,0x36,\r
-0x17,0x07,0x95,0x0e,0x3e,0x69,0x88,0xff,0x00,0x67,0x0b,0xfe,0xd7,0x5a,0xe2,0xbf,\r
-0xe0,0xad,0x3f,0xb5,0xed,0xe7,0x84,0xed,0x62,0xf8,0x37,0xe1,0x3b,0xf6,0xb6,0xbe,\r
-0xd4,0x2d,0xc5,0xc7,0x88,0x6e,0xa0,0x7c,0x3c,0x76,0xef,0xfe,0xae,0xd8,0x10,0x78,\r
-0x2e,0x3e,0x66,0xff,0x00,0x64,0xa8,0xe8,0xc6,0xbe,0x5a,0xfd,0x8a,0x7f,0xe0,0x9d,\r
-0x9a,0xff,0x00,0xed,0x53,0xa7,0xc9,0xe2,0x9d,0x5f,0x55,0x3e,0x15,0xf0,0x3c,0x53,\r
-0x18,0x12,0xed,0x21,0xf3,0x2e,0x6f,0x5d,0x71,0xb9,0x61,0x52,0x40,0x0a,0xbd,0x0b,\r
-0xb6,0x46,0x78,0x00,0xe0,0xe1,0x92,0xfc,0x8c,0xef,0x1a,0xff,0x00,0xc1,0x51,0x7f,\r
-0x68,0x5f,0x17,0xcd,0x37,0x91,0xe2,0xeb,0x7f,0x0e,0xdb,0x3b,0x16,0x5b,0x7d,0x1b,\r
-0x4f,0x86,0x30,0x83,0xb0,0x0e,0xea,0xcf,0xf9,0xb5,0x7d,0x1d,0xff,0x00,0x04,0xc4,\r
-0xf8,0xc5,0xf1,0xb7,0xf6,0x81,0xf8,0xe3,0x7d,0x71,0xe2,0x9f,0x88,0x1a,0xe6,0xad,\r
-0xe0,0xff,0x00,0x0f,0xd8,0xbd,0xd5,0xe5,0xb5,0xc3,0x29,0x86,0x79,0xe4,0xcc,0x70,\r
-0xc4,0xc7,0x6e,0x47,0x57,0x93,0x03,0xfe,0x79,0x57,0xc9,0xbf,0xb7,0x6f,0xc0,0x4f,\r
-0x01,0xfe,0xcd,0x7f,0x18,0x6d,0xbc,0x0b,0xe0,0x8d,0x57,0x58,0xd5,0xde,0xd7,0x4f,\r
-0x8e,0xe3,0x53,0x9f,0x57,0x9e,0x29,0x19,0x27,0x90,0x96,0x58,0xc0,0x8e,0x34,0x0b,\r
-0x88,0xf6,0x31,0xce,0x7f,0xd6,0x0e,0x98,0xaf,0xd3,0xef,0xf8,0x25,0x5f,0xc1,0x81,\r
-0xf0,0xbf,0xf6,0x5f,0xb1,0xd7,0x2e,0xad,0xfc,0xad,0x5f,0xc5,0xf3,0x9d,0x56,0x56,\r
-0x3f,0x7b,0xec,0xff,0x00,0x72,0xdd,0x7d,0x86,0xd0,0x5b,0xfe,0xda,0x50,0x08,0x8f,\r
-0xe3,0x97,0xfc,0x15,0x17,0xc0,0x9f,0x00,0x7e,0x2c,0xeb,0xfe,0x01,0xd7,0xfc,0x21,\r
-0xe2,0x5b,0xbd,0x43,0x48,0x92,0x34,0x92,0xea,0xc4,0x5b,0xb4,0x32,0x07,0x89,0x24,\r
-0x56,0x5d,0xd2,0x29,0xe8,0xe3,0xb7,0x50,0x6b,0xe8,0x3f,0xd9,0xdb,0xe3,0xe6,0x87,\r
-0xfb,0x4a,0xfc,0x30,0xb3,0xf1,0xc7,0x87,0x6c,0xef,0xac,0x34,0xcb,0x99,0xe5,0xb7,\r
-0x58,0x35,0x15,0x45,0x98,0x34,0x6d,0xb5,0xb2,0x15,0x98,0x63,0x3d,0x39,0xaf,0xc2,\r
-0xdf,0xdb,0xb3,0xc7,0x76,0x9f,0x11,0xbf,0x6b,0x6f,0x89,0x5a,0xcd,0x84,0xbe,0x75,\r
-0x90,0xd4,0xbe,0xc5,0x13,0x8e,0x84,0x5b,0xc6,0x90,0x12,0x3d,0x8b,0x46,0xc7,0xf1,\r
-0xaf,0xd8,0xaf,0xf8,0x27,0x2f,0x81,0x67,0xf0,0x0f,0xec,0x75,0xf0,0xfa,0xd2,0xe5,\r
-0x59,0x2e,0x2f,0xed,0xa4,0xd5,0x59,0x58,0x60,0x81,0x71,0x2b,0x4a,0x9f,0xf8,0xe3,\r
-0x2d,0x03,0x4f,0x53,0xe9,0x19,0xa7,0x5b,0x78,0x9e,0x49,0x18,0x24,0x68,0xa5,0x99,\r
-0x98,0xe0,0x00,0x3b,0xd7,0xc5,0xfe,0x2d,0xd7,0x5f,0xc4,0xde,0x25,0xd4,0x75,0x37,\r
-0x27,0xfd,0x22,0x66,0x65,0x07,0xb2,0x74,0x51,0xf8,0x00,0x05,0x7d,0x29,0xf1,0xbf,\r
-0xc4,0x5f,0xd8,0x1e,0x01,0xbc,0x54,0x70,0xb7,0x17,0xc4,0x5a,0x46,0x3d,0x43,0x7d,\r
-0xff,0x00,0xfc,0x74,0x37,0xe9,0x5f,0x2a,0x57,0xe7,0x1c,0x51,0x8a,0xe6,0x9c,0x30,\r
-0xeb,0xa6,0xaf,0xe7,0xb1,0xe1,0xe6,0x15,0x2f,0x25,0x4f,0xe6,0x14,0x51,0x45,0x7c,\r
-0x29,0xe3,0x9a,0x5e,0x1a,0x92,0xc6,0x2d,0x7f,0x4f,0x93,0x52,0x25,0x6c,0x23,0x99,\r
-0x5e,0x6d,0xab,0xb8,0x95,0x07,0x24,0x60,0x7a,0xe3,0x1f,0x8d,0x7d,0x2b,0x1f,0xc7,\r
-0x9f,0x06,0xb0,0x03,0xed,0xf2,0xaf,0xd6,0xda,0x4f,0xf0,0xaf,0x96,0x28,0xaf,0x6b,\r
-0x01,0x9b,0x56,0xcb,0xa3,0x28,0xd2,0x49,0xdf,0xbf,0xfc,0x39,0xd7,0x47,0x13,0x3a,\r
-0x09,0xa8,0xad,0xcf,0xaa,0xcf,0xc7,0x5f,0x06,0x81,0x9f,0xed,0x37,0xff,0x00,0xc0,\r
-0x69,0x3f,0xf8,0x9a,0xc7,0xd6,0x3f,0x68,0xcf,0x0e,0xda,0x44,0xc2,0xc6,0xde,0xef,\r
-0x50,0x97,0xb0,0xd9,0xe5,0xaf,0xe2,0x4f,0x3f,0xa5,0x7c,0xd9,0x45,0x7a,0x53,0xe2,\r
-0x6c,0x6c,0x95,0x92,0x8a,0xf9,0x7f,0xc1,0x37,0x79,0x85,0x67,0xb5,0x8e,0xa7,0xc7,\r
-0x5f,0x11,0x35,0x5f,0x1e,0xdd,0xab,0xde,0x32,0xc3,0x69,0x19,0x26,0x1b,0x48,0xbe,\r
-0xe2,0x7b,0x9f,0x53,0xee,0x7f,0x0c,0x57,0x2d,0x45,0x6b,0xe9,0x1e,0x12,0xd6,0xb5,\r
-0xed,0xa7,0x4f,0xd2,0xee,0xae,0x91,0xba,0x3c,0x71,0x1d,0x9f,0xf7,0xd7,0x4f,0xd6,\r
-0xbe,0x72,0x73,0xad,0x8b,0xa8,0xe5,0x2b,0xca,0x4f,0xe6,0x70,0xc9,0xce,0xac,0xae,\r
-0xf5,0x66,0x45,0x69,0x78,0x7b,0xc3,0xb7,0xfe,0x29,0xd5,0x21,0xd3,0xf4,0xe8,0x0c,\r
-0xd7,0x12,0x1f,0xf8,0x0a,0x0e,0xec,0xc7,0xb0,0x15,0xe9,0x5e,0x18,0xfd,0x9d,0x75,\r
-0x7d,0x45,0xd2,0x4d,0x66,0xe2,0x3d,0x36,0x0e,0x09,0x8a,0x32,0x24,0x94,0x8f,0x4e,\r
-0x38,0x1f,0x99,0xfa,0x57,0xb9,0x78,0x4f,0xc1,0x7a,0x57,0x82,0xec,0x3e,0xcb,0xa6,\r
-0x5b,0x08,0xb3,0x83,0x24,0xad,0xcc,0x92,0x1f,0x56,0x6e,0xff,0x00,0x4e,0x83,0xb0,\r
-0x15,0xf4,0x79,0x7f,0x0f,0xe2,0x31,0x12,0x52,0xc4,0x2e,0x48,0xfe,0x2f,0xfa,0xf3,\r
-0x3b,0xa8,0x60,0xa7,0x37,0x79,0xe8,0x8a,0xfe,0x01,0xf0,0x5d,0xaf,0x81,0xbc,0x3f,\r
-0x0e,0x9f,0x6e,0x7c,0xc9,0x4f,0xcf,0x3c,0xf8,0xc1,0x95,0xcf,0x53,0xf4,0xec,0x3d,\r
-0x85,0x74,0xb4,0x94,0xb5,0xfa,0x7d,0x2a,0x51,0xa3,0x05,0x4e,0x0a,0xc9,0x1f,0x43,\r
-0x18,0xa8,0xa5,0x15,0xb0,0x51,0x45,0x15,0xa9,0x41,0x5e,0x6f,0xf1,0xeb,0x5c,0xfe,\r
-0xc9,0xf0,0x05,0xc4,0x0a,0xdb,0x65,0xbe,0x91,0x6d,0xd7,0x1e,0x99,0xdc,0xdf,0xa0,\r
-0x23,0xf1,0xaf,0x47,0x3d,0x2b,0xe7,0x8f,0xda,0x4f,0x5b,0xfb,0x4e,0xbd,0xa6,0x69,\r
-0x68,0xdf,0x25,0xac,0x26,0x67,0x03,0xfb,0xce,0x70,0x3f,0x20,0xbf,0xad,0x78,0x79,\r
-0xd5,0x7f,0xab,0xe0,0x6a,0x49,0x6e,0xf4,0xfb,0xce,0x4c,0x5c,0xf9,0x28,0xc9,0x9e,\r
-0x39,0x45,0x14,0x57,0xe3,0x67,0xca,0x85,0x7a,0x67,0xec,0xfb,0xa2,0xff,0x00,0x69,\r
-0x78,0xec,0x5d,0xba,0x93,0x1d,0x84,0x0d,0x2e,0x7b,0x07,0x6f,0x95,0x41,0xfc,0x0b,\r
-0x1f,0xc2,0xbc,0xce,0xbe,0x89,0xfd,0x9b,0x74,0x41,0x6b,0xe1,0xdd,0x47,0x54,0x65,\r
-0x22,0x4b,0xc9,0xc4,0x4a,0x4f,0x42,0x91,0x8e,0x08,0xfc,0x59,0x87,0xe1,0x5e,0xf6,\r
-0x47,0x43,0xdb,0xe3,0xe0,0x9e,0xcb,0x5f,0xbb,0xfe,0x09,0xd9,0x84,0x87,0x3d,0x68,\r
-0xf9,0x6a,0x7b,0x08,0xe9,0x4b,0x45,0x15,0xfb,0x11,0xf5,0x21,0x48,0x4e,0x29,0x6a,\r
-0x9e,0xad,0xa8,0xc5,0xa4,0xe9,0xb7,0x57,0xb3,0x9c,0x43,0x6f,0x13,0x4a,0xe7,0xd9,\r
-0x41,0x27,0xf9,0x54,0xc9,0xa8,0xa6,0xde,0xc2,0x6e,0xda,0xb3,0xc3,0x3f,0x68,0x9f,\r
-0x1b,0xb5,0xc5,0xdc,0x3e,0x1b,0xb5,0x90,0x88,0xa2,0x02,0x6b,0xbd,0xa7,0xef,0x31,\r
-0xe5,0x50,0xfd,0x07,0xcd,0x8f,0x71,0xe9,0x5e,0x27,0x57,0x35,0x9d,0x52,0x7d,0x6f,\r
-0x55,0xbb,0xd4,0x2e,0x4e,0x67,0xb9,0x95,0xa5,0x7f,0xa9,0x39,0xc7,0xd0,0x74,0xfc,\r
-0x2a,0x9d,0x7e,0x25,0x98,0x62,0xe5,0x8d,0xc4,0xca,0xb3,0xdb,0xa7,0xa7,0x43,0xe4,\r
-0xab,0xd5,0x75,0xaa,0x39,0x30,0xa2,0x8a,0x2b,0xce,0x30,0x3a,0x5f,0x87,0xde,0x0a,\r
-0x9f,0xc7,0x5e,0x22,0x86,0xc2,0x32,0x63,0xb7,0x5f,0xde,0x5c,0x4c,0x07,0xdc,0x8f,\r
-0xbf,0xe2,0x7a,0x0f,0xfe,0xb5,0x7d,0x71,0xa3,0x69,0x16,0x9a,0x16,0x9b,0x05,0x8d,\r
-0x8c,0x2b,0x6f,0x6b,0x02,0xed,0x48,0xd0,0x71,0xf5,0x3e,0xa4,0xf5,0x27,0xa9,0xae,\r
-0x13,0xe0,0x4f,0x84,0xd7,0xc3,0xde,0x0d,0x8a,0xf2,0x44,0x02,0xf3,0x52,0xc5,0xc3,\r
-0x92,0x39,0x11,0xff,0x00,0xcb,0x31,0xf9,0x73,0xf5,0x63,0x5e,0x93,0x5f,0xad,0x64,\r
-0x59,0x7c,0x70,0x98,0x75,0x52,0x4b,0xdf,0x9e,0xaf,0xc9,0x74,0x47,0xd2,0xe0,0xe8,\r
-0x2a,0x54,0xd4,0x9e,0xec,0x4a,0x5a,0x28,0xaf,0xa6,0x3d,0x00,0xa2,0x8a,0x28,0x03,\r
-0x8c,0xf8,0xb1,0xe1,0x58,0xbc,0x55,0xe0,0xbb,0xe8,0x76,0x03,0x75,0x6e,0x86,0xe2,\r
-0xdd,0xb1,0xc8,0x75,0x19,0xc0,0xfa,0x8c,0x8f,0xc6,0xbe,0x47,0xaf,0xb9,0xe4,0x50,\r
-0xe8,0x54,0x8c,0x82,0x30,0x6b,0xe2,0x0d,0x46,0x11,0x6f,0xa8,0xdd,0x42,0x3a,0x47,\r
-0x2b,0xa0,0xfc,0x09,0x15,0xf9,0xd7,0x14,0xd0,0x8c,0x67,0x4e,0xb2,0xdd,0xdd,0x3f,\r
-0x91,0xe1,0x66,0x30,0x49,0xc6,0x5d,0xca,0xf4,0x51,0x45,0x7c,0x21,0xe3,0x85,0x7d,\r
-0x49,0xf0,0x17,0x5a,0x6d,0x57,0xe1,0xf5,0xb4,0x4e,0xe5,0xe4,0xb2,0x95,0xed,0xc9,\r
-0x3e,0x83,0xe6,0x51,0xf8,0x2b,0x01,0xf8,0x57,0xcb,0x75,0xf4,0x27,0xec,0xcf,0x29,\r
-0x3a,0x0e,0xb3,0x1f,0x65,0xba,0x56,0xfc,0xd3,0x1f,0xd2,0xbe,0xa7,0x86,0xea,0x38,\r
-0x63,0x94,0x57,0x54,0xff,0x00,0xcc,0xf4,0x70,0x12,0x6a,0xb5,0xbb,0x9e,0xcc,0x6b,\r
-0xe5,0x2f,0x8e,0x1a,0x9b,0xea,0x3f,0x11,0xb5,0x14,0x66,0x2d,0x1d,0xa8,0x48,0x23,\r
-0x1e,0x80,0x28,0x27,0xff,0x00,0x1e,0x66,0xaf,0xab,0x3b,0x57,0xc8,0xdf,0x17,0x6d,\r
-0x5a,0xd3,0xe2,0x3e,0xb8,0xad,0xd5,0xa6,0x12,0x0f,0xa3,0x28,0x23,0xf9,0xd7,0xd3,\r
-0x71,0x3c,0xa4,0xb0,0x91,0x4b,0x67,0x2f,0xd1,0x9d,0xf9,0x83,0xfd,0xd2,0xf5,0x38,\r
-0xfa,0x28,0xa2,0xbf,0x30,0x3e,0x7c,0x2b,0xb7,0xf8,0x35,0xa3,0xd9,0xeb,0x5e,0x3f,\r
-0xb0,0x8a,0xf7,0x6b,0x45,0x18,0x69,0x96,0x37,0xe4,0x48,0xca,0x32,0xa3,0xf3,0xe7,\r
-0xf0,0xae,0x22,0xac,0xe9,0xba,0x8d,0xce,0x91,0x7f,0x05,0xed,0xa4,0xcd,0x05,0xcc,\r
-0x0e,0x1e,0x39,0x13,0xaa,0x91,0x5d,0x38,0x6a,0x91,0xa3,0x5e,0x15,0x26,0xae,0x93,\r
-0x4e,0xc5,0xd3,0x92,0x8c,0xd4,0x9e,0xc7,0xdb,0xea,0x38,0xc5,0x3b,0x15,0xe2,0xbe,\r
-0x10,0xfd,0xa3,0x2c,0xe7,0x8d,0x21,0xf1,0x0d,0xb3,0xda,0xcc,0x38,0x37,0x56,0xeb,\r
-0xba,0x33,0xee,0x57,0xa8,0xfc,0x33,0x5e,0xa7,0xa3,0x78,0xbb,0x46,0xf1,0x0a,0x06,\r
-0xd3,0xb5,0x2b,0x6b,0xbf,0x55,0x8e,0x41,0xb8,0x7d,0x57,0xa8,0xaf,0xd9,0x70,0xb9,\r
-0x86,0x17,0x16,0x93,0xa5,0x35,0xe9,0xd7,0xee,0x3e,0xae,0x9d,0x7a,0x75,0x7e,0x16,\r
-0x6b,0xe2,0x82,0x29,0x37,0x52,0xe6,0xbd,0x23,0x70,0xc7,0xe3,0x4c,0x9e,0xde,0x3b,\r
-0x98,0xda,0x39,0x51,0x64,0x8d,0x86,0x19,0x1d,0x72,0x08,0xf4,0x22,0xa4,0xa2,0x95,\r
-0x93,0xdc,0x2c,0x50,0xd2,0x74,0x2b,0x0d,0x06,0x29,0x62,0xd3,0xed,0x21,0xb3,0x8a,\r
-0x49,0x0c,0xad,0x1c,0x08,0x15,0x4b,0x10,0x01,0x38,0x1f,0x41,0x57,0xe8,0xa2,0x94,\r
-0x62,0xa2,0xad,0x15,0x64,0x24,0x92,0xd1,0x05,0x14,0x51,0x54,0x30,0xae,0x67,0xe2,\r
-0x24,0xfe,0x47,0x85,0x2f,0x5b,0xa1,0xdb,0x8a,0xe9,0xab,0x88,0xf8,0xbd,0x71,0xf6,\r
-0x7f,0x07,0xdc,0x1c,0xe3,0x3f,0xe1,0x5c,0xb8,0xa9,0x72,0xd0,0x9b,0xf2,0x66,0x35,\r
-0x9d,0xa9,0xc9,0x9f,0x08,0x78,0xa6,0x5d,0xfa,0x9d,0xe3,0x67,0xf8,0xcd,0x79,0xb7,\r
-0xc3,0x9b,0x15,0xd7,0x3f,0x6a,0xdf,0x86,0x16,0x6f,0xc8,0x1a,0xd4,0x73,0xe3,0xde,\r
-0x25,0x69,0x47,0xea,0x95,0xdf,0x6b,0xaf,0xba,0x7b,0x86,0xf5,0x63,0x5c,0x9f,0xec,\r
-0xe3,0x0b,0xea,0x3f,0xb6,0xaf,0xc3,0xb4,0x0b,0xb9,0x21,0x96,0xf6,0x66,0xf6,0x0b,\r
-0x67,0x3e,0x0f,0xe6,0x45,0x7c,0x36,0x48,0xaf,0x56,0xe7,0xe4,0x38,0x15,0xed,0x33,\r
-0x9a,0x5e,0xad,0x9f,0xab,0x7b,0x68,0xa5,0xcd,0x15,0xfa,0x21,0xfb,0x08,0xb4,0x51,\r
-0x45,0x22,0xc4,0xcd,0x7c,0xcb,0xfb,0x60,0xf8,0xbc,0xee,0xd1,0xfc,0x33,0x0b,0xe0,\r
-0x1c,0xdf,0x5c,0x80,0x4f,0xba,0xc6,0x3e,0x9f,0x7c,0xfe,0x02,0xbe,0x97,0x95,0xc4,\r
-0x68,0xce,0xc4,0x2a,0xa8,0x24,0x92,0x70,0x00,0xaf,0xcf,0xaf,0x89,0xbe,0x2c,0x93,\r
-0xc6,0xfe,0x3c,0xd6,0x35,0x56,0x72,0xf1,0x4b,0x39,0x8e,0x01,0x9c,0x85,0x89,0x7e,\r
-0x54,0xc7,0xe0,0x33,0xf8,0xd7,0xce,0x67,0x98,0x8f,0x63,0x86,0xf6,0x6b,0x79,0x69,\r
-0xf2,0xea,0x7c,0xc7,0x10,0x62,0x7d,0x96,0x17,0xd9,0x47,0x79,0xbb,0x7c,0xba,0x9e,\r
-0x89,0xfb,0x2d,0x78,0x47,0xfb,0x6b,0xc6,0x8d,0xa9,0xcb,0x1e,0xe8,0x2c,0x17,0x70,\r
-0x27,0xa6,0xf3,0xd2,0xbe,0xc4,0x1d,0x2b,0xca,0x3f,0x67,0x0f,0x08,0xff,0x00,0xc2,\r
-0x37,0xf0,0xfe,0x09,0xe4,0x4d,0xb7,0x17,0xc7,0xce,0x62,0x47,0x38,0xed,0x5e,0xaf,\r
-0x5d,0x19,0x3e,0x1f,0xd8,0x61,0x63,0x7d,0xe5,0xab,0xf9,0xff,0x00,0xc0,0x3d,0x0c,\r
-0xab,0x0d,0xf5,0x6c,0x24,0x62,0xf7,0x7a,0xb1,0x68,0xa2,0x8a,0xf6,0xcf,0x5c,0x29,\r
-0x09,0xa5,0xa4,0xc5,0x00,0x7f,0x37,0xdf,0xb5,0x6f,0x8c,0xaf,0x3c,0x7d,0xfb,0x4a,\r
-0x7c,0x4c,0xd6,0xef,0x9c,0xc9,0x34,0xda,0xfd,0xe4,0x28,0x4f,0x55,0x8a,0x29,0x4c,\r
-0x51,0x2f,0xe1,0x1c,0x68,0x3f,0x0a,0xfd,0x53,0xfd,0x82,0x7f,0x6c,0xcf,0x83,0xf6,\r
-0x1f,0xb3,0x47,0x85,0xfc,0x31,0xa9,0xf8,0xa7,0x4c,0xf0,0xae,0xbb,0xe1,0xbb,0x13,\r
-0x6f,0x77,0xa7,0x6a,0x93,0xad,0xb1,0x99,0x94,0xb3,0x19,0x62,0x67,0x20,0x49,0xbf,\r
-0x24,0xe0,0x1c,0xe4,0x90,0x47,0x4a,0xf8,0x47,0xfe,0x0a,0x39,0xfb,0x2b,0x78,0x83,\r
-0xe0,0x87,0xc7,0x0f,0x10,0xf8,0xa2,0x1d,0x3e,0x69,0xfc,0x11,0xe2,0x7b,0xf9,0x75,\r
-0x1b,0x2d,0x4a,0x35,0xdd,0x1c,0x32,0xca,0xdb,0xe5,0x82,0x4c,0x0f,0x91,0x83,0xb3,\r
-0x6d,0xcf,0x55,0x23,0x07,0x39,0x03,0xe4,0x43,0xc7,0x19,0xaa,0x22,0xf6,0x67,0xaf,\r
-0x6b,0x7a,0xcd,0xcf,0xed,0x4b,0xfb,0x51,0x5c,0xea,0x1a,0x95,0xf2,0x58,0x0f,0x17,\r
-0x78,0x83,0x32,0x5d,0x5d,0xca,0xa8,0xb6,0x76,0xaf,0x20,0x03,0x73,0x36,0x00,0x11,\r
-0xc2,0x00,0xe7,0xfb,0x95,0xfa,0x69,0xfb,0x5b,0xff,0x00,0xc1,0x44,0x3e,0x1f,0x7c,\r
-0x15,0xf8,0x50,0xfe,0x01,0xf8,0x43,0xac,0xda,0x78,0x83,0xc4,0xc7,0x4f,0x5d,0x32,\r
-0xd2,0xe7,0x49,0x71,0x2d,0xa6,0x95,0x08,0x4f,0x2c,0x48,0x65,0x19,0x57,0x90,0x28,\r
-0xf9,0x55,0x49,0xc1,0xc1,0x38,0xc6,0x0f,0xe3,0x6f,0x5a,0xf5,0x3f,0x80,0xff,0x00,\r
-0xb3,0x47,0xc4,0x3f,0xda,0x3b,0xc4,0x91,0x69,0x3e,0x0b,0xd0,0x66,0xbc,0x8b,0x78,\r
-0x17,0x3a,0x9c,0xe0,0xc7,0x65,0x6a,0x33,0xcb,0x4b,0x2e,0x30,0x31,0x9f,0xba,0x32,\r
-0xc7,0xb0,0x34,0x09,0x17,0x3f,0x65,0xcf,0x80,0x7a,0xc7,0xed,0x37,0xf1,0xb7,0x43,\r
-0xf0,0x8d,0x92,0xcc,0x6d,0x27,0x9b,0xed,0x3a,0xb5,0xf8,0xc9,0xfb,0x35,0xa2,0x90,\r
-0x65,0x90,0x9e,0x79,0x3f,0x75,0x73,0xd5,0x99,0x6b,0xfa,0x2e,0xd2,0xb4,0xcb,0x6d,\r
-0x13,0x4b,0xb4,0xd3,0xec,0xa2,0x58,0x2c,0xed,0x21,0x48,0x21,0x89,0x06,0x02,0x22,\r
-0xa8,0x55,0x03,0xe8,0x00,0xaf,0x0f,0xfd,0x90,0xff,0x00,0x64,0x5f,0x0d,0x7e,0xc9,\r
-0xbe,0x00,0x1a,0x4e,0x98,0xcb,0xaa,0x78,0x86,0xfb,0x6c,0x9a,0xb6,0xb6,0xf1,0xed,\r
-0x7b,0x99,0x00,0xe1,0x50,0x73,0xb2,0x35,0xe7,0x6a,0xe4,0xf5,0x24,0x92,0x6b,0xdd,\r
-0x2f,0x6f,0x22,0xb0,0xb4,0x9e,0xe6,0x76,0xd9,0x0c,0x31,0xb4,0x8e,0xc7,0xb2,0x81,\r
-0x92,0x7f,0x2a,0x87,0x24,0x95,0xd9,0x5b,0x23,0xe7,0x6f,0xda,0x2f,0xc4,0x7f,0xda,\r
-0x1e,0x26,0xb5,0xd2,0xa3,0x6c,0xc7,0x61,0x16,0xe7,0x19,0xe3,0xcc,0x7c,0x1f,0xd1,\r
-0x42,0xfe,0x75,0xe4,0x95,0xa1,0xe2,0x0d,0x62,0x4f,0x10,0x6b,0x97,0xfa,0x94,0xbf,\r
-0x7e,0xea,0x66,0x97,0x1e,0x80,0x9e,0x07,0xe0,0x30,0x3f,0x0a,0xcf,0xaf,0xc4,0x31,\r
-0xf8,0x87,0x8a,0xc5,0x4e,0xb7,0x77,0xf8,0x74,0x3e,0x4a,0xb5,0x4f,0x6b,0x51,0xcc,\r
-0x28,0xa2,0xba,0x5f,0x87,0x1e,0x1f,0xff,0x00,0x84,0x9f,0xc6,0xba,0x5d,0x8b,0x2e,\r
-0xe8,0x4c,0xa2,0x49,0x81,0xe9,0xb1,0x7e,0x66,0x07,0xeb,0x8c,0x7e,0x35,0xcb,0x46,\r
-0x94,0xab,0x54,0x8d,0x28,0xef,0x27,0x6f,0xbc,0xce,0x31,0x73,0x92,0x8a,0xea,0x61,\r
-0x49,0xa7,0xdd,0x43,0xfe,0xb2,0xda,0x64,0xff,0x00,0x7a,0x32,0x2a,0xb9,0x18,0x35,\r
-0xf7,0x40,0x41,0x80,0x36,0x8c,0x56,0x37,0x88,0x3c,0x17,0xa3,0x78,0x9e,0xd9,0xe1,\r
-0xd4,0x34,0xe8,0x27,0xdc,0x31,0xe6,0x6c,0x02,0x45,0xf7,0x0c,0x39,0x15,0xf7,0x15,\r
-0x38,0x56,0x49,0x5e,0x9d,0x5b,0xbf,0x35,0xff,0x00,0x04,0xf5,0xe5,0x97,0x3b,0x7b,\r
-0xb2,0x3e,0x30,0xa2,0xba,0x4f,0x88,0x3e,0x0e,0x97,0xc0,0xfe,0x26,0xb8,0xd3,0x5d,\r
-0x8c,0x90,0xe0,0x4b,0x04,0xad,0xd5,0xe3,0x3d,0x09,0xf7,0x18,0x20,0xfb,0x8a,0xe6,\r
-0xeb,0xe1,0xaa,0xd2,0x9d,0x1a,0x8e,0x9c,0xd5,0x9a,0xd0,0xf2,0x25,0x17,0x06,0xe2,\r
-0xfa,0x05,0x74,0x7e,0x0d,0xf1,0xde,0xab,0xe0,0x9d,0x4a,0x3b,0x8b,0x2b,0x87,0x36,\r
-0xfb,0x81,0x96,0xd5,0x98,0xf9,0x72,0xaf,0x70,0x47,0x63,0xef,0xd4,0x57,0x39,0x45,\r
-0x14,0xaa,0xce,0x8c,0xd5,0x4a,0x6e,0xcd,0x04,0x64,0xe0,0xf9,0xa3,0xb9,0xf7,0x06,\r
-0x95,0xa8,0xc3,0xab,0xe9,0xb6,0xd7,0xb6,0xed,0xba,0x0b,0x88,0xd6,0x54,0x3e,0xc4,\r
-0x64,0x7f,0x3a,0xb7,0x5c,0x27,0xc1,0x2b,0xef,0xb7,0x7c,0x37,0xd2,0x49,0x39,0x68,\r
-0x83,0xc2,0x7f,0xe0,0x2e,0x40,0xfd,0x31,0x5d,0xdd,0x7e,0xe5,0x86,0xab,0xed,0xe8,\r
-0x42,0xaf,0x74,0x9f,0xde,0x8f,0xaf,0xa7,0x2e,0x78,0x29,0x77,0x0a,0x28,0xa2,0xba,\r
-0x4d,0x02,0x8a,0x28,0xa0,0x04,0x27,0x00,0xd7,0xc7,0x1f,0x11,0x35,0xcf,0xf8,0x48,\r
-0xbc,0x6d,0xac,0x5f,0x2b,0x07,0x8d,0xa7,0x64,0x8c,0x8e,0x85,0x17,0xe5,0x53,0xf8,\r
-0x80,0x0f,0xe3,0x5f,0x54,0x78,0xf7,0x5d,0xff,0x00,0x84,0x73,0xc1,0xfa,0xb6,0xa0,\r
-0xae,0x12,0x48,0xad,0xdb,0xcb,0x2d,0xd3,0x79,0x18,0x4f,0xfc,0x78,0x8a,0xf8,0xcc,\r
-0x0c,0x0c,0x57,0xc0,0x71,0x4d,0x7d,0x29,0xd0,0x5e,0xaf,0xf2,0x5f,0xa9,0xe2,0xe6,\r
-0x33,0xf8,0x60,0x2d,0x14,0x51,0x5f,0x9f,0x1e,0x20,0x57,0xd8,0xdf,0x0e,0xb4,0x4f,\r
-0xec,0x0f,0x04,0xe8,0xf6,0x44,0x61,0xd6,0xdd,0x5d,0xc7,0xfb,0x4d,0xf3,0x37,0xea,\r
-0xc6,0xbe,0x53,0xf0,0x5e,0x91,0xfd,0xbf,0xe2,0xcd,0x27,0x4f,0xc6,0x56,0x7b,0x94,\r
-0x0e,0x3f,0xd9,0x07,0x2d,0xfa,0x03,0x5f,0x68,0x28,0x01,0x40,0x1c,0x01,0x5f,0x7f,\r
-0xc2,0xd4,0x3f,0x89,0x5d,0xfa,0x7e,0xaf,0xf4,0x3d,0xac,0xba,0x1f,0x14,0xfe,0x41,\r
-0x4b,0x45,0x15,0xfa,0x09,0xed,0x85,0x79,0xb7,0xc7,0xed,0x63,0xfb,0x2f,0xe1,0xfc,\r
-0xf0,0xa9,0x2b,0x25,0xf4,0xc9,0x6e,0xa4,0x7a,0x67,0x73,0x7e,0x88,0x47,0xe3,0x5e,\r
-0x93,0x5e,0x17,0xfb,0x4e,0x6a,0x0e,0xb1,0xe8,0x36,0x4a,0x7e,0x46,0x32,0xcc,0xc3,\r
-0xdc,0x6d,0x03,0xf9,0xb5,0x78,0xd9,0xc5,0x57,0x47,0x01,0x56,0x4b,0xb5,0xbe,0xfd,\r
-0x0e,0x5c,0x54,0xb9,0x28,0xc9,0x9e,0x11,0x45,0x14,0x57,0xe3,0x07,0xca,0x05,0x5e,\r
-0xd0,0xb4,0xc6,0xd6,0xb5,0xab,0x0d,0x3d,0x0e,0x1a,0xea,0x74,0x87,0x3e,0x9b,0x88,\r
-0x19,0xaa,0x35,0xda,0x7c,0x1b,0xb4,0x5b,0xdf,0x89,0x3a,0x2a,0x3f,0xdd,0x57,0x79,\r
-0x3f,0x15,0x8d,0x88,0xfd,0x40,0xae,0xac,0x2d,0x3f,0x6d,0x5e,0x14,0xdf,0x56,0x97,\r
-0xe2,0x69,0x4e,0x3c,0xd3,0x8c,0x7c,0xcf,0xac,0xad,0xa0,0x8e,0xd6,0xde,0x28,0x62,\r
-0x50,0x91,0x46,0xa1,0x11,0x47,0x40,0x00,0xc0,0x02,0xa5,0xa4,0x14,0xb5,0xfb,0xaa,\r
-0x49,0x2b,0x23,0xec,0x42,0x8a,0x28,0xa6,0x01,0x45,0x14,0x50,0x04,0x73,0x38,0x86,\r
-0x27,0x76,0x38,0x55,0x04,0x93,0xf8,0x57,0xc3,0xd7,0x93,0x7d,0xa6,0xf2,0x79,0xbf,\r
-0xe7,0xa4,0x8c,0xff,0x00,0x99,0xcd,0x7d,0x79,0xf1,0x37,0x5a,0x5d,0x07,0xc0,0xba,\r
-0xc5,0xd1,0x38,0x73,0x01,0x8a,0x3c,0x1e,0x77,0x3f,0xca,0x3f,0x9e,0x7f,0x0a,0xf8,\r
-0xf6,0xbf,0x3a,0xe2,0x9a,0xa9,0xce,0x95,0x25,0xd1,0x36,0x78,0x59,0x8c,0xb5,0x8c,\r
-0x42,0x8a,0x28,0xaf,0x84,0x3c,0x70,0xaf,0xa1,0xff,0x00,0x66,0x98,0x36,0xf8,0x6b,\r
-0x56,0x97,0x04,0x6f,0xbb,0x0b,0x9f,0xa2,0x0f,0xf1,0xaf,0x9e,0x3a,0xd7,0xd5,0x5f,\r
-0x02,0xf4,0xa6,0xd3,0x3e,0x1d,0x58,0x3b,0xae,0xd9,0x2e,0x9d,0xee,0x08,0xf6,0x27,\r
-0x0b,0xff,0x00,0x8e,0x81,0x5f,0x55,0xc3,0x74,0xdc,0xf1,0xdc,0xdd,0x93,0xff,0x00,\r
-0x23,0xd1,0xc0,0x46,0xf5,0xaf,0xd9,0x1e,0x81,0x8e,0x2b,0xc3,0xbf,0x68,0x6f,0x02,\r
-0xcd,0x71,0xe4,0xf8,0x8e,0xce,0x33,0x20,0x89,0x04,0x57,0x61,0x47,0x21,0x73,0xf2,\r
-0xbf,0xe1,0x9c,0x1f,0xc3,0xde,0xbd,0xc4,0x53,0x66,0x85,0x27,0x8d,0xa3,0x91,0x16,\r
-0x44,0x71,0xb5,0x95,0x86,0x41,0x1e,0x86,0xbf,0x46,0xc7,0x60,0xe1,0x8e,0xa1,0x2a,\r
-0x33,0xeb,0xf8,0x33,0xdd,0xad,0x49,0x56,0x83,0x83,0x3e,0x17,0xa2,0xbd,0xc7,0xe2,\r
-0x1f,0xec,0xff,0x00,0x20,0x96,0x5b,0xff,0x00,0x0d,0x60,0xa3,0x65,0x9b,0x4f,0x76,\r
-0xc1,0x53,0xff,0x00,0x4c,0xd8,0xff,0x00,0x23,0xef,0xcf,0x41,0x5e,0x2d,0x7f,0xa7,\r
-0x5d,0x69,0x57,0x2f,0x6f,0x79,0x6f,0x2d,0xac,0xe9,0xf7,0xa3,0x95,0x0a,0xb0,0xfc,\r
-0x0d,0x7e,0x43,0x8c,0xcb,0xf1,0x18,0x19,0xb8,0xd5,0x8e,0x9d,0xfa,0x33,0xe6,0x2a,\r
-0xd0,0x9d,0x17,0x69,0x22,0xbd,0x14,0x51,0x5e,0x69,0x80,0x52,0xab,0x14,0x60,0xca,\r
-0x4a,0xb0,0x39,0x04,0x1c,0x11,0x49,0x45,0x34,0xed,0xaa,0x03,0xab,0xd1,0xbe,0x29,\r
-0xf8,0xa7,0x41,0xda,0xb6,0xba,0xcd,0xc3,0x46,0x08,0xfd,0xdd,0xc1,0xf3,0x94,0x8f,\r
-0x4f,0x9b,0x24,0x0f,0xa6,0x2b,0xd1,0x34,0x0f,0xda,0x56,0x65,0x65,0x4d,0x6b,0x4a,\r
-0x57,0x52,0x79,0x9a,0xc9,0x88,0x20,0x7f,0xb8,0xc7,0x9f,0xfb,0xe8,0x57,0x88,0x51,\r
-0x5e,0xae,0x1f,0x35,0xc6,0x61,0xbf,0x87,0x51,0xdb,0xb3,0xd5,0x7e,0x27,0x4c,0x31,\r
-0x35,0x69,0xfc,0x32,0x3e,0xc3,0xf0,0xc7,0xc4,0x9f,0x0f,0xf8,0xb8,0x2a,0xe9,0xf7,\r
-0xe8,0x6e,0x08,0xcf,0xd9,0xa5,0xf9,0x25,0x1f,0xf0,0x13,0xd7,0xf0,0xcd,0x74,0xf9,\r
-0xaf,0x85,0x91,0xda,0x37,0x57,0x46,0x2a,0xca,0x72,0x18,0x1c,0x10,0x6b,0xd6,0x7e,\r
-0x1c,0xfc,0x75,0xbe,0xd1,0x25,0x8a,0xc7,0x5e,0x77,0xbf,0xd3,0xce,0x14,0x5c,0x9e,\r
-0x66,0x8b,0xeb,0xfd,0xe1,0xf5,0xe7,0xeb,0xd2,0xbe,0xcb,0x01,0xc4,0xb0,0xaa,0xd5,\r
-0x3c,0x52,0xe5,0x7d,0xd6,0xdf,0x3e,0xc7,0xab,0x47,0x1e,0xa4,0xf9,0x6a,0x2b,0x1f,\r
-0x48,0xd1,0x50,0x59,0x5e,0xc1,0xa8,0x5a,0xc5,0x73,0x6d,0x2a,0xcf,0x6f,0x2a,0x87,\r
-0x8e,0x44,0x39,0x56,0x53,0xd0,0x83,0x53,0xd7,0xdb,0xa6,0x9a,0xba,0x3d,0x7d,0xc2,\r
-0x8a,0x28,0xa6,0x01,0x5e,0x5f,0xf1,0xfa,0xf4,0xda,0xf8,0x48,0xa8,0xfe,0x2c,0xd7,\r
-0xa8,0x57,0x8a,0xfe,0xd2,0xd7,0x5e,0x57,0x87,0xe3,0x4c,0xff,0x00,0x09,0x38,0xaf,\r
-0x2f,0x33,0x97,0x2e,0x12,0xa3,0xf2,0x38,0xb1,0xb2,0xe5,0xc3,0xcd,0xf9,0x1f,0x18,\r
-0x6b,0x32,0x65,0x65,0x6e,0xe4,0x93,0x55,0xff,0x00,0x62,0x7b,0x51,0xaa,0x7e,0xd9,\r
-0x36,0xcf,0x8c,0x8b,0x2d,0x16,0xfa,0xe7,0xe8,0x49,0x8a,0x3c,0xff,0x00,0xe4,0x43,\r
-0xf9,0xd1,0xad,0xbe,0xdb,0x69,0x0f,0xb1,0xad,0x6f,0xf8,0x27,0x95,0x9f,0xdb,0x3f,\r
-0x6a,0x3f,0x15,0x5e,0xe3,0x22,0xd7,0xc3,0x72,0xc5,0xbb,0xd0,0xc9,0x73,0x01,0xff,\r
-0x00,0xda,0x66,0xbe,0x63,0x21,0x8f,0xbd,0x73,0xf2,0xcc,0x8d,0x73,0xe7,0x09,0xf6,\r
-0x4c,0xfd,0x29,0xdb,0x45,0x1c,0xd1,0x5f,0x79,0x73,0xf5,0xeb,0x21,0xd4,0x51,0x49,\r
-0x48,0xa3,0xcd,0x3f,0x68,0x5f,0x18,0x9f,0x07,0xfc,0x31,0xd4,0xa4,0x85,0xf6,0x5d,\r
-0xdf,0x62,0xc6,0x03,0xe8,0x5f,0x3b,0x8f,0xe0,0x81,0x8f,0xd4,0x0a,0xf8,0xeb,0xc0,\r
-0x3e,0x1d,0x93,0xc5,0x3e,0x2c,0xd3,0x74,0xd8,0xd7,0x3e,0x6c,0xca,0x1b,0xd8,0x67,\r
-0x9a,0xf5,0x7f,0xda,0xdb,0xc6,0x1f,0xda,0xbe,0x30,0xb2,0xd0,0x61,0x7c,0xc1,0xa6,\r
-0xc3,0xe6,0x4a,0x01,0xe0,0xca,0xfe,0xbe,0xe1,0x40,0xff,0x00,0xbe,0xab,0x43,0xf6,\r
-0x4b,0xf0,0x7f,0xda,0xb5,0x7b,0xdd,0x76,0x64,0xca,0x5b,0x2f,0x97,0x11,0x3f,0xde,\r
-0x3d,0x6b,0xe0,0xb1,0xcd,0xe6,0x19,0x8c,0x68,0x2d,0x96,0x9f,0xe6,0x7c,0x06,0x2d,\r
-0xbc,0xc7,0x35,0x54,0x57,0xc3,0x1d,0x3e,0xed,0x59,0xf5,0x0e,0x9f,0x65,0x1e,0x9d,\r
-0x63,0x6f,0x6d,0x12,0x85,0x8e,0x14,0x08,0xa0,0x7a,0x01,0x8a,0xb3,0x48,0x3a,0x52,\r
-0xd7,0xde,0x24,0x92,0xb2,0x3e,0xf9,0x2b,0x2b,0x20,0xa2,0x8a,0x29,0x8c,0x2b,0xf2,\r
-0xdf,0xf6,0xd7,0xff,0x00,0x82,0x9b,0x78,0xf3,0xe1,0x1f,0xed,0x0d,0xa9,0xf8,0x43,\r
-0xe1,0xcc,0x9a,0x4b,0xe8,0xfa,0x0c,0x49,0x69,0x7d,0xfd,0xa1,0x69,0xf6,0x81,0x3d,\r
-0xe6,0x37,0x49,0x82,0x19,0x59,0x42,0x6e,0x09,0x80,0x7a,0xab,0x57,0xea,0x2c,0xb2,\r
-0xa4,0x31,0xb3,0xc8,0xea,0x88,0xa0,0x96,0x66,0x38,0x00,0x7a,0x93,0x5f,0x84,0x3f,\r
-0xf0,0x51,0x9f,0xd9,0xb7,0xc4,0x9f,0x0a,0xbe,0x3b,0xf8,0xa7,0xc5,0xe2,0xde,0x4d,\r
-0x4b,0xc1,0xbe,0x27,0xd4,0x65,0xd4,0xad,0x75,0x8b,0x71,0xbe,0x28,0xe5,0x99,0x8b,\r
-0xc9,0x04,0x84,0x67,0x63,0x2b,0xb3,0x63,0x38,0xdc,0xb8,0x23,0xb8,0x0d,0x09,0x9f,\r
-0x6d,0x7e,0xc1,0xff,0x00,0xb5,0xcf,0xc4,0xef,0xdb,0x5b,0xc4,0xde,0x24,0xd0,0xbc,\r
-0x73,0xe1,0x9f,0x07,0xcf,0xe0,0x9d,0x2e,0xc5,0x5f,0x51,0x78,0x74,0xf9,0x77,0x4d,\r
-0x2c,0x84,0x88,0x62,0xdb,0x24,0xce,0x9c,0xec,0x91,0x89,0xdb,0xc0,0x4c,0x63,0x90,\r
-0x47,0xb1,0xf8,0xbf,0xfe,0x09,0x9f,0xfb,0x3c,0xf8,0xc2,0xe9,0xae,0x64,0xf0,0x2a,\r
-0xe9,0x13,0x39,0x25,0x8e,0x91,0x79,0x35,0xb2,0x1c,0xff,0x00,0xb0,0x1b,0x68,0xfc,\r
-0x00,0xaf,0x84,0xbf,0xe0,0x93,0xbf,0xb5,0x1f,0x82,0x3e,0x09,0xea,0xfe,0x2e,0xf0,\r
-0x97,0x8d,0xb5,0x2b,0x7f,0x0f,0x45,0xe2,0x09,0x2d,0xee,0x2c,0xb5,0x6b,0xaf,0x92,\r
-0x01,0x24,0x61,0xd5,0xa2,0x96,0x4e,0x88,0x08,0x60,0x54,0x9e,0x33,0xbf,0x24,0x64,\r
-0x67,0xf5,0xef,0x4a,0xf1,0x66,0x89,0xad,0xdb,0x47,0x71,0xa7,0xeb,0x36,0x17,0xf0,\r
-0x48,0x01,0x49,0x6d,0xae,0x92,0x45,0x61,0xec,0x54,0x90,0x68,0x04,0x7c,0xe9,0xe1,\r
-0x0f,0xf8,0x26,0x9f,0xec,0xf1,0xe0,0xeb,0x85,0xb8,0x8f,0xc0,0x51,0xea,0xf3,0x29,\r
-0x05,0x5b,0x58,0xbc,0x9a,0xe5,0x47,0xfc,0x01,0x9f,0x69,0xfc,0x41,0xaf,0xa4,0x34,\r
-0x2f,0x0f,0x69,0x7e,0x18,0xd2,0xe0,0xd3,0x74,0x7d,0x3a,0xd7,0x4a,0xd3,0xe0,0x1b,\r
-0x62,0xb4,0xb2,0x85,0x61,0x89,0x07,0xa0,0x55,0x00,0x0a,0xd0,0x0c,0x18,0x02,0x08,\r
-0x20,0xf7,0x14,0x64,0x1a,0x43,0x16,0xbc,0xdb,0xe3,0xcf,0x88,0xff,0x00,0xb1,0x3c,\r
-0x0d,0x35,0xb4,0x6d,0x89,0xf5,0x17,0x16,0xeb,0x83,0xc8,0x5e,0xae,0x7e,0x98,0x18,\r
-0xff,0x00,0x81,0x0a,0xf4,0x83,0xc0,0xaf,0x99,0x7f,0x68,0x4f,0x10,0x9d,0x5f,0xc6,\r
-0x69,0xa7,0xa3,0x66,0x1d,0x3a,0x30,0x84,0x7f,0xd3,0x46,0xc3,0x37,0xe9,0xb4,0x7e,\r
-0x15,0xe0,0xe7,0x78,0x9f,0xaa,0xe0,0xa6,0xd6,0xf2,0xd1,0x7c,0xff,0x00,0xe0,0x1c,\r
-0x58,0xba,0x9e,0xce,0x93,0xf3,0x3c,0xbe,0x8a,0x28,0xaf,0xc7,0x4f,0x97,0x0a,0xf7,\r
-0x2f,0xd9,0xaf,0xc3,0xd9,0x93,0x55,0xd6,0xa4,0x5c,0xe3,0x16,0xb1,0x1f,0xfc,0x79,\r
-0xff,0x00,0xf6,0x5a,0xf0,0xda,0xfa,0xff,0x00,0xe1,0x77,0x87,0x8f,0x86,0x7c,0x0f,\r
-0xa5,0x5a,0x32,0x14,0x99,0xa2,0x13,0x4c,0x0f,0x50,0xef,0xf3,0x10,0x7e,0x99,0xc7,\r
-0xe1,0x5f,0x55,0xc3,0x98,0x6f,0x6d,0x8c,0xf6,0x8f,0x68,0x2b,0xfc,0xf6,0x47,0xa3,\r
-0x80,0xa7,0xcf,0x57,0x9b,0xb1,0xd6,0x51,0x49,0x4b,0x5f,0xab,0x1f,0x48,0x78,0x4f,\r
-0xed,0x35,0xa7,0x28,0x3a,0x1d,0xfa,0xaf,0xcc,0x7c,0xd8,0x5d,0xbd,0x7e,0xe9,0x5f,\r
-0xfd,0x9b,0xf3,0xaf,0x0a,0xaf,0xa3,0xff,0x00,0x69,0x38,0x03,0xf8,0x3a,0xc2,0x5c,\r
-0x72,0x97,0xca,0x33,0xec,0x63,0x7f,0xf0,0x15,0xf3,0x85,0x7e,0x47,0xc4,0x30,0x50,\r
-0xcc,0x26,0xd7,0x54,0x9f,0xe0,0x7c,0xce,0x39,0x5a,0xbb,0x0a,0x28,0xa2,0xbe,0x6c,\r
-0xe0,0x3e,0x92,0xfd,0x9b,0xef,0x84,0xfe,0x0c,0xbc,0xb6,0xce,0x5a,0x0b,0xc6,0xe3,\r
-0xd1,0x59,0x54,0x8f,0xd7,0x35,0xeb,0x35,0xe1,0x1f,0xb3,0x1d,0xd0,0x0d,0xe2,0x0b,\r
-0x62,0xdc,0x91,0x0c,0x8a,0xbf,0xf7,0xd8,0x27,0xf9,0x57,0xbb,0x66,0xbf,0x64,0xc9,\r
-0x6a,0x7b,0x4c,0x05,0x27,0xd9,0x5b,0xee,0x76,0x3e,0xa7,0x09,0x2e,0x6a,0x11,0x16,\r
-0x8a,0x28,0xaf,0x70,0xec,0x0a,0x28,0xa4,0x3d,0x28,0x03,0xc8,0x3f,0x69,0x0d,0x6f,\r
-0xec,0x9e,0x19,0xb1,0xd3,0x11,0x80,0x7b,0xd9,0xf7,0xb0,0xf5,0x44,0xe7,0xff,0x00,\r
-0x42,0x2b,0xf9,0x57,0xce,0x95,0xe9,0x7f,0xb4,0x06,0xb8,0x75,0x4f,0x1e,0x3d,0xa0,\r
-0x20,0xc5,0x61,0x0a,0xc2,0x30,0x73,0xf3,0x1f,0x99,0xbf,0xf4,0x20,0x3f,0x0a,0xf3,\r
-0x4a,0xfc,0x77,0x3b,0xaf,0xf5,0x8c,0x74,0xda,0xd9,0x69,0xf7,0x7f,0xc1,0x3e,0x5b,\r
-0x19,0x3e,0x7a,0xcf,0xcb,0x40,0xa2,0x8a,0x2b,0xc1,0x38,0xcf,0x55,0xfd,0x9d,0x74,\r
-0x53,0x7f,0xe3,0x2b,0x8b,0xf6,0x40,0x62,0xb1,0xb7,0x24,0x37,0xa3,0xb9,0xda,0x3f,\r
-0x40,0xf5,0xf4,0xb5,0x79,0x2f,0xec,0xe7,0xa2,0x7d,0x87,0xc1,0xf7,0x3a,0x83,0xc6,\r
-0x04,0x97,0xd7,0x07,0x6b,0xf7,0x31,0xa7,0xca,0x07,0xfd,0xf5,0xbf,0xf3,0xaf,0x5a,\r
-0xaf,0xd8,0x32,0x2a,0x1e,0xc3,0x01,0x0b,0xef,0x2d,0x7e,0xff,0x00,0xf8,0x16,0x3e,\r
-0xa3,0x07,0x0e,0x4a,0x2b,0xcf,0x50,0xa2,0x8a,0x2b,0xe8,0x0e,0xd0,0xaf,0x00,0xfd,\r
-0xa6,0xc6,0x35,0x3d,0x04,0xf6,0x30,0xcb,0xfc,0xd6,0xbd,0xfe,0xbc,0x67,0xf6,0x97,\r
-0xd2,0xbc,0xed,0x0f,0x49,0xd4,0x42,0x92,0x6d,0xe7,0x68,0x4e,0x07,0x00,0x3a,0xe7,\r
-0x27,0xf1,0x41,0xf9,0xd7,0x81,0x9e,0xc1,0xcf,0x2f,0xa8,0x97,0x93,0xfc,0x4e,0x2c,\r
-0x62,0xbd,0x09,0x1f,0x3d,0x51,0x45,0x15,0xf8,0xf1,0xf2,0xe1,0x5d,0xa7,0xc1,0xcb,\r
-0xc4,0xb1,0xf8,0x93,0xa2,0xbb,0x9c,0x2b,0xc8,0xf1,0x7e,0x2c,0x8c,0xa3,0xf5,0x22,\r
-0xb8,0xba,0xb1,0xa7,0xdf,0x4d,0xa5,0xdf,0xdb,0x5e,0x5b,0xb6,0xd9,0xed,0xe4,0x59,\r
-0x50,0xfa,0x32,0x9c,0x8f,0xe5,0x5d,0x38,0x6a,0xbe,0xc2,0xbc,0x2a,0xbf,0xb2,0xd3,\r
-0xfb,0x99,0x74,0xe5,0xc9,0x35,0x2e,0xcc,0xfb,0x88,0x52,0xd6,0x4f,0x86,0x3c,0x43,\r
-0x6d,0xe2,0x9d,0x0e,0xcf,0x53,0xb4,0x6c,0xc5,0x70,0x81,0xb6,0xe7,0x25,0x1b,0xba,\r
-0x9f,0x70,0x72,0x3f,0x0a,0xd6,0xaf,0xdd,0x21,0x38,0xce,0x2a,0x71,0x77,0x4c,0xfb,\r
-0x14,0xd3,0x57,0x41,0x45,0x14,0x55,0x8c,0x28,0xa4,0xc8,0xae,0x4f,0xe2,0x2f,0x8f,\r
-0xed,0x3c,0x07,0xa2,0xb5,0xcc,0x84,0x4b,0x7b,0x28,0x2b,0x6d,0x6d,0x9e,0x5d,0xbd,\r
-0x4f,0xfb,0x23,0xb9,0xff,0x00,0x1a,0xc6,0xb5,0x68,0x50,0xa6,0xea,0xd4,0x76,0x48,\r
-0x89,0x49,0x41,0x39,0x4b,0x63,0xcb,0x7f,0x68,0xdf,0x17,0x2d,0xc5,0xcd,0x9f,0x87,\r
-0xad,0xdf,0x3e,0x41,0x17,0x37,0x38,0xec,0xc4,0x10,0x8b,0xf9,0x12,0x7f,0x11,0x5e,\r
-0x27,0x56,0x75,0x2d,0x46,0xe3,0x56,0xbf,0x9e,0xf6,0xee,0x53,0x35,0xcc,0xee,0x64,\r
-0x91,0xcf,0x72,0x6a,0xb5,0x7e,0x2d,0x98,0x62,0xde,0x3b,0x13,0x2a,0xcf,0xae,0xde,\r
-0x9d,0x0f,0x94,0xaf,0x55,0xd6,0x9b,0x98,0x51,0x45,0x15,0xe7,0x18,0x16,0x74,0xcd,\r
-0x3e,0x6d,0x5b,0x51,0xb5,0xb2,0xb6,0x5d,0xf7,0x17,0x32,0x2c,0x51,0xa9,0xe8,0x59,\r
-0x8e,0x07,0xf3,0xaf,0xb5,0xb4,0x7d,0x3a,0x2d,0x1f,0x4a,0xb4,0xb1,0x80,0x62,0x1b,\r
-0x68,0x96,0x14,0x1e,0xca,0x00,0x1f,0xca,0xbc,0x03,0xf6,0x78,0xf0,0x69,0xd4,0x75,\r
-0xa9,0xb5,0xfb,0x84,0xff,0x00,0x47,0xb2,0x06,0x38,0x32,0x3e,0xf4,0xa4,0x72,0x7f,\r
-0x05,0x3f,0x99,0xf6,0xaf,0xa2,0x87,0x4a,0xfd,0x3b,0x86,0xb0,0x8e,0x8d,0x09,0x62,\r
-0x24,0xb5,0x9e,0xde,0x88,0xfa,0x0c,0xbe,0x97,0x2c,0x1c,0xdf,0x51,0x68,0xa4,0xcd,\r
-0x2d,0x7d,0x91,0xea,0x88,0x46,0x6b,0x33,0x5b,0xf0,0xd6,0x97,0xe2,0x2b,0x63,0x06,\r
-0xa5,0x61,0x05,0xec,0x7d,0x84,0xa8,0x09,0x1f,0x43,0xd4,0x7e,0x15,0xa9,0x45,0x4c,\r
-0xa1,0x19,0xae,0x59,0x2b,0xa1,0x34,0x9a,0xb3,0x3c,0x7b,0x5f,0xfd,0x9b,0xf4,0x8b,\r
-0xd6,0x32,0x69,0x57,0xd3,0xe9,0xac,0x4e,0x7c,0xb9,0x07,0x9d,0x18,0x1e,0x83,0x90,\r
-0x47,0xe6,0x6b,0xce,0x35,0xdf,0x81,0x3e,0x2a,0xd1,0x81,0x78,0xad,0xa2,0xd4,0xe2,\r
-0x19,0xf9,0xad,0x1f,0x2d,0x8e,0xdf,0x29,0xc1,0xfc,0xb3,0x5f,0x54,0x52,0x11,0x5f,\r
-0x3d,0x88,0xc8,0x30,0x35,0xf5,0x51,0xe5,0x7e,0x5f,0xe5,0xb1,0xc3,0x3c,0x15,0x19,\r
-0xf4,0xb7,0xa1,0xf0,0xe5,0xed,0x85,0xd6,0x9b,0x39,0x86,0xee,0xda,0x5b,0x59,0x87,\r
-0x58,0xe6,0x42,0x8d,0xf9,0x1a,0x82,0xbe,0xdb,0xd5,0xf4,0x1d,0x3f,0x5d,0xb6,0x36,\r
-0xfa,0x85,0x9c,0x37,0xb0,0x9f,0xe1,0x99,0x03,0x63,0xdc,0x7a,0x57,0x8b,0xfc,0x45,\r
-0xf8,0x03,0x1d,0xbd,0xb4,0xda,0x8f,0x86,0xb7,0xe5,0x32,0xef,0x60,0xe7,0x76,0x47,\r
-0x7d,0x84,0xf3,0x9f,0x63,0x9c,0xfa,0xf6,0xaf,0x91,0xc6,0xf0,0xe5,0x7a,0x11,0x75,\r
-0x28,0x4b,0x9d,0x2e,0x9b,0x3f,0xf8,0x27,0x9b,0x57,0x01,0x38,0x2e,0x68,0x3b,0xa3,\r
-0xc3,0x28,0xa0,0x8c,0x1c,0x74,0xa2,0xbe,0x40,0xf2,0xc2,0x8a,0x28,0xa0,0x0f,0x6f,\r
-0xfd,0x9d,0xbc,0x6b,0x22,0xdc,0xcf,0xe1,0xcb,0x99,0x0b,0x46,0xca,0x67,0xb5,0xdc,\r
-0x7e,0xe9,0x1f,0x79,0x07,0xb1,0xeb,0xf8,0x1a,0xf7,0xba,0xf8,0xf7,0xe1,0x7d,0xe3,\r
-0xd8,0xfc,0x41,0xd0,0x64,0x8c,0xe0,0xb5,0xd2,0xc6,0x7e,0x8d,0xf2,0x9f,0xd1,0x8d,\r
-0x7d,0x84,0x2b,0xf5,0x6e,0x1c,0xc4,0x4a,0xb6,0x13,0x92,0x6f,0xe1,0x76,0xf9,0x1f,\r
-0x47,0x80,0xa8,0xe7,0x4a,0xcf,0xa0,0xb4,0x51,0x45,0x7d,0x51,0xe9,0x08,0x78,0xaf,\r
-0x9f,0xbf,0x6a,0x3b,0xbd,0x96,0x51,0xc7,0x9e,0x89,0xd2,0xbe,0x81,0x35,0xf3,0x27,\r
-0xed,0x4f,0x77,0xfe,0x90,0x23,0x07,0xf8,0x45,0x78,0x59,0xd4,0xb9,0x70,0x53,0x3c,\r
-0xac,0xce,0x5c,0xb8,0x59,0xb3,0xe5,0x3f,0x11,0x3e,0xdb,0x19,0x4f,0xfb,0x26,0xbb,\r
-0xef,0xf8,0x26,0x55,0x81,0xb9,0xf8,0x97,0xf1,0x53,0x53,0xed,0x0d,0xa5,0x8d,0xb0,\r
-0x3f,0xef,0xbc,0xcd,0xff,0x00,0xb2,0x0a,0xf3,0x8f,0x16,0xc9,0xe5,0xe9,0xb3,0x9f,\r
-0x45,0xaf,0x63,0xff,0x00,0x82,0x5b,0xdb,0x16,0xb7,0xf8,0xab,0x7d,0xb7,0x89,0x35,\r
-0x1b,0x38,0x43,0x7a,0xec,0x8a,0x42,0x7f,0xf4,0x3a,0xf2,0xb2,0x28,0xe8,0xd9,0xf9,\r
-0xdf,0x0d,0x47,0x9b,0x33,0x9c,0xbb,0x44,0xfb,0xb3,0x9a,0x29,0xd4,0x57,0xd9,0x1f,\r
-0xac,0x85,0x52,0xd5,0xb5,0x28,0x74,0x9d,0x36,0xee,0xfa,0xe0,0xed,0x82,0xda,0x26,\r
-0x99,0xcf,0xfb,0x2a,0x32,0x6a,0xed,0x78,0xaf,0xed,0x53,0xe3,0x0f,0xec,0x0f,0x87,\r
-0xab,0xa5,0xc3,0x26,0xdb,0xad,0x5e,0x61,0x09,0x00,0xe0,0xf9,0x4b,0xf3,0x48,0x7e,\r
-0x9f,0x75,0x7f,0xe0,0x55,0xcd,0x89,0xac,0xb0,0xf4,0x65,0x55,0xf4,0x47,0x26,0x2e,\r
-0xba,0xc2,0xd0,0x9d,0x67,0xd1,0x1f,0x26,0x78,0x83,0x5a,0xb8,0xf1,0x6f,0x89,0x2f,\r
-0xf5,0x4b,0x8c,0xb5,0xc5,0xf5,0xc3,0x4a,0x47,0xa6,0x4f,0x03,0xf0,0x18,0x1f,0x85,\r
-0x7d,0xbd,0xf0,0x4b,0xc2,0x63,0xc2,0x3f,0x0f,0xf4,0xeb,0x76,0x4d,0xb3,0xcc,0x82,\r
-0x69,0x78,0xc7,0x26,0xbe,0x43,0xf8,0x3b,0xe1,0x46,0xf1,0x77,0x8f,0x74,0xcb,0x3d,\r
-0xbb,0xa1,0x59,0x04,0x92,0x9f,0x45,0x1c,0xd7,0xde,0xf0,0xc4,0xb0,0xc2,0x91,0xa0,\r
-0xda,0xaa,0x00,0x03,0xda,0xbe,0x4f,0x21,0xa2,0xea,0x54,0xa9,0x89,0x9f,0xa7,0xdf,\r
-0xab,0x3e,0x57,0x87,0xa8,0x39,0x73,0xe2,0xa7,0xbb,0xfe,0x99,0x25,0x14,0x56,0x47,\r
-0x8b,0xfc,0x53,0xa7,0x78,0x1f,0xc2,0x9a,0xcf,0x88,0xb5,0x79,0xbe,0xcf,0xa5,0xe9,\r
-0x36,0x73,0x5f,0x5d,0x4b,0x8c,0xec,0x8a,0x34,0x2e,0xe7,0x1d,0xf8,0x53,0x5f,0x6a,\r
-0x7d,0xa9,0xaf,0x45,0x7e,0x2d,0xcd,0xff,0x00,0x05,0x91,0xf8,0xd2,0x35,0x2b,0x86,\r
-0xb6,0xd1,0x7c,0x20,0xd6,0x2d,0x2b,0x18,0x22,0x9e,0xc2,0x7f,0x31,0x63,0x2c,0x76,\r
-0xab,0x30,0x9c,0x02,0x40,0xc0,0xce,0x2b,0xf5,0x5f,0xf6,0x6a,0xf1,0xbf,0x8a,0xfe,\r
-0x25,0x7c,0x0e,0xf0,0x8f,0x8a,0xfc,0x6b,0x65,0x63,0xa6,0xf8,0x83,0x5a,0xb3,0x5b,\r
-0xf9,0x2d,0x34,0xe4,0x74,0x8a,0x38,0xa4,0x25,0xa1,0xe1,0xd9,0x8e,0x4c,0x65,0x09,\r
-0xc9,0xea,0x48,0xa0,0x49,0xdc,0xf9,0xef,0xfe,0x0a,0xb9,0xf1,0xa3,0xfe,0x15,0x97,\r
-0xec,0xc9,0x73,0xe1,0xfb,0x39,0x8c,0x7a,0xb7,0x8c,0x6e,0x06,0x96,0x81,0x7a,0x8b,\r
-0x60,0x37,0xdc,0x1f,0xa1,0x50,0x13,0xfe,0xda,0x57,0xe2,0x00,0xd4,0x6e,0xc5,0xab,\r
-0xdb,0x0b,0xa9,0x85,0xb3,0xfd,0xe8,0x44,0x87,0x63,0x73,0x9e,0x47,0x4e,0xa2,0xbf,\r
-0xa2,0x9f,0x8f,0x5f,0xb2,0x2f,0xc3,0x3f,0xda,0x5e,0xfb,0x4b,0xbc,0xf1,0xf6,0x95,\r
-0x77,0xaa,0xcd,0xa6,0x44,0xf0,0xda,0x79,0x3a,0x8c,0xd6,0xeb,0x12,0xb1,0xcb,0x7c,\r
-0xa8,0xc0,0x12,0x48,0x19,0x24,0x67,0x81,0xe9,0x5e,0x33,0x7d,0xff,0x00,0x04,0x93,\r
-0xfd,0x9e,0xae,0xff,0x00,0xd5,0x69,0x5a,0xed,0x97,0xfd,0x70,0xd6,0x24,0x3f,0xfa,\r
-0x1e,0xea,0x62,0x6a,0xe7,0xe1,0xa7,0x34,0xf8,0x66,0x92,0xde,0x41,0x24,0x4e,0xd1,\r
-0x48,0x3a,0x32,0x1c,0x11,0xf8,0xd7,0xed,0x36,0xa9,0xff,0x00,0x04,0x70,0xf8,0x23,\r
-0x78,0xa7,0xec,0x9a,0xb7,0x8b,0xb4,0xf2,0x7b,0xa5,0xfc,0x2f,0x8f,0xfb,0xea,0x13,\r
-0x5c,0x9d,0xff,0x00,0xfc,0x11,0x47,0xe1,0xf4,0xad,0xfe,0x85,0xf1,0x0f,0xc4,0xd6,\r
-0xe3,0xd2,0xe2,0xde,0xde,0x5f,0xe4,0xab,0x4e,0xe2,0xb3,0x3f,0x28,0xad,0x3e,0x21,\r
-0xf8,0xaa,0xc3,0x02,0xd7,0xc4,0xda,0xc5,0xb6,0x3a,0x08,0x6f,0xe5,0x4c,0x7e,0x4d,\r
-0x5f,0xb1,0x9f,0xf0,0x49,0x2f,0x0c,0x78,0x9e,0x4f,0x82,0x3a,0xbf,0x8e,0x7c,0x53,\r
-0xae,0xea,0xda,0xcc,0xbe,0x20,0xbe,0xf2,0x74,0xf4,0xd4,0xef,0x25,0x9c,0x43,0x6d,\r
-0x06,0x54,0xb2,0x07,0x63,0x8d,0xf2,0x17,0xe9,0xd7,0x60,0xaf,0x36,0xbe,0xff,0x00,\r
-0x82,0x23,0xe8,0x0e,0xa7,0xec,0x9f,0x15,0xb5,0x28,0x4f,0xfd,0x36,0xd1,0xa3,0x93,\r
-0xf9,0x4c,0xb5,0xfa,0x0f,0xf0,0x97,0xe1,0xbe,0x9f,0xf0,0x87,0xe1,0x9f,0x86,0x7c,\r
-0x19,0xa5,0xb6,0xfb,0x1d,0x12,0xc2,0x2b,0x28,0xe5,0x2b,0xb4,0xc9,0xb5,0x70,0xce,\r
-0x47,0x38,0x2c,0xd9,0x63,0xcf,0x52,0x69,0x31,0xa4,0xce,0x8f,0x55,0xd4,0x62,0xd2,\r
-0x74,0xdb,0xab,0xd9,0xdb,0x6c,0x36,0xf1,0x34,0xae,0x7d,0x94,0x64,0xd7,0xc5,0x5a,\r
-0xb6,0xa5,0x2e,0xb1,0xaa,0x5d,0xdf,0x4e,0x73,0x35,0xcc,0xad,0x2b,0x7d,0x49,0xcd,\r
-0x7d,0x6b,0xf1,0x2b,0xc3,0xba,0x97,0x8a,0xfc,0x29,0x73,0xa5,0x69,0x93,0x41,0x04,\r
-0xd7,0x0c,0xa1,0xde,0x76,0x65,0x1b,0x01,0xc9,0x03,0x00,0xf2,0x70,0x07,0xd0,0x9a,\r
-0xf1,0x39,0x7f,0x67,0x2f,0x13,0xa2,0x92,0xb7,0x3a,0x6c,0x87,0xd1,0x66,0x70,0x7f,\r
-0x54,0xaf,0x85,0xe2,0x1a,0x18,0xbc,0x5c,0xe1,0x0a,0x34,0xdb,0x8a,0xd7,0x4e,0xe7,\r
-0x93,0x8e,0x85,0x5a,0x8d,0x46,0x11,0xba,0x47,0x95,0xd1,0x5e,0x87,0x3f,0xc0,0x5f,\r
-0x18,0xc2,0x7e,0x5b,0x18,0x26,0xf7,0x4b,0x84,0xfe,0xa4,0x55,0x39,0x3e,0x0a,0x78,\r
-0xd2,0x3c,0x9f,0xec,0x46,0x61,0xfe,0xcd,0xc4,0x47,0xff,0x00,0x66,0xaf,0x89,0x79,\r
-0x6e,0x36,0x3b,0xd2,0x97,0xdc,0xcf,0x25,0xd0,0xaa,0xbe,0xcb,0x32,0xfe,0x1d,0xf8,\r
-0x7b,0xfe,0x12,0x8f,0x19,0xe9,0x76,0x0c,0x81,0xe1,0x69,0x44,0x92,0x83,0xd3,0xcb,\r
-0x5f,0x99,0x87,0xe2,0x06,0x3f,0x1a,0xfb,0x1c,0x70,0x05,0x78,0xcf,0xc0,0xaf,0x87,\r
-0x5a,0x9f,0x86,0x75,0x2d,0x47,0x51,0xd6,0x2c,0x9a,0xd2,0x7d,0x82,0x08,0x55,0xc8,\r
-0x24,0x82,0x72,0xc7,0x82,0x7d,0x14,0x7e,0x75,0xec,0xd5,0xfa,0x37,0x0f,0x61,0x25,\r
-0x86,0xc2,0xb9,0x54,0x56,0x94,0x9f,0xe5,0xa2,0x3d,0xdc,0x0d,0x27,0x4e,0x9d,0xda,\r
-0xd5,0x8b,0x45,0x14,0x57,0xd4,0x9e,0x89,0xe6,0x1f,0xb4,0x3c,0x7e,0x67,0xc3,0xfc,\r
-0xff,0x00,0x72,0xee,0x36,0xfd,0x18,0x7f,0x5a,0xf9,0x8e,0xbe,0xa7,0xf8,0xf7,0x1e,\r
-0xff,0x00,0x86,0xb7,0xed,0xfd,0xc9,0x61,0x6f,0xfc,0x88,0x07,0xf5,0xaf,0x96,0x33,\r
-0x5f,0x96,0x71,0x32,0xb6,0x35,0x3f,0xee,0xaf,0xcd,0x9f,0x3b,0x98,0x2f,0xde,0xdf,\r
-0xc8,0x28,0xa2,0x8a,0xf9,0x23,0xcc,0x3d,0x5f,0xf6,0x6f,0xb9,0x31,0xf8,0xd6,0xf2,\r
-0x1c,0xe1,0x64,0xb1,0x63,0x8f,0x52,0x1d,0x3f,0xc4,0xd7,0xd2,0x63,0xad,0x7c,0xa1,\r
-0xf0,0x42,0xf1,0xad,0x3e,0x25,0x69,0x4a,0xa7,0x0b,0x30,0x96,0x26,0xfa,0x79,0x6c,\r
-0x7f,0x98,0x15,0xf5,0x78,0xaf,0xd5,0x38,0x6a,0x7c,0xd8,0x2e,0x5e,0xcd,0xff,0x00,\r
-0x99,0xf4,0x78,0x07,0x7a,0x36,0xec,0xc5,0xa2,0x8a,0x2b,0xeb,0x0f,0x48,0x2a,0x3b,\r
-0x89,0xd2,0xda,0x09,0x25,0x91,0x82,0x47,0x1a,0x96,0x66,0x27,0x80,0x00,0xe4,0xd3,\r
-0xcd,0x70,0xff,0x00,0x19,0xb5,0xcf,0xec,0x4f,0x87,0xba,0xa1,0x5c,0x79,0xb7,0x4a,\r
-0x2d,0x14,0x1e,0xfb,0xf8,0x6f,0xfc,0x77,0x71,0xfc,0x2b,0x9f,0x11,0x59,0x50,0xa3,\r
-0x3a,0xaf,0xa2,0x6c,0x89,0xcb,0x92,0x2e,0x5d,0x8f,0x96,0xb5,0xbd,0x56,0x4d,0x73,\r
-0x59,0xbe,0xd4,0x65,0x1b,0x64,0xba,0x9d,0xe6,0x2b,0xfd,0xdd,0xc4,0x9c,0x7e,0x15,\r
-0x4a,0x8a,0x2b,0xf0,0x99,0xc9,0xce,0x4e,0x4f,0x76,0x7c,0x73,0x77,0x77,0x61,0x40,\r
-0x04,0x90,0x07,0x24,0xd1,0x5d,0x17,0xc3,0xcd,0x1b,0xfb,0x7f,0xc6,0xda,0x3d,0x91,\r
-0x5d,0xc8,0xf7,0x0a,0xee,0x3d,0x51,0x7e,0x66,0xfd,0x14,0xd5,0xd1,0xa6,0xeb,0x54,\r
-0x8d,0x35,0xbb,0x69,0x0e,0x31,0x72,0x92,0x8a,0xea,0x7d,0x59,0xe0,0x9d,0x10,0x78,\r
-0x77,0xc2,0x7a,0x56,0x9e,0x17,0x6b,0x43,0x6e,0x81,0xc7,0xfb,0x64,0x65,0xbf,0x52,\r
-0x6b,0x76,0x90,0x74,0x18,0xe9,0x4b,0x5f,0xbb,0xd3,0x82,0xa7,0x05,0x05,0xb2,0x56,\r
-0x3e,0xc6,0x2b,0x95,0x24,0x82,0x8a,0x28,0xad,0x0a,0x0a,0xc0,0xf1,0xcf,0x86,0x93,\r
-0xc5,0xde,0x16,0xd4,0x34,0xb6,0x21,0x5a,0x78,0xff,0x00,0x76,0xc7,0xa2,0xc8,0x0e,\r
-0x54,0x9f,0x6c,0x81,0x5b,0xf4,0x86,0xb3,0xa9,0x08,0xd5,0x83,0x84,0xb6,0x7a,0x0a,\r
-0x49,0x49,0x38,0xbe,0xa7,0xc3,0x57,0x56,0xb2,0xd9,0x5c,0xcb,0x6f,0x3c,0x6d,0x14,\r
-0xd1,0x39,0x8d,0xd1,0x86,0x0a,0xb0,0x38,0x20,0xd4,0x55,0xf4,0x07,0xc6,0xef,0x85,\r
-0x32,0xea,0x8c,0xfe,0x20,0xd1,0xe1,0x32,0x5d,0x01,0x9b,0xab,0x64,0x1c,0xc8,0x07,\r
-0xf1,0xa8,0xee,0x40,0xea,0x3b,0x8f,0x7e,0xbf,0x3f,0xd7,0xe2,0xd9,0x86,0x06,0xa6,\r
-0x02,0xb3,0xa7,0x3d,0xba,0x3e,0xeb,0xfa,0xdc,0xf9,0x3a,0xf4,0x65,0x46,0x7c,0xac,\r
-0x28,0xa2,0x8a,0xf3,0x0e,0x73,0xb3,0xf8,0x73,0xf1,0x3a,0xfb,0xe1,0xf5,0xe3,0x04,\r
-0x43,0x77,0xa7,0x4a,0x73,0x35,0xab,0x1c,0x73,0xfd,0xe5,0x3d,0x8f,0xf3,0xfc,0xb1,\r
-0xf4,0x3f,0x86,0xbe,0x2b,0xf8,0x67,0xc4,0xd1,0x21,0x87,0x52,0x8a,0xd6,0x72,0x39,\r
-0xb7,0xbb,0x61,0x13,0x83,0xe9,0xc9,0xc1,0xfc,0x09,0xaf,0x91,0x68,0xaf,0xa1,0xcb,\r
-0xf3,0xbc,0x46,0x02,0x3e,0xcd,0x7b,0xd1,0xec,0xfa,0x7a,0x33,0xba,0x8e,0x2e,0xa5,\r
-0x15,0xcb,0xba,0x3e,0xe7,0x8e,0xe2,0x29,0x90,0x3c,0x72,0x23,0xa1,0xe8,0xca,0xc0,\r
-0x83,0x54,0xf5,0x0d,0x7f,0x4c,0xd2,0x50,0xb5,0xee,0xa1,0x6b,0x68,0xa3,0xbc,0xd3,\r
-0x2a,0xff,0x00,0x33,0x5f,0x13,0x2c,0x8e,0x83,0x0a,0xcc,0xa3,0xd8,0xe2,0x9a,0x79,\r
-0x39,0x27,0x27,0xde,0xbd,0xd7,0xc5,0x52,0xb7,0xbb,0x47,0x5f,0x5f,0xf8,0x07,0x67,\r
-0xf6,0x93,0xe9,0x1f,0xc7,0xfe,0x01,0xf4,0x6f,0x8c,0x7f,0x68,0x5d,0x2b,0x4c,0x89,\r
-0xe1,0xd0,0xe3,0x3a,0xa5,0xd9,0xc8,0x13,0x30,0x29,0x0a,0x7e,0x7c,0xb7,0xe1,0xc1,\r
-0xf5,0xaf,0x03,0xd7,0xbc,0x41,0x7f,0xe2,0x6d,0x4a,0x5b,0xfd,0x46,0xe1,0xae,0x6e,\r
-0x64,0xea,0xcd,0xd0,0x0e,0xc0,0x0e,0xc0,0x7a,0x0a,0xce,0xa2,0xbe,0x5f,0x1d,0x9a,\r
-0x62,0x71,0xef,0xf7,0xaf,0x4e,0xcb,0x63,0xce,0xad,0x88,0xa9,0x5b,0xe2,0xd8,0x28,\r
-0xa2,0x8a,0xf2,0x4e,0x60,0xad,0x8f,0x09,0xf8,0x5e,0xf7,0xc6,0x1a,0xe5,0xbe,0x9b,\r
-0x62,0x84,0xc9,0x21,0xcb,0xc8,0x47,0xcb,0x1a,0x7f,0x13,0x1f,0x61,0xfa,0x9c,0x0e,\r
-0xf4,0x78,0x5f,0xc2,0x9a,0x97,0x8c,0x35,0x44,0xb1,0xd3,0x60,0x32,0xc8,0x7e,0xfb,\r
-0x9c,0x84,0x89,0x7f,0xbc,0xc7,0xb0,0xfd,0x7d,0x33,0x5f,0x54,0x7c,0x3e,0xf8,0x7f,\r
-0x63,0xe0,0x2d,0x24,0x41,0x6e,0x04,0xd7,0x72,0x00,0x6e,0x2e,0x98,0x61,0xa4,0x3f,\r
-0xd0,0x0e,0xc2,0xbe,0x8b,0x29,0xca,0x67,0x8f,0xa8,0xa7,0x35,0x6a,0x6b,0x77,0xdf,\r
-0xc9,0x1d,0xb8,0x6c,0x34,0xab,0xca,0xef,0xe1,0x35,0xbc,0x35,0xe1,0xeb,0x5f,0x0b,\r
-0x68,0xb6,0xba,0x65,0x92,0x95,0x82,0x04,0xda,0x09,0xea,0xc7,0xbb,0x1f,0x72,0x72,\r
-0x7f,0x1a,0xd4,0x14,0x52,0xd7,0xeb,0x70,0x84,0x69,0xc5,0x46,0x2a,0xc9,0x1f,0x4e,\r
-0x92,0x4a,0xc8,0xc7,0xf1,0x4f,0x8a,0x6c,0x7c,0x21,0xa5,0x9d,0x43,0x51,0x76,0x4b,\r
-0x60,0xe9,0x19,0x28,0xbb,0x8e,0x58,0xe3,0xa7,0xb7,0x5e,0x39,0xc0,0xa9,0x74,0x3f,\r
-0x12,0x69,0x9e,0x23,0xb5,0x17,0x1a,0x6d,0xf4,0x37,0x91,0x11,0x92,0x62,0x6c,0x95,\r
-0xfa,0x8e,0xa0,0xfb,0x1a,0xf1,0xdf,0xda,0x5f,0x5d,0xf9,0x74,0x8d,0x1d,0x1b,0xae,\r
-0xeb,0xa9,0x00,0x3f,0xf0,0x15,0xff,0x00,0xd9,0xab,0xc4,0x2c,0xaf,0xee,0x74,0xeb,\r
-0x85,0x9e,0xd2,0xe2,0x5b,0x69,0xd7,0xee,0xc9,0x0b,0x94,0x61,0xf8,0x8a,0xf8,0xec,\r
-0x77,0x10,0x3c,0x16,0x32,0x54,0x79,0x79,0xa2,0xad,0xeb,0x73,0xcb,0xad,0x8d,0xf6,\r
-0x55,0x5c,0x6d,0x74,0x7d,0xc7,0x9a,0x5a,0xf9,0x63,0x44,0xf8,0xf1,0xe2,0xbd,0x1c,\r
-0x2a,0x4d,0x71,0x16,0xa7,0x10,0xfe,0x1b,0xa8,0xf2,0xd8,0xff,0x00,0x79,0x70,0x7f,\r
-0x3c,0xd7,0x6f,0xa6,0x7e,0xd3,0x36,0xcc,0x48,0xd4,0x34,0x39,0xa2,0x03,0xf8,0xad,\r
-0xa6,0x0f,0x93,0xf4,0x60,0xbf,0xce,0xbb,0xe8,0xf1,0x0e,0x06,0xaa,0xf7,0xa4,0xe2,\r
-0xfc,0xd7,0xf9,0x5c,0xda,0x18,0xea,0x32,0xdd,0xd8,0xf6,0xfc,0xd1,0x9a,0xf3,0x1b,\r
-0x0f,0xda,0x1f,0xc2,0xb7,0x6a,0x0c,0xdf,0x6d,0xb1,0x3e,0x93,0x41,0x9f,0xfd,0x00,\r
-0xb5,0x5f,0x5f,0x8e,0xbe,0x0b,0x23,0xfe,0x42,0xce,0x3e,0xb6,0xb2,0xff,0x00,0xf1,\r
-0x35,0xe9,0x47,0x33,0xc1,0x4b,0x6a,0xb1,0xfb,0xcd,0xd6,0x22,0x93,0xda,0x48,0xef,\r
-0xe9,0x1d,0x82,0xa1,0x24,0x80,0x31,0xce,0x6b,0xcd,0xaf,0xff,0x00,0x68,0x1f,0x09,\r
-0x5a,0xc2,0xcd,0x0c,0xd7,0x37,0xcc,0x3f,0x82,0x1b,0x76,0x52,0x7f,0xef,0xbd,0xa3,\r
-0xf5,0xaf,0x35,0xf1,0xe7,0xc7,0xab,0xef,0x12,0x5a,0x4d,0xa7,0xe9,0x36,0xe7,0x4c,\r
-0xb2,0x94,0x15,0x92,0x56,0x6c,0xcc,0xeb,0xe9,0xc7,0x0b,0xef,0x8c,0xfd,0x6b,0x93,\r
-0x13,0x9d,0xe0,0xa8,0x41,0xb5,0x35,0x27,0xd9,0x6a,0x67,0x53,0x17,0x4a,0x0a,0xf7,\r
-0xb9,0xe7,0xbe,0x28,0x96,0x0b,0x8f,0x12,0xea,0xd2,0xda,0xe3,0xec,0xcf,0x77,0x2b,\r
-0x45,0xb7,0xa6,0xd2,0xe4,0x8c,0x7e,0x15,0x97,0x45,0x15,0xf9,0x04,0xe5,0xcf,0x37,\r
-0x2e,0xee,0xe7,0xcb,0xb7,0x77,0x70,0xa2,0x8a,0x2a,0x04,0x75,0xff,0x00,0x08,0xf4,\r
-0xf6,0xd4,0xbe,0x22,0xe8,0x88,0x01,0xc4,0x73,0x79,0xc4,0x8e,0xc1,0x14,0xb7,0xf4,\r
-0xaf,0xae,0xc7,0x4a,0xf0,0x7f,0xd9,0xbf,0xc2,0xac,0x64,0xbe,0xf1,0x04,0xc9,0x85,\r
-0xdb,0xf6,0x6b,0x72,0x47,0x5e,0xee,0x7f,0x40,0x3f,0x3a,0xf7,0x81,0xd2,0xbf,0x57,\r
-0xe1,0xcc,0x3b,0xa3,0x82,0xe7,0x97,0xda,0x77,0xf9,0x74,0x3e,0x93,0x03,0x07,0x1a,\r
-0x57,0x7d,0x45,0xa2,0x8a,0x2b,0xea,0x4f,0x44,0x69,0xaf,0x92,0xff,0x00,0x69,0xfb,\r
-0xbf,0x33,0x5a,0x74,0xce,0x70,0xd5,0xf5,0xab,0x74,0xaf,0x8c,0x7f,0x68,0xdb,0xbf,\r
-0x3b,0xc4,0xb2,0x8c,0xff,0x00,0x19,0xaf,0x99,0xcf,0xdd,0xb0,0xb6,0xee,0xd1,0xe0,\r
-0x67,0x72,0xe5,0xc2,0x48,0xf9,0xcb,0xc7,0x32,0xec,0xd2,0x67,0x3d,0x3e,0x5a,0xfa,\r
-0x47,0xfe,0x09,0x79,0xa6,0x88,0x7e,0x0f,0xf8,0xbb,0x50,0xc7,0xcd,0x77,0xe2,0x39,\r
-0x57,0x38,0xec,0x90,0x42,0x07,0xea,0x4d,0x7c,0xc3,0xf1,0x1e,0x5f,0x2f,0x46,0x9c,\r
-0xe7,0xb1,0xfe,0x55,0xf5,0xff,0x00,0xfc,0x13,0x53,0x4f,0x36,0x9f,0xb3,0x2c,0x17,\r
-0x24,0x63,0xed,0xda,0xcd,0xf5,0xc0,0x3e,0xb8,0x93,0xcb,0xff,0x00,0xda,0x75,0x9e,\r
-0x47,0x1b,0x53,0xb9,0xf1,0xbc,0x27,0x1b,0xe2,0xeb,0xcf,0xc9,0x1f,0x55,0x51,0x45,\r
-0x15,0xf5,0x47,0xea,0x21,0x5f,0x13,0x7e,0xd3,0x3e,0x2f,0x3e,0x27,0xf8,0x9b,0x71,\r
-0x68,0x8e,0x4d,0xa6,0x92,0x9f,0x64,0x41,0xdb,0x7f,0x59,0x0f,0xe7,0x81,0xff,0x00,\r
-0x01,0xaf,0xae,0xbc,0x73,0xe2,0x68,0x7c,0x1d,0xe1,0x2d,0x57,0x59,0x9b,0x1b,0x6c,\r
-0xe0,0x69,0x14,0x1f,0xe2,0x7c,0x61,0x57,0xf1,0x62,0x07,0xe3,0x5f,0x9f,0x28,0x2e,\r
-0x75,0xcd,0x57,0x74,0x8c,0xd3,0x5d,0x5d,0xcc,0x59,0x98,0xf2,0x59,0xd9,0xb2,0x4f,\r
-0xe6,0x6b,0xe4,0xb8,0x83,0x11,0xcb,0x4e,0x34,0x23,0xbb,0xd7,0xfa,0xf9,0x9f,0x1b,\r
-0xc4,0x58,0x87,0xc9,0x0c,0x34,0x77,0x93,0xbb,0xf4,0xff,0x00,0x87,0x3e,0x96,0xfd,\r
-0x92,0x7c,0x1f,0xe4,0xd9,0xdf,0x6b,0xf2,0xa6,0x0c,0x87,0xc9,0x88,0x91,0xdb,0xb9,\r
-0xaf,0xa3,0xeb,0x97,0xf8,0x6f,0xe1,0xa4,0xf0,0x97,0x83,0x74,0xcd,0x39,0x54,0x2b,\r
-0x47,0x10,0x2f,0x8e,0xec,0x7a,0xd7,0x51,0x5e,0xde,0x5d,0x87,0xfa,0xb6,0x1a,0x14,\r
-0xfa,0xf5,0xf5,0x3e,0x8f,0x03,0x87,0x58,0x5c,0x3c,0x29,0x76,0x41,0x5f,0x0c,0x7f,\r
-0xc1,0x5c,0xbe,0x35,0x9f,0x87,0x7f,0xb3,0xbc,0x3e,0x0f,0xb2,0x9b,0xcb,0xd5,0x3c,\r
-0x65,0x75,0xf6,0x56,0xda,0xd8,0x65,0xb4,0x88,0xac,0x93,0x1f,0x70,0xc7,0xcb,0x42,\r
-0x3b,0x87,0x6f,0x4a,0xfb,0x9e,0xbf,0x23,0xff,0x00,0xe0,0xb6,0x56,0x5a,0x90,0xf8,\r
-0x89,0xf0,0xd6,0xf2,0x48,0xdc,0xe9,0x07,0x4a,0xb9,0x8a,0x17,0xc7,0xc8,0x26,0x13,\r
-0x29,0x90,0x7d,0x76,0x98,0xff,0x00,0x2a,0xf4,0xd1,0xdc,0xcf,0x86,0xbf,0x67,0xbf,\r
-0x04,0xe9,0xbf,0x12,0x7e,0x39,0x78,0x17,0xc3,0x3a,0xcd,0xe4,0x76,0x1a,0x56,0xa9,\r
-0xac,0x5b,0xdb,0x5d,0x4f,0x2b,0x05,0x51,0x19,0x71,0xb8,0x64,0xf7,0x61,0xf2,0x8f,\r
-0x72,0x2b,0xfa,0x16,0xf8,0xcd,0xf1,0x1b,0x4e,0xf8,0x1d,0xf0,0x6f,0xc5,0x1e,0x2e,\r
-0x9e,0x38,0xe3,0xb4,0xd0,0x34,0xc9,0x27,0x86,0xd9,0x70,0x81,0xdd,0x53,0x11,0x44,\r
-0xbd,0x86,0xe6,0xda,0xa0,0x7b,0xd7,0xf3,0x4e,0xac,0x51,0x83,0x29,0x2a,0xc0,0xe4,\r
-0x11,0xd4,0x57,0x5f,0xaa,0xfc,0x62,0xf1,0xde,0xbb,0xe1,0x97,0xf0,0xee,0xa7,0xe3,\r
-0x2d,0x7b,0x51,0xd0,0x5f,0x6e,0xed,0x32,0xeb,0x52,0x9a,0x5b,0x73,0xb4,0x86,0x5c,\r
-0xc6,0xcc,0x47,0x04,0x02,0x38,0xe3,0x14,0xc8,0x4e,0xc7,0x77,0xe1,0x9f,0xda,0x7f,\r
-0xe3,0xb6,0xb5,0xe2,0xab,0x6b,0x5d,0x23,0xe2,0x6f,0x8b,0x5b,0x55,0xd5,0x2f,0x16,\r
-0x28,0xa1,0x4d,0x5a,0x72,0xad,0x2c,0x8f,0x85,0x01,0x4b,0x60,0x0c,0xb7,0x40,0x31,\r
-0x5f,0xd0,0x5f,0xc3,0xcd,0x07,0x50,0xf0,0xbf,0x81,0x74,0x0d,0x27,0x55,0xd4,0xae,\r
-0x35,0x9d,0x52,0xce,0xc6,0x18,0x6f,0x35,0x0b,0xa9,0x0c,0x92,0x5c,0xcc,0x10,0x79,\r
-0x92,0x33,0x1e,0x4e,0x5b,0x26,0xbf,0x99,0xff,0x00,0x09,0xf8,0xaf,0x55,0xf0,0x37,\r
-0x89,0x34,0xed,0x7f,0x43,0xbc,0x6d,0x3f,0x58,0xd3,0xa7,0x5b,0x9b,0x5b,0xa4,0x55,\r
-0x66,0x8a,0x45,0x39,0x56,0x01,0x81,0x19,0x1e,0xe2,0xbe,0x84,0xd3,0x3f,0xe0,0xa5,\r
-0x1f,0xb4,0x76,0x95,0xf7,0x3e,0x24,0x5c,0x4e,0x3d,0x2e,0xb4,0xfb,0x49,0x7f,0xf4,\r
-0x28,0x8d,0x0c,0x69,0x9f,0xbf,0xd4,0x57,0xe1,0x66,0x99,0xff,0x00,0x05,0x62,0xfd,\r
-0xa1,0xec,0x17,0x12,0xeb,0xda,0x46,0xa1,0xef,0x73,0xa4,0x42,0x3f,0xf4,0x00,0xb5,\r
-0xbf,0x63,0xff,0x00,0x05,0x87,0xf8,0xed,0x6b,0x81,0x35,0x9f,0x84,0xaf,0x3f,0xeb,\r
-0xae,0x99,0x2a,0x9f,0xfc,0x76,0x61,0x4a,0xc5,0x5d,0x1f,0xb6,0x94,0x57,0x86,0xfe,\r
-0xc6,0x7f,0x16,0x3c,0x69,0xf1,0xc7,0xe0,0x3e,0x8b,0xe3,0x8f,0x1c,0x58,0xe9,0xba,\r
-0x6e,0xa3,0xac,0x49,0x2c,0xd6,0xb6,0xfa,0x64,0x4f,0x1c,0x7f,0x66,0x0d,0xb5,0x18,\r
-0x87,0x76,0x39,0x62,0xac,0x7a,0xe3,0x05,0x7f,0x1f,0x4a,0xf8,0xa1,0xe3,0xfd,0x3f,\r
-0xe1,0x67,0xc3,0xbf,0x12,0x78,0xbf,0x54,0x60,0x2c,0x34,0x4b,0x09,0xaf,0xa5,0x05,\r
-0xb1,0xbf,0x62,0x92,0x14,0x7b,0xb1,0xc2,0x8f,0x72,0x29,0x0c,0xea,0x28,0xaf,0xcb,\r
-0xad,0x3b,0xfe,0x0b,0x77,0x64,0x42,0x8b,0xef,0x84,0xd3,0xab,0x77,0xfb,0x3e,0xb8,\r
-0x0f,0xf3,0x80,0x57,0x61,0xa5,0x7f,0xc1,0x6a,0xfe,0x1b,0xcb,0x1e,0x75,0x2f,0x00,\r
-0x78,0xa6,0xd2,0x4f,0xee,0xda,0xbd,0xb4,0xe3,0xf3,0x69,0x13,0xf9,0x53,0xb0,0xae,\r
-0x8f,0xd1,0x5a,0x2b,0xe0,0x5b,0x4f,0xf8,0x2c,0xef,0xc1,0x89,0xb1,0xe7,0x78,0x6b,\r
-0xc6,0xb6,0xe7,0xd3,0xec,0x56,0xad,0xfc,0xae,0x2b,0xab,0xd1,0xbf,0xe0,0xad,0xdf,\r
-0xb3,0xe6,0xa6,0xa0,0xdd,0x6a,0x9a,0xee,0x90,0x7d,0x2f,0x34,0x89,0x1b,0x1f,0xf7,\r
-0xe8,0xbd,0x01,0x74,0x7d,0x9f,0x45,0x7c,0xa7,0x69,0xff,0x00,0x05,0x44,0xfd,0x9b,\r
-0x6e,0x80,0x27,0xe2,0x04,0x90,0x67,0xfe,0x7a,0xe8,0xb7,0xe3,0xf9,0x42,0x6b,0xa6,\r
-0xd2,0xff,0x00,0xe0,0xa0,0xbf,0xb3,0xce,0xae,0x14,0xc3,0xf1,0x4f,0x46,0x8b,0x77,\r
-0x41,0x74,0xb3,0x40,0x7f,0xf1,0xf4,0x14,0x87,0x73,0xe8,0x6a,0x2b,0xc9,0xf4,0xff,\r
-0x00,0xda,0xcb,0xe0,0xb6,0xa8,0xa1,0xad,0xfe,0x2b,0xf8,0x35,0x81,0xec,0xfa,0xe5,\r
-0xba,0x1f,0xc9,0x9c,0x56,0xfd,0x97,0xc7,0x5f,0x86,0xda,0x96,0x3e,0xc9,0xf1,0x07,\r
-0xc2,0xd7,0x39,0xe9,0xe5,0x6b,0x56,0xcd,0x9f,0xc9,0xe8,0x03,0xb4,0x9a,0x08,0xe7,\r
-0x52,0x92,0x22,0xc8,0x87,0xaa,0xb0,0xc8,0x3f,0x85,0x50,0x9f,0xc3,0x3a,0x3d,0xcf,\r
-0xfa,0xed,0x2e,0xce,0x5f,0xf7,0xed,0xd0,0xff,0x00,0x4a,0x76,0x9f,0xe2,0x4d,0x27,\r
-0x56,0x8c,0x49,0x63,0xa9,0xd9,0x5e,0xc6,0x79,0x0d,0x6f,0x70,0x92,0x03,0xf9,0x13,\r
-0x5a,0x0a,0xe1,0x86,0x41,0x04,0x7a,0x83,0x51,0x28,0x46,0x5f,0x12,0xb8,0x9a,0x4f,\r
-0x74,0x73,0xf3,0x7c,0x3c,0xf0,0xc5,0xc7,0x32,0x78,0x7f,0x4e,0x3f,0xf6,0xea,0x83,\r
-0xfa,0x55,0x49,0x7e,0x15,0x78,0x46,0x51,0xce,0x81,0x66,0xbf,0xee,0x47,0xb7,0xf9,\r
-0x57,0x59,0x9a,0x5a,0xc2,0x58,0x5a,0x12,0xde,0x0b,0xee,0x44,0x3a,0x70,0x7b,0xc5,\r
-0x1c,0x8e,0x9d,0xf0,0xaf,0xc2,0xfa,0x4e,0xa5,0x6f,0x7f,0x65,0xa5,0xad,0xbd,0xd4,\r
-0x0d,0xba,0x37,0x49,0x5f,0x83,0xd3,0xa6,0x71,0x5d,0x68,0xeb,0x4b,0x45,0x69,0x4e,\r
-0x8d,0x3a,0x2a,0xd4,0xe2,0x92,0xf2,0x2a,0x31,0x8c,0x34,0x8a,0xb0,0x51,0x45,0x15,\r
-0xb1,0x42,0x1a,0xe2,0x7e,0x28,0x7c,0x3c,0x9b,0xe2,0x1d,0x85,0x9d,0xaa,0x6a,0x22,\r
-0xc2,0x3b,0x79,0x0c,0xa5,0x4c,0x3e,0x66,0xf6,0xc6,0x07,0xf1,0x0c,0x63,0x27,0xd7,\r
-0xad,0x76,0xf4,0x56,0x15,0xe8,0x43,0x13,0x4d,0xd2,0xa8,0xaf,0x17,0xb9,0x13,0x82,\r
-0xa9,0x17,0x19,0x6c,0x7c,0xf5,0x37,0xec,0xcd,0xaa,0x2e,0x7c,0x9d,0x66,0xd1,0xff,\r
-0x00,0xdf,0x8d,0x97,0xfc,0x6a,0x93,0xfe,0xcd,0xbe,0x23,0x19,0xd9,0x7d,0xa6,0xb7,\r
-0xd6,0x49,0x07,0xfe,0xc9,0x5f,0x49,0x51,0x5e,0x0b,0xe1,0xdc,0xbd,0xfd,0x97,0xf7,\r
-0xb3,0x8d,0xe0,0x68,0xbe,0x9f,0x89,0xf3,0x1c,0xff,0x00,0xb3,0xbf,0x8a,0xa2,0x52,\r
-0x55,0xf4,0xf9,0x88,0xfe,0x14,0x9c,0x8f,0xe6,0xa2,0xbb,0x0f,0x83,0x7f,0x0a,0xb5,\r
-0x8f,0x0a,0x78,0x9a,0x7d,0x4b,0x57,0x82,0x38,0x55,0x20,0x31,0xc3,0xb6,0x45,0x7d,\r
-0xcc,0xc4,0x64,0xf0,0x78,0xc0,0x18,0xfc,0x6b,0xdb,0x28,0xaa,0xa1,0x90,0xe1,0x30,\r
-0xd5,0x63,0x5a,0x17,0xbc,0x7c,0xc2,0x18,0x2a,0x54,0xe4,0xa4,0xaf,0xa0,0x51,0x45,\r
-0x15,0xf4,0x67,0x78,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x87,0x9a,0xf2,0xef,\r
-0x88,0x7f,0x03,0xac,0x3c,0x55,0x24,0x97,0xda,0x63,0xa6,0x9b,0xa9,0xb6,0x59,0xb8,\r
-0xfd,0xd4,0xc7,0xd5,0x80,0xe8,0x7d,0xc7,0xe4,0x6b,0xd4,0xa8,0xae,0x4c,0x4e,0x16,\r
-0x8e,0x2e,0x1e,0xce,0xb4,0x6e,0x8c,0xea,0x53,0x8d,0x55,0xcb,0x35,0x73,0xe3,0x1f,\r
-0x13,0x78,0x1f,0x5b,0xf0,0x84,0xc5,0x35,0x4b,0x09,0x20,0x8f,0x38,0x13,0xaf,0xcd,\r
-0x13,0x7d,0x18,0x71,0xf8,0x75,0xf6,0xac,0x2a,0xfb,0x9e,0x68,0x52,0x78,0xca,0x48,\r
-0xaa,0xe8,0x78,0x2a,0xc3,0x20,0xd7,0x15,0xae,0x7c,0x18,0xf0,0x9e,0xb8,0x59,0xdf,\r
-0x4d,0x5b,0x49,0x4f,0xfc,0xb4,0xb3,0x6f,0x2b,0xf4,0x1f,0x2f,0xe9,0x5f,0x0f,0x8a,\r
-0xe1,0x79,0x5e,0xf8,0x69,0xfc,0x9f,0xf9,0xa3,0xc7,0xa9,0x97,0x3d,0xe9,0xbf,0xbc,\r
-0xf9,0x36,0x8a,0xf7,0xed,0x43,0xf6,0x65,0xb2,0x91,0x89,0xb0,0xd6,0xe7,0x85,0x7b,\r
-0x2d,0xc4,0x2b,0x27,0xea,0x0a,0xd6,0x0d,0xcf,0xec,0xd5,0xad,0x23,0x91,0x06,0xa9,\r
-0x63,0x2a,0xf6,0x32,0x07,0x43,0xfa,0x03,0x5e,0x0c,0xf2,0x2c,0xc2,0x0f,0xf8,0x77,\r
-0xf4,0x68,0xe3,0x78,0x3a,0xeb,0xec,0x9e,0x3f,0x45,0x7a,0xb1,0xfd,0x9b,0xfc,0x4b,\r
-0xda,0xf7,0x4b,0x3f,0xf6,0xd6,0x4f,0xfe,0x22,0x9e,0x9f,0xb3,0x6f,0x88,0xc9,0xf9,\r
-0xef,0xb4,0xd5,0x1e,0xd2,0x48,0x7f,0xf6,0x4a,0xc1,0x64,0xf8,0xf7,0xff,0x00,0x2e,\r
-0x99,0x1f,0x55,0xad,0xfc,0xac,0xf2,0x6a,0x2b,0xdb,0x74,0xff,0x00,0xd9,0x9a,0xe9,\r
-0xb9,0xbd,0xd7,0x22,0x8f,0xd5,0x60,0xb7,0x2f,0xfa,0x92,0x3f,0x95,0x75,0x9a,0x3f,\r
-0xec,0xf3,0xe1,0x9b,0x0c,0x35,0xdb,0x5d,0x6a,0x4c,0x3b,0x4b,0x26,0xc4,0xfc,0x97,\r
-0x07,0xf5,0xae,0xda,0x5c,0x3d,0x8f,0xa8,0xf5,0x8a,0x8f,0xab,0xff,0x00,0x2b,0x9a,\r
-0xc7,0x03,0x5a,0x5b,0xab,0x1f,0x36,0x59,0xd9,0x5c,0x6a,0x17,0x09,0x05,0xac,0x12,\r
-0xdc,0xcc,0xe7,0x0b,0x1c,0x28,0x59,0x8f,0xd0,0x0a,0xf5,0x5f,0x05,0xfe,0xcf,0x9a,\r
-0x9e,0xaa,0xd1,0xdc,0xeb,0xb2,0x7f,0x66,0x5a,0x13,0x9f,0x21,0x08,0x69,0xd8,0x7e,\r
-0xa1,0x7f,0x1c,0x9f,0x6a,0xf7,0xdd,0x1f,0xc3,0xba,0x6f,0x87,0xe1,0x31,0x69,0xd6,\r
-0x36,0xf6,0x51,0x9e,0xa2,0x18,0xc2,0xe7,0xeb,0xeb,0x5a,0x75,0xf4,0xd8,0x3e,0x19,\r
-0xa3,0x49,0xa9,0xe2,0x25,0xcc,0xfb,0x6c,0xbf,0xcd,0x9e,0x85,0x2c,0xbe,0x31,0xd6,\r
-0xa3,0xb9,0x93,0xe1,0xdf,0x0c,0xe9,0xbe,0x15,0xd3,0xd6,0xcf,0x4c,0xb5,0x4b,0x58,\r
-0x47,0x5d,0xbf,0x79,0xcf,0xab,0x1e,0xa4,0xfd,0x6b,0x54,0x74,0xa5,0xa2,0xbe,0xca,\r
-0x10,0x8d,0x38,0xa8,0xc1,0x59,0x23,0xd5,0x49,0x45,0x59,0x05,0x35,0xba,0x73,0x4e,\r
-0xa8,0x2f,0x56,0x66,0xb5,0x98,0x40,0x50,0x4f,0xb0,0xf9,0x65,0xfe,0xee,0xec,0x71,\r
-0x9f,0x6c,0xd5,0x3d,0x15,0xc6,0x7c,0x99,0xf1,0x6f,0x5d,0xfe,0xdf,0xf1,0xfe,0xab,\r
-0x32,0xb6,0xe8,0xa1,0x93,0xec,0xd1,0xf3,0x9e,0x13,0x83,0x8f,0xab,0x6e,0x3f,0x8d,\r
-0x71,0xd5,0xdd,0x6b,0xff,0x00,0x06,0x7c,0x5b,0xa3,0xb4,0x92,0x35,0x81,0xd4,0x50,\r
-0x1c,0x99,0xac,0xdb,0xcc,0x2d,0xef,0xb7,0xef,0x7e,0x95,0xc5,0xde,0xd9,0x5c,0x69,\r
-0xb3,0x18,0x6e,0xed,0xe5,0xb5,0x98,0x75,0x8e,0x64,0x28,0xdf,0x91,0xe6,0xbf,0x11,\r
-0xc6,0xd2,0xc4,0x2a,0xd3,0xa9,0x5e,0x0d,0x36,0xdb,0xd5,0x1f,0x23,0x5a,0x33,0xe7,\r
-0x72,0x92,0xdc,0x86,0x8a,0x28,0xaf,0x38,0xc0,0x28,0xa2,0x8a,0x00,0x28,0xa2,0x8a,\r
-0x00,0x28,0xa2,0xae,0xe9,0x5a,0x26,0xa1,0xae,0xcf,0xe4,0xe9,0xd6,0x53,0xde,0xcb,\r
-0xdd,0x60,0x42,0xd8,0xf7,0x38,0xe9,0xf8,0xd5,0x46,0x32,0x9b,0xe5,0x8a,0xbb,0x1a,\r
-0x4d,0xe8,0x8a,0x55,0xd4,0x78,0x03,0xc0,0x17,0xfe,0x3d,0xd5,0xd6,0xde,0xdd,0x5a,\r
-0x2b,0x38,0xc8,0x37,0x17,0x44,0x7c,0xb1,0xaf,0xa0,0xf5,0x63,0xd8,0x7f,0x4a,0xef,\r
-0xbc,0x1b,0xfb,0x3b,0xde,0xdd,0xba,0x5c,0x78,0x86,0x71,0x67,0x00,0xe4,0xda,0x40,\r
-0xc1,0xa4,0x6f,0x62,0xc3,0x81,0xf8,0x67,0xf0,0xaf,0x76,0xd1,0x74,0x5b,0x1f,0x0f,\r
-0xd8,0x47,0x65,0xa7,0xdb,0x25,0xad,0xb4,0x63,0xe5,0x44,0x1f,0xa9,0xf5,0x3e,0xe6,\r
-0xbe,0xc3,0x2c,0xe1,0xfa,0xb5,0xa4,0xaa,0x62,0x97,0x2c,0x7b,0x75,0x7f,0xe4,0x7a,\r
-0x98,0x7c,0x14,0xa4,0xd4,0xaa,0x68,0x83,0x45,0xd1,0xad,0x74,0x0d,0x32,0xdb,0x4f,\r
-0xb2,0x8c,0x45,0x6d,0x02,0x04,0x45,0xf6,0xf5,0x3e,0xa4,0xfa,0xd5,0xe1,0x4b,0x45,\r
-0x7e,0x99,0x18,0xa8,0x25,0x18,0xec,0x8f,0x7d,0x24,0x95,0x90,0x51,0x45,0x15,0x43,\r
-0x1b,0x21,0xdb,0x1b,0x1f,0x40,0x4d,0x7c,0x35,0xf1,0xd6,0xeb,0xcf,0xf1,0x4c,0xbc,\r
-0xe7,0xe6,0x26,0xbe,0xe0,0xbe,0x7f,0x2e,0xce,0x76,0x3d,0x90,0x9f,0xd2,0xbe,0x0b,\r
-0xf8,0xbb,0x38,0x9f,0xc5,0x13,0xfd,0x4f,0xf3,0xaf,0x91,0xe2,0x19,0x5a,0x9d,0x38,\r
-0xf7,0x67,0xcb,0x71,0x0c,0xad,0x86,0xb1,0xe0,0x5f,0x15,0xe7,0xf2,0xb4,0x59,0xb9,\r
-0xec,0x7f,0x95,0x7d,0xeb,0xfb,0x03,0x69,0xbf,0xd9,0xdf,0xb2,0x7f,0x81,0x7d,0x6e,\r
-0x23,0xb8,0xb9,0x38,0xff,0x00,0x6e,0xe2,0x53,0x5f,0x9f,0x7f,0x19,0x26,0x11,0xe8,\r
-0x92,0xf3,0x8f,0x94,0xff,0x00,0x2a,0xfd,0x29,0xfd,0x90,0xec,0x06,0x9b,0xfb,0x31,\r
-0x7c,0x33,0x84,0x2e,0xdc,0xe8,0x76,0xd2,0x90,0x7d,0x5d,0x77,0x9f,0xd5,0xab,0xb3,\r
-0x26,0x56,0xa2,0x78,0x1c,0x1f,0x1b,0xfb,0x79,0xf9,0xa3,0xd7,0xa8,0xa2,0x8a,0xfa,\r
-0x23,0xf4,0x83,0xe7,0x5f,0xda,0xf7,0xc6,0x0d,0x69,0xa2,0xe9,0x5e,0x1c,0x81,0xf0,\r
-0x6f,0x64,0x37,0x37,0x00,0x7f,0x71,0x3e,0xe8,0x3f,0x56,0x39,0xff,0x00,0x80,0xd7,\r
-0x94,0x7e,0xcf,0x3e,0x12,0xff,0x00,0x84,0xa3,0xe2,0x15,0xa3,0x3a,0x6e,0xb7,0xb3,\r
-0xfd,0xfb,0xfa,0x71,0xd2,0xb2,0x7e,0x36,0xf8,0xb1,0xbc,0x65,0xf1,0x33,0x5a,0xbb,\r
-0x0f,0xbe,0xda,0xde,0x53,0x67,0x6f,0xce,0x40,0x48,0xf2,0x38,0xfa,0xb6,0xe3,0xf8,\r
-0xd7,0xd0,0x7f,0xb2,0xb7,0x84,0x46,0x93,0xe1,0x29,0xf5,0x79,0x53,0x13,0xde,0xbe,\r
-0x14,0x91,0xfc,0x03,0xff,0x00,0xaf,0x5f,0x01,0xff,0x00,0x23,0x1c,0xd3,0xfb,0xa9,\r
-0xfe,0x0b,0xfc,0xd9,0xf9,0xfd,0x2f,0xf8,0x52,0xcd,0x5c,0xf7,0x8c,0x7f,0x25,0xff,\r
-0x00,0x04,0xf7,0x30,0x30,0x00,0xe9,0x4b,0x48,0x29,0x6b,0xef,0xcf,0xd0,0x02,0xbc,\r
-0xff,0x00,0xe3,0x67,0xc0,0x9f,0x05,0xfe,0xd0,0x9e,0x0c,0x97,0xc3,0x1e,0x37,0xd1,\r
-0xe3,0xd5,0xb4,0xd2,0xe2,0x58,0x9b,0x71,0x49,0xad,0xe5,0x00,0x81,0x24,0x4e,0x39,\r
-0x46,0xc1,0x23,0x8e,0xa0,0x90,0x72,0x09,0x15,0xe8,0x14,0x50,0x07,0xe6,0x47,0x8d,\r
-0x3f,0xe0,0x89,0xda,0x1d,0xc5,0xc3,0x4b,0xe1,0x5f,0x89,0xb7,0xfa,0x7c,0x1c,0x9f,\r
-0x23,0x57,0xd3,0x92,0xe5,0x87,0xfd,0xb4,0x47,0x8f,0xff,0x00,0x41,0xaf,0xcb,0x8f,\r
-0x1b,0x68,0x56,0x5e,0x17,0xf1,0x86,0xb5,0xa3,0xe9,0xda,0xb4,0x7a,0xf5,0x8e,0x9f,\r
-0x79,0x2d,0xac,0x3a,0x9c,0x31,0x98,0xe3,0xba,0x54,0x72,0xa2,0x55,0x52,0x49,0x0a,\r
-0xd8,0xc8,0xe7,0xa1,0xaf,0xe9,0x9b,0xc6,0x1a,0x1d,0xc7,0x89,0x7c,0x2b,0xac,0x69,\r
-0x16,0x9a,0x94,0xba,0x35,0xcd,0xfd,0x9c,0xb6,0xb1,0xea,0x10,0x20,0x69,0x2d,0x99,\r
-0xd0,0xa8,0x91,0x01,0xe0,0xb2,0xe7,0x23,0x3c,0x64,0x0a,0xfc,0xdd,0xd4,0x3f,0xe0,\r
-0x89,0x1a,0x41,0x95,0x5a,0xc7,0xe2,0x9d,0xea,0xc6,0x18,0x12,0x97,0x3a,0x42,0x31,\r
-0x23,0xb8,0xca,0xca,0x3f,0x95,0x3b,0x92,0xd1,0xf2,0x97,0xc2,0x7f,0xf8,0x26,0x5f,\r
-0xc6,0x3f,0x8c,0xbf,0x0d,0x34,0x4f,0x1b,0xe8,0x03,0x41,0x87,0x4b,0xd5,0xe2,0x69,\r
-0xad,0xed,0xf5,0x0b,0xd7,0x86,0xe3,0x60,0x76,0x50,0xc5,0x7c,0xb2,0x30,0xdb,0x77,\r
-0x0e,0x79,0x04,0x1a,0xd3,0xbc,0xff,0x00,0x82,0x4e,0x7e,0xd1,0x16,0xa4,0x88,0xf4,\r
-0x0d,0x1e,0xe8,0x0e,0xf0,0xeb,0x30,0x8c,0xff,0x00,0xdf,0x44,0x57,0xed,0xff,0x00,\r
-0x85,0x7c,0x35,0x63,0xe0,0xdf,0x0c,0xe9,0x3a,0x06,0x99,0x17,0x91,0xa6,0xe9,0x76,\r
-0x91,0x59,0x5a,0xc5,0x9c,0xec,0x8a,0x34,0x08,0x83,0xf2,0x51,0x5a,0xb4,0x5c,0x2c,\r
-0x8f,0xc0,0x4d,0x47,0xfe,0x09,0xa7,0xfb,0x47,0x69,0xcc,0xc0,0xfc,0x38,0x9a,0xe5,\r
-0x57,0xf8,0xad,0xb5,0x1b,0x47,0x07,0xe9,0xfb,0xdc,0x9a,0xc6,0xd1,0xbf,0x60,0x7f,\r
-0x8e,0xf7,0xde,0x25,0xd3,0x34,0xbb,0xcf,0x86,0x7e,0x20,0xb0,0x86,0xea,0xee,0x2b,\r
-0x79,0x6f,0x5e,0xd7,0x74,0x50,0x2b,0x38,0x53,0x23,0x32,0x92,0x02,0xa8,0x39,0x27,\r
-0x3d,0x05,0x7f,0x42,0x78,0xa0,0x80,0x7b,0x51,0x70,0xe5,0x46,0x2f,0x82,0xfc,0x29,\r
-0x63,0xe0,0x5f,0x07,0x68,0x9e,0x1c,0xd3,0x23,0x58,0xb4,0xfd,0x26,0xce,0x1b,0x28,\r
-0x11,0x46,0x00,0x48,0xd0,0x28,0xfd,0x05,0x7c,0x4f,0xff,0x00,0x05,0x7d,0xf8,0xb1,\r
-0x73,0xe1,0x4f,0x80,0x9a,0x6f,0x82,0x34,0xd5,0xb8,0x6b,0xef,0x15,0xde,0xff,0x00,\r
-0xa4,0x98,0x63,0x2c,0xa2,0xce,0xdf,0x6b,0xb8,0x62,0x3a,0x66,0x46,0x84,0x0f,0x50,\r
-0x1b,0xd2,0xbe,0xf3,0xa6,0xb2,0x2b,0x75,0x00,0xfd,0x45,0x22,0x8f,0xe5,0xad,0xa3,\r
-0x64,0x24,0x32,0xb2,0xe3,0xfb,0xc3,0x14,0xd1,0xcf,0x4e,0x6b,0xfa,0x8b,0xbc,0xd1,\r
-0x74,0xfd,0x42,0x33,0x1d,0xd5,0x85,0xb5,0xca,0x1e,0xab,0x34,0x2a,0xe0,0xfe,0x04,\r
-0x57,0x2d,0xab,0xfc,0x11,0xf8,0x77,0xaf,0xa9,0x5d,0x4b,0xc0,0x7e,0x19,0xbf,0x53,\r
-0xd4,0x5c,0xe9,0x16,0xf2,0x67,0xf3,0x4a,0x77,0x23,0x94,0xfe,0x67,0x71,0x9a,0x2b,\r
-0xfa,0x3a,0xba,0xfd,0x90,0x3e,0x07,0x5e,0xe7,0xcd,0xf8,0x43,0xe0,0x9c,0x9e,0xa5,\r
-0x34,0x1b,0x64,0x3f,0x98,0x41,0x5c,0xbe,0xad,0xff,0x00,0x04,0xfb,0xfd,0x9e,0xb5,\r
-0x9c,0xf9,0xdf,0x0b,0x74,0x58,0x73,0xff,0x00,0x3e,0x7e,0x6d,0xbf,0xfe,0x8b,0x75,\r
-0xc5,0x3b,0x87,0x29,0xfc,0xf6,0xd1,0x5f,0xbd,0x17,0x5f,0xf0,0x4b,0x8f,0xd9,0xb2,\r
-0xe9,0xcb,0x0f,0x01,0xcd,0x01,0x3f,0xf3,0xcb,0x5b,0xbe,0x03,0xf2,0xf3,0xab,0x9f,\r
-0xd5,0x3f,0xe0,0x92,0x1f,0xb3,0xed,0xfe,0xef,0xb3,0xe9,0xba,0xf6,0x9b,0x9e,0x9f,\r
-0x66,0xd5,0xdd,0xb1,0xff,0x00,0x7f,0x03,0x51,0x70,0xe5,0x3f,0x0d,0xe8,0xaf,0xd9,\r
-0xab,0xef,0xf8,0x23,0x0f,0xc1,0xdb,0x87,0x63,0x6d,0xe2,0x8f,0x19,0x5a,0x03,0xd1,\r
-0x7e,0xd5,0x6c,0xe0,0x7e,0x70,0x56,0x05,0xff,0x00,0xfc,0x11,0x43,0xc0,0x32,0x03,\r
-0xf6,0x2f,0x88,0x9e,0x24,0xb7,0x3d,0xbe,0xd1,0x6f,0x6f,0x2e,0x3f,0x25,0x5a,0x2e,\r
-0x1c,0xac,0xfc,0x89,0x8a,0xee,0x68,0x71,0xe5,0xcd,0x24,0x78,0xfe,0xeb,0x11,0x5a,\r
-0xf6,0x3e,0x3b,0xf1,0x2e,0x98,0x41,0xb3,0xf1,0x0e,0xab,0x69,0x8e,0x9e,0x45,0xec,\r
-0xa9,0xfc,0x9a,0xbf,0x4c,0x35,0x5f,0xf8,0x22,0x28,0x24,0xff,0x00,0x66,0x7c,0x59,\r
-0xd8,0x3b,0x0b,0xbd,0x13,0x71,0xff,0x00,0xc7,0x67,0x15,0xcd,0xde,0xff,0x00,0xc1,\r
-0x12,0xbc,0x5d,0x19,0x3f,0x64,0xf8,0x9d,0xa2,0x4e,0x3b,0x79,0xda,0x6c,0xd1,0xff,\r
-0x00,0x27,0x6a,0x05,0x66,0x7c,0x2f,0xa6,0xfe,0xd0,0x9f,0x14,0x34,0x62,0x0d,0x8f,\r
-0xc4,0x5f,0x15,0x5a,0xe3,0xa7,0x95,0xac,0xdc,0x2f,0xfe,0xcf,0x5d,0x56,0x9f,0xfb,\r
-0x6a,0xfc,0x77,0xd2,0xc0,0x16,0xff,0x00,0x15,0xfc,0x53,0x81,0xda,0x5d,0x45,0xe4,\r
-0xff,0x00,0xd0,0xb3,0x5f,0x4c,0x6a,0xdf,0xf0,0x46,0x1f,0x8b,0x96,0xc7,0xfe,0x25,\r
-0xfe,0x2c,0xf0,0x85,0xf0,0xff,0x00,0xa6,0xb3,0x5c,0xc2,0x7f,0xf4,0x4b,0x57,0x29,\r
-0x7d,0xff,0x00,0x04,0x87,0xf8,0xfd,0x68,0x48,0x8a,0x1f,0x0d,0x5e,0x81,0xde,0x1d,\r
-0x57,0x19,0xff,0x00,0xbe,0xd1,0x68,0x1d,0x99,0xe6,0x56,0x1f,0xf0,0x50,0xcf,0xda,\r
-0x23,0x4f,0x60,0x53,0xe2,0x86,0xab,0x28,0x1d,0xae,0x22,0x82,0x5f,0xfd,0x0a,0x33,\r
-0x5d,0x4e,0x9b,0xff,0x00,0x05,0x4c,0xfd,0xa3,0x34,0xec,0x67,0xc6,0x36,0x97,0x80,\r
-0x76,0xb9,0xd2,0x2d,0x9b,0x3f,0x92,0x03,0x4b,0xa9,0xff,0x00,0xc1,0x2c,0x7f,0x68,\r
-0xdd,0x3c,0x9d,0x9e,0x0d,0xb4,0xbd,0x03,0xbd,0xb6,0xb1,0x68,0x73,0xf8,0x34,0x8a,\r
-0x6b,0x8d,0xbf,0xff,0x00,0x82,0x7f,0xfe,0xd0,0xba,0x73,0xb2,0xc9,0xf0,0xb3,0x5a,\r
-0x93,0x6f,0x7b,0x7f,0x2a,0x50,0x7e,0x9b,0x5c,0xe6,0x8d,0x03,0x53,0xd5,0xac,0x7f,\r
-0xe0,0xaf,0x7f,0x1f,0x6d,0x14,0x09,0x64,0xf0,0xcd,0xe7,0xfb,0x53,0x69,0x44,0x1f,\r
-0xfc,0x72,0x45,0xae,0x9f,0x4b,0xff,0x00,0x82,0xce,0xfc,0x5e,0xb4,0x50,0x2f,0x7c,\r
-0x2f,0xe1,0x1b,0xff,0x00,0x53,0xf6,0x7b,0x88,0xcf,0xe9,0x35,0x7c,0xc5,0x7b,0xfb,\r
-0x1b,0xfc,0x73,0xd3,0xf7,0x79,0xff,0x00,0x09,0xbc,0x5c,0x02,0x8c,0x92,0x9a,0x4c,\r
-0xce,0x07,0xe2,0xaa,0x6b,0x90,0xd4,0x7e,0x0a,0xfc,0x42,0xd1,0xd9,0x96,0xfb,0xc0,\r
-0x9e,0x25,0xb4,0x2b,0xf7,0xbc,0xed,0x22,0xe1,0x71,0xf9,0xa5,0x1a,0x05,0xd9,0xf7,\r
-0xa6,0x9f,0xff,0x00,0x05,0xb3,0xf1,0x7c,0x48,0x3e,0xdd,0xf0,0xcb,0x44,0xb8,0x7f,\r
-0x5b,0x7d,0x46,0x68,0x87,0xe4,0x55,0xab,0x7f,0x4f,0xff,0x00,0x82,0xdd,0xce,0x31,\r
-0xf6,0xef,0x84,0x91,0xb7,0xa9,0xb7,0xd7,0x88,0xfd,0x0c,0x06,0xbf,0x32,0xee,0x7c,\r
-0x31,0xac,0x59,0x92,0x27,0xd2,0xaf,0x61,0x23,0xaf,0x99,0x6c,0xeb,0x8f,0xcc,0x56,\r
-0x73,0xa1,0x8d,0xb6,0xb0,0x2a,0xde,0x87,0x8a,0x34,0x0b,0xb3,0xf5,0xc7,0x4a,0xff,\r
-0x00,0x82,0xd8,0xf8,0x36,0x54,0xce,0xa5,0xf0,0xd7,0x5d,0xb6,0x6e,0xe2,0xd2,0xfa,\r
-0x19,0x87,0xfe,0x3c,0x12,0xba,0x0b,0x2f,0xf8,0x2d,0x17,0xc2,0x59,0x71,0xf6,0x9f,\r
-0x06,0xf8,0xc6,0xdc,0xfa,0xa4,0x36,0xae,0x3f,0xf4,0x78,0xaf,0xc6,0xdc,0xe7,0xbd,\r
-0x18,0x34,0x58,0x2e,0xcf,0xdb,0xbd,0x37,0xfe,0x0a,0xfd,0xf0,0x16,0xf5,0x03,0x5c,\r
-0x7f,0xc2,0x4d,0x60,0x4f,0x69,0xb4,0xb0,0xf8,0xff,0x00,0xbe,0x24,0x6a,0xe9,0xec,\r
-0xbf,0xe0,0xaa,0x5f,0xb3,0x75,0xdc,0x41,0xe4,0xf1,0xb5,0xdd,0xa3,0x1f,0xe0,0x9b,\r
-0x44,0xbd,0x24,0x7e,0x2b,0x11,0x1f,0xad,0x7e,0x0e,0xe2,0x8a,0x2c,0x1c,0xc7,0xf4,\r
-0x01,0x63,0xff,0x00,0x05,0x23,0xfd,0x9c,0x6f,0xc0,0xd9,0xf1,0x32,0xce,0x2c,0xf6,\r
-0x9e,0xc6,0xee,0x3f,0xfd,0x0a,0x21,0x5d,0x6e,0x99,0xfb,0x6a,0xfc,0x06,0xd5,0xe3,\r
-0x0f,0x07,0xc5,0xcf,0x08,0xc6,0x0f,0x6b,0xad,0x56,0x2b,0x73,0xf9,0x48,0x54,0xd7,\r
-0xf3,0xa5,0x9a,0x29,0x58,0x39,0x8f,0xe9,0x32,0xcf,0xf6,0x9c,0xf8,0x3f,0xa8,0x15,\r
-0x16,0xdf,0x15,0x3c,0x17,0x39,0x6e,0x82,0x3f,0x10,0x5a,0x1c,0xff,0x00,0xe4,0x4a,\r
-0xeb,0xb4,0xdf,0x1f,0x78,0x63,0x59,0x50,0xd6,0x1e,0x22,0xd2,0x6f,0x94,0xf2,0x0d,\r
-0xb5,0xf4,0x52,0x03,0xf9,0x31,0xaf,0xe6,0x16,0x9c,0xb2,0x32,0x10,0x55,0x8a,0x91,\r
-0xdc,0x1a,0x2c,0x1c,0xc7,0xf5,0x25,0x14,0xf1,0xcc,0x9b,0xe3,0x75,0x75,0xf5,0x52,\r
-0x08,0xa7,0xe6,0xbf,0x97,0x8b,0x7f,0x10,0xea,0xb6,0x98,0xf2,0x35,0x3b,0xc8,0x71,\r
-0xd3,0xcb,0xb8,0x75,0xc7,0xe4,0x6b,0x7b,0x4f,0xf8,0xc3,0xe3,0xcd,0x2b,0x1f,0x62,\r
-0xf1,0xb7,0x88,0xad,0x31,0xd3,0xc9,0xd5,0x67,0x4c,0x7e,0x4f,0x45,0x87,0xcc,0x7f,\r
-0x4d,0x39,0xa5,0xaf,0xe7,0x07,0x4e,0xfd,0xae,0x3e,0x35,0xe9,0x48,0xa9,0x69,0xf1,\r
-0x5b,0xc5,0xf0,0xa2,0xf0,0x17,0xfb,0x66,0x72,0x3f,0x22,0xd5,0xd1,0xe9,0xff,0x00,\r
-0xb7,0xbf,0xed,0x07,0xa6,0xe3,0xca,0xf8,0xab,0xaf,0xc9,0x8e,0xd7,0x12,0x24,0xdf,\r
-0xfa,0x1a,0x9a,0x2c,0x1c,0xc8,0xfe,0x86,0xe8,0xaf,0xc0,0xed,0x33,0xfe,0x0a,0x75,\r
-0xfb,0x46,0xe9,0x7d,0x3c,0x7c,0x2e,0x87,0xa5,0xd6,0x99,0x69,0x27,0xf3,0x8f,0x35,\r
-0xd2,0xd9,0x7f,0xc1,0x5b,0x3f,0x68,0x4b,0x5c,0x79,0xba,0xae,0x85,0x79,0xff,0x00,\r
-0x5d,0xb4,0x88,0xc6,0x7f,0xef,0x82,0xb4,0x58,0x77,0x47,0xee,0x65,0x15,0xf8,0xa9,\r
-0xa6,0xff,0x00,0xc1,0x63,0xbe,0x37,0x5a,0x11,0xf6,0xad,0x2f,0xc2,0x77,0xc3,0xbe,\r
-0xeb,0x09,0x90,0xff,0x00,0xe3,0xb3,0x0a,0xea,0xf4,0xff,0x00,0xf8,0x2d,0x67,0xc4,\r
-0x28,0x71,0xf6,0xdf,0x87,0xfe,0x1b,0xb9,0xff,0x00,0xae,0x33,0xdc,0x45,0xfc,0xd9,\r
-0xa8,0xb0,0x5d,0x1f,0xb0,0x14,0x57,0xe4,0xf5,0x8f,0xfc,0x16,0xe7,0x5b,0x56,0x1f,\r
-0x6c,0xf8,0x51,0x60,0xeb,0xdc,0xc1,0xad,0x3a,0x9f,0xd6,0x13,0x5d,0x66,0x99,0xff,\r
-0x00,0x05,0xb7,0xd0,0x5d,0x07,0xf6,0x8f,0xc2,0xdd,0x4a,0x27,0xef,0xf6,0x5d,0x56,\r
-0x37,0x1f,0xf8,0xf4,0x62,0x8b,0x05,0xd1,0xfa,0x6b,0x45,0x7e,0x77,0xd8,0xff,0x00,\r
-0xc1,0x6a,0x7e,0x18,0xc8,0x83,0xed,0x7e,0x06,0xf1,0x6c,0x12,0x1e,0xa2,0x1f,0xb2,\r
-0xc8,0x07,0xe2,0x65,0x5f,0xe5,0x5d,0x16,0x9b,0xff,0x00,0x05,0x8e,0xf8,0x23,0x76,\r
-0x07,0xda,0x74,0xaf,0x17,0x58,0x9e,0xfb,0xec,0x21,0x7c,0x7f,0xdf,0x33,0x1a,0x56,\r
-0x0b,0xa3,0xee,0xea,0x2b,0xe3,0xdd,0x33,0xfe,0x0a,0xbd,0xfb,0x3a,0xdf,0x45,0xbe,\r
-0x7f,0x12,0x6a,0xba,0x71,0xfe,0xe5,0xce,0x8d,0x72,0xc7,0xff,0x00,0x21,0xab,0x0a,\r
-0xdd,0xb2,0xff,0x00,0x82,0x9c,0x7e,0xcd,0xd7,0xcc,0x14,0x7c,0x43,0x10,0x93,0xff,\r
-0x00,0x3d,0xb4,0xab,0xd4,0xfe,0x70,0xd0,0x3b,0x9f,0x52,0xd1,0x5e,0x13,0xa6,0xfe,\r
-0xdd,0x5f,0x00,0x35,0x58,0x95,0xe2,0xf8,0xb1,0xe1,0xa8,0x81,0xed,0x75,0x77,0xe4,\r
-0x1f,0xc9,0xc0,0x35,0xbd,0x6b,0xfb,0x59,0x7c,0x14,0xbd,0x0a,0x61,0xf8,0xb5,0xe0,\r
-0xa6,0xdd,0xd0,0x1d,0x7e,0xd4,0x13,0xf8,0x17,0xa0,0x0f,0x58,0xa2,0xb8,0xed,0x33,\r
-0xe3,0x27,0x80,0xb5,0xa4,0x56,0xd3,0xfc,0x6d,0xe1,0xdb,0xd5,0x6e,0x86,0xdf,0x55,\r
-0x81,0xf3,0xf9,0x3d,0x74,0xd6,0x9a,0xb5,0x8d,0xfc,0x61,0xed,0xaf,0x2d,0xee,0x10,\r
-0xf4,0x68,0xa5,0x56,0x07,0xf1,0x06,0x80,0x2d,0xd4,0x17,0x56,0x70,0x5e,0x46,0x63,\r
-0x9e,0x08,0xe7,0x8c,0xf5,0x59,0x14,0x30,0x3f,0x81,0xa9,0x43,0x82,0x32,0x0e,0x7e,\r
-0x94,0xb9,0xa4,0xd2,0x6a,0xcc,0x37,0x39,0x4b,0xff,0x00,0x85,0x9e,0x14,0xd4,0x41,\r
-0x12,0xe8,0x56,0x6a,0x4f,0x56,0x85,0x3c,0xa3,0xf9,0xae,0x2b,0x02,0xf3,0xf6,0x7d,\r
-0xf0,0x95,0xc6,0x7c,0xb8,0x6e,0xad,0x73,0xff,0x00,0x3c,0xae,0x09,0xff,0x00,0xd0,\r
-0xb3,0x5e,0x95,0x9a,0x2b,0x86,0xa6,0x5f,0x84,0xab,0xf1,0xd2,0x8b,0xf9,0x23,0x07,\r
-0x42,0x9c,0xb7,0x8a,0x3c,0x7e,0x6f,0xd9,0xa7,0x44,0x63,0xfb,0xad,0x57,0x50,0x4f,\r
-0xf7,0xbc,0xb6,0xff,0x00,0xd9,0x45,0x56,0x6f,0xd9,0x9b,0x4f,0xcf,0xcb,0xad,0x5c,\r
-0x8f,0xac,0x4a,0x7f,0xad,0x7b,0x55,0x26,0x2b,0x8d,0xe4,0xb9,0x7b,0xff,0x00,0x97,\r
-0x4b,0xf1,0xff,0x00,0x33,0x3f,0xaa,0x50,0xfe,0x53,0xc6,0x13,0xf6,0x66,0xd3,0x54,\r
-0xfc,0xda,0xcd,0xd1,0xff,0x00,0x76,0x35,0x15,0x7e,0xd3,0xf6,0x70,0xf0,0xdc,0x0c,\r
-0x0c,0xd7,0x7a,0x85,0xcf,0xb3,0x48,0x8a,0x3f,0x45,0xaf,0x58,0xc5,0x2d,0x38,0xe4,\r
-0xd8,0x08,0xed,0x49,0x02,0xc2,0xd1,0x5f,0x64,0xe2,0x74,0xcf,0x83,0x7e,0x11,0xd2,\r
-0x88,0x29,0xa3,0xc5,0x3b,0x7a,0xdc,0xb3,0x4b,0xfa,0x31,0x22,0xba,0xfb,0x4b,0x2b,\r
-0x7b,0x08,0x56,0x1b,0x68,0x23,0x82,0x25,0xe0,0x24,0x48,0x14,0x0f,0xc0,0x54,0xf4,\r
-0x57,0xa5,0x4b,0x0f,0x46,0x82,0xb5,0x28,0x25,0xe8,0x8e,0x88,0xc2,0x30,0xf8,0x55,\r
-0x82,0x8a,0x28,0xae,0x82,0xc2,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x0c,0xef,0x10,\r
-0xcb,0xe4,0xe8,0x97,0xaf,0xe9,0x13,0x7f,0x2a,0xf8,0x0b,0xe2,0x14,0xe6,0x7f,0x11,\r
-0x5d,0x31,0xe7,0xe6,0x35,0xf7,0x7f,0x8e,0x66,0xf2,0x3c,0x2d,0xa8,0x36,0x71,0xfb,\r
-0xb2,0x2b,0xe0,0x2f,0x18,0x4b,0xe6,0xeb,0x37,0x6d,0xfe,0xd1,0xaf,0x88,0xe2,0x29,\r
-0x7b,0xf4,0xa3,0xea,0x7c,0x67,0x12,0x4a,0xd4,0xa2,0x8f,0x00,0xf8,0xed,0x75,0xe5,\r
-0x68,0x93,0x8c,0xf4,0x42,0x7f,0x4a,0xfd,0x6a,0xf8,0x37,0xa6,0xff,0x00,0x63,0x7c,\r
-0x24,0xf0,0x55,0x81,0x50,0x86,0xdb,0x45,0xb3,0x88,0xa8,0x18,0xc1,0x10,0xa0,0xaf,\r
-0xc8,0x7f,0x8e,0xbf,0xe9,0x36,0x82,0xd8,0x13,0x99,0x59,0x63,0xe3,0xfd,0xa3,0x8f,\r
-0xeb,0x5f,0xb3,0x7a,0x25,0xa8,0xb1,0xd1,0xec,0x6d,0x87,0x48,0x60,0x8e,0x31,0xf8,\r
-0x28,0x1f,0xd2,0xbd,0xcc,0xa9,0x5a,0x82,0x38,0xf8,0x3e,0x3f,0xec,0xd5,0x27,0xde,\r
-0x45,0xea,0x28,0xa2,0xbd,0xb3,0xef,0xcf,0xcd,0xfd,0x0b,0x4e,0x93,0xc4,0x1e,0x25,\r
-0x8e,0xce,0x20,0x5a,0x4b,0x8b,0x92,0xbf,0x9b,0x1a,0xfd,0x0a,0xf0,0xbe,0x8b,0x17,\r
-0x87,0xb4,0x1b,0x1d,0x3a,0x15,0xc2,0x41,0x12,0xa7,0xe3,0x8e,0x6b,0xe1,0x7f,0x80,\r
-0x9a,0xce,0x9f,0xa2,0x7c,0x4f,0x67,0xd6,0x07,0x96,0x6c,0xae,0x65,0x88,0xa3,0x8e,\r
-0x56,0x40,0xe4,0x73,0x9f,0xa5,0x7d,0xb5,0x6f,0xf1,0x0b,0x40,0xb8,0x50,0x57,0x51,\r
-0x8b,0xf1,0x35,0xf2,0x19,0x34,0x29,0xd1,0x9d,0x59,0xce,0x49,0x4a,0xf6,0xf9,0x1f,\r
-0x11,0xc3,0x2a,0x9a,0xc3,0xca,0xa4,0x9f,0xbc,0xdd,0xbe,0xe3,0xa4,0xa2,0xb1,0xe3,\r
-0xf1,0x6e,0x91,0x2f,0xdd,0xbf,0x84,0xff,0x00,0xc0,0xaa,0xd2,0x6b,0x76,0x12,0x7d,\r
-0xdb,0xc8,0x4f,0xfc,0x0c,0x57,0xd5,0xaa,0x90,0x7b,0x34,0x7d,0xaa,0x94,0x5f,0x52,\r
-0xf5,0x23,0x67,0x1c,0x75,0xf7,0xa8,0x12,0xf6,0xde,0x5f,0xb9,0x3c,0x6d,0xf4,0x61,\r
-0x52,0x89,0x50,0xf4,0x70,0x7f,0x1a,0xbb,0xa6,0x3b,0x8e,0x19,0xc0,0xc8,0xe6,0x8a,\r
-0x40,0xd9,0x1d,0x69,0x73,0x4c,0x62,0xd1,0x49,0x45,0x00,0x2d,0x14,0x51,0x40,0x05,\r
-0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x09,0x8a,0x5a,0x28,0xa0,\r
-0x02,0x8a,0x28,0xa0,0x02,0x92,0x96,0x8a,0x00,0x4c,0x0f,0x4a,0x31,0x4b,0x45,0x00,\r
-0x25,0x2d,0x14,0x50,0x01,0x45,0x14,0x50,0x03,0x1e,0x24,0x91,0x4a,0xba,0x2b,0x29,\r
-0xea,0x08,0xc8,0xac,0x4d,0x5b,0xc0,0x5e,0x19,0xd7,0xa2,0x31,0xea,0x7e,0x1d,0xd2,\r
-0x75,0x18,0xcf,0x54,0xba,0xb1,0x8a,0x50,0x7f,0x06,0x53,0x5b,0xd4,0x50,0x07,0x98,\r
-0xdf,0x7e,0xcb,0xdf,0x07,0x35,0x26,0x66,0xba,0xf8,0x51,0xe0,0xa9,0xd9,0xba,0xb3,\r
-0xf8,0x7e,0xd0,0x93,0xf8,0xf9,0x75,0x85,0xa9,0xfe,0xc5,0x1f,0x01,0xb5,0x58,0xca,\r
-0x4d,0xf0,0x8f,0xc2,0x31,0x8f,0x5b,0x6d,0x2a,0x28,0x0f,0xe7,0x18,0x53,0x5e,0xd7,\r
-0x45,0x00,0x7c,0xcb,0xa9,0x7f,0xc1,0x35,0xff,0x00,0x67,0x0d,0x53,0x3e,0x67,0xc3,\r
-0x4b,0x58,0x49,0xef,0x6d,0xa8,0x5d,0xc3,0xff,0x00,0xa0,0xca,0x2b,0x9e,0xbe,0xff,\r
-0x00,0x82,0x54,0x7e,0xce,0x37,0x6b,0x88,0xbc,0x21,0x7f,0x64,0x7f,0xbd,0x06,0xb7,\r
-0x78,0x4f,0xfe,0x3f,0x23,0x57,0xd7,0x74,0x50,0x16,0x3e,0x1b,0xd6,0x3f,0xe0,0x8f,\r
-0x5f,0x02,0xb5,0x01,0xfe,0x89,0x71,0xe2,0x9d,0x2c,0xff,0x00,0xd3,0xbe,0xa4,0x8f,\r
-0xff,0x00,0xa3,0x23,0x6a,0xe5,0xae,0xbf,0xe0,0x8a,0xff,0x00,0x0b,0x1c,0x9f,0xb3,\r
-0xf8,0xe3,0xc6,0x10,0xe7,0xa7,0x98,0xd6,0xaf,0x8f,0xca,0x11,0x5f,0xa1,0xb4,0x50,\r
-0x2b,0x23,0xf3,0x37,0x55,0xff,0x00,0x82,0x25,0x78,0x72,0x40,0xdf,0xd9,0x9f,0x14,\r
-0x35,0x4b,0x73,0xdb,0xed,0x7a,0x5c,0x72,0xe3,0xfe,0xf9,0x75,0xae,0x4e,0xef,0xfe,\r
-0x08,0x8b,0xab,0xab,0x1f,0xb2,0xfc,0x59,0xb1,0x91,0x7b,0x09,0xb4,0x37,0x53,0xf8,\r
-0xe2,0x73,0x5f,0xab,0xd4,0x50,0x16,0x47,0xe4,0x0e,0xa5,0xff,0x00,0x04,0x51,0xf8,\r
-0x81,0x10,0x3f,0x60,0xf8,0x85,0xe1,0xbb,0xa3,0xdb,0xcf,0xb7,0x9e,0x1c,0xfe,0x41,\r
-0xab,0x8f,0xd4,0xff,0x00,0xe0,0x8e,0x7f,0x1c,0x2d,0x1b,0x16,0xba,0x97,0x84,0xaf,\r
-0xc7,0xaa,0xea,0x12,0xa7,0xe8,0xd0,0xd7,0xed,0x6d,0x18,0xa7,0x70,0xb2,0x3f,0x0c,\r
-0x35,0x0f,0xf8,0x24,0xc7,0xed,0x0d,0x65,0x9f,0x2b,0x45,0xd1,0x6f,0xb1,0xff,0x00,\r
-0x3e,0xfa,0xc4,0x43,0x3f,0xf7,0xde,0xda,0xe5,0x35,0x6f,0xf8,0x26,0x9f,0xed,0x1d,\r
-0xa4,0xb1,0x07,0xe1,0xcc,0xd7,0x60,0x75,0x6b,0x5d,0x42,0xd2,0x41,0xff,0x00,0xa3,\r
-0x6b,0xf7,0xeb,0x14,0x62,0x8b,0x85,0x91,0xfc,0xf0,0x5e,0xfe,0xc2,0x3f,0xb4,0x05,\r
-0x81,0x22,0x5f,0x85,0x1e,0x22,0x6c,0x7f,0xcf,0x1b,0x71,0x2f,0xfe,0x80,0x4d,0x72,\r
-0xfa,0xa7,0xec,0xb7,0xf1,0x8b,0x46,0x62,0xb7,0x9f,0x0b,0x7c,0x5f,0x16,0x3a,0x91,\r
-0xa2,0x5c,0x38,0x1f,0x8a,0xa1,0x15,0xfd,0x23,0xd1,0x8a,0x2e,0x2b,0x1f,0xcc,0x7d,\r
-0xff,0x00,0xc2,0xef,0x19,0xe9,0x4c,0x56,0xf7,0xc2,0x5a,0xed,0x99,0x1d,0x44,0xfa,\r
-0x6c,0xc9,0x8f,0xcd,0x6b,0x02,0xe7,0x4e,0xbb,0xb3,0x62,0xb3,0xda,0xcd,0x03,0x0e,\r
-0xa2,0x48,0xca,0x91,0xf9,0x8a,0xfe,0xa3,0xf0,0x2a,0xbd,0xc6,0x99,0x67,0x76,0x8c,\r
-0x93,0xda,0xc1,0x32,0xb7,0x05,0x64,0x8c,0x30,0x3f,0x98,0xa2,0xe1,0xca,0x7f,0x2e,\r
-0x18,0xa2,0xbf,0xa6,0x6d,0x43,0xe0,0xc7,0xc3,0xed,0x58,0xb1,0xbe,0xf0,0x2f,0x86,\r
-0xaf,0x0b,0x72,0xc6,0x7d,0x22,0xdd,0xc9,0xfa,0xe5,0x2b,0x9e,0xbd,0xfd,0x95,0xbe,\r
-0x0c,0xea,0x0a,0xcb,0x3f,0xc2,0x8f,0x06,0x3e,0xee,0xa4,0x68,0x36,0xca,0x7f,0x30,\r
-0x80,0xd1,0x71,0x72,0x9f,0xcd,0xd5,0x18,0x3d,0x6b,0xfa,0x1a,0xd5,0x7f,0x60,0x8f,\r
-0xd9,0xf7,0x58,0x56,0x13,0xfc,0x29,0xd0,0x23,0xdd,0xd4,0xda,0xc4,0xd0,0x1f,0xcd,\r
-0x18,0x57,0x23,0x77,0xff,0x00,0x04,0xbb,0xfd,0x9b,0x2e,0xd9,0x9b,0xfe,0x15,0xfc,\r
-0x90,0x33,0x73,0x98,0x75,0xbb,0xf1,0xfa,0x79,0xf8,0x1f,0x95,0x3b,0x87,0x29,0xf8,\r
-0x27,0x45,0x7e,0xe5,0xeb,0x3f,0xf0,0x49,0x4f,0xd9,0xef,0x53,0x8c,0xad,0xae,0x91,\r
-0xad,0xe9,0x07,0xb3,0x5a,0x6b,0x12,0xb9,0x1f,0xf7,0xf7,0x7d,0x71,0xd7,0xbf,0xf0,\r
-0x46,0x0f,0x83,0x73,0xb9,0x6b,0x7f,0x14,0xf8,0xd6,0xdb,0x3f,0xc3,0xf6,0xcb,0x47,\r
-0x03,0xf3,0xb6,0xcf,0xeb,0x45,0xc3,0x94,0xfc,0x65,0xa2,0xbf,0x5f,0xb5,0x5f,0xf8,\r
-0x22,0x97,0xc3,0xc9,0x50,0x0d,0x37,0xe2,0x0f,0x89,0xed,0x5f,0xd6,0xea,0x1b,0x79,\r
-0xc7,0xe4,0xa8,0x95,0xc8,0xea,0x7f,0xf0,0x44,0x58,0x49,0x3f,0xd9,0xdf,0x16,0x9d,\r
-0x7d,0x05,0xd6,0x85,0x9f,0xd5,0x67,0x14,0x5c,0x56,0x67,0xe5,0x7d,0x48,0x97,0x33,\r
-0x45,0xf7,0x25,0x74,0xff,0x00,0x75,0x88,0xaf,0xd2,0x8b,0xef,0xf8,0x22,0x57,0x8a,\r
-0x63,0xcf,0xd8,0xfe,0x28,0xe9,0x13,0xfa,0x79,0xfa,0x54,0xb1,0x67,0xf2,0x91,0xab,\r
-0x95,0xd4,0xff,0x00,0xe0,0x8c,0x1f,0x16,0xad,0xc9,0xfb,0x0f,0x8b,0x3c,0x27,0x7a,\r
-0x07,0x4f,0x32,0x6b,0x88,0x89,0xff,0x00,0xc8,0x46,0x80,0xb3,0x3e,0x19,0xd3,0xfc,\r
-0x77,0xe2,0x5d,0x25,0x95,0xac,0x7c,0x43,0xaa,0xd9,0x95,0xe4,0x1b,0x7b,0xd9,0x13,\r
-0x1f,0x93,0x57,0x63,0xa7,0x7e,0xd3,0xbf,0x17,0xf4,0x95,0x55,0xb3,0xf8,0xa1,0xe2,\r
-0xfb,0x74,0x5e,0x8a,0x9a,0xdd,0xc8,0x03,0xf0,0xdf,0x5f,0x47,0x5e,0x7f,0xc1,0x20,\r
-0x7e,0x3e,0x5b,0x13,0xe5,0x8f,0x0b,0xdd,0x81,0xd3,0xc9,0xd5,0x58,0x67,0xfe,0xfa,\r
-0x8c,0x57,0x35,0xa9,0xff,0x00,0xc1,0x2b,0xff,0x00,0x68,0xcd,0x3c,0x31,0x8f,0xc2,\r
-0x16,0x77,0xd8,0xff,0x00,0x9f,0x5d,0x5e,0xd8,0xe7,0xe9,0xb9,0xd6,0x80,0xd4,0xf3,\r
-0x8b,0x4f,0xdb,0x7b,0xe3,0xdd,0x96,0x3c,0xaf,0x8b,0x3e,0x29,0x38,0xe9,0xe6,0xdf,\r
-0xb4,0x9f,0xfa,0x16,0x6b,0xa5,0xd3,0x7f,0xe0,0xa3,0xbf,0xb4,0x5e,0x99,0x81,0x1f,\r
-0xc4,0xbb,0xd9,0x80,0xed,0x73,0x69,0x6d,0x2e,0x7f,0xef,0xa8,0xcd,0x56,0xbf,0xff,\r
-0x00,0x82,0x78,0x7e,0xd1,0x3a,0x71,0x3e,0x67,0xc2,0xed,0x52,0x4c,0x7f,0xcf,0x09,\r
-0xed,0xe5,0xff,0x00,0xd0,0x64,0x35,0xcd,0x6a,0x5f,0xb1,0x97,0xc7,0x4d,0x28,0x91,\r
-0x71,0xf0,0x9f,0xc5,0x9c,0x75,0x30,0xe9,0x92,0x4a,0x3f,0x34,0x06,0x80,0xd4,0xf5,\r
-0x8b,0x2f,0xf8,0x2a,0xd7,0xed,0x17,0x68,0xa0,0x3f,0x8a,0x34,0xdb,0xac,0x77,0x9f,\r
-0x46,0xb7,0xe7,0xfe,0xf9,0x51,0x5b,0xf6,0x1f,0xf0,0x57,0xff,0x00,0x8f,0x56,0xa4,\r
-0x79,0xeb,0xe1,0x8b,0xc0,0x3a,0xf9,0xba,0x5b,0x29,0x3f,0xf7,0xcc,0x82,0xbe,0x5b,\r
-0xd4,0xfe,0x04,0xfc,0x49,0xd1,0x5c,0xa5,0xf7,0xc3,0xff,0x00,0x14,0x5a,0x30,0xea,\r
-0x25,0xd1,0xee,0x17,0xff,0x00,0x64,0xae,0x7e,0xf3,0xc1,0x5e,0x21,0xd3,0xce,0x2e,\r
-0xb4,0x1d,0x4e,0xd8,0xff,0x00,0xd3,0x6b,0x39,0x13,0xf9,0xad,0x03,0xd4,0xfb,0xcb,\r
-0x4d,0xff,0x00,0x82,0xd2,0xfc,0x51,0xb7,0x50,0x2f,0x7c,0x15,0xe1,0x5b,0xcf,0x52,\r
-0x82,0xe2,0x23,0xff,0x00,0xa3,0x0d,0x74,0x56,0x5f,0xf0,0x5b,0x5f,0x14,0x2e,0x05,\r
-0xdf,0xc3,0x0d,0x22,0x5f,0x53,0x06,0xa7,0x2a,0x7f,0x34,0x35,0xf9,0xab,0x34,0x12,\r
-0xdb,0xb6,0xd9,0x63,0x78,0x9b,0xd1,0xd4,0x83,0x4c,0xa3,0x40,0xbb,0x3f,0x54,0x74,\r
-0xbf,0xf8,0x2d,0xcd,0xbe,0x40,0xd4,0x7e,0x14,0x4a,0x07,0x73,0x6b,0xad,0x03,0xfa,\r
-0x34,0x35,0xd4,0x58,0xff,0x00,0xc1,0x6b,0xfc,0x07,0x20,0x1f,0x6c,0xf8,0x77,0xe2,\r
-0x38,0x0f,0xfd,0x30,0xb9,0xb7,0x93,0xf9,0x95,0xaf,0xc8,0x6c,0x51,0x45,0x85,0xcc,\r
-0xcf,0xd9,0x9d,0x3b,0xfe,0x0b,0x39,0xf0,0x82,0xe4,0x81,0x77,0xe1,0x8f,0x17,0xd9,\r
-0x67,0xf8,0xbe,0xcd,0x6f,0x20,0x1f,0x94,0xd5,0xd7,0x69,0xdf,0xf0,0x56,0xff,0x00,\r
-0xd9,0xf6,0xf2,0x20,0xd7,0x1a,0x96,0xbd,0xa7,0xb1,0xfe,0x19,0xf4,0x99,0x18,0x8f,\r
-0xfb,0xe0,0xb0,0xaf,0xc3,0x8a,0xb5,0xa4,0xd8,0xbe,0xa7,0xaa,0xd9,0xd9,0xc4,0xbb,\r
-0xa5,0xb8,0x99,0x21,0x50,0x3b,0x96,0x60,0x07,0xf3,0xa2,0xc3,0xb9,0xfd,0x3f,0xe8,\r
-0x3a,0xd5,0xb7,0x88,0xf4,0x4d,0x3f,0x56,0xb3,0x2e,0x6c,0xef,0xed,0xe3,0xba,0x84,\r
-0xc8,0xa5,0x58,0xa3,0xa8,0x65,0xca,0x9e,0x41,0xc1,0x1c,0x1a,0xbf,0x55,0x34,0xab,\r
-0x18,0xf4,0xcd,0x32,0xd2,0xce,0x14,0x11,0xc5,0x6f,0x0a,0x44,0x88,0x3a,0x28,0x55,\r
-0x00,0x0f,0xd2,0xad,0xd4,0x96,0x14,0x51,0x45,0x00,0x72,0x3f,0x14,0xe7,0xfb,0x3f,\r
-0x83,0x6f,0x4f,0xa8,0xc5,0x7c,0x0d,0xe2,0x29,0x37,0xdf,0xdd,0x37,0xab,0x9a,0xfb,\r
-0x9b,0xe3,0x65,0xcf,0x91,0xe0,0xc9,0x87,0xf7,0x8e,0x3f,0x4a,0xf8,0x43,0x5a,0x7d,\r
-0xd3,0x4e,0xde,0xac,0x6b,0xe0,0x33,0xe7,0x7c,0x54,0x23,0xd9,0x1f,0x01,0xc4,0xf3,\r
-0xb2,0x48,0xf1,0x4f,0x1a,0x42,0x35,0x2f,0x88,0x9e,0x12,0xb1,0x64,0xf3,0x16,0xe7,\r
-0x5a,0xb2,0x84,0xa6,0x33,0xb8,0x34,0xe8,0x08,0xfc,0x8d,0x7e,0xcc,0xa0,0x0a,0xa1,\r
-0x40,0xc0,0x1c,0x57,0xe3,0xef,0x87,0xac,0x9f,0x5c,0xfd,0xa4,0xfe,0x19,0x59,0x2f,\r
-0x3b,0xbc,0x47,0x67,0x26,0x3d,0x92,0x40,0xe7,0xff,0x00,0x40,0xaf,0xd8,0x31,0x5f,\r
-0x57,0x97,0x46,0xd4,0x11,0xd7,0xc2,0x71,0xe5,0xcb,0xef,0xdd,0xb1,0x68,0xa2,0x8a,\r
-0xf5,0x0f,0xb4,0x3f,0x3c,0xbf,0x6b,0x4f,0x07,0xde,0xfc,0x28,0xf8,0xc1,0x3e,0xbf,\r
-0x6f,0x19,0x5d,0x0b,0xc4,0x4d,0xf6,0x95,0x78,0xc6,0x04,0x73,0x80,0x04,0xaa,0x7d,\r
-0xc9,0xf9,0xff,0x00,0xe0,0x47,0xd2,0xb9,0x0d,0x2b,0xc6,0x12,0x5d,0xc4,0xaf,0x15,\r
-0xeb,0xe0,0x8e,0xcf,0x5f,0xa1,0xbf,0x13,0xfe,0x1a,0x68,0xdf,0x15,0xfc,0x21,0x77,\r
-0xe1,0xfd,0x6e,0x0f,0x36,0xda,0x61,0xba,0x39,0x57,0x1b,0xe0,0x90,0x0f,0x96,0x44,\r
-0x3d,0x88,0xcf,0xe3,0xc8,0x3c,0x1a,0xfc,0xed,0xf8,0x9f,0xfb,0x2e,0xf8,0xe3,0xe1,\r
-0x16,0xa9,0x33,0xdb,0xac,0x97,0xda,0x46,0xec,0xc3,0x7f,0x6e,0xa4,0xc6,0xc3,0x3c,\r
-0x06,0x1f,0xc2,0x7d,0x8f,0xe1,0x9a,0xf9,0x3c,0xcb,0x2d,0x84,0xe4,0xea,0x6c,0x7e,\r
-0x4f,0x9d,0xe5,0x78,0x9c,0x16,0x22,0x58,0xac,0x22,0x6e,0x13,0x77,0x69,0x74,0x66,\r
-0xfc,0x3e,0x28,0xd4,0x23,0xe6,0x3b,0xf9,0x47,0xfc,0x0e,0xaf,0x43,0xe3,0x9d,0x6e,\r
-0x1f,0xbb,0xa9,0x4b,0xf8,0xb5,0x78,0xb9,0xb9,0xf1,0x3e,0x9f,0xf2,0x4d,0x68,0x5c,\r
-0x8e,0xf8,0xe4,0xd2,0x8f,0x15,0xeb,0x11,0x7d,0xfb,0x09,0x3f,0x23,0x5f,0x35,0xf5,\r
-0x19,0xaf,0x86,0x4b,0xef,0x3c,0x48,0xe2,0x71,0xd1,0x5f,0x0c,0xbe,0xf3,0xdd,0x21,\r
-0xf8,0x9f,0xe2,0x38,0x0f,0xcb,0xa8,0xb9,0xad,0x1b,0x7f,0x8c,0xfe,0x26,0xb7,0xe9,\r
-0x7a,0xcd,0xf5,0xaf,0x9f,0x57,0xc7,0x97,0x91,0xfd,0xfb,0x49,0x57,0xf0,0x35,0x22,\r
-0x7c,0x46,0x2b,0xf7,0xe2,0x90,0x1f,0x71,0x4d,0x61,0x71,0x31,0xf8,0x64,0xfe,0xf3,\r
-0x55,0x99,0x63,0x61,0xba,0x91,0xf4,0x94,0x1f,0xb4,0x1f,0x8a,0x21,0xc7,0xef,0xf3,\r
-0xf8,0xd6,0xa5,0xbf,0xed,0x33,0xe2,0x38,0xb1,0xbc,0x96,0xc7,0xbd,0x7c,0xc2,0x9f,\r
-0x12,0x60,0xfe,0x2d,0xc3,0xf0,0xab,0x31,0xfc,0x44,0xb4,0x60,0x32,0xff,0x00,0xa5,\r
-0x5a,0x58,0xf8,0xed,0x37,0xf7,0x9b,0x47,0x3c,0xc5,0x43,0x79,0x4b,0xee,0x3e,0xa8,\r
-0xb5,0xfd,0xaa,0x75,0x98,0x88,0xf3,0x22,0xdc,0x3f,0x3a,0xd5,0xb7,0xfd,0xac,0xae,\r
-0x86,0x3c,0xcb,0x6c,0xfa,0xfc,0xa2,0xbe,0x4c,0x8f,0xc7,0x96,0x4d,0xff,0x00,0x2d,\r
-0x16,0xac,0xa7,0x8c,0xac,0x9f,0x1f,0xbd,0x43,0xf8,0xd5,0xac,0x46,0x63,0x0f,0xb4,\r
-0xcd,0xe3,0xc4,0x98,0x88,0xef,0x3f,0xc0,0xfa,0xfe,0xd7,0xf6,0xb2,0x84,0xe3,0xce,\r
-0xb6,0xff,0x00,0xc7,0x6b,0x52,0xdb,0xf6,0xab,0xd2,0xe4,0x23,0xcc,0x80,0x0f,0xc0,\r
-0xd7,0xc6,0x69,0xe2,0x8b,0x37,0xe9,0x2a,0xfe,0x06,0xa7,0x4d,0x7a,0xd5,0xfa,0x38,\r
-0x3f,0x8d,0x52,0xcc,0x73,0x18,0x6e,0xff,0x00,0x03,0xaa,0x3c,0x51,0x5b,0xf9,0x91,\r
-0xf6,0xdd,0xbf,0xed,0x3b,0xe1,0xe9,0x00,0xde,0x30,0x4f,0xfb,0x55,0xa9,0x6d,0xfb,\r
-0x43,0xf8,0x66,0x7c,0x66,0x5d,0xbf,0xf0,0x21,0x5f,0x0a,0xae,0xad,0x6e,0xdd,0x1c,\r
-0x54,0x83,0x50,0x84,0xf4,0x93,0xf5,0xad,0x16,0x73,0x8f,0x8e,0xf6,0xfb,0x8e,0xb8,\r
-0x71,0x45,0x4e,0xb6,0x3e,0xf8,0xb7,0xf8,0xdf,0xe1,0x99,0xc8,0xc5,0xd0,0x1f,0x88,\r
-0xad,0x28,0x3e,0x2a,0xf8,0x72,0x71,0x91,0x7e,0xa3,0xf2,0xaf,0xcf,0xa5,0xbf,0x51,\r
-0xf7,0x66,0x23,0xe8,0x6a,0x64,0xd4,0xe4,0x5f,0xbb,0x70,0xc3,0xfe,0x05,0x5a,0xac,\r
-0xfb,0x14,0xbe,0x28,0x2f,0xc4,0xeb,0x8f,0x13,0xcb,0xac,0x51,0xfa,0x19,0x17,0x8f,\r
-0xb4,0x29,0xbe,0xee,0xa1,0x1f,0xe7,0x57,0x23,0xf1,0x4e,0x95,0x2f,0xdd,0xbe,0x84,\r
-0xff,0x00,0xc0,0xab,0xf3,0xbe,0x3d,0x6e,0xf1,0x3e,0xe5,0xe4,0xa3,0xe8,0xf5,0x66,\r
-0x3f,0x15,0xea,0xb1,0x11,0xb7,0x50,0x9b,0xfe,0xfb,0x35,0xb2,0xe2,0x1a,0x8b,0xe2,\r
-0xa7,0xf8,0x9d,0x51,0xe2,0x58,0x3d,0xe0,0x7e,0x88,0xa6,0xb1,0x63,0x27,0xdd,0xbb,\r
-0x88,0xff,0x00,0xc0,0xc5,0x4a,0xb7,0x90,0x3f,0xdd,0x99,0x0f,0xd1,0x85,0x7e,0x7b,\r
-0x43,0xe3,0xfd,0x7a,0x2f,0xbb,0xa8,0xcb,0xf9,0xd5,0xf8,0x3e,0x2b,0x78,0x8e,0x0c,\r
-0x62,0xf9,0xcf,0xd4,0xd6,0xeb,0x88,0xa3,0xf6,0xa9,0xbf,0xbc,0xe8,0x8f,0x11,0xd0,\r
-0x7b,0xc5,0x9f,0x7f,0x09,0x14,0xff,0x00,0x10,0xfc,0xe9,0x73,0xef,0x5f,0x08,0xc1,\r
-0xf1,0xbf,0xc4,0xd0,0x7f,0xcb,0xd1,0x6f,0xc4,0xd6,0x9d,0xb7,0xed,0x11,0xe2,0x58,\r
-0x3a,0xcb,0x9f,0xf8,0x11,0xad,0xe3,0xc4,0x34,0x1e,0xf0,0x67,0x44,0x78,0x83,0x0a,\r
-0xf7,0xb9,0xf6,0xe0,0x34,0x66,0xbe,0x37,0xb6,0xfd,0xa7,0x35,0xf8,0x71,0xbf,0x2d,\r
-0xf8,0xd6,0xad,0xbf,0xed,0x57,0xaa,0x2f,0xfa,0xc8,0x49,0x1f,0x85,0x6d,0x1c,0xfb,\r
-0x08,0xf7,0xbf,0xdc,0x6f,0x1c,0xf3,0x06,0xfe,0xd1,0xf5,0x9e,0x68,0x07,0x35,0xf3,\r
-0x0d,0xbf,0xed,0x65,0x28,0xff,0x00,0x59,0x6f,0x9f,0xf8,0x0e,0x6b,0x52,0xdb,0xf6,\r
-0xb1,0xb5,0x38,0xf3,0x6d,0xc0,0xfc,0x2b,0xa2,0x39,0xd6,0x09,0xfd,0xaf,0xc0,0xe9,\r
-0x8e,0x6d,0x83,0x97,0xdb,0x3e,0x8b,0xa2,0xbc,0x26,0x0f,0xda,0xa3,0x47,0x7c,0x07,\r
-0x88,0x03,0xdf,0xad,0x6a,0x5b,0x7e,0xd2,0xde,0x1e,0x98,0x0d,0xe4,0x2f,0xfc,0x0a,\r
-0xb7,0x8e,0x6b,0x83,0x97,0xfc,0xbc,0x46,0xf1,0xc7,0xe1,0xa5,0xb4,0xd1,0xec,0x54,\r
-0x57,0x98,0xdb,0xfe,0xd0,0x3e,0x19,0x9f,0xfe,0x5b,0x05,0xff,0x00,0x81,0x56,0x9c,\r
-0x1f,0x19,0xfc,0x35,0x36,0x3f,0xd3,0x00,0xfc,0x45,0x74,0x47,0x1d,0x86,0x96,0xd5,\r
-0x17,0xde,0x6e,0xb1,0x34,0x65,0xb4,0xd1,0xdd,0xd1,0x5c,0xa4,0x1f,0x13,0xfc,0x3d,\r
-0x38,0x18,0xbe,0x41,0xf5,0x35,0x76,0x2f,0x1c,0xe8,0x93,0x7d,0xdb,0xf8,0x8f,0xe3,\r
-0x5b,0x2c,0x45,0x29,0x6d,0x25,0xf7,0x9a,0x2a,0xb4,0xde,0xd2,0x46,0xf5,0x15,0x97,\r
-0x1f,0x89,0x74,0xc9,0x47,0xcb,0x7d,0x09,0xff,0x00,0x81,0x55,0x94,0xd5,0xac,0xe4,\r
-0xfb,0xb7,0x51,0x1f,0xf8,0x10,0xad,0x54,0xe2,0xf6,0x65,0xa9,0x27,0xb3,0x2d,0xd1,\r
-0x51,0x0b,0xa8,0x5b,0xa4,0xa8,0x7f,0xe0,0x42,0x9e,0x1d,0x58,0x64,0x10,0x7e,0x86,\r
-0xaa,0xe8,0xab,0x8e,0xa2,0x93,0x34,0x66,0x98,0x0b,0x45,0x26,0x45,0x19,0xa0,0x05,\r
-0xa2,0x93,0x34,0xb4,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,\r
-0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,\r
-0x00,0x51,0x45,0x14,0x00,0x94,0x6d,0x06,0x96,0x8a,0x00,0x4c,0x51,0x8a,0x5a,0x28,\r
-0x01,0x31,0x4d,0x31,0xa1,0x04,0x15,0x04,0x1e,0xb9,0x14,0xfa,0x28,0x03,0x1e,0xfb,\r
-0xc1,0xba,0x06,0xa9,0x9f,0xb6,0x68,0x7a,0x6d,0xde,0x7a,0xf9,0xf6,0x91,0xbe,0x7f,\r
-0x31,0x5c,0xe5,0xf7,0xc0,0x6f,0x86,0x7a,0x9e,0xef,0xb5,0xfc,0x3c,0xf0,0xad,0xc9,\r
-0x6e,0xa6,0x5d,0x16,0xd9,0x89,0xfc,0x4a,0x57,0x77,0x45,0x00,0x78,0xd6,0xa9,0xfb,\r
-0x1a,0x7c,0x0b,0xd6,0x15,0xc5,0xcf,0xc2,0x6f,0x09,0x12,0xfd,0x5a,0x2d,0x2a,0x28,\r
-0x9b,0xfe,0xfa,0x40,0x08,0xae,0x2e,0xfb,0xfe,0x09,0xb1,0xfb,0x37,0x5f,0xbb,0xb4,\r
-0x9f,0x0c,0xad,0x23,0x2d,0xd7,0xc8,0xd4,0x6f,0x22,0x03,0xe8,0x16,0x60,0x05,0x7d,\r
-0x33,0x45,0x00,0x7c,0x97,0x7f,0xff,0x00,0x04,0xb0,0xfd,0x9b,0xaf,0x22,0x65,0x8f,\r
-0xc1,0x17,0x56,0x6c,0x7f,0x8e,0x0d,0x6e,0xf4,0x91,0xff,0x00,0x7d,0x4a,0xc3,0xf4,\r
-0xac,0x5d,0x0f,0xfe,0x09,0x3f,0xf0,0x43,0xc3,0x5e,0x2b,0xd2,0x3c,0x41,0xa7,0x37,\r
-0x89,0x21,0xba,0xd2,0xef,0x61,0xbe,0x86,0x17,0xd4,0x52,0x48,0x59,0xe3,0x70,0xe1,\r
-0x58,0x34,0x44,0x95,0x25,0x40,0x23,0x3d,0x3b,0xd7,0xd9,0xd4,0x50,0x2b,0x05,0x14,\r
-0x51,0x40,0xc2,0x8a,0x28,0xa0,0x0f,0x29,0xfd,0xa1,0x2e,0x7c,0x9f,0x0a,0x05,0xce,\r
-0x32,0x58,0xfe,0x95,0xf0,0xf6,0xaa,0xfc,0x48,0x7d,0xcd,0x7d,0x97,0xfb,0x4b,0xdc,\r
-0xf9,0x7a,0x24,0x29,0x9f,0xe1,0x3c,0x57,0xc5,0xda,0xb3,0xe2,0x27,0x3f,0x5a,0xfc,\r
-0xeb,0x38,0x7c,0xd8,0xfb,0x76,0x48,0xfc,0xd3,0x8a,0x27,0xef,0xdb,0xc8,0xe4,0x3e,\r
-0x04,0xda,0x0d,0x63,0xf6,0xc8,0xf8,0x6d,0x01,0xc9,0xf2,0xaf,0xe6,0xb9,0xe3,0xfe,\r
-0x99,0xdb,0xca,0xc3,0xf9,0x57,0xeb,0x58,0xaf,0xcb,0x1f,0xd8,0xe7,0x4f,0x6d,0x5f,\r
-0xf6,0xce,0xd0,0xa5,0x03,0x29,0x61,0xa7,0xdf,0x5d,0x37,0xb0,0xf2,0xbc,0xb1,0xfa,\r
-0xc8,0x2b,0xf5,0x38,0x77,0xaf,0xb7,0xc1,0xab,0x51,0x47,0xd1,0xf0,0xd4,0x39,0x32,\r
-0xca,0x7e,0x62,0xd1,0x45,0x15,0xdc,0x7d,0x40,0x98,0xa6,0xc9,0x0a,0x4a,0xa5,0x5d,\r
-0x43,0xa1,0xe0,0xab,0x0c,0x83,0x4f,0xa2,0x80,0x38,0xad,0x6b,0xe0,0xcf,0x83,0x35,\r
-0xf9,0x1a,0x4b,0xbd,0x02,0xd7,0xcc,0x61,0x82,0xd0,0x83,0x17,0xe8,0xa4,0x0a,0xe5,\r
-0xaf,0x7f,0x65,0x8f,0x01,0x5d,0x9c,0xad,0x95,0xc5,0xbf,0xb4,0x53,0x7f,0xf1,0x40,\r
-0xd7,0xaf,0x51,0x5c,0xd2,0xc3,0x51,0x96,0xf0,0x47,0x24,0xb0,0x98,0x79,0xbb,0xca,\r
-0x9a,0xfb,0x8f,0x09,0xba,0xfd,0x8f,0x3c,0x13,0x36,0x4a,0x4d,0xa8,0x46,0x7d,0xdd,\r
-0x08,0xff,0x00,0xd0,0x2b,0x02,0xff,0x00,0xf6,0x26,0xd0,0x27,0xcf,0xd9,0xf5,0x69,\r
-0x22,0x3f,0xf4,0xd2,0xdc,0x3f,0xf2,0x61,0x5f,0x4a,0x51,0xf8,0xd6,0x4f,0x03,0x87,\r
-0x7f,0x60,0xe7,0x79,0x6e,0x16,0x5f,0x63,0xf3,0x3e,0x50,0xbc,0xfd,0x84,0xec,0x64,\r
-0xe6,0x2d,0x6a,0x17,0x3f,0xed,0xda,0x95,0xff,0x00,0xd9,0x8d,0x73,0xd7,0xdf,0xb0,\r
-0x65,0xd9,0x62,0x20,0xbb,0xd3,0x5c,0x76,0x2c,0x59,0x4f,0xfe,0x81,0x5f,0x68,0x62,\r
-0x8c,0x56,0x4f,0x2e,0xa0,0xfa,0x3f,0xbd,0x98,0xbc,0xa7,0x0a,0xfe,0xcb,0xfb,0xd9,\r
-0xf0,0x8d,0xe7,0xec,0x1d,0xae,0x2a,0xb1,0x8d,0x6c,0x65,0x3d,0x82,0x4d,0x8c,0xfe,\r
-0x78,0xae,0x7a,0xfb,0xf6,0x20,0xf1,0x54,0x07,0xe4,0xd3,0x0b,0x0f,0xfa,0x67,0x70,\r
-0x87,0xff,0x00,0x66,0xaf,0xd0,0xfc,0x51,0x8a,0x87,0x96,0xd3,0xe9,0x27,0xf7,0x9c,\r
-0xf2,0xc8,0xf0,0xb2,0xef,0xf8,0x7f,0x91,0xf9,0xa7,0x7b,0xfb,0x1f,0x78,0xc6,0xd4,\r
-0x90,0xba,0x46,0xa0,0x4f,0xfb,0x1f,0x30,0xfd,0x2b,0x0a,0xef,0xf6,0x69,0xf1,0x85,\r
-0x91,0x3b,0xb4,0xed,0x4e,0x3c,0x7a,0xdb,0xb7,0xf8,0x57,0xea,0x4e,0x29,0x0a,0xe6,\r
-0xa1,0xe5,0xab,0xa4,0xdf,0xe0,0x72,0xcb,0x87,0x70,0xd2,0xeb,0xf8,0x23,0xf2,0x7a,\r
-0xef,0xe0,0xd7,0x8a,0x6c,0x72,0x59,0x6e,0xa3,0x03,0xfb,0xf1,0x11,0x59,0xef,0xe0,\r
-0x3f,0x13,0xdb,0x74,0x91,0xce,0x3d,0x54,0xd7,0xeb,0x83,0x44,0xae,0x30,0xc0,0x11,\r
-0xe8,0x45,0x55,0x9f,0x45,0xb0,0xba,0xff,0x00,0x5d,0x65,0x6f,0x30,0xff,0x00,0x6e,\r
-0x25,0x3f,0xd2,0xb2,0x79,0x6c,0xba,0x4f,0xf0,0x38,0xe5,0xc2,0xf8,0x79,0x76,0xfb,\r
-0xbf,0xe0,0x9f,0x92,0x6d,0xa0,0x78,0xaa,0xdf,0xdf,0xeb,0x9a,0x88,0xa7,0x8a,0x2d,\r
-0xfe,0xf4,0x3b,0xbe,0x86,0xbf,0x57,0xee,0x3c,0x03,0xe1,0xbb,0xa0,0x7c,0xdd,0x07,\r
-0x4d,0x7c,0xf7,0x36,0xa9,0xfe,0x15,0x97,0x73,0xf0,0x6f,0xc1,0x77,0x79,0xf3,0x3c,\r
-0x3b,0x67,0xff,0x00,0x00,0x52,0x9f,0xc8,0x8a,0xc9,0xe5,0xb5,0x3b,0xa6,0x72,0x4b,\r
-0x84,0xe9,0x74,0xb7,0xe2,0x8f,0xcb,0x31,0xaa,0xf8,0x8a,0x0f,0xbf,0x68,0xc6,0x94,\r
-0x78,0xab,0x58,0x8b,0xef,0xd8,0xcb,0xc7,0xfb,0x26,0xbf,0x4d,0xae,0x7f,0x67,0x8f,\r
-0x00,0xdd,0x67,0x3a,0x12,0x46,0x4f,0x74,0x99,0xff,0x00,0xf8,0xaa,0xc5,0xbb,0xfd,\r
-0x94,0xfc,0x09,0x75,0x9d,0xb6,0xf7,0x70,0x67,0xfe,0x79,0xca,0xbf,0xd5,0x4d,0x63,\r
-0x2c,0xb2,0xa7,0xf2,0xc5,0x9c,0xb2,0xe1,0x37,0xd3,0xff,0x00,0x4a,0x67,0xe7,0x32,\r
-0xf8,0xee,0xf6,0x3f,0xbf,0x6b,0x28,0xfc,0x0d,0x4c,0x9f,0x11,0x4a,0x9f,0x9e,0x17,\r
-0x1f,0x85,0x7d,0xf7,0x79,0xfb,0x1c,0x78,0x36,0x7f,0xf5,0x37,0x57,0xd1,0x1f,0xf6,\r
-0x8a,0x37,0xfe,0xca,0x2b,0x02,0xf3,0xf6,0x22,0xd1,0x26,0x72,0x62,0xd6,0x9d,0x17,\r
-0xd1,0xed,0x43,0x1f,0xcf,0x78,0xac,0x1e,0x59,0x3e,0xb4,0x97,0xde,0x73,0x4b,0x85,\r
-0xab,0xaf,0x86,0xff,0x00,0x7a,0x3e,0x2b,0x4f,0x89,0x10,0xff,0x00,0x10,0x65,0xfa,\r
-0x8a,0xb1,0x1f,0xc4,0x4b,0x46,0xea,0xf8,0xaf,0xac,0x2f,0x7f,0x61,0x2b,0x49,0x01,\r
-0xf2,0x35,0x88,0x1d,0xbb,0x09,0x2d,0x8a,0xff,0x00,0x53,0x5c,0xf5,0xe7,0xec,0x19,\r
-0xa8,0x1f,0xf5,0x77,0x5a,0x63,0x8f,0xf7,0x98,0x7f,0xec,0xb5,0x83,0xcb,0x5f,0x5a,\r
-0x4c,0xe7,0x97,0x0e,0xe2,0xe3,0xb3,0x97,0xe0,0xcf,0x9e,0xa3,0xf1,0xed,0x9b,0xff,\r
-0x00,0xcb,0x45,0x15,0x66,0x3f,0x19,0xd9,0x3f,0xfc,0xb5,0x4f,0xce,0xbd,0x7a,0xfb,\r
-0xf6,0x11,0xd7,0xe3,0x62,0x23,0x86,0xce,0x61,0xeb,0x1c,0xc0,0x67,0xf3,0xc5,0x73,\r
-0xf7,0x9f,0xb1,0x27,0x8b,0x21,0xdd,0xb3,0x4a,0x76,0x03,0xfe,0x79,0xdc,0x21,0xff,\r
-0x00,0xd9,0xab,0x09,0x65,0xb1,0x5b,0xd3,0x92,0xf9,0x1c,0xd2,0xc9,0x31,0xd1,0xea,\r
-0xff,0x00,0xf0,0x13,0x89,0x4f,0x14,0xd9,0xbf,0xfc,0xb5,0x4f,0xfb,0xea,0xa7,0x4d,\r
-0x7e,0xd5,0xff,0x00,0x8d,0x4f,0xe2,0x2b,0x4a,0xf7,0xf6,0x43,0xf1,0x8d,0xa0,0x2d,\r
-0xfd,0x8f,0xa8,0x81,0xe9,0x1a,0x16,0xfe,0x42,0xb0,0xef,0x7f,0x66,0xdf,0x17,0x58,\r
-0xf2,0xda,0x76,0xa7,0x17,0xfb,0xf6,0xed,0xfe,0x15,0xcf,0x2c,0xbe,0x9a,0xee,0xbe,\r
-0x47,0x3c,0xb2,0xdc,0x74,0x3a,0xfe,0x0c,0xbe,0xba,0xb5,0xbb,0x7f,0x18,0xa9,0x17,\r
-0x51,0x80,0xff,0x00,0x18,0xae,0x46,0xe7,0xe1,0x07,0x89,0xac,0x8e,0x1b,0xed,0x28,\r
-0x47,0x67,0x88,0xd5,0x17,0xf0,0x2f,0x89,0xad,0x8f,0x12,0x3f,0x1e,0xaa,0x6b,0x17,\r
-0x81,0xa5,0xd2,0x46,0x2f,0x0d,0x8d,0x8f,0x63,0xd0,0x16,0xfa,0x23,0xd2,0x4f,0xd6,\r
-0xa5,0x5b,0xdc,0x7d,0xd9,0x88,0xfc,0x6b,0xcc,0xdb,0x42,0xf1,0x4d,0xbe,0x79,0x27,\r
-0xeb,0x9a,0x66,0xcf,0x13,0x41,0xf7,0xa2,0x2d,0x8f,0x43,0x51,0xfd,0x9f,0x17,0xb4,\r
-0x85,0xc9,0x8d,0x8f,0xd8,0xfc,0x4f,0x55,0x4d,0x52,0x74,0xfb,0xb7,0x4e,0x3e,0x8d,\r
-0x56,0x23,0xd7,0xef,0xe3,0xfb,0x97,0xb2,0x8f,0xa3,0x1a,0xf2,0x1f,0xed,0x5f,0x10,\r
-0xc2,0x3e,0x6b,0x47,0x3f,0x4a,0x51,0xe2,0x9d,0x62,0x3f,0xbf,0x67,0x27,0xfd,0xf3,\r
-0x51,0xfd,0x9d,0x2e,0x92,0x41,0xed,0x31,0xb0,0xde,0x9b,0xfb,0xcf,0x67,0x8f,0xc6,\r
-0x1a,0xc4,0x5f,0x77,0x50,0x97,0xfe,0xfa,0xab,0xb0,0x7c,0x44,0xd7,0xe0,0xfb,0xba,\r
-0x84,0x9f,0x8d,0x78,0x7a,0xf8,0xea,0xf2,0x3f,0xf5,0x96,0xb2,0x8f,0xf8,0x09,0xa9,\r
-0x53,0xe2,0x29,0x5f,0xbf,0x14,0x8b,0xf5,0x14,0x96,0x06,0xbc,0x7e,0x17,0xf8,0x94,\r
-0xb1,0xd8,0xb8,0x6f,0x19,0x23,0xde,0x60,0xf8,0xb7,0xe2,0x48,0x3f,0xe5,0xf4,0x9f,\r
-0xad,0x69,0x43,0xf1,0xd7,0xc4,0xd0,0x81,0x8b,0x8c,0xe3,0xdc,0xd7,0xcf,0x91,0xfc,\r
-0x48,0x87,0xb8,0x65,0xfc,0x2a,0xcc,0x7f,0x11,0x2d,0x5b,0xab,0xe3,0xea,0x2a,0x95,\r
-0x0c,0x5c,0x7e,0x19,0x3f,0xbc,0xd5,0x67,0x18,0x98,0x6e,0xe4,0xbe,0x47,0xd1,0xb6,\r
-0xbf,0xb4,0x67,0x88,0xe0,0x00,0x17,0xcf,0xd0,0xd6,0xa5,0xbf,0xed,0x3f,0xae,0x46,\r
-0x7e,0x70,0xc7,0xf1,0xaf,0x99,0xe3,0xf1,0xed,0x9b,0x7f,0xcb,0x41,0xf8,0xd5,0x98,\r
-0xfc,0x69,0x66,0xf8,0xfd,0xea,0x7e,0x75,0x4a,0x58,0xf8,0x6d,0x26,0x6f,0x1e,0x20,\r
-0xaf,0x1f,0xb6,0xfe,0xe3,0xea,0x5b,0x7f,0xda,0xb3,0x50,0x4c,0x6f,0x84,0x93,0xf4,\r
-0x15,0xa9,0x6b,0xfb,0x58,0x37,0x1e,0x6c,0x39,0xff,0x00,0x80,0xd7,0xc9,0xd1,0xf8,\r
-0xae,0xd1,0xff,0x00,0xe5,0xa2,0x7e,0x75,0x3a,0x78,0x86,0xd5,0xfa,0x3a,0xfe,0x75,\r
-0x6b,0x19,0x98,0xc3,0xed,0x33,0xa6,0x3c,0x4d,0x59,0x7f,0xcb,0xc4,0x7d,0x7f,0x6f,\r
-0xfb,0x56,0xd9,0x39,0xc3,0xc2,0x07,0xd4,0x56,0xad,0xb7,0xed,0x45,0xa2,0xc9,0x8f,\r
-0x31,0x00,0xfc,0x6b,0xe3,0x15,0xd6,0x2d,0xdb,0xf8,0x87,0xe7,0x52,0x2e,0xa5,0x03,\r
-0x7f,0x1e,0x2b,0x45,0x9a,0xe6,0x11,0xdd,0xfe,0x07,0x5c,0x38,0x9a,0xb7,0xf3,0x26,\r
-0x7d,0xbb,0x6d,0xfb,0x48,0x78,0x7a,0x7c,0x6e,0x60,0xbf,0xf0,0x2a,0xd4,0x83,0xe3,\r
-0xdf,0x86,0x66,0xc7,0xef,0xc0,0xff,0x00,0x81,0x0a,0xf8,0x48,0x5f,0x44,0x7a,0x3f,\r
-0xeb,0x4f,0x5b,0xc5,0xea,0x25,0xc7,0xe3,0x5a,0x2c,0xef,0x1b,0x1d,0xd2,0xfb,0x8e,\r
-0xc8,0xf1,0x35,0x5e,0xa9,0x33,0xef,0xd8,0x3e,0x30,0xf8,0x6e,0x7c,0x62,0xec,0x0f,\r
-0xc4,0x55,0xe8,0x7e,0x25,0x78,0x7e,0x7c,0x6d,0xbe,0x4f,0xc6,0xbf,0x3e,0x56,0xf9,\r
-0x86,0x31,0x3b,0x7f,0xdf,0x55,0x3a,0x6a,0xd7,0x51,0xfd,0xcb,0xb9,0x07,0xd1,0xab,\r
-0x65,0xc4,0x18,0x85,0xbc,0x11,0xd5,0x1e,0x25,0x7d,0x60,0x7e,0x86,0x47,0xe3,0x4d,\r
-0x16,0x5c,0x62,0xfe,0x2f,0xc4,0xd5,0xa8,0xfc,0x45,0xa6,0xcb,0xf7,0x6f,0x61,0x3f,\r
-0xf0,0x2a,0xfc,0xf1,0x8f,0xc4,0x7a,0x8c,0x7f,0x76,0xf6,0x51,0xff,0x00,0x02,0xab,\r
-0x91,0x78,0xdf,0x5a,0x87,0xee,0xea,0x12,0x7e,0x75,0xb2,0xe2,0x29,0xaf,0x8a,0x9f,\r
-0xe2,0x74,0x47,0x89,0x21,0xd6,0x07,0xe8,0x52,0xea,0x96,0x8f,0xf7,0x6e,0x62,0x3f,\r
-0x46,0x15,0x2a,0xdc,0x44,0xdd,0x24,0x43,0xf4,0x22,0xbf,0x3f,0x20,0xf8,0x97,0xe2,\r
-0x08,0x08,0xdb,0x7c,0xe7,0xeb,0x57,0xe1,0xf8,0xc5,0xe2,0x48,0x7f,0xe5,0xec,0x9a,\r
-0xde,0x3c,0x45,0x0f,0xb5,0x4d,0x9d,0x31,0xe2,0x2c,0x3b,0xde,0x2c,0xfb,0xdc,0x3a,\r
-0x9e,0x8c,0x0f,0xe3,0x4b,0x9a,0xf8,0x66,0xdf,0xe3,0xdf,0x89,0x2d,0xff,0x00,0xe5,\r
-0xb6,0x7f,0x13,0x5a,0x96,0xdf,0xb4,0x87,0x88,0x21,0xc6,0xe6,0x2d,0xf8,0x9a,0xdd,\r
-0x71,0x0e,0x1d,0xef,0x16,0x8d,0xe3,0x9f,0xe1,0x1e,0xec,0xfb,0x4b,0x38,0xa3,0x22,\r
-0xbe,0x42,0xb7,0xfd,0xa8,0xb5,0x98,0xf1,0xb9,0x0f,0xe7,0x9a,0xd4,0xb5,0xfd,0xab,\r
-0x2e,0xd7,0x1e,0x64,0x44,0xfe,0x15,0xba,0xcf,0xb0,0x8f,0x7b,0xfd,0xc7,0x44,0x73,\r
-0xac,0x1c,0xbe,0xd1,0xf5,0x4e,0x45,0x15,0xf3,0x55,0xb7,0xed,0x5c,0xac,0x47,0x99,\r
-0x00,0x03,0xfd,0xda,0xd5,0xb7,0xfd,0xaa,0x74,0xe6,0xc6,0xf8,0x97,0xf2,0x35,0xbc,\r
-0x73,0x9c,0x14,0xbe,0xd9,0xd1,0x1c,0xd3,0x09,0x2d,0xa6,0x8f,0xa0,0x33,0x4b,0x5e,\r
-0x25,0x6b,0xfb,0x4e,0x68,0xb2,0xfd,0xf0,0x8b,0xf8,0x9a,0xd5,0xb7,0xfd,0xa2,0xfc,\r
-0x3b,0x36,0x01,0x60,0x0f,0xfb,0xd5,0xd1,0x1c,0xcf,0x07,0x2d,0xaa,0x23,0x75,0x8e,\r
-0xc3,0xcb,0x69,0xa3,0xd6,0x28,0xaf,0x3a,0x83,0xe3,0x9f,0x86,0xe6,0xc7,0xfa,0x40,\r
-0x5c,0xff,0x00,0xb4,0x2b,0x46,0xdf,0xe2,0xdf,0x87,0x6e,0x31,0x8b,0xb5,0x1f,0x52,\r
-0x2b,0x75,0x8d,0xc3,0x4b,0x6a,0x8b,0xef,0x36,0x58,0x8a,0x2f,0x69,0x23,0xb4,0xa2,\r
-0xb9,0xa8,0xfe,0x22,0xe8,0x12,0xfd,0xdb,0xf4,0xcd,0x5b,0x8b,0xc6,0x1a,0x44,0xdf,\r
-0x76,0xfa,0x2f,0xc4,0xd6,0xca,0xbd,0x29,0x6d,0x25,0xf7,0x9a,0x2a,0x90,0x7b,0x33,\r
-0x6a,0x8a,0xce,0x4f,0x10,0x69,0xd2,0x7d,0xdb,0xc8,0x5b,0xfe,0x05,0x56,0x13,0x51,\r
-0xb6,0x7e,0x97,0x11,0x1f,0xf8,0x18,0xad,0x14,0xe2,0xf6,0x65,0x73,0x2e,0xe5,0x9a,\r
-0x2a,0x35,0xb8,0x89,0xfe,0xec,0x88,0x7e,0x8d,0x4f,0xdc,0x3d,0x45,0x55,0xca,0x16,\r
-0x8a,0x29,0x33,0x4c,0x05,0xa2,0x93,0x34,0x66,0x80,0x16,0x8a,0x4a,0x33,0x40,0x0b,\r
-0x45,0x14,0x94,0x01,0xf3,0xdf,0xed,0x45,0x77,0xb6,0xde,0x38,0xf3,0xd2,0x3c,0x57,\r
-0xc7,0x5e,0x24,0xbc,0x5b,0x7b,0x39,0x58,0x9c,0x61,0x4d,0x7d,0x53,0xfb,0x54,0x5f,\r
-0x88,0xee,0x4a,0x93,0x8c,0x28,0x02,0xbe,0x1a,0xf8,0x97,0xe2,0x95,0xb6,0xb3,0x78,\r
-0x95,0xf2,0xc4,0x73,0xcd,0x7e,0x79,0x88,0xa6,0xeb,0xe6,0x53,0xf2,0xb1,0xf9,0x1f,\r
-0x13,0xd4,0x73,0xc4,0xaa,0x31,0xdd,0x9e,0xad,0xff,0x00,0x04,0xe8,0xd3,0xe6,0xd6,\r
-0x3f,0x69,0x8f,0x14,0xea,0xe1,0x37,0xda,0x69,0xfe,0x1f,0x92,0x06,0x7c,0xfd,0xd9,\r
-0x25,0xb8,0x8b,0x60,0xfc,0x44,0x4f,0xf9,0x57,0xe9,0x78,0xaf,0x87,0x7f,0xe0,0x96,\r
-0xbe,0x07,0x96,0xcb,0xc1,0x1e,0x34,0xf1,0xa4,0xe0,0x8f,0xed,0xcd,0x42,0x3b,0x3b,\r
-0x70,0xc3,0xac,0x56,0xca,0xd9,0x61,0xf5,0x69,0x98,0x7f,0xc0,0x2b,0xee,0x3a,0xfb,\r
-0xba,0x11,0xe5,0xa6,0x91,0xfa,0x46,0x59,0x43,0xea,0xf8,0x3a,0x74,0xfb,0x20,0xa2,\r
-0x8a,0x2b,0xa0,0xf5,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,\r
-0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,\r
-0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x93,0x14,0xb4,0x50,0x02,0x62,0x8c,\r
-0x52,0xd1,0x40,0x0d,0x23,0xd2,0x94,0x0a,0x5a,0x28,0x01,0x31,0x46,0xd1,0x4b,0x45,\r
-0x00,0x46,0xd0,0xa3,0x82,0x19,0x15,0x81,0xec,0x45,0x54,0x9b,0x40,0xd3,0x6e,0x46,\r
-0x26,0xd3,0xed,0x65,0x1f,0xed,0xc2,0xa7,0xfa,0x55,0xfa,0x2a,0x5c,0x53,0xdd,0x12,\r
-0xe2,0x9e,0xe8,0xe7,0x6e,0x7e,0x1e,0x78,0x62,0xf3,0xfd,0x76,0x81,0xa7,0x3f,0xfd,\r
-0xbb,0x20,0xfe,0x42,0xb2,0xee,0x7e,0x0b,0xf8,0x26,0xef,0x3e,0x67,0x87,0x2c,0xc6,\r
-0x7f,0xb8,0xa5,0x3f,0x91,0x15,0xdb,0x51,0x59,0xba,0x34,0x9e,0xf1,0x5f,0x71,0x93,\r
-0xa1,0x4a,0x5b,0xc1,0x7d,0xc8,0xf3,0x2b,0xbf,0xd9,0xc7,0xc0,0x37,0x60,0x8f,0xec,\r
-0x51,0x1f,0xba,0x4c,0xff,0x00,0xd4,0x9a,0xc7,0xba,0xfd,0x93,0xfc,0x09,0x70,0x72,\r
-0xb0,0xdd,0xc3,0xec,0x92,0xaf,0xf5,0x53,0x5e,0xcb,0x45,0x64,0xf0,0x94,0x1f,0xd8,\r
-0x46,0x0f,0x03,0x86,0x7b,0xd3,0x5f,0x71,0xe0,0x37,0xbf,0xb1,0xaf,0x84,0x27,0xcf,\r
-0x91,0x77,0x79,0x11,0x3f,0xdf,0xd8,0xf8,0xfd,0x05,0x61,0x5d,0x7e,0xc3,0xba,0x2c,\r
-0xb9,0xf2,0xf5,0xc6,0x5f,0x4d,0xd6,0x80,0xff,0x00,0xec,0xf5,0xf4,0xdd,0x15,0x9b,\r
-0xc0,0xe1,0xdf,0xd9,0xfc,0xcc,0x9e,0x5b,0x84,0x7f,0x63,0xf3,0x3e,0x46,0xd4,0x3f,\r
-0x61,0x38,0x98,0x9f,0xb3,0x6a,0xd6,0x92,0x0f,0xfa,0x69,0x01,0x4f,0xe5,0x9a,0xe7,\r
-0xef,0x3f,0x60,0xcd,0x49,0x89,0xf2,0xee,0xb4,0xb7,0x1d,0xbe,0x77,0x07,0xff,0x00,\r
-0x40,0xaf,0xb6,0x31,0x46,0x2b,0x37,0x97,0x50,0xe9,0x75,0xf3,0x31,0x79,0x46,0x15,\r
-0xf4,0x7f,0x79,0xf0,0x45,0xff,0x00,0xec,0x29,0xe2,0x18,0x81,0x31,0x5b,0x5a,0x4d,\r
-0x8e,0xd1,0xdc,0x00,0x4f,0xe7,0x8a,0xc0,0xba,0xfd,0x89,0xbc,0x5d,0x10,0x24,0x69,\r
-0x12,0x71,0xfd,0xcb,0x84,0x3f,0xc9,0xab,0xf4,0x5b,0x14,0x98,0x35,0x1f,0xd9,0xb4,\r
-0xfa,0x49,0x9c,0xf2,0xc8,0xf0,0xd2,0xea,0xff,0x00,0x0f,0xf2,0x3f,0x33,0x2f,0xbf,\r
-0x64,0xaf,0x18,0x59,0x96,0x1f,0xd8,0xda,0x96,0x47,0xfc,0xf3,0x8d,0x98,0x7e,0x60,\r
-0x56,0x15,0xdf,0xec,0xe7,0xe2,0xcb,0x30,0x49,0xd3,0xf5,0x38,0xc0,0xea,0x5a,0xdd,\r
-0xb1,0xfc,0xab,0xf5,0x47,0x14,0x9b,0x73,0xd6,0xb3,0x79,0x6f,0x6a,0x8c,0xe5,0x97,\r
-0x0e,0xe1,0xe5,0xd7,0xf0,0x47,0xe4,0xbd,0xcf,0xc2,0x3f,0x11,0xd9,0x83,0x93,0x70,\r
-0x9f,0xef,0x46,0x45,0x51,0x93,0xc0,0xfe,0x25,0xb7,0xe9,0x23,0xf1,0xea,0xa6,0xbf,\r
-0x5c,0xde,0xde,0x39,0x06,0x19,0x15,0x87,0xa3,0x0c,0xd5,0x3b,0x8f,0x0f,0x69,0x77,\r
-0x9f,0xeb,0xf4,0xeb,0x49,0xbf,0xdf,0x81,0x5b,0xf9,0x8a,0xcd,0xe5,0xd3,0xe9,0x3f,\r
-0xc0,0xe3,0x9f,0x0b,0xd0,0x97,0x6f,0xbb,0xfe,0x09,0xf9,0x24,0xda,0x1f,0x8a,0x2d,\r
-0xfb,0x96,0xc7,0xd6,0xa3,0x2b,0xe2,0x58,0x3a,0xc5,0xbb,0xe8,0x6b,0xf5,0x7a,0xe3,\r
-0xe1,0xb7,0x85,0x6e,0xb3,0xe6,0xf8,0x7b,0x4d,0x6c,0xf5,0x3f,0x66,0x40,0x7f,0x41,\r
-0x59,0x57,0x5f,0x04,0x7c,0x0f,0x77,0xf7,0xfc,0x3b,0x68,0x3d,0x76,0xee,0x5f,0xe4,\r
-0x6b,0x27,0x96,0xd5,0xee,0x99,0xc7,0x2e,0x14,0xa6,0xf6,0xb7,0xe2,0x7e,0x5a,0xff,\r
-0x00,0x6a,0xf8,0x86,0x1f,0xbd,0x6a,0xc7,0x1e,0x94,0xe1,0xe2,0x9d,0x62,0x2f,0xbf,\r
-0x67,0x27,0xfd,0xf3,0x5f,0xa6,0x37,0x7f,0xb3,0x5f,0x80,0x2e,0xff,0x00,0xe6,0x0c,\r
-0x61,0xff,0x00,0xae,0x73,0x3f,0xf5,0x26,0xb1,0xee,0xbf,0x64,0xbf,0x01,0xdc,0x92,\r
-0x56,0x1b,0xd8,0x7d,0x92,0x65,0xfe,0xaa,0x6b,0x17,0x96,0xd5,0xfe,0x58,0x9c,0xb2,\r
-0xe1,0x3e,0xcb,0xf1,0x7f,0xe4,0x7e,0x74,0x8f,0x1c,0xde,0xc6,0x7e,0x7b,0x59,0x07,\r
-0xe0,0x6a,0x54,0xf8,0x88,0xeb,0xf7,0xe2,0x71,0xf9,0xd7,0xde,0xd7,0xbf,0xb1,0x87,\r
-0x85,0x27,0xcf,0x91,0x7f,0x79,0x0f,0xfb,0xea,0xaf,0xfe,0x15,0x89,0x75,0xfb,0x0e,\r
-0x68,0xf2,0x92,0x63,0xd7,0x18,0x7b,0x35,0xa0,0x3f,0xfb,0x3d,0x61,0x2c,0xb6,0xa7,\r
-0x5a,0x6b,0xef,0x39,0xa5,0xc2,0xd5,0x97,0xc3,0x7f,0xbd,0x1f,0x16,0xc7,0xf1,0x1e,\r
-0x2e,0xe0,0x8a,0xb3,0x1f,0xc4,0x4b,0x66,0xea,0xf5,0xf5,0x5e,0xa1,0xfb,0x08,0x29,\r
-0xcf,0xd9,0xb5,0x6b,0x39,0x07,0x6f,0x36,0x16,0x5f,0xe5,0x9a,0xe7,0xee,0xff,0x00,\r
-0x60,0xbd,0x4c,0x82,0x52,0xe7,0x4a,0x7f,0x6d,0xce,0x3f,0xf6,0x4a,0xc2,0x59,0x6b,\r
-0xeb,0x49,0x9c,0xd2,0xe1,0xcc,0x5c,0x76,0x72,0xfc,0x19,0xf3,0xec,0x7e,0x3d,0xb4,\r
-0x7c,0x66,0x40,0x3e,0xb5,0x66,0x3f,0x1a,0xd9,0xbe,0x3f,0x7a,0xb5,0xea,0xfa,0x87,\r
-0xec,0x2f,0xe2,0x58,0x58,0x88,0xac,0x6d,0xe7,0x03,0xbc,0x57,0x0a,0x07,0xea,0x45,\r
-0x61,0x5e,0x7e,0xc5,0x3e,0x2f,0x81,0x49,0x1a,0x3c,0xa7,0x1f,0xf3,0xce,0x74,0x6f,\r
-0xe4,0xd5,0x83,0xcb,0xa3,0xd6,0x9c,0x97,0xc8,0xe7,0x96,0x49,0x8e,0x8e,0xd2,0x7f,\r
-0xf8,0x09,0xc6,0xc7,0xe2,0xcb,0x47,0xc7,0xef,0x53,0xf3,0xa9,0xd3,0xc4,0x76,0xaf,\r
-0xd2,0x45,0x3f,0x8d,0x5d,0xbc,0xfd,0x93,0x7c,0x61,0x66,0x0b,0x7f,0x62,0xea,0x60,\r
-0x7f,0xb1,0x13,0x37,0xf2,0x15,0x87,0x79,0xfb,0x3b,0xf8,0xb2,0xc7,0xef,0xe9,0xfa,\r
-0x9c,0x5f,0xef,0xdb,0xb0,0xfe,0x95,0xce,0xf0,0x14,0x97,0x46,0xbe,0x47,0x3c,0xb2,\r
-0xec,0x74,0x3e,0xd7,0xe0,0xcd,0x55,0xd6,0xad,0xdb,0xf8,0x87,0xe7,0x52,0x0d,0x4e,\r
-0x06,0xfe,0x31,0x5c,0x6d,0xc7,0xc2,0x9f,0x10,0xda,0x31,0x52,0xd3,0xa1,0x07,0x18,\r
-0x68,0xc8,0xaa,0x72,0x78,0x23,0xc4,0x96,0xfd,0x24,0x63,0x8f,0xf6,0x4d,0x66,0xf0,\r
-0x34,0xba,0x48,0xc1,0xe1,0x71,0xb1,0xec,0xcf,0x41,0x17,0xf0,0xff,0x00,0x7a,0x9e,\r
-0xb7,0x91,0xf6,0x7f,0xd6,0xbc,0xd1,0xb4,0x4f,0x13,0x41,0xdc,0x9f,0x6e,0x69,0xa4,\r
-0x78,0x96,0x0e,0xb1,0x16,0xfc,0x6b,0x37,0x97,0xc5,0xed,0x22,0x7d,0x9e,0x35,0x7d,\r
-0x84,0xfe,0x67,0xa8,0xad,0xe0,0x1d,0x25,0x23,0xf1,0xa9,0x93,0x50,0x95,0x7e,0xed,\r
-0xc3,0x8f,0xa3,0x57,0x93,0xff,0x00,0x6a,0xf8,0x82,0x1f,0xbd,0x6a,0xc7,0x1e,0x94,\r
-0xa3,0xc5,0x3a,0xbc,0x5f,0x7e,0xd2,0x4f,0xfb,0xe6,0xa1,0xe5,0xcf,0xa4,0x90,0x73,\r
-0x62,0xe3,0xbd,0x37,0xf7,0x9e,0xbd,0x1e,0xb5,0x7b,0x11,0xf9,0x2e,0xe4,0x1f,0x47,\r
-0x35,0x65,0x3c,0x55,0xaa,0xc7,0xf7,0x6f,0xa5,0xff,0x00,0xbe,0x8d,0x78,0xe0,0xf1,\r
-0xcd,0xe4,0x7f,0x7e,0xda,0x41,0xff,0x00,0x01,0x35,0x2a,0x7c,0x44,0x61,0xf7,0xa2,\r
-0x71,0x51,0xfd,0x9f,0x55,0x6c,0xff,0x00,0x11,0xac,0x5e,0x26,0x3b,0xc2,0x47,0xb4,\r
-0xc3,0xe3,0xcd,0x72,0x0f,0xbb,0x7d,0x27,0xe2,0x6a,0xec,0x3f,0x14,0x7c,0x43,0x0e,\r
-0x31,0x7a,0xe7,0xea,0x6b,0xc4,0x13,0xe2,0x3c,0x47,0x19,0xdd,0x56,0xa3,0xf8,0x89,\r
-0x6c,0x71,0x97,0x22,0x8f,0xa9,0xe2,0x63,0xb5,0xfe,0xf3,0x45,0x9a,0x57,0x86,0xfc,\r
-0xcb,0xef,0x3d,0xda,0xdf,0xe3,0x4f,0x89,0x20,0xc6,0x2e,0x4f,0xe6,0x6b,0x46,0xdb,\r
-0xe3,0xff,0x00,0x88,0xa0,0xc6,0x64,0x2c,0x7d,0x77,0x57,0x81,0x47,0xe3,0xdb,0x46,\r
-0xff,0x00,0x96,0x95,0x66,0x3f,0x1a,0xda,0x37,0xfc,0xb5,0x5a,0x7c,0x98,0xc8,0x6d,\r
-0x27,0xf7,0x9b,0x47,0x3c,0xad,0x1f,0xb6,0xfe,0xe3,0xe8,0x8b,0x7f,0xda,0x53,0x5f,\r
-0x8b,0x86,0x27,0x1e,0xcd,0x5a,0x96,0xdf,0xb5,0x26,0xab,0x10,0x1b,0xe3,0x63,0xf5,\r
-0x35,0xf3,0x5c,0x7e,0x2d,0xb4,0x7e,0x92,0xaf,0xe7,0x53,0xaf,0x88,0xed,0x5f,0xa3,\r
-0xaf,0xe7,0x56,0xab,0xe3,0xe1,0xb4,0xd9,0xd3,0x1e,0x22,0xac,0xbf,0xe5,0xe1,0xf5,\r
-0x0d,0xb7,0xed,0x59,0x73,0x91,0xe6,0xa1,0xff,0x00,0xbe,0x45,0x6b,0x5b,0x7e,0xd5,\r
-0xb0,0xb6,0x03,0xc2,0x3e,0xa4,0x57,0xc9,0xc9,0xad,0xdb,0xbf,0xf1,0x8f,0xce,0xa5,\r
-0x5d,0x52,0x06,0xfe,0x2a,0xb5,0x98,0x66,0x10,0xfb,0x6f,0xee,0x3a,0xe1,0xc4,0x95,\r
-0x97,0xdb,0x47,0xd8,0x16,0xbf,0xb5,0x26,0x9a,0xc3,0xf7,0xa8,0xbf,0x91,0xad,0x4b,\r
-0x6f,0xda,0x5b,0x44,0x9b,0x19,0x0a,0x3f,0x1a,0xf8,0xb4,0x6a,0x30,0x9e,0x77,0x0a,\r
-0x6b,0xea,0xb0,0x20,0x3f,0x3f,0xeb,0x5b,0x47,0x36,0xc7,0xad,0x2f,0x7f,0x91,0xd4,\r
-0xb8,0x9e,0xac,0x77,0x68,0xfb,0xa2,0xdf,0xf6,0x84,0xf0,0xec,0xa0,0x66,0x50,0x0f,\r
-0xb3,0x0a,0xb7,0x37,0xc7,0x8f,0x0d,0x43,0x6e,0x65,0x7b,0x8c,0x01,0xdb,0x70,0xcd,\r
-0x7e,0x7b,0xdf,0xf8,0xce,0xd6,0xc9,0x09,0x33,0x85,0xc7,0xfb,0x55,0xc0,0x78,0x93,\r
-0xe2,0xcc,0x80,0x34,0x76,0x92,0xb1,0x27,0xbe,0x6b,0xd5,0xa1,0x8f,0xcc,0x2a,0xbd,\r
-0x52,0x17,0xfa,0xd9,0x56,0x4f,0x96,0x9d,0x3e,0x66,0x7b,0xb7,0xed,0x37,0xf1,0xc6,\r
-0xcf,0x5f,0xd5,0xee,0xe4,0xb5,0x93,0x31,0x74,0x8c,0x1e,0xb5,0xf2,0xd7,0x87,0x3c,\r
-0x2b,0xaf,0xfc,0x6d,0xf1,0xe6,0x9f,0xe1,0x8d,0x0a,0x16,0xb8,0xd4,0x35,0x09,0x76,\r
-0x6e,0xfe,0x08,0x63,0xcf,0xcd,0x23,0x9e,0xca,0xa3,0x24,0x9f,0x6f,0x5a,0x93,0xc2,\r
-0xbe,0x13,0xf1,0x57,0xc6,0x6f,0x16,0x41,0xa3,0x68,0x36,0x13,0x6a,0xba,0x95,0xc3,\r
-0x70,0x89,0xf7,0x51,0x7b,0xbb,0xb1,0xe1,0x54,0x77,0x27,0xfa,0x8a,0xfd,0x46,0xfd,\r
-0x97,0x3f,0x65,0xdd,0x1b,0xf6,0x79,0xf0,0xdb,0x39,0x31,0xea,0x5e,0x2b,0xbe,0x41,\r
-0xfd,0xa1,0xa9,0xe3,0x8c,0x75,0xf2,0xa2,0xcf,0x21,0x01,0xfc,0x58,0xf2,0x7b,0x01,\r
-0xe9,0x61,0x70,0xaf,0x99,0xce,0x5b,0xbd,0x5b,0x34,0xcb,0x30,0x15,0x73,0x1c,0x53,\r
-0xc6,0x62,0x3f,0xe0,0x7a,0x23,0xd2,0xfe,0x17,0x7c,0x3e,0xd3,0x7e,0x15,0xf8,0x03,\r
-0x44,0xf0,0xa6,0x92,0x81,0x6c,0x74,0xbb,0x65,0x81,0x5b,0x1c,0xbb,0x75,0x67,0x3e,\r
-0xec,0xc4,0x93,0xf5,0xae,0xaa,0x90,0x0c,0x52,0xd7,0xd0,0x25,0x6d,0x0f,0xd2,0xd2,\r
-0xb2,0xb2,0x0a,0x28,0xa2,0x81,0x85,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,\r
-0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,\r
-0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,\r
-0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,\r
-0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,\r
-0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,\r
-0x51,0x40,0x05,0x14,0x51,0x40,0x09,0x46,0x29,0x68,0xa0,0x04,0xc5,0x18,0xa5,0xa2,\r
-0x80,0x13,0x6d,0x26,0xda,0x75,0x14,0x01,0x13,0xda,0xc3,0x26,0x77,0xc4,0x8d,0x9e,\r
-0xb9,0x50,0x6a,0x8d,0xc7,0x86,0xb4,0x9b,0xa0,0x44,0xda,0x5d,0x9c,0xca,0x7a,0x89,\r
-0x20,0x43,0xfd,0x2b,0x4e,0x8a,0x97,0x18,0xbd,0xd1,0x2e,0x31,0x7b,0xa3,0x98,0xb9,\r
-0xf8,0x65,0xe1,0x3b,0xb1,0xfb,0xdf,0x0e,0xe9,0xa7,0xe9,0x6c,0x8b,0xfc,0x85,0x65,\r
-0xdd,0x7c,0x0e,0xf0,0x35,0xd9,0x26,0x4f,0x0e,0x5a,0x0f,0xf7,0x37,0x27,0xf2,0x22,\r
-0xbb,0xba,0x2b,0x37,0x42,0x93,0xde,0x2b,0xee,0x31,0x78,0x7a,0x32,0xde,0x0b,0xee,\r
-0x47,0x96,0x5d,0xfe,0xcc,0xfe,0x00,0xbb,0x24,0xff,0x00,0x64,0x34,0x24,0xff,0x00,\r
-0xcf,0x39,0x9b,0x8f,0xcc,0x9a,0xc7,0xba,0xfd,0x91,0xfc,0x0b,0x71,0xf7,0x12,0xf6,\r
-0x13,0xfe,0xcc,0xaa,0x7f,0x9a,0xd7,0xb5,0xd1,0x59,0x3c,0x25,0x07,0xf6,0x11,0x8b,\r
-0xc0,0xe1,0x9f,0xfc,0xbb,0x47,0xcf,0x37,0xbf,0xb1,0x77,0x85,0x67,0x27,0xc8,0xd4,\r
-0x2e,0xe1,0x1e,0x8e,0x88,0xff,0x00,0xcb,0x15,0x8b,0x75,0xfb,0x0d,0x69,0x12,0xe7,\r
-0xcb,0xd7,0x58,0x7a,0x6f,0xb4,0x07,0xff,0x00,0x66,0xaf,0xa8,0x28,0xac,0xde,0x07,\r
-0x0e,0xfe,0xcf,0xe6,0x64,0xf2,0xcc,0x2b,0xfb,0x1f,0x8b,0x3e,0x3e,0xbf,0xfd,0x84,\r
-0x1c,0x93,0xf6,0x7d,0x56,0xc6,0x40,0x7f,0xe7,0xac,0x4c,0xbf,0xc8,0x1a,0xc1,0xbd,\r
-0xfd,0x83,0x35,0x65,0xc9,0x8e,0xe7,0x4b,0x97,0xe8,0xee,0x0f,0xea,0xa2,0xbe,0xdf,\r
-0xa4,0x6e,0x95,0x93,0xcb,0xa8,0x74,0xbf,0xde,0x60,0xf2,0x8c,0x2b,0xe8,0xfe,0xf3,\r
-0xe0,0x0b,0xef,0xd8,0x67,0xc4,0xd1,0x93,0xe5,0xe9,0xf0,0x4c,0x3f,0xe9,0x95,0xc2,\r
-0x0f,0xe6,0x45,0x61,0x5e,0x7e,0xc5,0x7e,0x30,0xb7,0x04,0x8d,0x16,0x63,0xff,0x00,\r
-0x5c,0xe7,0x46,0xfe,0x4c,0x6b,0xf4,0x6c,0x75,0xa0,0x75,0xac,0xde,0x5d,0x4f,0xa4,\r
-0x99,0xcf,0x2c,0x8f,0x0c,0xfa,0xbf,0xc3,0xfc,0x8f,0xcc,0x3b,0xcf,0xd9,0x53,0xc5,\r
-0xd6,0x8c,0x41,0xd1,0x35,0x51,0x8f,0xee,0xc0,0xec,0x3f,0x30,0x2b,0x16,0xfb,0xf6,\r
-0x7b,0xf1,0x56,0x9e,0xa5,0xa4,0xb1,0xd4,0xa1,0x03,0xbb,0xc0,0xc3,0xfa,0x57,0xea,\r
-0xb8,0xe9,0x4d,0x3c,0xd4,0x3c,0xbb,0xb4,0xd9,0xcb,0x2e,0x1d,0xc3,0xbe,0xbf,0x82,\r
-0x3f,0x24,0x67,0xf8,0x59,0xaf,0xda,0x9c,0x16,0x99,0x7f,0xde,0x42,0x2a,0xa3,0xf8,\r
-0x2b,0xc4,0x50,0x1e,0x25,0x6f,0xc4,0x1a,0xfd,0x75,0x96,0xd6,0x19,0x57,0xe7,0x89,\r
-0x1f,0xfd,0xe5,0x06,0xb3,0x2f,0x3c,0x37,0xa4,0x5d,0xff,0x00,0xaf,0xd2,0xec,0xa6,\r
-0xff,0x00,0xae,0x96,0xe8,0xdf,0xcc,0x57,0x34,0xf0,0x72,0x8f,0xdb,0xfc,0x3f,0xe0,\r
-0x9e,0x65,0x5e,0x1d,0xc3,0xc7,0xb7,0xdd,0xff,0x00,0x04,0xfc,0x94,0x9b,0x44,0xf1,\r
-0x2c,0x2b,0xc3,0x13,0xf4,0xcd,0x64,0x5d,0xe8,0x9e,0x28,0x94,0x13,0x99,0x31,0xec,\r
-0x09,0xaf,0xd4,0x6f,0x14,0x78,0x37,0x40,0x44,0x98,0xae,0x87,0xa6,0x83,0x8e,0xa2,\r
-0xd2,0x3f,0xf0,0xac,0x0f,0x06,0xf8,0x4b,0x43,0x9e,0xf1,0xd6,0x5d,0x1b,0x4f,0x91,\r
-0x72,0x38,0x7b,0x54,0x23,0xf9,0x57,0x1c,0x63,0x25,0x2b,0x2b,0x7d,0xc7,0x8f,0x2c,\r
-0x97,0x0c,0xa5,0xca,0x92,0xfb,0x8f,0xcc,0x9b,0x2f,0x86,0x9e,0x2d,0xf1,0x2d,0xd8,\r
-0xb7,0xb3,0xd3,0xef,0x75,0x19,0xd8,0xf1,0x15,0xbc,0x4c,0xed,0xcf,0xb0,0x15,0xf4,\r
-0x27,0xc2,0x4f,0xf8,0x27,0x6f,0x8a,0x7c,0x4d,0x3c,0x37,0x7e,0x31,0xb9,0x5f,0x0d,\r
-0xe9,0x99,0x05,0xa0,0x52,0x24,0xba,0x71,0xd7,0x85,0x1f,0x2a,0xfd,0x58,0xe4,0x7f,\r
-0x76,0xbf,0x46,0x74,0xed,0x2e,0xcf,0x4c,0xb7,0x58,0xac,0xed,0x20,0xb4,0x8c,0x0e,\r
-0x12,0x08,0xd5,0x00,0xfc,0x00,0xab,0x8b,0x5e,0xfd,0x1c,0x3d,0xd2,0x94,0xdd,0xcf,\r
-0xa2,0xc0,0xf0,0xed,0x18,0x5a,0x75,0x26,0xe4,0xbb,0x5a,0xc8,0xe2,0x7e,0x16,0xfc,\r
-0x1b,0xf0,0xa7,0xc1,0xcd,0x0c,0x69,0x9e,0x18,0xd2,0xe3,0xb3,0x46,0x03,0xce,0xb8,\r
-0x6f,0x9a,0x79,0xc8,0xef,0x23,0xf5,0x3f,0x4e,0x83,0xb0,0x15,0xdb,0x8e,0x28,0x1d,\r
-0x29,0x6b,0xd0,0x49,0x25,0x64,0x7d,0x8c,0x29,0xc6,0x9c,0x54,0x20,0xac,0x90,0x51,\r
-0x45,0x14,0xcd,0x02,0x8a,0x28,0xa0,0x0f,0xff,0xd9,};\r
-\r
-static const unsigned int dummy_align__runtime_shtml = 3;\r
-static const unsigned char data__runtime_shtml[] = {\r
-/* /runtime.shtml (15 chars) */\r
-0x2f,0x72,0x75,0x6e,0x74,0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x00,0x00,\r
-\r
-/* HTTP header */\r
-/* "HTTP/1.0 200 OK\r
-" (17 bytes) */\r
-0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d,\r
-0x0a,\r
-/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)\r
-" (63 bytes) */\r
-0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33,\r
-0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e,\r
-0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70,\r
-0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a,\r
-/* "Content-type: text/html\r
-Expires: Fri, 10 Apr 2008 14:00:00 GMT\r
-Pragma: no-cache\r
-\r
-" (85 bytes) */\r
-0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65,\r
-0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x45,0x78,0x70,0x69,0x72,0x65,0x73,\r
-0x3a,0x20,0x46,0x72,0x69,0x2c,0x20,0x31,0x30,0x20,0x41,0x70,0x72,0x20,0x32,0x30,\r
-0x30,0x38,0x20,0x31,0x34,0x3a,0x30,0x30,0x3a,0x30,0x30,0x20,0x47,0x4d,0x54,0x0d,\r
-0x0a,0x50,0x72,0x61,0x67,0x6d,0x61,0x3a,0x20,0x6e,0x6f,0x2d,0x63,0x61,0x63,0x68,\r
-0x65,0x0d,0x0a,0x0d,0x0a,\r
-/* raw file data (758 bytes) */\r
-0x3c,0x21,0x44,0x4f,0x43,0x54,0x59,0x50,0x45,0x20,0x48,0x54,0x4d,0x4c,0x20,0x50,\r
-0x55,0x42,0x4c,0x49,0x43,0x20,0x22,0x2d,0x2f,0x2f,0x57,0x33,0x43,0x2f,0x2f,0x44,\r
-0x54,0x44,0x20,0x48,0x54,0x4d,0x4c,0x20,0x34,0x2e,0x30,0x31,0x20,0x54,0x72,0x61,\r
-0x6e,0x73,0x69,0x74,0x69,0x6f,0x6e,0x61,0x6c,0x2f,0x2f,0x45,0x4e,0x22,0x20,0x22,\r
-0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x77,0x33,0x2e,0x6f,0x72,\r
-0x67,0x2f,0x54,0x52,0x2f,0x68,0x74,0x6d,0x6c,0x34,0x2f,0x6c,0x6f,0x6f,0x73,0x65,\r
-0x2e,0x64,0x74,0x64,0x22,0x3e,0x0d,0x0a,0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a,\r
-0x20,0x20,0x3c,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74,\r
-0x69,0x74,0x6c,0x65,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53,0x2e,0x6f,0x72,\r
-0x67,0x20,0x6c,0x77,0x49,0x50,0x20,0x57,0x45,0x42,0x20,0x73,0x65,0x72,0x76,0x65,\r
-0x72,0x20,0x64,0x65,0x6d,0x6f,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x0d,0x0a,\r
-0x20,0x20,0x3c,0x2f,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x3c,0x42,0x4f,\r
-0x44,0x59,0x20,0x6f,0x6e,0x4c,0x6f,0x61,0x64,0x3d,0x22,0x77,0x69,0x6e,0x64,0x6f,\r
-0x77,0x2e,0x73,0x65,0x74,0x54,0x69,0x6d,0x65,0x6f,0x75,0x74,0x28,0x26,0x71,0x75,\r
-0x6f,0x74,0x3b,0x6c,0x6f,0x63,0x61,0x74,0x69,0x6f,0x6e,0x2e,0x68,0x72,0x65,0x66,\r
-0x3d,0x27,0x72,0x75,0x6e,0x74,0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x27,\r
-0x26,0x71,0x75,0x6f,0x74,0x3b,0x2c,0x32,0x30,0x30,0x30,0x29,0x22,0x3e,0x0d,0x0a,\r
-0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x61,0x72,0x69,0x61,\r
-0x6c,0x22,0x3e,0x0d,0x0a,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x69,0x6e,\r
-0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x54,0x61,0x73,0x6b,0x20,\r
-0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c,0x3c,0x2f,\r
-0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x72,0x75,0x6e,0x74,\r
-0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x52,0x75,0x6e,0x20,0x54,\r
-0x69,0x6d,0x65,0x20,0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,\r
-0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,\r
-0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x66,0x72,0x65,0x65,0x72,\r
-0x74,0x6f,0x73,0x2e,0x6f,0x72,0x67,0x2f,0x22,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,\r
-0x4f,0x53,0x20,0x48,0x6f,0x6d,0x65,0x70,0x61,0x67,0x65,0x3c,0x2f,0x61,0x3e,0x20,\r
-0x3c,0x62,0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,\r
-0x3d,0x22,0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x22,0x3e,0x33,0x37,0x4b,0x20,\r
-0x6a,0x70,0x67,0x3c,0x2f,0x61,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,\r
-0x0d,0x0a,0x3c,0x68,0x72,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d,\r
-0x0a,0x3c,0x68,0x32,0x3e,0x52,0x75,0x6e,0x2d,0x74,0x69,0x6d,0x65,0x20,0x73,0x74,\r
-0x61,0x74,0x69,0x73,0x74,0x69,0x63,0x73,0x3c,0x2f,0x68,0x32,0x3e,0x0d,0x0a,0x50,\r
-0x61,0x67,0x65,0x20,0x77,0x69,0x6c,0x6c,0x20,0x72,0x65,0x66,0x72,0x65,0x73,0x68,\r
-0x20,0x65,0x76,0x65,0x72,0x79,0x20,0x32,0x20,0x73,0x65,0x63,0x6f,0x6e,0x64,0x73,\r
-0x2e,0x3c,0x70,0x3e,0x0d,0x0a,0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,\r
-0x3d,0x22,0x63,0x6f,0x75,0x72,0x69,0x65,0x72,0x22,0x3e,0x3c,0x70,0x72,0x65,0x3e,\r
-0x54,0x61,0x73,0x6b,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,\r
-0x41,0x62,0x73,0x20,0x54,0x69,0x6d,0x65,0x20,0x20,0x20,0x20,0x20,0x20,0x25,0x20,\r
-0x54,0x69,0x6d,0x65,0x3c,0x62,0x72,0x3e,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
-0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
-0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
-0x3c,0x62,0x72,0x3e,0x0d,0x0a,0x3c,0x21,0x2d,0x2d,0x23,0x72,0x75,0x6e,0x5f,0x73,\r
-0x74,0x61,0x74,0x73,0x2d,0x2d,0x3e,0x0d,0x0d,0x0a,0x3c,0x2f,0x70,0x72,0x65,0x3e,\r
-0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,\r
-0x0d,0x0a,0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0d,0x0a,0x3c,0x2f,0x68,0x74,0x6d,\r
-0x6c,0x3e,0x0d,0x0a,0x0d,0x0a,};\r
-\r
-\r
-\r
-const struct fsdata_file file__404_html[] = { {\r
-file_NULL,\r
-data__404_html,\r
-data__404_html + 12,\r
-sizeof(data__404_html) - 12,\r
-1,\r
-}};\r
-\r
-const struct fsdata_file file__index_shtml[] = { {\r
-file__404_html,\r
-data__index_shtml,\r
-data__index_shtml + 16,\r
-sizeof(data__index_shtml) - 16,\r
-1,\r
-}};\r
-\r
-const struct fsdata_file file__logo_jpg[] = { {\r
-file__index_shtml,\r
-data__logo_jpg,\r
-data__logo_jpg + 12,\r
-sizeof(data__logo_jpg) - 12,\r
-1,\r
-}};\r
-\r
-const struct fsdata_file file__runtime_shtml[] = { {\r
-file__logo_jpg,\r
-data__runtime_shtml,\r
-data__runtime_shtml + 16,\r
-sizeof(data__runtime_shtml) - 16,\r
-1,\r
-}};\r
-\r
-#define FS_ROOT file__runtime_shtml\r
-#define FS_NUMFILES 4\r
-\r
+++ /dev/null
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef __FSDATA_H__
-#define __FSDATA_H__
-
-#include "lwip/opt.h"
-#include "fs.h"
-
-struct fsdata_file {
- const struct fsdata_file *next;
- const unsigned char *name;
- const unsigned char *data;
- int len;
- u8_t http_header_included;
-#if HTTPD_PRECALCULATED_CHECKSUM
- u16_t chksum_count;
- const struct fsdata_chksum *chksum;
-#endif /* HTTPD_PRECALCULATED_CHECKSUM */
-};
-
-#endif /* __FSDATA_H__ */
+++ /dev/null
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-/* This httpd supports for a
- * rudimentary server-side-include facility which will replace tags of the form
- * <!--#tag--> in any file whose extension is .shtml, .shtm or .ssi with
- * strings provided by an include handler whose pointer is provided to the
- * module via function http_set_ssi_handler().
- * Additionally, a simple common
- * gateway interface (CGI) handling mechanism has been added to allow clients
- * to hook functions to particular request URIs.
- *
- * To enable SSI support, define label LWIP_HTTPD_SSI in lwipopts.h.
- * To enable CGI support, define label LWIP_HTTPD_CGI in lwipopts.h.
- *
- * By default, the server assumes that HTTP headers are already present in
- * each file stored in the file system. By defining LWIP_HTTPD_DYNAMIC_HEADERS in
- * lwipopts.h, this behavior can be changed such that the server inserts the
- * headers automatically based on the extension of the file being served. If
- * this mode is used, be careful to ensure that the file system image used
- * does not already contain the header information.
- *
- * File system images without headers can be created using the makefsfile
- * tool with the -h command line option.
- *
- *
- * Notes about valid SSI tags
- * --------------------------
- *
- * The following assumptions are made about tags used in SSI markers:
- *
- * 1. No tag may contain '-' or whitespace characters within the tag name.
- * 2. Whitespace is allowed between the tag leadin "<!--#" and the start of
- * the tag name and between the tag name and the leadout string "-->".
- * 3. The maximum tag name length is LWIP_HTTPD_MAX_TAG_NAME_LEN, currently 8 characters.
- *
- * Notes on CGI usage
- * ------------------
- *
- * The simple CGI support offered here works with GET method requests only
- * and can handle up to 16 parameters encoded into the URI. The handler
- * function may not write directly to the HTTP output but must return a
- * filename that the HTTP server will send to the browser as a response to
- * the incoming CGI request.
- *
- * @todo:
- * - don't use mem_malloc() (for SSI/dynamic headers)
- * - split too long functions into multiple smaller functions?
- * - support more file types?
- */
-#include "lwip/debug.h"
-#include "lwip/stats.h"
-#include "httpd.h"
-#include "httpd_structs.h"
-#include "lwip/tcp.h"
-#include "fs.h"
-
-#include <string.h>
-#include <stdlib.h>
-
-#if LWIP_TCP
-
-#ifndef HTTPD_DEBUG
-#define HTTPD_DEBUG LWIP_DBG_OFF
-#endif
-
-/** Set this to 1 and add the next line to lwippools.h to use a memp pool
- * for allocating struct http_state instead of the heap:
- *
- * LWIP_MEMPOOL(HTTPD_STATE, 20, 100, "HTTPD_STATE")
- */
-#ifndef HTTPD_USE_MEM_POOL
-#define HTTPD_USE_MEM_POOL 0
-#endif
-
-/** The server port for HTTPD to use */
-#ifndef HTTPD_SERVER_PORT
-#define HTTPD_SERVER_PORT 80
-#endif
-
-/** Maximum retries before the connection is aborted/closed.
- * - number of times pcb->poll is called -> default is 4*500ms = 2s;
- * - reset when pcb->sent is called
- */
-#ifndef HTTPD_MAX_RETRIES
-#define HTTPD_MAX_RETRIES 4
-#endif
-
-/** The poll delay is X*500ms */
-#ifndef HTTPD_POLL_INTERVAL
-#define HTTPD_POLL_INTERVAL 4
-#endif
-
-/** Priority for tcp pcbs created by HTTPD (very low by default).
- * Lower priorities get killed first when running out of memroy.
- */
-#ifndef HTTPD_TCP_PRIO
-#define HTTPD_TCP_PRIO TCP_PRIO_MIN
-#endif
-
-/** Set this to 1 to enabled timing each file sent */
-#ifndef LWIP_HTTPD_TIMING
-#define LWIP_HTTPD_TIMING 0
-#endif
-#ifndef HTTPD_DEBUG_TIMING
-#define HTTPD_DEBUG_TIMING LWIP_DBG_OFF
-#endif
-
-/** Set this to 1 on platforms where strnstr is not available */
-#ifndef LWIP_HTTPD_STRNSTR_PRIVATE
-#define LWIP_HTTPD_STRNSTR_PRIVATE 1
-#endif
-
-/** Set this to one to show error pages when parsing a request fails instead
- of simply closing the connection. */
-#ifndef LWIP_HTTPD_SUPPORT_EXTSTATUS
-#define LWIP_HTTPD_SUPPORT_EXTSTATUS 0
-#endif
-
-/** Set this to 0 to drop support for HTTP/0.9 clients (to save some bytes) */
-#ifndef LWIP_HTTPD_SUPPORT_V09
-#define LWIP_HTTPD_SUPPORT_V09 1
-#endif
-
-/** Set this to 1 to support HTTP request coming in in multiple packets/pbufs */
-#ifndef LWIP_HTTPD_SUPPORT_REQUESTLIST
-#define LWIP_HTTPD_SUPPORT_REQUESTLIST 0
-#endif
-
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
-/** Number of rx pbufs to enqueue to parse an incoming request (up to the first
- newline) */
-#ifndef LWIP_HTTPD_REQ_QUEUELEN
-#define LWIP_HTTPD_REQ_QUEUELEN 10
-#endif
-
-/** Number of (TCP payload-) bytes (in pbufs) to enqueue to parse and incoming
- request (up to the first double-newline) */
-#ifndef LWIP_HTTPD_REQ_BUFSIZE
-#define LWIP_HTTPD_REQ_BUFSIZE LWIP_HTTPD_MAX_REQ_LENGTH
-#endif
-
-/** Defines the maximum length of a HTTP request line (up to the first CRLF,
- copied from pbuf into this a global buffer when pbuf- or packet-queues
- are received - otherwise the input pbuf is used directly) */
-#ifndef LWIP_HTTPD_MAX_REQ_LENGTH
-#define LWIP_HTTPD_MAX_REQ_LENGTH 1023
-#endif
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
-
-/** Maximum length of the filename to send as response to a POST request,
- * filled in by the application when a POST is finished.
- */
-#ifndef LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN
-#define LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN 63
-#endif
-
-/** Set this to 0 to not send the SSI tag (default is on, so the tag will
- * be sent in the HTML page */
-#ifndef LWIP_HTTPD_SSI_INCLUDE_TAG
-#define LWIP_HTTPD_SSI_INCLUDE_TAG 1
-#endif
-
-/** Set this to 1 to call tcp_abort when tcp_close fails with memory error.
- * This can be used to prevent consuming all memory in situations where the
- * HTTP server has low priority compared to other communication. */
-#ifndef LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR
-#define LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR 0
-#endif
-
-#ifndef true
-#define true ((u8_t)1)
-#endif
-
-#ifndef false
-#define false ((u8_t)0)
-#endif
-
-/** Minimum length for a valid HTTP/0.9 request: "GET /\r\n" -> 7 bytes */
-#define MIN_REQ_LEN 7
-
-#define CRLF "\r\n"
-
-/** These defines check whether tcp_write has to copy data or not */
-
-/** This was TI's check whether to let TCP copy data or not
-#define HTTP_IS_DATA_VOLATILE(hs) ((hs->file < (char *)0x20000000) ? 0 : TCP_WRITE_FLAG_COPY)*/
-#ifndef HTTP_IS_DATA_VOLATILE
-#if LWIP_HTTPD_SSI
-/* Copy for SSI files, no copy for non-SSI files */
-#define HTTP_IS_DATA_VOLATILE(hs) ((hs)->tag_check ? TCP_WRITE_FLAG_COPY : 0)
-#else /* LWIP_HTTPD_SSI */
-/** Default: don't copy if the data is sent from file-system directly */
-#define HTTP_IS_DATA_VOLATILE(hs) (((hs->file != NULL) && (hs->handle != NULL) && (hs->file == \
- (char*)hs->handle->data + hs->handle->len - hs->left)) \
- ? 0 : TCP_WRITE_FLAG_COPY)
-#endif /* LWIP_HTTPD_SSI */
-#endif
-
-/** Default: headers are sent from ROM */
-#ifndef HTTP_IS_HDR_VOLATILE
-#define HTTP_IS_HDR_VOLATILE(hs, ptr) 0
-#endif
-
-#if LWIP_HTTPD_SSI
-/** Default: Tags are sent from struct http_state and are therefore volatile */
-#ifndef HTTP_IS_TAG_VOLATILE
-#define HTTP_IS_TAG_VOLATILE(ptr) TCP_WRITE_FLAG_COPY
-#endif
-#endif /* LWIP_HTTPD_SSI */
-
-typedef struct
-{
- const char *name;
- u8_t shtml;
-} default_filename;
-
-const default_filename g_psDefaultFilenames[] = {
- {"/index.shtml", true },
- {"/index.ssi", true },
- {"/index.shtm", true },
- {"/index.html", false },
- {"/index.htm", false }
-};
-
-#define NUM_DEFAULT_FILENAMES (sizeof(g_psDefaultFilenames) / \
- sizeof(default_filename))
-
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
-/** HTTP request is copied here from pbufs for simple parsing */
-static char httpd_req_buf[LWIP_HTTPD_MAX_REQ_LENGTH+1];
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
-
-#if LWIP_HTTPD_SUPPORT_POST
-/** Filename for response file to send when POST is finished */
-static char http_post_response_filename[LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN+1];
-#endif /* LWIP_HTTPD_SUPPORT_POST */
-
-#if LWIP_HTTPD_DYNAMIC_HEADERS
-/* The number of individual strings that comprise the headers sent before each
- * requested file.
- */
-#define NUM_FILE_HDR_STRINGS 3
-#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
-
-#if LWIP_HTTPD_SSI
-
-#define HTTPD_LAST_TAG_PART 0xFFFF
-
-const char * const g_pcSSIExtensions[] = {
- ".shtml", ".shtm", ".ssi", ".xml"
-};
-
-#define NUM_SHTML_EXTENSIONS (sizeof(g_pcSSIExtensions) / sizeof(const char *))
-
-enum tag_check_state {
- TAG_NONE, /* Not processing an SSI tag */
- TAG_LEADIN, /* Tag lead in "<!--#" being processed */
- TAG_FOUND, /* Tag name being read, looking for lead-out start */
- TAG_LEADOUT, /* Tag lead out "-->" being processed */
- TAG_SENDING /* Sending tag replacement string */
-};
-#endif /* LWIP_HTTPD_SSI */
-
-struct http_state {
- struct fs_file *handle;
- char *file; /* Pointer to first unsent byte in buf. */
-
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
- struct pbuf *req;
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
-
-#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS
- char *buf; /* File read buffer. */
- int buf_len; /* Size of file read buffer, buf. */
-#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
- u32_t left; /* Number of unsent bytes in buf. */
- u8_t retries;
-#if LWIP_HTTPD_SSI
- const char *parsed; /* Pointer to the first unparsed byte in buf. */
-#if !LWIP_HTTPD_SSI_INCLUDE_TAG
- const char *tag_started;/* Poitner to the first opening '<' of the tag. */
-#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG */
- const char *tag_end; /* Pointer to char after the closing '>' of the tag. */
- u32_t parse_left; /* Number of unparsed bytes in buf. */
- u16_t tag_index; /* Counter used by tag parsing state machine */
- u16_t tag_insert_len; /* Length of insert in string tag_insert */
-#if LWIP_HTTPD_SSI_MULTIPART
- u16_t tag_part; /* Counter passed to and changed by tag insertion function to insert multiple times */
-#endif /* LWIP_HTTPD_SSI_MULTIPART */
- u8_t tag_check; /* true if we are processing a .shtml file else false */
- u8_t tag_name_len; /* Length of the tag name in string tag_name */
- char tag_name[LWIP_HTTPD_MAX_TAG_NAME_LEN + 1]; /* Last tag name extracted */
- char tag_insert[LWIP_HTTPD_MAX_TAG_INSERT_LEN + 1]; /* Insert string for tag_name */
- enum tag_check_state tag_state; /* State of the tag processor */
-#endif /* LWIP_HTTPD_SSI */
-#if LWIP_HTTPD_CGI
- char *params[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Params extracted from the request URI */
- char *param_vals[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Values for each extracted param */
-#endif /* LWIP_HTTPD_CGI */
-#if LWIP_HTTPD_DYNAMIC_HEADERS
- const char *hdrs[NUM_FILE_HDR_STRINGS]; /* HTTP headers to be sent. */
- u16_t hdr_pos; /* The position of the first unsent header byte in the
- current string */
- u16_t hdr_index; /* The index of the hdr string currently being sent. */
-#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
-#if LWIP_HTTPD_TIMING
- u32_t time_started;
-#endif /* LWIP_HTTPD_TIMING */
-#if LWIP_HTTPD_SUPPORT_POST
- u32_t post_content_len_left;
-#if LWIP_HTTPD_POST_MANUAL_WND
- u32_t unrecved_bytes;
- struct tcp_pcb *pcb;
- u8_t no_auto_wnd;
-#endif /* LWIP_HTTPD_POST_MANUAL_WND */
-#endif /* LWIP_HTTPD_SUPPORT_POST*/
-};
-
-static err_t http_find_file(struct http_state *hs, const char *uri, int is_09);
-static err_t http_init_file(struct http_state *hs, struct fs_file *file, int is_09, const char *uri);
-static err_t http_poll(void *arg, struct tcp_pcb *pcb);
-
-#if LWIP_HTTPD_SSI
-/* SSI insert handler function pointer. */
-tSSIHandler g_pfnSSIHandler = NULL;
-int g_iNumTags = 0;
-const char **g_ppcTags = NULL;
-
-#define LEN_TAG_LEAD_IN 5
-const char * const g_pcTagLeadIn = "<!--#";
-
-#define LEN_TAG_LEAD_OUT 3
-const char * const g_pcTagLeadOut = "-->";
-#endif /* LWIP_HTTPD_SSI */
-
-#if LWIP_HTTPD_CGI
-/* CGI handler information */
-const tCGI *g_pCGIs;
-int g_iNumCGIs;
-#endif /* LWIP_HTTPD_CGI */
-
-#if LWIP_HTTPD_STRNSTR_PRIVATE
-/** Like strstr but does not need 'buffer' to be NULL-terminated */
-static char*
-strnstr(const char* buffer, const char* token, size_t n)
-{
- const char* p;
- int tokenlen = (int)strlen(token);
- if (tokenlen == 0) {
- return (char *)buffer;
- }
- for (p = buffer; *p && (p + tokenlen <= buffer + n); p++) {
- if ((*p == *token) && (strncmp(p, token, tokenlen) == 0)) {
- return (char *)p;
- }
- }
- return NULL;
-}
-#endif /* LWIP_HTTPD_STRNSTR_PRIVATE */
-
-/** Allocate a struct http_state. */
-static struct http_state*
-http_state_alloc(void)
-{
- struct http_state *ret;
-#if HTTPD_USE_MEM_POOL
- ret = (struct http_state *)memp_malloc(MEMP_HTTPD_STATE);
-#else /* HTTPD_USE_MEM_POOL */
- ret = (struct http_state *)mem_malloc(sizeof(struct http_state));
-#endif /* HTTPD_USE_MEM_POOL */
- if (ret != NULL) {
- /* Initialize the structure. */
- memset(ret, 0, sizeof(struct http_state));
-#if LWIP_HTTPD_DYNAMIC_HEADERS
- /* Indicate that the headers are not yet valid */
- ret->hdr_index = NUM_FILE_HDR_STRINGS;
-#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
- }
- return ret;
-}
-
-/** Free a struct http_state.
- * Also frees the file data if dynamic.
- */
-static void
-http_state_free(struct http_state *hs)
-{
- if (hs != NULL) {
- if(hs->handle) {
-#if LWIP_HTTPD_TIMING
- u32_t ms_needed = sys_now() - hs->time_started;
- u32_t needed = LWIP_MAX(1, (ms_needed/100));
- LWIP_DEBUGF(HTTPD_DEBUG_TIMING, ("httpd: needed %"U32_F" ms to send file of %d bytes -> %"U32_F" bytes/sec\n",
- ms_needed, hs->handle->len, ((((u32_t)hs->handle->len) * 10) / needed)));
-#endif /* LWIP_HTTPD_TIMING */
- fs_close(hs->handle);
- hs->handle = NULL;
- }
-#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS
- if (hs->buf != NULL) {
- mem_free(hs->buf);
- hs->buf = NULL;
- }
-#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
-#if HTTPD_USE_MEM_POOL
- memp_free(MEMP_HTTPD_STATE, hs);
-#else /* HTTPD_USE_MEM_POOL */
- mem_free(hs);
-#endif /* HTTPD_USE_MEM_POOL */
- }
-}
-
-/** Call tcp_write() in a loop trying smaller and smaller length
- *
- * @param pcb tcp_pcb to send
- * @param ptr Data to send
- * @param length Length of data to send (in/out: on return, contains the
- * amount of data sent)
- * @param apiflags directly passed to tcp_write
- * @return the return value of tcp_write
- */
-static err_t
-http_write(struct tcp_pcb *pcb, const void* ptr, u16_t *length, u8_t apiflags)
-{
- u16_t len;
- err_t err;
- LWIP_ASSERT("length != NULL", length != NULL);
- len = *length;
- do {
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Trying go send %d bytes\n", len));
- err = tcp_write(pcb, ptr, len, apiflags);
- if (err == ERR_MEM) {
- if ((tcp_sndbuf(pcb) == 0) ||
- (tcp_sndqueuelen(pcb) >= TCP_SND_QUEUELEN)) {
- /* no need to try smaller sizes */
- len = 1;
- } else {
- len /= 2;
- }
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE,
- ("Send failed, trying less (%d bytes)\n", len));
- }
- } while ((err == ERR_MEM) && (len > 1));
-
- if (err == ERR_OK) {
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Sent %d bytes\n", len));
- } else {
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Send failed with err %d (\"%s\")\n", err, lwip_strerr(err)));
- }
-
- *length = len;
- return err;
-}
-
-/**
- * The connection shall be actively closed.
- * Reset the sent- and recv-callbacks.
- *
- * @param pcb the tcp pcb to reset callbacks
- * @param hs connection state to free
- */
-static err_t
-http_close_conn(struct tcp_pcb *pcb, struct http_state *hs)
-{
- err_t err;
- LWIP_DEBUGF(HTTPD_DEBUG, ("Closing connection %p\n", (void*)pcb));
-
-#if LWIP_HTTPD_SUPPORT_POST
- if (hs != NULL) {
- if ((hs->post_content_len_left != 0)
-#if LWIP_HTTPD_POST_MANUAL_WND
- || ((hs->no_auto_wnd != 0) && (hs->unrecved_bytes != 0))
-#endif /* LWIP_HTTPD_POST_MANUAL_WND */
- ) {
- /* make sure the post code knows that the connection is closed */
- http_post_response_filename[0] = 0;
- httpd_post_finished(hs, http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN);
- }
- }
-#endif /* LWIP_HTTPD_SUPPORT_POST*/
-
-
- tcp_arg(pcb, NULL);
- tcp_recv(pcb, NULL);
- tcp_err(pcb, NULL);
- tcp_poll(pcb, NULL, 0);
- tcp_sent(pcb, NULL);
- if(hs != NULL) {
- http_state_free(hs);
- }
-
- err = tcp_close(pcb);
- if (err != ERR_OK) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("Error %d closing %p\n", err, (void*)pcb));
- /* error closing, try again later in poll */
- tcp_poll(pcb, http_poll, HTTPD_POLL_INTERVAL);
- }
- return err;
-}
-#if LWIP_HTTPD_CGI
-/**
- * Extract URI parameters from the parameter-part of an URI in the form
- * "test.cgi?x=y" @todo: better explanation!
- * Pointers to the parameters are stored in hs->param_vals.
- *
- * @param hs http connection state
- * @param params pointer to the NULL-terminated parameter string from the URI
- * @return number of parameters extracted
- */
-static int
-extract_uri_parameters(struct http_state *hs, char *params)
-{
- char *pair;
- char *equals;
- int loop;
-
- /* If we have no parameters at all, return immediately. */
- if(!params || (params[0] == '\0')) {
- return(0);
- }
-
- /* Get a pointer to our first parameter */
- pair = params;
-
- /* Parse up to LWIP_HTTPD_MAX_CGI_PARAMETERS from the passed string and ignore the
- * remainder (if any) */
- for(loop = 0; (loop < LWIP_HTTPD_MAX_CGI_PARAMETERS) && pair; loop++) {
-
- /* Save the name of the parameter */
- hs->params[loop] = pair;
-
- /* Remember the start of this name=value pair */
- equals = pair;
-
- /* Find the start of the next name=value pair and replace the delimiter
- * with a 0 to terminate the previous pair string. */
- pair = strchr(pair, '&');
- if(pair) {
- *pair = '\0';
- pair++;
- } else {
- /* We didn't find a new parameter so find the end of the URI and
- * replace the space with a '\0' */
- pair = strchr(equals, ' ');
- if(pair) {
- *pair = '\0';
- }
-
- /* Revert to NULL so that we exit the loop as expected. */
- pair = NULL;
- }
-
- /* Now find the '=' in the previous pair, replace it with '\0' and save
- * the parameter value string. */
- equals = strchr(equals, '=');
- if(equals) {
- *equals = '\0';
- hs->param_vals[loop] = equals + 1;
- } else {
- hs->param_vals[loop] = NULL;
- }
- }
-
- return loop;
-}
-#endif /* LWIP_HTTPD_CGI */
-
-#if LWIP_HTTPD_SSI
-/**
- * Insert a tag (found in an shtml in the form of "<!--#tagname-->" into the file.
- * The tag's name is stored in hs->tag_name (NULL-terminated), the replacement
- * should be written to hs->tag_insert (up to a length of LWIP_HTTPD_MAX_TAG_INSERT_LEN).
- * The amount of data written is stored to hs->tag_insert_len.
- *
- * @todo: return tag_insert_len - maybe it can be removed from struct http_state?
- *
- * @param hs http connection state
- */
-static void
-get_tag_insert(struct http_state *hs)
-{
- int loop;
- size_t len;
-#if LWIP_HTTPD_SSI_MULTIPART
- u16_t current_tag_part = hs->tag_part;
- hs->tag_part = HTTPD_LAST_TAG_PART;
-#endif /* LWIP_HTTPD_SSI_MULTIPART */
-
- if(g_pfnSSIHandler && g_ppcTags && g_iNumTags) {
-
- /* Find this tag in the list we have been provided. */
- for(loop = 0; loop < g_iNumTags; loop++) {
- if(strcmp(hs->tag_name, g_ppcTags[loop]) == 0) {
- hs->tag_insert_len = g_pfnSSIHandler(loop, hs->tag_insert,
- LWIP_HTTPD_MAX_TAG_INSERT_LEN
-#if LWIP_HTTPD_SSI_MULTIPART
- , current_tag_part, &hs->tag_part
-#endif /* LWIP_HTTPD_SSI_MULTIPART */
-#if LWIP_HTTPD_FILE_STATE
- , hs->handle->state
-#endif /* LWIP_HTTPD_FILE_STATE */
- );
- return;
- }
- }
- }
-
- /* If we drop out, we were asked to serve a page which contains tags that
- * we don't have a handler for. Merely echo back the tags with an error
- * marker. */
-#define UNKNOWN_TAG1_TEXT "<b>***UNKNOWN TAG "
-#define UNKNOWN_TAG1_LEN 18
-#define UNKNOWN_TAG2_TEXT "***</b>"
-#define UNKNOWN_TAG2_LEN 7
- len = LWIP_MIN(strlen(hs->tag_name),
- LWIP_HTTPD_MAX_TAG_INSERT_LEN - (UNKNOWN_TAG1_LEN + UNKNOWN_TAG2_LEN));
- MEMCPY(hs->tag_insert, UNKNOWN_TAG1_TEXT, UNKNOWN_TAG1_LEN);
- MEMCPY(&hs->tag_insert[UNKNOWN_TAG1_LEN], hs->tag_name, len);
- MEMCPY(&hs->tag_insert[UNKNOWN_TAG1_LEN + len], UNKNOWN_TAG2_TEXT, UNKNOWN_TAG2_LEN);
- hs->tag_insert[UNKNOWN_TAG1_LEN + len + UNKNOWN_TAG2_LEN] = 0;
-
- len = strlen(hs->tag_insert);
- LWIP_ASSERT("len <= 0xffff", len <= 0xffff);
- hs->tag_insert_len = (u16_t)len;
-}
-#endif /* LWIP_HTTPD_SSI */
-
-#if LWIP_HTTPD_DYNAMIC_HEADERS
-/**
- * Generate the relevant HTTP headers for the given filename and write
- * them into the supplied buffer.
- */
-static void
-get_http_headers(struct http_state *pState, char *pszURI)
-{
- unsigned int iLoop;
- char *pszWork;
- char *pszExt;
- char *pszVars;
-
- /* Ensure that we initialize the loop counter. */
- iLoop = 0;
-
- /* In all cases, the second header we send is the server identification
- so set it here. */
- pState->hdrs[1] = g_psHTTPHeaderStrings[HTTP_HDR_SERVER];
-
- /* Is this a normal file or the special case we use to send back the
- default "404: Page not found" response? */
- if (pszURI == NULL) {
- pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_FOUND];
- pState->hdrs[2] = g_psHTTPHeaderStrings[DEFAULT_404_HTML];
-
- /* Set up to send the first header string. */
- pState->hdr_index = 0;
- pState->hdr_pos = 0;
- return;
- } else {
- /* We are dealing with a particular filename. Look for one other
- special case. We assume that any filename with "404" in it must be
- indicative of a 404 server error whereas all other files require
- the 200 OK header. */
- if (strstr(pszURI, "404")) {
- pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_FOUND];
- } else if (strstr(pszURI, "400")) {
- pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_BAD_REQUEST];
- } else if (strstr(pszURI, "501")) {
- pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_IMPL];
- } else {
- pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_OK];
- }
-
- /* Determine if the URI has any variables and, if so, temporarily remove
- them. */
- pszVars = strchr(pszURI, '?');
- if(pszVars) {
- *pszVars = '\0';
- }
-
- /* Get a pointer to the file extension. We find this by looking for the
- last occurrence of "." in the filename passed. */
- pszExt = NULL;
- pszWork = strchr(pszURI, '.');
- while(pszWork) {
- pszExt = pszWork + 1;
- pszWork = strchr(pszExt, '.');
- }
-
- /* Now determine the content type and add the relevant header for that. */
- for(iLoop = 0; (iLoop < NUM_HTTP_HEADERS) && pszExt; iLoop++) {
- /* Have we found a matching extension? */
- if(!strcmp(g_psHTTPHeaders[iLoop].extension, pszExt)) {
- pState->hdrs[2] =
- g_psHTTPHeaderStrings[g_psHTTPHeaders[iLoop].headerIndex];
- break;
- }
- }
-
- /* Reinstate the parameter marker if there was one in the original URI. */
- if(pszVars) {
- *pszVars = '?';
- }
- }
-
- /* Does the URL passed have any file extension? If not, we assume it
- is a special-case URL used for control state notification and we do
- not send any HTTP headers with the response. */
- if(!pszExt) {
- /* Force the header index to a value indicating that all headers
- have already been sent. */
- pState->hdr_index = NUM_FILE_HDR_STRINGS;
- } else {
- /* Did we find a matching extension? */
- if(iLoop == NUM_HTTP_HEADERS) {
- /* No - use the default, plain text file type. */
- pState->hdrs[2] = g_psHTTPHeaderStrings[HTTP_HDR_DEFAULT_TYPE];
- }
-
- /* Set up to send the first header string. */
- pState->hdr_index = 0;
- pState->hdr_pos = 0;
- }
-}
-#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
-
-/**
- * Try to send more data on this pcb.
- *
- * @param pcb the pcb to send data
- * @param hs connection state
- */
-static u8_t
-http_send_data(struct tcp_pcb *pcb, struct http_state *hs)
-{
- err_t err;
- u16_t len;
- u16_t mss;
- u8_t data_to_send = false;
-#if LWIP_HTTPD_DYNAMIC_HEADERS
- u16_t hdrlen, sendlen;
-#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
-
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_send_data: pcb=%p hs=%p left=%d\n", (void*)pcb,
- (void*)hs, hs != NULL ? hs->left : 0));
-
-#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND
- if (hs->unrecved_bytes != 0) {
- return 0;
- }
-#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */
-
-#if LWIP_HTTPD_DYNAMIC_HEADERS
- /* If we were passed a NULL state structure pointer, ignore the call. */
- if (hs == NULL) {
- return 0;
- }
-
- /* Assume no error until we find otherwise */
- err = ERR_OK;
-
- /* Do we have any more header data to send for this file? */
- if(hs->hdr_index < NUM_FILE_HDR_STRINGS) {
- /* How much data can we send? */
- len = tcp_sndbuf(pcb);
- sendlen = len;
-
- while(len && (hs->hdr_index < NUM_FILE_HDR_STRINGS) && sendlen) {
- const void *ptr;
- u16_t old_sendlen;
- /* How much do we have to send from the current header? */
- hdrlen = (u16_t)strlen(hs->hdrs[hs->hdr_index]);
-
- /* How much of this can we send? */
- sendlen = (len < (hdrlen - hs->hdr_pos)) ? len : (hdrlen - hs->hdr_pos);
-
- /* Send this amount of data or as much as we can given memory
- * constraints. */
- ptr = (const void *)(hs->hdrs[hs->hdr_index] + hs->hdr_pos);
- old_sendlen = sendlen;
- err = http_write(pcb, ptr, &sendlen, HTTP_IS_HDR_VOLATILE(hs, ptr));
- if ((err == ERR_OK) && (old_sendlen != sendlen)) {
- /* Remember that we added some more data to be transmitted. */
- data_to_send = true;
- } else if (err != ERR_OK) {
- /* special case: http_write does not try to send 1 byte */
- sendlen = 0;
- }
-
- /* Fix up the header position for the next time round. */
- hs->hdr_pos += sendlen;
- len -= sendlen;
-
- /* Have we finished sending this string? */
- if(hs->hdr_pos == hdrlen) {
- /* Yes - move on to the next one */
- hs->hdr_index++;
- hs->hdr_pos = 0;
- }
- }
-
- /* If we get here and there are still header bytes to send, we send
- * the header information we just wrote immediately. If there are no
- * more headers to send, but we do have file data to send, drop through
- * to try to send some file data too. */
- if((hs->hdr_index < NUM_FILE_HDR_STRINGS) || !hs->file) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_output\n"));
- return 1;
- }
- }
-#else /* LWIP_HTTPD_DYNAMIC_HEADERS */
- /* Assume no error until we find otherwise */
- err = ERR_OK;
-#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
-
- /* Have we run out of file data to send? If so, we need to read the next
- * block from the file. */
- if (hs->left == 0) {
-#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS
- int count;
-#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
-
- /* Do we have a valid file handle? */
- if (hs->handle == NULL) {
- /* No - close the connection. */
- http_close_conn(pcb, hs);
- return 0;
- }
- if (fs_bytes_left(hs->handle) <= 0) {
- /* We reached the end of the file so this request is done.
- * @todo: don't close here for HTTP/1.1? */
- LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n"));
- http_close_conn(pcb, hs);
- return 0;
- }
-#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS
- /* Do we already have a send buffer allocated? */
- if(hs->buf) {
- /* Yes - get the length of the buffer */
- count = hs->buf_len;
- } else {
- /* We don't have a send buffer so allocate one up to 2mss bytes long. */
- count = 2 * tcp_mss(pcb);
- do {
- hs->buf = (char*)mem_malloc((mem_size_t)count);
- if (hs->buf != NULL) {
- hs->buf_len = count;
- break;
- }
- count = count / 2;
- } while (count > 100);
-
- /* Did we get a send buffer? If not, return immediately. */
- if (hs->buf == NULL) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("No buff\n"));
- return 0;
- }
- }
-
- /* Read a block of data from the file. */
- LWIP_DEBUGF(HTTPD_DEBUG, ("Trying to read %d bytes.\n", count));
-
- count = fs_read(hs->handle, hs->buf, count);
- if(count < 0) {
- /* We reached the end of the file so this request is done.
- * @todo: don't close here for HTTP/1.1? */
- LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n"));
- http_close_conn(pcb, hs);
- return 1;
- }
-
- /* Set up to send the block of data we just read */
- LWIP_DEBUGF(HTTPD_DEBUG, ("Read %d bytes.\n", count));
- hs->left = count;
- hs->file = hs->buf;
-#if LWIP_HTTPD_SSI
- hs->parse_left = count;
- hs->parsed = hs->buf;
-#endif /* LWIP_HTTPD_SSI */
-#else /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
- LWIP_ASSERT("SSI and DYNAMIC_HEADERS turned off but eof not reached", 0);
-#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
- }
-
-#if LWIP_HTTPD_SSI
- if(!hs->tag_check) {
-#endif /* LWIP_HTTPD_SSI */
- /* We are not processing an SHTML file so no tag checking is necessary.
- * Just send the data as we received it from the file. */
-
- /* We cannot send more data than space available in the send
- buffer. */
- if (tcp_sndbuf(pcb) < hs->left) {
- len = tcp_sndbuf(pcb);
- } else {
- len = (u16_t)hs->left;
- LWIP_ASSERT("hs->left did not fit into u16_t!", (len == hs->left));
- }
- mss = tcp_mss(pcb);
- if(len > (2 * mss)) {
- len = 2 * mss;
- }
-
- err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
- if (err == ERR_OK) {
- data_to_send = true;
- hs->file += len;
- hs->left -= len;
- }
-#if LWIP_HTTPD_SSI
- } else {
- /* We are processing an SHTML file so need to scan for tags and replace
- * them with insert strings. We need to be careful here since a tag may
- * straddle the boundary of two blocks read from the file and we may also
- * have to split the insert string between two tcp_write operations. */
-
- /* How much data could we send? */
- len = tcp_sndbuf(pcb);
-
- /* Do we have remaining data to send before parsing more? */
- if(hs->parsed > hs->file) {
- /* We cannot send more data than space available in the send
- buffer. */
- if (tcp_sndbuf(pcb) < (hs->parsed - hs->file)) {
- len = tcp_sndbuf(pcb);
- } else {
- LWIP_ASSERT("Data size does not fit into u16_t!",
- (hs->parsed - hs->file) <= 0xffff);
- len = (u16_t)(hs->parsed - hs->file);
- }
- mss = tcp_mss(pcb);
- if(len > (2 * mss)) {
- len = 2 * mss;
- }
-
- err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
- if (err == ERR_OK) {
- data_to_send = true;
- hs->file += len;
- hs->left -= len;
- }
-
- /* If the send buffer is full, return now. */
- if(tcp_sndbuf(pcb) == 0) {
- return data_to_send;
- }
- }
-
- LWIP_DEBUGF(HTTPD_DEBUG, ("State %d, %d left\n", hs->tag_state, hs->parse_left));
-
- /* We have sent all the data that was already parsed so continue parsing
- * the buffer contents looking for SSI tags. */
- while((hs->parse_left) && (err == ERR_OK)) {
- /* @todo: somewhere in this loop, 'len' should grow again... */
- if (len == 0) {
- return data_to_send;
- }
- switch(hs->tag_state) {
- case TAG_NONE:
- /* We are not currently processing an SSI tag so scan for the
- * start of the lead-in marker. */
- if(*hs->parsed == g_pcTagLeadIn[0]) {
- /* We found what could be the lead-in for a new tag so change
- * state appropriately. */
- hs->tag_state = TAG_LEADIN;
- hs->tag_index = 1;
-#if !LWIP_HTTPD_SSI_INCLUDE_TAG
- hs->tag_started = hs->parsed;
-#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG */
- }
-
- /* Move on to the next character in the buffer */
- hs->parse_left--;
- hs->parsed++;
- break;
-
- case TAG_LEADIN:
- /* We are processing the lead-in marker, looking for the start of
- * the tag name. */
-
- /* Have we reached the end of the leadin? */
- if(hs->tag_index == LEN_TAG_LEAD_IN) {
- hs->tag_index = 0;
- hs->tag_state = TAG_FOUND;
- } else {
- /* Have we found the next character we expect for the tag leadin? */
- if(*hs->parsed == g_pcTagLeadIn[hs->tag_index]) {
- /* Yes - move to the next one unless we have found the complete
- * leadin, in which case we start looking for the tag itself */
- hs->tag_index++;
- } else {
- /* We found an unexpected character so this is not a tag. Move
- * back to idle state. */
- hs->tag_state = TAG_NONE;
- }
-
- /* Move on to the next character in the buffer */
- hs->parse_left--;
- hs->parsed++;
- }
- break;
-
- case TAG_FOUND:
- /* We are reading the tag name, looking for the start of the
- * lead-out marker and removing any whitespace found. */
-
- /* Remove leading whitespace between the tag leading and the first
- * tag name character. */
- if((hs->tag_index == 0) && ((*hs->parsed == ' ') ||
- (*hs->parsed == '\t') || (*hs->parsed == '\n') ||
- (*hs->parsed == '\r'))) {
- /* Move on to the next character in the buffer */
- hs->parse_left--;
- hs->parsed++;
- break;
- }
-
- /* Have we found the end of the tag name? This is signalled by
- * us finding the first leadout character or whitespace */
- if((*hs->parsed == g_pcTagLeadOut[0]) ||
- (*hs->parsed == ' ') || (*hs->parsed == '\t') ||
- (*hs->parsed == '\n') || (*hs->parsed == '\r')) {
-
- if(hs->tag_index == 0) {
- /* We read a zero length tag so ignore it. */
- hs->tag_state = TAG_NONE;
- } else {
- /* We read a non-empty tag so go ahead and look for the
- * leadout string. */
- hs->tag_state = TAG_LEADOUT;
- LWIP_ASSERT("hs->tag_index <= 0xff", hs->tag_index <= 0xff);
- hs->tag_name_len = (u8_t)hs->tag_index;
- hs->tag_name[hs->tag_index] = '\0';
- if(*hs->parsed == g_pcTagLeadOut[0]) {
- hs->tag_index = 1;
- } else {
- hs->tag_index = 0;
- }
- }
- } else {
- /* This character is part of the tag name so save it */
- if(hs->tag_index < LWIP_HTTPD_MAX_TAG_NAME_LEN) {
- hs->tag_name[hs->tag_index++] = *hs->parsed;
- } else {
- /* The tag was too long so ignore it. */
- hs->tag_state = TAG_NONE;
- }
- }
-
- /* Move on to the next character in the buffer */
- hs->parse_left--;
- hs->parsed++;
-
- break;
-
- /* We are looking for the end of the lead-out marker. */
- case TAG_LEADOUT:
- /* Remove leading whitespace between the tag leading and the first
- * tag leadout character. */
- if((hs->tag_index == 0) && ((*hs->parsed == ' ') ||
- (*hs->parsed == '\t') || (*hs->parsed == '\n') ||
- (*hs->parsed == '\r'))) {
- /* Move on to the next character in the buffer */
- hs->parse_left--;
- hs->parsed++;
- break;
- }
-
- /* Have we found the next character we expect for the tag leadout? */
- if(*hs->parsed == g_pcTagLeadOut[hs->tag_index]) {
- /* Yes - move to the next one unless we have found the complete
- * leadout, in which case we need to call the client to process
- * the tag. */
-
- /* Move on to the next character in the buffer */
- hs->parse_left--;
- hs->parsed++;
-
- if(hs->tag_index == (LEN_TAG_LEAD_OUT - 1)) {
- /* Call the client to ask for the insert string for the
- * tag we just found. */
-#if LWIP_HTTPD_SSI_MULTIPART
- hs->tag_part = 0; /* start with tag part 0 */
-#endif /* LWIP_HTTPD_SSI_MULTIPART */
- get_tag_insert(hs);
-
- /* Next time through, we are going to be sending data
- * immediately, either the end of the block we start
- * sending here or the insert string. */
- hs->tag_index = 0;
- hs->tag_state = TAG_SENDING;
- hs->tag_end = hs->parsed;
-#if !LWIP_HTTPD_SSI_INCLUDE_TAG
- hs->parsed = hs->tag_started;
-#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/
-
- /* If there is any unsent data in the buffer prior to the
- * tag, we need to send it now. */
- if (hs->tag_end > hs->file) {
- /* How much of the data can we send? */
-#if LWIP_HTTPD_SSI_INCLUDE_TAG
- if(len > hs->tag_end - hs->file) {
- len = (u16_t)(hs->tag_end - hs->file);
- }
-#else /* LWIP_HTTPD_SSI_INCLUDE_TAG*/
- if(len > hs->tag_started - hs->file) {
- /* we would include the tag in sending */
- len = (u16_t)(hs->tag_started - hs->file);
- }
-#endif /* LWIP_HTTPD_SSI_INCLUDE_TAG*/
-
- err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
- if (err == ERR_OK) {
- data_to_send = true;
-#if !LWIP_HTTPD_SSI_INCLUDE_TAG
- if(hs->tag_started <= hs->file) {
- /* pretend to have sent the tag, too */
- len += hs->tag_end - hs->tag_started;
- }
-#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/
- hs->file += len;
- hs->left -= len;
- }
- }
- } else {
- hs->tag_index++;
- }
- } else {
- /* We found an unexpected character so this is not a tag. Move
- * back to idle state. */
- hs->parse_left--;
- hs->parsed++;
- hs->tag_state = TAG_NONE;
- }
- break;
-
- /*
- * We have found a valid tag and are in the process of sending
- * data as a result of that discovery. We send either remaining data
- * from the file prior to the insert point or the insert string itself.
- */
- case TAG_SENDING:
- /* Do we have any remaining file data to send from the buffer prior
- * to the tag? */
- if(hs->tag_end > hs->file) {
- /* How much of the data can we send? */
-#if LWIP_HTTPD_SSI_INCLUDE_TAG
- if(len > hs->tag_end - hs->file) {
- len = (u16_t)(hs->tag_end - hs->file);
- }
-#else /* LWIP_HTTPD_SSI_INCLUDE_TAG*/
- LWIP_ASSERT("hs->started >= hs->file", hs->tag_started >= hs->file);
- if (len > hs->tag_started - hs->file) {
- /* we would include the tag in sending */
- len = (u16_t)(hs->tag_started - hs->file);
- }
-#endif /* LWIP_HTTPD_SSI_INCLUDE_TAG*/
- if (len != 0) {
- err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
- } else {
- err = ERR_OK;
- }
- if (err == ERR_OK) {
- data_to_send = true;
-#if !LWIP_HTTPD_SSI_INCLUDE_TAG
- if(hs->tag_started <= hs->file) {
- /* pretend to have sent the tag, too */
- len += hs->tag_end - hs->tag_started;
- }
-#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/
- hs->file += len;
- hs->left -= len;
- }
- } else {
-#if LWIP_HTTPD_SSI_MULTIPART
- if(hs->tag_index >= hs->tag_insert_len) {
- /* Did the last SSIHandler have more to send? */
- if (hs->tag_part != HTTPD_LAST_TAG_PART) {
- /* If so, call it again */
- hs->tag_index = 0;
- get_tag_insert(hs);
- }
- }
-#endif /* LWIP_HTTPD_SSI_MULTIPART */
-
- /* Do we still have insert data left to send? */
- if(hs->tag_index < hs->tag_insert_len) {
- /* We are sending the insert string itself. How much of the
- * insert can we send? */
- if(len > (hs->tag_insert_len - hs->tag_index)) {
- len = (hs->tag_insert_len - hs->tag_index);
- }
-
- /* Note that we set the copy flag here since we only have a
- * single tag insert buffer per connection. If we don't do
- * this, insert corruption can occur if more than one insert
- * is processed before we call tcp_output. */
- err = http_write(pcb, &(hs->tag_insert[hs->tag_index]), &len,
- HTTP_IS_TAG_VOLATILE(hs));
- if (err == ERR_OK) {
- data_to_send = true;
- hs->tag_index += len;
- /* Don't return here: keep on sending data */
- }
- } else {
- /* We have sent all the insert data so go back to looking for
- * a new tag. */
- LWIP_DEBUGF(HTTPD_DEBUG, ("Everything sent.\n"));
- hs->tag_index = 0;
- hs->tag_state = TAG_NONE;
-#if !LWIP_HTTPD_SSI_INCLUDE_TAG
- hs->parsed = hs->tag_end;
-#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/
- }
- break;
- }
- }
- }
-
- /* If we drop out of the end of the for loop, this implies we must have
- * file data to send so send it now. In TAG_SENDING state, we've already
- * handled this so skip the send if that's the case. */
- if((hs->tag_state != TAG_SENDING) && (hs->parsed > hs->file)) {
- /* We cannot send more data than space available in the send
- buffer. */
- if (tcp_sndbuf(pcb) < (hs->parsed - hs->file)) {
- len = tcp_sndbuf(pcb);
- } else {
- LWIP_ASSERT("Data size does not fit into u16_t!",
- (hs->parsed - hs->file) <= 0xffff);
- len = (u16_t)(hs->parsed - hs->file);
- }
- if(len > (2 * tcp_mss(pcb))) {
- len = 2 * tcp_mss(pcb);
- }
-
- err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
- if (err == ERR_OK) {
- data_to_send = true;
- hs->file += len;
- hs->left -= len;
- }
- }
- }
-#endif /* LWIP_HTTPD_SSI */
-
- if((hs->left == 0) && (fs_bytes_left(hs->handle) <= 0)) {
- /* We reached the end of the file so this request is done.
- * This adds the FIN flag right into the last data segment.
- * @todo: don't close here for HTTP/1.1? */
- LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n"));
- http_close_conn(pcb, hs);
- return 0;
- }
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("send_data end.\n"));
- return data_to_send;
-}
-
-#if LWIP_HTTPD_SUPPORT_EXTSTATUS
-/** Initialize a http connection with a file to send for an error message
- *
- * @param hs http connection state
- * @param error_nr HTTP error number
- * @return ERR_OK if file was found and hs has been initialized correctly
- * another err_t otherwise
- */
-static err_t
-http_find_error_file(struct http_state *hs, u16_t error_nr)
-{
- const char *uri1, *uri2, *uri3;
- struct fs_file *file;
-
- if (error_nr == 501) {
- uri1 = "/501.html";
- uri2 = "/501.htm";
- uri3 = "/501.shtml";
- } else {
- /* 400 (bad request is the default) */
- uri1 = "/400.html";
- uri2 = "/400.htm";
- uri3 = "/400.shtml";
- }
- file = fs_open(uri1);
- if (file == NULL) {
- file = fs_open(uri2);
- if (file == NULL) {
- file = fs_open(uri3);
- if (file == NULL) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("Error page for error %"U16_F" not found\n",
- error_nr));
- return ERR_ARG;
- }
- }
- }
- return http_init_file(hs, file, 0, NULL);
-}
-#else /* LWIP_HTTPD_SUPPORT_EXTSTATUS */
-#define http_find_error_file(hs, error_nr) ERR_ARG
-#endif /* LWIP_HTTPD_SUPPORT_EXTSTATUS */
-
-/**
- * Get the file struct for a 404 error page.
- * Tries some file names and returns NULL if none found.
- *
- * @param uri pointer that receives the actual file name URI
- * @return file struct for the error page or NULL no matching file was found
- */
-static struct fs_file *
-http_get_404_file(const char **uri)
-{
- struct fs_file *file;
-
- *uri = "/404.html";
- file = fs_open(*uri);
- if(file == NULL) {
- /* 404.html doesn't exist. Try 404.htm instead. */
- *uri = "/404.htm";
- file = fs_open(*uri);
- if(file == NULL) {
- /* 404.htm doesn't exist either. Try 404.shtml instead. */
- *uri = "/404.shtml";
- file = fs_open(*uri);
- if(file == NULL) {
- /* 404.htm doesn't exist either. Indicate to the caller that it should
- * send back a default 404 page.
- */
- *uri = NULL;
- }
- }
- }
-
- return file;
-}
-
-#if LWIP_HTTPD_SUPPORT_POST
-static err_t
-http_handle_post_finished(struct http_state *hs)
-{
- /* application error or POST finished */
- /* NULL-terminate the buffer */
- http_post_response_filename[0] = 0;
- httpd_post_finished(hs, http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN);
- return http_find_file(hs, http_post_response_filename, 0);
-}
-
-/** Pass received POST body data to the application and correctly handle
- * returning a response document or closing the connection.
- * ATTENTION: The application is responsible for the pbuf now, so don't free it!
- *
- * @param hs http connection state
- * @param p pbuf to pass to the application
- * @return ERR_OK if passed successfully, another err_t if the response file
- * hasn't been found (after POST finished)
- */
-static err_t
-http_post_rxpbuf(struct http_state *hs, struct pbuf *p)
-{
- err_t err;
-
- /* adjust remaining Content-Length */
- if (hs->post_content_len_left < p->tot_len) {
- hs->post_content_len_left = 0;
- } else {
- hs->post_content_len_left -= p->tot_len;
- }
- err = httpd_post_receive_data(hs, p);
- if ((err != ERR_OK) || (hs->post_content_len_left == 0)) {
-#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND
- if (hs->unrecved_bytes != 0) {
- return ERR_OK;
- }
-#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */
- /* application error or POST finished */
- return http_handle_post_finished(hs);
- }
-
- return ERR_OK;
-}
-
-/** Handle a post request. Called from http_parse_request when method 'POST'
- * is found.
- *
- * @param pcb The tcp_pcb which received this packet.
- * @param p The input pbuf (containing the POST header and body).
- * @param hs The http connection state.
- * @param data HTTP request (header and part of body) from input pbuf(s).
- * @param data_len Size of 'data'.
- * @param uri The HTTP URI parsed from input pbuf(s).
- * @param uri_end Pointer to the end of 'uri' (here, the rest of the HTTP
- * header starts).
- * @return ERR_OK: POST correctly parsed and accepted by the application.
- * ERR_INPROGRESS: POST not completely parsed (no error yet)
- * another err_t: Error parsing POST or denied by the application
- */
-static err_t
-http_post_request(struct tcp_pcb *pcb, struct pbuf **inp, struct http_state *hs,
- char *data, u16_t data_len, char *uri, char *uri_end)
-{
- err_t err;
- /* search for end-of-header (first double-CRLF) */
- char* crlfcrlf = strnstr(uri_end + 1, CRLF CRLF, data_len - (uri_end + 1 - data));
-
-#if LWIP_HTTPD_POST_MANUAL_WND
- hs->pcb = pcb;
-#else /* LWIP_HTTPD_POST_MANUAL_WND */
- LWIP_UNUSED_ARG(pcb); /* only used for LWIP_HTTPD_POST_MANUAL_WND */
-#endif /* LWIP_HTTPD_POST_MANUAL_WND */
-
- if (crlfcrlf != NULL) {
- /* search for "Content-Length: " */
-#define HTTP_HDR_CONTENT_LEN "Content-Length: "
-#define HTTP_HDR_CONTENT_LEN_LEN 16
-#define HTTP_HDR_CONTENT_LEN_DIGIT_MAX_LEN 10
- char *scontent_len = strnstr(uri_end + 1, HTTP_HDR_CONTENT_LEN, crlfcrlf - (uri_end + 1));
- if (scontent_len != NULL) {
- char *scontent_len_end = strnstr(scontent_len + HTTP_HDR_CONTENT_LEN_LEN, CRLF, HTTP_HDR_CONTENT_LEN_DIGIT_MAX_LEN);
- if (scontent_len_end != NULL) {
- int content_len;
- char *conten_len_num = scontent_len + HTTP_HDR_CONTENT_LEN_LEN;
- *scontent_len_end = 0;
- content_len = atoi(conten_len_num);
- if (content_len > 0) {
- /* adjust length of HTTP header passed to application */
- const char *hdr_start_after_uri = uri_end + 1;
- u16_t hdr_len = LWIP_MIN(data_len, crlfcrlf + 4 - data);
- u16_t hdr_data_len = LWIP_MIN(data_len, crlfcrlf + 4 - hdr_start_after_uri);
- u8_t post_auto_wnd = 1;
- http_post_response_filename[0] = 0;
- err = httpd_post_begin(hs, uri, hdr_start_after_uri, hdr_data_len, content_len,
- http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN, &post_auto_wnd);
- if (err == ERR_OK) {
- /* try to pass in data of the first pbuf(s) */
- struct pbuf *q = *inp;
- u16_t start_offset = hdr_len;
-#if LWIP_HTTPD_POST_MANUAL_WND
- hs->no_auto_wnd = !post_auto_wnd;
-#endif /* LWIP_HTTPD_POST_MANUAL_WND */
- /* set the Content-Length to be received for this POST */
- hs->post_content_len_left = (u32_t)content_len;
-
- /* get to the pbuf where the body starts */
- while((q != NULL) && (q->len <= start_offset)) {
- struct pbuf *head = q;
- start_offset -= q->len;
- q = q->next;
- /* free the head pbuf */
- head->next = NULL;
- pbuf_free(head);
- }
- *inp = NULL;
- if (q != NULL) {
- /* hide the remaining HTTP header */
- pbuf_header(q, -(s16_t)start_offset);
-#if LWIP_HTTPD_POST_MANUAL_WND
- if (!post_auto_wnd) {
- /* already tcp_recved() this data... */
- hs->unrecved_bytes = q->tot_len;
- }
-#endif /* LWIP_HTTPD_POST_MANUAL_WND */
- return http_post_rxpbuf(hs, q);
- } else {
- return ERR_OK;
- }
- } else {
- /* return file passed from application */
- return http_find_file(hs, http_post_response_filename, 0);
- }
- } else {
- LWIP_DEBUGF(HTTPD_DEBUG, ("POST received invalid Content-Length: %s\n",
- conten_len_num));
- return ERR_ARG;
- }
- }
- }
- }
- /* if we come here, the POST is incomplete */
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
- return ERR_INPROGRESS;
-#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
- return ERR_ARG;
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
-}
-
-#if LWIP_HTTPD_POST_MANUAL_WND
-/** A POST implementation can call this function to update the TCP window.
- * This can be used to throttle data reception (e.g. when received data is
- * programmed to flash and data is received faster than programmed).
- *
- * @param connection A connection handle passed to httpd_post_begin for which
- * httpd_post_finished has *NOT* been called yet!
- * @param recved_len Length of data received (for window update)
- */
-void httpd_post_data_recved(void *connection, u16_t recved_len)
-{
- struct http_state *hs = (struct http_state*)connection;
- if (hs != NULL) {
- if (hs->no_auto_wnd) {
- u16_t len = recved_len;
- if (hs->unrecved_bytes >= recved_len) {
- hs->unrecved_bytes -= recved_len;
- } else {
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_LEVEL_WARNING, ("httpd_post_data_recved: recved_len too big\n"));
- len = (u16_t)hs->unrecved_bytes;
- hs->unrecved_bytes = 0;
- }
- if (hs->pcb != NULL) {
- if (len != 0) {
- tcp_recved(hs->pcb, len);
- }
- if ((hs->post_content_len_left == 0) && (hs->unrecved_bytes == 0)) {
- /* finished handling POST */
- http_handle_post_finished(hs);
- http_send_data(hs->pcb, hs);
- }
- }
- }
- }
-}
-#endif /* LWIP_HTTPD_POST_MANUAL_WND */
-
-#endif /* LWIP_HTTPD_SUPPORT_POST */
-
-/**
- * When data has been received in the correct state, try to parse it
- * as a HTTP request.
- *
- * @param p the received pbuf
- * @param hs the connection state
- * @param pcb the tcp_pcb which received this packet
- * @return ERR_OK if request was OK and hs has been initialized correctly
- * ERR_INPROGRESS if request was OK so far but not fully received
- * another err_t otherwise
- */
-static err_t
-http_parse_request(struct pbuf **inp, struct http_state *hs, struct tcp_pcb *pcb)
-{
- char *data;
- char *crlf;
- u16_t data_len;
- struct pbuf *p = *inp;
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
- u16_t clen;
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
-#if LWIP_HTTPD_SUPPORT_POST
- err_t err;
-#endif /* LWIP_HTTPD_SUPPORT_POST */
-
- LWIP_UNUSED_ARG(pcb); /* only used for post */
- LWIP_ASSERT("p != NULL", p != NULL);
- LWIP_ASSERT("hs != NULL", hs != NULL);
-
- if ((hs->handle != NULL) || (hs->file != NULL)) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("Received data while sending a file\n"));
- /* already sending a file */
- /* @todo: abort? */
- return ERR_USE;
- }
-
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
-
- LWIP_DEBUGF(HTTPD_DEBUG, ("Received %"U16_F" bytes\n", p->tot_len));
-
- /* first check allowed characters in this pbuf? */
-
- /* enqueue the pbuf */
- if (hs->req == NULL) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("First pbuf\n"));
- hs->req = p;
- } else {
- LWIP_DEBUGF(HTTPD_DEBUG, ("pbuf enqueued\n"));
- pbuf_cat(hs->req, p);
- }
-
- if (hs->req->next != NULL) {
- data_len = LWIP_MIN(hs->req->tot_len, LWIP_HTTPD_MAX_REQ_LENGTH);
- pbuf_copy_partial(hs->req, httpd_req_buf, data_len, 0);
- data = httpd_req_buf;
- } else
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
- {
- data = (char *)p->payload;
- data_len = p->len;
- if (p->len != p->tot_len) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("Warning: incomplete header due to chained pbufs\n"));
- }
- }
-
- /* received enough data for minimal request? */
- if (data_len >= MIN_REQ_LEN) {
- /* wait for CRLF before parsing anything */
- crlf = strnstr(data, CRLF, data_len);
- if (crlf != NULL) {
-#if LWIP_HTTPD_SUPPORT_POST
- int is_post = 0;
-#endif /* LWIP_HTTPD_SUPPORT_POST */
- int is_09 = 0;
- char *sp1, *sp2;
- u16_t left_len, uri_len;
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("CRLF received, parsing request\n"));
- /* parse method */
- if (!strncmp(data, "GET ", 4)) {
- sp1 = data + 3;
- /* received GET request */
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Received GET request\"\n"));
-#if LWIP_HTTPD_SUPPORT_POST
- } else if (!strncmp(data, "POST ", 5)) {
- /* store request type */
- is_post = 1;
- sp1 = data + 4;
- /* received GET request */
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Received POST request\n"));
-#endif /* LWIP_HTTPD_SUPPORT_POST */
- } else {
- /* null-terminate the METHOD (pbuf is freed anyway wen returning) */
- data[4] = 0;
- /* unsupported method! */
- LWIP_DEBUGF(HTTPD_DEBUG, ("Unsupported request method (not implemented): \"%s\"\n",
- data));
- return http_find_error_file(hs, 501);
- }
- /* if we come here, method is OK, parse URI */
- left_len = data_len - ((sp1 +1) - data);
- sp2 = strnstr(sp1 + 1, " ", left_len);
-#if LWIP_HTTPD_SUPPORT_V09
- if (sp2 == NULL) {
- /* HTTP 0.9: respond with correct protocol version */
- sp2 = strnstr(sp1 + 1, CRLF, left_len);
- is_09 = 1;
-#if LWIP_HTTPD_SUPPORT_POST
- if (is_post) {
- /* HTTP/0.9 does not support POST */
- goto badrequest;
- }
-#endif /* LWIP_HTTPD_SUPPORT_POST */
- }
-#endif /* LWIP_HTTPD_SUPPORT_V09 */
- uri_len = sp2 - (sp1 + 1);
- if ((sp2 != 0) && (sp2 > sp1)) {
- char *uri = sp1 + 1;
- /* null-terminate the METHOD (pbuf is freed anyway wen returning) */
- *sp1 = 0;
- uri[uri_len] = 0;
- LWIP_DEBUGF(HTTPD_DEBUG, ("Received \"%s\" request for URI: \"%s\"\n",
- data, uri));
-#if LWIP_HTTPD_SUPPORT_POST
- if (is_post) {
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
- struct pbuf **q = &hs->req;
-#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
- struct pbuf **q = inp;
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
- err = http_post_request(pcb, q, hs, data, data_len, uri, sp2);
- if (err != ERR_OK) {
- /* restore header for next try */
- *sp1 = ' ';
- *sp2 = ' ';
- uri[uri_len] = ' ';
- }
- if (err == ERR_ARG) {
- goto badrequest;
- }
- return err;
- } else
-#endif /* LWIP_HTTPD_SUPPORT_POST */
- {
- return http_find_file(hs, uri, is_09);
- }
- } else {
- LWIP_DEBUGF(HTTPD_DEBUG, ("invalid URI\n"));
- }
- }
- }
-
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
- clen = pbuf_clen(hs->req);
- if ((hs->req->tot_len <= LWIP_HTTPD_REQ_BUFSIZE) &&
- (clen <= LWIP_HTTPD_REQ_QUEUELEN)) {
- /* request not fully received (too short or CRLF is missing) */
- return ERR_INPROGRESS;
- } else
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
- {
-#if LWIP_HTTPD_SUPPORT_POST
-badrequest:
-#endif /* LWIP_HTTPD_SUPPORT_POST */
- LWIP_DEBUGF(HTTPD_DEBUG, ("bad request\n"));
- /* could not parse request */
- return http_find_error_file(hs, 400);
- }
-}
-
-/** Try to find the file specified by uri and, if found, initialize hs
- * accordingly.
- *
- * @param hs the connection state
- * @param uri the HTTP header URI
- * @param is_09 1 if the request is HTTP/0.9 (no HTTP headers in response)
- * @return ERR_OK if file was found and hs has been initialized correctly
- * another err_t otherwise
- */
-static err_t
-http_find_file(struct http_state *hs, const char *uri, int is_09)
-{
- size_t loop;
- struct fs_file *file = NULL;
- char *params;
-#if LWIP_HTTPD_CGI
- int i;
- int count;
-#endif /* LWIP_HTTPD_CGI */
-
-#if LWIP_HTTPD_SSI
- /*
- * By default, assume we will not be processing server-side-includes
- * tags
- */
- hs->tag_check = false;
-#endif /* LWIP_HTTPD_SSI */
-
- /* Have we been asked for the default root file? */
- if((uri[0] == '/') && (uri[1] == 0)) {
- /* Try each of the configured default filenames until we find one
- that exists. */
- for (loop = 0; loop < NUM_DEFAULT_FILENAMES; loop++) {
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Looking for %s...\n", g_psDefaultFilenames[loop].name));
- file = fs_open((char *)g_psDefaultFilenames[loop].name);
- uri = (char *)g_psDefaultFilenames[loop].name;
- if(file != NULL) {
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Opened.\n"));
-#if LWIP_HTTPD_SSI
- hs->tag_check = g_psDefaultFilenames[loop].shtml;
-#endif /* LWIP_HTTPD_SSI */
- break;
- }
- }
- if (file == NULL) {
- /* None of the default filenames exist so send back a 404 page */
- file = http_get_404_file(&uri);
-#if LWIP_HTTPD_SSI
- hs->tag_check = false;
-#endif /* LWIP_HTTPD_SSI */
- }
- } else {
- /* No - we've been asked for a specific file. */
- /* First, isolate the base URI (without any parameters) */
- params = (char *)strchr(uri, '?');
- if (params != NULL) {
- /* URI contains parameters. NULL-terminate the base URI */
- *params = '\0';
- params++;
- }
-
-#if LWIP_HTTPD_CGI
- /* Does the base URI we have isolated correspond to a CGI handler? */
- if (g_iNumCGIs && g_pCGIs) {
- for (i = 0; i < g_iNumCGIs; i++) {
- if (strcmp(uri, g_pCGIs[i].pcCGIName) == 0) {
- /*
- * We found a CGI that handles this URI so extract the
- * parameters and call the handler.
- */
- count = extract_uri_parameters(hs, params);
- uri = g_pCGIs[i].pfnCGIHandler(i, count, hs->params,
- hs->param_vals);
- break;
- }
- }
- }
-#endif /* LWIP_HTTPD_CGI */
-
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Opening %s\n", uri));
-
- file = fs_open(uri);
- if (file == NULL) {
- file = http_get_404_file(&uri);
- }
-#if LWIP_HTTPD_SSI
- if (file != NULL) {
- /*
- * See if we have been asked for an shtml file and, if so,
- * enable tag checking.
- */
- hs->tag_check = false;
- for (loop = 0; loop < NUM_SHTML_EXTENSIONS; loop++) {
- if (strstr(uri, g_pcSSIExtensions[loop])) {
- hs->tag_check = true;
- break;
- }
- }
- }
-#endif /* LWIP_HTTPD_SSI */
- }
- return http_init_file(hs, file, is_09, uri);
-}
-
-/** Initialize a http connection with a file to send (if found).
- * Called by http_find_file and http_find_error_file.
- *
- * @param hs http connection state
- * @param file file structure to send (or NULL if not found)
- * @param is_09 1 if the request is HTTP/0.9 (no HTTP headers in response)
- * @param uri the HTTP header URI
- * @return ERR_OK if file was found and hs has been initialized correctly
- * another err_t otherwise
- */
-static err_t
-http_init_file(struct http_state *hs, struct fs_file *file, int is_09, const char *uri)
-{
- if (file != NULL) {
- /* file opened, initialise struct http_state */
-#if LWIP_HTTPD_SSI
- hs->tag_index = 0;
- hs->tag_state = TAG_NONE;
- hs->parsed = file->data;
- hs->parse_left = file->len;
- hs->tag_end = file->data;
-#endif /* LWIP_HTTPD_SSI */
- hs->handle = file;
- hs->file = (char*)file->data;
- LWIP_ASSERT("File length must be positive!", (file->len >= 0));
- hs->left = file->len;
- hs->retries = 0;
-#if LWIP_HTTPD_TIMING
- hs->time_started = sys_now();
-#endif /* LWIP_HTTPD_TIMING */
-#if !LWIP_HTTPD_DYNAMIC_HEADERS
- LWIP_ASSERT("HTTP headers not included in file system", hs->handle->http_header_included);
-#endif /* !LWIP_HTTPD_DYNAMIC_HEADERS */
-#if LWIP_HTTPD_SUPPORT_V09
- if (hs->handle->http_header_included && is_09) {
- /* HTTP/0.9 responses are sent without HTTP header,
- search for the end of the header. */
- char *file_start = strnstr(hs->file, CRLF CRLF, hs->left);
- if (file_start != NULL) {
- size_t diff = file_start + 4 - hs->file;
- hs->file += diff;
- hs->left -= (u32_t)diff;
- }
- }
-#endif /* LWIP_HTTPD_SUPPORT_V09*/
- } else {
- hs->handle = NULL;
- hs->file = NULL;
- hs->left = 0;
- hs->retries = 0;
- }
-#if LWIP_HTTPD_DYNAMIC_HEADERS
- /* Determine the HTTP headers to send based on the file extension of
- * the requested URI. */
- if ((hs->handle == NULL) || !hs->handle->http_header_included) {
- get_http_headers(hs, (char*)uri);
- }
-#else /* LWIP_HTTPD_DYNAMIC_HEADERS */
- LWIP_UNUSED_ARG(uri);
-#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
- return ERR_OK;
-}
-
-/**
- * The pcb had an error and is already deallocated.
- * The argument might still be valid (if != NULL).
- */
-static void
-http_err(void *arg, err_t err)
-{
- struct http_state *hs = (struct http_state *)arg;
- LWIP_UNUSED_ARG(err);
-
- LWIP_DEBUGF(HTTPD_DEBUG, ("http_err: %s", lwip_strerr(err)));
-
- if (hs != NULL) {
- http_state_free(hs);
- }
-}
-
-/**
- * Data has been sent and acknowledged by the remote host.
- * This means that more data can be sent.
- */
-static err_t
-http_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
-{
- struct http_state *hs = (struct http_state *)arg;
-
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_sent %p\n", (void*)pcb));
-
- LWIP_UNUSED_ARG(len);
-
- if (hs == NULL) {
- return ERR_OK;
- }
-
- hs->retries = 0;
-
- http_send_data(pcb, hs);
-
- return ERR_OK;
-}
-
-/**
- * The poll function is called every 2nd second.
- * If there has been no data sent (which resets the retries) in 8 seconds, close.
- * If the last portion of a file has not been sent in 2 seconds, close.
- *
- * This could be increased, but we don't want to waste resources for bad connections.
- */
-static err_t
-http_poll(void *arg, struct tcp_pcb *pcb)
-{
- struct http_state *hs = (struct http_state *)arg;
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_poll: pcb=%p hs=%p pcb_state=%s\n",
- (void*)pcb, (void*)hs, tcp_debug_state_str(pcb->state)));
-
- if (hs == NULL) {
- err_t closed;
- /* arg is null, close. */
- LWIP_DEBUGF(HTTPD_DEBUG, ("http_poll: arg is NULL, close\n"));
- closed = http_close_conn(pcb, hs);
- LWIP_UNUSED_ARG(closed);
-#if LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR
- if (closed == ERR_MEM) {
- tcp_abort(pcb);
- return ERR_ABRT;
- }
-#endif /* LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR */
- return ERR_OK;
- } else {
- hs->retries++;
- if (hs->retries == HTTPD_MAX_RETRIES) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("http_poll: too many retries, close\n"));
- http_close_conn(pcb, hs);
- return ERR_OK;
- }
-
- /* If this connection has a file open, try to send some more data. If
- * it has not yet received a GET request, don't do this since it will
- * cause the connection to close immediately. */
- if(hs && (hs->handle)) {
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_poll: try to send more data\n"));
- if(http_send_data(pcb, hs)) {
- /* If we wrote anything to be sent, go ahead and send it now. */
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("tcp_output\n"));
- tcp_output(pcb);
- }
- }
- }
-
- return ERR_OK;
-}
-
-/**
- * Data has been received on this pcb.
- * For HTTP 1.0, this should normally only happen once (if the request fits in one packet).
- */
-static err_t
-http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
-{
- err_t parsed = ERR_ABRT;
- struct http_state *hs = (struct http_state *)arg;
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_recv: pcb=%p pbuf=%p err=%s\n", (void*)pcb,
- (void*)p, lwip_strerr(err)));
-
- if ((err != ERR_OK) || (p == NULL) || (hs == NULL)) {
- /* error or closed by other side? */
- if (p != NULL) {
- /* Inform TCP that we have taken the data. */
- tcp_recved(pcb, p->tot_len);
- pbuf_free(p);
- }
- if (hs == NULL) {
- /* this should not happen, only to be robust */
- LWIP_DEBUGF(HTTPD_DEBUG, ("Error, http_recv: hs is NULL, close\n"));
- }
- http_close_conn(pcb, hs);
- return ERR_OK;
- }
-
-#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND
- if (hs->no_auto_wnd) {
- hs->unrecved_bytes += p->tot_len;
- } else
-#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */
- {
- /* Inform TCP that we have taken the data. */
- tcp_recved(pcb, p->tot_len);
- }
-
-#if LWIP_HTTPD_SUPPORT_POST
- if (hs->post_content_len_left > 0) {
- /* reset idle counter when POST data is received */
- hs->retries = 0;
- /* this is data for a POST, pass the complete pbuf to the application */
- http_post_rxpbuf(hs, p);
- /* pbuf is passed to the application, don't free it! */
- if (hs->post_content_len_left == 0) {
- /* all data received, send response or close connection */
- http_send_data(pcb, hs);
- }
- return ERR_OK;
- } else
-#endif /* LWIP_HTTPD_SUPPORT_POST */
- {
- if (hs->handle == NULL) {
- parsed = http_parse_request(&p, hs, pcb);
- LWIP_ASSERT("http_parse_request: unexpected return value", parsed == ERR_OK
- || parsed == ERR_INPROGRESS ||parsed == ERR_ARG || parsed == ERR_USE);
- } else {
- LWIP_DEBUGF(HTTPD_DEBUG, ("http_recv: already sending data\n"));
- }
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
- if (parsed != ERR_INPROGRESS) {
- /* request fully parsed or error */
- if (hs->req != NULL) {
- pbuf_free(hs->req);
- hs->req = NULL;
- }
- }
-#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
- if (p != NULL) {
- /* pbuf not passed to application, free it now */
- pbuf_free(p);
- }
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
- if (parsed == ERR_OK) {
-#if LWIP_HTTPD_SUPPORT_POST
- if (hs->post_content_len_left == 0)
-#endif /* LWIP_HTTPD_SUPPORT_POST */
- {
- LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_recv: data %p len %"S32_F"\n", hs->file, hs->left));
- http_send_data(pcb, hs);
- }
- } else if (parsed == ERR_ARG) {
- /* @todo: close on ERR_USE? */
- http_close_conn(pcb, hs);
- }
- }
- return ERR_OK;
-}
-
-/**
- * A new incoming connection has been accepted.
- */
-static err_t
-http_accept(void *arg, struct tcp_pcb *pcb, err_t err)
-{
- struct http_state *hs;
- struct tcp_pcb_listen *lpcb = (struct tcp_pcb_listen*)arg;
- LWIP_UNUSED_ARG(err);
- LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept %p / %p\n", (void*)pcb, arg));
-
- /* Decrease the listen backlog counter */
- tcp_accepted(lpcb);
- /* Set priority */
- tcp_setprio(pcb, HTTPD_TCP_PRIO);
-
- /* Allocate memory for the structure that holds the state of the
- connection - initialized by that function. */
- hs = http_state_alloc();
- if (hs == NULL) {
- LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept: Out of memory, RST\n"));
- return ERR_MEM;
- }
-
- /* Tell TCP that this is the structure we wish to be passed for our
- callbacks. */
- tcp_arg(pcb, hs);
-
- /* Set up the various callback functions */
- tcp_recv(pcb, http_recv);
- tcp_err(pcb, http_err);
- tcp_poll(pcb, http_poll, HTTPD_POLL_INTERVAL);
- tcp_sent(pcb, http_sent);
-
- return ERR_OK;
-}
-
-/**
- * Initialize the httpd with the specified local address.
- */
-static void
-httpd_init_addr(ip_addr_t *local_addr)
-{
- struct tcp_pcb *pcb;
- err_t err;
-
- pcb = tcp_new();
- LWIP_ASSERT("httpd_init: tcp_new failed", pcb != NULL);
- tcp_setprio(pcb, HTTPD_TCP_PRIO);
- /* set SOF_REUSEADDR here to explicitly bind httpd to multiple interfaces */
- err = tcp_bind(pcb, local_addr, HTTPD_SERVER_PORT);
- LWIP_ASSERT("httpd_init: tcp_bind failed", err == ERR_OK);
- pcb = tcp_listen(pcb);
- LWIP_ASSERT("httpd_init: tcp_listen failed", pcb != NULL);
- /* initialize callback arg and accept callback */
- tcp_arg(pcb, pcb);
- tcp_accept(pcb, http_accept);
-}
-
-/**
- * Initialize the httpd: set up a listening PCB and bind it to the defined port
- */
-void
-httpd_init(void)
-{
-#if HTTPD_USE_MEM_POOL
- LWIP_ASSERT("memp_sizes[MEMP_HTTPD_STATE] >= sizeof(http_state)",
- memp_sizes[MEMP_HTTPD_STATE] >= sizeof(http_state));
-#endif
- LWIP_DEBUGF(HTTPD_DEBUG, ("httpd_init\n"));
-
- httpd_init_addr(IP_ADDR_ANY);
-}
-
-#if LWIP_HTTPD_SSI
-/**
- * Set the SSI handler function.
- *
- * @param ssi_handler the SSI handler function
- * @param tags an array of SSI tag strings to search for in SSI-enabled files
- * @param num_tags number of tags in the 'tags' array
- */
-void
-http_set_ssi_handler(tSSIHandler ssi_handler, const char **tags, int num_tags)
-{
- LWIP_DEBUGF(HTTPD_DEBUG, ("http_set_ssi_handler\n"));
-
- LWIP_ASSERT("no ssi_handler given", ssi_handler != NULL);
- LWIP_ASSERT("no tags given", tags != NULL);
- LWIP_ASSERT("invalid number of tags", num_tags > 0);
-
- g_pfnSSIHandler = ssi_handler;
- g_ppcTags = tags;
- g_iNumTags = num_tags;
-}
-#endif /* LWIP_HTTPD_SSI */
-
-#if LWIP_HTTPD_CGI
-/**
- * Set an array of CGI filenames/handler functions
- *
- * @param cgis an array of CGI filenames/handler functions
- * @param num_handlers number of elements in the 'cgis' array
- */
-void
-http_set_cgi_handlers(const tCGI *cgis, int num_handlers)
-{
- LWIP_ASSERT("no cgis given", cgis != NULL);
- LWIP_ASSERT("invalid number of handlers", num_handlers > 0);
-
- g_pCGIs = cgis;
- g_iNumCGIs = num_handlers;
-}
-#endif /* LWIP_HTTPD_CGI */
-
-#endif /* LWIP_TCP */
+++ /dev/null
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- * This version of the file has been modified by Texas Instruments to offer
- * simple server-side-include (SSI) and Common Gateway Interface (CGI)
- * capability.
- */
-
-#ifndef __HTTPD_H__
-#define __HTTPD_H__
-
-#include "lwip/opt.h"
-#include "lwip/err.h"
-#include "lwip/pbuf.h"
-
-
-/** Set this to 1 to support CGI */
-#ifndef LWIP_HTTPD_CGI
-#define LWIP_HTTPD_CGI 0
-#endif
-
-/** Set this to 1 to support SSI (Server-Side-Includes) */
-#ifndef LWIP_HTTPD_SSI
-#define LWIP_HTTPD_SSI 1
-#endif
-
-/** Set this to 1 to support HTTP POST */
-#ifndef LWIP_HTTPD_SUPPORT_POST
-#define LWIP_HTTPD_SUPPORT_POST 0
-#endif
-
-
-#if LWIP_HTTPD_CGI
-
-/*
- * Function pointer for a CGI script handler.
- *
- * This function is called each time the HTTPD server is asked for a file
- * whose name was previously registered as a CGI function using a call to
- * http_set_cgi_handler. The iIndex parameter provides the index of the
- * CGI within the ppcURLs array passed to http_set_cgi_handler. Parameters
- * pcParam and pcValue provide access to the parameters provided along with
- * the URI. iNumParams provides a count of the entries in the pcParam and
- * pcValue arrays. Each entry in the pcParam array contains the name of a
- * parameter with the corresponding entry in the pcValue array containing the
- * value for that parameter. Note that pcParam may contain multiple elements
- * with the same name if, for example, a multi-selection list control is used
- * in the form generating the data.
- *
- * The function should return a pointer to a character string which is the
- * path and filename of the response that is to be sent to the connected
- * browser, for example "/thanks.htm" or "/response/error.ssi".
- *
- * The maximum number of parameters that will be passed to this function via
- * iNumParams is defined by LWIP_HTTPD_MAX_CGI_PARAMETERS. Any parameters in the incoming
- * HTTP request above this number will be discarded.
- *
- * Requests intended for use by this CGI mechanism must be sent using the GET
- * method (which encodes all parameters within the URI rather than in a block
- * later in the request). Attempts to use the POST method will result in the
- * request being ignored.
- *
- */
-typedef const char *(*tCGIHandler)(int iIndex, int iNumParams, char *pcParam[],
- char *pcValue[]);
-
-/*
- * Structure defining the base filename (URL) of a CGI and the associated
- * function which is to be called when that URL is requested.
- */
-typedef struct
-{
- const char *pcCGIName;
- tCGIHandler pfnCGIHandler;
-} tCGI;
-
-void http_set_cgi_handlers(const tCGI *pCGIs, int iNumHandlers);
-
-
-/* The maximum number of parameters that the CGI handler can be sent. */
-#ifndef LWIP_HTTPD_MAX_CGI_PARAMETERS
-#define LWIP_HTTPD_MAX_CGI_PARAMETERS 16
-#endif
-
-#endif /* LWIP_HTTPD_CGI */
-
-#if LWIP_HTTPD_SSI
-
-/** LWIP_HTTPD_SSI_MULTIPART==1: SSI handler function is called with 2 more
- * arguments indicating a counter for insert string that are too long to be
- * inserted at once: the SSI handler function must then set 'next_tag_part'
- * which will be passed back to it in the next call. */
-#ifndef LWIP_HTTPD_SSI_MULTIPART
-#define LWIP_HTTPD_SSI_MULTIPART 0
-#endif
-
-/*
- * Function pointer for the SSI tag handler callback.
- *
- * This function will be called each time the HTTPD server detects a tag of the
- * form <!--#name--> in a .shtml, .ssi or .shtm file where "name" appears as
- * one of the tags supplied to http_set_ssi_handler in the ppcTags array. The
- * returned insert string, which will be appended after the the string
- * "<!--#name-->" in file sent back to the client,should be written to pointer
- * pcInsert. iInsertLen contains the size of the buffer pointed to by
- * pcInsert. The iIndex parameter provides the zero-based index of the tag as
- * found in the ppcTags array and identifies the tag that is to be processed.
- *
- * The handler returns the number of characters written to pcInsert excluding
- * any terminating NULL or a negative number to indicate a failure (tag not
- * recognized, for example).
- *
- * Note that the behavior of this SSI mechanism is somewhat different from the
- * "normal" SSI processing as found in, for example, the Apache web server. In
- * this case, the inserted text is appended following the SSI tag rather than
- * replacing the tag entirely. This allows for an implementation that does not
- * require significant additional buffering of output data yet which will still
- * offer usable SSI functionality. One downside to this approach is when
- * attempting to use SSI within JavaScript. The SSI tag is structured to
- * resemble an HTML comment but this syntax does not constitute a comment
- * within JavaScript and, hence, leaving the tag in place will result in
- * problems in these cases. To work around this, any SSI tag which needs to
- * output JavaScript code must do so in an encapsulated way, sending the whole
- * HTML <script>...</script> section as a single include.
- */
-typedef u16_t (*tSSIHandler)(int iIndex, char *pcInsert, int iInsertLen
-#if LWIP_HTTPD_SSI_MULTIPART
- , u16_t current_tag_part, u16_t *next_tag_part
-#endif /* LWIP_HTTPD_SSI_MULTIPART */
-#if LWIP_HTTPD_FILE_STATE
- , void *connection_state
-#endif /* LWIP_HTTPD_FILE_STATE */
- );
-
-void http_set_ssi_handler(tSSIHandler pfnSSIHandler,
- const char **ppcTags, int iNumTags);
-
-/* The maximum length of the string comprising the tag name */
-#ifndef LWIP_HTTPD_MAX_TAG_NAME_LEN
-#define LWIP_HTTPD_MAX_TAG_NAME_LEN 8
-#endif
-
-/* The maximum length of string that can be returned to replace any given tag */
-#ifndef LWIP_HTTPD_MAX_TAG_INSERT_LEN
-#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 192
-#endif
-
-#endif /* LWIP_HTTPD_SSI */
-
-#if LWIP_HTTPD_SUPPORT_POST
-
-/* These functions must be implemented by the application */
-
-/** Called when a POST request has been received. The application can decide
- * whether to accept it or not.
- *
- * @param connection Unique connection identifier, valid until httpd_post_end
- * is called.
- * @param uri The HTTP header URI receiving the POST request.
- * @param http_request The raw HTTP request (the first packet, normally).
- * @param http_request_len Size of 'http_request'.
- * @param content_len Content-Length from HTTP header.
- * @param response_uri Filename of response file, to be filled when denying the
- * request
- * @param response_uri_len Size of the 'response_uri' buffer.
- * @param post_auto_wnd Set this to 0 to let the callback code handle window
- * updates by calling 'httpd_post_data_recved' (to throttle rx speed)
- * default is 1 (httpd handles window updates automatically)
- * @return ERR_OK: Accept the POST request, data may be passed in
- * another err_t: Deny the POST request, send back 'bad request'.
- */
-err_t httpd_post_begin(void *connection, const char *uri, const char *http_request,
- u16_t http_request_len, int content_len, char *response_uri,
- u16_t response_uri_len, u8_t *post_auto_wnd);
-
-/** Called for each pbuf of data that has been received for a POST.
- * ATTENTION: The application is responsible for freeing the pbufs passed in!
- *
- * @param connection Unique connection identifier.
- * @param p Received data.
- * @return ERR_OK: Data accepted.
- * another err_t: Data denied, http_post_get_response_uri will be called.
- */
-err_t httpd_post_receive_data(void *connection, struct pbuf *p);
-
-/** Called when all data is received or when the connection is closed.
- * The application must return the filename/URI of a file to send in response
- * to this POST request. If the response_uri buffer is untouched, a 404
- * response is returned.
- *
- * @param connection Unique connection identifier.
- * @param response_uri Filename of response file, to be filled when denying the request
- * @param response_uri_len Size of the 'response_uri' buffer.
- */
-void httpd_post_finished(void *connection, char *response_uri, u16_t response_uri_len);
-
-#ifndef LWIP_HTTPD_POST_MANUAL_WND
-#define LWIP_HTTPD_POST_MANUAL_WND 0
-#endif
-
-#if LWIP_HTTPD_POST_MANUAL_WND
-void httpd_post_data_recved(void *connection, u16_t recved_len);
-#endif /* LWIP_HTTPD_POST_MANUAL_WND */
-
-#endif /* LWIP_HTTPD_SUPPORT_POST */
-
-void httpd_init(void);
-
-#endif /* __HTTPD_H__ */
+++ /dev/null
-#ifndef __HTTPD_STRUCTS_H__
-#define __HTTPD_STRUCTS_H__
-
-#include "httpd.h"
-
-/** This string is passed in the HTTP header as "Server: " */
-#ifndef HTTPD_SERVER_AGENT
-#define HTTPD_SERVER_AGENT "lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)"
-#endif
-
-/** Set this to 1 if you want to include code that creates HTTP headers
- * at runtime. Default is off: HTTP headers are then created statically
- * by the makefsdata tool. Static headers mean smaller code size, but
- * the (readonly) fsdata will grow a bit as every file includes the HTTP
- * header. */
-#ifndef LWIP_HTTPD_DYNAMIC_HEADERS
-#define LWIP_HTTPD_DYNAMIC_HEADERS 0
-#endif
-
-
-#if LWIP_HTTPD_DYNAMIC_HEADERS
-/** This struct is used for a list of HTTP header strings for various
- * filename extensions. */
-typedef struct
-{
- const char *extension;
- int headerIndex;
-} tHTTPHeader;
-
-/** A list of strings used in HTTP headers */
-static const char * const g_psHTTPHeaderStrings[] =
-{
- "Content-type: text/html\r\n\r\n",
- "Content-type: text/html\r\nExpires: Fri, 10 Apr 2008 14:00:00 GMT\r\nPragma: no-cache\r\n\r\n",
- "Content-type: image/gif\r\n\r\n",
- "Content-type: image/png\r\n\r\n",
- "Content-type: image/jpeg\r\n\r\n",
- "Content-type: image/bmp\r\n\r\n",
- "Content-type: image/x-icon\r\n\r\n",
- "Content-type: application/octet-stream\r\n\r\n",
- "Content-type: application/x-javascript\r\n\r\n",
- "Content-type: application/x-javascript\r\n\r\n",
- "Content-type: text/css\r\n\r\n",
- "Content-type: application/x-shockwave-flash\r\n\r\n",
- "Content-type: text/xml\r\n\r\n",
- "Content-type: text/plain\r\n\r\n",
- "HTTP/1.0 200 OK\r\n",
- "HTTP/1.0 404 File not found\r\n",
- "HTTP/1.0 400 Bad Request\r\n",
- "HTTP/1.0 501 Not Implemented\r\n",
- "HTTP/1.1 200 OK\r\n",
- "HTTP/1.1 404 File not found\r\n",
- "HTTP/1.1 400 Bad Request\r\n",
- "HTTP/1.1 501 Not Implemented\r\n",
- "Content-Length: ",
- "Connection: Close\r\n",
- "Server: "HTTPD_SERVER_AGENT"\r\n",
- "\r\n<html><body><h2>404: The requested file cannot be found.</h2></body></html>\r\n"
-};
-
-/* Indexes into the g_psHTTPHeaderStrings array */
-#define HTTP_HDR_HTML 0 /* text/html */
-#define HTTP_HDR_SSI 1 /* text/html Expires... */
-#define HTTP_HDR_GIF 2 /* image/gif */
-#define HTTP_HDR_PNG 3 /* image/png */
-#define HTTP_HDR_JPG 4 /* image/jpeg */
-#define HTTP_HDR_BMP 5 /* image/bmp */
-#define HTTP_HDR_ICO 6 /* image/x-icon */
-#define HTTP_HDR_APP 7 /* application/octet-stream */
-#define HTTP_HDR_JS 8 /* application/x-javascript */
-#define HTTP_HDR_RA 9 /* application/x-javascript */
-#define HTTP_HDR_CSS 10 /* text/css */
-#define HTTP_HDR_SWF 11 /* application/x-shockwave-flash */
-#define HTTP_HDR_XML 12 /* text/xml */
-#define HTTP_HDR_DEFAULT_TYPE 13 /* text/plain */
-#define HTTP_HDR_OK 14 /* 200 OK */
-#define HTTP_HDR_NOT_FOUND 15 /* 404 File not found */
-#define HTTP_HDR_BAD_REQUEST 16 /* 400 Bad request */
-#define HTTP_HDR_NOT_IMPL 17 /* 501 Not Implemented */
-#define HTTP_HDR_OK_11 18 /* 200 OK */
-#define HTTP_HDR_NOT_FOUND_11 19 /* 404 File not found */
-#define HTTP_HDR_BAD_REQUEST_11 20 /* 400 Bad request */
-#define HTTP_HDR_NOT_IMPL_11 21 /* 501 Not Implemented */
-#define HTTP_HDR_CONTENT_LENGTH 22 /* Content-Length: (HTTP 1.1)*/
-#define HTTP_HDR_CONN_CLOSE 23 /* Connection: Close (HTTP 1.1) */
-#define HTTP_HDR_SERVER 24 /* Server: HTTPD_SERVER_AGENT */
-#define DEFAULT_404_HTML 25 /* default 404 body */
-
-/** A list of extension-to-HTTP header strings */
-const static tHTTPHeader g_psHTTPHeaders[] =
-{
- { "html", HTTP_HDR_HTML},
- { "htm", HTTP_HDR_HTML},
- { "shtml",HTTP_HDR_SSI},
- { "shtm", HTTP_HDR_SSI},
- { "ssi", HTTP_HDR_SSI},
- { "gif", HTTP_HDR_GIF},
- { "png", HTTP_HDR_PNG},
- { "jpg", HTTP_HDR_JPG},
- { "bmp", HTTP_HDR_BMP},
- { "ico", HTTP_HDR_ICO},
- { "class",HTTP_HDR_APP},
- { "cls", HTTP_HDR_APP},
- { "js", HTTP_HDR_JS},
- { "ram", HTTP_HDR_RA},
- { "css", HTTP_HDR_CSS},
- { "swf", HTTP_HDR_SWF},
- { "xml", HTTP_HDR_XML}
-};
-
-#define NUM_HTTP_HEADERS (sizeof(g_psHTTPHeaders) / sizeof(tHTTPHeader))
-
-#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
-
-#endif /* __HTTPD_STRUCTS_H__ */
+++ /dev/null
-<html>
-<head><title>lwIP - A Lightweight TCP/IP Stack</title></head>
-<body bgcolor="white" text="black">
-
- <table width="100%">
- <tr valign="top"><td width="80">
- <a href="http://www.sics.se/"><img src="/img/sics.gif"
- border="0" alt="SICS logo" title="SICS logo"></a>
- </td><td width="500">
- <h1>lwIP - A Lightweight TCP/IP Stack</h1>
- <h2>404 - Page not found</h2>
- <p>
- Sorry, the page you are requesting was not found on this
- server.
- </p>
- </td><td>
-
- </td></tr>
- </table>
-</body>
-</html>
+++ /dev/null
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
-<html>\r
- <head>\r
- <title>FreeRTOS.org lwIP WEB server demo</title>\r
- </head>\r
- <BODY onLoad="window.setTimeout("location.href='index.shtml'",2000)">\r
-<font face="arial">\r
-<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS Homepage</a> <b>|</b> <a href="logo.jpg">37K jpg</a>\r
-<br><p>\r
-<hr>\r
-<br><p>\r
-<h2>Task statistics</h2>\r
-Page will refresh every 2 seconds.<p>\r
-<font face="courier"><pre>Task State Priority Stack #<br>************************************************<br>\r
-<!--#rtos_stats-->\r
-</pre></font>\r
-</font>\r
-</body>\r
-</html>\r
-\r
+++ /dev/null
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
-<html>\r
- <head>\r
- <title>FreeRTOS.org lwIP WEB server demo</title>\r
- </head>\r
- <BODY onLoad="window.setTimeout("location.href='runtime.shtml'",2000)">\r
-<font face="arial">\r
-<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS Homepage</a> <b>|</b> <a href="logo.jpg">37K jpg</a>\r
-<br><p>\r
-<hr>\r
-<br><p>\r
-<h2>Run-time statistics</h2>\r
-Page will refresh every 2 seconds.<p>\r
-<font face="courier"><pre>Task Abs Time % Time<br>****************************************<br>\r
-<!--#run_stats-->\r\r
-</pre></font>\r
-</font>\r
-</body>\r
-</html>\r
-\r
+++ /dev/null
-/**
- * makefsdata: Converts a directory structure for use with the lwIP httpd.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Jim Pettinato
- * Simon Goldschmidt
- *
- * @todo:
- * - take TCP_MSS, LWIP_TCP_TIMESTAMPS and
- * PAYLOAD_ALIGN_TYPE/PAYLOAD_ALIGNMENT as arguments
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#ifdef WIN32
-#define WIN32_LEAN_AND_MEAN
-#include "windows.h"
-#else
-#include <dir.h>
-#endif
-#include <dos.h>
-#include <string.h>
-
-/* Compatibility defines Win32 vs. DOS */
-#ifdef WIN32
-
-#define FIND_T WIN32_FIND_DATAA
-#define FIND_T_FILENAME(fInfo) (fInfo.cFileName)
-#define FIND_T_IS_DIR(fInfo) ((fInfo.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) != 0)
-#define FIND_T_IS_FILE(fInfo) ((fInfo.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) == 0)
-#define FIND_RET_T HANDLE
-#define FINDFIRST_FILE(path, result) FindFirstFileA(path, result)
-#define FINDFIRST_DIR(path, result) FindFirstFileA(path, result)
-#define FINDNEXT(ff_res, result) FindNextFileA(ff_res, result)
-#define FINDFIRST_SUCCEEDED(ret) (ret != INVALID_HANDLE_VALUE)
-#define FINDNEXT_SUCCEEDED(ret) (ret == TRUE)
-
-#define GETCWD(path, len) GetCurrentDirectoryA(len, path)
-#define CHDIR(path) SetCurrentDirectoryA(path)
-
-#define NEWLINE "\r\n"
-#define NEWLINE_LEN 2
-
-#else
-
-#define FIND_T struct fflbk
-#define FIND_T_FILENAME(fInfo) (fInfo.ff_name)
-#define FIND_T_IS_DIR(fInfo) ((fInfo.ff_attrib & FA_DIREC) == FA_DIREC)
-#define FIND_T_IS_FILE(fInfo) (1)
-#define FIND_RET_T int
-#define FINDFIRST_FILE(path, result) findfirst(path, result, FA_ARCH)
-#define FINDFIRST_DIR(path, result) findfirst(path, result, FA_DIREC)
-#define FINDNEXT(ff_res, result) FindNextFileA(ff_res, result)
-#define FINDFIRST_SUCCEEDED(ret) (ret == 0)
-#define FINDNEXT_SUCCEEDED(ret) (ret == 0)
-
-#define GETCWD(path, len) getcwd(path, len)
-#define CHDIR(path) chdir(path)
-
-#endif
-
-/* define this to get the header variables we use to build HTTP headers */
-#define LWIP_HTTPD_DYNAMIC_HEADERS 1
-#include "../httpd_structs.h"
-
-#include "../../../lwip-1.4.0/src/core/ipv4/inet_chksum.c"
-#include "../../../lwip-1.4.0/src/core/def.c"
-
-/** (Your server name here) */
-const char *serverID = "Server: "HTTPD_SERVER_AGENT"\r\n";
-
-/* change this to suit your MEM_ALIGNMENT */
-#define PAYLOAD_ALIGNMENT 4
-/* set this to 0 to prevent aligning payload */
-#define ALIGN_PAYLOAD 1
-/* define this to a type that has the required alignment */
-#define PAYLOAD_ALIGN_TYPE "unsigned int"
-static int payload_alingment_dummy_counter = 0;
-
-#define HEX_BYTES_PER_LINE 16
-
-#define MAX_PATH_LEN 256
-
-#define COPY_BUFSIZE 10240
-
-int process_sub(FILE *data_file, FILE *struct_file);
-int process_file(FILE *data_file, FILE *struct_file, const char *filename);
-int file_write_http_header(FILE *data_file, const char *filename, int file_size,
- u16_t *http_hdr_len, u16_t *http_hdr_chksum);
-int file_put_ascii(FILE *file, const char *ascii_string, int len, int *i);
-int s_put_ascii(char *buf, const char *ascii_string, int len, int *i);
-void concat_files(const char *file1, const char *file2, const char *targetfile);
-
-static unsigned char file_buffer_raw[COPY_BUFSIZE];
-/* 5 bytes per char + 3 bytes per line */
-static char file_buffer_c[COPY_BUFSIZE * 5 + ((COPY_BUFSIZE / HEX_BYTES_PER_LINE) * 3)];
-
-char curSubdir[MAX_PATH_LEN];
-char lastFileVar[MAX_PATH_LEN];
-char hdr_buf[4096];
-
-unsigned char processSubs = 1;
-unsigned char includeHttpHeader = 1;
-unsigned char useHttp11 = 0;
-unsigned char precalcChksum = 0;
-
-int main(int argc, char *argv[])
-{
- FIND_T fInfo;
- FIND_RET_T fret;
- char path[MAX_PATH_LEN];
- char appPath[MAX_PATH_LEN];
- FILE *data_file;
- FILE *struct_file;
- int filesProcessed;
- int i;
- char targetfile[MAX_PATH_LEN];
- strcpy(targetfile, "fsdata.c");
-
- memset(path, 0, sizeof(path));
- memset(appPath, 0, sizeof(appPath));
-
- printf(NEWLINE " makefsdata - HTML to C source converter" NEWLINE);
- printf(" by Jim Pettinato - circa 2003 " NEWLINE);
- printf(" extended by Simon Goldschmidt - 2009 " NEWLINE NEWLINE);
-
- strcpy(path, "fs");
- for(i = 1; i < argc; i++) {
- if (argv[i][0] == '-') {
- if (strstr(argv[i], "-s")) {
- processSubs = 0;
- } else if (strstr(argv[i], "-e")) {
- includeHttpHeader = 0;
- } else if (strstr(argv[i], "-11")) {
- useHttp11 = 1;
- } else if (strstr(argv[i], "-c")) {
- precalcChksum = 1;
- } else if((argv[i][1] == 'f') && (argv[i][2] == ':')) {
- strcpy(targetfile, &argv[i][3]);
- printf("Writing to file \"%s\"\n", targetfile);
- }
- } else {
- strcpy(path, argv[i]);
- }
- }
-
- /* if command line param or subdir named 'fs' not found spout usage verbiage */
- fret = FINDFIRST_DIR(path, &fInfo);
- if (!FINDFIRST_SUCCEEDED(fret)) {
- /* if no subdir named 'fs' (or the one which was given) exists, spout usage verbiage */
- printf(" Failed to open directory \"%s\"." NEWLINE NEWLINE, path);
- printf(" Usage: htmlgen [targetdir] [-s] [-i] [-f:<filename>]" NEWLINE NEWLINE);
- printf(" targetdir: relative or absolute path to files to convert" NEWLINE);
- printf(" switch -s: toggle processing of subdirectories (default is on)" NEWLINE);
- printf(" switch -e: exclude HTTP header from file (header is created at runtime, default is off)" NEWLINE);
- printf(" switch -11: include HTTP 1.1 header (1.0 is default)" NEWLINE);
- printf(" switch -c: precalculate checksums for all pages (default is off)" NEWLINE);
- printf(" switch -f: target filename (default is \"fsdata.c\")" NEWLINE);
- printf(" if targetdir not specified, htmlgen will attempt to" NEWLINE);
- printf(" process files in subdirectory 'fs'" NEWLINE);
- exit(-1);
- }
-
- printf("HTTP %sheader will %s statically included." NEWLINE,
- (includeHttpHeader ? (useHttp11 ? "1.1 " : "1.0 ") : ""),
- (includeHttpHeader ? "be" : "not be"));
-
- sprintf(curSubdir, ""); /* start off in web page's root directory - relative paths */
- printf(" Processing all files in directory %s", path);
- if (processSubs) {
- printf(" and subdirectories..." NEWLINE NEWLINE);
- } else {
- printf("..." NEWLINE NEWLINE);
- }
-
- GETCWD(appPath, MAX_PATH_LEN);
- data_file = fopen("fsdata.tmp", "wb");
- if (data_file == NULL) {
- printf("Failed to create file \"fsdata.tmp\"\n");
- exit(-1);
- }
- struct_file = fopen("fshdr.tmp", "wb");
- if (struct_file == NULL) {
- printf("Failed to create file \"fshdr.tmp\"\n");
- exit(-1);
- }
-
- CHDIR(path);
-
- fprintf(data_file, "#include \"fs.h\"" NEWLINE);
- fprintf(data_file, "#include \"lwip/def.h\"" NEWLINE);
- fprintf(data_file, "#include \"fsdata.h\"" NEWLINE NEWLINE NEWLINE);
-
- fprintf(data_file, "#define file_NULL (struct fsdata_file *) NULL" NEWLINE NEWLINE NEWLINE);
-
- sprintf(lastFileVar, "NULL");
-
- filesProcessed = process_sub(data_file, struct_file);
-
- /* data_file now contains all of the raw data.. now append linked list of
- * file header structs to allow embedded app to search for a file name */
- fprintf(data_file, NEWLINE NEWLINE);
- fprintf(struct_file, "#define FS_ROOT file_%s" NEWLINE, lastFileVar);
- fprintf(struct_file, "#define FS_NUMFILES %d" NEWLINE NEWLINE, filesProcessed);
-
- fclose(data_file);
- fclose(struct_file);
-
- CHDIR(appPath);
- /* append struct_file to data_file */
- printf(NEWLINE "Creating target file..." NEWLINE NEWLINE);
- concat_files("fsdata.tmp", "fshdr.tmp", targetfile);
-
- /* if succeeded, delete the temporary files */
- remove("fsdata.tmp");
- remove("fshdr.tmp");
-
- printf(NEWLINE "Processed %d files - done." NEWLINE NEWLINE, filesProcessed);
-
- return 0;
-}
-
-static void copy_file(const char *filename_in, FILE *fout)
-{
- FILE *fin;
- size_t len;
- fin = fopen(filename_in, "rb");
- if (fin == NULL) {
- printf("Failed to open file \"%s\"\n", filename_in);
- exit(-1);
- }
-
- while((len = fread(file_buffer_raw, 1, COPY_BUFSIZE, fin)) > 0)
- {
- fwrite(file_buffer_raw, 1, len, fout);
- }
- fclose(fin);
-}
-
-void concat_files(const char *file1, const char *file2, const char *targetfile)
-{
- FILE *fout;
- fout = fopen(targetfile, "wb");
- if (fout == NULL) {
- printf("Failed to open file \"%s\"\n", targetfile);
- exit(-1);
- }
- copy_file(file1, fout);
- copy_file(file2, fout);
- fclose(fout);
-}
-
-int process_sub(FILE *data_file, FILE *struct_file)
-{
- FIND_T fInfo;
- FIND_RET_T fret;
- int filesProcessed = 0;
- char oldSubdir[MAX_PATH_LEN];
-
- if (processSubs) {
- /* process subs recursively */
- strcpy(oldSubdir, curSubdir);
- fret = FINDFIRST_DIR("*", &fInfo);
- if (FINDFIRST_SUCCEEDED(fret)) {
- do {
- const char *curName = FIND_T_FILENAME(fInfo);
- if (curName == NULL) continue;
- if (curName[0] == '.') continue;
- if (strcmp(curName, "CVS") == 0) continue;
- if (!FIND_T_IS_DIR(fInfo)) continue;
- CHDIR(curName);
- strcat(curSubdir, "/");
- strcat(curSubdir, curName);
- printf(NEWLINE "processing subdirectory %s/..." NEWLINE, curSubdir);
- filesProcessed += process_sub(data_file, struct_file);
- CHDIR("..");
- strcpy(curSubdir, oldSubdir);
- } while (FINDNEXT_SUCCEEDED(FINDNEXT(fret, &fInfo)));
- }
- }
-
- fret = FINDFIRST_FILE("*.*", &fInfo);
- if (FINDFIRST_SUCCEEDED(fret)) {
- /* at least one file in directory */
- do {
- if (FIND_T_IS_FILE(fInfo)) {
- const char *curName = FIND_T_FILENAME(fInfo);
- printf("processing %s/%s..." NEWLINE, curSubdir, curName);
- if (process_file(data_file, struct_file, curName) < 0) {
- printf(NEWLINE "Error... aborting" NEWLINE);
- return -1;
- }
- filesProcessed++;
- }
- } while (FINDNEXT_SUCCEEDED(FINDNEXT(fret, &fInfo)));
- }
- return filesProcessed;
-}
-
-int get_file_size(const char* filename)
-{
- FILE *inFile;
- int file_size = -1;
- inFile = fopen(filename, "rb");
- if (inFile == NULL) {
- printf("Failed to open file \"%s\"\n", filename);
- exit(-1);
- }
- fseek(inFile, 0, SEEK_END);
- file_size = ftell(inFile);
- fclose(inFile);
- return file_size;
-}
-
-void process_file_data(const char *filename, FILE *data_file)
-{
- FILE *source_file;
- size_t len, written, i, src_off=0;
-
- source_file = fopen(filename, "rb");
-
- do {
- size_t off = 0;
- len = fread(file_buffer_raw, 1, COPY_BUFSIZE, source_file);
- if (len > 0) {
- for (i = 0; i < len; i++) {
- sprintf(&file_buffer_c[off], "0x%02.2x,", file_buffer_raw[i]);
- off += 5;
- if ((++src_off % HEX_BYTES_PER_LINE) == 0) {
- memcpy(&file_buffer_c[off], NEWLINE, NEWLINE_LEN);
- off += NEWLINE_LEN;
- }
- }
- written = fwrite(file_buffer_c, 1, off, data_file);
- }
- } while(len > 0);
- fclose(source_file);
-}
-
-int write_checksums(FILE *struct_file, const char *filename, const char *varname,
- u16_t hdr_len, u16_t hdr_chksum)
-{
- int chunk_size = TCP_MSS;
- int offset;
- size_t len;
- int i = 0;
- FILE *f;
-#if LWIP_TCP_TIMESTAMPS
- /* when timestamps are used, usable space is 12 bytes less per segment */
- chunk_size -= 12;
-#endif
-
- fprintf(struct_file, "#if HTTPD_PRECALCULATED_CHECKSUM" NEWLINE);
- fprintf(struct_file, "const struct fsdata_chksum chksums_%s[] = {" NEWLINE, varname);
-
- memset(file_buffer_raw, 0xab, sizeof(file_buffer_raw));
- f = fopen(filename, "rb");
- if (f == INVALID_HANDLE_VALUE) {
- printf("Failed to open file \"%s\"\n", filename);
- exit(-1);
- }
- if (hdr_len > 0) {
- /* add checksum for HTTP header */
- fprintf(struct_file, "{%d, 0x%04x, %d}," NEWLINE, 0, hdr_chksum, hdr_len);
- i++;
- }
- for (offset = hdr_len; ; offset += len) {
- unsigned short chksum;
- len = fread(file_buffer_raw, 1, chunk_size, f);
- if (len == 0) {
- break;
- }
- chksum = ~inet_chksum(file_buffer_raw, (u16_t)len);
- /* add checksum for data */
- fprintf(struct_file, "{%d, 0x%04x, %d}," NEWLINE, offset, chksum, len);
- i++;
- }
- fclose(f);
- fprintf(struct_file, "};" NEWLINE);
- fprintf(struct_file, "#endif /* HTTPD_PRECALCULATED_CHECKSUM */" NEWLINE);
- return i;
-}
-
-int process_file(FILE *data_file, FILE *struct_file, const char *filename)
-{
- char *pch;
- char varname[MAX_PATH_LEN];
- int i = 0;
- char qualifiedName[MAX_PATH_LEN];
- int file_size;
- u16_t http_hdr_chksum = 0;
- u16_t http_hdr_len = 0;
- int chksum_count = 0;
-
- /* create qualified name (TODO: prepend slash or not?) */
- sprintf(qualifiedName,"%s/%s", curSubdir, filename);
- /* create C variable name */
- strcpy(varname, qualifiedName);
- /* convert slashes & dots to underscores */
- while ((pch = strpbrk(varname, "./\\")) != NULL) {
- *pch = '_';
- }
-#if ALIGN_PAYLOAD
- /* to force even alignment of array */
- fprintf(data_file, "static const " PAYLOAD_ALIGN_TYPE " dummy_align_%s = %d;" NEWLINE, varname, payload_alingment_dummy_counter++);
-#endif /* ALIGN_PAYLOAD */
- fprintf(data_file, "static const unsigned char data_%s[] = {" NEWLINE, varname);
- /* encode source file name (used by file system, not returned to browser) */
- fprintf(data_file, "/* %s (%d chars) */" NEWLINE, qualifiedName, strlen(qualifiedName)+1);
- file_put_ascii(data_file, qualifiedName, strlen(qualifiedName)+1, &i);
-#if ALIGN_PAYLOAD
- /* pad to even number of bytes to assure payload is on aligned boundary */
- while(i % PAYLOAD_ALIGNMENT != 0) {
- fprintf(data_file, "0x%02.2x,", 0);
- i++;
- }
-#endif /* ALIGN_PAYLOAD */
- fprintf(data_file, NEWLINE);
-
- file_size = get_file_size(filename);
- if (includeHttpHeader) {
- file_write_http_header(data_file, filename, file_size, &http_hdr_len, &http_hdr_chksum);
- }
- if (precalcChksum) {
- chksum_count = write_checksums(struct_file, filename, varname, http_hdr_len, http_hdr_chksum);
- }
-
- /* build declaration of struct fsdata_file in temp file */
- fprintf(struct_file, "const struct fsdata_file file_%s[] = { {" NEWLINE, varname);
- fprintf(struct_file, "file_%s," NEWLINE, lastFileVar);
- fprintf(struct_file, "data_%s," NEWLINE, varname);
- fprintf(struct_file, "data_%s + %d," NEWLINE, varname, i);
- fprintf(struct_file, "sizeof(data_%s) - %d," NEWLINE, varname, i);
- fprintf(struct_file, "%d," NEWLINE, includeHttpHeader);
- if (precalcChksum) {
- fprintf(struct_file, "#if HTTPD_PRECALCULATED_CHECKSUM" NEWLINE);
- fprintf(struct_file, "%d, chksums_%s," NEWLINE, chksum_count, varname);
- fprintf(struct_file, "#endif /* HTTPD_PRECALCULATED_CHECKSUM */" NEWLINE);
- }
- fprintf(struct_file, "}};" NEWLINE NEWLINE);
- strcpy(lastFileVar, varname);
-
- /* write actual file contents */
- i = 0;
- fprintf(data_file, NEWLINE "/* raw file data (%d bytes) */" NEWLINE, file_size);
- process_file_data(filename, data_file);
- fprintf(data_file, "};" NEWLINE NEWLINE);
-
- return 0;
-}
-
-int file_write_http_header(FILE *data_file, const char *filename, int file_size,
- u16_t *http_hdr_len, u16_t *http_hdr_chksum)
-{
- int i = 0;
- int response_type = HTTP_HDR_OK;
- int file_type = HTTP_HDR_DEFAULT_TYPE;
- const char *cur_string;
- size_t cur_len;
- int written = 0;
- size_t hdr_len = 0;
- u16_t acc;
- const char *file_ext;
- int j;
-
- memset(hdr_buf, 0, sizeof(hdr_buf));
-
- if (useHttp11) {
- response_type = HTTP_HDR_OK_11;
- }
-
- fprintf(data_file, NEWLINE "/* HTTP header */");
- if (strstr(filename, "404") == filename) {
- response_type = HTTP_HDR_NOT_FOUND;
- if (useHttp11) {
- response_type = HTTP_HDR_NOT_FOUND_11;
- }
- } else if (strstr(filename, "400") == filename) {
- response_type = HTTP_HDR_BAD_REQUEST;
- if (useHttp11) {
- response_type = HTTP_HDR_BAD_REQUEST_11;
- }
- } else if (strstr(filename, "501") == filename) {
- response_type = HTTP_HDR_NOT_IMPL;
- if (useHttp11) {
- response_type = HTTP_HDR_NOT_IMPL_11;
- }
- }
- cur_string = g_psHTTPHeaderStrings[response_type];
- cur_len = strlen(cur_string);
- fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len);
- written += file_put_ascii(data_file, cur_string, cur_len, &i);
- i = 0;
- if (precalcChksum) {
- memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
- hdr_len += cur_len;
- }
-
- cur_string = serverID;
- cur_len = strlen(cur_string);
- fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len);
- written += file_put_ascii(data_file, cur_string, cur_len, &i);
- i = 0;
- if (precalcChksum) {
- memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
- hdr_len += cur_len;
- }
-
- file_ext = filename;
- while(strstr(file_ext, ".") != NULL) {
- file_ext = strstr(file_ext, ".");
- file_ext++;
- }
- if((file_ext == NULL) || (*file_ext == 0)) {
- printf("failed to get extension for file \"%s\", using default.\n", filename);
- } else {
- for(j = 0; j < NUM_HTTP_HEADERS; j++) {
- if(!strcmp(file_ext, g_psHTTPHeaders[j].extension)) {
- file_type = g_psHTTPHeaders[j].headerIndex;
- break;
- }
- }
- if (j >= NUM_HTTP_HEADERS) {
- printf("failed to get file type for extension \"%s\", using default.\n", file_ext);
- file_type = HTTP_HDR_DEFAULT_TYPE;
- }
- }
-
- if (useHttp11) {
- char intbuf[MAX_PATH_LEN];
- memset(intbuf, 0, sizeof(intbuf));
-
- cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONTENT_LENGTH];
- cur_len = strlen(cur_string);
- fprintf(data_file, NEWLINE "/* \"%s%d\r\n\" (%d+ bytes) */" NEWLINE, cur_string, file_size, cur_len+2);
- written += file_put_ascii(data_file, cur_string, cur_len, &i);
- if (precalcChksum) {
- memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
- hdr_len += cur_len;
- }
-
- _itoa(file_size, intbuf, 10);
- strcat(intbuf, "\r\n");
- cur_len = strlen(intbuf);
- written += file_put_ascii(data_file, intbuf, cur_len, &i);
- i = 0;
- if (precalcChksum) {
- memcpy(&hdr_buf[hdr_len], intbuf, cur_len);
- hdr_len += cur_len;
- }
-
- cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONN_CLOSE];
- cur_len = strlen(cur_string);
- fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len);
- written += file_put_ascii(data_file, cur_string, cur_len, &i);
- i = 0;
- if (precalcChksum) {
- memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
- hdr_len += cur_len;
- }
- }
-
- cur_string = g_psHTTPHeaderStrings[file_type];
- cur_len = strlen(cur_string);
- fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len);
- written += file_put_ascii(data_file, cur_string, cur_len, &i);
- i = 0;
- if (precalcChksum) {
- memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
- hdr_len += cur_len;
-
- LWIP_ASSERT("hdr_len <= 0xffff", hdr_len <= 0xffff);
- LWIP_ASSERT("strlen(hdr_buf) == hdr_len", strlen(hdr_buf) == hdr_len);
- acc = ~inet_chksum(hdr_buf, (u16_t)hdr_len);
- *http_hdr_len = (u16_t)hdr_len;
- *http_hdr_chksum = acc;
- }
-
- return written;
-}
-
-int file_put_ascii(FILE *file, const char* ascii_string, int len, int *i)
-{
- int x;
- for(x = 0; x < len; x++) {
- unsigned char cur = ascii_string[x];
- fprintf(file, "0x%02.2x,", cur);
- if ((++(*i) % HEX_BYTES_PER_LINE) == 0) {
- fprintf(file, NEWLINE);
- }
- }
- return len;
-}
-
-int s_put_ascii(char *buf, const char *ascii_string, int len, int *i)
-{
- int x;
- int idx = 0;
- for(x = 0; x < len; x++) {
- unsigned char cur = ascii_string[x];
- sprintf(&buf[idx], "0x%02.2x,", cur);
- idx += 5;
- if ((++(*i) % HEX_BYTES_PER_LINE) == 0) {
- sprintf(&buf[idx], NEWLINE);
- idx += NEWLINE_LEN;
- }
- }
- return len;
-}
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/* Standard includes. */\r
-#include <string.h>\r
-\r
-/* FreeRTOS includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-/* lwIP core includes */\r
-#include "lwip/opt.h"\r
-#include "lwip/tcpip.h"\r
-\r
-/* lwIP netif includes */\r
-#include "netif/etharp.h"\r
-\r
-/* applications includes */\r
-#include "apps/httpserver_raw/httpd.h"\r
-\r
-/* The constants that define the IP address, net mask, gateway address and MAC\r
-address are located at the bottom of FreeRTOSConfig.h. */\r
-#define LWIP_PORT_INIT_IPADDR(addr) IP4_ADDR((addr), configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 )\r
-#define LWIP_PORT_INIT_GW(addr) IP4_ADDR((addr), configGW_IP_ADDR0, configGW_IP_ADDR1, configGW_IP_ADDR2, configGW_IP_ADDR3 )\r
-#define LWIP_PORT_INIT_NETMASK(addr) IP4_ADDR((addr), configNET_MASK0,configNET_MASK1,configNET_MASK2,configNET_MASK3)\r
-#define LWIP_MAC_ADDR_BASE { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 }\r
-\r
-/* Definitions of the various SSI callback functions within the pccSSITags\r
-array. If pccSSITags is updated, then these definitions must also be updated. */\r
-#define ssiTASK_STATS_INDEX 0\r
-#define ssiRUN_TIME_STATS_INDEX 1\r
-\r
-/*\r
- * The SSI handler callback function passed to lwIP.\r
- */\r
-static unsigned short uslwIPAppsSSIHandler( int iIndex, char *pcBuffer, int iBufferLength );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The SSI strings that are embedded in the served html files. If this array\r
-is changed, then the index position defined by the #defines such as\r
-ssiTASK_STATS_INDEX above must also be updated. */\r
-static const char *pccSSITags[] =\r
-{\r
- "rtos_stats",\r
- "run_stats"\r
-};\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Called from the TCP/IP thread. */\r
-void lwIPAppsInit( void *pvArgument )\r
-{\r
-ip_addr_t xIPAddr, xNetMask, xGateway;\r
-extern err_t ethernetif_init( struct netif *xNetIf );\r
-static struct netif xNetIf;\r
-\r
- ( void ) pvArgument;\r
-\r
- /* Set up the network interface. */\r
- ip_addr_set_zero( &xGateway );\r
- ip_addr_set_zero( &xIPAddr );\r
- ip_addr_set_zero( &xNetMask );\r
-\r
- LWIP_PORT_INIT_GW(&xGateway);\r
- LWIP_PORT_INIT_IPADDR(&xIPAddr);\r
- LWIP_PORT_INIT_NETMASK(&xNetMask);\r
-\r
- netif_set_default( netif_add( &xNetIf, &xIPAddr, &xNetMask, &xGateway, NULL, ethernetif_init, tcpip_input ) );\r
- netif_set_up( &xNetIf );\r
-\r
- /* Initialise the raw http server. */\r
- httpd_init();\r
-\r
- /* Install the server side include handler. */\r
- http_set_ssi_handler( uslwIPAppsSSIHandler, pccSSITags, sizeof( pccSSITags ) / sizeof( char * ) );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static unsigned short uslwIPAppsSSIHandler( int iIndex, char *pcBuffer, int iBufferLength )\r
-{\r
-static unsigned int uiUpdateCount = 0;\r
-static char cUpdateString[ 200 ];\r
-extern char *pcMainGetTaskStatusMessage( void );\r
-\r
- /* Unused parameter. */\r
- ( void ) iBufferLength;\r
-\r
- /* The SSI handler function that generates text depending on the index of\r
- the SSI tag encountered. */\r
-\r
- switch( iIndex )\r
- {\r
- case ssiTASK_STATS_INDEX :\r
- vTaskList( pcBuffer );\r
- break;\r
-\r
- case ssiRUN_TIME_STATS_INDEX :\r
- vTaskGetRunTimeStats( pcBuffer );\r
- break;\r
- }\r
-\r
- /* Include a count of the number of times an SSI function has been executed\r
- in the returned string. */\r
- uiUpdateCount++;\r
- sprintf( cUpdateString, "\r\n\r\n%u\r\nStatus - %s", uiUpdateCount, pcMainGetTaskStatusMessage() );\r
- strcat( pcBuffer, cUpdateString );\r
- return strlen( pcBuffer );\r
-}\r
-\r
+++ /dev/null
-
-#define LWIP_PORT_INIT_IPADDR(addr) IP4_ADDR((addr), configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 )
-#define LWIP_PORT_INIT_GW(addr) IP4_ADDR((addr), configGW_IP_ADDR0, configGW_IP_ADDR1, configGW_IP_ADDR2, configGW_IP_ADDR3 )
-#define LWIP_PORT_INIT_NETMASK(addr) IP4_ADDR((addr), configNET_MASK0,configNET_MASK1,configNET_MASK2,configNET_MASK3)
-
-/* remember to change this MAC address to suit your needs!
- the last octet will be increased by netif->num for each netif */
-#define LWIP_MAC_ADDR_BASE { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 }
-
-/* configuration for applications */
-
-#define LWIP_CHARGEN_APP 0
-#define LWIP_DNS_APP 0
-#define LWIP_HTTPD_APP 1
-
+++ /dev/null
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef __LWIPOPTS_H__
-#define __LWIPOPTS_H__
-
-#include "xparameters.h"
-
-/* Define platform endianness (might already be defined) */
-#ifndef BYTE_ORDER
- #if XPAR_MICROBLAZE_0_ENDIANNESS == 1
- #define BYTE_ORDER LITTLE_ENDIAN
- #else
- #define BYTE_ORDER BIG_ENDIAN
- #endif
-#endif /* BYTE_ORDER */
-
-/* Using the Lite Ethernet IP. */
-#define XLWIP_CONFIG_INCLUDE_EMACLITE 1
-
-/* SSI options. */
-#define TCPIP_THREAD_NAME "tcpip"
-#define LWIP_HTTPD_MAX_TAG_NAME_LEN 20
-#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 1500
-#define TCPIP_THREAD_PRIO configLWIP_TASK_PRIORITY
-#define TCPIP_THREAD_STACKSIZE configMINIMAL_STACK_SIZE * 3
-
-/* MBox sizes cannot be zer, which is their default. */
-#define DEFAULT_TCP_RECVMBOX_SIZE 5
-#define DEFAULT_ACCEPTMBOX_SIZE 5
-#define TCPIP_MBOX_SIZE 10
-
-/* FreeRTOS is used. */
-#define NO_SYS 0
-
-/* In this example, sockets are not used, only the raw API. */
-#define LWIP_SOCKET 0
-
-/* In this example, only the raw API is used. */
-#define LWIP_NETCONN 0
-
-/* SNMP and IGMP are not required by this simple demo. ICMP is always useful
-though. */
-#define LWIP_SNMP 0
-#define LWIP_IGMP 0
-#define LWIP_ICMP 1
-
-/* DNS is not going to be used as this is a simple local example. */
-#define LWIP_DNS 0
-
-#define LWIP_HAVE_LOOPIF 0
-#define TCP_LISTEN_BACKLOG 0
-#define LWIP_SO_RCVTIMEO 1
-#define LWIP_SO_RCVBUF 1
-
-#ifdef LWIP_DEBUG
- #define LWIP_DBG_MIN_LEVEL 0
- #define PPP_DEBUG LWIP_DBG_OFF
- #define MEM_DEBUG LWIP_DBG_ON
- #define MEMP_DEBUG LWIP_DBG_ON
- #define PBUF_DEBUG LWIP_DBG_ON
- #define API_LIB_DEBUG LWIP_DBG_OFF
- #define API_MSG_DEBUG LWIP_DBG_OFF
- #define TCPIP_DEBUG LWIP_DBG_OFF
- #define NETIF_DEBUG LWIP_DBG_OFF
- #define SOCKETS_DEBUG LWIP_DBG_OFF
- #define DNS_DEBUG LWIP_DBG_OFF
- #define AUTOIP_DEBUG LWIP_DBG_OFF
- #define DHCP_DEBUG LWIP_DBG_OFF
- #define IP_DEBUG LWIP_DBG_OFF
- #define IP_REASS_DEBUG LWIP_DBG_OFF
- #define ICMP_DEBUG LWIP_DBG_OFF
- #define IGMP_DEBUG LWIP_DBG_OFF
- #define UDP_DEBUG LWIP_DBG_OFF
- #define TCP_DEBUG LWIP_DBG_OFF
- #define TCP_INPUT_DEBUG LWIP_DBG_OFF
- #define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
- #define TCP_RTO_DEBUG LWIP_DBG_OFF
- #define TCP_CWND_DEBUG LWIP_DBG_OFF
- #define TCP_WND_DEBUG LWIP_DBG_OFF
- #define TCP_FR_DEBUG LWIP_DBG_OFF
- #define TCP_QLEN_DEBUG LWIP_DBG_OFF
- #define TCP_RST_DEBUG LWIP_DBG_OFF
-#endif
-
-#define LWIP_DBG_TYPES_ON (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH|LWIP_DBG_HALT)
-
-
-
-/* ---------- Memory options ---------- */
-/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
- lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
- byte alignment -> define MEM_ALIGNMENT to 2. */
-/* MSVC port: intel processors don't need 4-byte alignment,
- but are faster that way! */
-#define MEM_ALIGNMENT 4
-
-/* MEM_SIZE: the size of the heap memory. If the application will send
-a lot of data that needs to be copied, this should be set high. */
-#define MEM_SIZE 10240
-
-/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
- sends a lot of data out of ROM (or other static memory), this
- should be set high. */
-#define MEMP_NUM_PBUF 10
-
-/* MEMP_NUM_RAW_PCB: the number of UDP protocol control blocks. One
- per active RAW "connection". */
-#define LWIP_RAW 0
-#define MEMP_NUM_RAW_PCB 0
-
-/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
- per active UDP "connection". */
-#define MEMP_NUM_UDP_PCB 2
-
-/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
- connections. */
-#define MEMP_NUM_TCP_PCB 40
-
-/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
- connections. */
-#define MEMP_NUM_TCP_PCB_LISTEN 2
-
-/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
- segments. */
-#define MEMP_NUM_TCP_SEG 10
-
-/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
- timeouts. */
-#define MEMP_NUM_SYS_TIMEOUT 15
-
-/* The following four are used only with the sequential API and can be
- set to 0 if the application only will use the raw API. */
-/* MEMP_NUM_NETBUF: the number of struct netbufs. */
-#define MEMP_NUM_NETBUF 0
-
-/* MEMP_NUM_NETCONN: the number of struct netconns. */
-#define MEMP_NUM_NETCONN 0
-
-/* MEMP_NUM_TCPIP_MSG_*: the number of struct tcpip_msg, which is used
- for sequential API communication and incoming packets. Used in
- src/api/tcpip.c. */
-#define MEMP_NUM_TCPIP_MSG_API 4
-#define MEMP_NUM_TCPIP_MSG_INPKT 4
-
-#define MEMP_NUM_ARP_QUEUE 5
-
-/* ---------- Pbuf options ---------- */
-/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
-#define PBUF_POOL_SIZE 10
-
-/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-#define PBUF_POOL_BUFSIZE 375
-
-/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
- link level header. */
-#define PBUF_LINK_HLEN 16
-
-/** SYS_LIGHTWEIGHT_PROT
- * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
- * for certain critical regions during buffer allocation, deallocation and memory
- * allocation and deallocation.
- */
-#define SYS_LIGHTWEIGHT_PROT (NO_SYS==0)
-
-
-/* ---------- TCP options ---------- */
-#define LWIP_TCP 1
-#define TCP_TTL 255
-
-/* Controls if TCP should queue segments that arrive out of
- order. Define to 0 if your device is low on memory. */
-#define TCP_QUEUE_OOSEQ 1
-
-/* TCP Maximum segment size. */
-#define TCP_MSS 1460
-
-/* TCP sender buffer space (bytes). */
-#define TCP_SND_BUF ( TCP_MSS * 2 )
-
-/* TCP sender buffer space (pbufs). This must be at least = 2 *
- TCP_SND_BUF/TCP_MSS for things to work. */
-#define TCP_SND_QUEUELEN (4 * TCP_SND_BUF/TCP_MSS)
-
-/* TCP writable space (bytes). This must be less than or equal
- to TCP_SND_BUF. It is the amount of space which must be
- available in the tcp snd_buf for select to return writable */
-#define TCP_SNDLOWAT (TCP_SND_BUF/2)
-
-/* TCP receive window. */
-#define TCP_WND ( PBUF_POOL_SIZE * PBUF_POOL_BUFSIZE )
-
-/* Maximum number of retransmissions of data segments. */
-#define TCP_MAXRTX 12
-
-/* Maximum number of retransmissions of SYN segments. */
-#define TCP_SYNMAXRTX 4
-
-
-/* ---------- ARP options ---------- */
-#define LWIP_ARP 1
-#define ARP_TABLE_SIZE 10
-#define ARP_QUEUEING 1
-
-
-/* ---------- IP options ---------- */
-/* Define IP_FORWARD to 1 if you wish to have the ability to forward
- IP packets across network interfaces. If you are going to run lwIP
- on a device with only one network interface, define this to 0. */
-#define IP_FORWARD 0
-
-/* IP reassembly and segmentation.These are orthogonal even
- * if they both deal with IP fragments */
-#define IP_REASSEMBLY 0
-#define IP_REASS_MAX_PBUFS 10
-#define MEMP_NUM_REASSDATA 10
-#define IP_FRAG 0
-
-
-/* ---------- ICMP options ---------- */
-#define ICMP_TTL 255
-
-
-/* ---------- DHCP options ---------- */
-/* Define LWIP_DHCP to 1 if you want DHCP configuration of
- interfaces. */
-#define LWIP_DHCP 0
-
-/* 1 if you want to do an ARP check on the offered address
- (recommended). */
-#define DHCP_DOES_ARP_CHECK (LWIP_DHCP)
-
-
-/* ---------- AUTOIP options ------- */
-#define LWIP_AUTOIP 0
-#define LWIP_DHCP_AUTOIP_COOP (LWIP_DHCP && LWIP_AUTOIP)
-
-
-/* ---------- UDP options ---------- */
-#define LWIP_UDP 1
-#define LWIP_UDPLITE 1
-#define UDP_TTL 255
-
-
-/* ---------- Statistics options ---------- */
-
-#define LWIP_STATS 1
-#define LWIP_STATS_DISPLAY 0
-
-#if LWIP_STATS
- #define LINK_STATS 1
- #define IP_STATS 1
- #define ICMP_STATS 0
- #define IGMP_STATS 0
- #define IPFRAG_STATS 0
- #define UDP_STATS 1
- #define TCP_STATS 1
- #define MEM_STATS 1
- #define MEMP_STATS 1
- #define PBUF_STATS 1
- #define SYS_STATS 1
-#endif /* LWIP_STATS */
-
-
-/* ---------- PPP options ---------- */
-
-#define PPP_SUPPORT 0 /* Set > 0 for PPP */
-
-#if PPP_SUPPORT
-
- #define NUM_PPP 1 /* Max PPP sessions. */
-
- /* Select modules to enable. Ideally these would be set in the makefile but
- * we're limited by the command line length so you need to modify the settings
- * in this file.
- */
- #define PPPOE_SUPPORT 1
- #define PPPOS_SUPPORT 1
- #define PAP_SUPPORT 1 /* Set > 0 for PAP. */
- #define CHAP_SUPPORT 1 /* Set > 0 for CHAP. */
- #define MSCHAP_SUPPORT 0 /* Set > 0 for MSCHAP (NOT FUNCTIONAL!) */
- #define CBCP_SUPPORT 0 /* Set > 0 for CBCP (NOT FUNCTIONAL!) */
- #define CCP_SUPPORT 0 /* Set > 0 for CCP (NOT FUNCTIONAL!) */
- #define VJ_SUPPORT 1 /* Set > 0 for VJ header compression. */
- #define MD5_SUPPORT 1 /* Set > 0 for MD5 (see also CHAP) */
-
-#endif /* PPP_SUPPORT */
-
-#endif /* __LWIPOPTS_H__ */
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * main-blinky.c is included when the "Blinky" build configuration is used.\r
- * main-full.c is included when the "Full" build configuration is used.\r
- *\r
- * main-blinky.c (this file) defines a very simple demo that creates two tasks,\r
- * one queue, and one timer. It also demonstrates how MicroBlaze interrupts\r
- * can interact with FreeRTOS tasks/timers.\r
- *\r
- * This simple demo project was developed and tested on the Spartan-6 SP605\r
- * development board, using the hardware configuration found in the hardware\r
- * project that is already included in the Eclipse project.\r
- *\r
- * The idle hook function:\r
- * The idle hook function demonstrates how to query the amount of FreeRTOS heap\r
- * space that is remaining (see vApplicationIdleHook() defined in this file).\r
- *\r
- * The main() Function:\r
- * main() creates one software timer, one queue, and two tasks. It then starts\r
- * the scheduler.\r
- *\r
- * The Queue Send Task:\r
- * The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
- * block for 200 milliseconds, before sending the value 100 to the queue that\r
- * was created within main(). Once the value is sent, the task loops back\r
- * around to block for another 200 milliseconds.\r
- *\r
- * The Queue Receive Task:\r
- * The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() sits in a loop that causes it to\r
- * repeatedly attempt to read data from the queue that was created within\r
- * main(). When data is received, the task checks the value of the data, and\r
- * if the value equals the expected 100, toggles an LED. The 'block time'\r
- * parameter passed to the queue receive function specifies that the task\r
- * should be held in the Blocked state indefinitely to wait for data to be\r
- * available on the queue. The queue receive task will only leave the Blocked\r
- * state when the queue send task writes to the queue. As the queue send task\r
- * writes to the queue every 200 milliseconds, the queue receive task leaves\r
- * the Blocked state every 200 milliseconds, and therefore toggles the LED\r
- * every 200 milliseconds.\r
- *\r
- * The LED Software Timer and the Button Interrupt:\r
- * The user buttons are configured to generate an interrupt each time one is\r
- * pressed. The interrupt service routine switches an LED on, and resets the\r
- * LED software timer. The LED timer has a 5000 millisecond (5 second) period,\r
- * and uses a callback function that is defined to just turn the LED off again.\r
- * Therefore, pressing the user button will turn the LED on, and the LED will\r
- * remain on until a full five seconds pass without the button being pressed.\r
- */\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "queue.h"\r
-#include "timers.h"\r
-\r
-/* BSP includes. */\r
-#include "xtmrctr.h"\r
-#include "xgpio.h"\r
-\r
-/* Priorities at which the tasks are created. */\r
-#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-\r
-/* The rate at which data is sent to the queue, specified in milliseconds, and\r
-converted to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
-\r
-/* The number of items the queue can hold. This is 1 as the receive task\r
-will remove items as they are added because it has the higher priority, meaning\r
-the send task should always find the queue empty. */\r
-#define mainQUEUE_LENGTH ( 1 )\r
-\r
-/* The LED toggled by the queue receive task. */\r
-#define mainTASK_CONTROLLED_LED 0x01UL\r
-\r
-/* The LED turned on by the button interrupt, and turned off by the LED timer. */\r
-#define mainTIMER_CONTROLLED_LED 0x02UL\r
-\r
-/* A block time of 0 simply means, "don't block". */\r
-#define mainDONT_BLOCK ( TickType_t ) 0\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Setup the NVIC, LED outputs, and button inputs.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
-/*\r
- * The tasks as described in the comments at the top of this file.\r
- */\r
-static void prvQueueReceiveTask( void *pvParameters );\r
-static void prvQueueSendTask( void *pvParameters );\r
-\r
-/*\r
- * The LED timer callback function. This does nothing but switch off the\r
- * LED defined by the mainTIMER_CONTROLLED_LED constant.\r
- */\r
-static void vLEDTimerCallback( TimerHandle_t xTimer );\r
-\r
-/*\r
- * The handler executed each time a button interrupt is generated. This ensures\r
- * the LED defined by mainTIMER_CONTROLLED_LED is on, and resets the timer so\r
- * the timer will not turn the LED off for a full 5 seconds after the button\r
- * interrupt occurred.\r
- */\r
-static void prvButtonInputInterruptHandler( void *pvUnused );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The queue used by the queue send and queue receive tasks. */\r
-static QueueHandle_t xQueue = NULL;\r
-\r
-/* The LED software timer. This uses vLEDTimerCallback() as its callback\r
-function. */\r
-static TimerHandle_t xLEDTimer = NULL;\r
-\r
-/* Maintains the current LED output state. */\r
-static volatile unsigned char ucGPIOState = 0U;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Structures that hold the state of the various peripherals used by this demo.\r
-These are used by the Xilinx peripheral driver API functions. */\r
-static XTmrCtr xTimer0Instance;\r
-static XGpio xOutputGPIOInstance, xInputGPIOInstance;\r
-\r
-/* Constants required by the Xilinx peripheral driver API functions that are\r
-relevant to the particular hardware set up. */\r
-static const unsigned long ulGPIOOutputChannel = 1UL, ulGPIOInputChannel = 1UL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-int main( void )\r
-{\r
- /* *************************************************************************\r
- This is a very simple project suitable for getting started with FreeRTOS.\r
- If you would prefer a more complex project that demonstrates a lot more\r
- features and tests, then select the 'Full' build configuration within the\r
- SDK Eclipse IDE.\r
- ***************************************************************************/\r
-\r
- /* Configure the interrupt controller, LED outputs and button inputs. */\r
- prvSetupHardware();\r
-\r
- /* Create the queue used by the queue send and queue receive tasks as\r
- described in the comments at the top of this file. */\r
- xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
-\r
- /* Sanity check that the queue was created. */\r
- configASSERT( xQueue );\r
-\r
- /* Start the two tasks as described in the comments at the top of this\r
- file. */\r
- xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
- xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
-\r
- /* Create the software timer that is responsible for turning off the LED\r
- if the button is not pushed within 5000ms, as described at the top of\r
- this file. The timer is not actually started until a button interrupt is\r
- pushed, as it is not until that point that the LED is turned on. */\r
- xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */\r
- ( 5000 / portTICK_PERIOD_MS ),/* The timer period, in this case 5000ms (5s). */\r
- pdFALSE, /* This is a one shot timer, so xAutoReload is set to pdFALSE. */\r
- ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
- vLEDTimerCallback /* The callback function that switches the LED off. */\r
- );\r
-\r
- /* Start the tasks and timer running. */\r
- vTaskStartScheduler();\r
-\r
- /* If all is well, the scheduler will now be running, and the following line\r
- will never be reached. If the following line does execute, then there was\r
- insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
- to be created. See the memory management section on the FreeRTOS web site\r
- for more details. */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The callback is executed when the LED timer expires. */\r
-static void vLEDTimerCallback( TimerHandle_t xTimer )\r
-{\r
- /* The timer has expired - so no button pushes have occurred in the last\r
- five seconds - turn the LED off. NOTE - accessing the LED port should use\r
- a critical section because it is accessed from multiple tasks, and the\r
- button interrupt - in this trivial case, for simplicity, the critical\r
- section is omitted. */\r
- ucGPIOState &= ~mainTIMER_CONTROLLED_LED;\r
- XGpio_DiscreteWrite( &xOutputGPIOInstance, ulGPIOOutputChannel, ucGPIOState );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The ISR is executed when the user button is pushed. */\r
-static void prvButtonInputInterruptHandler( void *pvUnused )\r
-{\r
-long lHigherPriorityTaskWoken = pdFALSE;\r
-\r
- /* The button was pushed, so ensure the LED is on before resetting the\r
- LED timer. The LED timer will turn the LED off if the button is not\r
- pushed within 5000ms. */\r
- ucGPIOState |= mainTIMER_CONTROLLED_LED;\r
- XGpio_DiscreteWrite( &xOutputGPIOInstance, ulGPIOOutputChannel, ucGPIOState );\r
-\r
- /* Ensure only the ISR safe reset API function is used, as this is executed\r
- in an interrupt context. */\r
- xTimerResetFromISR( xLEDTimer, &lHigherPriorityTaskWoken );\r
-\r
- /* Clear the interrupt before leaving. */\r
- XGpio_InterruptClear( &xInputGPIOInstance, ulGPIOInputChannel );\r
-\r
- /* If calling xTimerResetFromISR() caused a task (in this case the timer\r
- service/daemon task) to unblock, and the unblocked task has a priority\r
- higher than or equal to the task that was interrupted, then\r
- lHigherPriorityTaskWoken will now be set to pdTRUE, and calling\r
- portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */\r
- portYIELD_FROM_ISR( lHigherPriorityTaskWoken );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueSendTask( void *pvParameters )\r
-{\r
-TickType_t xNextWakeTime;\r
-const unsigned long ulValueToSend = 100UL;\r
-\r
- /* Initialise xNextWakeTime - this only needs to be done once. */\r
- xNextWakeTime = xTaskGetTickCount();\r
-\r
- for( ;; )\r
- {\r
- /* Place this task in the blocked state until it is time to run again.\r
- The block time is specified in ticks, the constant used converts ticks\r
- to ms. While in the Blocked state this task will not consume any CPU\r
- time. */\r
- vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
-\r
- /* Send to the queue - causing the queue receive task to unblock and\r
- toggle an LED. 0 is used as the block time so the sending operation\r
- will not block - it shouldn't need to block as the queue should always\r
- be empty at this point in the code. */\r
- xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueReceiveTask( void *pvParameters )\r
-{\r
-unsigned long ulReceivedValue;\r
-\r
- for( ;; )\r
- {\r
- /* Wait until something arrives in the queue - this task will block\r
- indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
- FreeRTOSConfig.h. */\r
- xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
-\r
- /* To get here something must have been received from the queue, but\r
- is it the expected value? If it is, toggle the green LED. */\r
- if( ulReceivedValue == 100UL )\r
- {\r
- /* NOTE - accessing the LED port should use a critical section\r
- because it is accessed from multiple tasks, and the button interrupt\r
- - in this trivial case, for simplicity, the critical section is\r
- omitted. */\r
- if( ( ucGPIOState & mainTASK_CONTROLLED_LED ) != 0 )\r
- {\r
- ucGPIOState &= ~mainTASK_CONTROLLED_LED;\r
- }\r
- else\r
- {\r
- ucGPIOState |= mainTASK_CONTROLLED_LED;\r
- }\r
-\r
- XGpio_DiscreteWrite( &xOutputGPIOInstance, ulGPIOOutputChannel, ucGPIOState );\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupHardware( void )\r
-{\r
-portBASE_TYPE xStatus;\r
-const unsigned char ucSetToOutput = 0U;\r
-\r
- /* Initialize the GPIO for the LEDs. */\r
- xStatus = XGpio_Initialize( &xOutputGPIOInstance, XPAR_LEDS_4BITS_DEVICE_ID );\r
- if( xStatus == XST_SUCCESS )\r
- {\r
- /* All bits on this channel are going to be outputs (LEDs). */\r
- XGpio_SetDataDirection( &xOutputGPIOInstance, ulGPIOOutputChannel, ucSetToOutput );\r
-\r
- /* Start with all LEDs off. */\r
- ucGPIOState = 0U;\r
- XGpio_DiscreteWrite( &xOutputGPIOInstance, ulGPIOOutputChannel, ucGPIOState );\r
- }\r
-\r
- /* Initialise the GPIO for the button inputs. */\r
- if( xStatus == XST_SUCCESS )\r
- {\r
- xStatus = XGpio_Initialize( &xInputGPIOInstance, XPAR_PUSH_BUTTONS_4BITS_DEVICE_ID );\r
- }\r
-\r
- if( xStatus == XST_SUCCESS )\r
- {\r
- /* Install the handler defined in this task for the button input.\r
- *NOTE* The FreeRTOS defined xPortInstallInterruptHandler() API function\r
- must be used for this purpose. */\r
- xStatus = xPortInstallInterruptHandler( XPAR_MICROBLAZE_0_INTC_PUSH_BUTTONS_4BITS_IP2INTC_IRPT_INTR, prvButtonInputInterruptHandler, NULL );\r
-\r
- if( xStatus == pdPASS )\r
- {\r
- /* Set buttons to input. */\r
- XGpio_SetDataDirection( &xInputGPIOInstance, ulGPIOInputChannel, ~( ucSetToOutput ) );\r
-\r
- /* Enable the button input interrupts in the interrupt controller.\r
- *NOTE* The vPortEnableInterrupt() API function must be used for this\r
- purpose. */\r
- vPortEnableInterrupt( XPAR_MICROBLAZE_0_INTC_PUSH_BUTTONS_4BITS_IP2INTC_IRPT_INTR );\r
-\r
- /* Enable GPIO channel interrupts. */\r
- XGpio_InterruptEnable( &xInputGPIOInstance, ulGPIOInputChannel );\r
- XGpio_InterruptGlobalEnable( &xInputGPIOInstance );\r
- }\r
- }\r
-\r
- configASSERT( ( xStatus == pdPASS ) );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
- /* vApplicationMallocFailedHook() will only be called if\r
- configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
- function that will get called if a call to pvPortMalloc() fails.\r
- pvPortMalloc() is called internally by the kernel whenever a task, queue or\r
- semaphore is created. It is also called by various parts of the demo\r
- application. If heap_1.c or heap_2.c are used, then the size of the heap\r
- available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
- FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
- to query the size of free heap space that remains (although it does not\r
- provide information on how the remaining heap might be fragmented). */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* vApplicationStackOverflowHook() will only be called if\r
- configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2. The handle and name\r
- of the offending task will be passed into the hook function via its\r
- parameters. However, when a stack has overflowed, it is possible that the\r
- parameters will have been corrupted, in which case the pxCurrentTCB variable\r
- can be inspected directly. */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIdleHook( void )\r
-{\r
-#ifdef EXAMPLE_CODE_ONLY\r
-\r
- The following code can only be included if heap_1.c or heap_2.c is used in\r
- the project. By default, heap_3.c is used, so the example code is\r
- excluded. See http://www.freertos.org/a00111.html for more information on\r
- memory management options.\r
-\r
- volatile size_t xFreeHeapSpace;\r
-\r
- /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
- to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
- task. It is essential that code added to this hook function never attempts\r
- to block in any way (for example, call xQueueReceive() with a block time\r
- specified, or call vTaskDelay()). If the application makes use of the\r
- vTaskDelete() API function (as this demo application does) then it is also\r
- important that vApplicationIdleHook() is permitted to return to its calling\r
- function, because it is the responsibility of the idle task to clean up\r
- memory allocated by the kernel to any task that has since been deleted. */\r
-\r
- /* This implementation of vApplicationIdleHook() simply demonstrates how\r
- the xPortGetFreeHeapSize() function can be used. */\r
- xFreeHeapSpace = xPortGetFreeHeapSize();\r
-\r
- if( xFreeHeapSpace > 100 )\r
- {\r
- /* By now, the kernel has allocated everything it is going to, so\r
- if there is a lot of heap remaining unallocated then\r
- the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be\r
- reduced accordingly. */\r
- }\r
-#endif\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This is an application defined callback function used to install the tick\r
-interrupt handler. It is provided as an application callback because the kernel\r
-will run on lots of different MicroBlaze and FPGA configurations - not all of\r
-which will have the same timer peripherals defined or available. This example\r
-uses the AXI Timer 0. If that is available on your hardware platform then this\r
-example callback implementation should not require modification. The name of\r
-the interrupt handler that should be installed is vPortTickISR(), which the\r
-function below declares as an extern. */\r
-void vApplicationSetupTimerInterrupt( void )\r
-{\r
-portBASE_TYPE xStatus;\r
-const unsigned char ucTimerCounterNumber = ( unsigned char ) 0U;\r
-const unsigned long ulCounterValue = ( ( XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ / configTICK_RATE_HZ ) - 1UL );\r
-extern void vPortTickISR( void *pvUnused );\r
-\r
- /* Initialise the timer/counter. */\r
- xStatus = XTmrCtr_Initialize( &xTimer0Instance, XPAR_AXI_TIMER_0_DEVICE_ID );\r
-\r
- if( xStatus == XST_SUCCESS )\r
- {\r
- /* Install the tick interrupt handler as the timer ISR.\r
- *NOTE* The xPortInstallInterruptHandler() API function must be used for\r
- this purpose. */\r
- xStatus = xPortInstallInterruptHandler( XPAR_INTC_0_TMRCTR_0_VEC_ID, vPortTickISR, NULL );\r
- }\r
-\r
- if( xStatus == pdPASS )\r
- {\r
- /* Enable the timer interrupt in the interrupt controller.\r
- *NOTE* The vPortEnableInterrupt() API function must be used for this\r
- purpose. */\r
- vPortEnableInterrupt( XPAR_INTC_0_TMRCTR_0_VEC_ID );\r
-\r
- /* Configure the timer interrupt handler. */\r
- XTmrCtr_SetHandler( &xTimer0Instance, ( void * ) vPortTickISR, NULL );\r
-\r
- /* Set the correct period for the timer. */\r
- XTmrCtr_SetResetValue( &xTimer0Instance, ucTimerCounterNumber, ulCounterValue );\r
-\r
- /* Enable the interrupts. Auto-reload mode is used to generate a\r
- periodic tick. Note that interrupts are disabled when this function is\r
- called, so interrupts will not start to be processed until the first\r
- task has started to run. */\r
- XTmrCtr_SetOptions( &xTimer0Instance, ucTimerCounterNumber, ( XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION | XTC_DOWN_COUNT_OPTION ) );\r
-\r
- /* Start the timer. */\r
- XTmrCtr_Start( &xTimer0Instance, ucTimerCounterNumber );\r
- }\r
-\r
- /* Sanity check that the function executed as expected. */\r
- configASSERT( ( xStatus == pdPASS ) );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This is an application defined callback function used to clear whichever\r
-interrupt was installed by the the vApplicationSetupTimerInterrupt() callback\r
-function - in this case the interrupt generated by the AXI timer. It is\r
-provided as an application callback because the kernel will run on lots of\r
-different MicroBlaze and FPGA configurations - not all of which will have the\r
-same timer peripherals defined or available. This example uses the AXI Timer 0.\r
-If that is available on your hardware platform then this example callback\r
-implementation should not require modification provided the example definition\r
-of vApplicationSetupTimerInterrupt() is also not modified. */\r
-void vApplicationClearTimerInterrupt( void )\r
-{\r
-unsigned long ulCSR;\r
-\r
- /* Clear the timer interrupt */\r
- ulCSR = XTmrCtr_GetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0 );\r
- XTmrCtr_SetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0, ulCSR );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* These functions are not used by the Blinky build configuration. However,\r
-they need to be defined because the Blinky and Full build configurations share\r
-a FreeRTOSConifg.h configuration file. */\r
-void vMainConfigureTimerForRunTimeStats( void ) {}\r
-unsigned long ulMainGetRunTimeCounterValue( void ) { return 1; }\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/* ****************************************************************************\r
- * main-blinky.c is included when the "Blinky" build configuration is used.\r
- * main-full.c is included when the "Full" build configuration is used.\r
- *\r
- * main-full.c creates a lot of demo and test tasks and timers, and is\r
- * therefore very comprehensive but also complex. If you would prefer a much\r
- * simpler project to get started with, then select the 'Blinky' build\r
- * configuration within the SDK Eclipse IDE. See the documentation page for\r
- * this demo on the http://www.FreeRTOS.org web site for more information.\r
- * ****************************************************************************\r
- *\r
- * main() creates all the demo application tasks and timers, then starts the\r
- * scheduler. The web documentation provides more details of the standard demo\r
- * application tasks, which provide no particular functionality, but do provide\r
- * a good example of how to use the FreeRTOS API.\r
- *\r
- * In addition to the standard demo tasks, the following tasks and tests are\r
- * defined and/or created within this file:\r
- *\r
- * TCP/IP ("lwIP") task - lwIP is used to create a basic web server. The web\r
- * server uses server side includes (SSI) to generate tables of task statistics,\r
- * and run time statistics (run time statistics show how much processing time\r
- * each task has consumed). See\r
- * http://www.FreeRTOS.org/Free-RTOS-for-Xilinx-MicroBlaze-on-Spartan-6-FPGA.html\r
- * for details on setting up and using the embedded web server.\r
- *\r
- * "Reg test" tasks - These test the task context switch mechanism by first\r
- * filling the MicroBlaze registers with known values, before checking that each\r
- * register maintains the value that was written to it as the tasks are switched\r
- * in and out. The two register test tasks do not use the same values, and\r
- * execute at a very low priority, to ensure they are pre-empted regularly.\r
- *\r
- * "Check" timer - The check timer period is initially set to five seconds.\r
- * The check timer callback function checks that all the standard demo tasks,\r
- * and the register check tasks, are not only still executing, but are executing\r
- * without reporting any errors. If the check timer discovers that a task has\r
- * either stalled, or reported an error, then it changes its own period from\r
- * the initial five seconds, to just 200ms. The check timer callback function\r
- * also toggles an LED each time it is called. This provides a visual\r
- * indication of the system status: If the LED toggles every five seconds then\r
- * no issues have been discovered. If the LED toggles every 200ms then an issue\r
- * has been discovered with at least one task. The last reported issue is\r
- * latched into the pcStatusMessage variable, and can also be viewed at the\r
- * bottom of the pages served by the embedded web server.\r
- *\r
- * ***NOTE*** This demo uses the standard comtest tasks, which has special\r
- * hardware requirements. See\r
- * http://www.FreeRTOS.org/Free-RTOS-for-Xilinx-MicroBlaze-on-Spartan-6-FPGA.html\r
- * for more information.\r
- *\r
- * This file also includes example implementations of the\r
- * vApplicationIdleHook(), vApplicationStackOverflowHook(),\r
- * vApplicationMallocFailedHook(), vApplicationClearTimerInterrupt(), and\r
- * vApplicationSetupTimerInterrupt() callback (hook) functions.\r
- */\r
-\r
-/* Standard includes. */\r
-#include <string.h>\r
-#include <stdio.h>\r
-\r
-/* BSP includes. */\r
-#include "xtmrctr.h"\r
-#include "microblaze_exceptions_g.h"\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "timers.h"\r
-\r
-/* Standard demo includes. */\r
-#include "partest.h"\r
-#include "flash.h"\r
-#include "BlockQ.h"\r
-#include "death.h"\r
-#include "blocktim.h"\r
-#include "semtest.h"\r
-#include "PollQ.h"\r
-#include "GenQTest.h"\r
-#include "QPeek.h"\r
-#include "recmutex.h"\r
-#include "flop.h"\r
-#include "dynamic.h"\r
-#include "comtest_strings.h"\r
-#include "TimerDemo.h"\r
-\r
-/* lwIP includes. */\r
-#include "lwip/tcpip.h"\r
-\r
-\r
-/* Priorities at which the various tasks are created. */\r
-#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
-#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
-#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
-#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
-\r
-/* The LED toggled by the check task. */\r
-#define mainCHECK_LED ( 3 )\r
-\r
-/* The rate at which mainCHECK_LED will toggle when all the tasks are running\r
-without error. See the description of the check timer in the comments at the\r
-top of this file. */\r
-#define mainNO_ERROR_CHECK_TIMER_PERIOD ( 5000 / portTICK_PERIOD_MS )\r
-\r
-/* The rate at which mainCHECK_LED will toggle when an error has been reported\r
-by at least one task. See the description of the check timer in the comments at\r
-the top of this file. */\r
-#define mainERROR_CHECK_TIMER_PERIOD ( 200 / portTICK_PERIOD_MS )\r
-\r
-/* A block time of zero simply means "don't block". */\r
-#define mainDONT_BLOCK ( ( TickType_t ) 0 )\r
-\r
-/* The LED used by the comtest tasks. See the comtest_strings.c file for more\r
-information. In this case an invalid LED number is provided as all four\r
-available LEDs (LEDs 0 to 3) are already in use. */\r
-#define mainCOM_TEST_LED ( 4 )\r
-\r
-/* Baud rate used by the comtest tasks. The baud rate used is actually fixed in\r
-UARTLite IP when the hardware was built, but the standard serial init function\r
-required a baud rate parameter to be provided - in this case it is just\r
-ignored. */\r
-#define mainCOM_TEST_BAUD_RATE ( XPAR_RS232_UART_1_BAUDRATE )\r
-\r
-/* The timer test task generates a lot of timers that all use a different\r
-period that is a multiple of the mainTIMER_TEST_PERIOD definition. */\r
-#define mainTIMER_TEST_PERIOD ( 20 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * The register test tasks as described in the comments at the top of this file.\r
- * The nature of the register test tasks means they have to be implemented in\r
- * assembler.\r
- */\r
-extern void vRegisterTest1( void *pvParameters );\r
-extern void vRegisterTest2( void *pvParameters );\r
-\r
-/*\r
- * Defines the 'check' timer functionality as described at the top of this file.\r
- * This function is the callback function associated with the 'check' timer.\r
- */\r
-static void vCheckTimerCallback( TimerHandle_t xTimer );\r
-\r
-/*\r
- * Configure the interrupt controller, LED outputs and button inputs.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
-/* Defined in lwIPApps.c. */\r
-extern void lwIPAppsInit( void *pvArguments );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The check timer callback function sets pcStatusMessage to a string that\r
-indicates the last reported error that it discovered. */\r
-static const char *pcStatusMessage = NULL;\r
-\r
-/* Structures that hold the state of the various peripherals used by this demo.\r
-These are used by the Xilinx peripheral driver API functions. In this case,\r
-only the timer/counter is used directly within this file. */\r
-static XTmrCtr xTimer0Instance;\r
-\r
-/* The 'check' timer, as described at the top of this file. */\r
-static TimerHandle_t xCheckTimer = NULL;\r
-\r
-/* Used in the run time stats calculations. */\r
-static unsigned long ulClocksPer10thOfAMilliSecond = 0UL;\r
-\r
-/* Constants used to set up the AXI timer to generate ticks. */\r
-static const unsigned char ucTimerCounterNumber = ( unsigned char ) 0U;\r
-static const unsigned long ulCounterReloadValue = ( ( XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ / configTICK_RATE_HZ ) - 1UL );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-int main( void )\r
-{\r
- /***************************************************************************\r
- This project includes a lot of demo and test tasks and timers, and is\r
- therefore comprehensive, but complex. If you would prefer a much simpler\r
- project to get started with, then select the 'Blinky' build configuration\r
- within the SDK Eclipse IDE.\r
- ***************************************************************************/\r
-\r
- /* Configure the interrupt controller, LED outputs and button inputs. */\r
- prvSetupHardware();\r
-\r
- /* This call creates the TCP/IP thread. */\r
- tcpip_init( lwIPAppsInit, NULL );\r
-\r
- /* Start the reg test tasks, as described in the comments at the top of this\r
- file. */\r
- xTaskCreate( vRegisterTest1, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) 0, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( vRegisterTest2, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) 0, tskIDLE_PRIORITY, NULL );\r
-\r
- /* Create the standard demo tasks. */\r
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
- vCreateBlockTimeTasks();\r
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
- vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
- vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
- vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
- vStartQueuePeekTasks();\r
- vStartRecursiveMutexTasks();\r
- vStartComTestStringsTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
- vStartDynamicPriorityTasks();\r
- vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
-\r
- /* Note - the set of standard demo tasks contains two versions of\r
- vStartMathTasks.c. One is defined in flop.c, and uses double precision\r
- floating point numbers and variables. The other is defined in sp_flop.c,\r
- and uses single precision floating point numbers and variables. The\r
- MicroBlaze floating point unit only handles single precision floating.\r
- Therefore, to test the floating point hardware, sp_flop.c should be included\r
- in this project. */\r
- vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
-\r
- /* The suicide tasks must be created last as they need to know how many\r
- tasks were running prior to their creation. This then allows them to\r
- ascertain whether or not the correct/expected number of tasks are running at\r
- any given time. */\r
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
- /* Create the 'check' timer - the timer that periodically calls the\r
- check function as described in the comments at the top of this file. Note\r
- that, for reasons stated in the comments within vApplicationIdleHook()\r
- (defined in this file), the check timer is not actually started until after\r
- the scheduler has been started. */\r
- xCheckTimer = xTimerCreate( "Check timer", mainNO_ERROR_CHECK_TIMER_PERIOD, pdTRUE, ( void * ) 0, vCheckTimerCallback );\r
-\r
- /* Start the scheduler running. From this point on, only tasks and\r
- interrupts will be executing. */\r
- vTaskStartScheduler();\r
-\r
- /* If all is well then the following line will never be reached. If\r
- execution does reach here, then it is highly probably that the heap size\r
- is too small for the idle and/or timer tasks to be created within\r
- vTaskStartScheduler(). */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void vCheckTimerCallback( TimerHandle_t xTimer )\r
-{\r
-extern unsigned long ulRegTest1CycleCount, ulRegTest2CycleCount;\r
-static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;\r
-static long lErrorAlreadyLatched = pdFALSE;\r
-TickType_t xExecutionRate = mainNO_ERROR_CHECK_TIMER_PERIOD;\r
-\r
- /* This is the callback function used by the 'check' timer, as described\r
- in the comments at the top of this file. */\r
-\r
- /* Don't overwrite any errors that have already been latched. */\r
- if( pcStatusMessage == NULL )\r
- {\r
- /* Check the standard demo tasks are running without error. */\r
- if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: GenQueue";\r
- }\r
- else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: QueuePeek\r\n";\r
- }\r
- else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: BlockQueue\r\n";\r
- }\r
- else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: BlockTime\r\n";\r
- }\r
- else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: SemTest\r\n";\r
- }\r
- else if( xArePollingQueuesStillRunning() != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: PollQueue\r\n";\r
- }\r
- else if( xIsCreateTaskStillRunning() != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: Death\r\n";\r
- }\r
- else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: RecMutex\r\n";\r
- }\r
- else if( xAreMathsTaskStillRunning() != pdPASS )\r
- {\r
- pcStatusMessage = "Error: Flop\r\n";\r
- }\r
- else if( xAreComTestTasksStillRunning() != pdPASS )\r
- {\r
- pcStatusMessage = "Error: Comtest\r\n";\r
- }\r
- else if( xAreDynamicPriorityTasksStillRunning() != pdPASS )\r
- {\r
- pcStatusMessage = "Error: Dynamic\r\n";\r
- }\r
- else if( xAreTimerDemoTasksStillRunning( xExecutionRate ) != pdTRUE )\r
- {\r
- pcStatusMessage = "Error: TimerDemo";\r
- }\r
- else if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )\r
- {\r
- /* Check the reg test tasks are still cycling. They will stop\r
- incrementing their loop counters if they encounter an error. */\r
- pcStatusMessage = "Error: RegTest1\r\n";\r
- }\r
- else if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )\r
- {\r
- pcStatusMessage = "Error: RegTest2\r\n";\r
- }\r
- }\r
-\r
- /* Store a local copy of the current reg test loop counters. If these have\r
- not incremented the next time this callback function is executed then the\r
- reg test tasks have either stalled or discovered an error. */\r
- ulLastRegTest1CycleCount = ulRegTest1CycleCount;\r
- ulLastRegTest2CycleCount = ulRegTest2CycleCount;\r
-\r
- /* Toggle the check LED to give an indication of the system status. If\r
- the LED toggles every 5 seconds then everything is ok. A faster toggle\r
- indicates an error. */\r
- vParTestToggleLED( mainCHECK_LED );\r
-\r
- if( pcStatusMessage != NULL )\r
- {\r
- if( lErrorAlreadyLatched == pdFALSE )\r
- {\r
- /* An error has occurred, so change the period of the timer that\r
- calls this callback function. This results in the LED toggling at\r
- a faster rate - giving the user visual feedback that something is not\r
- as it should be. This function is called from the context of the\r
- timer service task so must ***not*** attempt to block while calling\r
- this function. */\r
- if( xTimerChangePeriod( xTimer, mainERROR_CHECK_TIMER_PERIOD, mainDONT_BLOCK ) == pdPASS )\r
- {\r
- /* If the command to change the timer period was sent to the\r
- timer command queue successfully, then latch the fact that the\r
- timer period has already been changed. This is just done to\r
- prevent xTimerChangePeriod() being called on every execution of\r
- this function once an error has been discovered. */\r
- lErrorAlreadyLatched = pdTRUE;\r
- }\r
-\r
- /* Update the xExecutionRate variable too as the rate at which this\r
- callback is executed has to be passed into the\r
- xAreTimerDemoTasksStillRunning() function. */\r
- xExecutionRate = mainERROR_CHECK_TIMER_PERIOD;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This is an application defined callback function used to install the tick\r
-interrupt handler. It is provided as an application callback because the kernel\r
-will run on lots of different MicroBlaze and FPGA configurations - not all of\r
-which will have the same timer peripherals defined or available. This example\r
-uses the AXI Timer 0. If that is available on your hardware platform then this\r
-example callback implementation should not require modification. The name of\r
-the interrupt handler that should be installed is vPortTickISR(), which the\r
-function below declares as an extern. */\r
-void vApplicationSetupTimerInterrupt( void )\r
-{\r
-portBASE_TYPE xStatus;\r
-extern void vPortTickISR( void *pvUnused );\r
-\r
- /* Initialise the timer/counter. */\r
- xStatus = XTmrCtr_Initialize( &xTimer0Instance, XPAR_AXI_TIMER_0_DEVICE_ID );\r
-\r
- if( xStatus == XST_SUCCESS )\r
- {\r
- /* Install the tick interrupt handler as the timer ISR.\r
- *NOTE* The xPortInstallInterruptHandler() API function must be used for\r
- this purpose. */\r
- xStatus = xPortInstallInterruptHandler( XPAR_INTC_0_TMRCTR_0_VEC_ID, vPortTickISR, NULL );\r
- }\r
-\r
- if( xStatus == pdPASS )\r
- {\r
- /* Enable the timer interrupt in the interrupt controller.\r
- *NOTE* The vPortEnableInterrupt() API function must be used for this\r
- purpose. */\r
- vPortEnableInterrupt( XPAR_INTC_0_TMRCTR_0_VEC_ID );\r
-\r
- /* Configure the timer interrupt handler. */\r
- XTmrCtr_SetHandler( &xTimer0Instance, ( void * ) vPortTickISR, NULL );\r
-\r
- /* Set the correct period for the timer. */\r
- XTmrCtr_SetResetValue( &xTimer0Instance, ucTimerCounterNumber, ulCounterReloadValue );\r
-\r
- /* Enable the interrupts. Auto-reload mode is used to generate a\r
- periodic tick. Note that interrupts are disabled when this function is\r
- called, so interrupts will not start to be processed until the first\r
- task has started to run. */\r
- XTmrCtr_SetOptions( &xTimer0Instance, ucTimerCounterNumber, ( XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION | XTC_DOWN_COUNT_OPTION ) );\r
-\r
- /* Start the timer. */\r
- XTmrCtr_Start( &xTimer0Instance, ucTimerCounterNumber );\r
- }\r
-\r
- /* Sanity check that the function executed as expected. */\r
- configASSERT( ( xStatus == pdPASS ) );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This is an application defined callback function used to clear whichever\r
-interrupt was installed by the the vApplicationSetupTimerInterrupt() callback\r
-function - in this case the interrupt generated by the AXI timer. It is\r
-provided as an application callback because the kernel will run on lots of\r
-different MicroBlaze and FPGA configurations - not all of which will have the\r
-same timer peripherals defined or available. This example uses the AXI Timer 0.\r
-If that is available on your hardware platform then this example callback\r
-implementation should not require modification provided the example definition\r
-of vApplicationSetupTimerInterrupt() is also not modified. */\r
-void vApplicationClearTimerInterrupt( void )\r
-{\r
-unsigned long ulCSR;\r
-\r
- /* Clear the timer interrupt */\r
- ulCSR = XTmrCtr_GetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0 );\r
- XTmrCtr_SetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0, ulCSR );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
- /* vApplicationMallocFailedHook() will only be called if\r
- configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
- function that will get called if a call to pvPortMalloc() fails.\r
- pvPortMalloc() is called internally by the kernel whenever a task, queue or\r
- semaphore is created. It is also called by various parts of the demo\r
- application. If heap_1.c or heap_2.c are used, then the size of the heap\r
- available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
- FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
- to query the size of free heap space that remains (although it does not\r
- provide information on how the remaining heap might be fragmented). */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* vApplicationStackOverflowHook() will only be called if\r
- configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2. The handle and name\r
- of the offending task will be passed into the hook function via its\r
- parameters. However, when a stack has overflowed, it is possible that the\r
- parameters will have been corrupted, in which case the pxCurrentTCB variable\r
- can be inspected directly. */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIdleHook( void )\r
-{\r
-static long lCheckTimerStarted = pdFALSE;\r
-\r
- /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
- to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
- task. It is essential that code added to this hook function never attempts\r
- to block in any way (for example, call xQueueReceive() with a block time\r
- specified, or call vTaskDelay()). If the application makes use of the\r
- vTaskDelete() API function (as this demo application does) then it is also\r
- important that vApplicationIdleHook() is permitted to return to its calling\r
- function, because it is the responsibility of the idle task to clean up\r
- memory allocated by the kernel to any task that has since been deleted. */\r
-\r
- /* If the check timer has not already been started, then start it now.\r
- Normally, the xTimerStart() API function can be called immediately after the\r
- timer is created - how this demo application includes the timer demo tasks.\r
- The timer demo tasks, as part of their test function, deliberately fill up\r
- the timer command queue - meaning the check timer cannot be started until\r
- after the scheduler has been started - at which point the timer command\r
- queue will have been drained. */\r
- if( lCheckTimerStarted == pdFALSE )\r
- {\r
- xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
- lCheckTimerStarted = pdTRUE;\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )\r
-{\r
- ( void ) xRegisterDump;\r
-\r
- /* If configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h, then\r
- the kernel will automatically install its own exception handlers before the\r
- kernel is started, if the application writer has not already caused them to\r
- be installed by calling either of the vPortExceptionsInstallHandlers()\r
- or xPortInstallInterruptHandler() API functions before that time. The\r
- kernels exception handler populates an xPortRegisterDump structure with\r
- the processor state at the point that the exception was triggered - and also\r
- includes a strings that say what the exception cause was and which task was\r
- running at the time. The exception handler then passes the populated\r
- xPortRegisterDump structure into vApplicationExceptionRegisterDump() to\r
- allow the application writer to perform any debugging that may be necessary.\r
- However, defining vApplicationExceptionRegisterDump() within the application\r
- itself is optional. The kernel will use a default implementation if the\r
- application writer chooses not to provide their own. */\r
- for( ;; )\r
- {\r
- portNOP();\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupHardware( void )\r
-{\r
- taskDISABLE_INTERRUPTS();\r
-\r
- /* Configure the LED outputs. */\r
- vParTestInitialise();\r
-\r
- /* Tasks inherit the exception and cache configuration of the MicroBlaze\r
- at the point that they are created. */\r
- #if MICROBLAZE_EXCEPTIONS_ENABLED == 1\r
- microblaze_enable_exceptions();\r
- #endif\r
-\r
- #if XPAR_MICROBLAZE_USE_ICACHE == 1\r
- microblaze_invalidate_icache();\r
- microblaze_enable_icache();\r
- #endif\r
-\r
- #if XPAR_MICROBLAZE_USE_DCACHE == 1\r
- microblaze_invalidate_dcache();\r
- microblaze_enable_dcache();\r
- #endif\r
-\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vMainConfigureTimerForRunTimeStats( void )\r
-{\r
- /* How many times does the counter counter increment in 10ms? */\r
- ulClocksPer10thOfAMilliSecond = XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ / 10000UL;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-unsigned long ulMainGetRunTimeCounterValue( void )\r
-{\r
-unsigned long ulTimerCounts1, ulTimerCounts2, ulTickCount, ulReturn;\r
-\r
- /* NOTE: This can get called from a yield, in which case interrupts are\r
- disabled, or from a tick ISR, in which case the effect is the same as if\r
- interrupts were disabled. In either case, it is going to run atomically. */\r
-\r
- /* The timer is in down count mode. How many clocks have passed since it\r
- was last reloaded? */\r
- ulTimerCounts1 = ulCounterReloadValue - XTmrCtr_GetValue( &xTimer0Instance, ucTimerCounterNumber );\r
-\r
- /* How many times has it overflowed? */\r
- ulTickCount = xTaskGetTickCountFromISR();\r
-\r
- /* If this is being called from a yield, has the counter overflowed since\r
- it was read? If that is the case then ulTickCounts will need incrementing\r
- again as it will not yet have been incremented from the tick interrupt. */\r
- ulTimerCounts2 = ulCounterReloadValue - XTmrCtr_GetValue( &xTimer0Instance, ucTimerCounterNumber );\r
- if( ulTimerCounts2 < ulTimerCounts1 )\r
- {\r
- /* There is a tick interrupt pending but the tick count not yet\r
- incremented. */\r
- ulTickCount++;\r
-\r
- /* Use the second timer reading. */\r
- ulTimerCounts1 = ulTimerCounts2;\r
- }\r
-\r
- /* Convert the tick count into tenths of a millisecond. THIS ASSUMES\r
- configTICK_RATE_HZ is 1000! */\r
- ulReturn = ( ulTickCount * 10UL );\r
-\r
- /* Add on the number of tenths of a millisecond that have passed since the\r
- tick count last got updated. */\r
- ulReturn += ( ulTimerCounts1 / ulClocksPer10thOfAMilliSecond );\r
-\r
- /* Some crude rounding. */\r
- if( ( ulTimerCounts1 % ulClocksPer10thOfAMilliSecond ) > ( ulClocksPer10thOfAMilliSecond >> 1UL ) )\r
- {\r
- ulReturn++;\r
- }\r
-\r
- return ulReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-char *pcMainGetTaskStatusMessage( void )\r
-{\r
-char * pcReturn;\r
-\r
- if( pcStatusMessage == NULL )\r
- {\r
- pcReturn = ( char * ) "OK";\r
- }\r
- else\r
- {\r
- pcReturn = ( char * ) pcStatusMessage;\r
- }\r
-\r
- return pcReturn;\r
-}\r
-\r
-\r
-\r
+++ /dev/null
-/*\r
- Copyright 2001, 2002 Georges Menie (www.menie.org)\r
- stdarg version contributed by Christian Ettinger\r
-\r
- This program is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU Lesser General Public License as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- This program is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU Lesser General Public License for more details.\r
-\r
- You should have received a copy of the GNU Lesser General Public License\r
- along with this program; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-*/\r
-\r
-/*\r
- putchar is the only external dependency for this file,\r
- if you have a working putchar, leave it commented out.\r
- If not, uncomment the define below and\r
- replace outbyte(c) by your own function call.\r
-\r
-#define putchar(c) outbyte(c)\r
-*/\r
-\r
-#include <stdarg.h>\r
-\r
-static void printchar(char **str, int c)\r
-{\r
- extern int putchar(int c);\r
- \r
- if (str) {\r
- **str = c;\r
- ++(*str);\r
- }\r
- else (void)putchar(c);\r
-}\r
-\r
-#define PAD_RIGHT 1\r
-#define PAD_ZERO 2\r
-\r
-static int prints(char **out, const char *string, int width, int pad)\r
-{\r
- register int pc = 0, padchar = ' ';\r
-\r
- if (width > 0) {\r
- register int len = 0;\r
- register const char *ptr;\r
- for (ptr = string; *ptr; ++ptr) ++len;\r
- if (len >= width) width = 0;\r
- else width -= len;\r
- if (pad & PAD_ZERO) padchar = '0';\r
- }\r
- if (!(pad & PAD_RIGHT)) {\r
- for ( ; width > 0; --width) {\r
- printchar (out, padchar);\r
- ++pc;\r
- }\r
- }\r
- for ( ; *string ; ++string) {\r
- printchar (out, *string);\r
- ++pc;\r
- }\r
- for ( ; width > 0; --width) {\r
- printchar (out, padchar);\r
- ++pc;\r
- }\r
-\r
- return pc;\r
-}\r
-\r
-/* the following should be enough for 32 bit int */\r
-#define PRINT_BUF_LEN 12\r
-\r
-static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
-{\r
- char print_buf[PRINT_BUF_LEN];\r
- register char *s;\r
- register int t, neg = 0, pc = 0;\r
- register unsigned int u = i;\r
-\r
- if (i == 0) {\r
- print_buf[0] = '0';\r
- print_buf[1] = '\0';\r
- return prints (out, print_buf, width, pad);\r
- }\r
-\r
- if (sg && b == 10 && i < 0) {\r
- neg = 1;\r
- u = -i;\r
- }\r
-\r
- s = print_buf + PRINT_BUF_LEN-1;\r
- *s = '\0';\r
-\r
- while (u) {\r
- t = u % b;\r
- if( t >= 10 )\r
- t += letbase - '0' - 10;\r
- *--s = t + '0';\r
- u /= b;\r
- }\r
-\r
- if (neg) {\r
- if( width && (pad & PAD_ZERO) ) {\r
- printchar (out, '-');\r
- ++pc;\r
- --width;\r
- }\r
- else {\r
- *--s = '-';\r
- }\r
- }\r
-\r
- return pc + prints (out, s, width, pad);\r
-}\r
-\r
-static int print( char **out, const char *format, va_list args )\r
-{\r
- register int width, pad;\r
- register int pc = 0;\r
- char scr[2];\r
-\r
- for (; *format != 0; ++format) {\r
- if (*format == '%') {\r
- ++format;\r
- width = pad = 0;\r
- if (*format == '\0') break;\r
- if (*format == '%') goto out;\r
- if (*format == '-') {\r
- ++format;\r
- pad = PAD_RIGHT;\r
- }\r
- while (*format == '0') {\r
- ++format;\r
- pad |= PAD_ZERO;\r
- }\r
- for ( ; *format >= '0' && *format <= '9'; ++format) {\r
- width *= 10;\r
- width += *format - '0';\r
- }\r
- if( *format == 's' ) {\r
- register char *s = (char *)va_arg( args, int );\r
- pc += prints (out, s?s:"(null)", width, pad);\r
- continue;\r
- }\r
- if( *format == 'd' ) {\r
- pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
- continue;\r
- }\r
- if( *format == 'x' ) {\r
- pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
- continue;\r
- }\r
- if( *format == 'X' ) {\r
- pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
- continue;\r
- }\r
- if( *format == 'u' ) {\r
- pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
- continue;\r
- }\r
- if( *format == 'c' ) {\r
- /* char are converted to int then pushed on the stack */\r
- scr[0] = (char)va_arg( args, int );\r
- scr[1] = '\0';\r
- pc += prints (out, scr, width, pad);\r
- continue;\r
- }\r
- }\r
- else {\r
- out:\r
- printchar (out, *format);\r
- ++pc;\r
- }\r
- }\r
- if (out) **out = '\0';\r
- va_end( args );\r
- return pc;\r
-}\r
-\r
-int printf(const char *format, ...)\r
-{\r
- va_list args;\r
- \r
- va_start( args, format );\r
- return print( 0, format, args );\r
-}\r
-\r
-int sprintf(char *out, const char *format, ...)\r
-{\r
- va_list args;\r
- \r
- va_start( args, format );\r
- return print( &out, format, args );\r
-}\r
-\r
-\r
-int snprintf( char *buf, unsigned int count, const char *format, ... )\r
-{\r
- va_list args;\r
- \r
- ( void ) count;\r
- \r
- va_start( args, format );\r
- return print( &buf, format, args );\r
-}\r
-\r
-\r
-#ifdef TEST_PRINTF\r
-int main(void)\r
-{\r
- char *ptr = "Hello world!";\r
- char *np = 0;\r
- int i = 5;\r
- unsigned int bs = sizeof(int)*8;\r
- int mi;\r
- char buf[80];\r
-\r
- mi = (1 << (bs-1)) + 1;\r
- printf("%s\n", ptr);\r
- printf("printf test\n");\r
- printf("%s is null pointer\n", np);\r
- printf("%d = 5\n", i);\r
- printf("%d = - max int\n", mi);\r
- printf("char %c = 'a'\n", 'a');\r
- printf("hex %x = ff\n", 0xff);\r
- printf("hex %02x = 00\n", 0);\r
- printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
- printf("%d %s(s)%", 0, "message");\r
- printf("\n");\r
- printf("%d %s(s) with %%\n", 0, "message");\r
- sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
- sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
- sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
- sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
- sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
- sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
- sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
- sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
-\r
- return 0;\r
-}\r
-\r
-/*\r
- * if you compile this file with\r
- * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
- * you will get a normal warning:\r
- * printf.c:214: warning: spurious trailing `%' in format\r
- * this line is testing an invalid % at the end of the format string.\r
- *\r
- * this should display (on 32bit int machine) :\r
- *\r
- * Hello world!\r
- * printf test\r
- * (null) is null pointer\r
- * 5 = 5\r
- * -2147483647 = - max int\r
- * char a = 'a'\r
- * hex ff = ff\r
- * hex 00 = 00\r
- * signed -3 = unsigned 4294967293 = hex fffffffd\r
- * 0 message(s)\r
- * 0 message(s) with %\r
- * justif: "left "\r
- * justif: " right"\r
- * 3: 0003 zero padded\r
- * 3: 3 left justif.\r
- * 3: 3 right justif.\r
- * -3: -003 zero padded\r
- * -3: -3 left justif.\r
- * -3: -3 right justif.\r
- */\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR a UARTLite peripheral.\r
-*/\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "queue.h"\r
-#include "comtest_strings.h"\r
-\r
-/* Library includes. */\r
-#include "xuartlite.h"\r
-#include "xuartlite_l.h"\r
-\r
-/* Demo application includes. */\r
-#include "serial.h"\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Functions that are installed as the handler for interrupts that are caused by\r
-Rx and Tx events respectively. */\r
-static void prvRxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount );\r
-static void prvTxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount );\r
-\r
-/* Structure that hold the state of the UARTLite peripheral used by this demo.\r
-This is used by the Xilinx peripheral driver API functions. */\r
-static XUartLite xUartLiteInstance;\r
-\r
-/* The queue used to hold received characters. */\r
-static QueueHandle_t xRxedChars;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
-{\r
-portBASE_TYPE xStatus;\r
-\r
- /* The standard demo header file requires a baud rate to be passed into this\r
- function. However, in this case the baud rate is configured when the\r
- hardware is generated, leaving the ulWantedBaud parameter redundant. */\r
- ( void ) ulWantedBaud;\r
-\r
- /* Create the queue used to hold Rx characters. */\r
- xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
-\r
- /* If the queue was created correctly, then setup the serial port\r
- hardware. */\r
- if( xRxedChars != NULL )\r
- {\r
- xStatus = XUartLite_Initialize( &xUartLiteInstance, XPAR_UARTLITE_1_DEVICE_ID );\r
-\r
- if( xStatus == XST_SUCCESS )\r
- {\r
- /* Complete initialisation of the UART and its associated\r
- interrupts. */\r
- XUartLite_ResetFifos( &xUartLiteInstance );\r
- \r
- /* Install the handlers that the standard Xilinx library interrupt\r
- service routine will call when Rx and Tx events occur \r
- respectively. */\r
- XUartLite_SetRecvHandler( &xUartLiteInstance, ( XUartLite_Handler ) prvRxHandler, NULL );\r
- XUartLite_SetSendHandler( &xUartLiteInstance, ( XUartLite_Handler ) prvTxHandler, NULL );\r
- \r
- /* Install the standard Xilinx library interrupt handler itself.\r
- *NOTE* The xPortInstallInterruptHandler() API function must be used \r
- for this purpose. */ \r
- xStatus = xPortInstallInterruptHandler( XPAR_INTC_0_UARTLITE_1_VEC_ID, ( XInterruptHandler ) XUartLite_InterruptHandler, &xUartLiteInstance );\r
- \r
- /* Enable the interrupt in the peripheral. */\r
- XUartLite_EnableIntr( xUartLiteInstance.RegBaseAddress );\r
- \r
- /* Enable the interrupt in the interrupt controller.\r
- *NOTE* The vPortEnableInterrupt() API function must be used for this\r
- purpose. */\r
- vPortEnableInterrupt( XPAR_INTC_0_UARTLITE_1_VEC_ID );\r
- }\r
-\r
- configASSERT( xStatus == pdPASS );\r
- }\r
-\r
- /* This demo file only supports a single port but something must be\r
- returned to comply with the standard demo header file. */\r
- return ( xComPortHandle ) 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )\r
-{\r
- /* The port handle is not required as this driver only supports one port. */\r
- ( void ) pxPort;\r
-\r
- /* Get the next character from the receive queue. Return false if no \r
- characters are available, or arrive before xBlockTime expires. */\r
- if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
- {\r
- return pdTRUE;\r
- }\r
- else\r
- {\r
- return pdFALSE;\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
-{\r
- ( void ) pxPort;\r
-\r
- /* Output uxStringLength bytes starting from pcString. */\r
- XUartLite_Send( &xUartLiteInstance, ( unsigned char * ) pcString, usStringLength );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvRxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount )\r
-{\r
-signed char cRxedChar;\r
-portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
-\r
- ( void ) pvUnused;\r
- ( void ) uxByteCount;\r
-\r
- /* Place any received characters into the receive queue. */\r
- while( XUartLite_IsReceiveEmpty( xUartLiteInstance.RegBaseAddress ) == pdFALSE )\r
- {\r
- cRxedChar = XUartLite_ReadReg( xUartLiteInstance.RegBaseAddress, XUL_RX_FIFO_OFFSET);\r
- xQueueSendFromISR( xRxedChars, &cRxedChar, &xHigherPriorityTaskWoken );\r
- }\r
-\r
- /* If calling xQueueSendFromISR() caused a task to unblock, and the task \r
- that unblocked has a priority equal to or greater than the task currently\r
- in the Running state (the task that was interrupted), then \r
- xHigherPriorityTaskWoken will have been set to pdTRUE internally within the\r
- xQueueSendFromISR() API function. If xHigherPriorityTaskWoken is equal to\r
- pdTRUE then a context switch should be requested to ensure that the \r
- interrupt returns to the highest priority task that is able to run. */\r
- portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvTxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount )\r
-{\r
- ( void ) pvUnused;\r
- ( void ) uxByteCount;\r
-\r
- /* Nothing to do here. The Xilinx library function takes care of the\r
- transmission. */\r
- portNOP();\r
-}\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
+++ /dev/null
-/*******************************************************************/\r
-/* */\r
-/* This file is automatically generated by linker script generator.*/\r
-/* */\r
-/* Version: Xilinx EDK 13.1 EDK_O.40d */\r
-/* */\r
-/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */\r
-/* */\r
-/* Description : MicroBlaze Linker Script */\r
-/* */\r
-/*******************************************************************/\r
-\r
-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;\r
-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x10400;\r
-\r
-/* Define Memories in the system */\r
-\r
-MEMORY\r
-{\r
- microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00001FB0\r
- MCB_DDR3_S0_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x08000000\r
-}\r
-\r
-/* Specify the default entry point to the program */\r
-\r
-ENTRY(_start)\r
-\r
-/* Define the sections, and where they are mapped in memory */\r
-\r
-SECTIONS\r
-{\r
-.vectors.reset 0x00000000 : {\r
- *(.vectors.reset)\r
-} \r
-\r
-.vectors.sw_exception 0x00000008 : {\r
- *(.vectors.sw_exception)\r
-} \r
-\r
-.vectors.interrupt 0x00000010 : {\r
- *(.vectors.interrupt)\r
-} \r
-\r
-.vectors.hw_exception 0x00000020 : {\r
- *(.vectors.hw_exception)\r
-} \r
-\r
-.text : {\r
- *(.text)\r
- *(.text.*)\r
- *(.gnu.linkonce.t.*)\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.init : {\r
- KEEP (*(.init))\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.fini : {\r
- KEEP (*(.fini))\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.rodata : {\r
- __rodata_start = .;\r
- *(.rodata)\r
- *(.rodata.*)\r
- *(.gnu.linkonce.r.*)\r
- __rodata_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.sdata2 : {\r
- . = ALIGN(8);\r
- __sdata2_start = .;\r
- *(.sdata2)\r
- *(.sdata2.*)\r
- *(.gnu.linkonce.s2.*)\r
- . = ALIGN(8);\r
- __sdata2_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.sbss2 : {\r
- __sbss2_start = .;\r
- *(.sbss2)\r
- *(.sbss2.*)\r
- *(.gnu.linkonce.sb2.*)\r
- __sbss2_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.data : {\r
- . = ALIGN(4);\r
- __data_start = .;\r
- *(.data)\r
- *(.data.*)\r
- *(.gnu.linkonce.d.*)\r
- __data_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.got : {\r
- *(.got)\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.got1 : {\r
- *(.got1)\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.got2 : {\r
- *(.got2)\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.ctors : {\r
- __CTOR_LIST__ = .;\r
- ___CTORS_LIST___ = .;\r
- KEEP (*crtbegin.o(.ctors))\r
- KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\r
- KEEP (*(SORT(.ctors.*)))\r
- KEEP (*(.ctors))\r
- __CTOR_END__ = .;\r
- ___CTORS_END___ = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.dtors : {\r
- __DTOR_LIST__ = .;\r
- ___DTORS_LIST___ = .;\r
- KEEP (*crtbegin.o(.dtors))\r
- KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\r
- KEEP (*(SORT(.dtors.*)))\r
- KEEP (*(.dtors))\r
- __DTOR_END__ = .;\r
- ___DTORS_END___ = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.eh_frame : {\r
- *(.eh_frame)\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.jcr : {\r
- *(.jcr)\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.gcc_except_table : {\r
- *(.gcc_except_table)\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.sdata : {\r
- . = ALIGN(8);\r
- __sdata_start = .;\r
- *(.sdata)\r
- *(.sdata.*)\r
- *(.gnu.linkonce.s.*)\r
- __sdata_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.sbss : {\r
- . = ALIGN(4);\r
- __sbss_start = .;\r
- *(.sbss)\r
- *(.sbss.*)\r
- *(.gnu.linkonce.sb.*)\r
- . = ALIGN(8);\r
- __sbss_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.tdata : {\r
- __tdata_start = .;\r
- *(.tdata)\r
- *(.tdata.*)\r
- *(.gnu.linkonce.td.*)\r
- __tdata_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.tbss : {\r
- __tbss_start = .;\r
- *(.tbss)\r
- *(.tbss.*)\r
- *(.gnu.linkonce.tb.*)\r
- __tbss_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.bss : {\r
- . = ALIGN(4);\r
- __bss_start = .;\r
- *(.bss)\r
- *(.bss.*)\r
- *(.gnu.linkonce.b.*)\r
- *(COMMON)\r
- . = ALIGN(4);\r
- __bss_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );\r
-\r
-_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );\r
-\r
-/* Generate Stack and Heap definitions */\r
-\r
-.heap : {\r
- . = ALIGN(8);\r
- _heap = .;\r
- _heap_start = .;\r
- . += _HEAP_SIZE;\r
- _heap_end = .;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-.stack : {\r
- _stack_end = .;\r
- . += _STACK_SIZE;\r
- . = ALIGN(8);\r
- _stack = .;\r
- __stack = _stack;\r
-} > MCB_DDR3_S0_AXI_BASEADDR\r
-\r
-_end = .;\r
-}\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
-<?fileVersion 4.0.0?>\r
-\r
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
- <storageModule moduleId="org.eclipse.cdt.core.settings">\r
- <cconfiguration id="org.eclipse.cdt.core.default.config.1102591381">\r
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1102591381" moduleId="org.eclipse.cdt.core.settings" name="Configuration">\r
- <externalSettings/>\r
- <extensions/>\r
- </storageModule>\r
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
- <storageModule moduleId="org.eclipse.cdt.core.pathentry"/>\r
- </cconfiguration>\r
- </storageModule>\r
-</cproject>\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>\r
-<projectDescription>\r
- <name>StandAloneBSP</name>\r
- <comment></comment>\r
- <projects>\r
- <project>HardwareWithEthernetLite</project>\r
- </projects>\r
- <buildSpec>\r
- <buildCommand>\r
- <name>org.eclipse.cdt.make.core.makeBuilder</name>\r
- <triggers>clean,full,incremental,</triggers>\r
- <arguments>\r
- <dictionary>\r
- <key>org.eclipse.cdt.core.errorOutputParser</key>\r
- <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.append_environment</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.build.arguments</key>\r
- <value></value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.build.command</key>\r
- <value>make</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.build.target.auto</key>\r
- <value>all</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.build.target.clean</key>\r
- <value>clean</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.build.target.inc</key>\r
- <value>all</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
- <value>false</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>\r
- <value>true</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.environment</key>\r
- <value></value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.stopOnError</key>\r
- <value>false</value>\r
- </dictionary>\r
- <dictionary>\r
- <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
- <value>true</value>\r
- </dictionary>\r
- </arguments>\r
- </buildCommand>\r
- </buildSpec>\r
- <natures>\r
- <nature>com.xilinx.sdk.sw.SwProjectNature</nature>\r
- <nature>org.eclipse.cdt.core.cnature</nature>\r
- <nature>org.eclipse.cdt.make.core.makeNature</nature>\r
- </natures>\r
-</projectDescription>\r
+++ /dev/null
-THIRPARTY=false
-PROCESSOR=microblaze_0
-MSS_FILE=system.mss
+++ /dev/null
-# Makefile generated by Xilinx SDK.
-
--include libgen.options
-
-LIBRARIES = ${PROCESSOR}/lib/libxil.a
-MSS = system.mss
-
-all: libs
- @echo 'Finished building libraries'
-
-libs: $(LIBRARIES)
-
-$(LIBRARIES): $(MSS)
- libgen -hw ${HWSPEC}\
- ${REPOSITORIES}\
- -pe ${PROCESSOR} \
- -log libgen.log \
- $(MSS)
-
-clean:
- rm -rf ${PROCESSOR}
+++ /dev/null
-PROCESSOR=microblaze_0
-REPOSITORIES=-lp ../../KernelAwareBSPRepository
-HWSPEC=../HardwareWithEthernetLite/system.xml
+++ /dev/null
-\r
- PARAMETER VERSION = 2.2.0\r
-\r
-\r
-BEGIN OS\r
- PARAMETER OS_NAME = standalone\r
- PARAMETER OS_VER = 3.01.a\r
- PARAMETER PROC_INSTANCE = microblaze_0\r
- PARAMETER STDIN = RS232_Uart_1\r
- PARAMETER STDOUT = RS232_Uart_1\r
-END\r
-\r
-\r
-BEGIN PROCESSOR\r
- PARAMETER DRIVER_NAME = cpu\r
- PARAMETER DRIVER_VER = 1.13.a\r
- PARAMETER HW_INSTANCE = microblaze_0\r
-END\r
-\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = emaclite\r
- PARAMETER DRIVER_VER = 3.01.a\r
- PARAMETER HW_INSTANCE = Ethernet_Lite\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = gpio\r
- PARAMETER DRIVER_VER = 3.00.a\r
- PARAMETER HW_INSTANCE = LEDs_4Bits\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = s6_ddrx\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = MCB_DDR3\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = gpio\r
- PARAMETER DRIVER_VER = 3.00.a\r
- PARAMETER HW_INSTANCE = Push_Buttons_4Bits\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = uartlite\r
- PARAMETER DRIVER_VER = 2.00.a\r
- PARAMETER HW_INSTANCE = RS232_Uart_1\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = tmrctr\r
- PARAMETER DRIVER_VER = 2.03.a\r
- PARAMETER HW_INSTANCE = axi_timer_0\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = uartlite\r
- PARAMETER DRIVER_VER = 2.00.a\r
- PARAMETER HW_INSTANCE = debug_module\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = bram\r
- PARAMETER DRIVER_VER = 3.00.a\r
- PARAMETER HW_INSTANCE = microblaze_0_d_bram_ctrl\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = bram\r
- PARAMETER DRIVER_VER = 3.00.a\r
- PARAMETER HW_INSTANCE = microblaze_0_i_bram_ctrl\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = intc\r
- PARAMETER DRIVER_VER = 2.02.a\r
- PARAMETER HW_INSTANCE = microblaze_0_intc\r
-END\r
-\r
-\r
+++ /dev/null
- The following files will be modified:
- system.mhs
- system.mss
-
---------------------------------------
- The following changes will be made:
- Core ppc440mc_ddr2 2.00.a will be replaced by 2.00.b
- Core clock_generator 3.00.a will be replaced by 3.01.a
-
- Driver cpu_ppc440 1.00.b will be replaced by 1.01.a
- Driver iic 1.14.a will be replaced by 1.15.a
---------------------------------------
- The following changes need to be made manually by the user:
- Core xps_ethernetlite 2.01.a needs to be replaced by 3.00.a
- Core plbv46_pcie 3.00.b needs to be replaced by 4.01.a
+++ /dev/null
-No logfile was found.\r
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-The project file (XMP) has changed on disk.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-At Local date and time: Tue Jun 30 18:36:00 2009
- make -f system.make netlistclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:36:05 2009
- make -f system.make bitsclean started...
-\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:36:10 2009
- make -f system.make hwclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-rm -rf implementation synthesis xst hdl\r
-rm -rf xst.srp system.srp\r
-rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:36:16 2009
- make -f system.make libsclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:36:20 2009
- make -f system.make programclean started...
-\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:36:25 2009
- make -f system.make swclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Tue Jun 30 22:00:27 2009
- make -f system.make bits started...
-\r
-****************************************************\r
-Creating system netlist for hardware specification..\r
-****************************************************\r
-platgen -p xc5vfx70tff1136-1 -lang vhdl -msg __xps/ise/xmsgprops.lst system.mhs\r
-\r\r
-Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47\r\r
- (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-\r\r
-Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg\r\r
-__xps/ise/xmsgprops.lst system.mhs \r\r
-\r\r
-Parse\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system.mhs\r\r
-...\r\r
-\r\r
-Read MPD definitions ...\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Overriding IP level properties ...\r\r
-\r\r
-Performing IP level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
-Address Map for Processor ppc440_0\r\r
- (0b0000000000-0b0011111111) ppc440_0 \r\r
- (0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC\r\r
- (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0\r\r
- (0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0\r\r
- (0x81420000-0x8142ffff) LEDs_Positions plb_v46_0\r\r
- (0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0\r\r
- (0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0\r\r
- (0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0\r\r
- (0x81800000-0x8180ffff) xps_intc_0 plb_v46_0\r\r
- (0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0\r\r
- (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0\r\r
- (0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0\r\r
- (0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0\r\r
- (0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0\r\r
- (0xf8000000-0xf80fffff) SRAM plb_v46_0\r\r
- (0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
- C_SPLB0_P2P value to 0\r\r
-\r\r
-Computing clock values...\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 12\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
- PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
- PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
- value to 0x2000\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PORT_DWIDTH value to 64\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
- value to 8\r\r
-INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
- _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
- ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
- C_MPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
- C_MPLB_SMALLEST_SLAVE value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
- 2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-\r\r
-Checking platform address map ...\r\r
-\r\r
-Checking platform configuration ...\r\r
-INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - This design requires design constraints to guarantee\r\r
- performance.\r\r
- Please refer to the xps_ethernetlite_v2_00_a data sheet for details. \r\r
- The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs\r\r
- Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet\r\r
- operation.\r\r
-IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 109 - 1 master(s) : 12 slave(s)\r\r
-IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 290 - 1 master(s) : 1 slave(s)\r\r
-IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 394 - 1 master(s) : 1 slave(s)\r\r
-\r\r
-Checking port drivers...\r\r
-WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 461 - floating connection!\r\r
-\r\r
-Performing Clock DRCs...\r\r
-\r\r
-Performing Reset DRCs...\r\r
-\r\r
-Overriding system level properties...\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER\r\r
- C_PPC440MC_ADDR_BASE value to 0x00000000\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER\r\r
- C_PPC440MC_ADDR_HIGH value to 0x0fffffff\r\r
-INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0\r\r
- 1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER\r\r
- C_NUM_PPC_USED value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR\r\r
- value to 0b00000000000000000000000000000001\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE\r\r
- value to 0b00000000000000000000000000000001\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL\r\r
- value to 0b00000000000000000000000000000000\r\r
-\r\r
-Running system level update procedures...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
-\r\r
-Running system level DRCs...\r\r
-\r\r
-Performing System level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...\r\r
-INFO: The PCIe_Bridge core has constraints automatically generated by XPS in\r\r
-implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-INFO: The Ethernet_MAC core has constraints automatically generated by XPS in\r\r
-implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in\r\r
-implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-\r\r
-Modify defaults ...\r\r
-\r\r
-Creating stub ...\r\r
-\r\r
-Processing licensed instances ...\r\r
-Completion time: 0.00 seconds\r\r
-\r\r
-Creating hardware output directories ...\r\r
-\r\r
-Managing hardware (BBD-specified) netlist files ...\r\r
-IPNAME:plbv46_pcie INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 253 - Copying (BBD-specified) netlist files.\r\r
-IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 298 - Copying (BBD-specified) netlist files.\r\r
-IPNAME:apu_fpu_virtex5 INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 401 - Copying (BBD-specified) netlist files.\r\r
-\r\r
-Managing cache ...\r\r
-\r\r
-Elaborating instances ...\r\r
-IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 131 - elaborating IP\r\r
-\r\r
-Writing HDL for elaborated instances ...\r\r
-\r\r
-Inserting wrapper level ...\r\r
-Completion time: 0.00 seconds\r\r
-\r\r
-Constructing platform-level connectivity ...\r\r
-Completion time: 1.00 seconds\r\r
-\r\r
-Writing (top-level) BMM ...\r\r
-\r\r
-Writing (top-level and wrappers) HDL ...\r\r
-\r\r
-Generating synthesis project file ...\r\r
-\r\r
-Running XST synthesis ...\r\r
-\r\r
-INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option\r\r
- IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST\r\r
- synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. \r\r
-INSTANCE:ppc440_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 78 - Running XST synthesis\r\r
-INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 109 - Running XST synthesis\r\r
-INSTANCE:xps_bram_if_cntlr_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 118 - Running XST synthesis\r\r
-INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 131 - Running XST synthesis\r\r
-INSTANCE:rs232_uart_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 138 - Running XST synthesis\r\r
-INSTANCE:leds_8bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 154 - Running XST synthesis\r\r
-INSTANCE:leds_positions -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 168 - Running XST synthesis\r\r
-INSTANCE:push_buttons_5bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 182 - Running XST synthesis\r\r
-INSTANCE:dip_switches_8bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 196 - Running XST synthesis\r\r
-INSTANCE:iic_eeprom -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 210 - Running XST synthesis\r\r
-INSTANCE:sram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 223 - Running XST synthesis\r\r
-INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 253 - Running XST synthesis\r\r
-INSTANCE:ppc440_0_splb0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 290 - Running XST synthesis\r\r
-INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 298 - Running XST synthesis\r\r
-INSTANCE:ddr2_sdram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 317 - Running XST synthesis\r\r
-INSTANCE:sysace_compactflash -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 377 - Running XST synthesis\r\r
-INSTANCE:ppc440_0_fcb_v20 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 394 - Running XST synthesis\r\r
-INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 401 - Running XST synthesis\r\r
-INSTANCE:clock_generator_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 407 - Running XST synthesis\r\r
-INSTANCE:jtagppc_cntlr_inst -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 446 - Running XST synthesis\r\r
-INSTANCE:proc_sys_reset_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 452 - Running XST synthesis\r\r
-INSTANCE:xps_intc_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 464 - Running XST synthesis\r\r
-\r\r
-Running NGCBUILD ...\r\r
-IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 78 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..\r\r
-ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/ppc440_0_wrapper/ppc440_0_wrapper.ngc" ...\r\r
-\r\r
-Applying constraints in "ppc440_0_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ppc440_0_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 6 sec\r\r
-Total CPU time to NGCBUILD completion: 6 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 138 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc\r\r
-../rs232_uart_1_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/rs232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../rs232_uart_1_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 2 sec\r\r
-Total CPU time to NGCBUILD completion: 2 sec\r\r
-\r\r
-Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 253 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..\r\r
-pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/pcie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...\r\r
-Executing edif2ngd -noa\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\pcie_bridge_wrapper_fifo_generator_v4_3.edn"\r\r
-"pcie_bridge_wrapper_fifo_generator_v4_3.ngo"\r\r
-Release 11.2 - edif2ngd L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
-INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
-with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
-Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\pcie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
-Loading design module\r\r
-"../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\pcie_bridge_wrapper/dpram_70_512.ngc"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\pcie_bridge_wrapper/fifo_71x512.ngc"...\r\r
-\r\r
-Applying constraints in "pcie_bridge_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../pcie_bridge_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 13 sec\r\r
-Total CPU time to NGCBUILD completion: 9 sec\r\r
-\r\r
-Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 298 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..\r\r
-ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/ethernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...\r\r
-Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"\r\r
-"ethernetlite_v1_01_b_dmem_v2.ngo"\r\r
-Release 11.2 - edif2ngd L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
-INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
-with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
-Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\ethernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
-\r\r
-Applying constraints in "ethernet_mac_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ethernet_mac_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 9 sec\r\r
-Total CPU time to NGCBUILD completion: 6 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 317 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..\r\r
-ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...\r\r
-\r\r
-Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ddr2_sdram_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 7 sec\r\r
-Total CPU time to NGCBUILD completion: 7 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:ppc440_0_apu_fpu_virtex5_wrapper INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 401 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_apu_fpu_virtex5_wrapper.ucf -sd\r\r
-.. ppc440_0_apu_fpu_virtex5_wrapper.ngc ../ppc440_0_apu_fpu_virtex5_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/ppc440_0_apu_fpu_virtex5_wrapper/ppc440_0_apu_fpu_virtex5_wrapper.ngc" ...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\ppc440_0_apu_fpu_virtex5_wrapper/apu_fpu_dp_lo.ngc"...\r\r
-\r\r
-Applying constraints in "ppc440_0_apu_fpu_virtex5_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ppc440_0_apu_fpu_virtex5_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 7 sec\r\r
-Total CPU time to NGCBUILD completion: 7 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ppc440_0_apu_fpu_virtex5_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 464 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc\r\r
-../xps_intc_0_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/xps_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../xps_intc_0_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 2 sec\r\r
-Total CPU time to NGCBUILD completion: 2 sec\r\r
-\r\r
-Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-\r\r
-Rebuilding cache ...\r\r
-\r\r
-Total run time: 1120.00 seconds\r\r
-Running synthesis...\r
-bash -c "cd synthesis; ./synthesis.sh"\r
-xst -ifn system_xst.scr -intstyle silent\r
-Running XST synthesis ...\r
-XST completed\r
-Release 11.2 - ngcbuild L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Overriding Xilinx file <ngcflow.csf> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>\r\r
-\r\r
-Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe\r\r
-./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise\r\r
-../__xps/ise/system.ise\r\r
-\r\r
-Reading NGO file\r\r
-"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/synthesis/\r\r
-system.ngc" ...\r\r
-Loading design module "../implementation/ppc440_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/plb_v46_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...\r\r
-Loading design module\r\r
-"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...\r\r
-Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...\r\r
-Loading design module "../implementation/leds_8bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/leds_positions_wrapper.ngc"...\r\r
-Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/iic_eeprom_wrapper.ngc"...\r\r
-Loading design module "../implementation/sram_wrapper.ngc"...\r\r
-Loading design module "../implementation/pcie_bridge_wrapper.ngc"...\r\r
-Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...\r\r
-Loading design module "../implementation/ethernet_mac_wrapper.ngc"...\r\r
-Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...\r\r
-Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...\r\r
-Loading design module "../implementation/ppc440_0_fcb_v20_wrapper.ngc"...\r\r
-Loading design module\r\r
-"../implementation/ppc440_0_apu_fpu_virtex5_wrapper.ngc"...\r\r
-Loading design module "../implementation/clock_generator_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...\r\r
-Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/xps_intc_0_wrapper.ngc"...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../implementation/system.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 12 sec\r\r
-Total CPU time to NGCBUILD completion: 11 sec\r\r
-\r\r
-Writing NGCBUILD log file "../implementation/system.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-*********************************************\r
-Running Xilinx Implementation tools..\r
-*********************************************\r
-xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc\r
-Release 11.2 - Xflow L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise\r\r
-../__xps/ise/system.ise system.ngc \r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into\r\r
-working directory\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
-ion \r\r
-\r\r
-Using Flow File:\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
-ion/fpga.flw \r\r
-Using Option File(s): \r\r
- C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/xflow.opt \r\r
-\r\r
-Creating Script File ... \r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program ngdbuild\r\r
-# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm\r\r
-system.bmm\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/system.ngc" -uc system.ucf system.ngd \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - ngdbuild L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt\r\r
-timestamp -bm system.bmm\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
-ion/system.ngc -uc system.ucf system.ngd\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/system.ngc" ...\r\r
-Gathering constraint information from source properties...\r\r
-Done.\r\r
-\r\r
-Applying constraints in "system.ucf" to the design...\r\r
-WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance\r\r
- 'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_\r\r
- ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to\r\r
- 'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive. \r\r
- In order for functional simulation to be correct, the value of SIM_DEVICE\r\r
- should be changed in this same manner in the source netlist or constraint\r\r
- file.\r\r
-Resolving constraint associations...\r\r
-Checking Constraint Associations...\r\r
-WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM\r\r
- "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"\r\r
- * 4;> [system.ucf(264)]: This constraint will be ignored because the relative\r\r
- clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not\r\r
- found.\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *\r\r
- 1.25 PHASE 2 ns HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *\r\r
- 1.25 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *\r\r
- 1.25 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *\r\r
- 2 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *\r\r
- 0.625 HIGH 50%>\r\r
-\r\r
-Done...\r\r
-Checking Partitions ...\r\r
-\r\r
-Processing BMM file ...\r\r
-\r\r
-WARNING:NgdBuild:1212 - User specified non-default attribute value\r\r
- (8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM\r\r
- "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".\r\r
- This does not match the PERIOD constraint value (5 ns.). The uncertainty\r\r
- calculation will use the non-default attribute value. This could result in\r\r
- incorrect uncertainty calculated for DCM output clocks.\r\r
-Checking expanded design ...\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_\r\r
- ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].\r\r
- ALIGN_PIPE' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD\r\r
- RE_I' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR\r\r
- E_I' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
- "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad\r\r
- v_i" of type "PLL_ADV". This attribute will be ignored.\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[7].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[6].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[5].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[4].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
- _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
- _H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG0' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG1' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG2' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[1].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[2].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[3].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[4].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[5].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[6].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[7].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'ppc440_0_apu_fpu_virtex5/ppc440_0_apu_fpu_virtex5/gen_apu_fpu_dp_lo.netlist/\r\r
- fpu_is_full.sqrt_sqrt_flt_pt_op_sqrt_op.spd.op_round_logic.rnd2_carrys_q_del.\r\r
- no_rlocs.fast_del.carry_fd' has unconnected output pin\r\r
-WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
- "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"\r\r
- of type "PLL_ADV". This attribute will be ignored.\r\r
-WARNING:NgdBuild:452 - logical net 'N194' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N195' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N196' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N197' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N198' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N199' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N200' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N201' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N202' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N203' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N204' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N205' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N206' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N207' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N208' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N209' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N210' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N211' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N212' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N213' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N214' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N215' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N216' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N217' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N218' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N219' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N220' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N221' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N222' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N223' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N224' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N225' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N226' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N227' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N228' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N229' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N230' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N231' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N232' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N233' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N234' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N235' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N236' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N237' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N238' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N239' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N240' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N241' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N242' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N243' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N244' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N245' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N246' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N247' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N248' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N249' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N250' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N251' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N252' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N253' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N254' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N255' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N256' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N257' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N266' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N267' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N268' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N269' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N270' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N271' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N272' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N273' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N306' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N307' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N308' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N309' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N310' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N311' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N312' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N313' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'\r\r
- has no driver\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGDBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 349\r\r
-\r\r
-Writing NGD file "system.ngd" ...\r\r
-Total REAL time to NGDBUILD completion: 2 min 20 sec\r\r
-Total CPU time to NGDBUILD completion: 1 min 50 sec\r\r
-\r\r
-Writing NGDBUILD log file "system.bld"...\r\r
-\r\r
-NGDBUILD done.\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program map\r\r
-# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing\r\r
-system.ngd system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - Map L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>\r\r
-Using target part "5vfx70tff1136-1".\r\r
-WARNING:LIT:243 - Logical network N194 has no load.\r\r
-WARNING:LIT:395 - The above warning message is repeated 1028 more times for the\r\r
- following (max. 5 shown):\r\r
- N195,\r\r
- N196,\r\r
- N197,\r\r
- N198,\r\r
- N199\r\r
- To see the details of these warning messages, please use the -detail switch.\r\r
-Mapping design into LUTs...\r\r
-WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin\r\r
- connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has\r\r
- been removed.\r\r
-WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top\r\r
- level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.\r\r
-WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been\r\r
- optimized out of the design.\r\r
-Writing file system_map.ngm...\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-Running directed packing...\r\r
-Running delay-based LUT packing...\r\r
-Updating timing models...\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
- TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during\r\r
- timing analysis.\r\r
-INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report\r\r
- (.mrp).\r\r
-Running timing-driven placement...\r\r
-Total REAL time at the beginning of Placer: 2 mins 24 secs \r\r
-Total CPU time at the beginning of Placer: 2 mins 19 secs \r\r
-\r\r
-Phase 1.1 Initial Placement Analysis\r\r
-Phase 1.1 Initial Placement Analysis (Checksum:3a0b7697) REAL time: 2 mins 44 secs \r\r
-\r\r
-Phase 2.7 Design Feasibility Check\r\r
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
- Components associated with this bus are as follows: \r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS18\r\r
-\r\r
-\r\r
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
- Components associated with this bus are as follows: \r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33\r\r
-\r\r
-\r\r
-Phase 2.7 Design Feasibility Check (Checksum:3a0b7697) REAL time: 2 mins 45 secs \r\r
-\r\r
-Phase 3.31 Local Placement Optimization\r\r
-Phase 3.31 Local Placement Optimization (Checksum:c9fd22c3) REAL time: 2 mins 45 secs \r\r
-\r\r
-Phase 4.37 Local Placement Optimization\r\r
-Phase 4.37 Local Placement Optimization (Checksum:c9fd22c3) REAL time: 2 mins 45 secs \r\r
-\r\r
-Phase 5.33 Local Placement Optimization\r\r
-Phase 5.33 Local Placement Optimization (Checksum:c9fd22c3) REAL time: 10 mins 47 secs \r\r
-\r\r
-Phase 6.32 Local Placement Optimization\r\r
-Phase 6.32 Local Placement Optimization (Checksum:c9fd22c3) REAL time: 10 mins 52 secs \r\r
-\r\r
-Phase 7.2 Initial Clock and IO Placement\r\r
-\r\r
-\r\r
-\r\r
-There are 16 clock regions on the target FPGA device:\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y7: | CLOCKREGION_X1Y7: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 4 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y6: | CLOCKREGION_X1Y6: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 0 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use\r
- |\r\r
-| 4 edge BUFIOs available, 2 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 0 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 4 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y1>\r\r
- key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y2>\r\r
- key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 8 | 0 | 0 | 60 | 60 | 1280 | 640 | 1920 | 0 | 0 | 1 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|-------\r
--|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y6>\r\r
- key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | \r
- 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:\r\r
-#\r\r
-# Number of Regional Clocking Regions in the device: 16 (4 clock spines in each)\r\r
-# Number of Regional Clock Networks used in this design: 8 (each network can be\r\r
-# composed of up to 3 clock spines and cover up to 3 regional clock regions)\r\r
-# \r\r
-######################################################################################\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y27" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y9" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y11" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y4" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =\r\r
-CLOCKREGION_X0Y1;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y25" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y7" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =\r\r
-CLOCKREGION_X0Y1;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y26" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y10" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-Phase 7.2 Initial Clock and IO Placement (Checksum:b5943100) REAL time: 11 mins 10 secs \r\r
-\r\r
-Phase 8.36 Local Placement Optimization\r\r
-Phase 8.36 Local Placement Optimization (Checksum:b5943100) REAL time: 11 mins 10 secs \r\r
-\r\r
-.........\r
-..............\r
-.......\r\r
-....\r
-......\r
-......\r
-......\r
-......\r
-......\r
-.......\r
-.......\r
-......\r
-........\r
-......\r
-........\r
-.......\r
-........\r
-........\r
-......\r\r
-Phase 9.30 Global Clock Region Assignment\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:\r\r
-#\r\r
-# Number of Global Clock Regions : 16\r\r
-# Number of Global Clock Networks: 15\r\r
-#\r\r
-# Clock Region Assignment: SUCCESSFUL\r\r
-\r\r
-# Location of Clock Components\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;\r\r
-INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;\r\r
-INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;\r\r
-INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;\r\r
-INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;\r\r
-INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;\r\r
-INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;\r\r
-INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;\r\r
-INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;\r\r
-INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;\r\r
-INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;\r\r
-INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;\r\r
-\r\r
-# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1\r\r
-NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;\r\r
-TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30\r\r
-NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2\r\r
-NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3\r\r
-NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
-TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
-AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3 ;\r\r
-\r\r
-# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28\r\r
-NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8\r\r
-NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE = CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
-\r\r
-# clk_200_0000MHz driven by BUFGCTRL_X0Y4\r\r
-NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;\r\r
-TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;\r\r
-AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7\r\r
-NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
-TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE = CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31\r\r
-NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE = CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
-\r\r
-# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5\r\r
-NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6\r\r
-NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
-\r\r
-# NOTE: \r\r
-# This report is provided to help reproduce successful clock-region \r\r
-# assignments. The report provides range constraints for all global \r\r
-# clock networks, in a format that is directly usable in ucf files. \r\r
-#\r\r
-#END of Global Clock Net Distribution UCF Constraints\r\r
-######################################################################################\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:\r\r
-\r\r
-Number of Global Clock Regions : 16\r\r
-Number of Global Clock Networks: 15\r\r
-\r\r
-Clock Region Assignment: SUCCESSFUL\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y0> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 38 | 676 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 329 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | 1005 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y0> \r\r
- key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 55 | 1130 |PCIe_Bridge/Bridge_Clk\r\r
- 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 24 | 52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 29 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 79 | 1211 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y1> \r\r
- key resource utilizations (used/available): global-clocks - 6/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 164 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 2 | 1 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 33 | 942 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 1 | 1 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 51 | 1110 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y1> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 104 | 750 |PCIe_Bridge/Bridge_Clk\r\r
- 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 312 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 104 | 1077 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y2> \r\r
- key resource utilizations (used/available): global-clocks - 5/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 4 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 3 | 0 | 0 | 0 | 9 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 1074 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 109 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 3 | 0 | 0 | 0 | 9 | 42 | 0 | 0 | 0 | 0 | 1 | 0 | 47 | 1207 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y2> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 150 | 685 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 59 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk\r\r
- 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 28 | 407 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 178 | 1153 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y3> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 79 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 20 | 286 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 79 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 20 | 447 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y3> \r\r
- key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 126 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 27 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
- 6 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 0 | 0 | 0 | 116 | 933 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 0 | 0 | 0 | 116 | 1086 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y4> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 33 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 4 | 0 | 0 | 0 | 1 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 51 | 262 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 34 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 6 | 0 | 0 | 0 | 7 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 51 | 329 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y4> \r\r
- key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 |PCIe_Bridge/Bridge_Clk\r\r
- 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 76 | 1046 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 23 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 3 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 76 | 1089 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y5> \r\r
- key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 49 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 72 | 601 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 99 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 72 | 749 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y5> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 28 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 126 | 746 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 14 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 126 | 789 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y6> \r\r
- key resource utilizations (used/available): global-clocks - 7/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 91 | 751 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 249 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 8 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 2 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 106 | 1010 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y6> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 97 | 796 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 97 | 800 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y7> \r\r
- key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 106 | 471 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 310 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 116 | 782 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y7> \r\r
- key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 146 | 674 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 146 | 674 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-NOTE:\r\r
-The above detailed report is the initial placement of the logic after the clock region assignment. The final placement\r\r
-may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks\r\r
-maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.\r\r
-\r\r
-\r\r
-# END of Global Clock Net Loads Distribution Report:\r\r
-######################################################################################\r\r
-\r\r
-\r\r
-Phase 9.30 Global Clock Region Assignment (Checksum:b5943100) REAL time: 12 mins 45 secs \r\r
-\r\r
-Phase 10.3 Local Placement Optimization\r\r
-Phase 10.3 Local Placement Optimization (Checksum:b5943100) REAL time: 12 mins 46 secs \r\r
-\r\r
-Phase 11.5 Local Placement Optimization\r\r
-Phase 11.5 Local Placement Optimization (Checksum:b5943100) REAL time: 12 mins 47 secs \r\r
-\r\r
-Phase 12.8 Global Placement\r\r
-..\r
-...........\r
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-.\r
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-.\r
-.\r
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-.\r\r
-.\r
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-.\r
-....\r
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-.....\r\r
-.\r
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-.\r
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-....\r\r
-Phase 12.8 Global Placement (Checksum:64c223c7) REAL time: 20 mins 44 secs \r\r
-\r\r
-Phase 13.29 Local Placement Optimization\r\r
-Phase 13.29 Local Placement Optimization (Checksum:64c223c7) REAL time: 20 mins 44 secs \r\r
-\r\r
-Phase 14.5 Local Placement Optimization\r\r
-Phase 14.5 Local Placement Optimization (Checksum:64c223c7) REAL time: 20 mins 49 secs \r\r
-\r\r
-Phase 15.18 Placement Optimization\r\r
-Phase 15.18 Placement Optimization (Checksum:d0a37aa3) REAL time: 23 mins 25 secs \r\r
-\r\r
-Phase 16.5 Local Placement Optimization\r\r
-Phase 16.5 Local Placement Optimization (Checksum:d0a37aa3) REAL time: 23 mins 28 secs \r\r
-\r\r
-Phase 17.34 Placement Validation\r\r
-Phase 17.34 Placement Validation (Checksum:d0a37aa3) REAL time: 23 mins 30 secs \r\r
-\r\r
-Total REAL time to Placer completion: 23 mins 34 secs \r\r
-Total CPU time to Placer completion: 22 mins 30 secs \r\r
-Running post-placement packing...\r\r
-Writing output files...\r\r
-\r\r
-Design Summary:\r\r
-Number of errors: 0\r\r
-Number of warnings: 52\r\r
-Slice Logic Utilization:\r\r
- Number of Slice Registers: 14,755 out of 44,800 32%\r\r
- Number used as Flip Flops: 14,754\r\r
- Number used as Latches: 1\r\r
- Number of Slice LUTs: 16,419 out of 44,800 36%\r\r
- Number used as logic: 15,565 out of 44,800 34%\r\r
- Number using O6 output only: 14,103\r\r
- Number using O5 output only: 371\r\r
- Number using O5 and O6: 1,091\r\r
- Number used as Memory: 724 out of 13,120 5%\r\r
- Number used as Dual Port RAM: 228\r\r
- Number using O6 output only: 12\r\r
- Number using O5 output only: 32\r\r
- Number using O5 and O6: 184\r\r
- Number used as Single Port RAM: 4\r\r
- Number using O6 output only: 4\r\r
- Number used as Shift Register: 492\r\r
- Number using O6 output only: 492\r\r
- Number used as exclusive route-thru: 130\r\r
- Number of route-thrus: 581\r\r
- Number using O6 output only: 490\r\r
- Number using O5 output only: 81\r\r
- Number using O5 and O6: 10\r\r
-\r\r
-Slice Logic Distribution:\r\r
- Number of occupied Slices: 7,735 out of 11,200 69%\r\r
- Number of LUT Flip Flop pairs used: 21,404\r\r
- Number with an unused Flip Flop: 6,649 out of 21,404 31%\r\r
- Number with an unused LUT: 4,985 out of 21,404 23%\r\r
- Number of fully used LUT-FF pairs: 9,770 out of 21,404 45%\r\r
- Number of unique control sets: 1,397\r\r
- Number of slice register sites lost\r\r
- to control set restrictions: 3,281 out of 44,800 7%\r\r
-\r\r
- A LUT Flip Flop pair for this architecture represents one LUT paired with\r\r
- one Flip Flop within a slice. A control set is a unique combination of\r\r
- clock, reset, set, and enable signals for a registered element.\r\r
- The Slice Logic Distribution report is not meaningful if the design is\r\r
- over-mapped for a non-slice resource or if Placement fails.\r\r
- OVERMAPPING of BRAM resources should be ignored if the design is\r\r
- over-mapped for a non-BRAM resource or if placement fails.\r\r
-\r\r
-IO Utilization:\r\r
- Number of bonded IOBs: 255 out of 640 39%\r\r
- Number of LOCed IOBs: 255 out of 255 100%\r\r
- IOB Flip Flops: 494\r\r
- Number of bonded IPADs: 4 out of 50 8%\r\r
- Number of bonded OPADs: 2 out of 32 6%\r\r
-\r\r
-Specific Feature Utilization:\r\r
- Number of BlockRAM/FIFO: 22 out of 148 14%\r\r
- Number using BlockRAM only: 20\r\r
- Number using FIFO only: 2\r\r
- Total primitives used:\r\r
- Number of 36k BlockRAM used: 16\r\r
- Number of 18k BlockRAM used: 6\r\r
- Number of 36k FIFO used: 2\r\r
- Total Memory used (KB): 756 out of 5,328 14%\r\r
- Number of BUFG/BUFGCTRLs: 15 out of 32 46%\r\r
- Number used as BUFGs: 15\r\r
- Number of IDELAYCTRLs: 3 out of 22 13%\r\r
- Number of BUFDSs: 1 out of 8 12%\r\r
- Number of BUFIOs: 8 out of 80 10%\r\r
- Number of DCM_ADVs: 1 out of 12 8%\r\r
- Number of DSP48Es: 13 out of 128 10%\r\r
- Number of GTX_DUALs: 1 out of 8 12%\r\r
- Number of PCIEs: 1 out of 3 33%\r\r
- Number of LOCed PCIEs: 1 out of 1 100%\r\r
- Number of PLL_ADVs: 2 out of 6 33%\r\r
- Number of PPC440s: 1 out of 1 100%\r\r
-\r\r
- Number of RPM macros: 64\r\r
-Average Fanout of Non-Clock Nets: 3.80\r\r
-\r\r
-Peak Memory Usage: 888 MB\r\r
-Total REAL time to MAP completion: 24 mins 23 secs \r\r
-Total CPU time to MAP completion: 23 mins 18 secs \r\r
-\r\r
-Mapping completed.\r\r
-See MAP report file "system_map.mrp" for details.\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program par\r\r
-# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd\r\r
-system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - par L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>\r\r
-\r\r
-\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-\r\r
-Constraints file: system.pcf.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(90242)]\r\r
- overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(90241)].\r\r
-\r\r
-\r\r
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)\r\r
-Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)\r\r
-\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP \r\r
- "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.\r\r
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please\r\r
- consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.\r\r
-\r\r
-Device speed data version: "PRODUCTION 1.65 2009-06-01".\r\r
-\r\r
-\r\r
-\r\r
-Device Utilization Summary:\r\r
-\r\r
- Number of BUFDSs 1 out of 8 12%\r\r
- Number of BUFGs 15 out of 32 46%\r\r
- Number of BUFIOs 8 out of 80 10%\r\r
- Number of DCM_ADVs 1 out of 12 8%\r\r
- Number of DSP48Es 13 out of 128 10%\r\r
- Number of FIFO36_72_EXPs 2 out of 148 1%\r\r
- Number of LOCed FIFO36_72_EXPs 2 out of 2 100%\r\r
-\r\r
- Number of GTX_DUALs 1 out of 8 12%\r\r
- Number of IDELAYCTRLs 3 out of 22 13%\r\r
- Number of LOCed IDELAYCTRLs 3 out of 3 100%\r\r
-\r\r
- Number of ILOGICs 131 out of 800 16%\r\r
- Number of LOCed ILOGICs 8 out of 131 6%\r\r
-\r\r
- Number of External IOBs 255 out of 640 39%\r\r
- Number of LOCed IOBs 255 out of 255 100%\r\r
-\r\r
- Number of IODELAYs 80 out of 800 10%\r\r
- Number of LOCed IODELAYs 8 out of 80 10%\r\r
-\r\r
- Number of External IPADs 4 out of 690 1%\r\r
- Number of LOCed IPADs 4 out of 4 100%\r\r
-\r\r
- Number of JTAGPPCs 1 out of 1 100%\r\r
- Number of OLOGICs 236 out of 800 29%\r\r
- Number of External OPADs 2 out of 32 6%\r\r
- Number of LOCed OPADs 2 out of 2 100%\r\r
-\r\r
- Number of PCIEs 1 out of 3 33%\r\r
- Number of LOCed PCIEs 1 out of 1 100%\r\r
-\r\r
- Number of PLL_ADVs 2 out of 6 33%\r\r
- Number of PPC440s 1 out of 1 100%\r\r
- Number of RAMB18X2SDPs 4 out of 148 2%\r\r
- Number of RAMB36SDP_EXPs 6 out of 148 4%\r\r
- Number of LOCed RAMB36SDP_EXPs 1 out of 6 16%\r\r
-\r\r
- Number of RAMB36_EXPs 10 out of 148 6%\r\r
- Number of LOCed RAMB36_EXPs 6 out of 10 60%\r\r
-\r\r
- Number of Slice Registers 14755 out of 44800 32%\r\r
- Number used as Flip Flops 14754\r\r
- Number used as Latches 1\r\r
- Number used as LatchThrus 0\r\r
-\r\r
- Number of Slice LUTS 16419 out of 44800 36%\r\r
- Number of Slice LUT-Flip Flop pairs 21404 out of 44800 47%\r\r
-\r\r
-\r\r
-Overall effort level (-ol): High \r\r
-Router effort level (-rl): High \r\r
-\r\r
-Starting initial Timing Analysis. REAL time: 1 mins 25 secs \r\r
-Finished initial Timing Analysis. REAL time: 1 mins 27 secs \r\r
-\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-Starting Router\r\r
-\r\r
-INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note\r\r
- that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,\r\r
- verify that the same connectivity is available in the target device for this implementation. \r\r
-\r\r
-Phase 1 : 106522 unrouted; REAL time: 1 mins 45 secs \r\r
-\r\r
-Phase 2 : 93293 unrouted; REAL time: 2 mins \r\r
-\r\r
-Phase 3 : 39046 unrouted; REAL time: 4 mins 11 secs \r\r
-\r\r
-Phase 4 : 39025 unrouted; (Setup:0, Hold:89741, Component Switching Limit:0) REAL time: 4 mins 40 secs \r\r
-\r\r
-Updating file: system.ncd with current fully routed design.\r\r
-\r\r
-Phase 5 : 0 unrouted; (Setup:0, Hold:90756, Component Switching Limit:0) REAL time: 6 mins 33 secs \r\r
-\r\r
-Phase 6 : 0 unrouted; (Setup:0, Hold:90756, Component Switching Limit:0) REAL time: 6 mins 33 secs \r\r
-\r\r
-Phase 7 : 0 unrouted; (Setup:0, Hold:90756, Component Switching Limit:0) REAL time: 6 mins 33 secs \r\r
-\r\r
-Phase 8 : 0 unrouted; (Setup:0, Hold:90756, Component Switching Limit:0) REAL time: 6 mins 33 secs \r\r
-\r\r
-Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 30 secs \r\r
-\r\r
-Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 9 mins 7 secs \r\r
-Total REAL time to Router completion: 9 mins 7 secs \r\r
-Total CPU time to Router completion: 8 mins 54 secs \r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-Generating "PAR" statistics.\r\r
-\r\r
-**************************\r\r
-Generating Clock Report\r\r
-**************************\r\r
-\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_125_0000MHzPLL0_ | | | | | |\r\r
-| ADJUST | BUFGCTRL_X0Y2| No | 4263 | 0.532 | 2.076 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/Bridge_C | | | | | |\r\r
-| lk |BUFGCTRL_X0Y28| No | 1472 | 0.444 | 2.085 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_62_5000MHzPLL0_A | | | | | |\r\r
-| DJUST | BUFGCTRL_X0Y6| No | 490 | 0.318 | 2.057 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_125_0000MHz90PLL | | | | | |\r\r
-| 0_ADJUST | BUFGCTRL_X0Y5| No | 162 | 0.254 | 2.028 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_SysACE_Compac | | | | | |\r\r
-|tFlash_SysACE_CLK_pi | | | | | |\r\r
-| n_BUFGP | BUFGCTRL_X0Y8| No | 55 | 0.150 | 1.770 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/core_c | | | | | |\r\r
-| lk |BUFGCTRL_X0Y27| No | 94 | 0.260 | 2.085 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_Ethernet_MAC_ | | | | | |\r\r
-|PHY_rx_clk_pin_BUFGP | | | | | |\r\r
-| |BUFGCTRL_X0Y30| No | 12 | 0.093 | 1.934 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<0> | IO Clk| No | 18 | 0.095 | 0.419 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<1> | IO Clk| No | 18 | 0.083 | 0.380 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<2> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<3> | IO Clk| No | 18 | 0.107 | 0.404 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | |\r
- | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<5> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<4> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<6> | IO Clk| No | 18 | 0.096 | 0.393 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<7> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_Ethernet_MAC_ | | | | | |\r\r
-|PHY_tx_clk_pin_BUFGP | | | | | |\r\r
-| |BUFGCTRL_X0Y31| No | 6 | 0.004 | 1.941 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No | 2 | 0.000 | 1.739 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/pcie_b | | | | | |\r\r
-| lk/gt_usrclk |BUFGCTRL_X0Y29| No | 6 | 0.096 | 1.916 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| clk_200_0000MHz | BUFGCTRL_X0Y4| No | 4 | 0.128 | 1.879 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|RS232_Uart_1_Interru | | | | | |\r\r
-| pt | Local| | 1 | 0.000 | 1.071 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|Ethernet_MAC/Etherne | | | | | |\r\r
-| t_MAC/phy_tx_clk_i | Local| | 9 | 2.410 | 3.454 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|ppc440_0_jtagppc_bus | | | | | |\r\r
-| _JTGC405TCK | Local| | 1 | 0.000 | 1.678 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/pcie_b | | | | | |\r\r
-|lk/SIO/.pcie_gt_wrap | | | | | |\r\r
-| per_i/icdrreset<0> | Local| | 1 | 0.000 | 0.590 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-\r\r
-* Net Skew is the difference between the minimum and maximum routing\r\r
-only delays for the net. Note this is different from Clock Skew which\r\r
-is reported in TRCE timing report. Clock Skew is the difference between\r\r
-the minimum and maximum path delays which includes logic delays.\r\r
-\r\r
-Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)\r\r
-\r\r
-Number of Timing Constraints that were not applied: 5\r\r
-\r\r
-Asterisk (*) preceding a constraint indicates it was not met.\r\r
- This may be due to a setup or hold violation.\r\r
-\r\r
-----------------------------------------------------------------------------------------------------------\r\r
- Constraint | Check | Worst Case | Best Case | Timing | Timing \r\r
- | | Slack | Achievable | Errors | Score \r\r
-----------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP | 0.030ns| 7.970ns| 0| 0\r\r
- s HIGH 50% | HOLD | 0.030ns| | 0| 0\r\r
- | MINPERIOD | 0.000ns| 8.000ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP | 0.075ns| 3.925ns| 0| 0\r\r
- lus/comp_endpoint/core_clk" PERIOD = | HOLD | 0.366ns| | 0| 0\r\r
- 4 ns HIGH 50% | MINPERIOD | 0.000ns| 4.000ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.012ns| 0.838ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[2].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP | 0.021ns| 1.879ns| 0| 0\r\r
- CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS" | HOLD | 1.026ns| | 0| 0\r\r
- 1.9 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 0.026ns| 7.974ns| 0| 0\r\r
- L0_CLK_OUT_2_ = PERIOD TIMEGRP "c | HOLD | 0.079ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_2_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[0].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[1].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[5].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[3].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[4].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[6].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[7].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.068ns| 0.532ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<0>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<1>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<2>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<3>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<4>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<5>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<6>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<7>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP | 0.449ns| 7.551ns| 0| 0\r\r
- _Clk" TO TIMEGRP "Bridge_Clk" 8 ns | HOLD | 0.456ns| | 0| 0\r\r
- DATAPATHONLY | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP | 0.639ns| 7.361ns| 0| 0\r\r
- ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns | HOLD | 0.465ns| | 0| 0\r\r
- DATAPATHONLY | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns | MINPERIOD | 1.010ns| 3.990ns| 0| 0\r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY | 1.640ns| 4.360ns| 0| 0\r\r
- RP "PADS" TO TIMEGRP "RXCLK_GRP_E | HOLD | 1.060ns| | 0| 0\r\r
- thernet_MAC" 6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 2.000ns| 4.973ns| 0| 0\r\r
- L0_CLK_OUT_0_ = PERIOD TIMEGRP "c | HOLD | 0.476ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_0_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- PHASE 2 ns HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 6.000ns| 4.000ns| 0| 0\r\r
- pin" 100 MHz HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.644ns| 1.356ns| 0| 0\r\r
- L0_CLK_OUT_3_ = PERIOD TIMEGRP "c | HOLD | 0.476ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_3_" TS_sys_clk_pin * 2 HIG | | | | | \r\r
- H 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 4.149ns| 8.008ns| 0| 0\r\r
- L0_CLK_OUT_4_ = PERIOD TIMEGRP "c | HOLD | 0.172ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_4_" TS_sys_clk_pin * 0.625 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW | 4.422ns| 0.578ns| 0| 0\r\r
- UFGP" MAXSKEW = 5 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW | 4.778ns| 0.222ns| 0| 0\r\r
- UFGP" MAXSKEW = 5 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | MINPERIOD | 4.900ns| 3.100ns| 0| 0\r\r
- L0_CLK_OUT_1_ = PERIOD TIMEGRP "c | | | | | \r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_1_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY | 7.423ns| 2.577ns| 0| 0\r\r
- GRP "TXCLK_GRP_Ethernet_MAC" TO T | | | | | \r\r
- IMEGRP "PADS" 10 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP | 9.210ns| 13.685ns| 0| 0\r\r
- UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.479ns| | 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP | 13.663ns| 6.337ns| 0| 0\r\r
- M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.290ns| | 0| 0\r\r
- TIMEGRP "TNM_CLK90" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP | 15.735ns| 4.265ns| 0| 0\r\r
- TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.915ns| | 0| 0\r\r
- TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 17.698ns| 2.302ns| 0| 0\r\r
- NM_GATE_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.003ns| | 0| 0\r\r
- TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP | 18.121ns| 1.879ns| 0| 0\r\r
- P "TNM_CAL_RDEN_DLY" TO TIMEGRP " | HOLD | 0.001ns| | 0| 0\r\r
- TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 18.132ns| 1.868ns| 0| 0\r\r
- NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.023ns| | 0| 0\r\r
- TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP | 26.579ns| 3.421ns| 0| 0\r\r
- K_pin_BUFGP/IBUFG" PERIOD = 30 ns | HOLD | 0.465ns| | 0| 0\r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP | 32.855ns| 7.145ns| 0| 0\r\r
- UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.357ns| | 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- Pin to Pin Skew Constraint | MAXDELAY | 2106523.523ns| 2106523.837ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A | N/A| N/A| N/A| N/A\r\r
- P "TNM_RDEN_SEL_MUX" TO TIMEGRP " | | | | | \r\r
- TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A | N/A| N/A| N/A| N/A\r\r
- s HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
-\r\r
-\r\r
-Derived Constraint Report\r\r
-Derived Constraints for TS_MC_CLK\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-| | Period | Actual Period | Timing Errors | Paths Analyzed |\r\r
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-|TS_MC_CLK | 5.000ns| 3.990ns| 1.584ns| 0| 0| 0| 345|\r\r
-| TS_MC_PHY_INIT_DATA_SEL_0 | 20.000ns| 4.265ns| N/A| 0| 0| 21| 0|\r\r
-| TS_MC_PHY_INIT_DATA_SEL_90 | 20.000ns| 6.337ns| N/A| 0| 0| 274| 0|\r\r
-| TS_MC_GATE_DLY | 20.000ns| 2.302ns| N/A| 0| 0| 40| 0|\r\r
-| TS_MC_RDEN_DLY | 20.000ns| 1.868ns| N/A| 0| 0| 5| 0|\r\r
-| TS_MC_CAL_RDEN_DLY | 20.000ns| 1.879ns| N/A| 0| 0| 5| 0|\r\r
-| TS_MC_RDEN_SEL_MUX | 20.000ns| N/A| N/A| 0| 0| 0| 0|\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-\r\r
-Derived Constraints for TS_sys_clk_pin\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-| | Period | Actual Period | Timing Errors | Paths Analyzed |\r\r
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-|TS_sys_clk_pin | 10.000ns| 4.000ns| 9.967ns| 0| 0| 0| 4043451|\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 4.973ns| N/A| 0| 0| 626| 0|\r\r
-| erator_0_PLL0_CLK_OUT_0_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 3.100ns| N/A| 0| 0| 0| 0|\r\r
-| erator_0_PLL0_CLK_OUT_1_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 7.974ns| N/A| 0| 0| 4031781| 0|\r\r
-| erator_0_PLL0_CLK_OUT_2_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 5.000ns| 1.356ns| N/A| 0| 0| 2| 0|\r\r
-| erator_0_PLL0_CLK_OUT_3_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 16.000ns| 8.008ns| N/A| 0| 0| 11042| 0|\r\r
-| erator_0_PLL0_CLK_OUT_4_ | | | | | | | |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-\r\r
-All constraints were met.\r\r
-INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the \r\r
- constraint does not cover any paths or that it has no requested value.\r\r
-\r\r
-\r\r
-Generating Pad Report.\r\r
-\r\r
-All signals are completely routed.\r\r
-\r\r
-WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.\r\r
-\r\r
-Loading device for application Rf_Device from file '5vlx50t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
-INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128\r\r
-INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints\r\r
- found: 128, number successful: 128\r\r
-Total REAL time to PAR completion: 10 mins 4 secs \r\r
-Total CPU time to PAR completion: 9 mins 36 secs \r\r
-\r\r
-Peak Memory Usage: 754 MB\r\r
-\r\r
-Placer: Placement generated during map.\r\r
-Routing: Completed - No errors found.\r\r
-Timing: Completed - No errors found.\r\r
-\r\r
-Number of error messages: 0\r\r
-Number of warning messages: 9\r\r
-Number of info messages: 4\r\r
-\r\r
-Writing design to file system.ncd\r\r
-\r\r
-\r\r
-\r\r
-PAR done!\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program post_par_trce\r\r
-# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - Trace (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =\r\r
- 8 ns HIGH 50%;> [system.pcf(90242)] overrides constraint <NET\r\r
- "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(90241)].\r\r
-\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
- TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;\r\r
- ignored during timing analysis.\r\r
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more\r\r
- information, see the TSI report. Please consult the Xilinx Command Line\r\r
- Tools User Guide for information on generating a TSI report.\r\r
---------------------------------------------------------------------------------\r\r
-Release 11.2 Trace (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf\r\r
-\r\r
-\r\r
-Design file: system.ncd\r\r
-Physical constraint file: system.pcf\r\r
-Device,speed: xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING\r\r
-level 0)\r\r
-Report level: error report\r\r
---------------------------------------------------------------------------------\r\r
-\r\r
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths\r\r
- option. All paths that are not constrained will be reported in the\r\r
- unconstrained paths section(s) of the report.\r\r
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a\r\r
- 50 Ohm transmission line loading model. For the details of this model, and\r\r
- for more information on accounting for different loading conditions, please\r\r
- see the device datasheet.\r\r
-\r\r
-\r\r
-Timing summary:\r\r
----------------\r\r
-\r\r
-Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)\r\r
-\r\r
-Constraints cover 4233435 paths, 18 nets, and 96471 connections\r\r
-\r\r
-Design statistics:\r\r
- Minimum period: 13.685ns (Maximum frequency: 73.073MHz)\r\r
- Maximum path delay from/to any node: 7.551ns\r\r
- Maximum net delay: 0.838ns\r\r
- Maximum net skew: 0.578ns\r\r
-\r\r
-\r\r
-Analysis completed Tue Jun 30 23:01:07 2009\r\r
---------------------------------------------------------------------------------\r\r
-\r\r
-Generating Report ...\r\r
-\r\r
-Number of warnings: 2\r\r
-Number of info messages: 3\r\r
-Total time: 1 mins 41 secs \r\r
-\r\r
-\r\r
-xflow done!\r\r
-touch __xps/system_routed\r
-xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par\r
-Analyzing implementation/system.par\r\r
-*********************************************\r
-Running Bitgen..\r
-*********************************************\r
-cd implementation; bitgen -w -f bitgen.ut system; cd ..\r
-Release 11.2 - Bitgen L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-Opened constraints file system.pcf.\r\r
-\r\r
-Tue Jun 30 23:01:40 2009\r\r
-\r\r
-Running DRC.\r\r
-WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.\r\r
- Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX\r\r
- Transceiver User Guide to ensure that the design SelectIO usage meets the\r\r
- guidelines to minimize the impact on GTX performance. \r\r
-WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
- Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.\r\r
- This is not good design practice. Use the CE pin to control the loading of\r\r
- data into the flip-flop.\r\r
-WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w\r\r
- rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good\r\r
- design practice. Use the CE pin to control the loading of data into the\r\r
- flip-flop.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does\r\r
- not drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>\r\r
- is incomplete. The signal does not drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <ppc440_0_apu_fpu_virtex5/ppc440_0_apu_fpu_virtex5/gen_apu_fpu_dp_lo.netlist/\r\r
- fpu_is_full.sqrt_sqrt_flt_pt_op_sqrt_op.spd.op_exp_exp_sig_del_delay_55_2/Pro\r\r
- toComp7000.C6LUT.O6> is incomplete. The signal does not drive any load pins\r\r
- in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <ppc440_0_apu_fpu_virtex5/ppc440_0_apu_fpu_virtex5/gen_apu_fpu_dp_lo.netlist/\r\r
- fpu_is_full.sqrt_sqrt_flt_pt_op_sqrt_op.spd.op_exp_exp_sig_del_delay_55_1/Pro\r\r
- toComp7000.C6LUT.O6> is incomplete. The signal does not drive any load pins\r\r
- in the design.\r\r
-DRC detected 0 errors and 26 warnings. Please see the previously displayed\r\r
-individual error or warning messages for more details.\r\r
-Creating bit map...\r\r
-Saving bit stream in "system.bit".\r\r
-Bitstream generation is complete.\r\r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Wed Jul 01 10:06:56 2009
- make -f system.make download started...
-\r
-cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf\r
-*********************************************\r
-Initializing BRAM contents of the bitstream\r
-*********************************************\r
-bitinit -p xc5vfx70tff1136-1 system.mhs -pe ppc440_0 bootloops/ppc440_0.elf \\r
--bt implementation/system.bit -o implementation/download.bit\r
-\r\r
-bitinit version Xilinx EDK 11.2 Build EDK_LS3.47\r\r
-Copyright (c) Xilinx Inc. 2002.\r\r
-\r\r
-Parsing MHS File system.mhs...\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Overriding IP level properties ...\r\r
-\r\r
-Performing IP level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
-Address Map for Processor ppc440_0\r\r
- (0b0000000000-0b0011111111) ppc440_0 \r\r
- (0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC\r\r
- (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0\r\r
- (0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0\r\r
- (0x81420000-0x8142ffff) LEDs_Positions plb_v46_0\r\r
- (0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0\r\r
- (0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0\r\r
- (0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0\r\r
- (0x81800000-0x8180ffff) xps_intc_0 plb_v46_0\r\r
- (0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0\r\r
- (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0\r\r
- (0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0\r\r
- (0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0\r\r
- (0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0\r\r
- (0xf8000000-0xf80fffff) SRAM plb_v46_0\r\r
- (0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
- C_SPLB0_P2P value to 0\r\r
-\r\r
-Computing clock values...\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 12\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
- PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
- PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
- value to 0x2000\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PORT_DWIDTH value to 64\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
- value to 8\r\r
-INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
- _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
- ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
- C_MPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
- C_MPLB_SMALLEST_SLAVE value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
- 2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-\r\r
-Checking platform address map ...\r\r
-\r\r
-Initializing Memory...\r\r
-Running Data2Mem with the following command:\r\r
-data2mem -bm "implementation/system_bd" -bt "implementation/system.bit" -bd\r\r
-"bootloops/ppc440_0.elf" tag ppc440_0 -o b implementation/download.bit \r\r
-Memory Initialization completed successfully.\r\r
-\r\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
-write (count, cmdBuffer, dataBuffer) failed C0000004.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2301.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-Downloading c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex.\r\r
-Downloaded firmware version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 1 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-5: Device Temperature: Current Reading: 41.02 C, Min. Reading: 27.73 C, Max.\r\r
-Reading: 41.02 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.505 V, Min. Reading: 2.502 V, Max.\r\r
-Reading: 2.508 V\r\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Wed Jul 01 10:07:40 2009
- make -f system.make program started...
-\r
-*********************************************\r
-Creating software libraries...\r
-*********************************************\r
-libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss\r
-libgen\r\r
-Xilinx EDK 11.2 Build EDK_LS3.47\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
-__xps/ise/xmsgprops.lst system.mss \r\r
-\r\r
-Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Checking platform configuration ...\r\r
-IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 109 - 1 master(s) : 12 slave(s)\r\r
-IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 290 - 1 master(s) : 1 slave(s)\r\r
-IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 394 - 1 master(s) : 1 slave(s)\r\r
-\r\r
-Checking port drivers...\r\r
-WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 461 - floating connection!\r\r
-\r\r
-Performing Clock DRCs...\r\r
-\r\r
-Performing Reset DRCs...\r\r
-\r\r
-Overriding system level properties...\r\r
-\r\r
-Running system level update procedures...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
-\r\r
-Running system level DRCs...\r\r
-\r\r
-Performing System level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
-WARNING:EDK:411 - pcie -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- ss line 77 - deprecated driver!\r\r
-WARNING:EDK:411 - emaclite -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- ss line 83 - deprecated driver!\r\r
-INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
- - DDR2_SDRAM\r\r
- - DIP_Switches_8Bit\r\r
- - Ethernet_MAC\r\r
- - IIC_EEPROM\r\r
- - LEDs_8Bit\r\r
- - LEDs_Positions\r\r
- - PCIe_Bridge\r\r
- - Push_Buttons_5Bit\r\r
- - RS232_Uart_1\r\r
- - SRAM\r\r
- - SysACE_CompactFlash\r\r
- - ppc440_0_apu_fpu_virtex5\r\r
- - xps_bram_if_cntlr_1\r\r
- - xps_intc_0\r\r
-\r\r
--- Generating libraries for processor: ppc440_0 --\r\r
-\r\r
-\r\r
-Staging source files.\r\r
-Running DRCs.\r\r
-Running generate.\r\r
-Running post_generate.\r\r
-Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
-"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440 -O2 -c"\r\r
-"EXTRA_COMPILER_FLAGS=-g"'.\r\r
-\r\r
-Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
-"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440 -O2 -c"\r\r
-"EXTRA_COMPILER_FLAGS=-g"'.\r\r
-Compiling common\r
-powerpc-eabi-ar: creating ../../../lib/libxil.a
-\r
-Compiling lldma\r
-Compiling standalone\r
-Compiling gpio\r
-Compiling emaclite\r
-Compiling iic\r
-Compiling pci\r
-Compiling uartlite\r
-Compiling sysace\r
-Compiling intc\r
-Compiling cpu_ppc440\r
-Running execs_generate.\r\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51202 372 87844 139418 2209a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Wed Jul 01 11:26:01 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 1 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 33.15 C, Min. Reading: 30.69 C, Max.\r\r
-Reading: 33.64 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.505 V, Min. Reading: 2.502 V, Max.\r\r
-Reading: 2.508 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-Done.
-\r
-Done.
-\r
-Done.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-Done.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-Done.
-\r
-Done.
-\r
-Done.
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Wed Jul 01 17:11:24 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 150 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 3 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 42.99 C, Min. Reading: 34.13 C, Max.\r\r
-Reading: 42.99 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.505 V, Min. Reading: 2.502 V, Max.\r\r
-Reading: 2.505 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 12 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-At Local date and time: Wed Jul 01 17:17:34 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 150 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 0 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 62.68 C, Min. Reading: 62.68 C, Max.\r\r
-Reading: 66.13 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.996 V, Max.\r\r
-Reading: 0.999 V\r\r
-5: VCCAUX Supply: Current Reading: 2.502 V, Min. Reading: 2.502 V, Max.\r\r
-Reading: 2.505 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-Done.
-\r
-Done.
-\r
-Done.
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-At Local date and time: Wed Jul 01 18:45:58 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 3 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 42.99 C, Min. Reading: 37.58 C, Max.\r\r
-Reading: 42.99 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 0.999 V\r\r
-5: VCCAUX Supply: Current Reading: 2.505 V, Min. Reading: 2.502 V, Max.\r\r
-Reading: 2.505 V\r\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Thu Jul 02 09:58:07 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51202 372 87844 139418 2209a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 09:58:40 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
-write (count, cmdBuffer, dataBuffer) failed C0000004.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2301.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-Downloading c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex.\r\r
-Downloaded firmware version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 2 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 32.16 C, Min. Reading: 30.20 C, Max.\r\r
-Reading: 32.66 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.505 V, Min. Reading: 2.505 V, Max.\r\r
-Reading: 2.508 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-At Local date and time: Thu Jul 02 10:23:31 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50962 372 87844 139178 21faa RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-At Local date and time: Thu Jul 02 10:27:44 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 1 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 41.02 C, Min. Reading: 36.10 C, Max.\r\r
-Reading: 41.02 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.502 V, Min. Reading: 2.502 V, Max.\r\r
-Reading: 2.505 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 11:09:53 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51014 372 87852 139238 21fe6 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 11:19:46 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50970 372 87852 139194 21fba RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 11:36:56 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50962 372 87844 139178 21faa RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 11:45:58 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51002 372 87852 139226 21fda RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 11:50:02 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51010 372 87860 139242 21fea RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 11:55:33 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51006 372 87860 139238 21fe6 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 13:28:01 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51250 372 87860 139482 220da RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 13:29:26 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51242 372 87852 139466 220ca RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 13:31:57 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 1 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 74.00 C, Min. Reading: 41.02 C, Max.\r\r
-Reading: 74.49 C\r\r
-5: VCCINT Supply: Current Reading: 0.993 V, Min. Reading: 0.993 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.496 V, Min. Reading: 2.493 V, Max.\r\r
-Reading: 2.505 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-At Local date and time: Thu Jul 02 13:35:43 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 1 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 73.02 C, Min. Reading: 70.06 C, Max.\r\r
-Reading: 74.00 C\r\r
-5: VCCINT Supply: Current Reading: 0.993 V, Min. Reading: 0.993 V, Max.\r\r
-Reading: 0.999 V\r\r
-5: VCCAUX Supply: Current Reading: 2.496 V, Min. Reading: 2.493 V, Max.\r\r
-Reading: 2.502 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 12 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-At Local date and time: Thu Jul 02 13:38:54 2009
- make -f system.make program started...
-\r
-make: Nothing to be done for `program'.\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 13:39:15 2009
- make -f system.make programclean started...
-\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 13:39:21 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50774 372 87852 138998 21ef6 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 13:52:39 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50566 372 87852 138790 21e26 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 13:53:08 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50542 372 87860 138774 21e16 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 14:02:13 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50222 372 87860 138454 21cd6 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 14:20:50 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50298 372 87852 138522 21d1a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:31:05 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c: In function 'vSecondaryBlockTimeTestTask':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: 'tskTCB' has no member named 'xEventTaskList'
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1542: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
-\r
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:31:42 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c: In function 'vSecondaryBlockTimeTestTask':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: 'tskTCB' has no member named 'xEventList'
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1542: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
-\r
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:32:24 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1542: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51246 372 87844 139462 220c6 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:38:48 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1548: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1549: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: 'xSecondary' undeclared (first use in this function)
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: (Each undeclared identifier is reported only once
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: for each function it appears in.)
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
-\r
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:46:20 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1548: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1549: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: 'xSecondary' undeclared (first use in this function)
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: (Each undeclared identifier is reported only once
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: for each function it appears in.)
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
-\r
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:47:05 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1550: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1551: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51334 372 87852 139558 22126 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:48:10 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 0 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 69.08 C, Min. Reading: 66.62 C, Max.\r\r
-Reading: 75.48 C\r\r
-5: VCCINT Supply: Current Reading: 0.993 V, Min. Reading: 0.990 V, Max.\r\r
-Reading: 0.999 V\r\r
-5: VCCAUX Supply: Current Reading: 2.496 V, Min. Reading: 2.493 V, Max.\r\r
-Reading: 2.505 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-At Local date and time: Thu Jul 02 15:52:34 2009
- make -f system.make program started...
-\r
-make: Nothing to be done for `program'.\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:54:04 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c: In function 'vSecondaryBlockTimeTestTask':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: warning: dereferencing 'void *' pointer
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: request for member 'xEventListItem' in something not a structure or union
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSuspend':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: warning: dereferencing 'void *' pointer
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: error: request for member 'xEventListItem' in something not a structure or union
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1593: error: invalid operands to binary ==
-\r
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:55:43 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSuspend':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: warning: dereferencing 'void *' pointer
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: error: request for member 'xEventListItem' in something not a structure or union
-\r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1593: error: invalid operands to binary ==
-\r
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:57:13 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1593: error: cannot convert to a pointer type
-\r
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 15:58:01 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51338 372 87852 139562 2212a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 16:00:52 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51338 372 87852 139562 2212a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 16:32:08 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51878 372 87852 140102 22346 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Thu Jul 02 17:37:11 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51910 372 87852 140134 22366 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 17:37:43 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
-write (count, cmdBuffer, dataBuffer) failed C0000004.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2301.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-Downloading c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex.\r\r
-Downloaded firmware version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 2 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 42.99 C, Min. Reading: 37.58 C, Max.\r\r
-Reading: 44.47 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.505 V, Min. Reading: 2.502 V, Max.\r\r
-Reading: 2.508 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 18:25:53 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 51950 372 87844 140166 22386 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 20:25:21 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'xTaskCheckForTimeOut':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: error: 'xNumOfOverflows' undeclared (first use in this function)
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: error: (Each undeclared identifier is reported only once
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: error: for each function it appears in.)
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:77: error: 'pdTRUE' undeclared (first use in this function)
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:84: error: 'pdFALSE' undeclared (first use in this function)
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: At top level:
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:96: warning: conflicting types for 'vTaskSetTimeOutState'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:83: warning: previous implicit declaration of 'vTaskSetTimeOutState' was here
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'vTaskSetTimeOutState':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:97: error: 'xNumOfOverflows' undeclared (first use in this function)
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:109: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:111: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:116: error: expected expression before 'xTimeOutType'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:132: error: 'pdTRUE' undeclared (first use in this function)
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:134: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:142: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:150: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:103: warning: return type of 'main' is not 'int'
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 20:27:35 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:53:19: error: conio.h: No such file or directory
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:113: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:115: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:184: warning: incompatible implicit declaration of built-in function 'exit'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:107: warning: return type of 'main' is not 'int'
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 20:28:16 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:111: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:113: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:136: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:144: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:152: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:157: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:176: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:181: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:182: warning: incompatible implicit declaration of built-in function 'exit'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:105: warning: return type of 'main' is not 'int'
-\r
-/\r
-cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o: In function `vTaskSetTimeOutState':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: multiple definition of `vTaskSetTimeOutState'
-/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o:/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1697: first defined here
-/cygdrive/c/devtools/Xilinx/11.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: Warning: size of symbol `vTaskSetTimeOutState' changed from 68 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o to 72 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o
-/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o: In function `xTaskCheckForTimeOut':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:77: multiple definition of `xTaskCheckForTimeOut'
-/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o:/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1704: first defined here
-/cygdrive/c/devtools/Xilinx/11.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: Warning: size of symbol `xTaskCheckForTimeOut' changed from 388 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o to 276 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o
-/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o: In function `vTaskSwitchContext':
-tasks.c:(.text+0x1798): undefined reference to `vApplicationStackOverflowHook'
-tasks.c:(.text+0x17e8): undefined reference to `vApplicationStackOverflowHook'
-/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o: In function `main':
-main.c:(.text+0x2f4): undefined reference to `kbhit'
-main.c:(.text+0x304): undefined reference to `getch'
-collect2: ld returned 1 exit status
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 20:31:20 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:117: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:143: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:105: warning: return type of 'main' is not 'int'
-\r
-/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccZOTZW1.o: In function `vTaskSwitchContext':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1556: undefined reference to `vApplicationStackOverflowHook'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1557: undefined reference to `vApplicationStackOverflowHook'
-collect2: ld returned 1 exit status
-make: *** [RTOSDemo/executable.elf] Error 1
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 20:31:50 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:146: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50578 368 87832 138778 21e1a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 20:32:59 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:148: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50706 368 87832 138906 21e9a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 20:38:30 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:148: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50706 368 87832 138906 21e9a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 20:40:24 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:151: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50730 368 87840 138938 21eba RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 20:43:10 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:151: warning: incompatible implicit declaration of built-in function 'printf'
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50730 368 87840 138938 21eba RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-At Local date and time: Thu Jul 02 20:46:15 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50694 368 87840 138902 21e96 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 20:49:41 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50730 368 87840 138938 21eba RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 20:54:28 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50802 368 87832 139002 21efa RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 20:58:12 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50846 368 87832 139046 21f26 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 20:59:39 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:124: warning: comparison is always true due to limited range of data type
-/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
-\r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50866 368 87832 139066 21f3a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-At Local date and time: Thu Jul 02 21:29:34 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50622 372 87856 138850 21e62 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Done.
-\r
-Done.
-\r
-At Local date and time: Fri Jul 03 02:08:31 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 1 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 38.07 C, Min. Reading: 35.12 C, Max.\r\r
-Reading: 38.56 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.505 V, Min. Reading: 2.502 V, Max.\r\r
-Reading: 2.505 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Done.
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Fri Jul 03 18:19:28 2009
- make -f system.make download started...
-\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 5 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 59.23 C, Min. Reading: 38.07 C, Max.\r\r
-Reading: 74.99 C\r\r
-5: VCCINT Supply: Current Reading: 0.996 V, Min. Reading: 0.993 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.496 V, Min. Reading: 2.493 V, Max.\r\r
-Reading: 2.505 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-At Local date and time: Fri Jul 03 18:20:05 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O3 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=dp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D USE_DP_FPU -D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 44758 372 87852 132982 20776 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Sun Jul 05 09:36:55 2009
- make -f system.make hwclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-rm -rf implementation synthesis xst hdl\r
-rm -rf xst.srp system.srp\r
-rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Sun Jul 05 09:37:10 2009
- make -f system.make swclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
+++ /dev/null
- The following files will be modified:
- system.mhs
- system.mss
-
---------------------------------------
- The following changes will be made:
- Core ppc440mc_ddr2 2.00.a will be replaced by 2.00.b
- Core clock_generator 3.00.a will be replaced by 3.01.a
-
- Driver iic 1.14.a will be replaced by 1.15.a
- Driver cpu_ppc440 1.00.b will be replaced by 1.01.a
---------------------------------------
- The following changes need to be made manually by the user:
- Core plbv46_pcie 3.00.b needs to be replaced by 4.01.a
- Core xps_ethernetlite 2.01.a needs to be replaced by 3.00.a
+++ /dev/null
-No logfile was found.\r
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-The project file (XMP) has changed on disk.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-At Local date and time: Tue Jun 30 18:34:41 2009
- make -f system.make hwclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-rm -rf implementation synthesis xst hdl\r
-rm -rf xst.srp system.srp\r
-rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:34:46 2009
- make -f system.make bitsclean started...
-\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:34:52 2009
- make -f system.make netlistclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:34:57 2009
- make -f system.make libsclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:35:02 2009
- make -f system.make programclean started...
-\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:35:08 2009
- make -f system.make swclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Fri Jul 03 21:23:32 2009
- make -f system.make bits started...
-\r
-****************************************************\r
-Creating system netlist for hardware specification..\r
-****************************************************\r
-platgen -p xc5vfx70tff1136-1 -lang vhdl -msg __xps/ise/xmsgprops.lst system.mhs\r
-\r\r
-Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47\r\r
- (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-\r\r
-Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg\r\r
-__xps/ise/xmsgprops.lst system.mhs \r\r
-\r\r
-Parse\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mhs\r\r
-...\r\r
-\r\r
-Read MPD definitions ...\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Overriding IP level properties ...\r\r
-\r\r
-Performing IP level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
-Address Map for Processor ppc440_0\r\r
- (0b0000000000-0b0011111111) ppc440_0 \r\r
- (0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC\r\r
- (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0\r\r
- (0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0\r\r
- (0x81420000-0x8142ffff) LEDs_Positions plb_v46_0\r\r
- (0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0\r\r
- (0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0\r\r
- (0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0\r\r
- (0x81800000-0x8180ffff) xps_intc_0 plb_v46_0\r\r
- (0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0\r\r
- (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0\r\r
- (0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0\r\r
- (0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0\r\r
- (0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0\r\r
- (0xf8000000-0xf80fffff) SRAM plb_v46_0\r\r
- (0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
- C_SPLB0_P2P value to 0\r\r
-\r\r
-Computing clock values...\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 12\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
- PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
- PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
- value to 0x2000\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PORT_DWIDTH value to 64\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
- value to 8\r\r
-INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
- _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
- ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
- C_MPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
- C_MPLB_SMALLEST_SLAVE value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
- 2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-\r\r
-Checking platform address map ...\r\r
-\r\r
-Checking platform configuration ...\r\r
-INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - This design requires design constraints to guarantee\r\r
- performance.\r\r
- Please refer to the xps_ethernetlite_v2_00_a data sheet for details. \r\r
- The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs\r\r
- Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet\r\r
- operation.\r\r
-IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 109 - 1 master(s) : 12 slave(s)\r\r
-IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 290 - 1 master(s) : 1 slave(s)\r\r
-IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 394 - 1 master(s) : 1 slave(s)\r\r
-\r\r
-Checking port drivers...\r\r
-WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 462 - floating connection!\r\r
-\r\r
-Performing Clock DRCs...\r\r
-\r\r
-Performing Reset DRCs...\r\r
-\r\r
-Overriding system level properties...\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER\r\r
- C_PPC440MC_ADDR_BASE value to 0x00000000\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER\r\r
- C_PPC440MC_ADDR_HIGH value to 0x0fffffff\r\r
-INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0\r\r
- 1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER\r\r
- C_NUM_PPC_USED value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR\r\r
- value to 0b00000000000000000000000000000001\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE\r\r
- value to 0b00000000000000000000000000000001\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL\r\r
- value to 0b00000000000000000000000000000000\r\r
-\r\r
-Running system level update procedures...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
-\r\r
-Running system level DRCs...\r\r
-\r\r
-Performing System level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...\r\r
-INFO: The PCIe_Bridge core has constraints automatically generated by XPS in\r\r
-implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-INFO: The Ethernet_MAC core has constraints automatically generated by XPS in\r\r
-implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in\r\r
-implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-\r\r
-Modify defaults ...\r\r
-\r\r
-Creating stub ...\r\r
-\r\r
-Processing licensed instances ...\r\r
-Completion time: 0.00 seconds\r\r
-\r\r
-Creating hardware output directories ...\r\r
-\r\r
-Managing hardware (BBD-specified) netlist files ...\r\r
-IPNAME:plbv46_pcie INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 253 - Copying (BBD-specified) netlist files.\r\r
-IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 298 - Copying (BBD-specified) netlist files.\r\r
-IPNAME:apu_fpu_virtex5 INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 401 - Copying (BBD-specified) netlist files.\r\r
-\r\r
-Managing cache ...\r\r
-\r\r
-Elaborating instances ...\r\r
-IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 131 - elaborating IP\r\r
-\r\r
-Writing HDL for elaborated instances ...\r\r
-\r\r
-Inserting wrapper level ...\r\r
-Completion time: 2.00 seconds\r\r
-\r\r
-Constructing platform-level connectivity ...\r\r
-Completion time: 1.00 seconds\r\r
-\r\r
-Writing (top-level) BMM ...\r\r
-\r\r
-Writing (top-level and wrappers) HDL ...\r\r
-\r\r
-Generating synthesis project file ...\r\r
-\r\r
-Running XST synthesis ...\r\r
-\r\r
-INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option\r\r
- IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST\r\r
- synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. \r\r
-INSTANCE:ppc440_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 78 - Running XST synthesis\r\r
-INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 109 - Running XST synthesis\r\r
-INSTANCE:xps_bram_if_cntlr_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 118 - Running XST synthesis\r\r
-INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 131 - Running XST synthesis\r\r
-INSTANCE:rs232_uart_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 138 - Running XST synthesis\r\r
-INSTANCE:leds_8bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 154 - Running XST synthesis\r\r
-INSTANCE:leds_positions -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 168 - Running XST synthesis\r\r
-INSTANCE:push_buttons_5bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 182 - Running XST synthesis\r\r
-INSTANCE:dip_switches_8bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 196 - Running XST synthesis\r\r
-INSTANCE:iic_eeprom -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 210 - Running XST synthesis\r\r
-INSTANCE:sram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 223 - Running XST synthesis\r\r
-INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 253 - Running XST synthesis\r\r
-INSTANCE:ppc440_0_splb0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 290 - Running XST synthesis\r\r
-INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 298 - Running XST synthesis\r\r
-INSTANCE:ddr2_sdram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 317 - Running XST synthesis\r\r
-INSTANCE:sysace_compactflash -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 377 - Running XST synthesis\r\r
-INSTANCE:ppc440_0_fcb_v20 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 394 - Running XST synthesis\r\r
-INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 401 - Running XST synthesis\r\r
-INSTANCE:clock_generator_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 408 - Running XST synthesis\r\r
-INSTANCE:jtagppc_cntlr_inst -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 447 - Running XST synthesis\r\r
-INSTANCE:proc_sys_reset_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 453 - Running XST synthesis\r\r
-INSTANCE:xps_intc_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 465 - Running XST synthesis\r\r
-\r\r
-Running NGCBUILD ...\r\r
-IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 78 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..\r\r
-ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/ppc440_0_wrapper/ppc440_0_wrapper.ngc" ...\r\r
-\r\r
-Applying constraints in "ppc440_0_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ppc440_0_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 7 sec\r\r
-Total CPU time to NGCBUILD completion: 5 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 138 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc\r\r
-../rs232_uart_1_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/rs232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../rs232_uart_1_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 2 sec\r\r
-Total CPU time to NGCBUILD completion: 1 sec\r\r
-\r\r
-Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 253 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..\r\r
-pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/pcie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...\r\r
-Executing edif2ngd -noa\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\pcie_bridge_wrapper_fifo_generator_v4_3.edn"\r\r
-"pcie_bridge_wrapper_fifo_generator_v4_3.ngo"\r\r
-Release 11.2 - edif2ngd L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
-INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
-with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
-Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\pcie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
-Loading design module\r\r
-"../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\pcie_bridge_wrapper/dpram_70_512.ngc"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\pcie_bridge_wrapper/fifo_71x512.ngc"...\r\r
-\r\r
-Applying constraints in "pcie_bridge_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../pcie_bridge_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 13 sec\r\r
-Total CPU time to NGCBUILD completion: 7 sec\r\r
-\r\r
-Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 298 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..\r\r
-ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/ethernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...\r\r
-Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"\r\r
-"ethernetlite_v1_01_b_dmem_v2.ngo"\r\r
-Release 11.2 - edif2ngd L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
-INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
-with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
-Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\ethernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
-\r\r
-Applying constraints in "ethernet_mac_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ethernet_mac_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 8 sec\r\r
-Total CPU time to NGCBUILD completion: 5 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 317 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..\r\r
-ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...\r\r
-\r\r
-Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ddr2_sdram_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 6 sec\r\r
-Total CPU time to NGCBUILD completion: 5 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:ppc440_0_apu_fpu_virtex5_wrapper INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 401 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_apu_fpu_virtex5_wrapper.ucf -sd\r\r
-.. ppc440_0_apu_fpu_virtex5_wrapper.ngc ../ppc440_0_apu_fpu_virtex5_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/ppc440_0_apu_fpu_virtex5_wrapper/ppc440_0_apu_fpu_virtex5_wrapper.ngc" ...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
-tion\ppc440_0_apu_fpu_virtex5_wrapper/apu_fpu_sp_lo.ngc"...\r\r
-\r\r
-Applying constraints in "ppc440_0_apu_fpu_virtex5_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ppc440_0_apu_fpu_virtex5_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 6 sec\r\r
-Total CPU time to NGCBUILD completion: 5 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ppc440_0_apu_fpu_virtex5_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 465 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc\r\r
-../xps_intc_0_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/xps_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../xps_intc_0_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 2 sec\r\r
-Total CPU time to NGCBUILD completion: 1 sec\r\r
-\r\r
-Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-\r\r
-Rebuilding cache ...\r\r
-\r\r
-Total run time: 1330.00 seconds\r\r
-Running synthesis...\r
-bash -c "cd synthesis; ./synthesis.sh"\r
-xst -ifn system_xst.scr -intstyle silent\r
-Running XST synthesis ...\r
-XST completed\r
-Release 11.2 - ngcbuild L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Overriding Xilinx file <ngcflow.csf> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>\r\r
-\r\r
-Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe\r\r
-./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise\r\r
-../__xps/ise/system.ise\r\r
-\r\r
-Reading NGO file\r\r
-"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/synthesis/\r\r
-system.ngc" ...\r\r
-Loading design module "../implementation/ppc440_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/plb_v46_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...\r\r
-Loading design module\r\r
-"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...\r\r
-Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...\r\r
-Loading design module "../implementation/leds_8bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/leds_positions_wrapper.ngc"...\r\r
-Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/iic_eeprom_wrapper.ngc"...\r\r
-Loading design module "../implementation/sram_wrapper.ngc"...\r\r
-Loading design module "../implementation/pcie_bridge_wrapper.ngc"...\r\r
-Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...\r\r
-Loading design module "../implementation/ethernet_mac_wrapper.ngc"...\r\r
-Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...\r\r
-Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...\r\r
-Loading design module "../implementation/ppc440_0_fcb_v20_wrapper.ngc"...\r\r
-Loading design module\r\r
-"../implementation/ppc440_0_apu_fpu_virtex5_wrapper.ngc"...\r\r
-Loading design module "../implementation/clock_generator_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...\r\r
-Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/xps_intc_0_wrapper.ngc"...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../implementation/system.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 15 sec\r\r
-Total CPU time to NGCBUILD completion: 11 sec\r\r
-\r\r
-Writing NGCBUILD log file "../implementation/system.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-*********************************************\r
-Running Xilinx Implementation tools..\r
-*********************************************\r
-xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc\r
-Release 11.2 - Xflow L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise\r\r
-../__xps/ise/system.ise system.ngc \r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into\r\r
-working directory\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
-ion \r\r
-\r\r
-Using Flow File:\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
-ion/fpga.flw \r\r
-Using Option File(s): \r\r
- C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/xflow.opt \r\r
-\r\r
-Creating Script File ... \r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program ngdbuild\r\r
-# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm\r\r
-system.bmm\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/system.ngc" -uc system.ucf system.ngd \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - ngdbuild L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt\r\r
-timestamp -bm system.bmm\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
-ion/system.ngc -uc system.ucf system.ngd\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
-tion/system.ngc" ...\r\r
-Gathering constraint information from source properties...\r\r
-Done.\r\r
-\r\r
-Applying constraints in "system.ucf" to the design...\r\r
-WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance\r\r
- 'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_\r\r
- ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to\r\r
- 'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive. \r\r
- In order for functional simulation to be correct, the value of SIM_DEVICE\r\r
- should be changed in this same manner in the source netlist or constraint\r\r
- file.\r\r
-Resolving constraint associations...\r\r
-Checking Constraint Associations...\r\r
-WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM\r\r
- "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"\r\r
- * 4;> [system.ucf(264)]: This constraint will be ignored because the relative\r\r
- clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not\r\r
- found.\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *\r\r
- 1.25 PHASE 2 ns HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *\r\r
- 1.25 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *\r\r
- 1.25 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *\r\r
- 2 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *\r\r
- 0.625 HIGH 50%>\r\r
-\r\r
-Done...\r\r
-Checking Partitions ...\r\r
-\r\r
-Processing BMM file ...\r\r
-\r\r
-WARNING:NgdBuild:1212 - User specified non-default attribute value\r\r
- (8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM\r\r
- "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".\r\r
- This does not match the PERIOD constraint value (5 ns.). The uncertainty\r\r
- calculation will use the non-default attribute value. This could result in\r\r
- incorrect uncertainty calculated for DCM output clocks.\r\r
-Checking expanded design ...\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_\r\r
- ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].\r\r
- ALIGN_PIPE' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD\r\r
- RE_I' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR\r\r
- E_I' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
- "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad\r\r
- v_i" of type "PLL_ADV". This attribute will be ignored.\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[7].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[6].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[5].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[4].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
- _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
- _H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG0' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG1' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG2' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[1].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[2].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[3].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[4].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[5].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[6].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[7].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
- "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"\r\r
- of type "PLL_ADV". This attribute will be ignored.\r\r
-WARNING:NgdBuild:452 - logical net 'N194' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N195' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N196' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N197' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N198' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N199' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N200' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N201' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N202' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N203' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N204' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N205' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N206' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N207' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N208' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N209' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N210' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N211' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N212' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N213' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N214' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N215' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N216' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N217' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N218' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N219' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N220' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N221' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N222' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N223' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N224' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N225' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N226' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N227' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N228' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N229' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N230' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N231' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N232' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N233' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N234' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N235' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N236' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N237' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N238' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N239' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N240' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N241' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N242' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N243' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N244' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N245' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N246' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N247' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N248' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N249' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N250' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N251' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N252' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N253' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N254' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N255' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N256' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N257' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N266' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N267' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N268' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N269' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N270' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N271' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N272' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N273' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N306' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N307' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N308' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N309' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N310' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N311' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N312' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N313' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'\r\r
- has no driver\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGDBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 348\r\r
-\r\r
-Writing NGD file "system.ngd" ...\r\r
-Total REAL time to NGDBUILD completion: 2 min 3 sec\r\r
-Total CPU time to NGDBUILD completion: 1 min 21 sec\r\r
-\r\r
-Writing NGDBUILD log file "system.bld"...\r\r
-\r\r
-NGDBUILD done.\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program map\r\r
-# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing\r\r
-system.ngd system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - Map L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>\r\r
-Using target part "5vfx70tff1136-1".\r\r
-WARNING:LIT:243 - Logical network N194 has no load.\r\r
-WARNING:LIT:395 - The above warning message is repeated 1028 more times for the\r\r
- following (max. 5 shown):\r\r
- N195,\r\r
- N196,\r\r
- N197,\r\r
- N198,\r\r
- N199\r\r
- To see the details of these warning messages, please use the -detail switch.\r\r
-Mapping design into LUTs...\r\r
-WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin\r\r
- connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has\r\r
- been removed.\r\r
-WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top\r\r
- level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.\r\r
-WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been\r\r
- optimized out of the design.\r\r
-Writing file system_map.ngm...\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-Running directed packing...\r\r
-Running delay-based LUT packing...\r\r
-Updating timing models...\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
- TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during\r\r
- timing analysis.\r\r
-INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report\r\r
- (.mrp).\r\r
-Running timing-driven placement...\r\r
-Total REAL time at the beginning of Placer: 2 mins 41 secs \r\r
-Total CPU time at the beginning of Placer: 2 mins 8 secs \r\r
-\r\r
-Phase 1.1 Initial Placement Analysis\r\r
-Phase 1.1 Initial Placement Analysis (Checksum:9d0c7baf) REAL time: 3 mins 15 secs \r\r
-\r\r
-Phase 2.7 Design Feasibility Check\r\r
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
- Components associated with this bus are as follows: \r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS18\r\r
-\r\r
-\r\r
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
- Components associated with this bus are as follows: \r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33\r\r
-\r\r
-\r\r
-Phase 2.7 Design Feasibility Check (Checksum:9d0c7baf) REAL time: 3 mins 16 secs \r\r
-\r\r
-Phase 3.31 Local Placement Optimization\r\r
-Phase 3.31 Local Placement Optimization (Checksum:dec56134) REAL time: 3 mins 16 secs \r\r
-\r\r
-Phase 4.37 Local Placement Optimization\r\r
-Phase 4.37 Local Placement Optimization (Checksum:dec56134) REAL time: 3 mins 16 secs \r\r
-\r\r
-Phase 5.33 Local Placement Optimization\r\r
-Phase 5.33 Local Placement Optimization (Checksum:dec56134) REAL time: 13 mins \r\r
-\r\r
-Phase 6.32 Local Placement Optimization\r\r
-Phase 6.32 Local Placement Optimization (Checksum:dec56134) REAL time: 13 mins 5 secs \r\r
-\r\r
-Phase 7.2 Initial Clock and IO Placement\r\r
-\r\r
-\r\r
-\r\r
-There are 16 clock regions on the target FPGA device:\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y7: | CLOCKREGION_X1Y7: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 4 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y6: | CLOCKREGION_X1Y6: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 0 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use\r
- |\r\r
-| 4 edge BUFIOs available, 2 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 0 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 4 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y1>\r\r
- key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y2>\r\r
- key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-------------------------------------------------------------------------------------------------------------------------------------------------------\r
-----\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 8 | 0 | 0 | 60 | 60 | 1280 | 640 | 1920 | 0 | 0 | 1 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|-------\r
--|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y6>\r\r
- key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | \r
- 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:\r\r
-#\r\r
-# Number of Regional Clocking Regions in the device: 16 (4 clock spines in each)\r\r
-# Number of Regional Clock Networks used in this design: 8 (each network can be\r\r
-# composed of up to 3 clock spines and cover up to 3 regional clock regions)\r\r
-# \r\r
-######################################################################################\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y27" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y9" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y11" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y4" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =\r\r
-CLOCKREGION_X0Y1;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y25" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y7" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =\r\r
-CLOCKREGION_X0Y1;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y26" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y10" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-Phase 7.2 Initial Clock and IO Placement (Checksum:e5ad4bb9) REAL time: 13 mins 24 secs \r\r
-\r\r
-Phase 8.36 Local Placement Optimization\r\r
-Phase 8.36 Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 13 mins 24 secs \r\r
-\r\r
-.........................\r
-.\r\r
-.\r
-......\r
-.....\r
-.....\r
-.....\r
-.....\r
-......\r
-......\r
-.......\r
-......\r
-.......\r
-.......\r
-........\r
-.........\r
-........\r
-..\r\r
-Phase 9.30 Global Clock Region Assignment\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:\r\r
-#\r\r
-# Number of Global Clock Regions : 16\r\r
-# Number of Global Clock Networks: 15\r\r
-#\r\r
-# Clock Region Assignment: SUCCESSFUL\r\r
-\r\r
-# Location of Clock Components\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;\r\r
-INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;\r\r
-INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;\r\r
-INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;\r\r
-INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;\r\r
-INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;\r\r
-INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;\r\r
-INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;\r\r
-INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;\r\r
-INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;\r\r
-INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;\r\r
-INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;\r\r
-\r\r
-# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1\r\r
-NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;\r\r
-TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30\r\r
-NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2\r\r
-NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3\r\r
-NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
-TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
-AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;\r\r
-\r\r
-# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28\r\r
-NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8\r\r
-NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE = CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
-\r\r
-# clk_200_0000MHz driven by BUFGCTRL_X0Y4\r\r
-NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;\r\r
-TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;\r\r
-AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7\r\r
-NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
-TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE = CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31\r\r
-NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE = CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5\r\r
-NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6\r\r
-NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
-\r\r
-# NOTE: \r\r
-# This report is provided to help reproduce successful clock-region \r\r
-# assignments. The report provides range constraints for all global \r\r
-# clock networks, in a format that is directly usable in ucf files. \r\r
-#\r\r
-#END of Global Clock Net Distribution UCF Constraints\r\r
-######################################################################################\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:\r\r
-\r\r
-Number of Global Clock Regions : 16\r\r
-Number of Global Clock Networks: 15\r\r
-\r\r
-Clock Region Assignment: SUCCESSFUL\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y0> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 656 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 255 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 911 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y0> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 80 | 1263 |PCIe_Bridge/Bridge_Clk\r\r
- 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 24 | 52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 104 | 1315 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y1> \r\r
- key resource utilizations (used/available): global-clocks - 6/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 156 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 2 | 1 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 991 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 1 | 1 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 16 | 1155 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y1> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 240 | 1088 |PCIe_Bridge/Bridge_Clk\r\r
- 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 104 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 2 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 240 | 1203 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y2> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 5 | 0 | 0 | 0 | 9 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 1156 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 99 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 5 | 0 | 0 | 0 | 9 | 42 | 0 | 0 | 0 | 0 | 1 | 0 | 24 | 1267 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y2> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 28 | 382 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 90 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk\r\r
- 3 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 48 | 725 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 5 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 76 | 1199 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y3> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 86 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 12 | 281 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 210 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 12 | 580 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y3> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 43 |PCIe_Bridge/Bridge_Clk\r\r
- 4 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 99 | 1148 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 99 | 1191 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y4> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 36 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 4 | 0 | 0 | 0 | 1 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 37 | 263 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 219 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 6 | 0 | 0 | 0 | 7 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 37 | 518 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y4> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 83 | 834 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
- 0 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 37 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 83 | 892 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y5> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 48 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 74 | 579 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 227 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 4 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 97 | 858 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y5> \r\r
- key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 64 | 646 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 64 | 646 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y6> \r\r
- key resource utilizations (used/available): global-clocks - 7/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 65 | 555 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 100 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 2 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 67 | 666 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y6> \r\r
- key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 63 | 449 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 63 | 449 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y7> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 327 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 347 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y7> \r\r
- key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 34 | 208 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 34 | 208 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-NOTE:\r\r
-The above detailed report is the initial placement of the logic after the clock region assignment. The final placement\r\r
-may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks\r\r
-maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.\r\r
-\r\r
-\r\r
-# END of Global Clock Net Loads Distribution Report:\r\r
-######################################################################################\r\r
-\r\r
-\r\r
-Phase 9.30 Global Clock Region Assignment (Checksum:e5ad4bb9) REAL time: 14 mins 49 secs \r\r
-\r\r
-Phase 10.3 Local Placement Optimization\r\r
-Phase 10.3 Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 14 mins 49 secs \r\r
-\r\r
-Phase 11.5 Local Placement Optimization\r\r
-Phase 11.5 Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 14 mins 50 secs \r\r
-\r\r
-Phase 12.8 Global Placement\r\r
-....\r
-............................\r\r
-.....\r
-.......\r
-........\r
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-......\r
-........\r
-.......\r
-.........\r
-.........\r
-.........\r
-.........\r
-.........\r
-....\r\r
-.\r
-.......\r
-........\r
-.........\r
-..\r\r
-.....\r
-.......\r
-.......\r
-......\r
-.......\r
-.......\r
-.\r
-....\r
-......\r
-......\r
-.....\r
-.....\r
-.....\r
-....\r
-..\r
-......\r
-.....\r
-......\r
-..\r
-...\r
-......\r
-......\r
-........\r
-......\r
-......\r
-..\r\r
-.\r
-..\r
-....\r
-....\r
-.....\r
-......\r
-...\r
-......\r
-......\r
-.......\r\r
-....\r
-....\r
-...\r
-....\r
-.....\r
-....\r
-.\r
-..\r
-.....\r
-.....\r
-.....\r
-..\r\r
-.\r
-.....\r
-..\r
-.\r
-......\r
-......\r
-.\r
-...\r
-.....\r\r
-.\r
-.....\r
-.....\r
-.....\r
-......\r
-......\r
-......\r\r
-Phase 12.8 Global Placement (Checksum:651fc219) REAL time: 20 mins 14 secs \r\r
-\r\r
-Phase 13.29 Local Placement Optimization\r\r
-Phase 13.29 Local Placement Optimization (Checksum:651fc219) REAL time: 20 mins 14 secs \r\r
-\r\r
-Phase 14.5 Local Placement Optimization\r\r
-Phase 14.5 Local Placement Optimization (Checksum:651fc219) REAL time: 20 mins 19 secs \r\r
-\r\r
-Phase 15.18 Placement Optimization\r\r
-Phase 15.18 Placement Optimization (Checksum:11e1af7) REAL time: 23 mins 42 secs \r\r
-\r\r
-Phase 16.5 Local Placement Optimization\r\r
-Phase 16.5 Local Placement Optimization (Checksum:11e1af7) REAL time: 23 mins 46 secs \r\r
-\r\r
-Phase 17.34 Placement Validation\r\r
-Phase 17.34 Placement Validation (Checksum:11e1af7) REAL time: 23 mins 47 secs \r\r
-\r\r
-Total REAL time to Placer completion: 23 mins 51 secs \r\r
-Total CPU time to Placer completion: 21 mins \r\r
-Running post-placement packing...\r\r
-Writing output files...\r\r
-\r\r
-Design Summary:\r\r
-Number of errors: 0\r\r
-Number of warnings: 50\r\r
-Slice Logic Utilization:\r\r
- Number of Slice Registers: 13,531 out of 44,800 30%\r\r
- Number used as Flip Flops: 13,529\r\r
- Number used as Latches: 1\r\r
- Number used as Latch-thrus: 1\r\r
- Number of Slice LUTs: 14,602 out of 44,800 32%\r\r
- Number used as logic: 13,948 out of 44,800 31%\r\r
- Number using O6 output only: 12,711\r\r
- Number using O5 output only: 318\r\r
- Number using O5 and O6: 919\r\r
- Number used as Memory: 541 out of 13,120 4%\r\r
- Number used as Dual Port RAM: 164\r\r
- Number using O6 output only: 12\r\r
- Number using O5 output only: 32\r\r
- Number using O5 and O6: 120\r\r
- Number used as Single Port RAM: 4\r\r
- Number using O6 output only: 4\r\r
- Number used as Shift Register: 373\r\r
- Number using O6 output only: 373\r\r
- Number used as exclusive route-thru: 113\r\r
- Number of route-thrus: 497\r\r
- Number using O6 output only: 417\r\r
- Number using O5 output only: 70\r\r
- Number using O5 and O6: 10\r\r
-\r\r
-Slice Logic Distribution:\r\r
- Number of occupied Slices: 7,119 out of 11,200 63%\r\r
- Number of LUT Flip Flop pairs used: 19,423\r\r
- Number with an unused Flip Flop: 5,892 out of 19,423 30%\r\r
- Number with an unused LUT: 4,821 out of 19,423 24%\r\r
- Number of fully used LUT-FF pairs: 8,710 out of 19,423 44%\r\r
- Number of unique control sets: 1,396\r\r
- Number of slice register sites lost\r\r
- to control set restrictions: 3,277 out of 44,800 7%\r\r
-\r\r
- A LUT Flip Flop pair for this architecture represents one LUT paired with\r\r
- one Flip Flop within a slice. A control set is a unique combination of\r\r
- clock, reset, set, and enable signals for a registered element.\r\r
- The Slice Logic Distribution report is not meaningful if the design is\r\r
- over-mapped for a non-slice resource or if Placement fails.\r\r
- OVERMAPPING of BRAM resources should be ignored if the design is\r\r
- over-mapped for a non-BRAM resource or if placement fails.\r\r
-\r\r
-IO Utilization:\r\r
- Number of bonded IOBs: 255 out of 640 39%\r\r
- Number of LOCed IOBs: 255 out of 255 100%\r\r
- IOB Flip Flops: 494\r\r
- Number of bonded IPADs: 4 out of 50 8%\r\r
- Number of bonded OPADs: 2 out of 32 6%\r\r
-\r\r
-Specific Feature Utilization:\r\r
- Number of BlockRAM/FIFO: 22 out of 148 14%\r\r
- Number using BlockRAM only: 20\r\r
- Number using FIFO only: 2\r\r
- Total primitives used:\r\r
- Number of 36k BlockRAM used: 16\r\r
- Number of 18k BlockRAM used: 6\r\r
- Number of 36k FIFO used: 2\r\r
- Total Memory used (KB): 756 out of 5,328 14%\r\r
- Number of BUFG/BUFGCTRLs: 15 out of 32 46%\r\r
- Number used as BUFGs: 15\r\r
- Number of IDELAYCTRLs: 3 out of 22 13%\r\r
- Number of BUFDSs: 1 out of 8 12%\r\r
- Number of BUFIOs: 8 out of 80 10%\r\r
- Number of DCM_ADVs: 1 out of 12 8%\r\r
- Number of DSP48Es: 3 out of 128 2%\r\r
- Number of GTX_DUALs: 1 out of 8 12%\r\r
- Number of PCIEs: 1 out of 3 33%\r\r
- Number of LOCed PCIEs: 1 out of 1 100%\r\r
- Number of PLL_ADVs: 2 out of 6 33%\r\r
- Number of PPC440s: 1 out of 1 100%\r\r
-\r\r
- Number of RPM macros: 64\r\r
-Average Fanout of Non-Clock Nets: 3.81\r\r
-\r\r
-Peak Memory Usage: 789 MB\r\r
-Total REAL time to MAP completion: 24 mins 34 secs \r\r
-Total CPU time to MAP completion: 21 mins 42 secs \r\r
-\r\r
-Mapping completed.\r\r
-See MAP report file "system_map.mrp" for details.\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program par\r\r
-# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd\r\r
-system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - par L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>\r\r
-\r\r
-\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-\r\r
-Constraints file: system.pcf.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(78662)]\r\r
- overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(78661)].\r\r
-\r\r
-\r\r
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)\r\r
-Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)\r\r
-\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP \r\r
- "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.\r\r
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please\r\r
- consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.\r\r
-\r\r
-Device speed data version: "PRODUCTION 1.65 2009-06-01".\r\r
-\r\r
-\r\r
-\r\r
-Device Utilization Summary:\r\r
-\r\r
- Number of BUFDSs 1 out of 8 12%\r\r
- Number of BUFGs 15 out of 32 46%\r\r
- Number of BUFIOs 8 out of 80 10%\r\r
- Number of DCM_ADVs 1 out of 12 8%\r\r
- Number of DSP48Es 3 out of 128 2%\r\r
- Number of FIFO36_72_EXPs 2 out of 148 1%\r\r
- Number of LOCed FIFO36_72_EXPs 2 out of 2 100%\r\r
-\r\r
- Number of GTX_DUALs 1 out of 8 12%\r\r
- Number of IDELAYCTRLs 3 out of 22 13%\r\r
- Number of LOCed IDELAYCTRLs 3 out of 3 100%\r\r
-\r\r
- Number of ILOGICs 131 out of 800 16%\r\r
- Number of LOCed ILOGICs 8 out of 131 6%\r\r
-\r\r
- Number of External IOBs 255 out of 640 39%\r\r
- Number of LOCed IOBs 255 out of 255 100%\r\r
-\r\r
- Number of IODELAYs 80 out of 800 10%\r\r
- Number of LOCed IODELAYs 8 out of 80 10%\r\r
-\r\r
- Number of External IPADs 4 out of 690 1%\r\r
- Number of LOCed IPADs 4 out of 4 100%\r\r
-\r\r
- Number of JTAGPPCs 1 out of 1 100%\r\r
- Number of OLOGICs 236 out of 800 29%\r\r
- Number of External OPADs 2 out of 32 6%\r\r
- Number of LOCed OPADs 2 out of 2 100%\r\r
-\r\r
- Number of PCIEs 1 out of 3 33%\r\r
- Number of LOCed PCIEs 1 out of 1 100%\r\r
-\r\r
- Number of PLL_ADVs 2 out of 6 33%\r\r
- Number of PPC440s 1 out of 1 100%\r\r
- Number of RAMB18X2SDPs 4 out of 148 2%\r\r
- Number of RAMB36SDP_EXPs 6 out of 148 4%\r\r
- Number of LOCed RAMB36SDP_EXPs 1 out of 6 16%\r\r
-\r\r
- Number of RAMB36_EXPs 10 out of 148 6%\r\r
- Number of LOCed RAMB36_EXPs 6 out of 10 60%\r\r
-\r\r
- Number of Slice Registers 13531 out of 44800 30%\r\r
- Number used as Flip Flops 13529\r\r
- Number used as Latches 1\r\r
- Number used as LatchThrus 1\r\r
-\r\r
- Number of Slice LUTS 14602 out of 44800 32%\r\r
- Number of Slice LUT-Flip Flop pairs 19423 out of 44800 43%\r\r
-\r\r
-\r\r
-Overall effort level (-ol): High \r\r
-Router effort level (-rl): High \r\r
-\r\r
-Starting initial Timing Analysis. REAL time: 1 mins 3 secs \r\r
-Finished initial Timing Analysis. REAL time: 1 mins 5 secs \r\r
-\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-Starting Router\r\r
-\r\r
-INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note\r\r
- that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,\r\r
- verify that the same connectivity is available in the target device for this implementation. \r\r
-\r\r
-Phase 1 : 95521 unrouted; REAL time: 1 mins 22 secs \r\r
-\r\r
-Phase 2 : 84728 unrouted; REAL time: 1 mins 35 secs \r\r
-\r\r
-Phase 3 : 34551 unrouted; REAL time: 3 mins 59 secs \r\r
-\r\r
-Phase 4 : 34616 unrouted; (Setup:0, Hold:93713, Component Switching Limit:0) REAL time: 4 mins 32 secs \r\r
-\r\r
-Updating file: system.ncd with current fully routed design.\r\r
-\r\r
-Phase 5 : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0) REAL time: 5 mins 40 secs \r\r
-\r\r
-Phase 6 : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0) REAL time: 5 mins 40 secs \r\r
-\r\r
-Phase 7 : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0) REAL time: 5 mins 40 secs \r\r
-\r\r
-Phase 8 : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0) REAL time: 5 mins 40 secs \r\r
-\r\r
-Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 40 secs \r\r
-\r\r
-Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 55 secs \r\r
-Total REAL time to Router completion: 6 mins 55 secs \r\r
-Total CPU time to Router completion: 6 mins 44 secs \r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-Generating "PAR" statistics.\r\r
-\r\r
-**************************\r\r
-Generating Clock Report\r\r
-**************************\r\r
-\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_125_0000MHzPLL0_ | | | | | |\r\r
-| ADJUST | BUFGCTRL_X0Y2| No | 3788 | 0.520 | 2.062 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/Bridge_C | | | | | |\r\r
-| lk |BUFGCTRL_X0Y28| No | 1452 | 0.412 | 2.085 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_62_5000MHzPLL0_A | | | | | |\r\r
-| DJUST | BUFGCTRL_X0Y6| No | 504 | 0.299 | 2.065 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/core_c | | | | | |\r\r
-| lk |BUFGCTRL_X0Y27| No | 93 | 0.266 | 2.085 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_SysACE_Compac | | | | | |\r\r
-|tFlash_SysACE_CLK_pi | | | | | |\r\r
-| n_BUFGP | BUFGCTRL_X0Y8| No | 55 | 0.163 | 1.770 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_Ethernet_MAC_ | | | | | |\r\r
-|PHY_rx_clk_pin_BUFGP | | | | | |\r\r
-| |BUFGCTRL_X0Y30| No | 12 | 0.038 | 1.879 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_125_0000MHz90PLL | | | | | |\r\r
-| 0_ADJUST | BUFGCTRL_X0Y5| No | 167 | 0.285 | 2.028 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/pcie_b | | | | | |\r\r
-| lk/gt_usrclk |BUFGCTRL_X0Y29| No | 6 | 0.058 | 1.886 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| clk_200_0000MHz | BUFGCTRL_X0Y4| No | 4 | 0.100 | 1.879 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<0> | IO Clk| No | 18 | 0.095 | 0.419 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<1> | IO Clk| No | 18 | 0.083 | 0.380 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_Ethernet_MAC_ | | | | | |\r\r
-|PHY_tx_clk_pin_BUFGP | | | | | |\r\r
-| |BUFGCTRL_X0Y31| No | 6 | 0.004 | 1.941 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | |\r
- | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<2> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<3> | IO Clk| No | 18 | 0.107 | 0.404 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<5> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<4> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<6> | IO Clk| No | 18 | 0.096 | 0.393 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<7> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No | 2 | 0.000 | 1.739 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/pcie_b | | | | | |\r\r
-|lk/SIO/.pcie_gt_wrap | | | | | |\r\r
-| per_i/icdrreset<0> | Local| | 1 | 0.000 | 0.585 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|Ethernet_MAC/Etherne | | | | | |\r\r
-| t_MAC/phy_tx_clk_i | Local| | 9 | 2.887 | 3.720 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|RS232_Uart_1_Interru | | | | | |\r\r
-| pt | Local| | 1 | 0.000 | 0.743 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|ppc440_0_jtagppc_bus | | | | | |\r\r
-| _JTGC405TCK | Local| | 1 | 0.000 | 1.526 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-\r\r
-* Net Skew is the difference between the minimum and maximum routing\r\r
-only delays for the net. Note this is different from Clock Skew which\r\r
-is reported in TRCE timing report. Clock Skew is the difference between\r\r
-the minimum and maximum path delays which includes logic delays.\r\r
-\r\r
-Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)\r\r
-\r\r
-Number of Timing Constraints that were not applied: 5\r\r
-\r\r
-Asterisk (*) preceding a constraint indicates it was not met.\r\r
- This may be due to a setup or hold violation.\r\r
-\r\r
-----------------------------------------------------------------------------------------------------------\r\r
- Constraint | Check | Worst Case | Best Case | Timing | Timing \r\r
- | | Slack | Achievable | Errors | Score \r\r
-----------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP | 0.067ns| 7.933ns| 0| 0\r\r
- s HIGH 50% | HOLD | 0.035ns| | 0| 0\r\r
- | MINPERIOD | 0.000ns| 8.000ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP | 0.051ns| 3.949ns| 0| 0\r\r
- lus/comp_endpoint/core_clk" PERIOD = | HOLD | 0.349ns| | 0| 0\r\r
- 4 ns HIGH 50% | MINPERIOD | 0.000ns| 4.000ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 0.028ns| 7.972ns| 0| 0\r\r
- L0_CLK_OUT_2_ = PERIOD TIMEGRP "c | HOLD | 0.021ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_2_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP | 0.030ns| 1.870ns| 0| 0\r\r
- CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS" | HOLD | 1.027ns| | 0| 0\r\r
- 1.9 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[0].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[1].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[5].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[2].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[3].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[4].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[6].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[7].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<0>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<1>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<2>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<3>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<4>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<5>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<6>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<7>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP | 0.187ns| 7.813ns| 0| 0\r\r
- ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns | HOLD | 0.502ns| | 0| 0\r\r
- DATAPATHONLY | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP | 0.510ns| 7.490ns| 0| 0\r\r
- _Clk" TO TIMEGRP "Bridge_Clk" 8 ns | HOLD | 0.456ns| | 0| 0\r\r
- DATAPATHONLY | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns | MINPERIOD | 1.010ns| 3.990ns| 0| 0\r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY | 1.695ns| 4.305ns| 0| 0\r\r
- RP "PADS" TO TIMEGRP "RXCLK_GRP_E | HOLD | 1.060ns| | 0| 0\r\r
- thernet_MAC" 6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 2.151ns| 4.917ns| 0| 0\r\r
- L0_CLK_OUT_0_ = PERIOD TIMEGRP "c | HOLD | 0.404ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_0_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- PHASE 2 ns HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 6.000ns| 4.000ns| 0| 0\r\r
- pin" 100 MHz HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.664ns| 1.336ns| 0| 0\r\r
- L0_CLK_OUT_3_ = PERIOD TIMEGRP "c | HOLD | 0.465ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_3_" TS_sys_clk_pin * 2 HIG | | | | | \r\r
- H 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.842ns| 8.316ns| 0| 0\r\r
- L0_CLK_OUT_4_ = PERIOD TIMEGRP "c | HOLD | 0.116ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_4_" TS_sys_clk_pin * 0.625 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW | 4.455ns| 0.545ns| 0| 0\r\r
- UFGP" MAXSKEW = 5 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW | 4.833ns| 0.167ns| 0| 0\r\r
- UFGP" MAXSKEW = 5 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | MINPERIOD | 4.900ns| 3.100ns| 0| 0\r\r
- L0_CLK_OUT_1_ = PERIOD TIMEGRP "c | | | | | \r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_1_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY | 7.423ns| 2.577ns| 0| 0\r\r
- GRP "TXCLK_GRP_Ethernet_MAC" TO T | | | | | \r\r
- IMEGRP "PADS" 10 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP | 9.363ns| 13.248ns| 0| 0\r\r
- UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.458ns| | 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP | 13.905ns| 6.095ns| 0| 0\r\r
- TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.812ns| | 0| 0\r\r
- TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP | 14.527ns| 5.473ns| 0| 0\r\r
- M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.262ns| | 0| 0\r\r
- TIMEGRP "TNM_CLK90" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 17.706ns| 2.294ns| 0| 0\r\r
- NM_GATE_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.056ns| | 0| 0\r\r
- TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP | 18.115ns| 1.885ns| 0| 0\r\r
- P "TNM_CAL_RDEN_DLY" TO TIMEGRP " | HOLD | 0.231ns| | 0| 0\r\r
- TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 18.117ns| 1.883ns| 0| 0\r\r
- NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.020ns| | 0| 0\r\r
- TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP | 26.887ns| 3.113ns| 0| 0\r\r
- K_pin_BUFGP/IBUFG" PERIOD = 30 ns | HOLD | 0.468ns| | 0| 0\r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP | 32.341ns| 7.659ns| 0| 0\r\r
- UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.314ns| | 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- Pin to Pin Skew Constraint | MAXDELAY | 2106523.523ns| 2106523.837ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A | N/A| N/A| N/A| N/A\r\r
- P "TNM_RDEN_SEL_MUX" TO TIMEGRP " | | | | | \r\r
- TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A | N/A| N/A| N/A| N/A\r\r
- s HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
-\r\r
-\r\r
-Derived Constraint Report\r\r
-Derived Constraints for TS_MC_CLK\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-| | Period | Actual Period | Timing Errors | Paths Analyzed |\r\r
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-|TS_MC_CLK | 5.000ns| 3.990ns| 1.524ns| 0| 0| 0| 345|\r\r
-| TS_MC_PHY_INIT_DATA_SEL_0 | 20.000ns| 6.095ns| N/A| 0| 0| 21| 0|\r\r
-| TS_MC_PHY_INIT_DATA_SEL_90 | 20.000ns| 5.473ns| N/A| 0| 0| 274| 0|\r\r
-| TS_MC_GATE_DLY | 20.000ns| 2.294ns| N/A| 0| 0| 40| 0|\r\r
-| TS_MC_RDEN_DLY | 20.000ns| 1.883ns| N/A| 0| 0| 5| 0|\r\r
-| TS_MC_CAL_RDEN_DLY | 20.000ns| 1.885ns| N/A| 0| 0| 5| 0|\r\r
-| TS_MC_RDEN_SEL_MUX | 20.000ns| N/A| N/A| 0| 0| 0| 0|\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-\r\r
-Derived Constraints for TS_sys_clk_pin\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-| | Period | Actual Period | Timing Errors | Paths Analyzed |\r\r
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-|TS_sys_clk_pin | 10.000ns| 4.000ns| 9.965ns| 0| 0| 0| 1090426|\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 4.917ns| N/A| 0| 0| 626| 0|\r\r
-| erator_0_PLL0_CLK_OUT_0_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 3.100ns| N/A| 0| 0| 0| 0|\r\r
-| erator_0_PLL0_CLK_OUT_1_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 7.972ns| N/A| 0| 0| 1078756| 0|\r\r
-| erator_0_PLL0_CLK_OUT_2_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 5.000ns| 1.336ns| N/A| 0| 0| 2| 0|\r\r
-| erator_0_PLL0_CLK_OUT_3_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 16.000ns| 8.316ns| N/A| 0| 0| 11042| 0|\r\r
-| erator_0_PLL0_CLK_OUT_4_ | | | | | | | |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-\r\r
-All constraints were met.\r\r
-INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the \r\r
- constraint does not cover any paths or that it has no requested value.\r\r
-\r\r
-\r\r
-Generating Pad Report.\r\r
-\r\r
-All signals are completely routed.\r\r
-\r\r
-WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.\r\r
-\r\r
-Loading device for application Rf_Device from file '5vlx50t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
-INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128\r\r
-INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints\r\r
- found: 128, number successful: 128\r\r
-Total REAL time to PAR completion: 7 mins 33 secs \r\r
-Total CPU time to PAR completion: 7 mins 9 secs \r\r
-\r\r
-Peak Memory Usage: 705 MB\r\r
-\r\r
-Placer: Placement generated during map.\r\r
-Routing: Completed - No errors found.\r\r
-Timing: Completed - No errors found.\r\r
-\r\r
-Number of error messages: 0\r\r
-Number of warning messages: 9\r\r
-Number of info messages: 4\r\r
-\r\r
-Writing design to file system.ncd\r\r
-\r\r
-\r\r
-\r\r
-PAR done!\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program post_par_trce\r\r
-# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - Trace (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =\r\r
- 8 ns HIGH 50%;> [system.pcf(78662)] overrides constraint <NET\r\r
- "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(78661)].\r\r
-\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
- TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;\r\r
- ignored during timing analysis.\r\r
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more\r\r
- information, see the TSI report. Please consult the Xilinx Command Line\r\r
- Tools User Guide for information on generating a TSI report.\r\r
---------------------------------------------------------------------------------\r\r
-Release 11.2 Trace (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf\r\r
-\r\r
-\r\r
-Design file: system.ncd\r\r
-Physical constraint file: system.pcf\r\r
-Device,speed: xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING\r\r
-level 0)\r\r
-Report level: error report\r\r
---------------------------------------------------------------------------------\r\r
-\r\r
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths\r\r
- option. All paths that are not constrained will be reported in the\r\r
- unconstrained paths section(s) of the report.\r\r
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a\r\r
- 50 Ohm transmission line loading model. For the details of this model, and\r\r
- for more information on accounting for different loading conditions, please\r\r
- see the device datasheet.\r\r
-\r\r
-\r\r
-Timing summary:\r\r
----------------\r\r
-\r\r
-Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)\r\r
-\r\r
-Constraints cover 1280410 paths, 18 nets, and 87141 connections\r\r
-\r\r
-Design statistics:\r\r
- Minimum period: 13.248ns (Maximum frequency: 75.483MHz)\r\r
- Maximum path delay from/to any node: 7.813ns\r\r
- Maximum net delay: 0.805ns\r\r
- Maximum net skew: 0.545ns\r\r
-\r\r
-\r\r
-Analysis completed Fri Jul 03 22:25:44 2009\r\r
---------------------------------------------------------------------------------\r\r
-\r\r
-Generating Report ...\r\r
-\r\r
-Number of warnings: 2\r\r
-Number of info messages: 3\r\r
-Total time: 1 mins 34 secs \r\r
-\r\r
-\r\r
-xflow done!\r\r
-touch __xps/system_routed\r
-xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par\r
-Analyzing implementation/system.par\r\r
-*********************************************\r
-Running Bitgen..\r
-*********************************************\r
-cd implementation; bitgen -w -f bitgen.ut system; cd ..\r
-Release 11.2 - Bitgen L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-Opened constraints file system.pcf.\r\r
-\r\r
-Fri Jul 03 22:26:27 2009\r\r
-\r\r
-Running DRC.\r\r
-WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.\r\r
- Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX\r\r
- Transceiver User Guide to ensure that the design SelectIO usage meets the\r\r
- guidelines to minimize the impact on GTX performance. \r\r
-WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w\r\r
- rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good\r\r
- design practice. Use the CE pin to control the loading of data into the\r\r
- flip-flop.\r\r
-WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
- Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.\r\r
- This is not good design practice. Use the CE pin to control the loading of\r\r
- data into the flip-flop.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does\r\r
- not drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>\r\r
- is incomplete. The signal does not drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-DRC detected 0 errors and 24 warnings. Please see the previously displayed\r\r
-individual error or warning messages for more details.\r\r
-Creating bit map...\r\r
-Saving bit stream in "system.bit".\r\r
-Bitstream generation is complete.\r\r
-\r
-\r
-Done!
-\r
-At Local date and time: Sat Jul 04 08:21:51 2009
- make -f system.make download started...
-\r
-cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf\r
-*********************************************\r
-Initializing BRAM contents of the bitstream\r
-*********************************************\r
-bitinit -p xc5vfx70tff1136-1 system.mhs -pe ppc440_0 bootloops/ppc440_0.elf \\r
--bt implementation/system.bit -o implementation/download.bit\r
-\r\r
-bitinit version Xilinx EDK 11.2 Build EDK_LS3.47\r\r
-Copyright (c) Xilinx Inc. 2002.\r\r
-\r\r
-Parsing MHS File system.mhs...\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Overriding IP level properties ...\r\r
-\r\r
-Performing IP level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
-Address Map for Processor ppc440_0\r\r
- (0b0000000000-0b0011111111) ppc440_0 \r\r
- (0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC\r\r
- (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0\r\r
- (0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0\r\r
- (0x81420000-0x8142ffff) LEDs_Positions plb_v46_0\r\r
- (0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0\r\r
- (0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0\r\r
- (0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0\r\r
- (0x81800000-0x8180ffff) xps_intc_0 plb_v46_0\r\r
- (0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0\r\r
- (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0\r\r
- (0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0\r\r
- (0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0\r\r
- (0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0\r\r
- (0xf8000000-0xf80fffff) SRAM plb_v46_0\r\r
- (0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
- C_SPLB0_P2P value to 0\r\r
-\r\r
-Computing clock values...\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 12\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
- PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
- PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
- value to 0x2000\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PORT_DWIDTH value to 64\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
- value to 8\r\r
-INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
- _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
- ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
- C_MPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
- C_MPLB_SMALLEST_SLAVE value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
- 2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-\r\r
-Checking platform address map ...\r\r
-\r\r
-Initializing Memory...\r\r
-Running Data2Mem with the following command:\r\r
-data2mem -bm "implementation/system_bd" -bt "implementation/system.bit" -bd\r\r
-"bootloops/ppc440_0.elf" tag ppc440_0 -o b implementation/download.bit \r\r
-Memory Initialization completed successfully.\r\r
-\r\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
-write (count, cmdBuffer, dataBuffer) failed C0000004.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2301.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-Downloading c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex.\r\r
-Downloaded firmware version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-Elapsed time = 2 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 30.69 C, Min. Reading: 27.24 C, Max.\r\r
-Reading: 30.69 C\r\r
-5: VCCINT Supply: Current Reading: 0.999 V, Min. Reading: 0.999 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.505 V, Min. Reading: 2.505 V, Max.\r\r
-Reading: 2.508 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 10 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Sat Jul 04 08:22:29 2009
- make -f system.make program started...
-\r
-*********************************************\r
-Creating software libraries...\r
-*********************************************\r
-libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss\r
-libgen\r\r
-Xilinx EDK 11.2 Build EDK_LS3.47\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
-__xps/ise/xmsgprops.lst system.mss \r\r
-\r\r
-Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Checking platform configuration ...\r\r
-IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 109 - 1 master(s) : 12 slave(s)\r\r
-IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 290 - 1 master(s) : 1 slave(s)\r\r
-IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
-line 394 - 1 master(s) : 1 slave(s)\r\r
-\r\r
-Checking port drivers...\r\r
-WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- hs line 462 - floating connection!\r\r
-\r\r
-Performing Clock DRCs...\r\r
-\r\r
-Performing Reset DRCs...\r\r
-\r\r
-Overriding system level properties...\r\r
-\r\r
-Running system level update procedures...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
-\r\r
-Running system level DRCs...\r\r
-\r\r
-Performing System level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
-WARNING:EDK:411 - pcie -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- ss line 77 - deprecated driver!\r\r
-WARNING:EDK:411 - emaclite -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
- ss line 83 - deprecated driver!\r\r
-INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
- - DDR2_SDRAM\r\r
- - DIP_Switches_8Bit\r\r
- - Ethernet_MAC\r\r
- - IIC_EEPROM\r\r
- - LEDs_8Bit\r\r
- - LEDs_Positions\r\r
- - PCIe_Bridge\r\r
- - Push_Buttons_5Bit\r\r
- - RS232_Uart_1\r\r
- - SRAM\r\r
- - SysACE_CompactFlash\r\r
- - ppc440_0_apu_fpu_virtex5\r\r
- - xps_bram_if_cntlr_1\r\r
- - xps_intc_0\r\r
-\r\r
--- Generating libraries for processor: ppc440_0 --\r\r
-\r\r
-\r\r
-Staging source files.\r\r
-Running DRCs.\r\r
-Running generate.\r\r
-Running post_generate.\r\r
-Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
-"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=sp_full -mcpu=440 -O2 -c"\r\r
-"EXTRA_COMPILER_FLAGS=-g"'.\r\r
-\r\r
-Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
-"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=sp_full -mcpu=440 -O2 -c"\r\r
-"EXTRA_COMPILER_FLAGS=-g"'.\r\r
-Compiling common\r
-powerpc-eabi-ar: creating ../../../lib/libxil.a
-\r
-Compiling lldma\r
-Compiling standalone\r
-Compiling gpio\r
-Compiling emaclite\r
-Compiling iic\r
-Compiling pci\r
-Compiling uartlite\r
-Compiling sysace\r
-Compiling intc\r
-Compiling cpu_ppc440\r
-Running execs_generate.\r\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mfpu=sp_full -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 50674 372 86528 137574 21966 RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/; exit;"
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Sun Jul 05 09:36:10 2009
- make -f system.make hwclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-rm -rf implementation synthesis xst hdl\r
-rm -rf xst.srp system.srp\r
-rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Sun Jul 05 09:36:23 2009
- make -f system.make swclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
+++ /dev/null
- The following files will be modified:
- system.mhs
- system.mss
-
---------------------------------------
- The following changes will be made:
- Core ppc440mc_ddr2 2.00.a will be replaced by 2.00.b
- Core clock_generator 3.00.a will be replaced by 3.01.a
-
- Driver cpu_ppc440 1.00.b will be replaced by 1.01.a
- Driver iic 1.14.a will be replaced by 1.15.a
---------------------------------------
- The following changes need to be made manually by the user:
- Core plbv46_pcie 3.00.b needs to be replaced by 4.01.a
- Core xps_ethernetlite 2.01.a needs to be replaced by 3.00.a
+++ /dev/null
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r
- 251 - deprecated core for architecture 'virtex5fx'!
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r
- 296 - deprecated core for architecture 'virtex5fx'!
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r
- 251 - deprecated core for architecture 'virtex5fx'!
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r
- 296 - deprecated core for architecture 'virtex5fx'!
-
-Checking platform configuration ...
-IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r
-107 - 1 master(s) : 12 slave(s)
-IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r
-288 - 1 master(s) : 1 slave(s)
-
-Checking port drivers...
-WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r
- 446 - floating connection!
-
-Performing Clock DRCs...
-
-Performing Reset DRCs...
-
-Overriding system level properties...
-
-Running system level update procedures...
-
-Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
-
-Running system level DRCs...
-
-Performing System level DRCs on properties...
-
-Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
+++ /dev/null
-No logfile was found.\r
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 251 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 296 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Mon Jun 29 21:01:23 2009
- make -f system.make program started...
-\r
-*********************************************\r
-Creating software libraries...\r
-*********************************************\r
-libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss\r
-libgen\r\r
-Xilinx EDK 11.2 Build EDK_LS3.47\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
-__xps/ise/xmsgprops.lst system.mss \r\r
-\r\r
-Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
- m.mhs line 251 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
- m.mhs line 296 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
- m.mhs line 251 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
- m.mhs line 296 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Checking platform configuration ...\r\r
-IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
-C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m\r\r
-hs line 107 - 1 master(s) : 12 slave(s)\r\r
-IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
-C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m\r\r
-hs line 288 - 1 master(s) : 1 slave(s)\r\r
-\r\r
-Checking port drivers...\r\r
-WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
- m.mhs line 446 - floating connection!\r\r
-\r\r
-Performing Clock DRCs...\r\r
-\r\r
-Performing Reset DRCs...\r\r
-\r\r
-Overriding system level properties...\r\r
-\r\r
-Running system level update procedures...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
-\r\r
-Running system level DRCs...\r\r
-\r\r
-Performing System level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
-WARNING:EDK:494 -\r\r
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\synth\r\r
- esis\ not found.\r\r
-WARNING:EDK:2530 - Timing and Resource utilization information not added\r\r
-WARNING:EDK:411 - pcie -\r\r
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
- m.mss line 77 - deprecated driver!\r\r
-WARNING:EDK:411 - emaclite -\r\r
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
- m.mss line 83 - deprecated driver!\r\r
-INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
- - DDR2_SDRAM\r\r
- - DIP_Switches_8Bit\r\r
- - Ethernet_MAC\r\r
- - IIC_EEPROM\r\r
- - LEDs_8Bit\r\r
- - LEDs_Positions\r\r
- - PCIe_Bridge\r\r
- - Push_Buttons_5Bit\r\r
- - RS232_Uart_1\r\r
- - SRAM\r\r
- - SysACE_CompactFlash\r\r
- - xps_bram_if_cntlr_1\r\r
- - xps_intc_0\r\r
-\r\r
--- Generating libraries for processor: ppc440_0 --\r\r
-\r\r
-\r\r
-Staging source files.\r\r
-Running DRCs.\r\r
-Running generate.\r\r
-Running post_generate.\r\r
-Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
-"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"\r\r
-"EXTRA_COMPILER_FLAGS=-g"'.\r\r
-\r\r
-Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
-"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"\r\r
-"EXTRA_COMPILER_FLAGS=-g"'.\r\r
-Compiling common\r
-powerpc-eabi-ar: creating ../../../lib/libxil.a
-\r
-Compiling lldma\r
-Compiling standalone\r
-Compiling gpio\r
-Compiling emaclite\r
-Compiling iic\r
-Compiling pci\r
-Compiling uartlite\r
-Compiling sysace\r
-Compiling intc\r
-Compiling cpu_ppc440\r
-Running execs_generate.\r\r
-powerpc-eabi-gcc -O0 /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mcpu=440 -Wl,-T -Wl,/cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 53754 372 86524 140650 2256a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Tue Jun 30 18:32:58 2009
- make -f system.make hwclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-rm -rf implementation synthesis xst hdl\r
-rm -rf xst.srp system.srp\r
-rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:33:07 2009
- make -f system.make netlistclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:33:13 2009
- make -f system.make bitsclean started...
-\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:33:24 2009
- make -f system.make libsclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:33:31 2009
- make -f system.make programclean started...
-\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-At Local date and time: Tue Jun 30 18:33:37 2009
- make -f system.make swclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Tue Jun 30 20:53:14 2009
- make -f system.make program started...
-\r
-*********************************************\r
-Creating software libraries...\r
-*********************************************\r
-libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss\r
-libgen\r\r
-Xilinx EDK 11.2 Build EDK_LS3.47\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
-__xps/ise/xmsgprops.lst system.mss \r\r
-\r\r
-Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 251 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 296 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 251 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 296 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Checking platform configuration ...\r\r
-IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-107 - 1 master(s) : 12 slave(s)\r\r
-IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-288 - 1 master(s) : 1 slave(s)\r\r
-\r\r
-Checking port drivers...\r\r
-WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 446 - floating connection!\r\r
-\r\r
-Performing Clock DRCs...\r\r
-\r\r
-Performing Reset DRCs...\r\r
-\r\r
-Overriding system level properties...\r\r
-\r\r
-Running system level update procedures...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
-\r\r
-Running system level DRCs...\r\r
-\r\r
-Performing System level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
-WARNING:EDK:494 -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\synthesis\ not\r\r
- found.\r\r
-WARNING:EDK:2530 - Timing and Resource utilization information not added\r\r
-WARNING:EDK:411 - pcie -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line\r\r
- 77 - deprecated driver!\r\r
-WARNING:EDK:411 - emaclite -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line\r\r
- 83 - deprecated driver!\r\r
-INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
- - DDR2_SDRAM\r\r
- - DIP_Switches_8Bit\r\r
- - Ethernet_MAC\r\r
- - IIC_EEPROM\r\r
- - LEDs_8Bit\r\r
- - LEDs_Positions\r\r
- - PCIe_Bridge\r\r
- - Push_Buttons_5Bit\r\r
- - RS232_Uart_1\r\r
- - SRAM\r\r
- - SysACE_CompactFlash\r\r
- - xps_bram_if_cntlr_1\r\r
- - xps_intc_0\r\r
-\r\r
--- Generating libraries for processor: ppc440_0 --\r\r
-\r\r
-\r\r
-Staging source files.\r\r
-Running DRCs.\r\r
-Running generate.\r\r
-Running post_generate.\r\r
-Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
-"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"\r\r
-"EXTRA_COMPILER_FLAGS=-g"'.\r\r
-\r\r
-Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
-"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"\r\r
-"EXTRA_COMPILER_FLAGS=-g"'.\r\r
-Compiling common\r
-powerpc-eabi-ar: creating ../../../lib/libxil.a
-\r
-Compiling lldma\r
-Compiling standalone\r
-Compiling gpio\r
-Compiling emaclite\r
-Compiling iic\r
-Compiling pci\r
-Compiling uartlite\r
-Compiling sysace\r
-Compiling intc\r
-Compiling cpu_ppc440\r
-Running execs_generate.\r\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 53754 372 86524 140650 2256a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Tue Jun 30 21:05:40 2009
- make -f system.make bits started...
-\r
-****************************************************\r
-Creating system netlist for hardware specification..\r
-****************************************************\r
-platgen -p xc5vfx70tff1136-1 -lang vhdl -msg __xps/ise/xmsgprops.lst system.mhs\r
-\r\r
-Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47\r\r
- (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-\r\r
-Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg\r\r
-__xps/ise/xmsgprops.lst system.mhs \r\r
-\r\r
-Parse C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs\r\r
-...\r\r
-\r\r
-Read MPD definitions ...\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 251 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 296 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 251 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 296 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Overriding IP level properties ...\r\r
-\r\r
-Performing IP level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
-Address Map for Processor ppc440_0\r\r
- (0b0000000000-0b0011111111) ppc440_0 \r\r
- (0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC\r\r
- (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0\r\r
- (0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0\r\r
- (0x81420000-0x8142ffff) LEDs_Positions plb_v46_0\r\r
- (0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0\r\r
- (0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0\r\r
- (0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0\r\r
- (0x81800000-0x8180ffff) xps_intc_0 plb_v46_0\r\r
- (0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0\r\r
- (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0\r\r
- (0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0\r\r
- (0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0\r\r
- (0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0\r\r
- (0xf8000000-0xf80fffff) SRAM plb_v46_0\r\r
- (0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
- C_SPLB0_P2P value to 0\r\r
-\r\r
-Computing clock values...\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 12\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
- PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
- PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
- value to 0x2000\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PORT_DWIDTH value to 64\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
- value to 8\r\r
-INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
- _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
- ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
- C_MPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
- C_MPLB_SMALLEST_SLAVE value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
- 2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-\r\r
-Checking platform address map ...\r\r
-\r\r
-Checking platform configuration ...\r\r
-INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 296 - This design requires design constraints to guarantee performance.\r\r
- Please refer to the xps_ethernetlite_v2_00_a data sheet for details. \r\r
- The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs\r\r
- Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet\r\r
- operation.\r\r
-IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-107 - 1 master(s) : 12 slave(s)\r\r
-IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-288 - 1 master(s) : 1 slave(s)\r\r
-\r\r
-Checking port drivers...\r\r
-WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 446 - floating connection!\r\r
-\r\r
-Performing Clock DRCs...\r\r
-\r\r
-Performing Reset DRCs...\r\r
-\r\r
-Overriding system level properties...\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER\r\r
- C_PPC440MC_ADDR_BASE value to 0x00000000\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER\r\r
- C_PPC440MC_ADDR_HIGH value to 0x0fffffff\r\r
-INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0\r\r
- 1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER\r\r
- C_NUM_PPC_USED value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR\r\r
- value to 0b00000000000000000000000000000001\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE\r\r
- value to 0b00000000000000000000000000000001\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL\r\r
- value to 0b00000000000000000000000000000000\r\r
-\r\r
-Running system level update procedures...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
-\r\r
-Running system level DRCs...\r\r
-\r\r
-Performing System level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
-\r\r
-Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...\r\r
-INFO: The PCIe_Bridge core has constraints automatically generated by XPS in\r\r
-implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-INFO: The Ethernet_MAC core has constraints automatically generated by XPS in\r\r
-implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in\r\r
-implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.\r\r\r
-It can be overridden by constraints placed in the system.ucf file.\r\r\r
-\r\r
-\r\r\r
-\r\r
-\r\r
-Modify defaults ...\r\r
-\r\r
-Creating stub ...\r\r
-\r\r
-Processing licensed instances ...\r\r
-Completion time: 0.00 seconds\r\r
-\r\r
-Creating hardware output directories ...\r\r
-\r\r
-Managing hardware (BBD-specified) netlist files ...\r\r
-IPNAME:plbv46_pcie INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-251 - Copying (BBD-specified) netlist files.\r\r
-IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-296 - Copying (BBD-specified) netlist files.\r\r
-\r\r
-Managing cache ...\r\r
-\r\r
-Elaborating instances ...\r\r
-IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-129 - elaborating IP\r\r
-\r\r
-Writing HDL for elaborated instances ...\r\r
-\r\r
-Inserting wrapper level ...\r\r
-Completion time: 1.00 seconds\r\r
-\r\r
-Constructing platform-level connectivity ...\r\r
-Completion time: 1.00 seconds\r\r
-\r\r
-Writing (top-level) BMM ...\r\r
-\r\r
-Writing (top-level and wrappers) HDL ...\r\r
-\r\r
-Generating synthesis project file ...\r\r
-\r\r
-Running XST synthesis ...\r\r
-\r\r
-INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option\r\r
- IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST\r\r
- synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. \r\r
-INSTANCE:ppc440_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78\r\r
-- Running XST synthesis\r\r
-INSTANCE:plb_v46_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-107 - Running XST synthesis\r\r
-INSTANCE:xps_bram_if_cntlr_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-116 - Running XST synthesis\r\r
-INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-129 - Running XST synthesis\r\r
-INSTANCE:rs232_uart_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-136 - Running XST synthesis\r\r
-INSTANCE:leds_8bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-152 - Running XST synthesis\r\r
-INSTANCE:leds_positions -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-166 - Running XST synthesis\r\r
-INSTANCE:push_buttons_5bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-180 - Running XST synthesis\r\r
-INSTANCE:dip_switches_8bit -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-194 - Running XST synthesis\r\r
-INSTANCE:iic_eeprom -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-208 - Running XST synthesis\r\r
-INSTANCE:sram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-221 - Running XST synthesis\r\r
-INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-251 - Running XST synthesis\r\r
-INSTANCE:ppc440_0_splb0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-288 - Running XST synthesis\r\r
-INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-296 - Running XST synthesis\r\r
-INSTANCE:ddr2_sdram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-315 - Running XST synthesis\r\r
-INSTANCE:sysace_compactflash -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-375 - Running XST synthesis\r\r
-INSTANCE:clock_generator_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-392 - Running XST synthesis\r\r
-INSTANCE:jtagppc_cntlr_inst -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-431 - Running XST synthesis\r\r
-INSTANCE:proc_sys_reset_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-437 - Running XST synthesis\r\r
-INSTANCE:xps_intc_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-449 - Running XST synthesis\r\r
-\r\r
-Running NGCBUILD ...\r\r
-IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78\r\r
-- Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..\r\r
-ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pp\r\r
-c440_0_wrapper/ppc440_0_wrapper.ngc" ...\r\r
-\r\r
-Applying constraints in "ppc440_0_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ppc440_0_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 7 sec\r\r
-Total CPU time to NGCBUILD completion: 6 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-136 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc\r\r
-../rs232_uart_1_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/rs\r\r
-232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../rs232_uart_1_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 8 sec\r\r
-Total CPU time to NGCBUILD completion: 2 sec\r\r
-\r\r
-Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-251 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..\r\r
-pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pc\r\r
-ie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...\r\r
-Executing edif2ngd -noa\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
-ie_bridge_wrapper_fifo_generator_v4_3.edn"\r\r
-"pcie_bridge_wrapper_fifo_generator_v4_3.ngo"\r\r
-Release 11.2 - edif2ngd L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
-INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
-with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
-Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
-ie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
-Loading design module\r\r
-"../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
-ie_bridge_wrapper/dpram_70_512.ngc"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
-ie_bridge_wrapper/fifo_71x512.ngc"...\r\r
-\r\r
-Applying constraints in "pcie_bridge_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../pcie_bridge_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 13 sec\r\r
-Total CPU time to NGCBUILD completion: 9 sec\r\r
-\r\r
-Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-296 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..\r\r
-ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/et\r\r
-hernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...\r\r
-Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"\r\r
-"ethernetlite_v1_01_b_dmem_v2.ngo"\r\r
-Release 11.2 - edif2ngd L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
-INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
-with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
-Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
-Loading design module\r\r
-"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\et\r\r
-hernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
-\r\r
-Applying constraints in "ethernet_mac_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ethernet_mac_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 9 sec\r\r
-Total CPU time to NGCBUILD completion: 6 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-315 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..\r\r
-ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/dd\r\r
-r2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...\r\r
-\r\r
-Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../ddr2_sdram_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 7 sec\r\r
-Total CPU time to NGCBUILD completion: 7 sec\r\r
-\r\r
-Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -\r\r
-C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
-449 - Running NGCBUILD\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
-xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc\r\r
-../xps_intc_0_wrapper.ngc\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xp\r\r
-s_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../xps_intc_0_wrapper.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 1 sec\r\r
-Total CPU time to NGCBUILD completion: 1 sec\r\r
-\r\r
-Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-\r\r
-Rebuilding cache ...\r\r
-\r\r
-Total run time: 1039.00 seconds\r\r
-Running synthesis...\r
-bash -c "cd synthesis; ./synthesis.sh"\r
-xst -ifn system_xst.scr -intstyle silent\r
-Running XST synthesis ...\r
-XST completed\r
-Release 11.2 - ngcbuild L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Overriding Xilinx file <ngcflow.csf> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>\r\r
-\r\r
-Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe\r\r
-./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise\r\r
-../__xps/ise/system.ise\r\r
-\r\r
-Reading NGO file\r\r
-"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/synthesis/system.\r\r
-ngc" ...\r\r
-Loading design module "../implementation/ppc440_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/plb_v46_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...\r\r
-Loading design module\r\r
-"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...\r\r
-Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...\r\r
-Loading design module "../implementation/leds_8bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/leds_positions_wrapper.ngc"...\r\r
-Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...\r\r
-Loading design module "../implementation/iic_eeprom_wrapper.ngc"...\r\r
-Loading design module "../implementation/sram_wrapper.ngc"...\r\r
-Loading design module "../implementation/pcie_bridge_wrapper.ngc"...\r\r
-Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...\r\r
-Loading design module "../implementation/ethernet_mac_wrapper.ngc"...\r\r
-Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...\r\r
-Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...\r\r
-Loading design module "../implementation/clock_generator_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...\r\r
-Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...\r\r
-Loading design module "../implementation/xps_intc_0_wrapper.ngc"...\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGCBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 0\r\r
-\r\r
-Writing NGC file "../implementation/system.ngc" ...\r\r
-Total REAL time to NGCBUILD completion: 10 sec\r\r
-Total CPU time to NGCBUILD completion: 9 sec\r\r
-\r\r
-Writing NGCBUILD log file "../implementation/system.blc"...\r\r
-\r\r
-NGCBUILD done.\r\r
-*********************************************\r
-Running Xilinx Implementation tools..\r
-*********************************************\r
-xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc\r
-Release 11.2 - Xflow L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise\r\r
-../__xps/ise/system.ise system.ngc \r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into\r\r
-working directory\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation \r\r
-\r\r
-Using Flow File:\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/fpg\r\r
-a.flw \r\r
-Using Option File(s): \r\r
- C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xf\r\r
-low.opt \r\r
-\r\r
-Creating Script File ... \r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program ngdbuild\r\r
-# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm\r\r
-system.bmm\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy\r\r
-stem.ngc" -uc system.ucf system.ngd \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - ngdbuild L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-\r\r
-Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt\r\r
-timestamp -bm system.bmm\r\r
-C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sys\r\r
-tem.ngc -uc system.ucf system.ngd\r\r
-\r\r
-Reading NGO file\r\r
-"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy\r\r
-stem.ngc" ...\r\r
-Gathering constraint information from source properties...\r\r
-Done.\r\r
-\r\r
-Applying constraints in "system.ucf" to the design...\r\r
-WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance\r\r
- 'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_\r\r
- ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to\r\r
- 'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive. \r\r
- In order for functional simulation to be correct, the value of SIM_DEVICE\r\r
- should be changed in this same manner in the source netlist or constraint\r\r
- file.\r\r
-Resolving constraint associations...\r\r
-Checking Constraint Associations...\r\r
-WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM\r\r
- "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"\r\r
- * 4;> [system.ucf(264)]: This constraint will be ignored because the relative\r\r
- clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not\r\r
- found.\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *\r\r
- 1.25 PHASE 2 ns HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *\r\r
- 1.25 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *\r\r
- 1.25 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *\r\r
- 2 HIGH 50%>\r\r
-\r\r
-INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
- 'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
- clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
- The following new TNM groups and period specifications were generated at the\r\r
- PLL_ADV output(s): \r\r
- CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =\r\r
- PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *\r\r
- 0.625 HIGH 50%>\r\r
-\r\r
-Done...\r\r
-Checking Partitions ...\r\r
-\r\r
-Processing BMM file ...\r\r
-\r\r
-WARNING:NgdBuild:1212 - User specified non-default attribute value\r\r
- (8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM\r\r
- "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".\r\r
- This does not match the PERIOD constraint value (5 ns.). The uncertainty\r\r
- calculation will use the non-default attribute value. This could result in\r\r
- incorrect uncertainty calculated for DCM output clocks.\r\r
-Checking expanded design ...\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_\r\r
- ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].\r\r
- ALIGN_PIPE' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD\r\r
- RE_I' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR\r\r
- E_I' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
- ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG\r\r
- ' has unconnected output pin\r\r
-WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
- "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad\r\r
- v_i" of type "PLL_ADV". This attribute will be ignored.\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[7].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[6].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[5].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
- _4to7[4].I_FDRSE_BE4to7' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
- URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B\r\r
- E0to3' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
- _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
- _H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
- E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG0' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG1' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
- SIZE2_REG2' has unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has\r\r
- unconnected output pin\r\r
-WARNING:NgdBuild:443 - SFF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected\r\r
- output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'\r\r
- has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[1].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[2].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[3].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[4].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[5].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[6].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:440 - FF primitive\r\r
- 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
- /gen_rden[7].u_calib_rden_r' has unconnected output pin\r\r
-WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
- "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"\r\r
- of type "PLL_ADV". This attribute will be ignored.\r\r
-WARNING:NgdBuild:452 - logical net 'N194' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N195' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N196' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N197' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N198' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N199' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N200' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N201' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N202' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N203' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N204' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N205' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N206' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N207' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N208' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N209' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N210' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N211' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N212' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N213' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N214' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N215' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N216' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N217' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N218' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N219' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N220' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N221' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N222' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N223' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N224' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N225' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N226' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N227' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N228' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N229' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N230' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N231' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N232' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N233' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N234' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N235' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N236' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N237' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N238' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N239' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N240' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N241' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N242' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N243' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N244' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N245' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N246' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N247' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N248' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N249' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N250' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N251' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N252' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N253' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N254' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N255' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N256' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N257' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N266' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N267' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N268' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N269' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N270' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N271' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N272' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N273' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N306' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N307' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N308' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N309' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N310' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N311' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N312' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'N313' has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'\r\r
- has no driver\r\r
-WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'\r\r
- has no driver\r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-NGDBUILD Design Results Summary:\r\r
- Number of errors: 0\r\r
- Number of warnings: 348\r\r
-\r\r
-Writing NGD file "system.ngd" ...\r\r
-Total REAL time to NGDBUILD completion: 1 min 58 sec\r\r
-Total CPU time to NGDBUILD completion: 1 min 28 sec\r\r
-\r\r
-Writing NGDBUILD log file "system.bld"...\r\r
-\r\r
-NGDBUILD done.\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program map\r\r
-# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing\r\r
-system.ngd system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - Map L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>\r\r
-Using target part "5vfx70tff1136-1".\r\r
-WARNING:LIT:243 - Logical network N194 has no load.\r\r
-WARNING:LIT:395 - The above warning message is repeated 1200 more times for the\r\r
- following (max. 5 shown):\r\r
- N195,\r\r
- N196,\r\r
- N197,\r\r
- N198,\r\r
- N199\r\r
- To see the details of these warning messages, please use the -detail switch.\r\r
-Mapping design into LUTs...\r\r
-WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin\r\r
- connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has\r\r
- been removed.\r\r
-WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top\r\r
- level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.\r\r
-WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been\r\r
- optimized out of the design.\r\r
-Writing file system_map.ngm...\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
- of frag REGCLKAU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
- of frag REGCLKAL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
- er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
- x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
- /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
- noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
- em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
- ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
- P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
- nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP\r\r
- of frag RDRCLKU connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP_RDRCLKU_tiesig\r\r
-WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP\r\r
- of frag RDRCLKL connected to power/ground net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
- /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
- 36.noeccerr.SDP_RDRCLKL_tiesig\r\r
-Running directed packing...\r\r
-Running delay-based LUT packing...\r\r
-Updating timing models...\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
- TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during\r\r
- timing analysis.\r\r
-INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report\r\r
- (.mrp).\r\r
-Running timing-driven placement...\r\r
-Total REAL time at the beginning of Placer: 1 mins 55 secs \r\r
-Total CPU time at the beginning of Placer: 1 mins 43 secs \r\r
-\r\r
-Phase 1.1 Initial Placement Analysis\r\r
-Phase 1.1 Initial Placement Analysis (Checksum:150b88e2) REAL time: 2 mins 13 secs \r\r
-\r\r
-Phase 2.7 Design Feasibility Check\r\r
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
- Components associated with this bus are as follows: \r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS18\r\r
- Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS18\r\r
-\r\r
-\r\r
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
- Components associated with this bus are as follows: \r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVDCI_33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33\r\r
- Comp: fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33\r\r
-\r\r
-\r\r
-Phase 2.7 Design Feasibility Check (Checksum:150b88e2) REAL time: 2 mins 14 secs \r\r
-\r\r
-Phase 3.31 Local Placement Optimization\r\r
-Phase 3.31 Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs \r\r
-\r\r
-Phase 4.37 Local Placement Optimization\r\r
-Phase 4.37 Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs \r\r
-\r\r
-Phase 5.33 Local Placement Optimization\r\r
-Phase 5.33 Local Placement Optimization (Checksum:f23945c2) REAL time: 8 mins 58 secs \r\r
-\r\r
-Phase 6.32 Local Placement Optimization\r\r
-Phase 6.32 Local Placement Optimization (Checksum:f23945c2) REAL time: 9 mins 1 secs \r\r
-\r\r
-Phase 7.2 Initial Clock and IO Placement\r\r
-\r\r
-\r\r
-\r\r
-There are 16 clock regions on the target FPGA device:\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y7: | CLOCKREGION_X1Y7: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 4 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y6: | CLOCKREGION_X1Y6: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 0 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 2 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use\r
- |\r\r
-| 4 edge BUFIOs available, 2 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 0 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: |\r\r
-| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |\r\r
-| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |\r\r
-| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |\r\r
-| 4 center BUFIOs available, 0 in use | |\r\r
-| | |\r\r
-|------------------------------------------|------------------------------------------|\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y1>\r\r
- key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y2>\r\r
- key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 8 | 0 | 0 | 60 | 60 | 1280 | 640 | 1920 | 0 | 0 | 1 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|-------\r
--|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y6>\r\r
- key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
-|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
-| | clock | BRAM | | | | | | | | | | | |\r\r
-| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Upper Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| | Lower Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| clock | region | -----------------------------------------------\r\r
-| type | expansion | | <IO/Regional clock Net Name>\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | \r
- 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"\r\r
-|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
-\r\r
-\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:\r\r
-#\r\r
-# Number of Regional Clocking Regions in the device: 16 (4 clock spines in each)\r\r
-# Number of Regional Clock Networks used in this design: 8 (each network can be\r\r
-# composed of up to 3 clock spines and cover up to 3 regional clock regions)\r\r
-# \r\r
-######################################################################################\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y27" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y9" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y11" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y4" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =\r\r
-CLOCKREGION_X0Y1;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y25" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y7" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =\r\r
-CLOCKREGION_X0Y1;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y26" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =\r\r
-CLOCKREGION_X0Y6;\r\r
-\r\r
-\r\r
-# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"\r\r
-INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =\r\r
-"BUFIO_X0Y10" ;\r\r
-NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =\r\r
-"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
-TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =\r\r
-"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
-AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =\r\r
-CLOCKREGION_X0Y2;\r\r
-\r\r
-\r\r
-Phase 7.2 Initial Clock and IO Placement (Checksum:7e049af9) REAL time: 9 mins 19 secs \r\r
-\r\r
-Phase 8.36 Local Placement Optimization\r\r
-Phase 8.36 Local Placement Optimization (Checksum:7e049af9) REAL time: 9 mins 19 secs \r\r
-\r\r
-....................\r
-.................\r\r
-.....\r
-......\r
-.....\r
-......\r
-.....\r
-.....\r
-......\r
-......\r
-.......\r
-......\r
-.......\r
-.......\r
-.......\r
-..\r\r
-Phase 9.30 Global Clock Region Assignment\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:\r\r
-#\r\r
-# Number of Global Clock Regions : 16\r\r
-# Number of Global Clock Networks: 15\r\r
-#\r\r
-# Clock Region Assignment: SUCCESSFUL\r\r
-\r\r
-# Location of Clock Components\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;\r\r
-INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;\r\r
-INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;\r\r
-INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;\r\r
-INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;\r\r
-INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;\r\r
-INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;\r\r
-INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;\r\r
-INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;\r\r
-INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;\r\r
-INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;\r\r
-INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;\r\r
-INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;\r\r
-INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;\r\r
-INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;\r\r
-\r\r
-# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1\r\r
-NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;\r\r
-TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30\r\r
-NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE = CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2\r\r
-NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3\r\r
-NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
-TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
-AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;\r\r
-\r\r
-# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28\r\r
-NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8\r\r
-NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE = CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
-\r\r
-# clk_200_0000MHz driven by BUFGCTRL_X0Y4\r\r
-NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;\r\r
-TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;\r\r
-AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7\r\r
-NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
-TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE = CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31\r\r
-NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
-TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
-AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
-\r\r
-# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5\r\r
-NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6\r\r
-NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;\r\r
-TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;\r\r
-AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
-\r\r
-# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0\r\r
-NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
-TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
-AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
-\r\r
-# NOTE: \r\r
-# This report is provided to help reproduce successful clock-region \r\r
-# assignments. The report provides range constraints for all global \r\r
-# clock networks, in a format that is directly usable in ucf files. \r\r
-#\r\r
-#END of Global Clock Net Distribution UCF Constraints\r\r
-######################################################################################\r\r
-\r\r
-\r\r
-######################################################################################\r\r
-GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:\r\r
-\r\r
-Number of Global Clock Regions : 16\r\r
-Number of Global Clock Networks: 15\r\r
-\r\r
-Clock Region Assignment: SUCCESSFUL\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y0> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 548 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 202 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 750 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y0> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 38 | 934 |PCIe_Bridge/Bridge_Clk\r\r
- 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 24 | 52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 62 | 986 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y1> \r\r
- key resource utilizations (used/available): global-clocks - 6/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 195 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 1 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 719 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 1 | 1 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 17 | 918 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y1> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 500 |PCIe_Bridge/Bridge_Clk\r\r
- 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 364 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 884 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y2> \r\r
- key resource utilizations (used/available): global-clocks - 5/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 5 | 0 | 0 | 0 | 9 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 58 | 913 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 142 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 7 | 0 | 0 | 0 | 9 | 42 | 0 | 0 | 0 | 0 | 1 | 0 | 58 | 1072 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y2> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 94 | 387 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 81 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk\r\r
- 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 500 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 130 | 970 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y3> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 83 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 36 | 272 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 154 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 36 | 512 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y3> \r\r
- key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 290 |PCIe_Bridge/Bridge_Clk\r\r
- 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 659 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 66 | 950 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y4> \r\r
- key resource utilizations (used/available): global-clocks - 5/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |PCIe_Bridge/Bridge_Clk\r\r
- 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 34 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 4 | 0 | 0 | 0 | 1 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 231 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 200 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 6 | 0 | 0 | 0 | 7 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 466 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y4> \r\r
- key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 54 | 367 |PCIe_Bridge/Bridge_Clk\r\r
- 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 602 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 3 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 74 | 985 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y5> \r\r
- key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 2 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 48 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 517 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 206 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 28 | 773 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y5> \r\r
- key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 68 | 285 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 50 | 333 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 118 | 639 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y6> \r\r
- key resource utilizations (used/available): global-clocks - 7/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg\r\r
- 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin\r\r
- 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |clk_125_0000MHz90PLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 605 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 158 |clk_62_5000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 12 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 2 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 27 | 777 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y6> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 103 |PCIe_Bridge/Bridge_Clk\r\r
- 0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 413 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 516 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X0Y7> \r\r
- key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 495 |clk_125_0000MHzPLL0_ADJUST\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 |clk_62_5000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 514 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-\r\r
-Clock-Region: <CLOCKREGION_X1Y7> \r\r
- key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)\r\r
- FIFO | | | | | | | | | | | | | |\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- | | | | | | | | | | | | | | <Global clock Net Name>\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 327 |clk_125_0000MHzPLL0_ADJUST\r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
- 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 327 | Total \r\r
---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
-\r\r
-NOTE:\r\r
-The above detailed report is the initial placement of the logic after the clock region assignment. The final placement\r\r
-may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks\r\r
-maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.\r\r
-\r\r
-\r\r
-# END of Global Clock Net Loads Distribution Report:\r\r
-######################################################################################\r\r
-\r\r
-\r\r
-Phase 9.30 Global Clock Region Assignment (Checksum:7e049af9) REAL time: 10 mins 42 secs \r\r
-\r\r
-Phase 10.3 Local Placement Optimization\r\r
-Phase 10.3 Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 43 secs \r\r
-\r\r
-Phase 11.5 Local Placement Optimization\r\r
-Phase 11.5 Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 45 secs \r\r
-\r\r
-Phase 12.8 Global Placement\r\r
-.............................\r
-....\r\r
-.\r
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-Phase 12.8 Global Placement (Checksum:4ba01660) REAL time: 15 mins 18 secs \r\r
-\r\r
-Phase 13.29 Local Placement Optimization\r\r
-Phase 13.29 Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 18 secs \r\r
-\r\r
-Phase 14.5 Local Placement Optimization\r\r
-Phase 14.5 Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 22 secs \r\r
-\r\r
-Phase 15.18 Placement Optimization\r\r
-Phase 15.18 Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 1 secs \r\r
-\r\r
-Phase 16.5 Local Placement Optimization\r\r
-Phase 16.5 Local Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 3 secs \r\r
-\r\r
-Phase 17.34 Placement Validation\r\r
-Phase 17.34 Placement Validation (Checksum:f81b02a1) REAL time: 18 mins 5 secs \r\r
-\r\r
-Total REAL time to Placer completion: 18 mins 7 secs \r\r
-Total CPU time to Placer completion: 17 mins 4 secs \r\r
-Running post-placement packing...\r\r
-Writing output files...\r\r
-\r\r
-Design Summary:\r\r
-Number of errors: 0\r\r
-Number of warnings: 50\r\r
-Slice Logic Utilization:\r\r
- Number of Slice Registers: 12,128 out of 44,800 27%\r\r
- Number used as Flip Flops: 12,127\r\r
- Number used as Latches: 1\r\r
- Number of Slice LUTs: 12,266 out of 44,800 27%\r\r
- Number used as logic: 11,767 out of 44,800 26%\r\r
- Number using O6 output only: 10,791\r\r
- Number using O5 output only: 282\r\r
- Number using O5 and O6: 694\r\r
- Number used as Memory: 392 out of 13,120 2%\r\r
- Number used as Dual Port RAM: 56\r\r
- Number using O6 output only: 12\r\r
- Number using O5 and O6: 44\r\r
- Number used as Single Port RAM: 4\r\r
- Number using O6 output only: 4\r\r
- Number used as Shift Register: 332\r\r
- Number using O6 output only: 332\r\r
- Number used as exclusive route-thru: 107\r\r
- Number of route-thrus: 438\r\r
- Number using O6 output only: 382\r\r
- Number using O5 output only: 51\r\r
- Number using O5 and O6: 5\r\r
-\r\r
-Slice Logic Distribution:\r\r
- Number of occupied Slices: 6,488 out of 11,200 57%\r\r
- Number of LUT Flip Flop pairs used: 17,046\r\r
- Number with an unused Flip Flop: 4,918 out of 17,046 28%\r\r
- Number with an unused LUT: 4,780 out of 17,046 28%\r\r
- Number of fully used LUT-FF pairs: 7,348 out of 17,046 43%\r\r
- Number of unique control sets: 1,288\r\r
- Number of slice register sites lost\r\r
- to control set restrictions: 3,000 out of 44,800 6%\r\r
-\r\r
- A LUT Flip Flop pair for this architecture represents one LUT paired with\r\r
- one Flip Flop within a slice. A control set is a unique combination of\r\r
- clock, reset, set, and enable signals for a registered element.\r\r
- The Slice Logic Distribution report is not meaningful if the design is\r\r
- over-mapped for a non-slice resource or if Placement fails.\r\r
- OVERMAPPING of BRAM resources should be ignored if the design is\r\r
- over-mapped for a non-BRAM resource or if placement fails.\r\r
-\r\r
-IO Utilization:\r\r
- Number of bonded IOBs: 255 out of 640 39%\r\r
- Number of LOCed IOBs: 255 out of 255 100%\r\r
- IOB Flip Flops: 494\r\r
- Number of bonded IPADs: 4 out of 50 8%\r\r
- Number of bonded OPADs: 2 out of 32 6%\r\r
-\r\r
-Specific Feature Utilization:\r\r
- Number of BlockRAM/FIFO: 23 out of 148 15%\r\r
- Number using BlockRAM only: 21\r\r
- Number using FIFO only: 2\r\r
- Total primitives used:\r\r
- Number of 36k BlockRAM used: 16\r\r
- Number of 18k BlockRAM used: 6\r\r
- Number of 36k FIFO used: 2\r\r
- Total Memory used (KB): 756 out of 5,328 14%\r\r
- Number of BUFG/BUFGCTRLs: 15 out of 32 46%\r\r
- Number used as BUFGs: 15\r\r
- Number of IDELAYCTRLs: 3 out of 22 13%\r\r
- Number of BUFDSs: 1 out of 8 12%\r\r
- Number of BUFIOs: 8 out of 80 10%\r\r
- Number of DCM_ADVs: 1 out of 12 8%\r\r
- Number of GTX_DUALs: 1 out of 8 12%\r\r
- Number of PCIEs: 1 out of 3 33%\r\r
- Number of LOCed PCIEs: 1 out of 1 100%\r\r
- Number of PLL_ADVs: 2 out of 6 33%\r\r
- Number of PPC440s: 1 out of 1 100%\r\r
-\r\r
- Number of RPM macros: 64\r\r
-Average Fanout of Non-Clock Nets: 3.76\r\r
-\r\r
-Peak Memory Usage: 701 MB\r\r
-Total REAL time to MAP completion: 18 mins 45 secs \r\r
-Total CPU time to MAP completion: 17 mins 40 secs \r\r
-\r\r
-Mapping completed.\r\r
-See MAP report file "system_map.mrp" for details.\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program par\r\r
-# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd\r\r
-system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - par L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>\r\r
-\r\r
-\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-\r\r
-Constraints file: system.pcf.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)]\r\r
- overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].\r\r
-\r\r
-\r\r
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)\r\r
-Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)\r\r
-\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP \r\r
- "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.\r\r
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please\r\r
- consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.\r\r
-\r\r
-Device speed data version: "PRODUCTION 1.65 2009-06-01".\r\r
-\r\r
-\r\r
-\r\r
-Device Utilization Summary:\r\r
-\r\r
- Number of BUFDSs 1 out of 8 12%\r\r
- Number of BUFGs 15 out of 32 46%\r\r
- Number of BUFIOs 8 out of 80 10%\r\r
- Number of DCM_ADVs 1 out of 12 8%\r\r
- Number of FIFO36_72_EXPs 2 out of 148 1%\r\r
- Number of LOCed FIFO36_72_EXPs 2 out of 2 100%\r\r
-\r\r
- Number of GTX_DUALs 1 out of 8 12%\r\r
- Number of IDELAYCTRLs 3 out of 22 13%\r\r
- Number of LOCed IDELAYCTRLs 3 out of 3 100%\r\r
-\r\r
- Number of ILOGICs 131 out of 800 16%\r\r
- Number of LOCed ILOGICs 8 out of 131 6%\r\r
-\r\r
- Number of External IOBs 255 out of 640 39%\r\r
- Number of LOCed IOBs 255 out of 255 100%\r\r
-\r\r
- Number of IODELAYs 80 out of 800 10%\r\r
- Number of LOCed IODELAYs 8 out of 80 10%\r\r
-\r\r
- Number of External IPADs 4 out of 690 1%\r\r
- Number of LOCed IPADs 4 out of 4 100%\r\r
-\r\r
- Number of JTAGPPCs 1 out of 1 100%\r\r
- Number of OLOGICs 236 out of 800 29%\r\r
- Number of External OPADs 2 out of 32 6%\r\r
- Number of LOCed OPADs 2 out of 2 100%\r\r
-\r\r
- Number of PCIEs 1 out of 3 33%\r\r
- Number of LOCed PCIEs 1 out of 1 100%\r\r
-\r\r
- Number of PLL_ADVs 2 out of 6 33%\r\r
- Number of PPC440s 1 out of 1 100%\r\r
- Number of RAMB18X2SDPs 5 out of 148 3%\r\r
- Number of RAMB36SDP_EXPs 6 out of 148 4%\r\r
- Number of LOCed RAMB36SDP_EXPs 1 out of 6 16%\r\r
-\r\r
- Number of RAMB36_EXPs 10 out of 148 6%\r\r
- Number of LOCed RAMB36_EXPs 6 out of 10 60%\r\r
-\r\r
- Number of Slice Registers 12128 out of 44800 27%\r\r
- Number used as Flip Flops 12127\r\r
- Number used as Latches 1\r\r
- Number used as LatchThrus 0\r\r
-\r\r
- Number of Slice LUTS 12266 out of 44800 27%\r\r
- Number of Slice LUT-Flip Flop pairs 17046 out of 44800 38%\r\r
-\r\r
-\r\r
-Overall effort level (-ol): High \r\r
-Router effort level (-rl): High \r\r
-\r\r
-Starting initial Timing Analysis. REAL time: 51 secs \r\r
-Finished initial Timing Analysis. REAL time: 52 secs \r\r
-\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load. PAR will not attempt to route this\r\r
- signal.\r\r
-Starting Router\r\r
-\r\r
-INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note\r\r
- that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,\r\r
- verify that the same connectivity is available in the target device for this implementation. \r\r
-\r\r
-Phase 1 : 82160 unrouted; REAL time: 1 mins 9 secs \r\r
-\r\r
-Phase 2 : 72970 unrouted; REAL time: 1 mins 22 secs \r\r
-\r\r
-Phase 3 : 28783 unrouted; REAL time: 3 mins 31 secs \r\r
-\r\r
-Phase 4 : 28815 unrouted; (Setup:0, Hold:103206, Component Switching Limit:0) REAL time: 3 mins 57 secs \r\r
-\r\r
-Updating file: system.ncd with current fully routed design.\r\r
-\r\r
-Phase 5 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs \r\r
-\r\r
-Phase 6 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs \r\r
-\r\r
-Phase 7 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs \r\r
-\r\r
-Phase 8 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs \r\r
-\r\r
-Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 25 secs \r\r
-\r\r
-Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 57 secs \r\r
-Total REAL time to Router completion: 7 mins 57 secs \r\r
-Total CPU time to Router completion: 7 mins 31 secs \r\r
-\r\r
-Partition Implementation Status\r\r
--------------------------------\r\r
-\r\r
- No Partitions were found in this design.\r\r
-\r\r
--------------------------------\r\r
-\r\r
-Generating "PAR" statistics.\r\r
-\r\r
-**************************\r\r
-Generating Clock Report\r\r
-**************************\r\r
-\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_125_0000MHzPLL0_ | | | | | |\r\r
-| ADJUST | BUFGCTRL_X0Y2| No | 3176 | 0.533 | 2.076 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/Bridge_C | | | | | |\r\r
-| lk |BUFGCTRL_X0Y28| No | 1481 | 0.519 | 2.085 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_62_5000MHzPLL0_A | | | | | |\r\r
-| DJUST | BUFGCTRL_X0Y6| No | 501 | 0.313 | 2.062 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|clk_125_0000MHz90PLL | | | | | |\r\r
-| 0_ADJUST | BUFGCTRL_X0Y5| No | 165 | 0.262 | 2.028 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/core_c | | | | | |\r\r
-| lk |BUFGCTRL_X0Y27| No | 92 | 0.338 | 2.085 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_SysACE_Compac | | | | | |\r\r
-|tFlash_SysACE_CLK_pi | | | | | |\r\r
-| n_BUFGP | BUFGCTRL_X0Y8| No | 55 | 0.171 | 1.797 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/pcie_b | | | | | |\r\r
-| lk/gt_usrclk |BUFGCTRL_X0Y29| No | 6 | 0.065 | 1.886 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_Ethernet_MAC_ | | | | | |\r\r
-|PHY_rx_clk_pin_BUFGP | | | | | |\r\r
-| |BUFGCTRL_X0Y30| No | 12 | 0.086 | 1.874 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|fpga_0_Ethernet_MAC_ | | | | | |\r\r
-|PHY_tx_clk_pin_BUFGP | | | | | |\r\r
-| |BUFGCTRL_X0Y31| No | 6 | 0.004 | 1.941 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<0> | IO Clk| No | 18 | 0.095 | 0.419 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<1> | IO Clk| No | 18 | 0.083 | 0.380 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | |\r
- | | |\r\r
-| y_io/delayed_dqs<2> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<3> | IO Clk| No | 18 | 0.107 | 0.404 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<5> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<4> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<6> | IO Clk| No | 18 | 0.096 | 0.393 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|DDR2_SDRAM/DDR2_SDRA | | | | | |\r\r
-|M/u_ddr2_top/u_mem_i | | | | | |\r\r
-|f_top/u_phy_top/u_ph | | | | | |\r\r
-| y_io/delayed_dqs<7> | IO Clk| No | 18 | 0.101 | 0.425 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No | 2 | 0.000 | 1.739 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-| clk_200_0000MHz | BUFGCTRL_X0Y4| No | 4 | 0.100 | 1.879 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|RS232_Uart_1_Interru | | | | | |\r\r
-| pt | Local| | 1 | 0.000 | 0.625 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|PCIe_Bridge/PCIe_Bri | | | | | |\r\r
-|dge/comp_block_plus/ | | | | | |\r\r
-|comp_endpoint/pcie_b | | | | | |\r\r
-|lk/SIO/.pcie_gt_wrap | | | | | |\r\r
-| per_i/icdrreset<0> | Local| | 1 | 0.000 | 0.590 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|Ethernet_MAC/Etherne | | | | | |\r\r
-| t_MAC/phy_tx_clk_i | Local| | 9 | 3.273 | 3.994 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-|ppc440_0_jtagppc_bus | | | | | |\r\r
-| _JTGC405TCK | Local| | 1 | 0.000 | 1.699 |\r\r
-+---------------------+--------------+------+------+------------+-------------+\r\r
-\r\r
-* Net Skew is the difference between the minimum and maximum routing\r\r
-only delays for the net. Note this is different from Clock Skew which\r\r
-is reported in TRCE timing report. Clock Skew is the difference between\r\r
-the minimum and maximum path delays which includes logic delays.\r\r
-\r\r
-Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)\r\r
-\r\r
-Number of Timing Constraints that were not applied: 5\r\r
-\r\r
-Asterisk (*) preceding a constraint indicates it was not met.\r\r
- This may be due to a setup or hold violation.\r\r
-\r\r
-----------------------------------------------------------------------------------------------------------\r\r
- Constraint | Check | Worst Case | Best Case | Timing | Timing \r\r
- | | Slack | Achievable | Errors | Score \r\r
-----------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP | 0.026ns| 7.974ns| 0| 0\r\r
- s HIGH 50% | HOLD | 0.030ns| | 0| 0\r\r
- | MINPERIOD | 0.000ns| 8.000ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP | 0.026ns| 3.974ns| 0| 0\r\r
- lus/comp_endpoint/core_clk" PERIOD = | HOLD | 0.315ns| | 0| 0\r\r
- 4 ns HIGH 50% | MINPERIOD | 0.000ns| 4.000ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.012ns| 0.838ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[7].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.015ns| 0.835ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[0].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP | 0.021ns| 1.879ns| 0| 0\r\r
- CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS" | HOLD | 1.026ns| | 0| 0\r\r
- 1.9 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 0.027ns| 7.973ns| 0| 0\r\r
- L0_CLK_OUT_2_ = PERIOD TIMEGRP "c | HOLD | 0.021ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_2_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[1].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[5].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[2].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[3].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[4].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | | \r\r
- dqs[6].u_iob_dqs/en_dqs_sync" MAX | | | | | \r\r
- DELAY = 0.85 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.068ns| 0.532ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<1>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<0>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<2>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<3>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<4>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<5>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<6>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0\r\r
- _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | | \r\r
- qs<7>" MAXDELAY = 0.6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP | 0.188ns| 7.812ns| 0| 0\r\r
- ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns | HOLD | 0.516ns| | 0| 0\r\r
- DATAPATHONLY | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns | MINPERIOD | 1.010ns| 3.990ns| 0| 0\r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP | 1.252ns| 6.748ns| 0| 0\r\r
- _Clk" TO TIMEGRP "Bridge_Clk" 8 ns | HOLD | 0.451ns| | 0| 0\r\r
- DATAPATHONLY | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY | 1.700ns| 4.300ns| 0| 0\r\r
- RP "PADS" TO TIMEGRP "RXCLK_GRP_E | HOLD | 1.060ns| | 0| 0\r\r
- thernet_MAC" 6 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 2.073ns| 5.466ns| 0| 0\r\r
- L0_CLK_OUT_0_ = PERIOD TIMEGRP "c | HOLD | 0.307ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_0_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- PHASE 2 ns HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 6.000ns| 4.000ns| 0| 0\r\r
- pin" 100 MHz HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.700ns| 8.600ns| 0| 0\r\r
- L0_CLK_OUT_4_ = PERIOD TIMEGRP "c | HOLD | 0.153ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_4_" TS_sys_clk_pin * 0.625 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.950ns| 1.050ns| 0| 0\r\r
- L0_CLK_OUT_3_ = PERIOD TIMEGRP "c | HOLD | 0.465ns| | 0| 0\r\r
- lock_generator_0_clock_generator_0_PLL0_C | MINLOWPULSE | 3.946ns| 1.054ns| 0| 0\r\r
- LK_OUT_3_" TS_sys_clk_pin * 2 HIG | | | | | \r\r
- H 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW | 4.392ns| 0.608ns| 0| 0\r\r
- UFGP" MAXSKEW = 5 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW | 4.789ns| 0.211ns| 0| 0\r\r
- UFGP" MAXSKEW = 5 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_clock_generator_0_clock_generator_0_PL | MINPERIOD | 4.900ns| 3.100ns| 0| 0\r\r
- L0_CLK_OUT_1_ = PERIOD TIMEGRP "c | | | | | \r\r
- lock_generator_0_clock_generator_0_PLL0_C | | | | | \r\r
- LK_OUT_1_" TS_sys_clk_pin * 1.25 | | | | | \r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY | 7.423ns| 2.577ns| 0| 0\r\r
- GRP "TXCLK_GRP_Ethernet_MAC" TO T | | | | | \r\r
- IMEGRP "PADS" 10 ns | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP | 10.092ns| 11.165ns| 0| 0\r\r
- UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.473ns| | 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP | 13.832ns| 6.168ns| 0| 0\r\r
- M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.471ns| | 0| 0\r\r
- TIMEGRP "TNM_CLK90" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP | 16.202ns| 3.798ns| 0| 0\r\r
- TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.049ns| | 0| 0\r\r
- TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 17.943ns| 2.057ns| 0| 0\r\r
- NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.295ns| | 0| 0\r\r
- TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 17.975ns| 2.025ns| 0| 0\r\r
- NM_GATE_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.030ns| | 0| 0\r\r
- TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP | 18.085ns| 1.915ns| 0| 0\r\r
- P "TNM_CAL_RDEN_DLY" TO TIMEGRP " | HOLD | 0.096ns| | 0| 0\r\r
- TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP | 26.710ns| 3.290ns| 0| 0\r\r
- K_pin_BUFGP/IBUFG" PERIOD = 30 ns | HOLD | 0.465ns| | 0| 0\r\r
- HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP | 32.431ns| 7.569ns| 0| 0\r\r
- UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.351ns| | 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- Pin to Pin Skew Constraint | MAXDELAY | 2106523.523ns| 2106523.837ns| 0| 0\r\r
-------------------------------------------------------------------------------------------------------\r\r
- TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A | N/A| N/A| N/A| N/A\r\r
- P "TNM_RDEN_SEL_MUX" TO TIMEGRP " | | | | | \r\r
- TNM_CLK0" TS_MC_CLK * 4 | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
- NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A | N/A| N/A| N/A| N/A\r\r
- s HIGH 50% | | | | | \r\r
-------------------------------------------------------------------------------------------------------\r\r
-\r\r
-\r\r
-Derived Constraint Report\r\r
-Derived Constraints for TS_MC_CLK\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-| | Period | Actual Period | Timing Errors | Paths Analyzed |\r\r
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-|TS_MC_CLK | 5.000ns| 3.990ns| 1.542ns| 0| 0| 0| 345|\r\r
-| TS_MC_PHY_INIT_DATA_SEL_0 | 20.000ns| 3.798ns| N/A| 0| 0| 21| 0|\r\r
-| TS_MC_PHY_INIT_DATA_SEL_90 | 20.000ns| 6.168ns| N/A| 0| 0| 274| 0|\r\r
-| TS_MC_GATE_DLY | 20.000ns| 2.025ns| N/A| 0| 0| 40| 0|\r\r
-| TS_MC_RDEN_DLY | 20.000ns| 2.057ns| N/A| 0| 0| 5| 0|\r\r
-| TS_MC_CAL_RDEN_DLY | 20.000ns| 1.915ns| N/A| 0| 0| 5| 0|\r\r
-| TS_MC_RDEN_SEL_MUX | 20.000ns| N/A| N/A| 0| 0| 0| 0|\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-\r\r
-Derived Constraints for TS_sys_clk_pin\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-| | Period | Actual Period | Timing Errors | Paths Analyzed |\r\r
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-|TS_sys_clk_pin | 10.000ns| 4.000ns| 9.966ns| 0| 0| 0| 636358|\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 5.466ns| N/A| 0| 0| 626| 0|\r\r
-| erator_0_PLL0_CLK_OUT_0_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 3.100ns| N/A| 0| 0| 0| 0|\r\r
-| erator_0_PLL0_CLK_OUT_1_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 8.000ns| 7.973ns| N/A| 0| 0| 624688| 0|\r\r
-| erator_0_PLL0_CLK_OUT_2_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 5.000ns| 1.054ns| N/A| 0| 0| 2| 0|\r\r
-| erator_0_PLL0_CLK_OUT_3_ | | | | | | | |\r\r
-| TS_clock_generator_0_clock_gen| 16.000ns| 8.600ns| N/A| 0| 0| 11042| 0|\r\r
-| erator_0_PLL0_CLK_OUT_4_ | | | | | | | |\r\r
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
-\r\r
-All constraints were met.\r\r
-INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the \r\r
- constraint does not cover any paths or that it has no requested value.\r\r
-\r\r
-\r\r
-Generating Pad Report.\r\r
-\r\r
-All signals are completely routed.\r\r
-\r\r
-WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.\r\r
-\r\r
-Loading device for application Rf_Device from file '5vlx50t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
-INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128\r\r
-INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints\r\r
- found: 128, number successful: 128\r\r
-Total REAL time to PAR completion: 9 mins 1 secs \r\r
-Total CPU time to PAR completion: 8 mins 19 secs \r\r
-\r\r
-Peak Memory Usage: 653 MB\r\r
-\r\r
-Placer: Placement generated during map.\r\r
-Routing: Completed - No errors found.\r\r
-Timing: Completed - No errors found.\r\r
-\r\r
-Number of error messages: 0\r\r
-Number of warning messages: 9\r\r
-Number of info messages: 4\r\r
-\r\r
-Writing design to file system.ncd\r\r
-\r\r
-\r\r
-\r\r
-PAR done!\r\r
-\r\r
-\r\r
-\r\r
-#----------------------------------------------#\r\r
-# Starting program post_par_trce\r\r
-# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf \r\r
-#----------------------------------------------#\r\r
-Release 11.2 - Trace (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =\r\r
- 8 ns HIGH 50%;> [system.pcf(65973)] overrides constraint <NET\r\r
- "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].\r\r
-\r\r
-WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
- TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;\r\r
- ignored during timing analysis.\r\r
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more\r\r
- information, see the TSI report. Please consult the Xilinx Command Line\r\r
- Tools User Guide for information on generating a TSI report.\r\r
---------------------------------------------------------------------------------\r\r
-Release 11.2 Trace (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-\r\r
-trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf\r\r
-\r\r
-\r\r
-Design file: system.ncd\r\r
-Physical constraint file: system.pcf\r\r
-Device,speed: xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING\r\r
-level 0)\r\r
-Report level: error report\r\r
---------------------------------------------------------------------------------\r\r
-\r\r
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths\r\r
- option. All paths that are not constrained will be reported in the\r\r
- unconstrained paths section(s) of the report.\r\r
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a\r\r
- 50 Ohm transmission line loading model. For the details of this model, and\r\r
- for more information on accounting for different loading conditions, please\r\r
- see the device datasheet.\r\r
-\r\r
-\r\r
-Timing summary:\r\r
----------------\r\r
-\r\r
-Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)\r\r
-\r\r
-Constraints cover 826342 paths, 18 nets, and 74598 connections\r\r
-\r\r
-Design statistics:\r\r
- Minimum period: 11.165ns (Maximum frequency: 89.566MHz)\r\r
- Maximum path delay from/to any node: 7.812ns\r\r
- Maximum net delay: 0.838ns\r\r
- Maximum net skew: 0.608ns\r\r
-\r\r
-\r\r
-Analysis completed Tue Jun 30 21:57:31 2009\r\r
---------------------------------------------------------------------------------\r\r
-\r\r
-Generating Report ...\r\r
-\r\r
-Number of warnings: 2\r\r
-Number of info messages: 3\r\r
-Total time: 1 mins 36 secs \r\r
-\r\r
-\r\r
-xflow done!\r\r
-touch __xps/system_routed\r
-xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par\r
-Analyzing implementation/system.par\r\r
-*********************************************\r
-Running Bitgen..\r
-*********************************************\r
-cd implementation; bitgen -w -f bitgen.ut system; cd ..\r
-Release 11.2 - Bitgen L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-PMSPEC -- Overriding Xilinx file\r\r
-<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
-<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
-Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
-c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
- "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
-Opened constraints file system.pcf.\r\r
-\r\r
-Tue Jun 30 21:58:01 2009\r\r
-\r\r
-Running DRC.\r\r
-WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.\r\r
- Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX\r\r
- Transceiver User Guide to ensure that the design SelectIO usage meets the\r\r
- guidelines to minimize the impact on GTX performance. \r\r
-WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
- PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w\r\r
- rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good\r\r
- design practice. Use the CE pin to control the loading of data into the\r\r
- flip-flop.\r\r
-WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
- Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.\r\r
- This is not good design practice. Use the CE pin to control the loading of\r\r
- data into the flip-flop.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does\r\r
- not drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal\r\r
- <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not\r\r
- drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>\r\r
- is incomplete. The signal does not drive any load pins in the design.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not\r\r
- used.\r\r
-WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
- block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
- qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF\r\r
- Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
-DRC detected 0 errors and 24 warnings. Please see the previously displayed\r\r
-individual error or warning messages for more details.\r\r
-Creating bit map...\r\r
-Saving bit stream in "system.bit".\r\r
-Bitstream generation is complete.\r\r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Sat Jul 04 20:43:06 2009
- make -f system.make download started...
-\r
-cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf\r
-*********************************************\r
-Initializing BRAM contents of the bitstream\r
-*********************************************\r
-bitinit -p xc5vfx70tff1136-1 system.mhs -pe ppc440_0 bootloops/ppc440_0.elf \\r
--bt implementation/system.bit -o implementation/download.bit\r
-\r\r
-bitinit version Xilinx EDK 11.2 Build EDK_LS3.47\r\r
-Copyright (c) Xilinx Inc. 2002.\r\r
-\r\r
-Parsing MHS File system.mhs...\r\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 251 - deprecated core for architecture 'virtex5fx'!\r\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
- 296 - deprecated core for architecture 'virtex5fx'!\r\r
-\r\r
-Overriding IP level properties ...\r\r
-\r\r
-Performing IP level DRCs on properties...\r\r
-\r\r
-Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
-Address Map for Processor ppc440_0\r\r
- (0b0000000000-0b0011111111) ppc440_0 \r\r
- (0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC\r\r
- (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0\r\r
- (0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0\r\r
- (0x81420000-0x8142ffff) LEDs_Positions plb_v46_0\r\r
- (0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0\r\r
- (0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0\r\r
- (0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0\r\r
- (0x81800000-0x8180ffff) xps_intc_0 plb_v46_0\r\r
- (0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0\r\r
- (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0\r\r
- (0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0\r\r
- (0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0\r\r
- (0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0\r\r
- (0xf8000000-0xf80fffff) SRAM plb_v46_0\r\r
- (0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0\r\r
-INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
- 01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
- C_SPLB0_P2P value to 0\r\r
-\r\r
-Computing clock values...\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
- 'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
- performed for IPs connected to that clock port, unless they are connected\r\r
- through the clock generator IP. \r\r
-\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 12\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
- PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
- v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
- PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
- value to 0x2000\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PORT_DWIDTH value to 64\r\r
-INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
- \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
- value to 8\r\r
-INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
- _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
- ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
- ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
- a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
- C_MPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
- C_MPLB_SMALLEST_SLAVE value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
- C_SPLB_SMALLEST_MASTER value to 128\r\r
-INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
- b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
- C_PLBV46_NUM_SLAVES value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_PLBV46_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
- ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
- value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
- 2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
- PARAMETER C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
- C_SPLB_DWIDTH value to 128\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
- C_SPLB_MID_WIDTH value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
- \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
- C_SPLB_NUM_MASTERS value to 1\r\r
-INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
- C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
- ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
- value to 128\r\r
-\r\r
-Checking platform address map ...\r\r
-\r\r
-Initializing Memory...\r\r
-Running Data2Mem with the following command:\r\r
-data2mem -bm "implementation/system_bd" -bt "implementation/system.bit" -bd\r\r
-"bootloops/ppc440_0.elf" tag ppc440_0 -o b implementation/download.bit \r\r
-Memory Initialization completed successfully.\r\r
-\r\r
-*********************************************\r
-Downloading Bitstream onto the target board\r
-*********************************************\r
-impact -batch etc/download.cmd\r
-Release 11.2 - iMPACT L.46 (nt)\r\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.\r\r
-Preference Table\r\r
-Name Setting \r\r
-StartupClock Auto_Correction \r\r
-AutoSignature False \r\r
-KeepSVF False \r\r
-ConcurrentMode False \r\r
-UseHighz False \r\r
-ConfigOnFailure Stop \r\r
-UserLevel Novice \r\r
-MessageLevel Detailed \r\r
-svfUseTime false \r\r
-SpiByteSwap Auto_Correction \r\r
-AutoDetecting cable. Please wait.\r\r
-Connecting to cable (Usb Port - USB21).\r\r
-Checking cable driver.\r\r
- Driver file xusb_xp2.sys found.\r\r
- Driver version: src=2301, dest=2301.\r\r
- Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
-13:58:07, version = 900.\r\r
- Cable PID = 0008.\r\r
- Max current requested during enumeration is 300 mA.\r\r
-Type = 0x0005.\r\r
- Cable Type = 3, Revision = 0.\r\r
- Setting cable speed to 6 MHz.\r\r
-Cable connection established.\r\r
-Firmware version = 2401.\r\r
-File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
-Firmware hex file version = 2401.\r\r
-PLD file version = 200Dh.\r\r
- PLD version = 200Dh.\r\r
-Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
-INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
-\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-done.\r\r
-Elapsed time = 0 sec.\r\r
-Elapsed time = 0 sec.\r\r
-'5': Loading file 'implementation/download.bit' ...\r\r
-INFO:iMPACT:1777 - \r
- Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
-\r
-done.\r\r
-UserID read from the bitstream file = 0xFFFFFFFF.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-Maximum TCK operating frequency for this device chain: 10000000.\r\r
-Validating chain...\r\r
-Boundary-scan chain validated successfully.\r\r
-5: Device Temperature: Current Reading: 72.52 C, Min. Reading: 30.69 C, Max.\r\r
-Reading: 74.49 C\r\r
-5: VCCINT Supply: Current Reading: 0.993 V, Min. Reading: 0.993 V, Max.\r\r
-Reading: 1.002 V\r\r
-5: VCCAUX Supply: Current Reading: 2.496 V, Min. Reading: 2.493 V, Max.\r\r
-Reading: 2.508 V\r\r
-INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
-\r
-'5': Programming device...\r\r
- Match_cycle = 2.\r\r
-done.\r\r
-'5': Reading status register contents...\r\r
-CRC error : 0\r\r
-Decryptor security set : 0\r\r
-DCM locked : 1\r\r
-DCI matched : 1\r\r
-End of startup signal from Startup block : 1\r\r
-status of GTS_CFG_B : 1\r\r
-status of GWE : 1\r\r
-status of GHIGH : 1\r\r
-value of MODE pin M0 : 1\r\r
-value of MODE pin M1 : 0\r\r
-Value of MODE pin M2 : 1\r\r
-Internal signal indicates when housecleaning is completed: 1\r\r
-Value driver in from INIT pad : 1\r\r
-Internal signal indicates that chip is configured : 1\r\r
-Value of DONE pin : 1\r\r
-Indicates when ID value written does not match chip ID: 0\r\r
-Decryptor error Signal : 0\r\r
-System Monitor Over-Temperature Alarm : 0\r\r
-startup_state[18] CFG startup state machine : 0\r\r
-startup_state[19] CFG startup state machine : 0\r\r
-startup_state[20] CFG startup state machine : 1\r\r
-E-fuse program voltage available : 0\r\r
-SPI Flash Type[22] Select : 1\r\r
-SPI Flash Type[23] Select : 1\r\r
-SPI Flash Type[24] Select : 1\r\r
-CFG bus width auto detection result : 0\r\r
-CFG bus width auto detection result : 0\r\r
-Reserved : 0\r\r
-BPI address wrap around error : 0\r\r
-IPROG pulsed : 0\r\r
-read back crc error : 0\r\r
-Indicates that efuse logic is busy : 0\r\r
- Match_cycle = 2.\r\r
-'5': Programmed successfully.\r\r
-Elapsed time = 11 sec.\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-----------------------------------------------------------------------\r\r
-INFO:iMPACT:2219 - Status register values:\r
-INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
-INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
-INFO:iMPACT - '5': Programing completed successfully.\r
-INFO:iMPACT - '5': Checking done pin....done.\r
-\r
-\r
-\r
-Done!
-\r
-At Local date and time: Sat Jul 04 20:43:42 2009
- make -f system.make program started...
-\r
-powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \\r
- -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \\r
--D GCC_PPC440 -mregnames \r
-powerpc-eabi-size RTOSDemo/executable.elf \r
- text data bss dec hex filename\r
- 53174 372 86528 140074 2232a RTOSDemo/executable.elf\r
-\r
-\r
-Done!
-\r
-start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; exit;"
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 11.2 Build EDK_LS3.47
-\r
-Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-\r
-WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
-\r
-WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
-\r
-Generating Block Diagram to Buffer
-\r
-Generated Block Diagram SVG
-\r
-At Local date and time: Sun Jul 05 09:35:22 2009
- make -f system.make hwclean started...
-\r
-rm -f implementation/system.ngc\r
-rm -f platgen.log\r
-rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
-rm -f implementation/system.bmm\r
-rm -f implementation/system.bit\r
-rm -f implementation/system.ncd\r
-rm -f implementation/system_bd.bmm \r
-rm -f implementation/system_map.ncd \r
-rm -f __xps/system_routed\r
-rm -rf implementation synthesis xst hdl\r
-rm -rf xst.srp system.srp\r
-rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
-\r
-\r
-Done!
-\r
-At Local date and time: Sun Jul 05 09:35:36 2009
- make -f system.make swclean started...
-\r
-rm -rf ppc440_0/\r
-rm -f libgen.log\r
-rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
-rm -f RTOSDemo/executable.elf \r
-\r
-\r
-Done!
-\r
-Writing filter settings....
-\r
-Done writing filter settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
-\r
-Done writing Tab View settings to:
- C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
-\r
*/\r
\r
/******************************************************************************\r
- * NOTE 1: The Win32 port is a simulation (or is that emulation?) only! Do not\r
- * expect to get real time behaviour from the Win32 port or this demo\r
- * application. It is provided as a convenient development and demonstration\r
- * test bed only. This was tested using Windows XP on a dual core laptop.\r
- *\r
- * Windows will not be running the FreeRTOS simulator threads continuously, so\r
- * the timing information in the FreeRTOS+Trace logs have no meaningful units.\r
- * See the documentation page for the Windows simulator for an explanation of\r
- * the slow timing:\r
+ * NOTE 1: Do not expect to get real time behaviour from the Win32 port or this\r
+ * demo application. It is provided as a convenient development and\r
+ * demonstration test bed only. Windows will not be running the FreeRTOS\r
+ * threads continuously, so the timing information in the FreeRTOS+Trace logs\r
+ * have no meaningful units. See the documentation page for the Windows\r
+ * simulator for further explanation:\r
* http://www.freertos.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html\r
* - READ THE WEB DOCUMENTATION FOR THIS PORT FOR MORE INFORMATION ON USING IT -\r
*\r
* in main.c.\r
******************************************************************************\r
*\r
- * main_blinky() creates one queue, and two tasks. It then starts the\r
- * scheduler.\r
+ * main_blinky() creates one queue, one software timer, and two tasks. It then\r
+ * starts the scheduler.\r
*\r
* The Queue Send Task:\r
* The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
- * block for 200 (simulated as far as the scheduler is concerned, but in\r
- * reality much longer - see notes above) milliseconds, before sending the\r
- * value 100 to the queue that was created within main_blinky(). Once the\r
- * value is sent, the task loops back around to block for another 200\r
- * (simulated) milliseconds.\r
+ * this file. It uses vTaskDelayUntil() to create a period task that sends the\r
+ * value 100 to the queue every 200 milliseconds (please read the notes above\r
+ * regarding the accuracy of timing under Windows).\r
+ *\r
+ * The Queue Send Software Timer:\r
+ * The timer is a one-shot timer that is reset by a key press. The timer's\r
+ * period is set to two seconds - if the timer expires then its callback\r
+ * function writes the value 200 to the queue. The callback function is\r
+ * implemented by prvQueueSendTimerCallback() within this file.\r
*\r
* The Queue Receive Task:\r
* The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
- * blocks on attempts to read data from the queue that was created within\r
- * main_blinky(). When data is received, the task checks the value of the\r
- * data, and if the value equals the expected 100, outputs a message. The\r
- * 'block time' parameter passed to the queue receive function specifies that\r
- * the task should be held in the Blocked state indefinitely to wait for data\r
- * to be available on the queue. The queue receive task will only leave the\r
- * Blocked state when the queue send task writes to the queue. As the queue\r
- * send task writes to the queue every 200 (simulated - see notes above)\r
- * milliseconds, the queue receive task leaves the Blocked state every 200\r
- * milliseconds, and therefore outputs a message every 200 milliseconds.\r
+ * in this file. prvQueueReceiveTask() waits for data to arrive on the queue.\r
+ * When data is received, the task checks the value of the data, then outputs a\r
+ * message to indicate if the data came from the queue send task or the queue\r
+ * send software timer. As the queue send task writes to the queue every 200ms,\r
+ * the queue receive task will print a message indicating that it received data\r
+ * from the queue send task every 200ms. The queue receive task will print a\r
+ * message indicating that it received data from the queue send software timer\r
+ * 2 seconds after a key was last pressed.\r
*/\r
\r
/* Standard includes. */\r
#include <stdio.h>\r
+#include <conio.h>\r
\r
/* Kernel includes. */\r
#include "FreeRTOS.h"\r
#include "task.h"\r
+#include "timers.h"\r
#include "semphr.h"\r
\r
/* Priorities at which the tasks are created. */\r
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
\r
-/* The rate at which data is sent to the queue. The 200ms value is converted\r
-to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+/* The rate at which data is sent to the queue. The times are converted from\r
+milliseconds to ticks by the pdMS_TO_TICKS() macro where they are used. */\r
+#define mainTASK_SEND_FREQUENCY_MS 200\r
+#define mainTIMER_SEND_FREQUENCY_MS 2000\r
\r
-/* The number of items the queue can hold. This is 1 as the receive task\r
-will remove items as they are added, meaning the send task should always find\r
-the queue empty. */\r
-#define mainQUEUE_LENGTH ( 1 )\r
+/* The number of items the queue can hold. */\r
+#define mainQUEUE_LENGTH ( 2 )\r
\r
/* Values passed to the two tasks just to check the task parameter\r
functionality. */\r
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
\r
+/* The values sent to the queue receive task from the queue send task and the\r
+queue send software timer respectively. */\r
+#define mainVALUE_SENT_FROM_TASK ( 100UL )\r
+#define mainVALUE_SENT_FROM_TIMER ( 200UL )\r
+\r
/*-----------------------------------------------------------*/\r
\r
/*\r
static void prvQueueReceiveTask( void *pvParameters );\r
static void prvQueueSendTask( void *pvParameters );\r
\r
+/*\r
+ * The callback function executed when the software timer expires.\r
+ */\r
+static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle );\r
+\r
/*-----------------------------------------------------------*/\r
\r
/* The queue used by both tasks. */\r
static QueueHandle_t xQueue = NULL;\r
\r
+/* A software timer that is started from the tick hook. */\r
+static TimerHandle_t xTimer = NULL;\r
+\r
/*-----------------------------------------------------------*/\r
\r
void main_blinky( void )\r
{\r
+const TickType_t xTimerPeriod = pdMS_TO_TICKS( mainTIMER_SEND_FREQUENCY_MS );\r
+\r
/* Create the queue. */\r
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
\r
\r
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
\r
+ /* Create the software timer, but don't start it yet. */\r
+ xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */\r
+ xTimerPeriod, /* The period of the software timer in ticks. */\r
+ pdFALSE, /* xAutoReload is set to pdFALSE, so this is a one shot timer. */\r
+ NULL, /* The timer's ID is not used. */\r
+ prvQueueSendTimerCallback );/* The function executed when the timer expires. */\r
+\r
/* Start the tasks and timer running. */\r
vTaskStartScheduler();\r
}\r
static void prvQueueSendTask( void *pvParameters )\r
{\r
TickType_t xNextWakeTime;\r
-const unsigned long ulValueToSend = 100UL;\r
-const TickType_t xBlockTime = pdMS_TO_TICKS( mainQUEUE_SEND_FREQUENCY_MS );\r
+const TickType_t xBlockTime = pdMS_TO_TICKS( mainTASK_SEND_FREQUENCY_MS );\r
+const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK;\r
\r
/* Remove compiler warning in the case that configASSERT() is not\r
defined. */\r
/* Send to the queue - causing the queue receive task to unblock and\r
toggle the LED. 0 is used as the block time so the sending operation\r
will not block - it shouldn't need to block as the queue should always\r
- be empty at this point in the code. */\r
+ have at least one space at this point in the code. */\r
xQueueSend( xQueue, &ulValueToSend, 0U );\r
}\r
}\r
/*-----------------------------------------------------------*/\r
\r
+static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle )\r
+{\r
+const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER;\r
+\r
+ /* Avoid compiler warnings resulting from the unused parameter. */\r
+ ( void ) xTimerHandle;\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ write out a message. This function is called from the timer/daemon task, so\r
+ must not block. Hence the block time is set to 0. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
static void prvQueueReceiveTask( void *pvParameters )\r
{\r
unsigned long ulReceivedValue;\r
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
\r
/* To get here something must have been received from the queue, but\r
- is it the expected value? If it is, toggle the LED. */\r
- if( ulReceivedValue == 100UL )\r
+ is it the expected value? Normally calling printf() from a task is not\r
+ a good idea. Here there is lots of stack space and only one task is\r
+ using console IO so it is ok. */\r
+ if( ulReceivedValue == mainVALUE_SENT_FROM_TASK )\r
+ {\r
+ printf( "Message received from task\r\n" );\r
+ }\r
+ else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER )\r
+ {\r
+ printf( "Message received from software timer\r\n" );\r
+ }\r
+ else\r
+ {\r
+ printf( "Unexpected message\r\n" );\r
+ }\r
+\r
+ /* Reset the timer if a key has been pressed. The timer will write\r
+ mainVALUE_SENT_FROM_TIMER to the queue when it expires. */\r
+ if( _kbhit() != 0 )\r
{\r
- /* Normally calling printf() from a task is not a good idea. Here\r
- there is lots of stack space and only one task is using console IO\r
- so it is ok. */\r
- printf( "Message received\r\n" );\r
- ulReceivedValue = 0U;\r
+ /* Remove the key from the input buffer. */\r
+ ( void ) _getch();\r
+\r
+ /* Reset the software timer. */\r
+ xTimerReset( xTimer, portMAX_DELAY );\r
}\r
}\r
}\r
/*-----------------------------------------------------------*/\r
\r
+\r
pop_x r15\r
mov.w r15, &usCriticalNesting\r
popm_x #12, r15\r
+ nop\r
pop.w sr\r
+ nop\r
ret_x\r
.endm\r
;-----------------------------------------------------------\r
nesting variable is initialised to a non-zero value. */\r
#define portINITIAL_NESTING_VALUE ( 0xff )\r
\r
-/* The bit within the MSR register that enabled/disables interrupts. */\r
+/* The bit within the MSR register that enabled/disables interrupts and \r
+exceptions respectively. */\r
#define portMSR_IE ( 0x02U )\r
+#define portMSR_EE ( 0x100U )\r
\r
/* If the floating point unit is included in the MicroBlaze build, then the\r
FSR register is saved as part of the task context. portINITIAL_FSR is the value\r
*pxTopOfStack = ( StackType_t ) 0x00000000;\r
pxTopOfStack--;\r
\r
- #if XPAR_MICROBLAZE_0_USE_FPU != 0\r
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )\r
/* The FSR value placed in the initial task context is just 0. */\r
*pxTopOfStack = portINITIAL_FSR;\r
pxTopOfStack--;\r
disabled. Each task will enable interrupts automatically when it enters\r
the running state for the first time. */\r
*pxTopOfStack = mfmsr() & ~portMSR_IE;\r
+ \r
+ #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )\r
+ {\r
+ /* Ensure exceptions are enabled for the task. */\r
+ *pxTopOfStack |= portMSR_EE;\r
+ }\r
+ #endif\r
+\r
pxTopOfStack--;\r
\r
/* First stack an initial value for the critical section nesting. This\r
exception. */\r
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;\r
\r
- #if XPAR_MICROBLAZE_0_USE_FPU != 0\r
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )\r
{\r
xRegisterDump.ulFSR = mffsr();\r
}\r
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";\r
break;\r
\r
- #if XPAR_MICROBLAZE_0_USE_FPU != 0\r
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )\r
\r
case XEXC_ID_FPU :\r
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";\r
break;\r
\r
- #endif /* XPAR_MICROBLAZE_0_USE_FPU */\r
+ #endif /* XPAR_MICROBLAZE_USE_FPU */\r
}\r
\r
/* vApplicationExceptionRegisterDump() is a callback function that the\r
{\r
ulHandlersAlreadyInstalled = pdTRUE;\r
\r
- #if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1\r
+ #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1\r
microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );\r
- #endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/\r
+ #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/\r
\r
- #if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1\r
+ #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1\r
microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );\r
- #endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/\r
+ #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */\r
\r
- #if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1\r
+ #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1\r
microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/\r
+ #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */\r
\r
- #if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1\r
+ #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1\r
microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/\r
+ #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */\r
\r
- #if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1\r
+ #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1\r
microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/\r
+ #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */\r
\r
- #if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1\r
+ #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1\r
microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/\r
+ #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */\r
\r
- #if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1\r
+ #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1\r
microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );\r
- #endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/\r
+ #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */\r
\r
- #if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1\r
+ #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1\r
microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );\r
- #endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/\r
+ #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */\r
\r
- #if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1\r
+ #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1\r
microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );\r
- #endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/\r
+ #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */\r
+\r
+ microblaze_enable_exceptions();\r
}\r
}\r
\r
\r
/* The context is oversized to allow functions called from the ISR to write\r
back into the caller stack. */\r
-#if XPAR_MICROBLAZE_0_USE_FPU != 0\r
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )\r
#define portCONTEXT_SIZE 136\r
#define portMINUS_CONTEXT_SIZE -136\r
#else\r
mfs r18, rmsr\r
swi r18, r1, portMSR_OFFSET\r
\r
- #if XPAR_MICROBLAZE_0_USE_FPU != 0\r
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )\r
/* Stack FSR. */\r
mfs r18, rfsr\r
swi r18, r1, portFSR_OFFSET\r
lwi r18, r1, portMSR_OFFSET\r
mts rmsr, r18\r
\r
- #if XPAR_MICROBLAZE_0_USE_FPU != 0\r
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )\r
/* Reload the FSR from the stack. */\r
lwi r18, r1, portFSR_OFFSET\r
mts rfsr, r18\r
vTaskSwitchContext() being made from a single interrupt, as a single interrupt\r
can result in multiple peripherals being serviced. */\r
extern volatile uint32_t ulTaskSwitchRequested;\r
-#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) ulTaskSwitchRequested = 1\r
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1\r
\r
#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )\r
\r
/*-----------------------------------------------------------*/\r
\r
#ifdef __GNUC__\r
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \\r
- __asm volatile( "mov %0, %%eax \n\t" \\r
- "bsr %%eax, %%eax \n\t" \\r
- "mov %%eax, %1 \n\t" \\r
- :"=r"(uxTopPriority) : "r"(uxReadyPriorities) : "eax" )\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \\r
+ __asm volatile( "bsr %1, %0\n\t" \\r
+ :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )\r
#else\r
/* BitScanReverse returns the bit position of the most significant '1'\r
in the word. */\r
Queue_t *pxNewQueue;\r
size_t xQueueSizeInBytes;\r
QueueHandle_t xReturn = NULL;\r
-int8_t *pcAllocatedBuffer;\r
\r
/* Remove compiler warnings about unused parameters should\r
configUSE_TRACE_FACILITY not be set to 1. */\r
}\r
\r
/* Allocate the new queue structure and storage area. */\r
- pcAllocatedBuffer = ( int8_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );\r
+ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );\r
\r
- if( pcAllocatedBuffer != NULL )\r
+ if( pxNewQueue != NULL )\r
{\r
- pxNewQueue = ( Queue_t * ) pcAllocatedBuffer; /*lint !e826 MISRA The buffer cannot be too small because it was dimensioned by sizeof( Queue_t ) + xQueueSizeInBytes. */\r
-\r
if( uxItemSize == ( UBaseType_t ) 0 )\r
{\r
/* No RAM was allocated for the queue storage area, but PC head\r
else\r
{\r
/* Jump past the queue structure to find the location of the queue\r
- storage area - adding the padding bytes to get a better alignment. */\r
- pxNewQueue->pcHead = pcAllocatedBuffer + sizeof( Queue_t );\r
+ storage area. */\r
+ pxNewQueue->pcHead = ( ( int8_t * ) pxNewQueue ) + sizeof( Queue_t );\r
}\r
\r
/* Initialise the queue members as described above where the queue type\r
projects / freertos / commitdiff
