--- /dev/null
+\r
+Microsoft Visual Studio Solution File, Format Version 11.00\r
+# Atmel Studio Solution File, Format Version 11.00\r
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "RTOSDemo", "RTOSDemo\RTOSDemo.cproj", "{2A475B6A-78B0-4237-8947-341BD379AB5C}"\r
+EndProject\r
+Global\r
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution\r
+ Debug|ARM = Debug|ARM\r
+ Release|ARM = Release|ARM\r
+ EndGlobalSection\r
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution\r
+ {2A475B6A-78B0-4237-8947-341BD379AB5C}.Debug|ARM.ActiveCfg = Debug|ARM\r
+ {2A475B6A-78B0-4237-8947-341BD379AB5C}.Debug|ARM.Build.0 = Debug|ARM\r
+ {2A475B6A-78B0-4237-8947-341BD379AB5C}.Release|ARM.ActiveCfg = Release|ARM\r
+ {2A475B6A-78B0-4237-8947-341BD379AB5C}.Release|ARM.Build.0 = Release|ARM\r
+ EndGlobalSection\r
+ GlobalSection(SolutionProperties) = preSolution\r
+ HideSolutionNode = FALSE\r
+ EndGlobalSection\r
+EndGlobal\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">\r
+ <PropertyGroup>\r
+ <SchemaVersion>2.0</SchemaVersion>\r
+ <ProjectVersion>6.1</ProjectVersion>\r
+ <ProjectGuid>{2a475b6a-78b0-4237-8947-341bd379ab5c}</ProjectGuid>\r
+ <Name>$(MSBuildProjectName)</Name>\r
+ <AssemblyName>$(MSBuildProjectName)</AssemblyName>\r
+ <RootNamespace>$(MSBuildProjectName)</RootNamespace>\r
+ <AsfFrameworkConfig>\r
+ <framework-data>\r
+ <options>\r
+ <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam0.drivers.port" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam0.drivers.system" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.basic.serial" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.applications.user_application.xplained_pro2" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.utils" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam0.utils.cmsis.samd20.source.template" value="Add" config="" content-id="Atmel.ASF" />\r
+ </options>\r
+ <configurations>\r
+ <configuration key="config.sam0.drivers.sercom.usart" value="callback" default="callback" content-id="Atmel.ASF" />\r
+ </configurations>\r
+ <files>\r
+ <file path="src/main.c" framework="" version="" source="common2/applications/xplained_pro_user_application/main.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/config/conf_board.h" framework="" version="" source="common2/applications/xplained_pro_user_application/samd20j18_samd20_xplained_pro/config/conf_board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/config/conf_clocks.h" framework="" version="" source="common2/applications/xplained_pro_user_application/samd20j18_samd20_xplained_pro/config/conf_clocks.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/boards/board.h" framework="" version="" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/utils/interrupt.h" framework="" version="" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/utils/parts.h" framework="" version="" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/boards/samd20_xplained_pro/board_init.c" framework="" version="" source="sam0/boards/samd20_xplained_pro/board_init.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h" framework="" version="" source="sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/port/port.c" framework="" version="" source="sam0/drivers/port/port.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/port/port.h" framework="" version="" source="sam0/drivers/port/port.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h" framework="" version="" source="sam0/drivers/port/quick_start/qs_port_basic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/clock/clock.c" framework="" version="" source="sam0/drivers/system/clock/clock.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/clock/clock.h" framework="" version="" source="sam0/drivers/system/clock/clock.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/clock/clock_config_check.h" framework="" version="" source="sam0/drivers/system/clock/clock_config_check.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/clock/gclk.c" framework="" version="" source="sam0/drivers/system/clock/gclk.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/clock/gclk.h" framework="" version="" source="sam0/drivers/system/clock/gclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/clock/quick_start_clock/qs_clock_source.h" framework="" version="" source="sam0/drivers/system/clock/quick_start_clock/qs_clock_source.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/clock/quick_start_gclk/qs_gclk_basic.h" framework="" version="" source="sam0/drivers/system/clock/quick_start_gclk/qs_gclk_basic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/interrupt/quick_start/qs_system_interrupt.h" framework="" version="" source="sam0/drivers/system/interrupt/quick_start/qs_system_interrupt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt.c" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt.h" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/pinmux/pinmux.c" framework="" version="" source="sam0/drivers/system/pinmux/pinmux.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/pinmux/pinmux.h" framework="" version="" source="sam0/drivers/system/pinmux/pinmux.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h" framework="" version="" source="sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/system.c" framework="" version="" source="sam0/drivers/system/system.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/drivers/system/system.h" framework="" version="" source="sam0/drivers/system/system.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_ac.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_ac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_adc.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_dac.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_dac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_dsu.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_dsu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_eic.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_eic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_evsys.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_evsys.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_gclk.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_gclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_nvmctrl.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_nvmctrl.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_pac.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_pac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_pm.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_pm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_port.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_port.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_rtc.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_sercom.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_sercom.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_sysctrl.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_sysctrl.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_tc.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/component/component_wdt.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_ac.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_ac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_adc.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_dac.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_dac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_dsu.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_dsu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_eic.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_eic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_evsys.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_evsys.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_gclk.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_gclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_nvmctrl.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_nvmctrl.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac0.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_pac0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac1.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_pac1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac2.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_pac2.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pm.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_pm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_port.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_port.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_rtc.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom0.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_sercom0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom1.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_sercom1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom2.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_sercom2.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom3.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_sercom3.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom4.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_sercom4.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom5.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_sercom5.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sysctrl.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_sysctrl.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc0.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc1.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc2.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_tc2.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc3.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_tc3.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc4.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_tc4.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc5.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_tc5.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc6.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_tc6.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc7.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_tc7.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_wdt.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20e14.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20e14.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20e15.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20e15.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20e16.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20e16.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20e17.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20e17.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20e18.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20e18.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20g14.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20g14.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20g15.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20g15.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20g16.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20g16.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20g17.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20g17.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20g18.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20g18.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20j14.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20j14.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20j15.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20j15.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20j16.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20j16.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20j17.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20j17.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/pio/pio_samd20j18.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/pio/pio_samd20j18.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam0/utils/cmsis/samd20/include/samd20.h" framework="" version="" source="sam0/utils/cmsis/samd20/include/samd20.h" changed="False" content-id="Atmel.ASF" />\r
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+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_port.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_rtc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_sercom0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_sercom1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_sercom2.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_sercom3.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_sercom4.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_sercom5.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_sysctrl.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_tc0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_tc1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_tc2.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_tc3.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_tc4.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_tc5.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_tc6.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_tc7.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\instance_wdt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20e14.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20e15.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20e16.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20e17.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20e18.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20g14.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20g15.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20g16.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20g17.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20g18.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20j14.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20j15.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20j16.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20j17.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\pio_samd20j18.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20e14.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20e15.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20e16.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20e17.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20e18.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20g14.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20g15.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20g16.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20g17.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20g18.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20j14.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20j15.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20j16.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20j17.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\include\samd20j18.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\cmsis\samd20\source\system_samd20.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\compiler.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\header_files\io.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\linker_scripts\samd20\gcc\samd20j18_flash.ld">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\make\Makefile.sam.in">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\preprocessor\mrepeat.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\preprocessor\preprocessor.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\preprocessor\stringz.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\preprocessor\tpaste.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam0\utils\status_codes.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\CMSIS END USER LICENCE AGREEMENT.pdf">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\arm_math.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cm0plus.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cmFunc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cmInstr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Lib\GCC\libarm_cortexM0l_math.a">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\README.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\license.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ </ItemGroup>\r
+ <ItemGroup>\r
+ <Folder Include="src\" />\r
+ <Folder Include="src\ASF\" />\r
+ <Folder Include="src\ASF\common\" />\r
+ <Folder Include="src\ASF\common\boards\" />\r
+ <Folder Include="src\ASF\common\services\" />\r
+ <Folder Include="src\ASF\common\services\serial\" />\r
+ <Folder Include="src\ASF\common\services\serial\sam0_usart\" />\r
+ <Folder Include="src\ASF\common\utils\" />\r
+ <Folder Include="src\ASF\common\utils\interrupt\" />\r
+ <Folder Include="src\ASF\sam0\" />\r
+ <Folder Include="src\ASF\sam0\boards\" />\r
+ <Folder Include="src\ASF\sam0\boards\samd20_xplained_pro\" />\r
+ <Folder Include="src\ASF\sam0\drivers\" />\r
+ <Folder Include="src\ASF\sam0\drivers\port\" />\r
+ <Folder Include="src\ASF\sam0\drivers\port\quick_start\" />\r
+ <Folder Include="src\ASF\sam0\drivers\sercom\" />\r
+ <Folder Include="src\ASF\sam0\drivers\sercom\usart\" />\r
+ <Folder Include="src\ASF\sam0\drivers\sercom\usart\quick_start\" />\r
+ <Folder Include="src\ASF\sam0\drivers\sercom\usart\quick_start_callback\" />\r
+ <Folder Include="src\ASF\sam0\drivers\system\" />\r
+ <Folder Include="src\ASF\sam0\drivers\system\clock\" />\r
+ <Folder Include="src\ASF\sam0\drivers\system\clock\quick_start_clock\" />\r
+ <Folder Include="src\ASF\sam0\drivers\system\clock\quick_start_gclk\" />\r
+ <Folder Include="src\ASF\sam0\drivers\system\interrupt\" />\r
+ <Folder Include="src\ASF\sam0\drivers\system\interrupt\quick_start\" />\r
+ <Folder Include="src\ASF\sam0\drivers\system\pinmux\" />\r
+ <Folder Include="src\ASF\sam0\drivers\system\pinmux\quick_start\" />\r
+ <Folder Include="src\ASF\sam0\utils\" />\r
+ <Folder Include="src\ASF\sam0\utils\cmsis\" />\r
+ <Folder Include="src\ASF\sam0\utils\cmsis\samd20\" />\r
+ <Folder Include="src\ASF\sam0\utils\cmsis\samd20\include\" />\r
+ <Folder Include="src\ASF\sam0\utils\cmsis\samd20\include\component\" />\r
+ <Folder Include="src\ASF\sam0\utils\cmsis\samd20\include\instance\" />\r
+ <Folder Include="src\ASF\sam0\utils\cmsis\samd20\include\pio\" />\r
+ <Folder Include="src\ASF\sam0\utils\cmsis\samd20\source\" />\r
+ <Folder Include="src\ASF\sam0\utils\cmsis\samd20\source\gcc\" />\r
+ <Folder Include="src\ASF\sam0\utils\header_files\" />\r
+ <Folder Include="src\ASF\sam0\utils\linker_scripts\" />\r
+ <Folder Include="src\ASF\sam0\utils\linker_scripts\samd20\" />\r
+ <Folder Include="src\ASF\sam0\utils\linker_scripts\samd20\gcc\" />\r
+ <Folder Include="src\ASF\sam0\utils\make\" />\r
+ <Folder Include="src\ASF\sam0\utils\preprocessor\" />\r
+ <Folder Include="src\ASF\sam0\utils\syscalls\" />\r
+ <Folder Include="src\ASF\sam0\utils\syscalls\gcc\" />\r
+ <Folder Include="src\ASF\thirdparty\" />\r
+ <Folder Include="src\ASF\thirdparty\CMSIS\" />\r
+ <Folder Include="src\ASF\thirdparty\CMSIS\Include\" />\r
+ <Folder Include="src\ASF\thirdparty\CMSIS\Lib\" />\r
+ <Folder Include="src\ASF\thirdparty\CMSIS\Lib\GCC\" />\r
+ <Folder Include="src\config\" />\r
+ <Folder Include="src\FreeRTOS-Source" />\r
+ <Folder Include="src\FreeRTOS-Source\include" />\r
+ <Folder Include="src\FreeRTOS-Source\portable" />\r
+ <Folder Include="src\FreeRTOS-CLI" />\r
+ </ItemGroup>\r
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />\r
+</Project>
\ No newline at end of file
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Standard board header file.\r
+ *\r
+ * This file includes the appropriate board header file according to the\r
+ * defined board (parameter BOARD).\r
+ *\r
+ * Copyright (c) 2009-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+/**\r
+ * \defgroup group_common_boards Generic board support\r
+ *\r
+ * The generic board support module includes board-specific definitions\r
+ * and function prototypes, such as the board initialization function.\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/*! \name Base Boards\r
+ */\r
+//! @{\r
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.\r
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.\r
+#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board.\r
+#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.\r
+#define EVK1105 5 //!< AT32UC3A EVK1105 board.\r
+#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.\r
+#define UC3L_EK 7 //!< AT32UC3L-EK board.\r
+#define XPLAIN 8 //!< ATxmega128A1 Xplain board.\r
+#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.\r
+#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.\r
+#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.\r
+#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.\r
+#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.\r
+#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.\r
+#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.\r
+#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.\r
+#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board\r
+#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board\r
+#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board\r
+#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.\r
+#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.\r
+#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.\r
+#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.\r
+#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.\r
+#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.\r
+#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards\r
+#define RZ600 31 //!< AT32UC3A RZ600 MCU board\r
+#define SAM3S_EK 32 //!< SAM3S-EK board.\r
+#define SAM3U_EK 33 //!< SAM3U-EK board.\r
+#define SAM3X_EK 34 //!< SAM3X-EK board.\r
+#define SAM3N_EK 35 //!< SAM3N-EK board.\r
+#define SAM3S_EK2 36 //!< SAM3S-EK2 board.\r
+#define SAM4S_EK 37 //!< SAM4S-EK board.\r
+#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.\r
+#define STK600_MEGA 39 //!< STK600 MEGA board.\r
+#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.\r
+#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.\r
+#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.\r
+#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.\r
+#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board\r
+#define SAM4L_EK 45 //!< SAM4L-EK board.\r
+#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.\r
+#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.\r
+#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.\r
+#define SAM4S_EK2 49 //!< SAM4S-EK2 board.\r
+#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.\r
+#define SAM4E_EK 51 //!< SAM4E-EK board.\r
+#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.\r
+#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.\r
+#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.\r
+#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit\r
+#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 zigbit\r
+#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B zigbit\r
+#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.\r
+#define SAMD20_XPLAINED_PRO 59 //!< SAMD20 Xplained PRO board\r
+#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.\r
+#define SAM4N_XPLAINED_PRO 61 //!< SAM4N-XPLAINED-PRO board.\r
+#define XMEGA_A3_REB_CBB 62 //!< SAM4L8 Xplained Pro board.\r
+#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB\r
+#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices\r
+#define AVR_SIMULATOR_UC3 98 //!< AVR SIMULATOR for AVR UC3 device family.\r
+#define USER_BOARD 99 //!< User-reserved board (if any).\r
+#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader)\r
+//! @}\r
+\r
+/*! \name Extension Boards\r
+ */\r
+//! @{\r
+#define EXT1102 1 //!< AT32UC3B EXT1102 board\r
+#define MC300 2 //!< AT32UC3 MC300 board\r
+#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1\r
+#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2\r
+#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board\r
+#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board\r
+#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"\r
+#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600\r
+#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600\r
+#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600\r
+#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard\r
+#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board\r
+#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).\r
+//! @}\r
+\r
+#if BOARD == EVK1100\r
+# include "evk1100/evk1100.h"\r
+#elif BOARD == EVK1101\r
+# include "evk1101/evk1101.h"\r
+#elif BOARD == UC3C_EK\r
+# include "uc3c_ek/uc3c_ek.h"\r
+#elif BOARD == EVK1104\r
+# include "evk1104/evk1104.h"\r
+#elif BOARD == EVK1105\r
+# include "evk1105/evk1105.h"\r
+#elif BOARD == STK600_RCUC3L0\r
+# include "stk600/rcuc3l0/stk600_rcuc3l0.h"\r
+#elif BOARD == UC3L_EK\r
+# include "uc3l_ek/uc3l_ek.h"\r
+#elif BOARD == STK600_RCUC3L4\r
+# include "stk600/rcuc3l4/stk600_rcuc3l4.h"\r
+#elif BOARD == XPLAIN\r
+# include "xplain/xplain.h"\r
+#elif BOARD == STK600_MEGA\r
+ /*No header-file to include*/\r
+#elif BOARD == STK600_MEGA_RF\r
+# include "stk600.h"\r
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO\r
+# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"\r
+#elif BOARD == ATMEGA256RFR2_ZIGBIT\r
+# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"\r
+#elif BOARD == STK600_RC032X\r
+# include "stk600/rc032x/stk600_rc032x.h"\r
+#elif BOARD == STK600_RC044X\r
+# include "stk600/rc044x/stk600_rc044x.h"\r
+#elif BOARD == STK600_RC064X\r
+# include "stk600/rc064x/stk600_rc064x.h"\r
+#elif BOARD == STK600_RC100X\r
+# include "stk600/rc100x/stk600_rc100x.h"\r
+#elif BOARD == UC3_A3_XPLAINED\r
+# include "uc3_a3_xplained/uc3_a3_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED\r
+# include "uc3_l0_xplained/uc3_l0_xplained.h"\r
+#elif BOARD == STK600_RCUC3B0\r
+# include "stk600/rcuc3b0/stk600_rcuc3b0.h"\r
+#elif BOARD == STK600_RCUC3D\r
+# include "stk600/rcuc3d/stk600_rcuc3d.h"\r
+#elif BOARD == STK600_RCUC3C0\r
+# include "stk600/rcuc3c0/stk600_rcuc3c0.h"\r
+#elif BOARD == XMEGA_B1_XPLAINED\r
+# include "xmega_b1_xplained/xmega_b1_xplained.h"\r
+#elif BOARD == STK600_RC064X_LCDX\r
+# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"\r
+#elif BOARD == STK600_RC100X_LCDX\r
+# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"\r
+#elif BOARD == XMEGA_A1_XPLAINED\r
+# include "xmega_a1_xplained/xmega_a1_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED_BC\r
+# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"\r
+#elif BOARD == SAM3S_EK\r
+# include "sam3s_ek/sam3s_ek.h"\r
+# include "system_sam3s.h"\r
+#elif BOARD == SAM3S_EK2\r
+# include "sam3s_ek2/sam3s_ek2.h"\r
+# include "system_sam3sd8.h"\r
+#elif BOARD == SAM3U_EK\r
+# include "sam3u_ek/sam3u_ek.h"\r
+# include "system_sam3u.h"\r
+#elif BOARD == SAM3X_EK\r
+# include "sam3x_ek/sam3x_ek.h"\r
+# include "system_sam3x.h"\r
+#elif BOARD == SAM3N_EK\r
+# include "sam3n_ek/sam3n_ek.h"\r
+# include "system_sam3n.h"\r
+#elif BOARD == SAM4S_EK\r
+# include "sam4s_ek/sam4s_ek.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == SAM4S_WPIR_RD\r
+# include "sam4s_wpir_rd/sam4s_wpir_rd.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == SAM4S_XPLAINED\r
+# include "sam4s_xplained/sam4s_xplained.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == SAM4S_EK2\r
+# include "sam4s_ek2/sam4s_ek2.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == MEGA_1284P_XPLAINED\r
+ /*No header-file to include*/\r
+#elif BOARD == ARDUINO_DUE_X\r
+# include "arduino_due_x/arduino_due_x.h"\r
+# include "system_sam3x.h"\r
+#elif BOARD == SAM4L_EK\r
+# include "sam4l_ek/sam4l_ek.h"\r
+#elif BOARD == SAM4E_EK\r
+# include "sam4e_ek/sam4e_ek.h"\r
+#elif BOARD == SAMD20_XPLAINED_PRO\r
+# include "samd20_xplained_pro/samd20_xplained_pro.h"\r
+#elif BOARD == SAM4N_XPLAINED_PRO\r
+# include "sam4n_xplained_pro/sam4n_xplained_pro.h"\r
+#elif BOARD == MEGA1284P_XPLAINED_BC\r
+# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"\r
+#elif BOARD == UC3_L0_QT600\r
+# include "uc3_l0_qt600/uc3_l0_qt600.h"\r
+#elif BOARD == XMEGA_A3BU_XPLAINED\r
+# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"\r
+#elif BOARD == XMEGA_E5_XPLAINED\r
+# include "xmega_e5_xplained/xmega_e5_xplained.h"\r
+#elif BOARD == UC3B_BOARD_CONTROLLER\r
+# include "uc3b_board_controller/uc3b_board_controller.h"\r
+#elif BOARD == RZ600\r
+# include "rz600/rz600.h"\r
+#elif BOARD == STK600_RCUC3A0\r
+# include "stk600/rcuc3a0/stk600_rcuc3a0.h"\r
+#elif BOARD == ATXMEGA128A1_QT600\r
+# include "atxmega128a1_qt600/atxmega128a1_qt600.h"\r
+#elif BOARD == STK600_RCUC3L3\r
+# include "stk600/rcuc3l3/stk600_rcuc3l3.h"\r
+#elif BOARD == SAM4S_XPLAINED_PRO\r
+# include "sam4s_xplained_pro/sam4s_xplained_pro.h"\r
+#elif BOARD == SAM4L_XPLAINED_PRO\r
+# include "sam4l_xplained_pro/sam4l_xplained_pro.h"\r
+#elif BOARD == SAM4L8_XPLAINED_PRO\r
+# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"\r
+#elif BOARD == SIMULATOR_XMEGA_A1\r
+# include "simulator/xmega_a1/simulator_xmega_a1.h"\r
+#elif BOARD == XMEGA_C3_XPLAINED\r
+# include "xmega_c3_xplained/xmega_c3_xplained.h"\r
+#elif BOARD == XMEGA_RF233_ZIGBIT\r
+# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"\r
+#elif BOARD == XMEGA_A3_REB_CBB\r
+# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"\r
+#elif BOARD == ATMEGARFX_RCB\r
+# include "atmegarfx_rcb/atmegarfx_rcb.h"\r
+#elif BOARD == XMEGA_RF212B_ZIGBIT\r
+# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"\r
+#elif BOARD == AVR_SIMULATOR_UC3\r
+# include "avr_simulator_uc3/avr_simulator_uc3.h"\r
+#elif BOARD == USER_BOARD\r
+ // User-reserved area: #include the header file of your board here (if any).\r
+# include "user_board.h"\r
+#elif BOARD == DUMMY_BOARD\r
+# include "dummy/dummy_board.h"\r
+#else\r
+# error No known Atmel board defined\r
+#endif\r
+\r
+#if (defined EXT_BOARD)\r
+# if EXT_BOARD == MC300\r
+# include "mc300/mc300.h"\r
+# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)\r
+# include "sensors_xplained/sensors_xplained.h"\r
+# elif EXT_BOARD == RZ600_AT86RF231\r
+# include "at86rf231/at86rf231.h"\r
+# elif EXT_BOARD == RZ600_AT86RF230B\r
+# include "at86rf230b/at86rf230b.h"\r
+# elif EXT_BOARD == RZ600_AT86RF212\r
+# include "at86rf212/at86rf212.h"\r
+# elif EXT_BOARD == SECURITY_XPLAINED\r
+# include "security_xplained.h"\r
+# elif EXT_BOARD == USER_EXT_BOARD\r
+ // User-reserved area: #include the header file of your extension board here\r
+ // (if any).\r
+# endif\r
+#endif\r
+\r
+\r
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+\r
+#endif // #ifdef __AVR32_ABI_COMPILER__\r
+#else\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _BOARD_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief USART Serial wrapper service for the SAM D20 devices.\r
+ *\r
+ * Copyright (c) 2009-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef _USART_SERIAL_H_\r
+#define _USART_SERIAL_H_\r
+\r
+#include "compiler.h"\r
+#ifndef SAMD20\r
+# include "sysclk.h"\r
+#endif\r
+#include "status_codes.h"\r
+#include "usart.h"\r
+\r
+/*! \name Serial Management Configuration\r
+ */\r
+//! @{\r
+//#include "conf_usart_serial.h"\r
+//! @}\r
+\r
+typedef Sercom * usart_inst_t;\r
+\r
+struct usart_module usart;\r
+\r
+/*! \brief Initializes the Usart in master mode.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param options Options needed to set up RS232 communication (see \ref usart_serial_options_t).\r
+ *\r
+ * \retval true if the initialization was successful\r
+ * \retval false if initialization failed (error in baud rate calculation)\r
+ */\r
+static inline bool usart_serial_init(struct usart_module *const module,\r
+ usart_inst_t const hw, const struct usart_config *const config)\r
+{\r
+ if (usart_init(module, hw, config) == STATUS_OK) {\r
+ return true;\r
+ }\r
+ else {\r
+ return false;\r
+ }\r
+}\r
+\r
+/*! \brief Sends a character with the USART.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param c Character to write.\r
+ *\r
+ * \return Status code\r
+ */\r
+static inline enum status_code usart_serial_putchar(struct usart_module *const module,\r
+ uint8_t c)\r
+{\r
+ return usart_write_wait(module, c);\r
+}\r
+/*! \brief Waits until a character is received, and returns it.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param data Data to read\r
+ *\r
+ */\r
+static inline void usart_serial_getchar(struct usart_module *const module,\r
+ uint8_t *c)\r
+{\r
+ uint16_t temp;\r
+\r
+ usart_read_wait(module, &temp);\r
+\r
+ *c = temp;\r
+}\r
+\r
+/**\r
+ * \brief Send a sequence of bytes to USART device\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param data Data buffer to read\r
+ * \param len Length of data\r
+ *\r
+ */\r
+static inline enum status_code usart_serial_write_packet(struct usart_module *const module,\r
+ const uint8_t *tx_data, uint16_t length)\r
+{\r
+ return usart_write_buffer_wait(module, tx_data, length);\r
+}\r
+\r
+/**\r
+ * \brief Receive a sequence of bytes from USART device\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param data Data buffer to write\r
+ * \param len Length of data\r
+ *\r
+ */\r
+static inline enum status_code usart_serial_read_packet(struct usart_module *const module,\r
+ uint8_t *rx_data, uint16_t length)\r
+{\r
+ return usart_read_buffer_wait(module, rx_data, length);\r
+}\r
+\r
+#endif // _USART_SERIAL_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Serial Mode management\r
+ *\r
+ * Copyright (c) 2010 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SERIAL_H_INCLUDED\r
+#define SERIAL_H_INCLUDED\r
+\r
+#include <parts.h>\r
+#include "status_codes.h"\r
+\r
+/**\r
+ * \typedef usart_if\r
+ *\r
+ * This type can be used independently to refer to USART module for the\r
+ * architecture used. It refers to the correct type definition for the\r
+ * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3.\r
+ */\r
+\r
+#if XMEGA\r
+# include "xmega_usart/usart_serial.h"\r
+#elif MEGA_RF\r
+# include "megarf_usart/usart_serial.h"\r
+#elif UC3\r
+# include "uc3_usart/usart_serial.h"\r
+#elif SAMD20\r
+#include "sam0_usart/usart_serial.h"\r
+#elif SAM\r
+# include "sam_uart/uart_serial.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ *\r
+ * \defgroup serial_group Serial Interface (Serial)\r
+ *\r
+ * See \ref serial_quickstart.\r
+ *\r
+ * This is the common API for serial interface. Additional features are available\r
+ * in the documentation of the specific modules.\r
+ *\r
+ * \section serial_group_platform Platform Dependencies\r
+ *\r
+ * The serial API is partially chip- or platform-specific. While all\r
+ * platforms provide mostly the same functionality, there are some\r
+ * variations around how different bus types and clock tree structures\r
+ * are handled.\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behaviour. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - usart_serial_init()\r
+ * - usart_serial_putchar()\r
+ * - usart_serial_getchar()\r
+ * - usart_serial_write_packet()\r
+ * - usart_serial_read_packet()\r
+ *\r
+ *\r
+ * @{\r
+ */\r
+ \r
+//! @}\r
+\r
+/**\r
+ * \page serial_quickstart Quick start guide for Serial Interface service\r
+ *\r
+ * This is the quick start guide for the \ref serial_group "Serial Interface module", with\r
+ * step-by-step instructions on how to configure and use the serial in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \section serial_use_cases Serial use cases\r
+ * - \ref serial_basic_use_case\r
+ * - \subpage serial_use_case_1\r
+ *\r
+ * \section serial_basic_use_case Basic use case - transmit a character\r
+ * In this use case, the serial module is configured for:\r
+ * - Using USARTD0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * The use case waits for a received character on the configured USART and\r
+ * echoes the character back to the same USART.\r
+ *\r
+ * \section serial_basic_use_case_setup Setup steps\r
+ *\r
+ * \subsection serial_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclk)"\r
+ *\r
+ * \subsection serial_basic_use_case_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_serial.h file, but it can also be added to your main application file.)\r
+ * \code\r
+ * #define USART_SERIAL &USARTD0\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH USART_CHSIZE_8BIT_gc\r
+ * #define USART_SERIAL_PARITY USART_PMODE_DISABLED_gc\r
+ * #define USART_SERIAL_STOP_BIT false\r
+ * \endcode\r
+ *\r
+ * A variable for the received byte must be added:\r
+ * \code uint8_t received_byte; \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * static usart_serial_options_t usart_options = {\r
+ * .baudrate = USART_SERIAL_BAUDRATE,\r
+ * .charlength = USART_SERIAL_CHAR_LENGTH,\r
+ * .paritytype = USART_SERIAL_PARITY,\r
+ * .stopbits = USART_SERIAL_STOP_BIT\r
+ * };\r
+ *\r
+ * usart_serial_init(USART_SERIAL, &usart_options);\r
+ * \endcode\r
+ *\r
+ * \subsection serial_basic_use_case_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * - \code sysclk_init(); \endcode\r
+ * -# Create serial USART options struct:\r
+ * - \code\r
+ * static usart_serial_options_t usart_options = {\r
+ * .baudrate = USART_SERIAL_BAUDRATE,\r
+ * .charlength = USART_SERIAL_CHAR_LENGTH,\r
+ * .paritytype = USART_SERIAL_PARITY,\r
+ * .stopbits = USART_SERIAL_STOP_BIT\r
+ * };\r
+ * \endcode\r
+ * -# Initialize the serial service:\r
+ * - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode\r
+ *\r
+ * \section serial_basic_use_case_usage Usage steps\r
+ *\r
+ * \subsection serial_basic_use_case_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * usart_serial_getchar(USART_SERIAL, &received_byte);\r
+ * usart_serial_putchar(USART_SERIAL, received_byte);\r
+ * \endcode\r
+ *\r
+ * \subsection serial_basic_use_case_usage_flow Workflow\r
+ * -# Wait for reception of a character:\r
+ * - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode\r
+ * -# Echo the character back:\r
+ * - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode\r
+ */\r
+\r
+/**\r
+ * \page serial_use_case_1 Advanced use case - Send a packet of serial data\r
+ *\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USARTD0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * The use case sends a string of text through the USART.\r
+ *\r
+ * \section serial_use_case_1_setup Setup steps\r
+ *\r
+ * \subsection serial_use_case_1_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclk)"\r
+ *\r
+ * \subsection serial_use_case_1_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_serial.h file, but it can also be added to your main application file.):\r
+ * \code\r
+ * #define USART_SERIAL &USARTD0\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH USART_CHSIZE_8BIT_gc\r
+ * #define USART_SERIAL_PARITY USART_PMODE_DISABLED_gc\r
+ * #define USART_SERIAL_STOP_BIT false\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * static usart_serial_options_t usart_options = {\r
+ * .baudrate = USART_SERIAL_BAUDRATE,\r
+ * .charlength = USART_SERIAL_CHAR_LENGTH,\r
+ * .paritytype = USART_SERIAL_PARITY,\r
+ * .stopbits = USART_SERIAL_STOP_BIT\r
+ * };\r
+ *\r
+ * usart_serial_init(USART_SERIAL, &usart_options);\r
+ * \endcode\r
+ *\r
+ * \subsection serial_use_case_1_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * - \code sysclk_init(); \endcode\r
+ * -# Create USART options struct:\r
+ * - \code\r
+ * static usart_serial_options_t usart_options = {\r
+ * .baudrate = USART_SERIAL_BAUDRATE,\r
+ * .charlength = USART_SERIAL_CHAR_LENGTH,\r
+ * .paritytype = USART_SERIAL_PARITY,\r
+ * .stopbits = USART_SERIAL_STOP_BIT\r
+ * };\r
+ * \endcode\r
+ * -# Initialize in RS232 mode:\r
+ * - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode\r
+ *\r
+ * \section serial_use_case_1_usage Usage steps\r
+ *\r
+ * \subsection serial_use_case_1_usage_code Example code\r
+ * Add to, e.g., main loop in application C-file:\r
+ * \code\r
+ * usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));\r
+ * \endcode\r
+ *\r
+ * \subsection serial_use_case_1_usage_flow Workflow\r
+ * -# Write a string of text to the USART:\r
+ * - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode\r
+ */\r
+\r
+#endif /* SERIAL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for 8- and 32-bit AVR\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef UTILS_INTERRUPT_H\r
+#define UTILS_INTERRUPT_H\r
+\r
+#include <parts.h>\r
+\r
+#if XMEGA || MEGA || TINY\r
+# include "interrupt/interrupt_avr8.h"\r
+#elif UC3\r
+# include "interrupt/interrupt_avr32.h"\r
+#elif SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4L || SAM4E || SAMD20 || SAM\r
+# include "interrupt/interrupt_sam_nvic.h"\r
+#else\r
+# error Unsupported device.\r
+#endif\r
+\r
+/**\r
+ * \defgroup interrupt_group Global interrupt management\r
+ *\r
+ * This is a driver for global enabling and disabling of interrupts.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \def CONFIG_INTERRUPT_FORCE_INTC\r
+ * \brief Force usage of the ASF INTC driver\r
+ *\r
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.\r
+ * This is useful to ensure compatibility across compilers and shall be used only when required\r
+ * by the application needs.\r
+ */\r
+# define CONFIG_INTERRUPT_FORCE_INTC\r
+#endif\r
+\r
+//! \name Global interrupt flags\r
+//@{\r
+/**\r
+ * \typedef irqflags_t\r
+ * \brief Type used for holding state of interrupt flag\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_enable\r
+ * \brief Enable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_disable\r
+ * \brief Disable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \fn irqflags_t cpu_irq_save(void)\r
+ * \brief Get and clear the global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_restore.\r
+ *\r
+ * \return Current state of interrupt flags.\r
+ *\r
+ * \note This function leaves interrupts disabled.\r
+ */\r
+\r
+/**\r
+ * \fn void cpu_irq_restore(irqflags_t flags)\r
+ * \brief Restore global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_save.\r
+ *\r
+ * \param flags State to set interrupt flag to.\r
+ */\r
+\r
+/**\r
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+ * \brief Check if interrupts are globally enabled in supplied flags\r
+ *\r
+ * \param flags Currents state of interrupt flags.\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_is_enabled\r
+ * \brief Check if interrupts are globally enabled\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+/**\r
+ * \ingroup interrupt_group\r
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions\r
+ */\r
+\r
+#endif /* UTILS_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "interrupt_sam_nvic.h"\r
+\r
+#if !defined(__DOXYGEN__)\r
+/* Deprecated - global flag to determine the global interrupt state. Required by\r
+ * QTouch library, however new applications should use cpu_irq_is_enabled()\r
+ * which probes the true global interrupt state from the CPU special registers.\r
+ */\r
+volatile bool g_interrupt_enabled = true;\r
+#endif\r
+\r
+void cpu_irq_enter_critical(void)\r
+{\r
+ if (cpu_irq_critical_section_counter == 0) {\r
+ if (cpu_irq_is_enabled()) {\r
+ cpu_irq_disable();\r
+ cpu_irq_prev_interrupt_state = true;\r
+ } else {\r
+ /* Make sure the to save the prev state as false */\r
+ cpu_irq_prev_interrupt_state = false;\r
+ }\r
+\r
+ }\r
+\r
+ cpu_irq_critical_section_counter++;\r
+}\r
+\r
+void cpu_irq_leave_critical(void)\r
+{\r
+ /* Check if the user is trying to leave a critical section when not in a critical section */\r
+ Assert(cpu_irq_critical_section_counter > 0);\r
+\r
+ cpu_irq_critical_section_counter--;\r
+\r
+ /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag\r
+ was enabled when entering critical state */\r
+ if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {\r
+ cpu_irq_enable();\r
+ }\r
+}\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_INTERRUPT_INTERRUPT_H\r
+#define UTILS_INTERRUPT_INTERRUPT_H\r
+\r
+#include <compiler.h>\r
+#include <parts.h>\r
+\r
+/**\r
+ * \weakgroup interrupt_group\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Interrupt Service Routine definition\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Define service routine\r
+ *\r
+ * \note For NVIC devices the interrupt service routines are predefined to\r
+ * add to vector table in binary generation, so there is no service\r
+ * register at run time. The routine collections are in exceptions.h.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * ISR(foo_irq_handler)\r
+ * {\r
+ * // Function definition\r
+ * ...\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \param func Name for the function.\r
+ */\r
+# define ISR(func) \\r
+ void func (void)\r
+\r
+/**\r
+ * \brief Initialize interrupt vectors\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to initialize them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * This must be called prior to \ref irq_register_handler.\r
+ */\r
+# define irq_initialize_vectors() \\r
+ do { \\r
+ } while(0)\r
+\r
+/**\r
+ * \brief Register handler for interrupt\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to register them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * irq_initialize_vectors();\r
+ * irq_register_handler(foo_irq_handler);\r
+ * \endcode\r
+ *\r
+ * \note The function \a func must be defined with the \ref ISR macro.\r
+ * \note The functions prototypes can be found in the device exception header\r
+ * files (exceptions.h).\r
+ */\r
+# define irq_register_handler(int_num, int_prio) \\r
+ NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \\r
+ NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \\r
+ NVIC_EnableIRQ( (IRQn_Type)int_num); \\r
+\r
+//@}\r
+\r
+# define cpu_irq_enable() \\r
+ do { \\r
+ g_interrupt_enabled = true; \\r
+ __DMB(); \\r
+ __enable_irq(); \\r
+ } while (0)\r
+# define cpu_irq_disable() \\r
+ do { \\r
+ __disable_irq(); \\r
+ __DMB(); \\r
+ g_interrupt_enabled = false; \\r
+ } while (0)\r
+\r
+typedef uint32_t irqflags_t;\r
+\r
+#if !defined(__DOXYGEN__)\r
+extern volatile bool g_interrupt_enabled;\r
+#endif\r
+\r
+#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)\r
+\r
+static volatile uint32_t cpu_irq_critical_section_counter;\r
+static volatile bool cpu_irq_prev_interrupt_state;\r
+\r
+static inline irqflags_t cpu_irq_save(void)\r
+{\r
+ irqflags_t flags = cpu_irq_is_enabled();\r
+ cpu_irq_disable();\r
+ return flags;\r
+}\r
+\r
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+{\r
+ return (flags);\r
+}\r
+\r
+static inline void cpu_irq_restore(irqflags_t flags)\r
+{\r
+ if (cpu_irq_is_enabled_flags(flags))\r
+ cpu_irq_enable();\r
+}\r
+\r
+void cpu_irq_enter_critical(void);\r
+void cpu_irq_leave_critical(void);\r
+\r
+/**\r
+ * \weakgroup interrupt_deprecated_group\r
+ * @{\r
+ */\r
+\r
+#define Enable_global_interrupt() cpu_irq_enable()\r
+#define Disable_global_interrupt() cpu_irq_disable()\r
+#define Is_global_interrupt_enabled() cpu_irq_is_enabled()\r
+\r
+//@}\r
+\r
+//@}\r
+\r
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Atmel part identification macros\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ATMEL_PARTS_H\r
+#define ATMEL_PARTS_H\r
+\r
+/**\r
+ * \defgroup part_macros_group Atmel part identification macros\r
+ *\r
+ * This collection of macros identify which series and families that the various\r
+ * Atmel parts belong to. These can be used to select part-dependent sections of\r
+ * code at compile time.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Convenience macros for part checking\r
+ * @{\r
+ */\r
+/* ! Check GCC and IAR part definition for 8-bit AVR */\r
+#define AVR8_PART_IS_DEFINED(part) \\r
+ (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))\r
+\r
+/* ! Check GCC and IAR part definition for 32-bit AVR */\r
+#define AVR32_PART_IS_DEFINED(part) \\r
+ (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))\r
+\r
+/* ! Check GCC and IAR part definition for SAM */\r
+#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup uc3_part_macros_group AVR UC3 parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name AVR UC3 A series\r
+ * @{\r
+ */\r
+#define UC3A0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A0128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A0256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A0512) \\r
+ )\r
+\r
+#define UC3A1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A1128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A1256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A1512) \\r
+ )\r
+\r
+#define UC3A3 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A364) || \\r
+ AVR32_PART_IS_DEFINED(UC3A364S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3128S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3256S) \\r
+ )\r
+\r
+#define UC3A4 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A464) || \\r
+ AVR32_PART_IS_DEFINED(UC3A464S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4128S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4256S) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 B series\r
+ * @{\r
+ */\r
+#define UC3B0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3B064) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0128) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0256) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0512) \\r
+ )\r
+\r
+#define UC3B1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3B164) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1128) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1256) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1512) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 C series\r
+ * @{\r
+ */\r
+#define UC3C0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C064C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0512C) \\r
+ )\r
+\r
+#define UC3C1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C164C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1512C) \\r
+ )\r
+\r
+#define UC3C2 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C264C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2512C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 D series\r
+ * @{\r
+ */\r
+#define UC3D3 ( \\r
+ AVR32_PART_IS_DEFINED(UC64D3) || \\r
+ AVR32_PART_IS_DEFINED(UC128D3) \\r
+ )\r
+\r
+#define UC3D4 ( \\r
+ AVR32_PART_IS_DEFINED(UC64D4) || \\r
+ AVR32_PART_IS_DEFINED(UC128D4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 L series\r
+ * @{\r
+ */\r
+#define UC3L0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L016) || \\r
+ AVR32_PART_IS_DEFINED(UC3L032) || \\r
+ AVR32_PART_IS_DEFINED(UC3L064) \\r
+ )\r
+\r
+#define UC3L0128 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L0128) \\r
+ )\r
+\r
+#define UC3L0256 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L0256) \\r
+ )\r
+\r
+#define UC3L3 ( \\r
+ AVR32_PART_IS_DEFINED(UC64L3U) || \\r
+ AVR32_PART_IS_DEFINED(UC128L3U) || \\r
+ AVR32_PART_IS_DEFINED(UC256L3U) \\r
+ )\r
+\r
+#define UC3L4 ( \\r
+ AVR32_PART_IS_DEFINED(UC64L4U) || \\r
+ AVR32_PART_IS_DEFINED(UC128L4U) || \\r
+ AVR32_PART_IS_DEFINED(UC256L4U) \\r
+ )\r
+\r
+#define UC3L3_L4 (UC3L3 || UC3L4)\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 families\r
+ * @{\r
+ */\r
+/** AVR UC3 A family */\r
+#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)\r
+\r
+/** AVR UC3 B family */\r
+#define UC3B (UC3B0 || UC3B1)\r
+\r
+/** AVR UC3 C family */\r
+#define UC3C (UC3C0 || UC3C1 || UC3C2)\r
+\r
+/** AVR UC3 D family */\r
+#define UC3D (UC3D3 || UC3D4)\r
+\r
+/** AVR UC3 L family */\r
+#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)\r
+/** @} */\r
+\r
+/** AVR UC3 product line */\r
+#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup xmega_part_macros_group AVR XMEGA parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name AVR XMEGA A series\r
+ * @{\r
+ */\r
+#define XMEGA_A1 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A1) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A1) \\r
+ )\r
+\r
+#define XMEGA_A3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3) \\r
+ )\r
+\r
+#define XMEGA_A3B ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3B) \\r
+ )\r
+\r
+#define XMEGA_A4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16A4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32A4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA AU series\r
+ * @{\r
+ */\r
+#define XMEGA_A1U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A1U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A1U) \\r
+ )\r
+\r
+#define XMEGA_A3U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3U) \\r
+ )\r
+\r
+#define XMEGA_A3BU ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3BU) \\r
+ )\r
+\r
+#define XMEGA_A4U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A4U) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA B series\r
+ * @{\r
+ */\r
+#define XMEGA_B1 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64B1) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128B1) \\r
+ )\r
+\r
+#define XMEGA_B3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64B3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128B3) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA C series\r
+ * @{\r
+ */\r
+#define XMEGA_C3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega384C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64C3) \\r
+ )\r
+\r
+#define XMEGA_C4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega32C4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega16C4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA D series\r
+ * @{\r
+ */\r
+#define XMEGA_D3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega384D3) \\r
+ )\r
+\r
+#define XMEGA_D4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128D4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA E series\r
+ * @{\r
+ */\r
+#define XMEGA_E5 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega8E5) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega16E5) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32E5) \\r
+ )\r
+/** @} */\r
+\r
+\r
+/**\r
+ * \name AVR XMEGA families\r
+ * @{\r
+ */\r
+/** AVR XMEGA A family */\r
+#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)\r
+\r
+/** AVR XMEGA AU family */\r
+#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)\r
+\r
+/** AVR XMEGA B family */\r
+#define XMEGA_B (XMEGA_B1 || XMEGA_B3)\r
+\r
+/** AVR XMEGA C family */\r
+#define XMEGA_C (XMEGA_C3 || XMEGA_C4)\r
+\r
+/** AVR XMEGA D family */\r
+#define XMEGA_D (XMEGA_D3 || XMEGA_D4)\r
+\r
+/** AVR XMEGA E family */\r
+#define XMEGA_E (XMEGA_E5)\r
+/** @} */\r
+\r
+\r
+/** AVR XMEGA product line */\r
+#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup mega_part_macros_group megaAVR parts\r
+ *\r
+ * \note These megaAVR groupings are based on the groups in AVR Libc for the\r
+ * part header files. They are not names of official megaAVR device series or\r
+ * families.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name ATmegaxx0/xx1 subgroups\r
+ * @{\r
+ */\r
+#define MEGA_XX0 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega640) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1280) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2560) \\r
+ )\r
+\r
+#define MEGA_XX1 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega1281) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2561) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name megaAVR groups\r
+ * @{\r
+ */\r
+/** ATmegaxx0/xx1 group */\r
+#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)\r
+\r
+/** ATmegaxx4 group */\r
+#define MEGA_XX4 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega164A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128RFA1) \\r
+ )\r
+\r
+/** ATmegaxx4 group */\r
+#define MEGA_XX4_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega164A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284P) \\r
+ )\r
+\r
+/** ATmegaxx8 group */\r
+#define MEGA_XX8 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega48) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328P) \\r
+ )\r
+\r
+/** ATmegaxx8A/P/PA group */\r
+#define MEGA_XX8_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega48A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328P) \\r
+ )\r
+\r
+/** ATmegaxx group */\r
+#define MEGA_XX ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+\r
+/** ATmegaxxA/P/PA group */\r
+#define MEGA_XX_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+/** ATmegaxxRFA1 group */\r
+#define MEGA_RFA1 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega128RFA1) \\r
+ )\r
+\r
+/** ATmegaxxRFR2 group */\r
+#define MEGA_RFR2 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega64RFR2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128RFR2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega256RFR2) \\r
+ )\r
+\r
+\r
+/** ATmegaxxRFxx group */\r
+#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)\r
+\r
+/**\r
+ * \name ATmegaxx_un0/un1/un2 subgroups\r
+ * @{\r
+ */\r
+#define MEGA_XX_UN0 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) \\r
+ )\r
+\r
+/** ATmegaxx group without power reduction and\r
+ * And interrupt sense register.\r
+ */\r
+#define MEGA_XX_UN1 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega64) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+\r
+/** ATmegaxx group without power reduction and\r
+ * And interrupt sense register.\r
+ */\r
+#define MEGA_XX_UN2 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega169P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega169PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329PA) \\r
+ )\r
+\r
+/** Devices added to complete megaAVR offering.\r
+ * Please do not use this group symbol as it is not intended\r
+ * to be permanent: the devices should be regrouped.\r
+ */\r
+#define MEGA_UNCATEGORIZED ( \\r
+ AVR8_PART_IS_DEFINED(AT90CAN128) || \\r
+ AVR8_PART_IS_DEFINED(AT90CAN32) || \\r
+ AVR8_PART_IS_DEFINED(AT90CAN64) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM1) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM216) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM2B) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM316) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM3B) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM81) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB1286) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB1287) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB162) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB646) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB647) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB82) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284) || \\r
+ AVR8_PART_IS_DEFINED(ATmega162) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega165A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega165P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega165PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega169A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16M1) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16U2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16U4) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2564RFR2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega256RFA2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega325) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3250) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3250A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3250P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3250PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega325A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega325P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega325PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3290) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3290A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3290P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3290PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32M1) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32U2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32U4) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega645) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6450) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6450A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6450P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega645A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega645P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega649) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6490) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6490A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6490P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega649A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega649P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64M1) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64RFA2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8515) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8535) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8U2) \\r
+ )\r
+\r
+/** Unspecified group */\r
+#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \\r
+ MEGA_UNCATEGORIZED)\r
+\r
+/** @} */\r
+\r
+/** megaAVR product line */\r
+#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \\r
+ MEGA_UNSPECIFIED)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup tiny_part_macros_group tinyAVR parts\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name tinyAVR groups\r
+ * @{\r
+ */\r
+\r
+/** Devices added to complete tinyAVR offering.\r
+ * Please do not use this group symbol as it is not intended\r
+ * to be permanent: the devices should be regrouped.\r
+ */\r
+#define TINY_UNCATEGORIZED ( \\r
+ AVR8_PART_IS_DEFINED(ATtiny10) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny13) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny13A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny1634) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny167) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny20) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny2313) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny2313A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny24) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny24A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny25) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny26) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny261) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny261A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny4) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny40) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny4313) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny43U) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny44) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny44A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny45) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny461) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny461A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny48) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny5) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny828) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny84) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny84A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny85) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny861) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny861A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny87) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny88) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny9) \\r
+ )\r
+\r
+/** @} */\r
+\r
+/** tinyAVR product line */\r
+#define TINY (TINY_UNCATEGORIZED)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup sam_part_macros_group SAM parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name SAM3S series\r
+ * @{\r
+ */\r
+#define SAM3S1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S1A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S1B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S1C) \\r
+ )\r
+\r
+#define SAM3S2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S2A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S2B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S2C) \\r
+ )\r
+\r
+#define SAM3S4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S4A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S4B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S4C) \\r
+ )\r
+\r
+#define SAM3S8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S8B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S8C) \\r
+ )\r
+\r
+#define SAM3SD8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3SD8B) || \\r
+ SAM_PART_IS_DEFINED(SAM3SD8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3U series\r
+ * @{\r
+ */\r
+#define SAM3U1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U1C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U1E) \\r
+ )\r
+\r
+#define SAM3U2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U2C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U2E) \\r
+ )\r
+\r
+#define SAM3U4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U4C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U4E) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3N series\r
+ * @{\r
+ */\r
+#define SAM3N1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N1A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N1B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N1C) \\r
+ )\r
+\r
+#define SAM3N2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N2A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N2B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N2C) \\r
+ )\r
+\r
+#define SAM3N4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N4A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N4B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N4C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3X series\r
+ * @{\r
+ */\r
+#define SAM3X4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3X4C) || \\r
+ SAM_PART_IS_DEFINED(SAM3X4E) \\r
+ )\r
+\r
+#define SAM3X8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3X8C) || \\r
+ SAM_PART_IS_DEFINED(SAM3X8E) || \\r
+ SAM_PART_IS_DEFINED(SAM3X8H) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3A series\r
+ * @{\r
+ */\r
+#define SAM3A4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3A4C) \\r
+ )\r
+\r
+#define SAM3A8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3A8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4S series\r
+ * @{\r
+ */\r
+#define SAM4S8 ( \\r
+ SAM_PART_IS_DEFINED(SAM4S8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4S8C) \\r
+ )\r
+\r
+#define SAM4S16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4S16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4S16C) \\r
+ )\r
+\r
+#define SAM4SA16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4SA16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4SA16C) \\r
+ )\r
+\r
+#define SAM4SD16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4SD16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4SD16C) \\r
+ )\r
+\r
+#define SAM4SD32 ( \\r
+ SAM_PART_IS_DEFINED(SAM4SD32B) || \\r
+ SAM_PART_IS_DEFINED(SAM4SD32C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4L series\r
+ * @{\r
+ */\r
+#define SAM4LS ( \\r
+ SAM_PART_IS_DEFINED(SAM4LS2A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS2B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS2C) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS4A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS4B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS4C) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS8A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS8C) \\r
+ )\r
+\r
+#define SAM4LC ( \\r
+ SAM_PART_IS_DEFINED(SAM4LC2A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC2B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC2C) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC4A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC4B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC4C) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC8A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAMD20 series\r
+ * @{\r
+ */\r
+#define SAMD20J ( \\r
+ SAM_PART_IS_DEFINED(SAMD20J14) || \\r
+ SAM_PART_IS_DEFINED(SAMD20J15) || \\r
+ SAM_PART_IS_DEFINED(SAMD20J16) || \\r
+ SAM_PART_IS_DEFINED(SAMD20J17) || \\r
+ SAM_PART_IS_DEFINED(SAMD20J18) \\r
+ )\r
+\r
+#define SAMD20G ( \\r
+ SAM_PART_IS_DEFINED(SAMD20G14) || \\r
+ SAM_PART_IS_DEFINED(SAMD20G15) || \\r
+ SAM_PART_IS_DEFINED(SAMD20G16) || \\r
+ SAM_PART_IS_DEFINED(SAMD20G17) || \\r
+ SAM_PART_IS_DEFINED(SAMD20G18) \\r
+ )\r
+\r
+#define SAMD20E ( \\r
+ SAM_PART_IS_DEFINED(SAMD20E14) || \\r
+ SAM_PART_IS_DEFINED(SAMD20E15) || \\r
+ SAM_PART_IS_DEFINED(SAMD20E16) || \\r
+ SAM_PART_IS_DEFINED(SAMD20E17) || \\r
+ SAM_PART_IS_DEFINED(SAMD20E18) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4E series\r
+ * @{\r
+ */\r
+#define SAM4E8 ( \\r
+ SAM_PART_IS_DEFINED(SAM4E8E) \\r
+ )\r
+\r
+#define SAM4E16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4E16E) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4N series\r
+ * @{\r
+ */\r
+#define SAM4N8 ( \\r
+ SAM_PART_IS_DEFINED(SAM4N8A) || \\r
+ SAM_PART_IS_DEFINED(SAM4N8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4N8C) \\r
+ )\r
+\r
+#define SAM4N16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4N16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4N16C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM families\r
+ * @{\r
+ */\r
+/** SAM3S Family */\r
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)\r
+\r
+/** SAM3U Family */\r
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)\r
+\r
+/** SAM3N Family */\r
+#define SAM3N (SAM3N1 || SAM3N2 || SAM3N4)\r
+\r
+/** SAM3XA Family */\r
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)\r
+\r
+/** SAM4S Family */\r
+#define SAM4S (SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)\r
+\r
+/** SAM4L Family */\r
+#define SAM4L (SAM4LS || SAM4LC)\r
+\r
+/** SAMD20 Family */\r
+#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)\r
+/** @} */\r
+\r
+/** SAM4E Family */\r
+#define SAM4E (SAM4E8 || SAM4E16)\r
+\r
+/** SAM4N Family */\r
+#define SAM4N (SAM4N8 || SAM4N16)\r
+\r
+/** @} */\r
+\r
+/** SAM product line */\r
+#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || SAMD20 || SAM4N)\r
+\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+#endif /* ATMEL_PARTS_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Xplained Pro board initialization\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <compiler.h>\r
+#include <board.h>\r
+#include <conf_board.h>\r
+#include <port.h>\r
+\r
+#if defined(__GNUC__)\r
+void board_init(void) WEAK __attribute__((alias("system_board_init")));\r
+#elif defined(__ICCARM__)\r
+void board_init(void);\r
+# pragma weak board_init=system_board_init\r
+#endif\r
+\r
+void system_board_init(void)\r
+{\r
+ struct port_config pin_conf;\r
+ port_get_config_defaults(&pin_conf);\r
+\r
+ /* Configure LEDs as outputs, turn them off */\r
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT;\r
+ port_pin_set_config(LED_0_PIN, &pin_conf);\r
+ port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);\r
+\r
+ /* Set buttons as inputs */\r
+ pin_conf.direction = PORT_PIN_DIR_INPUT;\r
+ pin_conf.input_pull = PORT_PIN_PULL_UP;\r
+ port_pin_set_config(BUTTON_0_PIN, &pin_conf);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Xplained Pro board definition\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SAMD20_XPLAINED_PRO_H_INCLUDED\r
+#define SAMD20_XPLAINED_PRO_H_INCLUDED\r
+\r
+#include <conf_board.h>\r
+#include <compiler.h>\r
+\r
+/**\r
+ * \ingroup group_common_boards\r
+ * \defgroup samd20_xplained_pro_group SAM D20 Xplained Pro board\r
+ *\r
+ * @{\r
+ */\r
+\r
+void system_board_init(void);\r
+\r
+/**\r
+ * \defgroup samd20_xplained_pro_features_group Features\r
+ *\r
+ * Symbols that describe features and capabilities of the board.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/** Name string macro */\r
+#define BOARD_NAME "SAMD20_XPLAINED_PRO"\r
+\r
+/** \name Resonator definitions\r
+ * @{ */\r
+#define BOARD_FREQ_SLCK_XTAL (32768U)\r
+#define BOARD_FREQ_SLCK_BYPASS (32768U)\r
+#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */\r
+#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */\r
+#define BOARD_MCK CHIP_FREQ_CPU_MAX\r
+#define BOARD_OSC_STARTUP_US 15625\r
+/** @} */\r
+\r
+/** \name LED0 definitions\r
+ * @{ */\r
+#define LED0_PIN PIN_PA14\r
+#define LED0_ACTIVE false\r
+#define LED0_INACTIVE !LED0_ACTIVE\r
+/** @} */\r
+\r
+/** \name SW0 definitions\r
+ * @{ */\r
+#define SW0_PIN PIN_PA15\r
+#define SW0_ACTIVE false\r
+#define SW0_INACTIVE !SW0_ACTIVE\r
+#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15\r
+#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15\r
+#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15\r
+#define SW0_EIC_LINE 15\r
+/** @} */\r
+\r
+/**\r
+ * \name LED #0 definitions\r
+ *\r
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro\r
+ * boards.\r
+ *\r
+ * @{ */\r
+#define LED_0_NAME "LED0 (yellow)"\r
+#define LED_0_PIN LED0_PIN\r
+#define LED_0_ACTIVE LED0_ACTIVE\r
+#define LED_0_INACTIVE LED0_INACTIVE\r
+/** @} */\r
+\r
+/** Number of on-board LEDs */\r
+#define LED_COUNT 1\r
+\r
+/**\r
+ * \name Button #0 definitions\r
+ *\r
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro\r
+ * boards.\r
+ *\r
+ * @{ */\r
+#define BUTTON_0_NAME "SW0"\r
+#define BUTTON_0_PIN SW0_PIN\r
+#define BUTTON_0_ACTIVE SW0_ACTIVE\r
+#define BUTTON_0_INACTIVE SW0_INACTIVE\r
+#define BUTTON_0_EIC_PIN SW0_EIC_PIN\r
+#define BUTTON_0_EIC_MUX SW0_EIC_MUX\r
+#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX\r
+#define BUTTON_0_EIC_LINE SW0_EIC_LINE\r
+/** @} */\r
+\r
+/** Number of on-board buttons */\r
+#define BUTTON_COUNT 1\r
+\r
+/** \name Extension header #1 pin definitions\r
+ * @{\r
+ */\r
+#define EXT1_PIN_3 PIN_PB00\r
+#define EXT1_PIN_4 PIN_PB01\r
+#define EXT1_PIN_5 PIN_PB06\r
+#define EXT1_PIN_6 PIN_PB07\r
+#define EXT1_PIN_7 PIN_PB02\r
+#define EXT1_PIN_8 PIN_PB03\r
+#define EXT1_PIN_9 PIN_PB04\r
+#define EXT1_PIN_10 PIN_PB05\r
+#define EXT1_PIN_11 PIN_PA08\r
+#define EXT1_PIN_12 PIN_PA09\r
+#define EXT1_PIN_13 PIN_PB09\r
+#define EXT1_PIN_14 PIN_PB08\r
+#define EXT1_PIN_15 PIN_PA05\r
+#define EXT1_PIN_16 PIN_PA06\r
+#define EXT1_PIN_17 PIN_PA04\r
+#define EXT1_PIN_18 PIN_PA07\r
+/** @} */\r
+\r
+/** \name Extension header #1 pin definitions by function\r
+ * @{\r
+ */\r
+#define EXT1_PIN_ADC_0 EXT1_PIN_3\r
+#define EXT1_PIN_ADC_1 EXT1_PIN_4\r
+#define EXT1_PIN_GPIO_0 EXT1_PIN_5\r
+#define EXT1_PIN_GPIO_1 EXT1_PIN_6\r
+#define EXT1_PIN_PWM_0 EXT1_PIN_7\r
+#define EXT1_PIN_PWM_1 EXT1_PIN_8\r
+#define EXT1_PIN_IRQ EXT1_PIN_9\r
+#define EXT1_PIN_I2C_SDA EXT1_PIN_11\r
+#define EXT1_PIN_I2C_SCL EXT1_PIN_12\r
+#define EXT1_PIN_UART_RX EXT1_PIN_13\r
+#define EXT1_PIN_UART_TX EXT1_PIN_14\r
+#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10\r
+#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15\r
+#define EXT1_PIN_SPI_MOSI EXT1_PIN_16\r
+#define EXT1_PIN_SPI_MISO EXT1_PIN_17\r
+#define EXT1_PIN_SPI_SCK EXT1_PIN_18\r
+/** @} */\r
+\r
+/** \name Extension header #1 ADC definitions\r
+ * @{\r
+ */\r
+#define EXT1_ADC_MODULE ADC\r
+#define EXT1_ADC_0_CHANNEL 8\r
+#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8\r
+#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8\r
+#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8\r
+#define EXT1_ADC_1_CHANNEL 9\r
+#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9\r
+#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9\r
+#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9\r
+/** @} */\r
+\r
+/** \name Extension header #1 PWM definitions\r
+ * @{\r
+ */\r
+#define EXT1_PWM_MODULE TC6\r
+#define EXT1_PWM_0_CHANNEL 0\r
+#define EXT1_PWM_0_PIN PIN_PB02F_TC6_WO0\r
+#define EXT1_PWM_0_MUX MUX_PB02F_TC6_WO0\r
+#define EXT1_PWM_0_PINMUX PINMUX_PB02F_TC6_WO0\r
+#define EXT1_PWM_1_CHANNEL 1\r
+#define EXT1_PWM_1_PIN PIN_PB03F_TC6_WO1\r
+#define EXT1_PWM_1_MUX MUX_PB03F_TC6_WO1\r
+#define EXT1_PWM_1_PINMUX PINMUX_PB03F_TC6_WO1\r
+/** @} */\r
+\r
+/** \name Extension header #1 IRQ/External interrupt definitions\r
+ * @{\r
+ */\r
+#define EXT1_IRQ_MODULE EIC\r
+#define EXT1_IRQ_INPUT 4\r
+#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4\r
+#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4\r
+#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4\r
+/** @} */\r
+\r
+/** \name Extension header #1 I2C definitions\r
+ * @{\r
+ */\r
+#define EXT1_I2C_MODULE SERCOM2\r
+#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0\r
+#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1\r
+/** @} */\r
+\r
+/** \name Extension header #1 UART definitions\r
+ * @{\r
+ */\r
+#define EXT1_UART_MODULE SERCOM4\r
+#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1\r
+#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0\r
+#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1\r
+#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED\r
+#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED\r
+/** @} */\r
+\r
+/** \name Extension header #1 SPI definitions\r
+ * @{\r
+ */\r
+#define EXT1_SPI_MODULE SERCOM0\r
+#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E\r
+#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0\r
+#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1\r
+#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2\r
+#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3\r
+/** @} */\r
+\r
+/** \name Extension header #2 pin definitions\r
+ * @{\r
+ */\r
+#define EXT2_PIN_3 PIN_PA10\r
+#define EXT2_PIN_4 PIN_PA11\r
+#define EXT2_PIN_5 PIN_PA20\r
+#define EXT2_PIN_6 PIN_PA21\r
+#define EXT2_PIN_7 PIN_PA22\r
+#define EXT2_PIN_8 PIN_PA23\r
+#define EXT2_PIN_9 PIN_PB14\r
+#define EXT2_PIN_10 PIN_PB15\r
+#define EXT2_PIN_11 PIN_PA08\r
+#define EXT2_PIN_12 PIN_PA09\r
+#define EXT2_PIN_13 PIN_PB13\r
+#define EXT2_PIN_14 PIN_PB12\r
+#define EXT2_PIN_15 PIN_PA17\r
+#define EXT2_PIN_16 PIN_PA18\r
+#define EXT2_PIN_17 PIN_PA16\r
+#define EXT2_PIN_18 PIN_PA19\r
+/** @} */\r
+\r
+/** \name Extension header #2 pin definitions by function\r
+ * @{\r
+ */\r
+#define EXT2_PIN_ADC_0 EXT2_PIN_3\r
+#define EXT2_PIN_ADC_1 EXT2_PIN_4\r
+#define EXT2_PIN_GPIO_0 EXT2_PIN_5\r
+#define EXT2_PIN_GPIO_1 EXT2_PIN_6\r
+#define EXT2_PIN_PWM_0 EXT2_PIN_7\r
+#define EXT2_PIN_PWM_1 EXT2_PIN_8\r
+#define EXT2_PIN_IRQ EXT2_PIN_9\r
+#define EXT2_PIN_I2C_SDA EXT2_PIN_11\r
+#define EXT2_PIN_I2C_SCL EXT2_PIN_12\r
+#define EXT2_PIN_UART_RX EXT2_PIN_13\r
+#define EXT2_PIN_UART_TX EXT2_PIN_14\r
+#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10\r
+#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15\r
+#define EXT2_PIN_SPI_MOSI EXT2_PIN_16\r
+#define EXT2_PIN_SPI_MISO EXT2_PIN_17\r
+#define EXT2_PIN_SPI_SCK EXT2_PIN_18\r
+/** @} */\r
+\r
+/** \name Extension header #2 ADC definitions\r
+ * @{\r
+ */\r
+#define EXT2_ADC_MODULE ADC\r
+#define EXT2_ADC_0_CHANNEL 18\r
+#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18\r
+#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18\r
+#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18\r
+#define EXT2_ADC_1_CHANNEL 19\r
+#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19\r
+#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19\r
+#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19\r
+/** @} */\r
+\r
+/** \name Extension header #2 PWM definitions\r
+ * @{\r
+ */\r
+#define EXT2_PWM_MODULE TC4\r
+#define EXT2_PWM_0_CHANNEL 0\r
+#define EXT2_PWM_0_PIN PIN_PA22F_TC4_WO0\r
+#define EXT2_PWM_0_MUX MUX_PA22F_TC4_WO0\r
+#define EXT2_PWM_0_PINMUX PINMUX_PA22F_TC4_WO0\r
+#define EXT2_PWM_1_CHANNEL 1\r
+#define EXT2_PWM_1_PIN PIN_PA23F_TC4_WO1\r
+#define EXT2_PWM_1_MUX MUX_PA23F_TC4_WO1\r
+#define EXT2_PWM_1_PINMUX PINMUX_PA23F_TC4_WO1\r
+/** @} */\r
+\r
+/** \name Extension header #2 IRQ/External interrupt definitions\r
+ * @{\r
+ */\r
+#define EXT2_IRQ_MODULE EIC\r
+#define EXT2_IRQ_INPUT 14\r
+#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14\r
+#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14\r
+#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14\r
+/** @} */\r
+\r
+ /** \name Extension header #2 I2C definitions\r
+ * @{\r
+ */\r
+#define EXT2_I2C_MODULE SERCOM2\r
+#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0\r
+#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1\r
+/** @} */\r
+\r
+/** \name Extension header #2 UART definitions\r
+ * @{\r
+ */\r
+#define EXT2_UART_MODULE SERCOM4\r
+#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1\r
+#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0\r
+#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1\r
+#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED\r
+#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED\r
+/** @} */\r
+\r
+/** \name Extension header #2 SPI definitions\r
+ * @{\r
+ */\r
+#define EXT2_SPI_MODULE SERCOM1\r
+#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E\r
+#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0\r
+#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1\r
+#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2\r
+#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3\r
+/** @} */\r
+\r
+/** \name Extension header #3 pin definitions\r
+ * @{\r
+ */\r
+#define EXT3_PIN_3 PIN_PA02\r
+#define EXT3_PIN_4 PIN_PA03\r
+#define EXT3_PIN_5 PIN_PB30\r
+#define EXT3_PIN_6 PIN_PA15\r
+#define EXT3_PIN_7 PIN_PA12\r
+#define EXT3_PIN_8 PIN_PA13\r
+#define EXT3_PIN_9 PIN_PA28\r
+#define EXT3_PIN_10 PIN_PA27\r
+#define EXT3_PIN_11 PIN_PA08\r
+#define EXT3_PIN_12 PIN_PA09\r
+#define EXT3_PIN_13 PIN_PB11\r
+#define EXT3_PIN_14 PIN_PB10\r
+#define EXT3_PIN_15 PIN_PB17\r
+#define EXT3_PIN_16 PIN_PB22\r
+#define EXT3_PIN_17 PIN_PB16\r
+#define EXT3_PIN_18 PIN_PB23\r
+/** @} */\r
+\r
+/** \name Extension header #3 pin definitions by function\r
+ * @{\r
+ */\r
+#define EXT3_PIN_ADC_0 EXT3_PIN_3\r
+#define EXT3_PIN_ADC_1 EXT3_PIN_4\r
+#define EXT3_PIN_GPIO_0 EXT3_PIN_5\r
+#define EXT3_PIN_GPIO_1 EXT3_PIN_6\r
+#define EXT3_PIN_PWM_0 EXT3_PIN_7\r
+#define EXT3_PIN_PWM_1 EXT3_PIN_8\r
+#define EXT3_PIN_IRQ EXT3_PIN_9\r
+#define EXT3_PIN_I2C_SDA EXT3_PIN_11\r
+#define EXT3_PIN_I2C_SCL EXT3_PIN_12\r
+#define EXT3_PIN_UART_RX EXT3_PIN_13\r
+#define EXT3_PIN_UART_TX EXT3_PIN_14\r
+#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10\r
+#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15\r
+#define EXT3_PIN_SPI_MOSI EXT3_PIN_16\r
+#define EXT3_PIN_SPI_MISO EXT3_PIN_17\r
+#define EXT3_PIN_SPI_SCK EXT3_PIN_18\r
+/** @} */\r
+\r
+/** \name Extension header #3 ADC definitions\r
+ * @{\r
+ */\r
+#define EXT3_ADC_MODULE ADC\r
+#define EXT3_ADC_0_CHANNEL 0\r
+#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0\r
+#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0\r
+#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0\r
+#define EXT3_ADC_1_CHANNEL 1\r
+#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1\r
+#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1\r
+#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1\r
+/** @} */\r
+\r
+/** \name Extension header #3 PWM definitions\r
+ * @{\r
+ */\r
+#define EXT3_PWM_MODULE TC2\r
+#define EXT3_PWM_0_CHANNEL 0\r
+#define EXT3_PWM_0_PIN PIN_PA12E_TC2_WO0\r
+#define EXT3_PWM_0_MUX MUX_PA12E_TC2_WO0\r
+#define EXT3_PWM_0_PINMUX PINMUX_PA12E_TC2_WO0\r
+#define EXT3_PWM_1_CHANNEL 1\r
+#define EXT3_PWM_1_PIN PIN_PA13E_TC2_WO1\r
+#define EXT3_PWM_1_MUX MUX_PA13E_TC2_WO1\r
+#define EXT3_PWM_1_PINMUX PINMUX_PA13E_TC2_WO1\r
+/** @} */\r
+\r
+/** \name Extension header #3 IRQ/External interrupt definitions\r
+ * @{\r
+ */\r
+#define EXT3_IRQ_MODULE EIC\r
+#define EXT3_IRQ_INPUT 8\r
+#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8\r
+#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8\r
+#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8\r
+/** @} */\r
+\r
+/** \name Extension header #3 I2C definitions\r
+ * @{\r
+ */\r
+#define EXT3_I2C_MODULE SERCOM2\r
+#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0\r
+#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1\r
+/** @} */\r
+\r
+/** \name Extension header #3 UART definitions\r
+ * @{\r
+ */\r
+#define EXT3_UART_MODULE SERCOM4\r
+#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3\r
+#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED\r
+#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED\r
+#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2\r
+#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3\r
+/** @} */\r
+\r
+/** \name Extension header #3 SPI definitions\r
+ * @{\r
+ */\r
+#define EXT3_SPI_MODULE SERCOM5\r
+#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E\r
+#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0\r
+#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1\r
+#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2\r
+#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3\r
+/** @} */\r
+\r
+/** \name Embedded debugger GPIO interface definitions\r
+ * @{\r
+ */\r
+#define EDBG_GPIO0_PIN PIN_PA27\r
+#define EDBG_GPIO1_PIN PIN_PA28\r
+#define EDBG_GPIO2_PIN PIN_PA20\r
+#define EDBG_GPIO3_PIN PIN_PA21\r
+/** @} */\r
+\r
+/** \name Embedded debugger USART interface definitions\r
+ * @{\r
+ */\r
+#define EDBG_UART_MODULE -1 /* Not available on this board */\r
+#define EDBG_UART_RX_PIN -1 /* Not available on this board */\r
+#define EDBG_UART_RX_MUX -1 /* Not available on this board */\r
+#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */\r
+#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */\r
+#define EDBG_UART_TX_PIN -1 /* Not available on this board */\r
+#define EDBG_UART_TX_MUX -1 /* Not available on this board */\r
+#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */\r
+#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */\r
+/** @} */\r
+\r
+/** \name Embedded debugger I2C interface definitions\r
+ * @{\r
+ */\r
+#define EDBG_I2C_MODULE SERCOM2\r
+#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0\r
+#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1\r
+/** @} */\r
+\r
+/** \name Embedded debugger SPI interface definitions\r
+ * @{\r
+ */\r
+#define EDBG_SPI_MODULE SERCOM5\r
+#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E\r
+#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0\r
+#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1\r
+#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2\r
+#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3\r
+/** @} */\r
+\r
+/** \name Embedded debugger CDC Gateway USART interface definitions\r
+ * @{\r
+ */\r
+#define EDBG_CDC_MODULE SERCOM3\r
+#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3\r
+#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_UNUSED\r
+#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_UNUSED\r
+#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_PA24C_SERCOM3_PAD2\r
+#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_PA25C_SERCOM3_PAD3\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+#endif /* SAMD20_XPLAINED_PRO_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 GPIO Port Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include <port.h>\r
+\r
+/**\r
+ * \brief Writes a Port pin configuration to the hardware module.\r
+ *\r
+ * Writes out a given configuration of a Port pin configuration to the hardware\r
+ * module.\r
+ *\r
+ * \note If the pin direction is set as an output, the pull-up/pull-down input\r
+ * configuration setting is ignored.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to configure.\r
+ * \param[in] config Configuration settings for the pin.\r
+ */\r
+void port_pin_set_config(\r
+ const uint8_t gpio_pin,\r
+ const struct port_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(config);\r
+\r
+ struct system_pinmux_config pinmux_config;\r
+ system_pinmux_get_config_defaults(&pinmux_config);\r
+\r
+ pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;\r
+ pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;\r
+ pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;\r
+\r
+ system_pinmux_pin_set_config(gpio_pin, &pinmux_config);\r
+}\r
+\r
+/**\r
+ * \brief Writes a Port group configuration group to the hardware module.\r
+ *\r
+ * Writes out a given configuration of a Port group configuration to the\r
+ * hardware module.\r
+ *\r
+ * \note If the pin direction is set as an output, the pull-up/pull-down input\r
+ * configuration setting is ignored.\r
+ *\r
+ * \param[out] port Base of the PORT module to write to.\r
+ * \param[in] mask Mask of the port pin(s) to configure.\r
+ * \param[in] config Configuration settings for the pin group.\r
+ */\r
+void port_group_set_config(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const struct port_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(port);\r
+ Assert(config);\r
+\r
+ struct system_pinmux_config pinmux_config;\r
+ system_pinmux_get_config_defaults(&pinmux_config);\r
+\r
+ pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;\r
+ pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;\r
+ pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;\r
+\r
+ system_pinmux_group_set_config(port, mask, &pinmux_config);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 GPIO Port Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef PORT_H_INCLUDED\r
+#define PORT_H_INCLUDED\r
+\r
+/**\r
+ * \defgroup asfdoc_samd20_port_group SAM D20 Port Driver (PORT)\r
+ *\r
+ * This driver for SAM D20 devices provides an interface for the configuration\r
+ * and management of the device's General Purpose Input/Output (GPIO) pin\r
+ * functionality, for manual pin state reading and writing.\r
+ *\r
+ * The following peripherals are used by this module:\r
+ *\r
+ * - PORT (GPIO Management)\r
+ *\r
+ * The outline of this documentation is as follows:\r
+ * - \ref asfdoc_samd20_port_prerequisites\r
+ * - \ref asfdoc_samd20_port_module_overview\r
+ * - \ref asfdoc_samd20_port_special_considerations\r
+ * - \ref asfdoc_samd20_port_extra_info\r
+ * - \ref asfdoc_samd20_port_examples\r
+ * - \ref asfdoc_samd20_port_api_overview\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_port_prerequisites Prerequisites\r
+ *\r
+ * There are no prerequisites for this module.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_port_module_overview Module Overview\r
+ *\r
+ * The device GPIO (PORT) module provides an interface between the user\r
+ * application logic and external hardware peripherals, when general pin state\r
+ * manipulation is required. This driver provides an easy-to-use interface to\r
+ * the physical pin input samplers and output drivers, so that pins can be read\r
+ * from or written to for general purpose external hardware control.\r
+ *\r
+ * \subsection asfdoc_samd20_port_module_overview_pin_numbering Physical and Logical GPIO Pins\r
+ * SAM D20 devices use two naming conventions for the I/O pins in the device; one\r
+ * physical, and one logical. Each physical pin on a device package is assigned\r
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a\r
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the\r
+ * former is used to map physical pins to their physical internal device module\r
+ * counterparts, for simplicity the design of this driver uses the logical GPIO\r
+ * numbers instead.\r
+ *\r
+ * \subsection asfdoc_samd20_port_module_overview_physical Physical Connection\r
+ *\r
+ * \ref asfdoc_samd20_port_module_int_connections "The diagram below" shows how\r
+ * this module is interconnected within the device.\r
+ *\r
+ * \anchor asfdoc_samd20_port_module_int_connections\r
+ * \dot\r
+ * digraph overview {\r
+ * node [label="Port Pad" shape=square] pad;\r
+ *\r
+ * subgraph driver {\r
+ * node [label="Peripheral Mux" shape=trapezium] pinmux;\r
+ * node [label="GPIO Module" shape=ellipse] gpio;\r
+ * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;\r
+ * }\r
+ *\r
+ * pinmux -> gpio;\r
+ * pad -> pinmux;\r
+ * pinmux -> peripherals;\r
+ * }\r
+ * \enddot\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_port_special_considerations Special Considerations\r
+ *\r
+ * The SAM D20 port pin input sampler can be disabled when the pin is configured\r
+ * in pure output mode to save power; reading the pin state of a pin configured\r
+ * in output-only mode will read the logical output state that was last set.\r
+ *\r
+ * \section asfdoc_samd20_port_extra_info Extra Information\r
+ *\r
+ * For extra information see \ref asfdoc_samd20_port_extra. This includes:\r
+ * - \ref asfdoc_samd20_port_extra_acronyms\r
+ * - \ref asfdoc_samd20_port_extra_dependencies\r
+ * - \ref asfdoc_samd20_port_extra_errata\r
+ * - \ref asfdoc_samd20_port_extra_history\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_port_examples Examples\r
+ *\r
+ * For a list of examples related to this driver, see\r
+ * \ref asfdoc_samd20_port_exqsg.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_port_api_overview API Overview\r
+ * @{\r
+ */\r
+\r
+#include <compiler.h>\r
+#include <pinmux.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** \name PORT Alias Macros\r
+ * @{\r
+ */\r
+\r
+/** Convenience definition for GPIO module group A on the device (if\r
+ * available). */\r
+#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)\r
+# define PORTA PORT->Group[0]\r
+#endif\r
+\r
+#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)\r
+/** Convenience definition for GPIO module group B on the device (if\r
+ * available). */\r
+# define PORTB PORT->Group[1]\r
+#endif\r
+\r
+#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)\r
+/** Convenience definition for GPIO module group C on the device (if\r
+ * available). */\r
+# define PORTC PORT->Group[2]\r
+#endif\r
+\r
+#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)\r
+/** Convenience definition for GPIO module group D on the device (if\r
+ * available). */\r
+# define PORTD PORT->Group[3]\r
+#endif\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \brief Port pin direction configuration enum.\r
+ *\r
+ * Enum for the possible pin direction settings of the port pin configuration\r
+ * structure, to indicate the direction the pin should use.\r
+ */\r
+enum port_pin_dir {\r
+ /** The pin's input buffer should be enabled, so that the pin state can\r
+ * be read. */\r
+ PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT,\r
+ /** The pin's output buffer should be enabled, so that the pin state can\r
+ * be set. */\r
+ PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT,\r
+ /** The pin's output and input buffers should be enabled, so that the pin\r
+ * state can be set and read back. */\r
+ PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,\r
+};\r
+\r
+/**\r
+ * \brief Port pin input pull configuration enum.\r
+ *\r
+ * Enum for the possible pin pull settings of the port pin configuration\r
+ * structure, to indicate the type of logic level pull the pin should use.\r
+ */\r
+enum port_pin_pull {\r
+ /** No logical pull should be applied to the pin. */\r
+ PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,\r
+ /** Pin should be pulled up when idle. */\r
+ PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,\r
+ /** Pin should be pulled down when idle. */\r
+ PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,\r
+};\r
+\r
+/**\r
+ * \brief Port pin configuration structure.\r
+ *\r
+ * Configuration structure for a port pin instance. This structure should be\r
+ * initialized by the \ref port_get_config_defaults() function before being\r
+ * modified by the user application.\r
+ */\r
+struct port_config {\r
+ /** Port buffer input/output direction. */\r
+ enum port_pin_dir direction;\r
+\r
+ /** Port pull-up/pull-down for input pins. */\r
+ enum port_pin_pull input_pull;\r
+};\r
+\r
+/** \name State reading/writing (physical group orientated)\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.\r
+ *\r
+ * Retrieves the PORT module group instance associated with a given logical\r
+ * GPIO pin number.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to convert.\r
+ *\r
+ * \return Base address of the associated PORT module.\r
+ */\r
+static inline PortGroup* port_get_group_from_gpio_pin(\r
+ const uint8_t gpio_pin)\r
+{\r
+ return system_pinmux_get_group_from_gpio_pin(gpio_pin);\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the state of a group of port pins that are configured as inputs.\r
+ *\r
+ * Reads the current logic level of a port module's pins and returns the\r
+ * current levels as a bitmask.\r
+ *\r
+ * \param[in] port Base of the PORT module to read from.\r
+ * \param[in] mask Mask of the port pin(s) to read.\r
+ *\r
+ * \return Status of the port pin(s) input buffers.\r
+ */\r
+static inline uint32_t port_group_get_input_level(\r
+ const PortGroup *const port,\r
+ const uint32_t mask)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(port);\r
+\r
+ return (port->IN.reg & mask);\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the state of a group of port pins that are configured as outputs.\r
+ *\r
+ * Reads the current logical output level of a port module's pins and returns\r
+ * the current levels as a bitmask.\r
+ *\r
+ * \param[in] port Base of the PORT module to read from.\r
+ * \param[in] mask Mask of the port pin(s) to read.\r
+ *\r
+ * \return Status of the port pin(s) output buffers.\r
+ */\r
+static inline uint32_t port_group_get_output_level(\r
+ const PortGroup *const port,\r
+ const uint32_t mask)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(port);\r
+\r
+ return (port->OUT.reg & mask);\r
+}\r
+\r
+/**\r
+ * \brief Sets the state of a group of port pins that are configured as outputs.\r
+ *\r
+ * Sets the current output level of a port module's pins to a given logic\r
+ * level.\r
+ *\r
+ * \param[out] port Base of the PORT module to write to.\r
+ * \param[in] mask Mask of the port pin(s) to change.\r
+ * \param[in] level_mask Mask of the port level(s) to set.\r
+ */\r
+static inline void port_group_set_output_level(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const uint32_t level_mask)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(port);\r
+\r
+ port->OUTSET.reg = (mask & level_mask);\r
+ port->OUTCLR.reg = (mask & ~level_mask);\r
+}\r
+\r
+/**\r
+ * \brief Toggles the state of a group of port pins that are configured as an outputs.\r
+ *\r
+ * Toggles the current output levels of a port module's pins.\r
+ *\r
+ * \param[out] port Base of the PORT module to write to.\r
+ * \param[in] mask Mask of the port pin(s) to toggle.\r
+ */\r
+static inline void port_group_toggle_output_level(\r
+ PortGroup *const port,\r
+ const uint32_t mask)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(port);\r
+\r
+ port->OUTTGL.reg = mask;\r
+}\r
+\r
+/** @} */\r
+\r
+/** \name Configuration and initialization\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Initializes a Port pin/group configuration structure to defaults.\r
+ *\r
+ * Initializes a given Port pin/group configuration structure to a set of\r
+ * known default values. This function should be called on all new\r
+ * instances of these configuration structures before being modified by the\r
+ * user application.\r
+ *\r
+ * The default configuration is as follows:\r
+ * \li Input mode with internal pullup enabled\r
+ *\r
+ * \param[out] config Configuration structure to initialize to default values.\r
+ */\r
+static inline void port_get_config_defaults(\r
+ struct port_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(config);\r
+\r
+ /* Default configuration values */\r
+ config->direction = PORT_PIN_DIR_INPUT;\r
+ config->input_pull = PORT_PIN_PULL_UP;\r
+}\r
+\r
+void port_pin_set_config(\r
+ const uint8_t gpio_pin,\r
+ const struct port_config *const config);\r
+\r
+void port_group_set_config(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const struct port_config *const config);\r
+\r
+/** @} */\r
+\r
+/** \name State reading/writing (logical pin orientated)\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieves the state of a port pin that is configured as an input.\r
+ *\r
+ * Reads the current logic level of a port pin and returns the current\r
+ * level as a boolean value.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to read.\r
+ *\r
+ * \return Status of the port pin's input buffer.\r
+ */\r
+static inline bool port_pin_get_input_level(\r
+ const uint8_t gpio_pin)\r
+{\r
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));\r
+\r
+ return (port_base->IN.reg & pin_mask);\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the state of a port pin that is configured as an output.\r
+ *\r
+ * Reads the current logical output level of a port pin and returns the current\r
+ * level as a boolean value.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to read.\r
+ *\r
+ * \return Status of the port pin's output buffer.\r
+ */\r
+static inline bool port_pin_get_output_level(\r
+ const uint8_t gpio_pin)\r
+{\r
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));\r
+\r
+ return (port_base->OUT.reg & pin_mask);\r
+}\r
+\r
+/**\r
+ * \brief Sets the state of a port pin that is configured as an output.\r
+ *\r
+ * Sets the current output level of a port pin to a given logic level.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to write to.\r
+ * \param[in] level Logical level to set the given pin to.\r
+ */\r
+static inline void port_pin_set_output_level(\r
+ const uint8_t gpio_pin,\r
+ const bool level)\r
+{\r
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));\r
+\r
+ /* Set the pin to high or low atomically based on the requested level */\r
+ if (level) {\r
+ port_base->OUTSET.reg = pin_mask;\r
+ } else {\r
+ port_base->OUTCLR.reg = pin_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Toggles the state of a port pin that is configured as an output.\r
+ *\r
+ * Toggles the current output level of a port pin.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to toggle.\r
+ */\r
+static inline void port_pin_toggle_output_level(\r
+ const uint8_t gpio_pin)\r
+{\r
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));\r
+\r
+ /* Toggle pin output level */\r
+ port_base->OUTTGL.reg = pin_mask;\r
+}\r
+\r
+/** @} */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \page asfdoc_samd20_port_extra Extra Information for PORT Driver\r
+ *\r
+ * \section asfdoc_samd20_port_extra_acronyms Acronyms\r
+ * Below is a table listing the acronyms used in this module, along with their\r
+ * intended meanings.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Acronym</th>\r
+ * <th>Description</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>GPIO</td>\r
+ * <td>General Purpose Input/Output</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>MUX</td>\r
+ * <td>Multiplexer</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_port_extra_dependencies Dependencies\r
+ * This driver has the following dependencies:\r
+ *\r
+ * - \ref asfdoc_samd20_system_pinmux_group "System Pin Multiplexer Driver"\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_port_extra_errata Errata\r
+ * There are no errata related to this driver.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_port_extra_history Module History\r
+ * An overview of the module history is presented in the table below, with\r
+ * details on the enhancements and fixes made to the module since its first\r
+ * release. The current version of this corresponds to the newest version in\r
+ * the table.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Changelog</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Initial Release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_port_exqsg Examples for PORT Driver\r
+ *\r
+ * This is a list of the available Quick Start guides (QSGs) and example\r
+ * applications for \ref asfdoc_samd20_port_group. QSGs are simple examples with\r
+ * step-by-step instructions to configure and use this driver in a selection of\r
+ * use cases. Note that QSGs can be compiled as a standalone application or be\r
+ * added to the user application.\r
+ *\r
+ * - \subpage asfdoc_samd20_port_basic_use_case\r
+ *\r
+ * \page asfdoc_samd20_port_document_revision_history Document Revision History\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Doc. Rev.</td>\r
+ * <th>Date</td>\r
+ * <th>Comments</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>B</td>\r
+ * <td>06/2013</td>\r
+ * <td>Corrected documentation typos.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>A</td>\r
+ * <td>06/2013</td>\r
+ * <td>Initial release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 GPIO Port Driver Quick Start\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_port_basic_use_case Quick Start Guide for PORT - Basic\r
+ *\r
+ * In this use case, the PORT module is configured for:\r
+ * \li One pin in input mode, with pull-up enabled\r
+ * \li One pin in output mode\r
+ *\r
+ * This use case sets up the PORT to read the current state of a GPIO pin set as\r
+ * an input, and mirrors the opposite logical state on a pin configured as an\r
+ * output.\r
+ *\r
+ * \section asfdoc_samd20_port_basic_use_case_setup Setup\r
+ *\r
+ * \subsection asfdoc_samd20_port_basic_use_case_setup_prereq Prerequisites\r
+ * There are no special setup requirements for this use-case.\r
+ *\r
+ * \subsection asfdoc_samd20_port_basic_use_case_setup_code Code\r
+ * Copy-paste the following setup code to your user application:\r
+ * \snippet qs_port_basic.c setup\r
+ *\r
+ * Add to user application initialization (typically the start of \c main()):\r
+ * \snippet qs_port_basic.c setup_init\r
+ *\r
+ * \subsection asfdoc_samd20_port_basic_use_case_setup_flow Workflow\r
+ * -# Create a PORT module pin configuration struct, which can be filled out to\r
+ * adjust the configuration of a single port pin.\r
+ * \snippet qs_port_basic.c setup_1\r
+ * -# Initialize the pin configuration struct with the module's default values.\r
+ * \note This should always be performed before using the configuration\r
+ * struct to ensure that all values are initialized to known default\r
+ * settings.\r
+ *\r
+ * \snippet qs_port_basic.c setup_2\r
+ * -# Adjust the configuration struct to request an input pin.\r
+ * \snippet qs_port_basic.c setup_3\r
+ * -# Configure GPIO10 with the initialized pin configuration struct, to enable\r
+ * the input sampler on the pin.\r
+ * \snippet qs_port_basic.c setup_4\r
+ * -# Adjust the configuration struct to request an output pin.\r
+ * \note The existing configuration struct may be re-used, as long as any\r
+ * values that have been altered from the default settings are taken\r
+ * into account by the user application.\r
+ *\r
+ * \snippet qs_port_basic.c setup_5\r
+ * -# Configure GPIO11 with the initialized pin configuration struct, to enable\r
+ * the output driver on the pin.\r
+ * \snippet qs_port_basic.c setup_6\r
+ *\r
+ * \section asfdoc_samd20_port_basic_use_case_use_main Use Case\r
+ *\r
+ * \subsection asfdoc_samd20_port_basic_use_case_code Code\r
+ * Copy-paste the following code to your user application:\r
+ * \snippet qs_port_basic.c main\r
+ *\r
+ * \subsection asfdoc_samd20_port_basic_use_case_flow Workflow\r
+ * -# Read in the current input sampler state of GPIO10, which has been\r
+ * configured as an input in the use-case setup code.\r
+ * \snippet qs_port_basic.c main_1\r
+ * -# Write the inverted pin level state to GPIO11, which has been configured as\r
+ * an output in the use-case setup code.\r
+ * \snippet qs_port_basic.c main_2\r
+ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Serial Peripheral Interface Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include "sercom.h"\r
+\r
+#define SHIFT 32\r
+\r
+#if !defined(__DOXYGEN__)\r
+/**\r
+ * \internal Configuration structure to save current gclk status.\r
+ */\r
+struct _sercom_conf {\r
+ /* Status of gclk generator initialization. */\r
+ bool generator_is_set;\r
+ /* Sercom gclk generator used. */\r
+ enum gclk_generator generator_source;\r
+};\r
+\r
+static struct _sercom_conf _sercom_config;\r
+\r
+/**\r
+ * \internal Calculate synchronous baudrate value (SPI/UART)\r
+ */\r
+enum status_code _sercom_get_sync_baud_val(\r
+ const uint32_t baudrate,\r
+ const uint32_t external_clock,\r
+ uint16_t *const baudvalue)\r
+{\r
+ /* Baud value variable */\r
+ uint16_t baud_calculated = 0;\r
+\r
+ /* Check if baudrate is outside of valid range. */\r
+ if (baudrate > (external_clock / 2)) {\r
+ /* Return with error code */\r
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;\r
+ }\r
+\r
+ /* Calculate BAUD value from clock frequency and baudrate */\r
+ baud_calculated = (external_clock / (2 * baudrate)) - 1;\r
+\r
+ /* Check if BAUD value is more than 255, which is maximum\r
+ * for synchronous mode */\r
+ if (baud_calculated > 0xFF) {\r
+ /* Return with an error code */\r
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;\r
+ } else {\r
+ *baudvalue = baud_calculated;\r
+ return STATUS_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * \internal Calculate asynchronous baudrate value (UART)\r
+*/\r
+enum status_code _sercom_get_async_baud_val(\r
+ const uint32_t baudrate,\r
+ const uint32_t peripheral_clock,\r
+ uint16_t *const baudval)\r
+{\r
+ /* Temporary variables */\r
+ uint64_t ratio = 0;\r
+ uint64_t scale = 0;\r
+ uint64_t baud_calculated = 0;\r
+\r
+ /* Check if the baudrate is outside of valid range */\r
+ if ((baudrate * 16) >= peripheral_clock) {\r
+ /* Return with error code */\r
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;\r
+ }\r
+\r
+ /* Calculate the BAUD value */\r
+ ratio = ((16 * (uint64_t)baudrate) << SHIFT) / peripheral_clock;\r
+ scale = ((uint64_t)1 << SHIFT) - ratio;\r
+ baud_calculated = (65536 * scale) >> SHIFT;\r
+\r
+ *baudval = baud_calculated;\r
+\r
+ return STATUS_OK;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Set GCLK channel to generator.\r
+ *\r
+ * This will set the appropriate GCLK channel to the requested GCLK generator.\r
+ * This will set the generator for all SERCOM instances, and the user will thus\r
+ * only be able to set the same generator that has previously been set, if any.\r
+ *\r
+ * After the generator has been set the first time, the generator can be changed\r
+ * using the \c force_change flag.\r
+ *\r
+ * \param[in] generator_source The generator to use for SERCOM.\r
+ * \param[in] force_change Force change the generator.\r
+ *\r
+ * \return Status code indicating the GCLK generator change operation.\r
+ * \retval STATUS_OK If the generator update request was\r
+ * successful.\r
+ * \retval STATUS_ERR_ALREADY_INITIALIZED If a generator was already configured\r
+ * and the new configuration was not\r
+ * forced.\r
+ */\r
+enum status_code sercom_set_gclk_generator(\r
+ const enum gclk_generator generator_source,\r
+ const bool force_change)\r
+{\r
+ /* Check if valid option. */\r
+ if (!_sercom_config.generator_is_set || force_change) {\r
+ /* Create and fill a GCLK configuration structure for the new config. */\r
+ struct system_gclk_chan_config gclk_chan_conf;\r
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);\r
+ gclk_chan_conf.source_generator = generator_source;\r
+ system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);\r
+ system_gclk_chan_enable(SERCOM_GCLK_ID);\r
+\r
+ /* Save config. */\r
+ _sercom_config.generator_source = generator_source;\r
+ _sercom_config.generator_is_set = true;\r
+\r
+ return STATUS_OK;\r
+ } else if (generator_source == _sercom_config.generator_source) {\r
+ /* Return status OK if same config. */\r
+ return STATUS_OK;\r
+ }\r
+\r
+ /* Return invalid config to already initialized GCLK. */\r
+ return STATUS_ERR_ALREADY_INITIALIZED;\r
+}\r
+\r
+/** \internal\r
+ * Creates a switch statement case entry to convert a SERCOM instance and pad\r
+ * index to the default SERCOM pad MUX setting.\r
+ */\r
+#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \\r
+ case (uintptr_t)SERCOM##n: \\r
+ switch (pad) { \\r
+ case 0: \\r
+ return SERCOM##n##_PAD0_DEFAULT; \\r
+ case 1: \\r
+ return SERCOM##n##_PAD1_DEFAULT; \\r
+ case 2: \\r
+ return SERCOM##n##_PAD2_DEFAULT; \\r
+ case 3: \\r
+ return SERCOM##n##_PAD3_DEFAULT; \\r
+ } \\r
+ break;\r
+\r
+/**\r
+ * \internal Gets the default PAD pinout for a given SERCOM.\r
+ *\r
+ * Returns the PINMUX settings for the given SERCOM and pad. This is used\r
+ * for default configuration of pins.\r
+ *\r
+ * \param[in] sercom_module Pointer to the SERCOM module\r
+ * \param[in] pad PAD to get default pinout for\r
+ *\r
+ * \returns The default PINMUX for the given SERCOM instance and PAD\r
+ *\r
+ */\r
+uint32_t _sercom_get_default_pad(\r
+ Sercom *const sercom_module,\r
+ const uint8_t pad)\r
+{\r
+ switch ((uintptr_t)sercom_module) {\r
+ /* Auto-generate a lookup table for the default SERCOM pad defaults */\r
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)\r
+ }\r
+\r
+ Assert(false);\r
+ return 0;\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Serial Peripheral Interface Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SERCOM_H_INCLUDED\r
+#define SERCOM_H_INCLUDED\r
+\r
+#include <compiler.h>\r
+#include <system.h>\r
+#include <clock.h>\r
+#include "sercom_interrupt.h"\r
+#include "sercom_pinout.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#if (SERCOM0_GCLK_ID_SLOW == SERCOM1_GCLK_ID_SLOW && \\r
+ SERCOM0_GCLK_ID_SLOW == SERCOM2_GCLK_ID_SLOW && \\r
+ SERCOM0_GCLK_ID_SLOW == SERCOM3_GCLK_ID_SLOW)\r
+# define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW\r
+#else\r
+# error "SERCOM modules must share the same slow GCLK channel ID."\r
+#endif\r
+\r
+enum status_code sercom_set_gclk_generator(\r
+ const enum gclk_generator generator_source,\r
+ const bool force_change);\r
+\r
+enum status_code _sercom_get_sync_baud_val(\r
+ const uint32_t baudrate,\r
+ const uint32_t external_clock,\r
+ uint16_t *const baudval);\r
+\r
+enum status_code _sercom_get_async_baud_val(\r
+ const uint32_t baudrate,\r
+ const uint32_t peripheral_clock,\r
+ uint16_t *const baudval);\r
+\r
+uint32_t _sercom_get_default_pad(\r
+ Sercom *const sercom_module,\r
+ const uint8_t pad);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif //__SERCOM_H_INCLUDED\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Serial Peripheral Interface Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include "sercom_interrupt.h"\r
+\r
+void *_sercom_instances[SERCOM_INST_NUM];\r
+\r
+/** Save status of initialized handlers. */\r
+static bool _handler_table_initialized = false;\r
+\r
+/** Void pointers for saving device instance structures. */\r
+static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);\r
+\r
+/**\r
+ * \internal\r
+ * Default interrupt handler.\r
+ *\r
+ * \param[in] instance SERCOM instance used.\r
+ */\r
+static void _sercom_default_handler(\r
+ const uint8_t instance)\r
+{\r
+ Assert(false);\r
+}\r
+\r
+/**\r
+ * \internal\r
+ * Find index of given instance.\r
+ *\r
+ * \param[in] sercom_instance Instance pointer.\r
+ *\r
+ * \return Index of given instance.\r
+ */\r
+uint8_t _sercom_get_sercom_inst_index(\r
+ Sercom *const sercom_instance)\r
+{\r
+ /* Save all available SERCOM instances for compare. */\r
+ Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;\r
+\r
+ /* Find index for sercom instance. */\r
+ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {\r
+ if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {\r
+ return i;\r
+ }\r
+ }\r
+\r
+ /* Invalid data given. */\r
+ Assert(false);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \internal\r
+ * Saves the given callback handler.\r
+ *\r
+ * \param[in] instance Instance index.\r
+ * \param[in] interrupt_handler Pointer to instance callback handler.\r
+ */\r
+void _sercom_set_handler(\r
+ const uint8_t instance,\r
+ const sercom_handler_t interrupt_handler)\r
+{\r
+ /* Initialize handlers with default handler and device instances with 0. */\r
+ if (_handler_table_initialized == false) {\r
+ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {\r
+ _sercom_interrupt_handlers[i] = &_sercom_default_handler;\r
+ _sercom_instances[i] = NULL;\r
+ }\r
+\r
+ _handler_table_initialized = true;\r
+ }\r
+\r
+ /* Save interrupt handler. */\r
+ _sercom_interrupt_handlers[instance] = interrupt_handler;\r
+}\r
+\r
+\r
+/** \internal\r
+ * Converts a given SERCOM index to its interrupt vector index.\r
+ */\r
+#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \\r
+ SYSTEM_INTERRUPT_MODULE_SERCOM##n,\r
+\r
+/** \internal\r
+ * Generates a SERCOM interrupt handler function for a given SERCOM index.\r
+ */\r
+#define _SERCOM_INTERRUPT_HANDLER(n, unused) \\r
+ void SERCOM##n##_Handler(void) \\r
+ { \\r
+ _sercom_interrupt_handlers[n](n); \\r
+ }\r
+\r
+/**\r
+ * \internal\r
+ * Returns the system interrupt vector.\r
+ *\r
+ * \param[in] sercom_instance Instance pointer\r
+ *\r
+ * \return Enum of system interrupt vector\r
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0\r
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1\r
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2\r
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3\r
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4\r
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5\r
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6\r
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7\r
+ */\r
+enum system_interrupt_vector _sercom_get_interrupt_vector(\r
+ Sercom *const sercom_instance)\r
+{\r
+ const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =\r
+ {\r
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)\r
+ };\r
+\r
+ /* Retrieve the index of the SERCOM being requested */\r
+ uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);\r
+\r
+ /* Get the vector number from the lookup table for the requested SERCOM */\r
+ return (enum system_interrupt_vector)sercom_int_vectors[instance_index];\r
+}\r
+\r
+/** Auto-generate a set of interrupt handlers for each SERCOM in the device */\r
+MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Serial Peripheral Interface Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SERCOM_INTERRUPT_H_INCLUDED\r
+#define SERCOM_INTERRUPT_H_INCLUDED\r
+\r
+#include "sercom.h"\r
+#include <system_interrupt.h>\r
+\r
+/* Look-up table for device instances. */\r
+extern void *_sercom_instances[SERCOM_INST_NUM];\r
+\r
+typedef void (*sercom_handler_t)(uint8_t instance);\r
+\r
+uint8_t _sercom_get_sercom_inst_index(\r
+ Sercom *const sercom_instance);\r
+\r
+enum system_interrupt_vector _sercom_get_interrupt_vector(\r
+ Sercom *const sercom_instance);\r
+\r
+void _sercom_set_handler(\r
+ const uint8_t instance,\r
+ const sercom_handler_t interrupt_handler);\r
+\r
+#endif /* SERCOM_INTERRUPT_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 SERCOM Module Pinout Definitions\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SERCOM_PINOUT_H_INCLUDED\r
+#define SERCOM_PINOUT_H_INCLUDED\r
+\r
+#include "sercom.h"\r
+\r
+/* SERCOM0 */\r
+#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0\r
+#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1\r
+#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2\r
+#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3\r
+\r
+/* SERCOM1 */\r
+#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0\r
+#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1\r
+#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2\r
+#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3\r
+\r
+/* SERCOM2 */\r
+#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0\r
+#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1\r
+#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2\r
+#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3\r
+\r
+/* SERCOM3 */\r
+#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0\r
+#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1\r
+#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2\r
+#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3\r
+\r
+/* SERCOM4 */\r
+#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0\r
+#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1\r
+#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2\r
+#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3\r
+\r
+/* SERCOM5 */\r
+#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0\r
+#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1\r
+#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2\r
+#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3\r
+\r
+#endif /* SERCOM_PINOUT_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 USART Interface Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_sercom_usart_basic_use_case Quick Start Guide for SERCOM USART - Basic\r
+ *\r
+ * This quick start will echo back characters typed into the terminal. In this\r
+ * use case the USART will be configured with the following settings:\r
+ * - Asynchronous mode\r
+ * - 9600 Baudrate\r
+ * - 8-bits, No Parity and 1 Stop Bit\r
+ * - TX and RX enabled and connected to the Xplained PRO Embedded Debugger virtual COM port\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_basic_use_case_setup Setup\r
+ *\r
+ * \subsection asfdoc_samd20_sercom_usart_basic_use_case_prereq Prerequisites\r
+ * There are no special setup requirements for this use-case.\r
+ *\r
+ * \subsection asfdoc_samd20_usart_basic_use_case_setup_code Code\r
+ * Add to the main application source file, outside of any functions:\r
+ * \snippet qs_usart_basic_use.c module_inst\r
+ *\r
+ * Copy-paste the following setup code to your user application:\r
+ * \snippet qs_usart_basic_use.c setup\r
+ *\r
+ * Add to user application initialization (typically the start of \c main()):\r
+ * \snippet qs_usart_basic_use.c setup_init\r
+ *\r
+ * \subsection asfdoc_samd20_usart_basic_use_case_setup_flow Workflow\r
+ * -# Create a module software instance structure for the USART module to store\r
+ * the USART driver state while it is in use.\r
+ * \note This should never go out of scope as long as the module is in use.\r
+ * In most cases, this should be global.\r
+ *\r
+ * \snippet qs_usart_basic_use.c module_inst\r
+ * -# Configure the USART module.\r
+ * -# Create a USART module configuration struct, which can be filled out to\r
+ * adjust the configuration of a physical USART peripheral.\r
+ * \snippet qs_usart_basic_use.c setup_config\r
+ * -# Initialize the USART configuration struct with the module's default values.\r
+ * \note This should always be performed before using the configuration\r
+ * struct to ensure that all values are initialized to known default\r
+ * settings.\r
+ *\r
+ * \snippet qs_usart_basic_use.c setup_config_defaults\r
+ * -# Alter the USART settings to configure the physical pinout, baud rate and\r
+ * other relevant parameters.\r
+ * \snippet qs_usart_basic_use.c setup_change_config\r
+ * -# Configure the USART module with the desired settings, retrying while the\r
+ * driver is busy until the configuration is stressfully set.\r
+ * \snippet qs_usart_basic_use.c setup_set_config\r
+ * -# Enable the USART module.\r
+ * \snippet qs_usart_basic_use.c setup_enable\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_usart_basic_use_case_main Use Case\r
+ *\r
+ * \subsection asfdoc_samd20_usart_basic_use_case_main_code Code\r
+ * Copy-paste the following code to your user application:\r
+ * \snippet qs_usart_basic_use.c main\r
+ *\r
+ * \subsection asfdoc_samd20_usart_basic_use_case_main_flow Workflow\r
+ * -# Send a string to the USART to show the demo is running, blocking until\r
+ * all characters have been sent.\r
+ * \snippet qs_usart_basic_use.c main_send_string\r
+ * -# Enter an infinite loop to continuously echo received values on the USART.\r
+ * \snippet qs_usart_basic_use.c main_loop\r
+ * -# Perform a blocking read of the USART, storing the received character into\r
+ * the previously declared temporary variable.\r
+ * \snippet qs_usart_basic_use.c main_read\r
+ * -# Echo the received variable back to the USART via a blocking write.\r
+ * \snippet qs_usart_basic_use.c main_write\r
+ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 USART Interface Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_sercom_usart_callback_use_case Quick Start Guide for SERCOM USART - Callback\r
+ *\r
+ * This quick start will echo back characters typed into the terminal, using\r
+ * asynchronous TX and RX callbacks from the USART peripheral. In this use case\r
+ * the USART will be configured with the following settings:\r
+ * - Asynchronous mode\r
+ * - 9600 Baudrate\r
+ * - 8-bits, No Parity and 1 Stop Bit\r
+ * - TX and RX enabled and connected to the Xplained PRO Embedded Debugger virtual COM port\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_callback_use_case_setup Setup\r
+ *\r
+ * \subsection asfdoc_samd20_sercom_usart_callback_use_case_prereq Prerequisites\r
+ * There are no special setup requirements for this use-case.\r
+ *\r
+ * \subsection asfdoc_samd20_usart_callback_use_case_setup_code Code\r
+ * Add to the main application source file, outside of any functions:\r
+ * \snippet qs_usart_callback.c module_inst\r
+ * \snippet qs_usart_callback.c rx_buffer_var\r
+ *\r
+ * Copy-paste the following callback function code to your user application:\r
+ * \snippet qs_usart_callback.c callback_funcs\r
+ *\r
+ * Copy-paste the following setup code to your user application:\r
+ * \snippet qs_usart_callback.c setup\r
+ *\r
+ * Add to user application initialization (typically the start of \c main()):\r
+ * \snippet qs_usart_callback.c setup_init\r
+ *\r
+ * \subsection asfdoc_samd20_usart_callback_use_case_setup_flow Workflow\r
+ * -# Create a module software instance structure for the USART module to store\r
+ * the USART driver state while it is in use.\r
+ * \note This should never go out of scope as long as the module is in use.\r
+ * In most cases, this should be global.\r
+ *\r
+ * \snippet qs_usart_callback.c module_inst\r
+ * -# Configure the USART module.\r
+ * -# Create a USART module configuration struct, which can be filled out to\r
+ * adjust the configuration of a physical USART peripheral.\r
+ * \snippet qs_usart_callback.c setup_config\r
+ * -# Initialize the USART configuration struct with the module's default values.\r
+ * \note This should always be performed before using the configuration\r
+ * struct to ensure that all values are initialized to known default\r
+ * settings.\r
+ *\r
+ * \snippet qs_usart_callback.c setup_config_defaults\r
+ * -# Alter the USART settings to configure the physical pinout, baud rate and\r
+ * other relevant parameters.\r
+ * \snippet qs_usart_callback.c setup_change_config\r
+ * -# Configure the USART module with the desired settings, retrying while the\r
+ * driver is busy until the configuration is stressfully set.\r
+ * \snippet qs_usart_callback.c setup_set_config\r
+ * -# Enable the USART module.\r
+ * \snippet qs_usart_callback.c setup_enable\r
+ * -# Configure the USART callbacks.\r
+ * -# Register the TX and RX callback functions with the driver.\r
+ * \snippet qs_usart_callback.c setup_register_callbacks\r
+ * -# Enable the TX and RX callbacks so that they will be called by the driver\r
+ * when appropriate.\r
+ * \snippet qs_usart_callback.c setup_enable_callbacks\r
+ *\r
+ * \section asfdoc_samd20_usart_callback_use_case_main Use Case\r
+ *\r
+ * \subsection asfdoc_samd20_usart_callback_use_case_main_code Code\r
+ * Copy-paste the following code to your user application:\r
+ * \snippet qs_usart_callback.c main\r
+ *\r
+ * \subsection asfdoc_samd20_usart_callback_use_case_main_flow Workflow\r
+ * -# Enable global interrupts, so that the callbacks can be fired.\r
+ * \snippet qs_usart_callback.c enable_global_interrupts\r
+ * -# Send a string to the USART to show the demo is running, blocking until\r
+ * all characters have been sent.\r
+ * \snippet qs_usart_callback.c main_send_string\r
+ * -# Enter an infinite loop to continuously echo received values on the USART.\r
+ * \snippet qs_usart_callback.c main_loop\r
+ * -# Perform an asynchronous read of the USART, which will fire the registered\r
+ * callback when characters are received.\r
+ * \snippet qs_usart_callback.c main_read\r
+ */\r
+\r
+#include <asf.h>\r
+#include <conf_clocks.h>\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 SERCOM USART Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include "usart.h"\r
+#include <pinmux.h>\r
+#if USART_CALLBACK_MODE == true\r
+# include "usart_interrupt.h"\r
+#endif\r
+\r
+/**\r
+ * \internal Checks a USART config against current set config\r
+ *\r
+ * This function will check that the config does not alter the\r
+ * configuration of the module. If the new config changes any\r
+ * setting, the initialization will be discarded.\r
+ *\r
+ * \param[in] module Pointer to the software instance struct\r
+ * \param[in] config Pointer to the configuration struct\r
+ *\r
+ * \return The status of the configuration\r
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.\r
+ * \retval STATUS_ERR_DENIED If configuration was different from previous\r
+ * \retval STATUS_OK If the configuration was written\r
+ */\r
+static enum status_code _usart_check_config(\r
+ struct usart_module *const module,\r
+ const struct usart_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+ Sercom *const hw = (module->hw);\r
+\r
+ uint32_t pad0 = config->pinmux_pad0;\r
+ uint32_t pad1 = config->pinmux_pad1;\r
+ uint32_t pad2 = config->pinmux_pad2;\r
+ uint32_t pad3 = config->pinmux_pad3;\r
+\r
+ /* SERCOM PAD0 */\r
+ if (pad0 == PINMUX_DEFAULT) {\r
+ pad0 = _sercom_get_default_pad(hw, 0);\r
+ }\r
+ if ((pad0 != PINMUX_UNUSED) && ((pad0 & 0xFFFF)!=\r
+ system_pinmux_pin_get_mux_position(pad0 >> 16))) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* SERCOM PAD1 */\r
+ if (pad1 == PINMUX_DEFAULT) {\r
+ pad1 = _sercom_get_default_pad(hw, 1);\r
+ }\r
+ if ((pad1 != PINMUX_UNUSED) && ((pad1 & 0xFFFF) !=\r
+ system_pinmux_pin_get_mux_position(pad1 >> 16))) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* SERCOM PAD2 */\r
+ if (pad2 == PINMUX_DEFAULT) {\r
+ pad2 = _sercom_get_default_pad(hw, 2);\r
+ }\r
+ if ((pad2 != PINMUX_UNUSED) && ((pad2 & 0xFFFF) !=\r
+ system_pinmux_pin_get_mux_position(pad2 >> 16))) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* SERCOM PAD3 */\r
+ if (pad3 == PINMUX_DEFAULT) {\r
+ pad3 = _sercom_get_default_pad(hw, 3);\r
+ }\r
+ if ((pad3 != PINMUX_UNUSED) && ((pad3 & 0xFFFF) !=\r
+ system_pinmux_pin_get_mux_position(pad3 >> 16))) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* Find baud value and compare it */\r
+ uint16_t baud = 0;\r
+ enum status_code status_code = STATUS_OK;\r
+\r
+ switch (config->transfer_mode)\r
+ {\r
+ case USART_TRANSFER_SYNCHRONOUSLY:\r
+ if (!config->use_external_clock) {\r
+ status_code = _sercom_get_sync_baud_val(config->baudrate,\r
+ system_gclk_chan_get_hz(SERCOM_GCLK_ID), &baud);\r
+ }\r
+\r
+ break;\r
+\r
+ case USART_TRANSFER_ASYNCHRONOUSLY:\r
+ if (config->use_external_clock) {\r
+ status_code =\r
+ _sercom_get_async_baud_val(config->baudrate,\r
+ config->ext_clock_freq, &baud);\r
+ } else {\r
+ status_code =\r
+ _sercom_get_async_baud_val(config->baudrate,\r
+ system_gclk_chan_get_hz(SERCOM_GCLK_ID), &baud);\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ if (status_code != STATUS_OK) {\r
+ /* Baud rate calculation error, return status code */\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ if (usart_hw->BAUD.reg != baud) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ uint32_t ctrla = 0;\r
+ uint32_t ctrlb = 0;\r
+\r
+ /* Check sample mode, data order, internal muxing, and clock polarity */\r
+ ctrla = (uint32_t)config->data_order |\r
+ (uint32_t)config->mux_setting |\r
+ (uint32_t)config->transfer_mode |\r
+ SERCOM_USART_CTRLA_MODE(0) |\r
+ (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);\r
+\r
+ /* set enable bit */\r
+ ctrla |= (SERCOM_USART_CTRLA_ENABLE);\r
+\r
+ if (config->use_external_clock == false) {\r
+ ctrla |= SERCOM_USART_CTRLA_MODE_USART_INT_CLK;\r
+ }\r
+ else {\r
+ ctrla |= SERCOM_USART_CTRLA_MODE_USART_EXT_CLK;\r
+ }\r
+\r
+ /* Check stopbits and character size */\r
+ ctrlb = (uint32_t)config->stopbits | (uint32_t)config->character_size |\r
+ (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |\r
+ (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);\r
+\r
+ /* Check parity mode bits */\r
+ if (config->parity != USART_PARITY_NONE) {\r
+ ctrla |= SERCOM_USART_CTRLA_FORM(1);\r
+ ctrlb |= config->parity;\r
+ } else {\r
+ ctrla |= SERCOM_USART_CTRLA_FORM(0);\r
+ }\r
+\r
+ if (usart_hw->CTRLA.reg == ctrla && usart_hw->CTRLB.reg == ctrlb) {\r
+ module->character_size = config->character_size;\r
+ return STATUS_OK;\r
+ } else {\r
+ module->hw = NULL;\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+}\r
+\r
+/**\r
+ * \internal\r
+ * Set Configuration of the USART module\r
+ */\r
+static enum status_code _usart_set_config(\r
+ struct usart_module *const module,\r
+ const struct usart_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Index for generic clock */\r
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);\r
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;\r
+\r
+ /* Cache new register values to minimize the number of register writes */\r
+ uint32_t ctrla = 0;\r
+ uint32_t ctrlb = 0;\r
+ uint16_t baud = 0;\r
+\r
+ /* Set data order, internal muxing, and clock polarity */\r
+ ctrla = (uint32_t)config->data_order |\r
+ (uint32_t)config->mux_setting |\r
+ (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);\r
+\r
+ enum status_code status_code = STATUS_OK;\r
+\r
+ /* Get baud value from mode and clock */\r
+ switch (config->transfer_mode)\r
+ {\r
+ case USART_TRANSFER_SYNCHRONOUSLY:\r
+ if (!config->use_external_clock) {\r
+ status_code = _sercom_get_sync_baud_val(config->baudrate,\r
+ system_gclk_chan_get_hz(gclk_index), &baud);\r
+ }\r
+\r
+ break;\r
+\r
+ case USART_TRANSFER_ASYNCHRONOUSLY:\r
+ if (config->use_external_clock) {\r
+ status_code =\r
+ _sercom_get_async_baud_val(config->baudrate,\r
+ config->ext_clock_freq, &baud);\r
+ } else {\r
+ status_code =\r
+ _sercom_get_async_baud_val(config->baudrate,\r
+ system_gclk_chan_get_hz(gclk_index), &baud);\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ /* Check if calculating the baud rate failed */\r
+ if (status_code != STATUS_OK) {\r
+ /* Abort */\r
+ return status_code;\r
+ }\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /*Set baud val */\r
+ usart_hw->BAUD.reg = baud;\r
+\r
+ /* Set sample mode */\r
+ ctrla |= config->transfer_mode;\r
+\r
+ if (config->use_external_clock == false) {\r
+ ctrla |= SERCOM_USART_CTRLA_MODE_USART_INT_CLK;\r
+ }\r
+ else {\r
+ ctrla |= SERCOM_USART_CTRLA_MODE_USART_EXT_CLK;\r
+ }\r
+\r
+ /* Set stopbits, character size and enable transceivers */\r
+ ctrlb = (uint32_t)config->stopbits | (uint32_t)config->character_size |\r
+ (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |\r
+ (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);\r
+\r
+ /* Set parity mode */\r
+ if (config->parity != USART_PARITY_NONE) {\r
+ ctrla |= SERCOM_USART_CTRLA_FORM(1);\r
+ ctrlb |= config->parity;\r
+ } else {\r
+ ctrla |= SERCOM_USART_CTRLA_FORM(0);\r
+ }\r
+\r
+ /* Set run mode during device sleep */\r
+ if (config->run_in_standby) {\r
+ /* Enable in sleep mode */\r
+ ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;\r
+ }\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /* Write configuration to CTRLB */\r
+ usart_hw->CTRLB.reg = ctrlb;\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /* Write configuration to CTRLA */\r
+ usart_hw->CTRLA.reg = ctrla;\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Initializes the device\r
+ *\r
+ * Initializes the USART device based on the setting specified in the\r
+ * configuration struct.\r
+ *\r
+ * \param[out] module Pointer to USART device\r
+ * \param[in] hw Pointer to USART hardware instance\r
+ * \param[in] config Pointer to configuration struct\r
+ *\r
+ * \return Status of the initialization\r
+ *\r
+ * \retval STATUS_OK The initialization was successful\r
+ * \retval STATUS_BUSY The USART module is busy\r
+ * resetting\r
+ * \retval STATUS_ERR_DENIED The USART have not been disabled in\r
+ * advance of initialization\r
+ * \retval STATUS_ERR_INVALID_ARG The configuration struct contains\r
+ * invalid configuration\r
+ * \retval STATUS_ERR_ALREADY_INITIALIZED The SERCOM instance has already been\r
+ * initialized with different clock\r
+ * configuration\r
+ * \retval STATUS_ERR_BAUD_UNAVAILABLE The BAUD rate given by the\r
+ * configuration\r
+ * struct cannot be reached with\r
+ * the current clock configuration\r
+ */\r
+enum status_code usart_init(\r
+ struct usart_module *const module,\r
+ Sercom *const hw,\r
+ const struct usart_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(hw);\r
+ Assert(config);\r
+\r
+ enum status_code status_code = STATUS_OK;\r
+\r
+ /* Assign module pointer to software instance struct */\r
+ module->hw = hw;\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);\r
+ uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;\r
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;\r
+\r
+ if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {\r
+ /* The module is busy resetting itself */\r
+ return STATUS_BUSY;\r
+ }\r
+\r
+ if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {\r
+ /* Check if the new setting are the same as the old */\r
+ return _usart_check_config(module, config);\r
+ }\r
+\r
+ /* Turn on module in PM */\r
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);\r
+\r
+ /* Set up the GCLK for the module */\r
+ struct system_gclk_chan_config gclk_chan_conf;\r
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);\r
+ gclk_chan_conf.source_generator = config->generator_source;\r
+ system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);\r
+ system_gclk_chan_enable(gclk_index);\r
+ sercom_set_gclk_generator(config->generator_source, false);\r
+\r
+ /* Set character size */\r
+ module->character_size = config->character_size;\r
+\r
+ /* Set transmitter and receiver status */\r
+ module->receiver_enabled = config->receiver_enable;\r
+ module->transmitter_enabled = config->transmitter_enable;\r
+\r
+ /* Configure Pins */\r
+ struct system_pinmux_config pin_conf;\r
+ system_pinmux_get_config_defaults(&pin_conf);\r
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;\r
+\r
+ /* Set configuration according to the config struct */\r
+ status_code = _usart_set_config(module, config);\r
+ if(status_code != STATUS_OK) {\r
+ return status_code;\r
+ }\r
+\r
+ uint32_t pad0 = config->pinmux_pad0;\r
+ uint32_t pad1 = config->pinmux_pad1;\r
+ uint32_t pad2 = config->pinmux_pad2;\r
+ uint32_t pad3 = config->pinmux_pad3;\r
+\r
+ /* SERCOM PAD0 */\r
+ if (pad0 == PINMUX_DEFAULT) {\r
+ pad0 = _sercom_get_default_pad(hw, 0);\r
+ }\r
+ if (pad0 != PINMUX_UNUSED) {\r
+ pin_conf.mux_position = pad0 & 0xFFFF;\r
+ system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);\r
+ }\r
+\r
+ /* SERCOM PAD1 */\r
+ if (pad1 == PINMUX_DEFAULT) {\r
+ pad1 = _sercom_get_default_pad(hw, 1);\r
+ }\r
+ if (pad1 != PINMUX_UNUSED) {\r
+ pin_conf.mux_position = pad1 & 0xFFFF;\r
+ system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);\r
+ }\r
+\r
+ /* SERCOM PAD2 */\r
+ if (pad2 == PINMUX_DEFAULT) {\r
+ pad2 = _sercom_get_default_pad(hw, 2);\r
+ }\r
+ if (pad2 != PINMUX_UNUSED) {\r
+ pin_conf.mux_position = pad2 & 0xFFFF;\r
+ system_pinmux_pin_set_config(pad2 >> 16, &pin_conf);\r
+ }\r
+\r
+ /* SERCOM PAD3 */\r
+ if (pad3 == PINMUX_DEFAULT) {\r
+ pad3 = _sercom_get_default_pad(hw, 3);\r
+ }\r
+ if (pad3 != PINMUX_UNUSED) {\r
+ pin_conf.mux_position = pad3 & 0xFFFF;\r
+ system_pinmux_pin_set_config(pad3 >> 16, &pin_conf);\r
+ }\r
+#if USART_CALLBACK_MODE == true\r
+ /* Initialize parameters */\r
+ for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {\r
+ module->callback[i] = NULL;\r
+ }\r
+\r
+ module->tx_buffer_ptr = NULL;\r
+ module->rx_buffer_ptr = NULL;\r
+ module->remaining_tx_buffer_length = 0x0000;\r
+ module->remaining_rx_buffer_length = 0x0000;\r
+ module->callback_reg_mask = 0x00;\r
+ module->callback_enable_mask = 0x00;\r
+ module->rx_status = STATUS_OK;\r
+ module->tx_status = STATUS_OK;\r
+\r
+ /* Set interrupt handler and register USART software module struct in\r
+ * look-up table */\r
+ uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);\r
+ _sercom_set_handler(instance_index, _usart_interrupt_handler);\r
+ _sercom_instances[instance_index] = module;\r
+#endif\r
+ return status_code;\r
+}\r
+\r
+/**\r
+ * \brief Transmit a character via the USART\r
+ *\r
+ * This blocking function will transmit a single character via the\r
+ * USART.\r
+ *\r
+ * \param[in] module Pointer to the software instance struct\r
+ * \param[in] tx_data Data to transfer\r
+ *\r
+ * \return Status of the operation\r
+ * \retval STATUS_OK If the operation was completed\r
+ * \retval STATUS_BUSY If the operation was not completed, due to the USART\r
+ * module being busy.\r
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled\r
+ */\r
+enum status_code usart_write_wait(\r
+ struct usart_module *const module,\r
+ const uint16_t tx_data)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Check that the transmitter is enabled */\r
+ if (!(module->transmitter_enabled)) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+#if USART_CALLBACK_MODE == true\r
+ /* Check if the USART is busy doing asynchronous operation. */\r
+ if (module->remaining_tx_buffer_length > 0) {\r
+ return STATUS_BUSY;\r
+ }\r
+\r
+#else\r
+ /* Check if USART is ready for new data */\r
+ if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {\r
+ /* Return error code */\r
+ return STATUS_BUSY;\r
+ }\r
+#endif\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /* Write data to USART module */\r
+ usart_hw->DATA.reg = tx_data;\r
+\r
+ while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {\r
+ /* Wait until data is sent */\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Receive a character via the USART\r
+ *\r
+ * This blocking function will receive a character via the USART.\r
+ *\r
+ * \param[in] module Pointer to the software instance struct\r
+ * \param[out] rx_data Pointer to received data\r
+ *\r
+ * \return Status of the operation\r
+ * \retval STATUS_OK If the operation was completed\r
+ * \retval STATUS_BUSY If the operation was not completed,\r
+ * due to the USART module being busy\r
+ * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,\r
+ * due to configuration mismatch between USART\r
+ * and the sender\r
+ * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,\r
+ * due to the baud rate being too low or the\r
+ * system frequency being too high\r
+ * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due to\r
+ * data being corrupted\r
+ * \retval STATUS_ERR_DENIED If the receiver is not enabled\r
+ */\r
+enum status_code usart_read_wait(\r
+ struct usart_module *const module,\r
+ uint16_t *const rx_data)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Error variable */\r
+ uint8_t error_code;\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Check that the receiver is enabled */\r
+ if (!(module->receiver_enabled)) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+#if USART_CALLBACK_MODE == true\r
+ /* Check if the USART is busy doing asynchronous operation. */\r
+ if (module->remaining_rx_buffer_length > 0) {\r
+ return STATUS_BUSY;\r
+ }\r
+\r
+#else\r
+ /* Check if USART has new data */\r
+ if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {\r
+ /* Return error code */\r
+ return STATUS_BUSY;\r
+ }\r
+#endif\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /* Read out the status code and mask away all but the 3 LSBs*/\r
+ error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);\r
+\r
+ /* Check if an error has occurred during the receiving */\r
+ if (error_code) {\r
+ /* Check which error occurred */\r
+ if (error_code & SERCOM_USART_STATUS_FERR) {\r
+ /* Clear flag by writing a 1 to it and\r
+ * return with an error code */\r
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;\r
+\r
+ return STATUS_ERR_BAD_FORMAT;\r
+ } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {\r
+ /* Clear flag by writing a 1 to it and\r
+ * return with an error code */\r
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;\r
+\r
+ return STATUS_ERR_OVERFLOW;\r
+ } else if (error_code & SERCOM_USART_STATUS_PERR) {\r
+ /* Clear flag by writing a 1 to it and\r
+ * return with an error code */\r
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;\r
+\r
+ return STATUS_ERR_BAD_DATA;\r
+ }\r
+ }\r
+\r
+ /* Read data from USART module */\r
+ *rx_data = usart_hw->DATA.reg;\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Transmit a buffer of characters via the USART\r
+ *\r
+ * This blocking function will transmit a block of \c length characters\r
+ * via the USART\r
+ *\r
+ * \note Using this function in combination with the interrupt (\c _job) functions is\r
+ * not recommended as it has no functionality to check if there is an\r
+ * ongoing interrupt driven operation running or not.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] tx_data Pointer to data to transmit\r
+ * \param[in] length Number of characters to transmit\r
+ *\r
+ * \return Status of the operation\r
+ * \retval STATUS_OK If operation was completed\r
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid\r
+ * arguments\r
+ * \retval STATUS_ERR_TIMEOUT If operation was not completed, due to USART\r
+ * module timing out\r
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled\r
+ */\r
+enum status_code usart_write_buffer_wait(\r
+ struct usart_module *const module,\r
+ const uint8_t *tx_data,\r
+ uint16_t length)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Check if the buffer length is valid */\r
+ if (length == 0) {\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ /* Check that the transmitter is enabled */\r
+ if (!(module->transmitter_enabled)) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ uint16_t tx_pos = 0;\r
+\r
+ /* Blocks while buffer is being transferred */\r
+ while (length--) {\r
+ /* Wait for the USART to be ready for new data and abort\r
+ * operation if it doesn't get ready within the timeout*/\r
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {\r
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {\r
+ break;\r
+ } else if (i == USART_TIMEOUT) {\r
+ return STATUS_ERR_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Data to send is at least 8 bits long */\r
+ uint16_t data_to_send = tx_data[tx_pos++];\r
+\r
+ /* Check if the character size exceeds 8 bit */\r
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {\r
+ data_to_send |= (tx_data[tx_pos++] << 8);\r
+ }\r
+\r
+ /* Send the data through the USART module */\r
+ usart_write_wait(module, data_to_send);\r
+ }\r
+\r
+ /* Wait until Transmit is complete or timeout */\r
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {\r
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {\r
+ break;\r
+ } else if (i == USART_TIMEOUT) {\r
+ return STATUS_ERR_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Receive a buffer of \c length characters via the USART\r
+ *\r
+ * This blocking function will receive a block of \c length characters\r
+ * via the USART.\r
+ *\r
+ * \note Using this function in combination with the interrupt (\c *_job)\r
+ * functions is not recommended as it has no functionality to check if\r
+ * there is an ongoing interrupt driven operation running or not.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[out] rx_data Pointer to receive buffer\r
+ * \param[in] length Number of characters to receive\r
+ *\r
+ * \return Status of the operation.\r
+ * \retval STATUS_OK If operation was completed\r
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to an\r
+ * invalid argument being supplied\r
+ * \retval STATUS_ERR_TIMEOUT If operation was not completed, due\r
+ * to USART module timing out\r
+ * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,\r
+ * due to a configuration mismatch\r
+ * between USART and the sender\r
+ * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,\r
+ * due to the baud rate being too low or the\r
+ * system frequency being too high\r
+ * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due\r
+ * to data being corrupted\r
+ * \retval STATUS_ERR_DENIED If the receiver is not enabled\r
+ */\r
+enum status_code usart_read_buffer_wait(\r
+ struct usart_module *const module,\r
+ uint8_t *rx_data,\r
+ uint16_t length)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Check if the buffer length is valid */\r
+ if (length == 0) {\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ /* Check that the receiver is enabled */\r
+ if (!(module->receiver_enabled)) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ uint16_t rx_pos = 0;\r
+\r
+ /* Blocks while buffer is being received */\r
+ while (length--) {\r
+ /* Wait for the USART to have new data and abort operation if it\r
+ * doesn't get ready within the timeout*/\r
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {\r
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {\r
+ break;\r
+ } else if (i == USART_TIMEOUT) {\r
+ return STATUS_ERR_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ enum status_code retval;\r
+ uint16_t received_data = 0;\r
+\r
+ retval = usart_read_wait(module, &received_data);\r
+\r
+ if (retval != STATUS_OK) {\r
+ /* Overflow, abort */\r
+ return retval;\r
+ }\r
+\r
+ /* Read value will be at least 8-bits long */\r
+ rx_data[rx_pos++] = received_data;\r
+\r
+ /* If 9-bit data, write next received byte to the buffer */\r
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {\r
+ rx_data[rx_pos++] = (received_data >> 8);\r
+ }\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
--- /dev/null
+/**\r
+ *\r
+ * \file\r
+ *\r
+ * \brief SAM D20 SERCOM USART Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef USART_H_INCLUDED\r
+#define USART_H_INCLUDED\r
+\r
+/**\r
+ * \defgroup asfdoc_samd20_sercom_usart_group SAM D20 Serial USART Driver (SERCOM USART)\r
+ *\r
+ * This driver for SAM D20 devices provides an interface for the configuration\r
+ * and management of the SERCOM module in its USART mode to transfer or receive\r
+ * USART data frames. The following driver API modes are covered by this\r
+ * manual:\r
+ *\r
+ * - Polled APIs\r
+ * \if USART_CALLBACK_MODE\r
+ * - Callback APIs\r
+ * \endif\r
+ *\r
+ * The following peripherals are used by this module:\r
+ *\r
+ * - SERCOM (Serial Communication Interface)\r
+ *\r
+ * The outline of this documentation is as follows:\r
+ * - \ref asfdoc_samd20_sercom_usart_prerequisites\r
+ * - \ref asfdoc_samd20_sercom_usart_overview\r
+ * - \ref asfdoc_samd20_sercom_usart_special_considerations\r
+ * - \ref asfdoc_samd20_sercom_usart_extra_info\r
+ * - \ref asfdoc_samd20_sercom_usart_examples\r
+ * - \ref asfdoc_samd20_sercom_usart_api_overview\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_prerequisites Prerequisites\r
+ *\r
+ * To use the USART you need to have a GCLK generator enabled and running\r
+ * that can be used as the SERCOM clock source. This can either be configured\r
+ * in conf_clocks.h or by using the system clock driver.\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_overview Module Overview\r
+ *\r
+ * This driver will use one (or more) SERCOM interfaces on the system\r
+ * and configure it to run as a USART interface in either synchronous\r
+ * or asynchronous mode.\r
+ *\r
+ * \subsection asfdoc_samd20_sercom_usart_overview_frame_format Frame Format\r
+ *\r
+ * Communication is based on frames, where the frame format can be customized\r
+ * to accommodate a wide range of standards. A frame consists of a start bit,\r
+ * a number of data bits, an optional parity bit for error detection as well\r
+ * as a configurable length stop bit(s) - see\r
+ * \ref asfdoc_samd20_sercom_usart_frame_diagram "the figure below".\r
+ * \ref asfdoc_samd20_sercom_usart_frame_params "The table below" shows the\r
+ * available parameters you can change in a frame.\r
+ *\r
+ * \anchor asfdoc_samd20_sercom_usart_frame_params\r
+ * <table>\r
+ * <caption>USART Frame Parameters</caption>\r
+ * <tr>\r
+ * <th>Parameter</th>\r
+ * <th>Options</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Start bit</td>\r
+ * <td>1</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Data bits</td>\r
+ * <td>5, 6, 7, 8, 9</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Parity bit</td>\r
+ * <td>None, Even, Odd</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Stop bits</td>\r
+ * <td>1, 2</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \anchor asfdoc_samd20_sercom_usart_frame_diagram\r
+ * \image html usart_frame.svg "USART Frame overview" width=100%\r
+ *\r
+ * \subsection asfdoc_samd20_sercom_usart_overview_sync Synchronous mode\r
+ *\r
+ * In synchronous mode a dedicated clock line is provided; either by the USART\r
+ * itself if in master mode, or by an external master if in slave mode.\r
+ * Maximum transmission speed is the same as the GCLK clocking the USART\r
+ * peripheral when in slave mode, and the GCLK divided by two if in\r
+ * master mode. In synchronous mode the interface needs three lines to\r
+ * communicate:\r
+ * - TX (Transmit pin)\r
+ * - RX (Receive pin)\r
+ * - XCK (Clock pin)\r
+ *\r
+ * \subsubsection asfdoc_samd20_sercom_usart_overview_sync_sampling Data sampling\r
+ * In synchronous mode the data is sampled on either the rising or falling edge\r
+ * of the clock signal. This is configured by setting the clock polarity in the\r
+ * configuration struct.\r
+ *\r
+ * \subsection asfdoc_samd20_sercom_usart_overview_async Asynchronous mode\r
+ *\r
+ * In asynchronous mode no dedicated clock line is used, and the communication\r
+ * is based on matching the clock speed on the transmitter and receiver. The\r
+ * clock is generated from the internal SERCOM baudrate generator, and the\r
+ * frames are synchronized by using the frame start bits. Maximum transmission\r
+ * speed is limited to the SERCOM GCLK divided by 16.\r
+ * In asynchronous mode the interface only needs two lines to communicate:\r
+ * - TX (Transmit pin)\r
+ * - RX (Receive pin)\r
+ *\r
+ * \subsubsection asfdoc_samd20_sercom_usart_overview_async_clock_matching Transmitter/receiver clock matching\r
+ *\r
+ * For successful transmit and receive using the asynchronous mode the receiver\r
+ * and transmitter clocks needs to be closely matched. When receiving a frame\r
+ * that does not match the selected baud rate closely enough the receiver will\r
+ * be unable to synchronize the frame(s), and garbage transmissions will\r
+ * result.\r
+ *\r
+ * \subsection asfdoc_samd20_sercom_usart_parity Parity\r
+ * Parity can be enabled to detect if a transmission was in error. This is done by\r
+ * counting the number of "1" bits in the frame. When using Even parity the\r
+ * parity bit will be set if the total number of "1"s in the frame are an even\r
+ * number. If using Odd parity the parity bit will be set if the total number\r
+ * of "1"s are Odd.\r
+ *\r
+ * When receiving a character the receiver will count the number of "1"s in the\r
+ * frame and give an error if the received frame and parity bit disagree.\r
+ *\r
+ * \subsection asfdoc_samd20_sercom_usart_overview_pin_configuration GPIO configuration\r
+ *\r
+ * the SERCOM module have four internal PADS where the RX pin can be placed at all\r
+ * the PADS, and the TX and XCK pins have two predefined positions that can be changed.\r
+ * The PADS can then be routed to an external GPIO pin using the normal pin\r
+ * multiplexing scheme on the SAM D20.\r
+ *\r
+ * For SERCOM pad multiplexer position documentation, see\r
+ * \ref asfdoc_samd20_sercom_usart_mux_settings.\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_special_considerations Special Considerations\r
+ *\r
+ * \if USART_CALLBACK_MODE\r
+ * Never execute large portions of code in the callbacks. These\r
+ * are run from the interrupt routine, and thus having long callbacks will\r
+ * keep the processor in the interrupt handler for an equally long time.\r
+ * A common way to handle this is to use global flags signaling the\r
+ * main application that an interrupt event has happened, and only do the\r
+ * minimal needed processing in the callback.\r
+ * \else\r
+ * No special considerations.\r
+ * \endif\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_extra_info Extra Information\r
+ *\r
+ * For extra information see \ref asfdoc_samd20_sercom_usart_extra. This includes:\r
+ * - \ref asfdoc_samd20_sercom_usart_extra_acronyms\r
+ * - \ref asfdoc_samd20_sercom_usart_extra_dependencies\r
+ * - \ref asfdoc_samd20_sercom_usart_extra_errata\r
+ * - \ref asfdoc_samd20_sercom_usart_extra_history\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_examples Examples\r
+ *\r
+ * For a list of examples related to this driver, see\r
+ * \ref asfdoc_samd20_sercom_usart_exqsg.\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_api_overview API Overview\r
+ * @{\r
+ */\r
+\r
+#include <sercom.h>\r
+#include <pinmux.h>\r
+\r
+#if USART_CALLBACK_MODE == true\r
+# include <sercom_interrupt.h>\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifndef PINMUX_DEFAULT\r
+# define PINMUX_DEFAULT 0\r
+#endif\r
+\r
+#ifndef PINMUX_UNUSED\r
+# define PINMUX_UNUSED 0xFFFFFFFF\r
+#endif\r
+\r
+#ifndef USART_TIMEOUT\r
+# define USART_TIMEOUT 0xFFFF\r
+#endif\r
+\r
+#if USART_CALLBACK_MODE == true\r
+/**\r
+ * \brief USART Callback enum\r
+ *\r
+ * Callbacks for the Asynchronous USART driver\r
+ */\r
+/* TODO: Add support for RX started interrupt. */\r
+enum usart_callback {\r
+ /** Callback for buffer transmitted */\r
+ USART_CALLBACK_BUFFER_TRANSMITTED,\r
+ /** Callback for buffer received */\r
+ USART_CALLBACK_BUFFER_RECEIVED,\r
+ /** Callback for error */\r
+ USART_CALLBACK_ERROR,\r
+# if !defined(__DOXYGEN__)\r
+ /** Number of available callbacks. */\r
+ USART_CALLBACK_N,\r
+# endif\r
+};\r
+#endif\r
+\r
+/**\r
+ * \brief USART Data Order enum\r
+ *\r
+ * The data order decides which of MSB or LSB is shifted out first when data is\r
+ * transferred\r
+ */\r
+enum usart_dataorder {\r
+ /** The MSB will be shifted out first during transmission,\r
+ * and shifted in first during reception */\r
+ USART_DATAORDER_MSB = 0,\r
+ /** The LSB will be shifted out first during transmission,\r
+ * and shifted in first during reception */\r
+ USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD,\r
+};\r
+\r
+/**\r
+ * \brief USART Transfer mode enum\r
+ *\r
+ * Select USART transfer mode\r
+ */\r
+enum usart_transfer_mode {\r
+ /** Transfer of data is done synchronously */\r
+ USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE),\r
+ /** Transfer of data is done asynchronously */\r
+ USART_TRANSFER_ASYNCHRONOUSLY = 0\r
+};\r
+\r
+/**\r
+ * \brief USART Parity enum\r
+ *\r
+ * Select parity USART parity mode\r
+ */\r
+enum usart_parity {\r
+ /** For odd parity checking, the parity bit will be set if number of\r
+ * ones being transferred is even */\r
+ USART_PARITY_ODD = SERCOM_USART_CTRLB_PMODE,\r
+\r
+ /** For even parity checking, the parity bit will be set if number of\r
+ * ones being received is odd */\r
+ USART_PARITY_EVEN = 0,\r
+\r
+ /** No parity checking will be executed, and there will be no parity bit\r
+ * in the received frame */\r
+ USART_PARITY_NONE = 0xFF,\r
+};\r
+\r
+/**\r
+ * \brief USART signal mux settings\r
+ *\r
+ * Set the functionality of the SERCOM pins.\r
+ */\r
+enum usart_signal_mux_settings {\r
+ /** See \ref asfdoc_samd20_sercom_usart_mux_setting_a */\r
+ USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)),\r
+ /** See \ref asfdoc_samd20_sercom_usart_mux_setting_b */\r
+ USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO),\r
+ /** See \ref asfdoc_samd20_sercom_usart_mux_setting_c */\r
+ USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)),\r
+ /** See \ref asfdoc_samd20_sercom_usart_mux_setting_d */\r
+ USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO),\r
+ /** See \ref asfdoc_samd20_sercom_usart_mux_setting_e */\r
+ USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)),\r
+ /** See \ref asfdoc_samd20_sercom_usart_mux_setting_f */\r
+ USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO),\r
+ /** See \ref asfdoc_samd20_sercom_usart_mux_setting_g */\r
+ USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)),\r
+ /** See \ref asfdoc_samd20_sercom_usart_mux_setting_h */\r
+ USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO),\r
+};\r
+\r
+/**\r
+ * \brief USART Stop Bits enum\r
+ *\r
+ * Number of stop bits for a frame.\r
+ */\r
+enum usart_stopbits {\r
+ /** Each transferred frame contains 1 stop bit */\r
+ USART_STOPBITS_1 = 0,\r
+ /** Each transferred frame contains 2 stop bits */\r
+ USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE,\r
+};\r
+\r
+/**\r
+ * \brief USART Character Size\r
+ *\r
+ * Number of bits for the character sent in a frame.\r
+ */\r
+enum usart_character_size {\r
+ /** The char being sent in a frame is 5 bits long */\r
+ USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5),\r
+ /** The char being sent in a frame is 6 bits long */\r
+ USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6),\r
+ /** The char being sent in a frame is 7 bits long */\r
+ USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7),\r
+ /** The char being sent in a frame is 8 bits long */\r
+ USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0),\r
+ /** The char being sent in a frame is 9 bits long */\r
+ USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1),\r
+};\r
+\r
+\r
+/**\r
+ * \brief USART Transceiver\r
+ *\r
+ * Select Receiver or Transmitter\r
+ */\r
+enum usart_transceiver_type {\r
+ /** The parameter is for the Receiver */\r
+ USART_TRANSCEIVER_RX,\r
+ /** The parameter is for the Transmitter */\r
+ USART_TRANSCEIVER_TX,\r
+};\r
+\r
+/**\r
+ * \brief USART configuration struct\r
+ *\r
+ * Configuration options for USART\r
+ */\r
+struct usart_config {\r
+ /** USART bit order (MSB or LSB first) */\r
+ enum usart_dataorder data_order;\r
+ /** USART in asynchronous or synchronous mode */\r
+ enum usart_transfer_mode transfer_mode;\r
+ /** USART parity */\r
+ enum usart_parity parity;\r
+ /** Number of stop bits */\r
+ enum usart_stopbits stopbits;\r
+ /** USART character size */\r
+ enum usart_character_size character_size;\r
+ /** USART pin out */\r
+ enum usart_signal_mux_settings mux_setting;\r
+ /** USART baud rate */\r
+ uint32_t baudrate;\r
+ /** Enable receiver */\r
+ bool receiver_enable;\r
+ /** Enable transmitter */\r
+ bool transmitter_enable;\r
+\r
+ /** USART Clock Polarity.\r
+ * If true, data changes on falling XCK edge and\r
+ * is sampled at rising edge.\r
+ * If false, data changes on rising XCK edge and\r
+ * is sampled at falling edge.\r
+ * */\r
+ bool clock_polarity_inverted;\r
+\r
+ /** States whether to use the external clock applied to the XCK pin.\r
+ * In synchronous mode the shift register will act directly on the XCK clock.\r
+ * In asynchronous mode the XCK will be the input to the USART hardware module.\r
+ */\r
+ bool use_external_clock;\r
+ /** External clock frequency in synchronous mode.\r
+ * This must be set if \c use_external_clock is true. */\r
+ uint32_t ext_clock_freq;\r
+ /** If true the USART will be kept running in Standby sleep mode */\r
+ bool run_in_standby;\r
+ /** GCLK generator source */\r
+ enum gclk_generator generator_source;\r
+ /** PAD0 pinmux */\r
+ uint32_t pinmux_pad0;\r
+ /** PAD1 pinmux */\r
+ uint32_t pinmux_pad1;\r
+ /** PAD2 pinmux */\r
+ uint32_t pinmux_pad2;\r
+ /** PAD3 pinmux */\r
+ uint32_t pinmux_pad3;\r
+};\r
+\r
+#if USART_CALLBACK_MODE == true\r
+/* Forward Declaration for the device instance */\r
+struct usart_module;\r
+\r
+/* Type of the callback functions */\r
+typedef void (*usart_callback_t)(const struct usart_module *const module);\r
+#endif\r
+\r
+/**\r
+ * \brief SERCOM USART driver software device instance structure.\r
+ *\r
+ * SERCOM USART driver software instance structure, used to retain software\r
+ * state information of an associated hardware module instance.\r
+ *\r
+ * \note The fields of this structure should not be altered by the user\r
+ * application; they are reserved for module-internal use only.\r
+ */\r
+struct usart_module {\r
+#if !defined(__DOXYGEN__)\r
+ /** Pointer to the hardware instance */\r
+ Sercom *hw;\r
+ /** Character size of the data being transferred */\r
+ enum usart_character_size character_size;\r
+ /** Receiver enabled */\r
+ bool receiver_enabled;\r
+ /** Transmitter enabled */\r
+ bool transmitter_enabled;\r
+# if USART_CALLBACK_MODE == true\r
+ /** Array to store callback function pointers in */\r
+ usart_callback_t callback[USART_CALLBACK_N];\r
+ /** Buffer pointer to where the next received character will be put */\r
+ volatile uint8_t *rx_buffer_ptr;\r
+\r
+ /** Buffer pointer to where the next character will be transmitted from\r
+ **/\r
+ volatile uint8_t *tx_buffer_ptr;\r
+ /** Remaining characters to receive */\r
+ volatile uint16_t remaining_rx_buffer_length;\r
+ /** Remaining characters to transmit */\r
+ volatile uint16_t remaining_tx_buffer_length;\r
+ /** Bit mask for callbacks registered */\r
+ uint8_t callback_reg_mask;\r
+ /** Bit mask for callbacks enabled */\r
+ uint8_t callback_enable_mask;\r
+ /** Holds the status of the ongoing or last read operation */\r
+ volatile enum status_code rx_status;\r
+ /** Holds the status of the ongoing or last write operation */\r
+ volatile enum status_code tx_status;\r
+# endif\r
+#endif\r
+};\r
+\r
+#if !defined (__DOXYGEN__)\r
+/**\r
+ * \internal\r
+ * Waits until synchronization is complete\r
+ */\r
+static inline void _usart_wait_for_sync(\r
+ const struct usart_module *const module)\r
+{\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ while (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY) {\r
+ /* Wait until the synchronization is complete */\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Check if peripheral is busy syncing registers across clock domains\r
+ *\r
+ * Return peripheral synchronization status. If doing a non-blocking\r
+ * implementation this function can be used to check the sync state and hold of\r
+ * any new actions until sync is complete. If this functions is not run; the\r
+ * functions will block until the sync has completed.\r
+ *\r
+ * \param[in] module Pointer to peripheral module\r
+ *\r
+ * \return Peripheral sync status\r
+ *\r
+ * \retval true Peripheral is busy syncing\r
+ * \retval false Peripheral is not busy syncing and can be read/written without\r
+ * stalling the bus.\r
+ */\r
+static inline bool usart_is_syncing(\r
+ const struct usart_module *const module)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ if(usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY) {\r
+ return true;\r
+ } else {\r
+ return false;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Initializes the device to predefined defaults\r
+ *\r
+ * Initialize the USART device to predefined defaults:\r
+ * - 8-bit asynchronous USART\r
+ * - No parity\r
+ * - 1 stop bit\r
+ * - 9600 baud\r
+ * - Transmitter enabled\r
+ * - Receiver enabled\r
+ * - GCLK generator 0 as clock source\r
+ * - Default pin configuration\r
+ *\r
+ * The configuration struct will be updated with the default\r
+ * configuration.\r
+ *\r
+ * \param[in,out] config Pointer to configuration struct\r
+ */\r
+static inline void usart_get_config_defaults(\r
+ struct usart_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(config);\r
+\r
+ /* Set default config in the config struct */\r
+ config->data_order = USART_DATAORDER_LSB;\r
+ config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY;\r
+ config->parity = USART_PARITY_NONE;\r
+ config->stopbits = USART_STOPBITS_1;\r
+ config->character_size = USART_CHARACTER_SIZE_8BIT;\r
+ config->baudrate = 9600;\r
+ config->receiver_enable = true;\r
+ config->transmitter_enable = true;\r
+ config->clock_polarity_inverted = false;\r
+ config->use_external_clock = false;\r
+ config->ext_clock_freq = 0;\r
+ config->mux_setting = USART_RX_1_TX_2_XCK_3;\r
+ config->run_in_standby = false;\r
+ config->generator_source = GCLK_GENERATOR_0;\r
+ config->pinmux_pad0 = PINMUX_DEFAULT;\r
+ config->pinmux_pad1 = PINMUX_DEFAULT;\r
+ config->pinmux_pad2 = PINMUX_DEFAULT;\r
+ config->pinmux_pad3 = PINMUX_DEFAULT;\r
+}\r
+\r
+enum status_code usart_init(\r
+ struct usart_module *const module,\r
+ Sercom *const hw,\r
+ const struct usart_config *const config);\r
+\r
+/**\r
+ * \brief Enable the module\r
+ *\r
+ * Enables the USART module\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ */\r
+static inline void usart_enable(\r
+ const struct usart_module *const module)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+#if USART_CALLBACK_MODE == true\r
+ /* Enable Global interrupt for module */\r
+ system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));\r
+#endif\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /* Enable USART module */\r
+ usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;\r
+}\r
+\r
+/**\r
+ * \brief Disable module\r
+ *\r
+ * Disables the USART module\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ */\r
+static inline void usart_disable(\r
+ const struct usart_module *const module)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Disable Global interrupt for module */\r
+ system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /* Disable USART module */\r
+ usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;\r
+}\r
+\r
+/**\r
+ * \brief Resets the USART module\r
+ *\r
+ * Disables and resets the USART module.\r
+ *\r
+ * \param[in] module Pointer to the USART software instance struct\r
+ */\r
+static inline void usart_reset(\r
+ const struct usart_module *const module)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ usart_disable(module);\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /* Reset module */\r
+ usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;\r
+}\r
+\r
+/**\r
+ * \name Writing and reading\r
+ * @{\r
+ */\r
+enum status_code usart_write_wait(\r
+ struct usart_module *const module,\r
+ const uint16_t tx_data);\r
+\r
+enum status_code usart_read_wait(\r
+ struct usart_module *const module,\r
+ uint16_t *const rx_data);\r
+\r
+enum status_code usart_write_buffer_wait(\r
+ struct usart_module *const module,\r
+ const uint8_t *tx_data,\r
+ uint16_t length);\r
+\r
+enum status_code usart_read_buffer_wait(\r
+ struct usart_module *const module,\r
+ uint8_t *rx_data,\r
+ uint16_t length);\r
+/** @} */\r
+\r
+/**\r
+ * \name Enabling/Disabling receiver and transmitter\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Enable Transceiver\r
+ *\r
+ * Enable the given transceiver. Either RX or TX.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] transceiver_type Transceiver type.\r
+ */\r
+static inline void usart_enable_transceiver(\r
+ struct usart_module *const module,\r
+ enum usart_transceiver_type transceiver_type)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ switch (transceiver_type) {\r
+ case USART_TRANSCEIVER_RX:\r
+ /* Enable RX */\r
+ usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;\r
+ module->receiver_enabled = true;\r
+ break;\r
+\r
+ case USART_TRANSCEIVER_TX:\r
+ /* Enable TX */\r
+ usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;\r
+ module->transmitter_enabled = true;\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable Transceiver\r
+ *\r
+ * Disable the given transceiver (RX or TX).\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] transceiver_type Transceiver type.\r
+ */\r
+static inline void usart_disable_transceiver(\r
+ struct usart_module *const module,\r
+ enum usart_transceiver_type transceiver_type)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Wait until synchronization is complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ switch (transceiver_type) {\r
+ case USART_TRANSCEIVER_RX:\r
+ /* Disable RX */\r
+ usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;\r
+ module->receiver_enabled = false;\r
+ break;\r
+\r
+ case USART_TRANSCEIVER_TX:\r
+ /* Disable TX */\r
+ usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;\r
+ module->transmitter_enabled = false;\r
+ break;\r
+ }\r
+}\r
+\r
+/** @} */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @} */\r
+\r
+/**\r
+* \page asfdoc_samd20_sercom_usart_extra Extra Information for SERCOM USART Driver\r
+*\r
+* \section asfdoc_samd20_sercom_usart_extra_acronyms Acronyms\r
+*\r
+* Below is a table listing the acronyms used in this module, along with their\r
+* intended meanings.\r
+*\r
+* <table>\r
+* <tr>\r
+* <th>Acronym</th>\r
+* <th>Description</th>\r
+* </tr>\r
+* <tr>\r
+* <td>SERCOM</td>\r
+* <td>Serial Communication Interface</td>\r
+* </tr>\r
+* <tr>\r
+* <td>USART</td>\r
+* <td>Universal Synchronous and Asynchronous Serial Receiver and Transmitter</td>\r
+* </tr>\r
+* <tr>\r
+* <td>LSB</td>\r
+* <td>Least Significant Bit</td>\r
+* </tr>\r
+* <tr>\r
+* <td>MSB</td>\r
+* <td>Most Significant Bit</td>\r
+* </tr>\r
+* </table>\r
+*\r
+*\r
+* \section asfdoc_samd20_sercom_usart_extra_dependencies Dependencies\r
+* This driver has the following dependencies:\r
+*\r
+* - \ref asfdoc_samd20_system_pinmux_group "System Pin Multiplexer Driver"\r
+* - \ref asfdoc_samd20_system_clock_group "System clock configuration"\r
+*\r
+*\r
+* \section asfdoc_samd20_sercom_usart_extra_errata Errata\r
+* There are no errata related to this driver.\r
+*\r
+*\r
+* \section asfdoc_samd20_sercom_usart_extra_history Module History\r
+* An overview of the module history is presented in the table below, with\r
+* details on the enhancements and fixes made to the module since its first\r
+* release. The current version of this corresponds to the newest version in\r
+* the table.\r
+*\r
+ * <table>\r
+ * <tr>\r
+ * <th>Changelog</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>\li Added new \c transmitter_enable and \c receiver_enable boolean\r
+ * values to \c struct usart_config.\r
+ * \li Altered \c usart_write_* and usart_read_* functions to abort with\r
+ * an error code if the relevant transceiver is not enabled.\r
+ * \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait()\r
+ * not aborting correctly when a timeout condition occurs.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Initial Release</td>\r
+ * </tr>\r
+ * </table>\r
+*/\r
+\r
+/**\r
+ * \page asfdoc_samd20_sercom_usart_exqsg Examples for SERCOM USART Driver\r
+ *\r
+ * This is a list of the available Quick Start guides (QSGs) and example\r
+ * applications for \ref asfdoc_samd20_sercom_usart_group. QSGs are simple examples with\r
+ * step-by-step instructions to configure and use this driver in a selection of\r
+ * use cases. Note that QSGs can be compiled as a standalone application or be\r
+ * added to the user application.\r
+ *\r
+ * - \subpage asfdoc_samd20_sercom_usart_basic_use_case\r
+ * \if USART_CALLBACK_MODE\r
+ * - \subpage asfdoc_samd20_sercom_usart_callback_use_case\r
+ * \endif\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_sercom_usart_mux_settings SERCOM USART MUX Settings\r
+ *\r
+ * The different options for functionality of the SERCOM pads.\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_mux_setting_a MUX Setting A\r
+ *\r
+ * Enum: \ref USART_RX_0_TX_0_XCK_1\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th> Function </th>\r
+ * <th> RX </th>\r
+ * <th> TX </th>\r
+ * <th> XCK </th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD0 </td>\r
+ * <td> x </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD1 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD2 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD3 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_mux_setting_b MUX Setting B\r
+ *\r
+ * Enum: \ref USART_RX_0_TX_2_XCK_3\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th> Function </th>\r
+ * <th> RX </th>\r
+ * <th> TX </th>\r
+ * <th> XCK </th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD0 </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD1 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD2 </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD3 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_mux_setting_c MUX Setting C\r
+ *\r
+ * Enum: \ref USART_RX_1_TX_0_XCK_1\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th> Function </th>\r
+ * <th> RX </th>\r
+ * <th> TX </th>\r
+ * <th> XCK </th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD0 </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD1 </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD2 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD3 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_mux_setting_d MUX Setting D\r
+ *\r
+ * Enum: \ref USART_RX_1_TX_2_XCK_3\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th> Function </th>\r
+ * <th> RX </th>\r
+ * <th> TX </th>\r
+ * <th> XCK </th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD0 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD1 </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD2 </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD3 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_mux_setting_e MUX Setting E\r
+ *\r
+ * Enum: \ref USART_RX_2_TX_0_XCK_1\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th> Function </th>\r
+ * <th> RX </th>\r
+ * <th> TX </th>\r
+ * <th> XCK </th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD0 </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD1 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD2 </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD3 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_mux_setting_f MUX Setting F\r
+ *\r
+ * Enum: \ref USART_RX_2_TX_2_XCK_3\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th> Function </th>\r
+ * <th> RX </th>\r
+ * <th> TX </th>\r
+ * <th> XCK </th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD0 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD1 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD2 </td>\r
+ * <td> x </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD3 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_mux_setting_g MUX Setting G\r
+ *\r
+ * Enum: \ref USART_RX_3_TX_0_XCK_1\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th> Function </th>\r
+ * <th> RX </th>\r
+ * <th> TX </th>\r
+ * <th> XCK </th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD0 </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD1 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD2 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD3 </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \section asfdoc_samd20_sercom_usart_mux_setting_h MUX Setting H\r
+ *\r
+ * Enum: \ref USART_RX_3_TX_2_XCK_3\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th> Function </th>\r
+ * <th> RX </th>\r
+ * <th> TX </th>\r
+ * <th> XCK </th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD0 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD1 </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD2 </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td> PAD3 </td>\r
+ * <td> x </td>\r
+ * <td> </td>\r
+ * <td> x </td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \page asfdoc_samd20_sercom_usart_document_revision_history Document Revision History\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Doc. Rev.</td>\r
+ * <th>Date</td>\r
+ * <th>Comments</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>B</td>\r
+ * <td>06/2013</td>\r
+ * <td>Corrected documentation typos.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>A</td>\r
+ * <td>06/2013</td>\r
+ * <td>Initial release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+#endif /* USART_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 SERCOM USART Asynchronous Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "usart_interrupt.h"\r
+\r
+/**\r
+ * \internal\r
+ * Asynchronous write of a buffer with a given length\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] tx_data Pointer to data to be transmitted\r
+ * \param[in] length Length of data buffer\r
+ *\r
+ */\r
+void _usart_write_buffer(\r
+ struct usart_module *const module,\r
+ uint8_t *tx_data,\r
+ uint16_t length)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Write parameters to the device instance */\r
+ module->remaining_tx_buffer_length = length;\r
+ module->tx_buffer_ptr = tx_data;\r
+ module->tx_status = STATUS_BUSY;\r
+\r
+ /* Enable the Data Register Empty Interrupt */\r
+ usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;\r
+}\r
+\r
+/**\r
+ * \internal\r
+ * Asynchronous read of a buffer with a given length\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] rx_data Pointer to data to be received\r
+ * \param[in] length Length of data buffer\r
+ *\r
+ */\r
+void _usart_read_buffer(\r
+ struct usart_module *const module,\r
+ uint8_t *rx_data,\r
+ uint16_t length)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ /* Set length for the buffer and the pointer, and let\r
+ * the interrupt handler do the rest */\r
+ module->remaining_rx_buffer_length = length;\r
+ module->rx_buffer_ptr = rx_data;\r
+ module->rx_status = STATUS_BUSY;\r
+\r
+ /* Enable the RX Complete Interrupt */\r
+ usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;\r
+}\r
+\r
+/**\r
+ * \brief Registers a callback\r
+ *\r
+ * Registers a callback function which is implemented by the user.\r
+ *\r
+ * \note The callback must be enabled by \ref usart_enable_callback,\r
+ * in order for the interrupt handler to call it when the conditions for\r
+ * the callback type are met.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] callback_func Pointer to callback function\r
+ * \param[in] callback_type Callback type given by an enum\r
+ *\r
+ */\r
+void usart_register_callback(\r
+ struct usart_module *const module,\r
+ usart_callback_t callback_func,\r
+ enum usart_callback callback_type)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(callback_func);\r
+\r
+ /* Register callback function */\r
+ module->callback[callback_type] = callback_func;\r
+\r
+ /* Set the bit corresponding to the callback_type */\r
+ module->callback_reg_mask |= (1 << callback_type);\r
+}\r
+\r
+/**\r
+ * \brief Unregisters a callback\r
+ *\r
+ * Unregisters a callback function which is implemented by the user.\r
+ *\r
+ * \param[in,out] module Pointer to USART software instance struct\r
+ * \param[in] callback_type Callback type given by an enum\r
+ *\r
+ */\r
+void usart_unregister_callback(\r
+ struct usart_module *const module,\r
+ enum usart_callback callback_type)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+\r
+ /* Unregister callback function */\r
+ module->callback[callback_type] = NULL;\r
+\r
+ /* Clear the bit corresponding to the callback_type */\r
+ module->callback_reg_mask &= ~(1 << callback_type);\r
+}\r
+\r
+/**\r
+ * \brief Asynchronous write a single char\r
+ *\r
+ * Sets up the driver to write the data given. If registered and enabled,\r
+ * a callback function will be called when the transmit is completed.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] tx_data Data to transfer\r
+ *\r
+ * \returns Status of the operation\r
+ * \retval STATUS_OK If operation was completed\r
+ * \retval STATUS_BUSY If operation was not completed, due to the\r
+ * USART module being busy\r
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled\r
+ */\r
+enum status_code usart_write_job(\r
+ struct usart_module *const module,\r
+ const uint16_t tx_data)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+ /* Check if the USART transmitter is busy */\r
+ if (module->remaining_tx_buffer_length > 0) {\r
+ return STATUS_BUSY;\r
+ }\r
+\r
+ /* Check that the transmitter is enabled */\r
+ if (!(module->transmitter_enabled)) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* Call internal write buffer function with length 1 */\r
+ _usart_write_buffer(module, (uint8_t *)&tx_data, 1);\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Asynchronous read a single char\r
+ *\r
+ * Sets up the driver to read data from the USART module to the data\r
+ * pointer given. If registered and enabled, a callback will be called\r
+ * when the receiving is completed.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[out] rx_data Pointer to where received data should be put\r
+ *\r
+ * \returns Status of the operation\r
+ * \retval STATUS_OK If operation was completed\r
+ * \retval STATUS_BUSY If operation was not completed,\r
+ */\r
+enum status_code usart_read_job(\r
+ struct usart_module *const module,\r
+ uint16_t *const rx_data)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+\r
+ /* Check if the USART receiver is busy */\r
+ if (module->remaining_rx_buffer_length > 0) {\r
+ return STATUS_BUSY;\r
+ }\r
+\r
+ /* Call internal read buffer function with length 1 */\r
+ _usart_read_buffer(module, (uint8_t *)rx_data, 1);\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Asynchronous buffer write\r
+ *\r
+ * Sets up the driver to write a given buffer over the USART. If registered and\r
+ * enabled, a callback function will be called.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] tx_data Pointer do data buffer to transmit\r
+ * \param[in] length Length of the data to transmit\r
+ *\r
+ * \returns Status of the operation\r
+ * \retval STATUS_OK If operation was completed successfully.\r
+ * \retval STATUS_BUSY If operation was not completed, due to the\r
+ * USART module being busy\r
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid\r
+ * arguments\r
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled\r
+ */\r
+enum status_code usart_write_buffer_job(\r
+ struct usart_module *const module,\r
+ uint8_t *tx_data,\r
+ uint16_t length)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+\r
+ if (length == 0) {\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ /* Check if the USART transmitter is busy */\r
+ if (module->remaining_tx_buffer_length > 0) {\r
+ return STATUS_BUSY;\r
+ }\r
+ \r
+ /* Check that the receiver is enabled */\r
+ if (!(module->transmitter_enabled)) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* Issue internal asynchronous write */\r
+ _usart_write_buffer(module, tx_data, length);\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Asynchronous buffer read\r
+ *\r
+ * Sets up the driver to read from the USART to a given buffer. If registered\r
+ * and enabled, a callback function will be called.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[out] rx_data Pointer to data buffer to receive\r
+ * \param[in] length Data buffer length\r
+ *\r
+ * \returns Status of the operation\r
+ * \retval STATUS_OK If operation was completed\r
+ * \retval STATUS_BUSY If operation was not completed, due to the\r
+ * USART module being busy\r
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid\r
+ * arguments\r
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled\r
+ */\r
+enum status_code usart_read_buffer_job(\r
+ struct usart_module *const module,\r
+ uint8_t *rx_data,\r
+ uint16_t length)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(rx_data);\r
+\r
+ if (length == 0) {\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+ \r
+ /* Check that the receiver is enabled */\r
+ if (!(module->receiver_enabled)) {\r
+ return STATUS_ERR_DENIED;\r
+ }\r
+\r
+ /* Check if the USART receiver is busy */\r
+ if (module->remaining_rx_buffer_length > 0) {\r
+ return STATUS_BUSY;\r
+ }\r
+\r
+ /* Issue internal asynchronous read */\r
+ _usart_read_buffer(module, rx_data, length);\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Cancels ongoing read/write operation\r
+ *\r
+ * Cancels the ongoing read/write operation modifying parameters in the\r
+ * USART software struct.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] transceiver_type Transfer type to cancel\r
+ */\r
+void usart_abort_job(\r
+ struct usart_module *const module,\r
+ enum usart_transceiver_type transceiver_type)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+ Assert(module->hw);\r
+\r
+ /* Get a pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw = &(module->hw->USART);\r
+\r
+ switch(transceiver_type) {\r
+ case USART_TRANSCEIVER_RX:\r
+ /* Clear the interrupt flag in order to prevent the receive\r
+ * complete callback to fire */\r
+ usart_hw->INTFLAG.reg |= SERCOM_USART_INTFLAG_RXC;\r
+\r
+ /* Clear the software reception buffer */\r
+ module->remaining_rx_buffer_length = 0;\r
+\r
+ break;\r
+\r
+ case USART_TRANSCEIVER_TX:\r
+ /* Clear the interrupt flag in order to prevent the receive\r
+ * complete callback to fire */\r
+ usart_hw->INTFLAG.reg |= SERCOM_USART_INTFLAG_TXC;\r
+\r
+ /* Clear the software reception buffer */\r
+ module->remaining_tx_buffer_length = 0;\r
+\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get status from the ongoing or last asynchronous transfer operation\r
+ *\r
+ * Returns the error from a given ongoing or last asynchronous transfer operation.\r
+ * Either from a read or write transfer.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] transceiver_type Transfer type to check\r
+ *\r
+ * \return Status of the given job.\r
+ * \retval STATUS_OK No error occurred during the last transfer\r
+ * \retval STATUS_BUSY A transfer is ongoing\r
+ * \retval STATUS_ERR_BAD_DATA The last operation was aborted due to a\r
+ * parity error. The transfer could be affected\r
+ * by external noise.\r
+ * \retval STATUS_ERR_BAD_FORMAT The last operation was aborted due to a\r
+ * frame error.\r
+ * \retval STATUS_ERR_OVERFLOW The last operation was aborted due to a\r
+ * buffer overflow.\r
+ * \retval STATUS_ERR_INVALID_ARG An invalid transceiver enum given.\r
+ */\r
+enum status_code usart_get_job_status(\r
+ struct usart_module *const module,\r
+ enum usart_transceiver_type transceiver_type)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+\r
+ /* Variable for status code */\r
+ enum status_code status_code;\r
+\r
+ switch(transceiver_type) {\r
+ case USART_TRANSCEIVER_RX:\r
+ status_code = module->rx_status;\r
+ break;\r
+\r
+ case USART_TRANSCEIVER_TX:\r
+ status_code = module->tx_status;\r
+ break;\r
+\r
+ default:\r
+ status_code = STATUS_ERR_INVALID_ARG;\r
+ break;\r
+ }\r
+\r
+ return status_code;\r
+}\r
+\r
+/**\r
+ * \internal\r
+ * Handles interrupts as they occur, and it will run callback functions\r
+ * which are registered and enabled.\r
+ *\r
+ * \param[in] instance ID of the SERCOM instance calling the interrupt\r
+ * handler.\r
+ */\r
+void _usart_interrupt_handler(\r
+ uint8_t instance)\r
+{\r
+ /* Temporary variables */\r
+ uint16_t interrupt_status;\r
+ uint16_t callback_status;\r
+ uint8_t error_code;\r
+\r
+\r
+ /* Get device instance from the look-up table */\r
+ struct usart_module *module\r
+ = (struct usart_module *)_sercom_instances[instance];\r
+\r
+ /* Pointer to the hardware module instance */\r
+ SercomUsart *const usart_hw\r
+ = &(module->hw->USART);\r
+\r
+ /* Wait for the synchronization to complete */\r
+ _usart_wait_for_sync(module);\r
+\r
+ /* Read and mask interrupt flag register */\r
+ interrupt_status = usart_hw->INTFLAG.reg;\r
+ callback_status = module->callback_reg_mask\r
+ &module->callback_enable_mask;\r
+\r
+ /* Check if a DATA READY interrupt has occurred,\r
+ * and if there is more to transfer */\r
+ if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {\r
+ if (module->remaining_tx_buffer_length) {\r
+ /* Write value will be at least 8-bits long */\r
+ uint16_t data_to_send = *(module->tx_buffer_ptr);\r
+ /* Increment 8-bit pointer */\r
+ (module->tx_buffer_ptr)++;\r
+\r
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {\r
+ data_to_send = (*(module->tx_buffer_ptr) << 8);\r
+ /* Increment 8-bit pointer */\r
+ (module->tx_buffer_ptr)++;\r
+ }\r
+ /* Write the data to send */\r
+ usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);\r
+\r
+ if (--(module->remaining_tx_buffer_length) == 0) {\r
+ /* Disable the Data Register Empty Interrupt */\r
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;\r
+ /* Enable Transmission Complete interrupt */\r
+ usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;\r
+\r
+ }\r
+ } else {\r
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;\r
+ }\r
+\r
+ /* Check if the Transmission Complete interrupt has occurred and\r
+ * that the transmit buffer is empty */\r
+ }\r
+ if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {\r
+\r
+ /* Disable TX Complete Interrupt, and set STATUS_OK */\r
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;\r
+ module->tx_status = STATUS_OK;\r
+\r
+ /* Run callback if registered and enabled */\r
+ if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {\r
+ (*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);\r
+ }\r
+\r
+ /* Check if the Receive Complete interrupt has occurred, and that\r
+ * there's more data to receive */\r
+ }\r
+ if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {\r
+\r
+ if (module->remaining_rx_buffer_length) {\r
+ /* Read out the status code and mask away all but the 4 LSBs*/\r
+ error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);\r
+\r
+ /* Check if an error has occurred during the receiving */\r
+ if (error_code) {\r
+ /* Check which error occurred */\r
+ if (error_code & SERCOM_USART_STATUS_FERR) {\r
+ /* Store the error code and clear flag by writing 1 to it */\r
+ module->rx_status = STATUS_ERR_BAD_FORMAT;\r
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_FERR;\r
+ } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {\r
+ /* Store the error code and clear flag by writing 1 to it */\r
+ module->rx_status = STATUS_ERR_OVERFLOW;\r
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF;\r
+ } else if (error_code & SERCOM_USART_STATUS_PERR) {\r
+ /* Store the error code and clear flag by writing 1 to it */\r
+ module->rx_status = STATUS_ERR_BAD_DATA;\r
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_PERR;\r
+ }\r
+\r
+ /* Run callback if registered and enabled */\r
+ if (callback_status\r
+ & (1 << USART_CALLBACK_ERROR)) {\r
+ (*(module->callback[USART_CALLBACK_ERROR]))(module);\r
+ }\r
+\r
+ } else {\r
+\r
+ /* Read current packet from DATA register,\r
+ * increment buffer pointer and decrement buffer length */\r
+ uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);\r
+\r
+ /* Read value will be at least 8-bits long */\r
+ *(module->rx_buffer_ptr) = received_data;\r
+ /* Increment 8-bit pointer */\r
+ module->rx_buffer_ptr += 1;\r
+\r
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {\r
+ /* 9-bit data, write next received byte to the buffer */\r
+ *(module->rx_buffer_ptr) = (received_data >> 8);\r
+ /* Increment 8-bit pointer */\r
+ module->rx_buffer_ptr += 1;\r
+ }\r
+\r
+ /* Check if the last character have been received */\r
+ if(--(module->remaining_rx_buffer_length) == 0) {\r
+ /* Disable RX Complete Interrupt,\r
+ * and set STATUS_OK */\r
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;\r
+ module->rx_status = STATUS_OK;\r
+\r
+ /* Run callback if registered and enabled */\r
+ if (callback_status\r
+ & (1 << USART_CALLBACK_BUFFER_RECEIVED)) {\r
+ (*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);\r
+ }\r
+ }\r
+ }\r
+ } else {\r
+ /* This should not happen. Disable Receive Complete interrupt. */\r
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 SERCOM USART Asynchronous Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef USART_INTERRUPT_H_INCLUDED\r
+#define USART_INTERRUPT_H_INCLUDED\r
+\r
+#include "usart.h"\r
+\r
+#if !defined(__DOXYGEN__)\r
+void _usart_write_buffer(\r
+ struct usart_module *const module,\r
+ uint8_t *tx_data,\r
+ uint16_t length);\r
+\r
+void _usart_read_buffer(\r
+ struct usart_module *const module,\r
+ uint8_t *rx_data,\r
+ uint16_t length);\r
+\r
+void _usart_interrupt_handler(\r
+ uint8_t instance);\r
+#endif\r
+\r
+/**\r
+ * \addtogroup asfdoc_samd20_sercom_usart_group\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Callback Management\r
+ * @{\r
+ */\r
+void usart_register_callback(\r
+ struct usart_module *const module,\r
+ usart_callback_t callback_func,\r
+ enum usart_callback callback_type);\r
+\r
+void usart_unregister_callback(\r
+ struct usart_module *module,\r
+ enum usart_callback callback_type);\r
+\r
+/**\r
+ * \brief Enables callback\r
+ *\r
+ * Enables the callback function registered by the \ref usart_register_callback.\r
+ * The callback function will be called from the interrupt handler when the\r
+ * conditions for the callback type are met.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] callback_type Callback type given by an enum\r
+ */\r
+static inline void usart_enable_callback(\r
+ struct usart_module *const module,\r
+ enum usart_callback callback_type)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+\r
+ /* Enable callback */\r
+ module->callback_enable_mask |= (1 << callback_type);\r
+\r
+}\r
+\r
+/**\r
+ * \brief Disable callback\r
+ *\r
+ * Disables the callback function registered by the \ref usart_register_callback,\r
+ * and the callback will not be called from the interrupt routine.\r
+ *\r
+ * \param[in] module Pointer to USART software instance struct\r
+ * \param[in] callback_type Callback type given by an enum\r
+ */\r
+static inline void usart_disable_callback(\r
+ struct usart_module *const module,\r
+ enum usart_callback callback_type)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(module);\r
+\r
+ /* Disable callback */\r
+ module->callback_enable_mask &= ~(1 << callback_type);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \name Writing and reading\r
+ * @{\r
+ */\r
+enum status_code usart_write_job(\r
+ struct usart_module *const module,\r
+ const uint16_t tx_data);\r
+\r
+enum status_code usart_read_job(\r
+ struct usart_module *const module,\r
+ uint16_t *const rx_data);\r
+\r
+enum status_code usart_write_buffer_job(\r
+ struct usart_module *const module,\r
+ uint8_t *tx_data,\r
+ uint16_t length);\r
+\r
+enum status_code usart_read_buffer_job(\r
+ struct usart_module *const module,\r
+ uint8_t *rx_data,\r
+ uint16_t length);\r
+\r
+void usart_abort_job(\r
+ struct usart_module *const module,\r
+ enum usart_transceiver_type transceiver_type);\r
+\r
+enum status_code usart_get_job_status(\r
+ struct usart_module *const module,\r
+ enum usart_transceiver_type transceiver_type);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* USART_INTERRUPT_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Clock Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include <clock.h>\r
+#include <conf_clocks.h>\r
+\r
+/**\r
+ * \internal\r
+ * \brief DFLL-specific data container\r
+ */\r
+struct _system_clock_dfll_config {\r
+ uint32_t control;\r
+ uint32_t val;\r
+ uint32_t mul;\r
+};\r
+\r
+/**\r
+ * \internal\r
+ * \brief XOSC-specific data container\r
+ */\r
+struct _system_clock_xosc_config {\r
+ uint32_t frequency;\r
+};\r
+\r
+/**\r
+ * \internal\r
+ * \brief System clock module data container\r
+ */\r
+struct _system_clock_module {\r
+ volatile struct _system_clock_dfll_config dfll;\r
+ volatile struct _system_clock_xosc_config xosc;\r
+ volatile struct _system_clock_xosc_config xosc32k;\r
+};\r
+\r
+/**\r
+ * \internal\r
+ * \brief Internal module instance to cache configuration values\r
+ */\r
+static struct _system_clock_module _system_clock_inst = {\r
+ .dfll = {\r
+ .control = 0,\r
+ .val = 0,\r
+ .mul = 0,\r
+ },\r
+ .xosc = {\r
+ .frequency = 0,\r
+ },\r
+ .xosc32k = {\r
+ .frequency = 0,\r
+ },\r
+ };\r
+\r
+/**\r
+ * \internal\r
+ * \brief Wait for sync to the DFLL control registers\r
+ */\r
+static inline void _system_dfll_wait_for_sync(void)\r
+{\r
+ while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {\r
+ /* Wait for DFLL sync */\r
+ }\r
+}\r
+\r
+/**\r
+ * \internal\r
+ * \brief Wait for sync to the OSC32K control registers\r
+ */\r
+static inline void _system_osc32k_wait_for_sync(void)\r
+{\r
+ while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {\r
+ /* Wait for OSC32K sync */\r
+ }\r
+}\r
+\r
+static inline void _system_clock_source_dfll_set_config_errata_9905(void)\r
+{\r
+\r
+ /* Disable ONDEMAND mode while writing configurations */\r
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND;\r
+ _system_dfll_wait_for_sync();\r
+\r
+ SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;\r
+ SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;\r
+\r
+ /* Write full configuration to DFLL control register */\r
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;\r
+}\r
+\r
+/**\r
+ * \brief Retrieve the frequency of a clock source\r
+ *\r
+ * Determines the current operating frequency of a given clock source.\r
+ *\r
+ * \param[in] clock_source Clock source to get the frequency of\r
+ *\r
+ * \returns Frequency of the given clock source, in Hz\r
+ */\r
+uint32_t system_clock_source_get_hz(\r
+ const enum system_clock_source clock_source)\r
+{\r
+ switch (clock_source) {\r
+ case SYSTEM_CLOCK_SOURCE_XOSC:\r
+ return _system_clock_inst.xosc.frequency;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_OSC8M:\r
+ return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_OSC32K:\r
+ return 32768UL;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_ULP32K:\r
+ return 32768UL;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:\r
+ return _system_clock_inst.xosc32k.frequency;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_DFLL:\r
+\r
+ /* Check if the DFLL has been configured */\r
+ if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))\r
+ return 0;\r
+\r
+ /* Make sure that the DFLL module is ready */\r
+ _system_dfll_wait_for_sync();\r
+\r
+ /* Check if operating in closed loop mode */\r
+ if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) {\r
+ return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *\r
+ (_system_clock_inst.dfll.mul & 0xffff);\r
+ }\r
+\r
+ return 48000000UL;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure the internal OSC8M oscillator clock source\r
+ *\r
+ * Configures the 8MHz (nominal) internal RC oscillator with the given\r
+ * configuration settings.\r
+ *\r
+ * \param[in] config OSC8M configuration structure containing the new config\r
+ */\r
+void system_clock_source_osc8m_set_config(\r
+ struct system_clock_source_osc8m_config *const config)\r
+{\r
+ SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;\r
+\r
+ /* Use temporary struct to reduce register access */\r
+ temp.bit.PRESC = config->prescaler;\r
+ temp.bit.ONDEMAND = config->on_demand;\r
+ temp.bit.RUNSTDBY = config->run_in_standby;\r
+\r
+ SYSCTRL->OSC8M = temp;\r
+}\r
+\r
+/**\r
+ * \brief Configure the internal OSC32K oscillator clock source\r
+ *\r
+ * Configures the 32KHz (nominal) internal RC oscillator with the given\r
+ * configuration settings.\r
+ *\r
+ * \param[in] config OSC32K configuration structure containing the new config\r
+ */\r
+void system_clock_source_osc32k_set_config(\r
+ struct system_clock_source_osc32k_config *const config)\r
+{\r
+ SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;\r
+\r
+ /* Update settings via a temporary struct to reduce register access */\r
+ temp.bit.EN1K = config->enable_1khz_output;\r
+ temp.bit.EN32K = config->enable_32khz_output;\r
+ temp.bit.STARTUP = config->startup_time;\r
+ temp.bit.ONDEMAND = config->on_demand;\r
+ temp.bit.RUNSTDBY = config->run_in_standby;\r
+\r
+ SYSCTRL->OSC32K = temp;\r
+}\r
+\r
+/**\r
+ * \brief Configure the external oscillator clock source\r
+ *\r
+ * Configures the external oscillator clock source with the given configuration\r
+ * settings.\r
+ *\r
+ * \param[in] config External oscillator configuration structure containing\r
+ * the new config\r
+ */\r
+void system_clock_source_xosc_set_config(\r
+ struct system_clock_source_xosc_config *const config)\r
+{\r
+ SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;\r
+\r
+ temp.bit.STARTUP = config->startup_time;\r
+\r
+ if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {\r
+ temp.bit.XTALEN = 1;\r
+ } else {\r
+ temp.bit.XTALEN = 0;\r
+ }\r
+\r
+ temp.bit.AMPGC = config->auto_gain_control;\r
+\r
+ /* Set gain if automatic gain control is not selected */\r
+ if (!config->auto_gain_control) {\r
+ if (config->frequency <= 2000000) {\r
+ temp.bit.GAIN = 0;\r
+ } else if (config->frequency <= 4000000) {\r
+ temp.bit.GAIN = 1;\r
+ } else if (config->frequency <= 8000000) {\r
+ temp.bit.GAIN = 2;\r
+ } else if (config->frequency <= 16000000) {\r
+ temp.bit.GAIN = 3;\r
+ } else if (config->frequency <= 30000000) {\r
+ temp.bit.GAIN = 4;\r
+ }\r
+\r
+ }\r
+\r
+ temp.bit.ONDEMAND = config->on_demand;\r
+ temp.bit.RUNSTDBY = config->run_in_standby;\r
+\r
+ /* Store XOSC frequency for internal use */\r
+ _system_clock_inst.xosc.frequency = config->frequency;\r
+\r
+ SYSCTRL->XOSC = temp;\r
+}\r
+\r
+/**\r
+ * \brief Configure the XOSC32K external 32KHz oscillator clock source\r
+ *\r
+ * Configures the external 32KHz oscillator clock source with the given\r
+ * configuration settings.\r
+ *\r
+ * \param[in] config XOSC32K configuration structure containing the new config\r
+ */\r
+void system_clock_source_xosc32k_set_config(\r
+ struct system_clock_source_xosc32k_config *const config)\r
+{\r
+ SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;\r
+\r
+ temp.bit.STARTUP = config->startup_time;\r
+\r
+ if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {\r
+ temp.bit.XTALEN = 1;\r
+ } else {\r
+ temp.bit.XTALEN = 0;\r
+ }\r
+\r
+ temp.bit.AAMPEN = config->auto_gain_control;\r
+ temp.bit.EN1K = config->enable_1khz_output;\r
+ temp.bit.EN32K = config->enable_32khz_output;\r
+\r
+ temp.bit.ONDEMAND = config->on_demand;\r
+ temp.bit.RUNSTDBY = config->run_in_standby;\r
+\r
+ /* Cache the new frequency in case the user needs to check the current\r
+ * operating frequency later */\r
+ _system_clock_inst.xosc32k.frequency = config->frequency;\r
+\r
+ SYSCTRL->XOSC32K = temp;\r
+}\r
+\r
+/**\r
+ * \brief Configure the DFLL clock source\r
+ *\r
+ * Configures the Digital Frequency Locked Loop clock source with the given\r
+ * configuration settings.\r
+ *\r
+ * \note The DFLL will be running when this function returns, as the DFLL module\r
+ * needs to be enabled in order to perform the module configuration.\r
+ *\r
+ * \param[in] config DFLL configuration structure containing the new config\r
+ */\r
+void system_clock_source_dfll_set_config(\r
+ struct system_clock_source_dfll_config *const config)\r
+{\r
+ _system_clock_inst.dfll.val =\r
+ SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |\r
+ SYSCTRL_DFLLVAL_FINE(config->fine_value);\r
+\r
+ _system_clock_inst.dfll.control =\r
+ (uint32_t)config->wakeup_lock |\r
+ (uint32_t)config->stable_tracking |\r
+ (uint32_t)config->quick_lock |\r
+ (uint32_t)config->chill_cycle |\r
+ (uint32_t)config->run_in_standby << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos |\r
+ (uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos;\r
+\r
+ if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {\r
+ _system_clock_inst.dfll.mul =\r
+ SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |\r
+ SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) |\r
+ SYSCTRL_DFLLMUL_MUL(config->multiply_factor);\r
+\r
+ /* Enable the closed loop mode */\r
+ _system_clock_inst.dfll.control |= config->loop_mode;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Writes the calibration values for a given oscillator clock source\r
+ *\r
+ * Writes an oscillator calibration value to the given oscillator control\r
+ * registers. The acceptable ranges are:\r
+ *\r
+ * For OSC32K:\r
+ * - 7 bits (max value 128)\r
+ * For OSC8MHZ:\r
+ * - 8 bits (Max value 255)\r
+ * For OSCULP:\r
+ * - 5 bits (Max value 32)\r
+ *\r
+ * \note The frequency range parameter applies only when configuring the 8MHz\r
+ * oscillator and will be ignored for the other oscillators.\r
+ *\r
+ * \param[in] clock_source Clock source to calibrate\r
+ * \param[in] calibration_value Calibration value to write\r
+ * \param[in] freq_range Frequency range (8MHz oscillator only)\r
+ *\r
+ * \retval STATUS_ERR_INVALID_ARG The selected clock source is not available\r
+ */\r
+enum status_code system_clock_source_write_calibration(\r
+ const enum system_clock_source clock_source,\r
+ const uint16_t calibration_value,\r
+ const uint8_t freq_range)\r
+{\r
+ switch (clock_source) {\r
+ case SYSTEM_CLOCK_SOURCE_OSC8M:\r
+\r
+ if (calibration_value > 0xfff || freq_range > 4) {\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ SYSCTRL->OSC8M.bit.CALIB = calibration_value;\r
+ SYSCTRL->OSC8M.bit.FRANGE = freq_range;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_OSC32K:\r
+\r
+ if (calibration_value > 128) {\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ _system_osc32k_wait_for_sync();\r
+ SYSCTRL->OSC32K.bit.CALIB = calibration_value;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_ULP32K:\r
+\r
+ if (calibration_value > 32) {\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ return STATUS_ERR_INVALID_ARG;\r
+ break;\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Enables a clock source\r
+ *\r
+ * Enables a clock source which has been previously configured.\r
+ *\r
+ * \param[in] clock_source Clock source to enable\r
+ *\r
+ * \retval STATUS_OK Clock source was enabled successfully and\r
+ * is ready\r
+ * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this\r
+ * device\r
+ *\r
+ * \retval STATUS_ERR_NOT_INITIALIZED DFLL configuration is not initialized\r
+ */\r
+enum status_code system_clock_source_enable(\r
+ const enum system_clock_source clock_source)\r
+{\r
+ switch (clock_source) {\r
+ case SYSTEM_CLOCK_SOURCE_OSC8M:\r
+ SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;\r
+ return STATUS_OK;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_OSC32K:\r
+ SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_XOSC:\r
+ SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:\r
+ SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_DFLL:\r
+ _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;\r
+ _system_clock_source_dfll_set_config_errata_9905();\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_ULP32K:\r
+ /* Always enabled */\r
+ return STATUS_OK;\r
+\r
+ default:\r
+ Assert(false);\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Disables a clock source\r
+ *\r
+ * Disables a clock source that was previously enabled.\r
+ *\r
+ * \param[in] clock_source Clock source to disable\r
+ *\r
+ * \retval STATUS_OK Clock source was disabled successfully\r
+ * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was\r
+ * given\r
+ */\r
+enum status_code system_clock_source_disable(\r
+ const enum system_clock_source clock_source)\r
+{\r
+ switch (clock_source) {\r
+ case SYSTEM_CLOCK_SOURCE_OSC8M:\r
+ SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_OSC32K:\r
+ SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_XOSC:\r
+ SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:\r
+ SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_DFLL:\r
+ _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;\r
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_ULP32K:\r
+ /* Not possible to disable */\r
+ return STATUS_ERR_INVALID_ARG;\r
+\r
+ default:\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Checks if a clock source is ready\r
+ *\r
+ * Checks if a given clock source is ready to be used.\r
+ *\r
+ * \param[in] clock_source Clock source to check if ready\r
+ *\r
+ * \returns Ready state of the given clock source.\r
+ *\r
+ * \retval true Clock source is enabled and ready\r
+ * \retval false Clock source is disabled or not yet ready\r
+ */\r
+bool system_clock_source_is_ready(\r
+ const enum system_clock_source clock_source)\r
+{\r
+ uint32_t mask;\r
+\r
+ switch (clock_source) {\r
+ case SYSTEM_CLOCK_SOURCE_OSC8M:\r
+ mask = SYSCTRL_PCLKSR_OSC8MRDY;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_OSC32K:\r
+ mask = SYSCTRL_PCLKSR_OSC32KRDY;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_XOSC:\r
+ mask = SYSCTRL_PCLKSR_XOSCRDY;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:\r
+ mask = SYSCTRL_PCLKSR_XOSC32KRDY;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_DFLL:\r
+ mask = SYSCTRL_PCLKSR_DFLLRDY;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_SOURCE_ULP32K:\r
+ /* Not possible to disable */\r
+ return true;\r
+\r
+ default:\r
+ return false;\r
+ }\r
+\r
+ return ((SYSCTRL->PCLKSR.reg & mask) != 0);\r
+}\r
+\r
+/* Include some checks for conf_clocks.h validation */\r
+#include "clock_config_check.h"\r
+\r
+#if !defined(__DOXYGEN__)\r
+/** \internal\r
+ *\r
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.\r
+ */\r
+# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \\r
+ if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \\r
+ struct system_gclk_gen_config gclk_conf; \\r
+ system_gclk_gen_get_config_defaults(&gclk_conf); \\r
+ gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \\r
+ gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \\r
+ gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \\r
+ gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \\r
+ system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \\r
+ system_gclk_gen_enable(GCLK_GENERATOR_##n); \\r
+ }\r
+\r
+/** \internal\r
+ *\r
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h,\r
+ * provided that it is not the main Generic Clock Generator channel.\r
+ */\r
+# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \\r
+ if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }\r
+#endif\r
+\r
+/**\r
+ * \brief Initialize clock system based on the configuration in conf_clocks.h\r
+ *\r
+ * This function will apply the settings in conf_clocks.h when run from the user\r
+ * application. All clock sources and GCLK generators are running when this function\r
+ * returns.\r
+ */\r
+void system_clock_init(void)\r
+{\r
+ /* Workaround for errata 10558 */\r
+ SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD12RDY | SYSCTRL_INTFLAG_BOD33RDY |\r
+ SYSCTRL_INTFLAG_BOD12DET | SYSCTRL_INTFLAG_BOD33DET |\r
+ SYSCTRL_INTFLAG_DFLLRDY;\r
+\r
+ system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);\r
+\r
+ /* XOSC */\r
+#if CONF_CLOCK_XOSC_ENABLE == true\r
+ struct system_clock_source_xosc_config xosc_conf;\r
+ system_clock_source_xosc_get_config_defaults(&xosc_conf);\r
+\r
+ xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;\r
+ xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME;\r
+ xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;\r
+ xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;\r
+ xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND;\r
+ xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY;\r
+\r
+ system_clock_source_xosc_set_config(&xosc_conf);\r
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);\r
+#endif\r
+\r
+\r
+ /* XOSC32K */\r
+#if CONF_CLOCK_XOSC32K_ENABLE == true\r
+ struct system_clock_source_xosc32k_config xosc32k_conf;\r
+ system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);\r
+\r
+ xosc32k_conf.frequency = 32768UL;\r
+ xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;\r
+ xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME;\r
+ xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;\r
+ xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;\r
+ xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;\r
+ xosc32k_conf.on_demand = CONF_CLOCK_XOSC32K_ON_DEMAND;\r
+ xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;\r
+\r
+ system_clock_source_xosc32k_set_config(&xosc32k_conf);\r
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);\r
+#endif\r
+\r
+\r
+ /* OSCK32K */\r
+#if CONF_CLOCK_OSC32K_ENABLE == true\r
+ SYSCTRL->OSC32K.bit.CALIB =\r
+ (*(uint32_t *)SYSCTRL_FUSES_OSC32KCAL_ADDR >> SYSCTRL_FUSES_OSC32KCAL_Pos);\r
+\r
+ struct system_clock_source_osc32k_config osc32k_conf;\r
+ system_clock_source_osc32k_get_config_defaults(&osc32k_conf);\r
+\r
+ osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME;\r
+ osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;\r
+ osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;\r
+ osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND;\r
+ osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;\r
+\r
+ system_clock_source_osc32k_set_config(&osc32k_conf);\r
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);\r
+#endif\r
+\r
+\r
+ /* DFLL (Open and Closed Loop) */\r
+#if CONF_CLOCK_DFLL_ENABLE == true\r
+ struct system_clock_source_dfll_config dfll_conf;\r
+ system_clock_source_dfll_get_config_defaults(&dfll_conf);\r
+\r
+ dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE;\r
+ dfll_conf.on_demand = CONF_CLOCK_DFLL_ON_DEMAND;\r
+ dfll_conf.run_in_standby = CONF_CLOCK_DFLL_RUN_IN_STANDBY;\r
+\r
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {\r
+ dfll_conf.coarse_value = CONF_CLOCK_DFLL_COARSE_VALUE;\r
+ dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE;\r
+ }\r
+\r
+# if CONF_CLOCK_DFLL_QUICK_LOCK == true\r
+ dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;\r
+# else\r
+ dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;\r
+# endif\r
+\r
+# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true\r
+ dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;\r
+# else\r
+ dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;\r
+# endif\r
+\r
+# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true\r
+ dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;\r
+# else\r
+ dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;\r
+# endif\r
+\r
+# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true\r
+ dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;\r
+# else\r
+ dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;\r
+# endif\r
+\r
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {\r
+ dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;\r
+ }\r
+\r
+ dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;\r
+ dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;\r
+\r
+ system_clock_source_dfll_set_config(&dfll_conf);\r
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);\r
+#endif\r
+\r
+\r
+ /* OSC8M */\r
+ struct system_clock_source_osc8m_config osc8m_conf;\r
+ system_clock_source_osc8m_get_config_defaults(&osc8m_conf);\r
+\r
+ osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER;\r
+ osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND;\r
+ osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;\r
+\r
+ system_clock_source_osc8m_set_config(&osc8m_conf);\r
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);\r
+\r
+\r
+ /* GCLK */\r
+#if CONF_CLOCK_CONFIGURE_GCLK == true\r
+ system_gclk_init();\r
+\r
+ /* Configure all GCLK generators except for the main generator, which\r
+ * is configured later after all other clock systems are set up */\r
+ MREPEAT(GCLK_GEN_NUM_MSB, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);\r
+\r
+# if (CONF_CLOCK_DFLL_ENABLE)\r
+ /* Enable DFLL reference clock if in closed loop mode */\r
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {\r
+ struct system_gclk_chan_config dfll_gclk_chan_conf;\r
+\r
+ system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);\r
+ dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;\r
+ system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);\r
+ system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);\r
+ }\r
+# endif\r
+\r
+ /* Configure the main GCLK last as it might depend on other generators */\r
+ _CONF_CLOCK_GCLK_CONFIG(0, ~);\r
+#endif\r
+\r
+\r
+ /* CPU and BUS clocks */\r
+ system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);\r
+ system_main_clock_set_failure_detect(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT);\r
+ system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);\r
+ system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Clock Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SYSTEM_CLOCK_H_INCLUDED\r
+#define SYSTEM_CLOCK_H_INCLUDED\r
+\r
+/**\r
+ * \defgroup asfdoc_samd20_system_clock_group SAM D20 System Clock Management Driver (SYSTEM CLOCK)\r
+ *\r
+ * This driver for SAM D20 devices provides an interface for the configuration\r
+ * and management of the device's clocking related functions. This includes\r
+ * the various clock sources, bus clocks and generic clocks within the device,\r
+ * with functions to manage the enabling, disabling, source selection and\r
+ * prescaling of clocks to various internal peripherals.\r
+ *\r
+ * The following peripherals are used by this module:\r
+ *\r
+ * - GCLK (Generic Clock Management)\r
+ * - PM (Power Management)\r
+ * - SYSCTRL (Clock Source Control)\r
+ *\r
+ * The outline of this documentation is as follows:\r
+ * - \ref asfdoc_samd20_system_clock_prerequisites\r
+ * - \ref asfdoc_samd20_system_clock_module_overview\r
+ * - \ref asfdoc_samd20_system_clock_special_considerations\r
+ * - \ref asfdoc_samd20_system_clock_extra_info\r
+ * - \ref asfdoc_samd20_system_clock_examples\r
+ * - \ref asfdoc_samd20_system_clock_api_overview\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_clock_prerequisites Prerequisites\r
+ *\r
+ * There are no prerequisites for this module.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_clock_module_overview Module Overview\r
+ * The SAM D20 devices contain a sophisticated clocking system, which is designed\r
+ * to give the maximum flexibility to the user application. This system allows\r
+ * a system designer to tune the performance and power consumption of the device\r
+ * in a dynamic manner, to achieve the best trade-off between the two for a\r
+ * particular application.\r
+ *\r
+ * This driver provides a set of functions for the configuration and management\r
+ * of the various clock related functionality within the device.\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_module_overview_clock_sources Clock Sources\r
+ * The SAM D20 devices have a number of master clock source modules, each of\r
+ * which being capable of producing a stabilized output frequency which can then\r
+ * be fed into the various peripherals and modules within the device.\r
+ *\r
+ * Possible clock source modules include internal R/C oscillators, internal\r
+ * DFLL modules, as well as external crystal oscillators and/or clock inputs.\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_module_overview_cpu_clock CPU / Bus Clocks\r
+ * The CPU and AHB/APBx buses are clocked by the same physical clock source\r
+ * (referred in this module as the Main Clock), however the APBx buses may\r
+ * have additional prescaler division ratios set to give each peripheral bus a\r
+ * different clock speed.\r
+ *\r
+ * The general main clock tree for the CPU and associated buses is shown in\r
+ * \ref asfdoc_samd20_system_clock_module_clock_tree "the figure below".\r
+ *\r
+ * \anchor asfdoc_samd20_system_clock_module_clock_tree\r
+ * \dot\r
+ * digraph overview {\r
+ * rankdir=LR;\r
+ * clk_src [label="Clock Sources", shape=none, height=0];\r
+ * node [label="CPU Bus" shape=ellipse] cpu_bus;\r
+ * node [label="AHB Bus" shape=ellipse] ahb_bus;\r
+ * node [label="APBA Bus" shape=ellipse] apb_a_bus;\r
+ * node [label="APBB Bus" shape=ellipse] apb_b_bus;\r
+ * node [label="APBC Bus" shape=ellipse] apb_c_bus;\r
+ * node [label="Main Bus\nPrescaler" shape=square] main_prescaler;\r
+ * node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;\r
+ * node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;\r
+ * node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;\r
+ * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;\r
+ *\r
+ * clk_src -> main_clock_mux;\r
+ * main_clock_mux -> main_prescaler;\r
+ * main_prescaler -> cpu_bus;\r
+ * main_prescaler -> ahb_bus;\r
+ * main_prescaler -> apb_a_prescaler;\r
+ * main_prescaler -> apb_b_prescaler;\r
+ * main_prescaler -> apb_c_prescaler;\r
+ * apb_a_prescaler -> apb_a_bus;\r
+ * apb_b_prescaler -> apb_b_bus;\r
+ * apb_c_prescaler -> apb_c_bus;\r
+ * }\r
+ * \enddot\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_module_overview_clock_masking Clock Masking\r
+ * To save power, the input clock to one or more peripherals on the AHB and APBx\r
+ * busses can be masked away - when masked, no clock is passed into the module.\r
+ * Disabling of clocks of unused modules will prevent all access to the masked\r
+ * module, but will reduce the overall device power consumption.\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_module_overview_gclk Generic Clocks\r
+ * Within the SAM D20 devices are a number of Generic Clocks; these are used to\r
+ * provide clocks to the various peripheral clock domains in the device in a\r
+ * standardized manner. One or more master source clocks can be selected as the\r
+ * input clock to a Generic Clock Generator, which can prescale down the input\r
+ * frequency to a slower rate for use in a peripheral.\r
+ *\r
+ * Additionally, a number of individually selectable Generic Clock Channels are\r
+ * provided, which multiplex and gate the various generator outputs for one or\r
+ * more peripherals within the device. This setup allows for a single common\r
+ * generator to feed one or more channels, which can then be enabled or disabled\r
+ * individually as required.\r
+ *\r
+ * \anchor asfdoc_samd20_system_clock_module_chain_overview\r
+ * \dot\r
+ * digraph overview {\r
+ * rankdir=LR;\r
+ * node [label="Clock\nSource a" shape=square] system_clock_source;\r
+ * node [label="Generator 1" shape=square] clock_gen;\r
+ * node [label="Channel x" shape=square] clock_chan0;\r
+ * node [label="Channel y" shape=square] clock_chan1;\r
+ * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;\r
+ * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;\r
+ *\r
+ * system_clock_source -> clock_gen;\r
+ * clock_gen -> clock_chan0;\r
+ * clock_chan0 -> peripheral0;\r
+ * clock_gen -> clock_chan1;\r
+ * clock_chan1 -> peripheral1;\r
+ * }\r
+ * \enddot\r
+ *\r
+ * \subsubsection asfdoc_samd20_system_clock_module_chain_example Clock Chain Example\r
+ * An example setup of a complete clock chain within the device is shown in\r
+ * \ref asfdoc_samd20_system_clock_module_chain_example_fig "the figure below".\r
+ *\r
+ * \anchor asfdoc_samd20_system_clock_module_chain_example_fig\r
+ * \dot\r
+ * digraph overview {\r
+ * rankdir=LR;\r
+ * node [label="External\nOscillator" shape=square] system_clock_source0;\r
+ * node [label="Generator 0" shape=square] clock_gen0;\r
+ * node [label="Channel x" shape=square] clock_chan0;\r
+ * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0;\r
+ *\r
+ * system_clock_source0 -> clock_gen0;\r
+ * clock_gen0 -> clock_chan0;\r
+ * clock_chan0 -> peripheral0;\r
+ * node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;\r
+ * node [label="Generator 1" shape=square] clock_gen1;\r
+ * node [label="Channel y" shape=square] clock_chan1;\r
+ * node [label="Channel z" shape=square] clock_chan2;\r
+ * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1;\r
+ * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2;\r
+ *\r
+ * system_clock_source1 -> clock_gen1;\r
+ * clock_gen1 -> clock_chan1;\r
+ * clock_gen1 -> clock_chan2;\r
+ * clock_chan1 -> peripheral1;\r
+ * clock_chan2 -> peripheral2;\r
+ * }\r
+ * \enddot\r
+ *\r
+ * \subsubsection asfdoc_samd20_system_clock_module_overview_gclk_generators Generic Clock Generators\r
+ * Each Generic Clock generator within the device can source its input clock\r
+ * from one of the provided Source Clocks, and prescale the output for one or\r
+ * more Generic Clock Channels in a one-to-many relationship. The generators\r
+ * thus allow for several clocks to be generated of different frequencies,\r
+ * power usages and accuracies, which can be turned on and off individually to\r
+ * disable the clocks to multiple peripherals as a group.\r
+ *\r
+ * \subsubsection asfdoc_samd20_system_clock_module_overview_gclk_channels Generic Clock Channels\r
+ * To connect a Generic Clock Generator to a peripheral within the\r
+ * device, a Generic Clock Channel is used. Each peripheral or\r
+ * peripheral group has an associated Generic Clock Channel, which serves as the\r
+ * clock input for the peripheral(s). To supply a clock to the peripheral\r
+ * module(s), the associated channel must be connected to a running Generic\r
+ * Clock Generator and the channel enabled.\r
+ *\r
+ * \section asfdoc_samd20_system_clock_special_considerations Special Considerations\r
+ *\r
+ * There are no special considerations for this module.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_clock_extra_info Extra Information\r
+ *\r
+ * For extra information see \ref asfdoc_samd20_system_clock_extra. This includes:\r
+ * - \ref asfdoc_samd20_system_clock_extra_acronyms\r
+ * - \ref asfdoc_samd20_system_clock_extra_dependencies\r
+ * - \ref asfdoc_samd20_system_clock_extra_errata\r
+ * - \ref asfdoc_samd20_system_clock_extra_history\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_clock_examples Examples\r
+ *\r
+ * For a list of examples related to this driver, see\r
+ * \ref asfdoc_samd20_system_clock_exqsg.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_clock_api_overview API Overview\r
+ * @{\r
+ */\r
+\r
+#include <compiler.h>\r
+#include <gclk.h>\r
+\r
+/**\r
+ * \brief Available start-up times for the XOSC32K\r
+ *\r
+ * Available external 32KHz oscillator start-up times, as a number of external\r
+ * clock cycles.\r
+ */\r
+enum system_xosc32k_startup {\r
+ /** Wait 0 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC32K_STARTUP_0,\r
+ /** Wait 32 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC32K_STARTUP_32,\r
+ /** Wait 2048 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC32K_STARTUP_2048,\r
+ /** Wait 4096 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC32K_STARTUP_4096,\r
+ /** Wait 16384 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC32K_STARTUP_16384,\r
+ /** Wait 32768 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC32K_STARTUP_32768,\r
+ /** Wait 65536 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC32K_STARTUP_65536,\r
+ /** Wait 131072 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC32K_STARTUP_131072,\r
+};\r
+\r
+/**\r
+ * \brief Available start-up times for the XOSC\r
+ *\r
+ * Available external oscillator start-up times, as a number of external clock\r
+ * cycles.\r
+ */\r
+enum system_xosc_startup {\r
+ /** Wait 1 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_1,\r
+ /** Wait 2 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_2,\r
+ /** Wait 4 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_4,\r
+ /** Wait 8 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_8,\r
+ /** Wait 16 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_16,\r
+ /** Wait 32 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_32,\r
+ /** Wait 64 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_64,\r
+ /** Wait 128 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_128,\r
+ /** Wait 256 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_256,\r
+ /** Wait 512 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_512,\r
+ /** Wait 1024 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_1024,\r
+ /** Wait 2048 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_2048,\r
+ /** Wait 4096 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_4096,\r
+ /** Wait 8192 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_8192,\r
+ /** Wait 16384 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_16384,\r
+ /** Wait 32768 clock cycles until the clock source is considered stable */\r
+ SYSTEM_XOSC_STARTUP_32768,\r
+};\r
+\r
+/**\r
+ * \brief Available start-up times for the OSC32K\r
+ *\r
+ * Available internal 32KHz oscillator start-up times, as a number of internal\r
+ * OSC32K clock cycles.\r
+ */\r
+enum system_osc32k_startup {\r
+ /** Wait 0 clock cycles until the clock source is considered stable */\r
+ SYSTEM_OSC32K_STARTUP_0,\r
+ /** Wait 2 clock cycles until the clock source is considered stable */\r
+ SYSTEM_OSC32K_STARTUP_2,\r
+ /** Wait 4 clock cycles until the clock source is considered stable */\r
+ SYSTEM_OSC32K_STARTUP_4,\r
+ /** Wait 8 clock cycles until the clock source is considered stable */\r
+ SYSTEM_OSC32K_STARTUP_8,\r
+ /** Wait 16 clock cycles until the clock source is considered stable */\r
+ SYSTEM_OSC32K_STARTUP_16,\r
+ /** Wait 32 clock cycles until the clock source is considered stable */\r
+ SYSTEM_OSC32K_STARTUP_32,\r
+ /** Wait 64 clock cycles until the clock source is considered stable */\r
+ SYSTEM_OSC32K_STARTUP_64,\r
+ /** Wait 128 clock cycles until the clock source is considered stable */\r
+ SYSTEM_OSC32K_STARTUP_128,\r
+};\r
+\r
+/**\r
+ * \brief Division prescalers for the internal 8MHz system clock\r
+ *\r
+ * Available prescalers for the internal 8MHz (nominal) system clock.\r
+ */\r
+enum system_osc8m_div {\r
+ /** Do not divide the 8MHz RC oscillator output */\r
+ SYSTEM_OSC8M_DIV_1,\r
+ /** Divide the 8MHz RC oscillator output by 2 */\r
+ SYSTEM_OSC8M_DIV_2,\r
+ /** Divide the 8MHz RC oscillator output by 4 */\r
+ SYSTEM_OSC8M_DIV_4,\r
+ /** Divide the 8MHz RC oscillator output by 8 */\r
+ SYSTEM_OSC8M_DIV_8,\r
+};\r
+\r
+/**\r
+ * \brief Main CPU and APB/AHB bus clock source prescaler values\r
+ *\r
+ * Available division ratios for the CPU and APB/AHB bus clocks.\r
+ */\r
+enum system_main_clock_div {\r
+ /** Divide Main clock by 1 */\r
+ SYSTEM_MAIN_CLOCK_DIV_1,\r
+ /** Divide Main clock by 2 */\r
+ SYSTEM_MAIN_CLOCK_DIV_2,\r
+ /** Divide Main clock by 4 */\r
+ SYSTEM_MAIN_CLOCK_DIV_4,\r
+ /** Divide Main clock by 8 */\r
+ SYSTEM_MAIN_CLOCK_DIV_8,\r
+ /** Divide Main clock by 16 */\r
+ SYSTEM_MAIN_CLOCK_DIV_16,\r
+ /** Divide Main clock by 32 */\r
+ SYSTEM_MAIN_CLOCK_DIV_32,\r
+ /** Divide Main clock by 64 */\r
+ SYSTEM_MAIN_CLOCK_DIV_64,\r
+ /** Divide Main clock by 128 */\r
+ SYSTEM_MAIN_CLOCK_DIV_128,\r
+};\r
+\r
+/**\r
+ * \brief External clock source types.\r
+ *\r
+ * Available external clock source types.\r
+ */\r
+enum system_clock_external {\r
+ /** The external clock source is a crystal oscillator */\r
+ SYSTEM_CLOCK_EXTERNAL_CRYSTAL,\r
+ /** The connected clock source is an external logic level clock signal */\r
+ SYSTEM_CLOCK_EXTERNAL_CLOCK,\r
+};\r
+\r
+/**\r
+ * \brief Operating modes of the DFLL clock source.\r
+ *\r
+ * Available operating modes of the DFLL clock source module,\r
+ */\r
+enum system_clock_dfll_loop_mode {\r
+ /** The DFLL is operating in open loop mode with no feedback */\r
+ SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,\r
+ /** The DFLL is operating in closed loop mode with frequency feedback from\r
+ * a low frequency reference clock\r
+ */\r
+ SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,\r
+};\r
+\r
+/**\r
+ * \brief Locking behavior for the DFLL during device wake-up\r
+ *\r
+ * DFLL lock behavior modes on device wake-up from sleep.\r
+ */\r
+enum system_clock_dfll_wakeup_lock {\r
+ /** Keep DFLL lock when the device wakes from sleep */\r
+ SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,\r
+ /** Lose DFLL lock when the devices wakes from sleep */\r
+ SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,\r
+};\r
+\r
+/**\r
+ * \brief Fine tracking behavior for the DFLL once a lock has been acquired\r
+ *\r
+ * DFLL fine tracking behavior modes after a lock has been acquired.\r
+ */\r
+enum system_clock_dfll_stable_tracking {\r
+ /** Keep tracking after the DFLL has gotten a fine lock */\r
+ SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,\r
+ /** Stop tracking after the DFLL has gotten a fine lock */\r
+ SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,\r
+};\r
+\r
+/**\r
+ * \brief Chill-cycle behavior of the DFLL module\r
+ *\r
+ * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period\r
+ * of time when the DFLL output frequency is not measured by the unit, to allow\r
+ * the output to stabilize after a change in the input clock source.\r
+ */\r
+enum system_clock_dfll_chill_cycle {\r
+ /** Enable a chill cycle, where the DFLL output frequency is not measured */\r
+ SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,\r
+ /** Disable a chill cycle, where the DFLL output frequency is not measured */\r
+ SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,\r
+};\r
+\r
+/**\r
+ * \brief QuickLock settings for the DFLL module\r
+ *\r
+ * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of\r
+ * the DFLL output frequency at the expense of accuracy.\r
+ */\r
+enum system_clock_dfll_quick_lock {\r
+ /** Enable the QuickLock feature for looser lock requirements on the DFLL */\r
+ SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,\r
+ /** Disable the QuickLock feature for strict lock requirements on the DFLL */\r
+ SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,\r
+};\r
+\r
+/**\r
+ * \brief List of APB peripheral buses\r
+ *\r
+ * Available bus clock domains on the APB bus.\r
+ */\r
+enum system_clock_apb_bus {\r
+ /** Peripheral bus A on the APB bus. */\r
+ SYSTEM_CLOCK_APB_APBA,\r
+ /** Peripheral bus B on the APB bus. */\r
+ SYSTEM_CLOCK_APB_APBB,\r
+ /** Peripheral bus C on the APB bus. */\r
+ SYSTEM_CLOCK_APB_APBC,\r
+};\r
+\r
+/**\r
+ * \brief Available clock sources in the system\r
+ *\r
+ * Clock sources available to the GCLK generators\r
+ */\r
+enum system_clock_source {\r
+ /** Internal 8MHz RC oscillator */\r
+ SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M,\r
+ /** Internal 32kHz RC oscillator */\r
+ SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,\r
+ /** External oscillator */\r
+ SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC ,\r
+ /** External 32kHz oscillator */\r
+ SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,\r
+ /** Digital Frequency Locked Loop (DFLL) */\r
+ SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,\r
+ /** Internal Ultra Low Power 32kHz oscillator */\r
+ SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,\r
+};\r
+\r
+/**\r
+ * \brief Configuration structure for XOSC\r
+ *\r
+ * External oscillator clock configuration structure.\r
+ */\r
+struct system_clock_source_xosc_config {\r
+ /** External clock type */\r
+ enum system_clock_external external_clock;\r
+ /** Crystal oscillator start-up time */\r
+ enum system_xosc_startup startup_time;\r
+ /** Enable automatic amplitude gain control */\r
+ bool auto_gain_control;\r
+ /** External clock/crystal frequency */\r
+ uint32_t frequency;\r
+ /** Keep the XOSC enabled in standby sleep mode */\r
+ bool run_in_standby;\r
+ /** Run On Demand. If this is set the XOSC won't run\r
+ * until requested by a peripheral */\r
+ bool on_demand;\r
+};\r
+\r
+/**\r
+ * \brief Configuration structure for XOSC32K\r
+ *\r
+ * External 32KHz oscillator clock configuration structure.\r
+ */\r
+struct system_clock_source_xosc32k_config {\r
+ /** External clock type */\r
+ enum system_clock_external external_clock;\r
+ /** Crystal oscillator start-up time */\r
+ enum system_xosc32k_startup startup_time;\r
+ /** Enable automatic amplitude control */\r
+ bool auto_gain_control;\r
+ /** Enable 1kHz output */\r
+ bool enable_1khz_output;\r
+ /** Enable 32kHz output */\r
+ bool enable_32khz_output;\r
+ /** External clock/crystal frequency */\r
+ uint32_t frequency;\r
+ /** Keep the XOSC32K enabled in standby sleep mode */\r
+ bool run_in_standby;\r
+ /** Run On Demand. If this is set the XOSC32K won't run\r
+ * until requested by a peripheral */\r
+ bool on_demand;\r
+};\r
+\r
+/**\r
+ * \brief Configuration structure for OSC8M\r
+ *\r
+ * Internal 8MHz (nominal) oscillator configuration structure.\r
+ */\r
+struct system_clock_source_osc8m_config {\r
+ /* Internal 8MHz RC oscillator prescaler */\r
+ enum system_osc8m_div prescaler;\r
+ /** Keep the OSC8M enabled in standby sleep mode */\r
+ bool run_in_standby;\r
+ /** Run On Demand. If this is set the OSC8M won't run\r
+ * until requested by a peripheral */\r
+ bool on_demand;\r
+};\r
+\r
+/**\r
+ * \brief Configuration structure for OSC32K\r
+ *\r
+ * Internal 32KHz (nominal) oscillator configuration structure.\r
+ */\r
+struct system_clock_source_osc32k_config {\r
+ /** Startup time */\r
+ enum system_osc32k_startup startup_time;\r
+ /** Enable 1kHz output */\r
+ bool enable_1khz_output;\r
+ /** Enable 32kHz output */\r
+ bool enable_32khz_output;\r
+ /** Keep the OSC32K enabled in standby sleep mode */\r
+ bool run_in_standby;\r
+ /** Run On Demand. If this is set the OSC32K won't run\r
+ * until requested by a peripheral */\r
+ bool on_demand;\r
+};\r
+\r
+/**\r
+ * \brief Configuration structure for DFLL\r
+ *\r
+ * DFLL oscillator configuration structure.\r
+ */\r
+struct system_clock_source_dfll_config {\r
+ /** Loop mode */\r
+ enum system_clock_dfll_loop_mode loop_mode;\r
+ /** Keep the DFLL enabled in standby sleep mode */\r
+ bool run_in_standby;\r
+ /** Run On Demand. If this is set the DFLL won't run\r
+ * until requested by a peripheral */\r
+ bool on_demand;\r
+ /** Enable Quick Lock */\r
+ enum system_clock_dfll_quick_lock quick_lock;\r
+ /** Enable Chill Cycle */\r
+ enum system_clock_dfll_chill_cycle chill_cycle;\r
+ /** DFLL lock state on wakeup */\r
+ enum system_clock_dfll_wakeup_lock wakeup_lock;\r
+ /** DFLL tracking after fine lock */\r
+ enum system_clock_dfll_stable_tracking stable_tracking;\r
+ /** Coarse calibration value (Open loop mode) */\r
+ uint8_t coarse_value;\r
+ /** Fine calibration value (Open loop mode) */\r
+ uint8_t fine_value;\r
+ /** Coarse adjustment max step size (Closed loop mode) */\r
+ uint8_t coarse_max_step;\r
+ /** Fine adjustment max step size (Closed loop mode) */\r
+ uint8_t fine_max_step;\r
+ /** DFLL multiply factor (Closed loop mode */\r
+ uint16_t multiply_factor;\r
+};\r
+\r
+/**\r
+ * \name External Oscillator management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieve the default configuration for XOSC\r
+ *\r
+ * Fills a configuration structure with the default configuration for an\r
+ * external oscillator module:\r
+ * - External Crystal\r
+ * - Start-up time of 16384 external clock cycles\r
+ * - Automatic crystal gain control mode enabled\r
+ * - Frequency of 12MHz\r
+ * - Don't run in STANDBY sleep mode\r
+ * - Run only when requested by peripheral (on demand)\r
+ *\r
+ * \param[out] config Configuration structure to fill with default values\r
+ */\r
+static inline void system_clock_source_xosc_get_config_defaults(\r
+ struct system_clock_source_xosc_config *const config)\r
+{\r
+ Assert(config);\r
+\r
+ config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;\r
+ config->startup_time = SYSTEM_XOSC_STARTUP_16384;\r
+ config->auto_gain_control = true;\r
+ config->frequency = 12000000UL;\r
+ config->run_in_standby = false;\r
+ config->on_demand = true;\r
+}\r
+\r
+void system_clock_source_xosc_set_config(\r
+ struct system_clock_source_xosc_config *const config);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * \name External 32KHz Oscillator management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieve the default configuration for XOSC32K\r
+ *\r
+ * Fills a configuration structure with the default configuration for an\r
+ * external 32KHz oscillator module:\r
+ * - External Crystal\r
+ * - Start-up time of 16384 external clock cycles\r
+ * - Automatic crystal gain control mode enabled\r
+ * - Frequency of 32.768KHz\r
+ * - 1KHz clock output disabled\r
+ * - 32KHz clock output enabled\r
+ * - Don't run in STANDBY sleep mode\r
+ * - Run only when requested by peripheral (on demand)\r
+ *\r
+ * \param[out] config Configuration structure to fill with default values\r
+ */\r
+static inline void system_clock_source_xosc32k_get_config_defaults(\r
+ struct system_clock_source_xosc32k_config *const config)\r
+{\r
+ Assert(config);\r
+\r
+ config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;\r
+ config->startup_time = SYSTEM_XOSC32K_STARTUP_16384;\r
+ config->auto_gain_control = true;\r
+ config->frequency = 32768UL;\r
+ config->enable_1khz_output = false;\r
+ config->enable_32khz_output = true;\r
+ config->run_in_standby = false;\r
+ config->on_demand = true;\r
+}\r
+\r
+void system_clock_source_xosc32k_set_config(\r
+ struct system_clock_source_xosc32k_config *const config);\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * \name Internal 32KHz Oscillator management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieve the default configuration for OSC32K\r
+ *\r
+ * Fills a configuration structure with the default configuration for an\r
+ * internal 32KHz oscillator module:\r
+ * - 1KHz clock output enabled\r
+ * - 32KHz clock output enabled\r
+ * - Don't run in STANDBY sleep mode\r
+ * - Run only when requested by peripheral (on demand)\r
+ *\r
+ * \param[out] config Configuration structure to fill with default values\r
+ */\r
+static inline void system_clock_source_osc32k_get_config_defaults(\r
+ struct system_clock_source_osc32k_config *const config)\r
+{\r
+ Assert(config);\r
+\r
+ config->enable_1khz_output = true;\r
+ config->enable_32khz_output = true;\r
+ config->run_in_standby = false;\r
+ config->on_demand = true;\r
+}\r
+\r
+void system_clock_source_osc32k_set_config(\r
+ struct system_clock_source_osc32k_config *const config);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * \name Internal 8MHz Oscillator management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieve the default configuration for OSC8M\r
+ *\r
+ * Fills a configuration structure with the default configuration for an\r
+ * internal 8MHz (nominal) oscillator module:\r
+ * - Clock output frequency divided by a factor of 8\r
+ * - Don't run in STANDBY sleep mode\r
+ * - Run only when requested by peripheral (on demand)\r
+ *\r
+ * \param[out] config Configuration structure to fill with default values\r
+ */\r
+static inline void system_clock_source_osc8m_get_config_defaults(\r
+ struct system_clock_source_osc8m_config *const config)\r
+{\r
+ Assert(config);\r
+\r
+ config->prescaler = SYSTEM_OSC8M_DIV_8;\r
+ config->run_in_standby = false;\r
+ config->on_demand = true;\r
+}\r
+\r
+void system_clock_source_osc8m_set_config(\r
+ struct system_clock_source_osc8m_config *const config);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * \name Internal DFLL management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieve the default configuration for DFLL\r
+ *\r
+ * Fills a configuration structure with the default configuration for a\r
+ * DFLL oscillator module:\r
+ * - Open loop mode\r
+ * - QuickLock mode enabled\r
+ * - Chill cycle enabled\r
+ * - Output frequency lock maintained during device wake-up\r
+ * - Continuous tracking of the output frequency\r
+ * - Default tracking values at the mid-points for both coarse and fine\r
+ * tracking parameters\r
+ * - Don't run in STANDBY sleep mode\r
+ * - Run only when requested by peripheral (on demand)\r
+ *\r
+ * \param[out] config Configuration structure to fill with default values\r
+ */\r
+static inline void system_clock_source_dfll_get_config_defaults(\r
+ struct system_clock_source_dfll_config *const config)\r
+{\r
+ Assert(config);\r
+\r
+ config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;\r
+ config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;\r
+ config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;\r
+ config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;\r
+ config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;\r
+ config->run_in_standby = false;\r
+ config->on_demand = true;\r
+\r
+ /* Open loop mode calibration value */\r
+ config->coarse_value = 0x1f / 4; /* Midpoint */\r
+ config->fine_value = 0xff / 4; /* Midpoint */\r
+\r
+ /* Closed loop mode */\r
+ config->coarse_max_step = 1;\r
+ config->fine_max_step = 1;\r
+ config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */\r
+}\r
+\r
+void system_clock_source_dfll_set_config(\r
+ struct system_clock_source_dfll_config *const config);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \name Clock source management\r
+ * @{\r
+ */\r
+enum status_code system_clock_source_write_calibration(\r
+ const enum system_clock_source system_clock_source,\r
+ const uint16_t calibration_value,\r
+ const uint8_t freq_range);\r
+\r
+enum status_code system_clock_source_enable(\r
+ const enum system_clock_source system_clock_source);\r
+\r
+enum status_code system_clock_source_disable(\r
+ const enum system_clock_source clk_source);\r
+\r
+bool system_clock_source_is_ready(\r
+ const enum system_clock_source clk_source);\r
+\r
+uint32_t system_clock_source_get_hz(\r
+ const enum system_clock_source clk_source);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \name Main clock management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Enable or disable the main clock failure detection.\r
+ *\r
+ * This mechanism allows switching automatically the main clock to the safe\r
+ * RCSYS clock, when the main clock source is considered off.\r
+ *\r
+ * This may happen for instance when an external crystal is selected as the\r
+ * clock source of the main clock and the crystal dies. The mechanism is to\r
+ * detect, during a RCSYS period, at least one rising edge of the main clock.\r
+ * If no rising edge is seen the clock is considered failed.\r
+ * As soon as the detector is enabled, the clock failure detector\r
+ * CFD) will monitor the divided main clock. When a clock failure is detected,\r
+ * the main clock automatically switches to the RCSYS clock and the CFD\r
+ * interrupt is generated if enabled.\r
+ *\r
+ * \note The failure detect must be disabled if the system clock is the same or\r
+ * slower than 32kHz as it will believe the system clock has failed with\r
+ * a too-slow clock.\r
+ *\r
+ * \param[in] enable Boolean \c true to enable, \c false to disable detection\r
+ */\r
+static inline void system_main_clock_set_failure_detect(\r
+ const bool enable)\r
+{\r
+ if (enable) {\r
+ PM->CTRL.reg |= PM_CTRL_CFDEN;\r
+ } else {\r
+ PM->CTRL.reg &= ~PM_CTRL_CFDEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set main CPU clock divider.\r
+ *\r
+ * Sets the clock divider used on the main clock to provide the CPU clock.\r
+ *\r
+ * \param[in] divider CPU clock divider to set\r
+ */\r
+static inline void system_cpu_clock_set_divider(\r
+ const enum system_main_clock_div divider)\r
+{\r
+ Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);\r
+ PM->CPUSEL.reg = (uint32_t)divider;\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current frequency of the CPU core.\r
+ *\r
+ * Retrieves the operating frequency of the CPU core, obtained from the main\r
+ * generic clock and the set CPU bus divider.\r
+ *\r
+ * \return Current CPU frequency in Hz.\r
+ */\r
+static inline uint32_t system_cpu_clock_get_hz(void)\r
+{\r
+ return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);\r
+}\r
+\r
+/**\r
+ * \brief Set APBx clock divider.\r
+ *\r
+ * Set the clock divider used on the main clock to provide the clock for the\r
+ * given APBx bus.\r
+ *\r
+ * \param[in] divider APBx bus divider to set\r
+ * \param[in] bus APBx bus to set divider for\r
+ *\r
+ * \returns Status of the clock division change operation.\r
+ *\r
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given\r
+ * \retval STATUS_OK The APBx clock was set successfully\r
+ */\r
+static inline enum status_code system_apb_clock_set_divider(\r
+ const enum system_clock_apb_bus bus,\r
+ const enum system_main_clock_div divider)\r
+{\r
+ switch (bus) {\r
+ case SYSTEM_CLOCK_APB_APBA:\r
+ PM->APBASEL.reg = (uint32_t)divider;\r
+ break;\r
+ case SYSTEM_CLOCK_APB_APBB:\r
+ PM->APBBSEL.reg = (uint32_t)divider;\r
+ break;\r
+ case SYSTEM_CLOCK_APB_APBC:\r
+ PM->APBCSEL.reg = (uint32_t)divider;\r
+ break;\r
+ default:\r
+ Assert(false);\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current frequency of a ABPx.\r
+ *\r
+ * Retrieves the operating frequency of an APBx bus, obtained from the main\r
+ * generic clock and the set APBx bus divider.\r
+ *\r
+ * \return Current APBx bus frequency in Hz.\r
+ */\r
+static inline uint32_t system_apb_clock_get_hz(\r
+ const enum system_clock_apb_bus bus)\r
+{\r
+ uint16_t bus_divider = 0;\r
+\r
+ switch (bus) {\r
+ case SYSTEM_CLOCK_APB_APBA:\r
+ bus_divider = PM->APBASEL.reg;\r
+ break;\r
+ case SYSTEM_CLOCK_APB_APBB:\r
+ bus_divider = PM->APBBSEL.reg;\r
+ break;\r
+ case SYSTEM_CLOCK_APB_APBC:\r
+ bus_divider = PM->APBCSEL.reg;\r
+ break;\r
+ default:\r
+ Assert(false);\r
+ return 0;\r
+ }\r
+\r
+ return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \name Bus clock masking\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Set bits in the clock mask for the AHB bus.\r
+ *\r
+ * This function will set bits in the clock mask for the AHB bus.\r
+ * Any bits set to 1 will enable that clock, 0 bits in the mask\r
+ * will be ignored\r
+ *\r
+ * \param[in] ahb_mask AHB clock mask to enable\r
+ */\r
+static inline void system_ahb_clock_set_mask(\r
+ const uint32_t ahb_mask)\r
+{\r
+ PM->AHBMASK.reg |= ahb_mask;\r
+}\r
+\r
+/**\r
+ * \brief Clear bits in the clock mask for the AHB bus.\r
+ *\r
+ * This function will clear bits in the clock mask for the AHB bus.\r
+ * Any bits set to 1 will disable that clock, 0 bits in the mask\r
+ * will be ignored.\r
+ *\r
+ * \param[in] ahb_mask AHB clock mask to disable\r
+ */\r
+static inline void system_ahb_clock_clear_mask(\r
+ const uint32_t ahb_mask)\r
+{\r
+ PM->AHBMASK.reg &= ~ahb_mask;\r
+}\r
+\r
+/**\r
+ * \brief Set bits in the clock mask for an APBx bus.\r
+ *\r
+ * This function will set bits in the clock mask for an APBx bus.\r
+ * Any bits set to 1 will enable the corresponding module clock, zero bits in\r
+ * the mask will be ignored.\r
+ *\r
+ * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from\r
+ * the device header files\r
+ * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*\r
+ * constants from the device header files\r
+ *\r
+ * \returns Status indicating the result of the clock mask change operation.\r
+ *\r
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus given\r
+ * \retval STATUS_OK The clock mask was set successfully\r
+ */\r
+static inline enum status_code system_apb_clock_set_mask(\r
+ const enum system_clock_apb_bus bus,\r
+ const uint32_t mask)\r
+{\r
+ switch (bus) {\r
+ case SYSTEM_CLOCK_APB_APBA:\r
+ PM->APBAMASK.reg |= mask;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_APB_APBB:\r
+ PM->APBBMASK.reg |= mask;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_APB_APBC:\r
+ PM->APBCMASK.reg |= mask;\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ return STATUS_ERR_INVALID_ARG;\r
+\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Clear bits in the clock mask for an APBx bus.\r
+ *\r
+ * This function will clear bits in the clock mask for an APBx bus.\r
+ * Any bits set to 1 will disable the corresponding module clock, zero bits in\r
+ * the mask will be ignored.\r
+ *\r
+ * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from\r
+ * the device header files\r
+ * \param[in] bus Bus to clear clock mask bits for\r
+ *\r
+ * \returns Status indicating the result of the clock mask change operation.\r
+ *\r
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given.\r
+ * \retval STATUS_OK The clock mask was changed successfully.\r
+ */\r
+static inline enum status_code system_apb_clock_clear_mask(\r
+ const enum system_clock_apb_bus bus,\r
+ const uint32_t mask)\r
+{\r
+ switch (bus) {\r
+ case SYSTEM_CLOCK_APB_APBA:\r
+ PM->APBAMASK.reg &= ~mask;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_APB_APBB:\r
+ PM->APBBMASK.reg &= ~mask;\r
+ break;\r
+\r
+ case SYSTEM_CLOCK_APB_APBC:\r
+ PM->APBCMASK.reg &= ~mask;\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \name System Clock Initialization\r
+ * @{\r
+ */\r
+\r
+void system_clock_init(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \name System Flash Wait States\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Set flash controller wait states\r
+ *\r
+ * Will set the number of wait states that are used by the onboard\r
+ * flash memory. The number of wait states depend on both device\r
+ * supply voltage and CPU speed. The required number of wait states\r
+ * can be found in the electrical characteristics of the device.\r
+ *\r
+ * \param[in] wait_states Number of wait states to use for internal flash\r
+ */\r
+static inline void system_flash_set_waitstates(uint8_t wait_states)\r
+{\r
+ Assert((wait_states & NVMCTRL_CTRLB_RWS_Msk) == wait_states);\r
+ NVMCTRL->CTRLB.bit.RWS = wait_states;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_clock_extra Extra Information for SYSTEM CLOCK Driver\r
+ *\r
+ * \section asfdoc_samd20_system_clock_extra_acronyms Acronyms\r
+ * Below is a table listing the acronyms used in this module, along with their\r
+ * intended meanings.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Acronym</th>\r
+ * <th>Description</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>DFLL</td>\r
+ * <td>Digital Frequency Locked Loop</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>MUX</td>\r
+ * <td>Multiplexer</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>OSC32K</td>\r
+ * <td>Internal 32KHz Oscillator</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>OSC8M</td>\r
+ * <td>Internal 8MHz Oscillator</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>PLL</td>\r
+ * <td>Phase Locked Loop</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>OSC</td>\r
+ * <td>Oscillator</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>XOSC</td>\r
+ * <td>External Oscillator</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>XOSC32K</td>\r
+ * <td>External 32KHz Oscillator</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>AHB</td>\r
+ * <td>Advanced High-performance Bus</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>APB</td>\r
+ * <td>Advanced Peripheral Bus</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_clock_extra_dependencies Dependencies\r
+ * This driver has the following dependencies:\r
+ *\r
+ * - None\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_clock_extra_errata Errata\r
+ * <tr>\r
+ * <td>\r
+ * \li This driver implements workaround for errata 10558\r
+ * "Several reset values of SYSCTRL.INTFLAG are wrong (BOD and DFLL)"<br>\r
+ * When system_init is called it will reset these interrupts flags before they are used.\r
+ * </td>\r
+ * </tr>\r
+ *\r
+ * <tr>\r
+ * <td>\r
+ * \li This driver implements experimental workaround for errata 9905<br>\r
+ * "The DFLL clock must be requested before being configured otherwise a\r
+ * write access to a DFLL register can freeze the device."<br>\r
+ * This driver will enable and configure the DFLL before the ONDEMAND bit is set.\r
+ * </td>\r
+ * </tr>\r
+ * \r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_clock_extra_history Module History\r
+ * An overview of the module history is presented in the table below, with\r
+ * details on the enhancements and fixes made to the module since its first\r
+ * release. The current version of this corresponds to the newest version in\r
+ * the table.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Changelog</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>\r
+ * \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from true to false\r
+ * </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>\li Updated dfll configuration function to implement workaround for errata 9905 in the DFLL module.\r
+ * \li Updated \c system_clock_init() to reset interrupt flags before they are used, errata 10558.\r
+ * \li Fixed \c system_clock_source_get_hz() to return correcy DFLL frequency number.\r
+ * </td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>\li Fixed \c system_clock_source_is_ready not returning the correct\r
+ * state for \c SYSTEM_CLOCK_SOURCE_OSC8M.\r
+ * \li Renamed the various \c system_clock_source_*_get_default_config()\r
+ * functions to \c system_clock_source_*_get_config_defaults() to\r
+ * match the remainder of ASF.\r
+ * \li Added OSC8M calibration constant loading from the device signature\r
+ * row when the oscillator is initialized.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Initial Release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_clock_exqsg Examples for System Clock Driver\r
+ *\r
+ * This is a list of the available Quick Start guides (QSGs) and example\r
+ * applications for \ref asfdoc_samd20_system_clock_group. QSGs are simple\r
+ * examples with step-by-step instructions to configure and use this driver in\r
+ * a selection of use cases. Note that QSGs can be compiled as a standalone\r
+ * application or be added to the user application.\r
+ *\r
+ * - \subpage asfdoc_samd20_system_clock_basic_use_case\r
+ * - \subpage asfdoc_samd20_system_gclk_basic_use_case\r
+ *\r
+ * \page asfdoc_samd20_system_clock_document_revision_history Document Revision History\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Doc. Rev.</td>\r
+ * <th>Date</td>\r
+ * <th>Comments</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>B</td>\r
+ * <td>06/2013</td>\r
+ * <td>Corrected documentation typos.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>A</td>\r
+ * <td>06/2013</td>\r
+ * <td>Initial release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+#endif /* SYSTEM_CLOCK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Clock Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CLOCK_CONFIG_CHECK_H\r
+# define CLOCK_CONFIG_CHECK_H\r
+\r
+#if !defined(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT)\r
+# error CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)\r
+# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_CPU_DIVIDER)\r
+# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_APBA_DIVIDER)\r
+# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_APBB_DIVIDER)\r
+# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC8M_PRESCALER)\r
+# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)\r
+# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC_ENABLE)\r
+# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)\r
+# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)\r
+# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)\r
+# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)\r
+# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)\r
+# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE)\r
+# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)\r
+# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)\r
+# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)\r
+# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)\r
+# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)\r
+# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)\r
+# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC32K_ENABLE)\r
+# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)\r
+# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)\r
+# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)\r
+# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)\r
+# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_ENABLE)\r
+# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)\r
+# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)\r
+# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_DFLL_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_COARSE_VALUE)\r
+# error CONF_CLOCK_DFLL_COARSE_VALUE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)\r
+# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)\r
+# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)\r
+# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)\r
+# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)\r
+# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)\r
+# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)\r
+# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)\r
+# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)\r
+# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_CONFIGURE_GCLK)\r
+# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_0_ENABLE)\r
+# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)\r
+# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)\r
+# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)\r
+# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_1_ENABLE)\r
+# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)\r
+# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)\r
+# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)\r
+# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_2_ENABLE)\r
+# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)\r
+# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)\r
+# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)\r
+# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_3_ENABLE)\r
+# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)\r
+# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)\r
+# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)\r
+# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_4_ENABLE)\r
+# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)\r
+# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)\r
+# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)\r
+# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_5_ENABLE)\r
+# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)\r
+# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)\r
+# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)\r
+# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_6_ENABLE)\r
+# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)\r
+# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)\r
+# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)\r
+# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_7_ENABLE)\r
+# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)\r
+# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)\r
+# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)\r
+# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clock.h\r
+#endif\r
+\r
+#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)\r
+# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clock.h\r
+#endif\r
+\r
+#endif /* CLOCK_CONFIG_CHECK_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Generic Clock Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <gclk.h>\r
+#include <clock.h>\r
+#include <system_interrupt.h>\r
+\r
+/**\r
+ * \brief Initializes the GCLK driver.\r
+ *\r
+ * Initializes the Generic Clock module, disabling and resetting all active\r
+ * Generic Clock Generators and Channels to their power-on default values.\r
+ */\r
+void system_gclk_init(void)\r
+{\r
+ /* Turn on the digital interface clock */\r
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);\r
+\r
+ /* Software reset the module to ensure it is re-initialized correctly */\r
+ GCLK->CTRL.reg = GCLK_CTRL_SWRST;\r
+ while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {\r
+ /* Wait for reset to complete */\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Writes a Generic Clock Generator configuration to the hardware module.\r
+ *\r
+ * Writes out a given configuration of a Generic Clock Generator configuration\r
+ * to the hardware module.\r
+ *\r
+ * \note Changing the clock source on the fly (on a running\r
+ * generator) can take additional time if the clock source is configured\r
+ * to only run on-demand (ONDEMAND bit is set) and it is not currently\r
+ * running (no peripheral is requesting the clock source). In this case\r
+ * the GCLK will request the new clock while still keeping a request to\r
+ * the old clock source until the new clock source is ready.\r
+ *\r
+ * \note This function will not start a generator that is not already running;\r
+ * to start the generator, call \ref system_gclk_gen_enable()\r
+ * after configuring a generator.\r
+ *\r
+ * \param[in] generator Generic Clock Generator index to configure\r
+ * \param[in] config Configuration settings for the generator\r
+ */\r
+void system_gclk_gen_set_config(\r
+ const uint8_t generator,\r
+ struct system_gclk_gen_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(config);\r
+\r
+ /* Cache new register configurations to minimize sync requirements. */\r
+ uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);\r
+ uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos);\r
+\r
+ /* Select the requested source clock for the generator */\r
+ new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;\r
+\r
+ /* Configure the clock to be either high or low when disabled */\r
+ if (config->high_when_disabled) {\r
+ new_genctrl_config |= GCLK_GENCTRL_OOV;\r
+ }\r
+\r
+ /* Configure if the clock output to I/O pin should be enabled. */\r
+ if (config->output_enable) {\r
+ new_genctrl_config |= GCLK_GENCTRL_OE;\r
+ }\r
+\r
+ /* Set division factor */\r
+ if (config->division_factor > 1) {\r
+ /* Check if division is a power of two */\r
+ if (((config->division_factor & (config->division_factor - 1)) == 0)) {\r
+ /* Determine the index of the highest bit set to get the\r
+ * division factor that must be loaded into the division\r
+ * register */\r
+\r
+ uint32_t div2_count = 0;\r
+\r
+ uint32_t mask;\r
+ for (mask = (1UL << 1); mask < config->division_factor;\r
+ mask <<= 1) {\r
+ div2_count++;\r
+ }\r
+\r
+ /* Set binary divider power of 2 division factor */\r
+ new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos;\r
+ new_genctrl_config |= GCLK_GENCTRL_DIVSEL;\r
+ } else {\r
+ /* Set integer division factor */\r
+\r
+ new_gendiv_config |=\r
+ (config->division_factor) << GCLK_GENDIV_DIV_Pos;\r
+\r
+ /* Enable non-binary division with increased duty cycle accuracy */\r
+ new_genctrl_config |= GCLK_GENCTRL_IDC;\r
+ }\r
+\r
+ }\r
+\r
+ /* Enable or disable the clock in standby mode */\r
+ if (config->run_in_standby) {\r
+ new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;\r
+ }\r
+\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+\r
+ system_interrupt_enter_critical_section();\r
+\r
+ /* Select the correct generator */\r
+ *((uint8_t*)&GCLK->GENDIV.reg) = generator;\r
+\r
+ /* Write the new generator configuration */\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+ GCLK->GENDIV.reg = new_gendiv_config;\r
+\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+ GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);\r
+\r
+ system_interrupt_leave_critical_section();\r
+}\r
+\r
+/**\r
+ * \brief Enables a Generic Clock Generator that was previously configured.\r
+ *\r
+ * Starts the clock generation of a Generic Clock Generator that was previously\r
+ * configured via a call to \ref system_gclk_gen_set_config().\r
+ *\r
+ * \param[in] generator Generic Clock Generator index to enable\r
+ */\r
+void system_gclk_gen_enable(\r
+ const uint8_t generator)\r
+{\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+\r
+ system_interrupt_enter_critical_section();\r
+\r
+ /* Select the requested generator */\r
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+\r
+ /* Enable generator */\r
+ GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;\r
+\r
+ system_interrupt_leave_critical_section();\r
+}\r
+\r
+/**\r
+ * \brief Disables a Generic Clock Generator that was previously enabled.\r
+ *\r
+ * Stops the clock generation of a Generic Clock Generator that was previously\r
+ * started via a call to \ref system_gclk_gen_enable().\r
+ *\r
+ * \param[in] generator Generic Clock Generator index to disable\r
+ */\r
+void system_gclk_gen_disable(\r
+ const uint8_t generator)\r
+{\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+\r
+ system_interrupt_enter_critical_section();\r
+\r
+ /* Select the requested generator */\r
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+\r
+ /* Disable generator */\r
+ GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;\r
+ while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {\r
+ /* Wait for clock to become disabled */\r
+ }\r
+\r
+ system_interrupt_leave_critical_section();\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the clock frequency of a Generic Clock generator.\r
+ *\r
+ * Determines the clock frequency (in Hz) of a specified Generic Clock\r
+ * generator, used as a source to a Generic Clock Channel module.\r
+ *\r
+ * \param[in] generator Generic Clock Generator index\r
+ *\r
+ * \return The frequency of the generic clock generator, in Hz.\r
+ */\r
+uint32_t system_gclk_gen_get_hz(\r
+ const uint8_t generator)\r
+{\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+\r
+ system_interrupt_enter_critical_section();\r
+\r
+ /* Select the appropriate generator */\r
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+\r
+ /* Get the frequency of the source connected to the GCLK generator */\r
+ uint32_t gen_input_hz = system_clock_source_get_hz(\r
+ (enum system_clock_source)GCLK->GENCTRL.bit.SRC);\r
+\r
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;\r
+\r
+ uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;\r
+\r
+ /* Select the appropriate generator division register */\r
+ *((uint8_t*)&GCLK->GENDIV.reg) = generator;\r
+ while (system_gclk_is_syncing()) {\r
+ /* Wait for synchronization */\r
+ };\r
+\r
+ uint32_t divider = GCLK->GENDIV.bit.DIV;\r
+\r
+ system_interrupt_leave_critical_section();\r
+\r
+ /* Check if the generator is using fractional or binary division */\r
+ if (!divsel && divider > 1) {\r
+ gen_input_hz /= divider;\r
+ } else if (divsel) {\r
+ gen_input_hz >>= (divider+1);\r
+ }\r
+\r
+ return gen_input_hz;\r
+}\r
+\r
+/**\r
+ * \brief Writes a Generic Clock configuration to the hardware module.\r
+ *\r
+ * Writes out a given configuration of a Generic Clock configuration to the\r
+ * hardware module. If the clock is currently running, it will be stopped.\r
+ *\r
+ * \note Once called the clock will not be running; to start the clock,\r
+ * call \ref system_gclk_chan_enable() after configuring a clock channel.\r
+ *\r
+ * \param[in] channel Generic Clock channel to configure\r
+ * \param[in] config Configuration settings for the clock\r
+ */\r
+void system_gclk_chan_set_config(\r
+ const uint8_t channel,\r
+ struct system_gclk_chan_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(config);\r
+\r
+ /* Cache the new config to reduce sync requirements */\r
+ uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);\r
+\r
+ /* Select the desired generic clock generator */\r
+ new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;\r
+\r
+ /* Enable write lock if requested to prevent further modification */\r
+ if (config->write_lock) {\r
+ new_clkctrl_config |= GCLK_CLKCTRL_WRTLOCK;\r
+ }\r
+\r
+ /* Disable generic clock channel */\r
+ system_gclk_chan_disable(channel);\r
+\r
+ /* Write the new configuration */\r
+ GCLK->CLKCTRL.reg = new_clkctrl_config;\r
+}\r
+\r
+/**\r
+ * \brief Enables a Generic Clock that was previously configured.\r
+ *\r
+ * Starts the clock generation of a Generic Clock that was previously\r
+ * configured via a call to \ref system_gclk_chan_set_config().\r
+ *\r
+ * \param[in] channel Generic Clock channel to enable\r
+ */\r
+void system_gclk_chan_enable(\r
+ const uint8_t channel)\r
+{\r
+ system_interrupt_enter_critical_section();\r
+\r
+ /* Select the requested generator channel */\r
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;\r
+\r
+ /* Enable the generic clock */\r
+ GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;\r
+\r
+ system_interrupt_leave_critical_section();\r
+}\r
+\r
+/**\r
+ * \brief Disables a Generic Clock that was previously enabled.\r
+ *\r
+ * Stops the clock generation of a Generic Clock that was previously started\r
+ * via a call to \ref system_gclk_chan_enable().\r
+ *\r
+ * \param[in] channel Generic Clock channel to disable\r
+ */\r
+void system_gclk_chan_disable(\r
+ const uint8_t channel)\r
+{\r
+ system_interrupt_enter_critical_section();\r
+\r
+ /* Select the requested generator channel */\r
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;\r
+\r
+ /* Disable the generic clock */\r
+ GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;\r
+ while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {\r
+ /* Wait for clock to become disabled */\r
+ }\r
+\r
+ system_interrupt_leave_critical_section();\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the clock frequency of a Generic Clock channel.\r
+ *\r
+ * Determines the clock frequency (in Hz) of a specified Generic Clock\r
+ * channel, used as a source to a device peripheral module.\r
+ *\r
+ * \param[in] channel Generic Clock Channel index\r
+ *\r
+ * \return The frequency of the generic clock channel, in Hz.\r
+ */\r
+uint32_t system_gclk_chan_get_hz(\r
+ const uint8_t channel)\r
+{\r
+ uint8_t gen_id;\r
+\r
+ system_interrupt_enter_critical_section();\r
+\r
+ /* Select the requested generic clock channel */\r
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;\r
+ gen_id = GCLK->CLKCTRL.bit.GEN;\r
+\r
+ system_interrupt_leave_critical_section();\r
+\r
+ /* Return the clock speed of the associated GCLK generator */\r
+ return system_gclk_gen_get_hz(gen_id);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Generic Clock Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED\r
+#define SYSTEM_CLOCK_GCLK_H_INCLUDED\r
+\r
+/**\r
+ * \addtogroup asfdoc_samd20_system_clock_group\r
+ *\r
+ * @{\r
+ */\r
+\r
+#include <compiler.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief List of available GCLK generators.\r
+ *\r
+ * List of Available GCLK generators. This enum is used in the peripheral\r
+ * device drivers to select the GCLK generator to be used for its operation.\r
+ *\r
+ * The number of GCLK generators available is device dependent.\r
+ */\r
+enum gclk_generator {\r
+ /** GCLK generator channel 0. */\r
+ GCLK_GENERATOR_0,\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)\r
+ /** GCLK generator channel 1. */\r
+ GCLK_GENERATOR_1,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)\r
+ /** GCLK generator channel 2. */\r
+ GCLK_GENERATOR_2,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)\r
+ /** GCLK generator channel 3. */\r
+ GCLK_GENERATOR_3,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)\r
+ /** GCLK generator channel 4. */\r
+ GCLK_GENERATOR_4,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)\r
+ /** GCLK generator channel 5. */\r
+ GCLK_GENERATOR_5,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)\r
+ /** GCLK generator channel 6. */\r
+ GCLK_GENERATOR_6,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)\r
+ /** GCLK generator channel 7. */\r
+ GCLK_GENERATOR_7,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)\r
+ /** GCLK generator channel 8. */\r
+ GCLK_GENERATOR_8,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)\r
+ /** GCLK generator channel 9. */\r
+ GCLK_GENERATOR_9,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)\r
+ /** GCLK generator channel 10. */\r
+ GCLK_GENERATOR_10,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)\r
+ /** GCLK generator channel 11. */\r
+ GCLK_GENERATOR_11,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)\r
+ /** GCLK generator channel 12. */\r
+ GCLK_GENERATOR_12,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)\r
+ /** GCLK generator channel 13. */\r
+ GCLK_GENERATOR_13,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)\r
+ /** GCLK generator channel 14. */\r
+ GCLK_GENERATOR_14,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)\r
+ /** GCLK generator channel 15. */\r
+ GCLK_GENERATOR_15,\r
+#endif\r
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)\r
+ /** GCLK generator channel 16. */\r
+ GCLK_GENERATOR_16,\r
+#endif\r
+};\r
+\r
+/**\r
+ * \brief Generic Clock Generator configuration structure.\r
+ *\r
+ * Configuration structure for a Generic Clock Generator channel. This\r
+ * structure should be initialized by the\r
+ * \ref system_gclk_gen_get_config_defaults() function before being modified by\r
+ * the user application.\r
+ */\r
+struct system_gclk_gen_config {\r
+ /** Source clock input channel index. */\r
+ uint8_t source_clock;\r
+ /** If \c true, the generator output level is high when disabled. */\r
+ bool high_when_disabled;\r
+ /** Integer division factor of the clock output compared to the input. */\r
+ uint32_t division_factor;\r
+ /** If \c true, the clock is kept enabled during device standby mode. */\r
+ bool run_in_standby;\r
+ /** If \c true, enables GCLK generator clock output to a GPIO pin. */\r
+ bool output_enable;\r
+};\r
+\r
+/**\r
+ * \brief Generic Clock configuration structure.\r
+ *\r
+ * Configuration structure for a Generic Clock channel. This structure\r
+ * should be initialized by the \ref system_gclk_chan_get_config_defaults()\r
+ * function before being modified by the user application.\r
+ */\r
+struct system_gclk_chan_config {\r
+ /** Generic Clock Generator source channel. */\r
+ enum gclk_generator source_generator;\r
+ /** If \c true the clock configuration will be locked until the device is\r
+ * reset. */\r
+ bool write_lock;\r
+};\r
+\r
+/** \name Generic Clock management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.\r
+ *\r
+ * Checks to see if the underlying hardware peripheral module(s) are currently\r
+ * synchronizing across multiple clock domains to the hardware bus, This\r
+ * function can be used to delay further operations on a module until such time\r
+ * that it is ready, to prevent blocking delays for synchronization in the\r
+ * user application.\r
+ *\r
+ * \return Synchronization status of the underlying hardware module(s).\r
+ *\r
+ * \retval true if the module has completed synchronization\r
+ * \retval false if the module synchronization is ongoing\r
+ */\r
+static inline bool system_gclk_is_syncing(void)\r
+{\r
+ if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {\r
+ return true;\r
+ }\r
+\r
+ return false;\r
+}\r
+\r
+void system_gclk_init(void);\r
+\r
+/** @} */\r
+\r
+\r
+/**\r
+ * \name Generic Clock management (Generators)\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Initializes a Generic Clock Generator configuration structure to defaults.\r
+ *\r
+ * Initializes a given Generic Clock Generator configuration structure to\r
+ * a set of known default values. This function should be called on all\r
+ * new instances of these configuration structures before being modified\r
+ * by the user application.\r
+ *\r
+ * The default configuration is as follows:\r
+ * \li Clock is generated undivided from the source frequency\r
+ * \li Clock generator output is low when the generator is disabled\r
+ * \li The input clock is sourced from input clock channel 0\r
+ * \li Clock will be disabled during sleep\r
+ * \li The clock output will not be routed to a physical GPIO pin\r
+ *\r
+ * \param[out] config Configuration structure to initialize to default values\r
+ */\r
+static inline void system_gclk_gen_get_config_defaults(\r
+ struct system_gclk_gen_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(config);\r
+\r
+ /* Default configuration values */\r
+ config->division_factor = 1;\r
+ config->high_when_disabled = false;\r
+ config->source_clock = GCLK_SOURCE_OSC8M;\r
+ config->run_in_standby = false;\r
+ config->output_enable = false;\r
+}\r
+\r
+void system_gclk_gen_set_config(\r
+ const uint8_t generator,\r
+ struct system_gclk_gen_config *const config);\r
+\r
+void system_gclk_gen_enable(\r
+ const uint8_t generator);\r
+\r
+void system_gclk_gen_disable(\r
+ const uint8_t generator);\r
+\r
+/** @} */\r
+\r
+\r
+/**\r
+ * \name Generic Clock management (Channels)\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Initializes a Generic Clock configuration structure to defaults.\r
+ *\r
+ * Initializes a given Generic Clock configuration structure to a set of\r
+ * known default values. This function should be called on all new\r
+ * instances of these configuration structures before being modified by the\r
+ * user application.\r
+ *\r
+ * The default configuration is as follows:\r
+ * \li Clock is sourced from the Generic Clock Generator channel 0\r
+ * \li Clock configuration will not be write-locked when set\r
+ *\r
+ * \param[out] config Configuration structure to initialize to default values\r
+ */\r
+static inline void system_gclk_chan_get_config_defaults(\r
+ struct system_gclk_chan_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(config);\r
+\r
+ /* Default configuration values */\r
+ config->source_generator = GCLK_GENERATOR_0;\r
+ config->write_lock = false;\r
+}\r
+\r
+void system_gclk_chan_set_config(\r
+ const uint8_t channel,\r
+ struct system_gclk_chan_config *const config);\r
+\r
+void system_gclk_chan_enable(\r
+ const uint8_t channel);\r
+\r
+void system_gclk_chan_disable(\r
+ const uint8_t channel);\r
+\r
+/** @} */\r
+\r
+\r
+/**\r
+ * \name Generic Clock frequency retrieval\r
+ * @{\r
+ */\r
+\r
+uint32_t system_gclk_gen_get_hz(\r
+ const uint8_t generator);\r
+\r
+uint32_t system_gclk_chan_get_hz(\r
+ const uint8_t channel);\r
+\r
+/** @} */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @} */\r
+\r
+#endif\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 System Clock Driver Quick Start\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_clock_basic_use_case Quick Start Guide for SYSTEM CLOCK - Basic\r
+ *\r
+ * In this case we apply the following configuration:\r
+ * - RC8MHz (internal 8MHz RC oscillator)\r
+ * - Divide by 4, giving a frequency of 2MHz\r
+ * - DFLL (Digital frequency locked loop)\r
+ * - Open loop mode\r
+ * - 48MHz frequency\r
+ * - CPU clock\r
+ * - Use the DFLL, configured to 48MHz\r
+ *\r
+ * \section asfdoc_samd20_system_clock_basic_use_case_setup Setup\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_basic_use_case_setup_prereq Prerequisites\r
+ * There are no special setup requirements for this use-case.\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_basic_use_case_setup_code Code\r
+ * Copy-paste the following setup code to your application:\r
+ * \snippet qs_clock_source.c setup\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_basic_use_case_setup_flow Workflow\r
+ * -# Create a EXTOSC32K module configuration struct, which can be filled\r
+ * out to adjust the configuration of the external 32KHz oscillator channel.\r
+ * \snippet qs_clock_source.c config_extosc32k_config\r
+ *\r
+ * -# Initialize the oscillator configuration struct with the module's default\r
+ * values.\r
+ * \note This should always be performed before using the configuration\r
+ * struct to ensure that all values are initialized to known default\r
+ * settings.\r
+ *\r
+ * \snippet qs_clock_source.c config_extosc32k_get_defaults\r
+ *\r
+ * -# Alter the EXTOSC32K module configuration struct to require a start-up time\r
+ * of 4096 clock cycles.\r
+ * \snippet qs_clock_source.c config_extosc32k_change_defaults\r
+ *\r
+ * -# Write the new configuration to the EXTOSC32K module.\r
+ * \snippet qs_clock_source.c config_extosc32k_set_config\r
+ *\r
+ * -# Create a DFLL module configuration struct, which can be filled\r
+ * out to adjust the configuration of the external 32KHz oscillator channel.\r
+ * \snippet qs_clock_source.c config_dfll_config\r
+ *\r
+ * -# Initialize the DFLL oscillator configuration struct with the module's\r
+ * default values.\r
+ * \note This should always be performed before using the configuration\r
+ * struct to ensure that all values are initialized to known default\r
+ * settings.\r
+ *\r
+ * \snippet qs_clock_source.c config_dfll_get_defaults\r
+ *\r
+ * -# Write the new configuration to the DFLL module.\r
+ * \snippet qs_clock_source.c config_extosc32k_set_config\r
+\r
+\r
+ * \section asfdoc_samd20_system_clock_basic_use_case_use_main Use Case\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_basic_use_case_code Code\r
+ *\r
+ * Copy-paste the following code to your user application:\r
+ * \snippet qs_clock_source.c main\r
+ *\r
+ * \subsection asfdoc_samd20_system_clock_basic_use_case_flow Workflow\r
+ * -# Configure the external 32KHz oscillator source using the previously\r
+ * defined setup function.\r
+ * \snippet qs_clock_source.c config_extosc32k_main\r
+ *\r
+ * -# Enable the configured external 32KHz oscillator source.\r
+ * \snippet qs_clock_source.c enable_extosc32k_main\r
+ *\r
+ * -# Configure the DFLL oscillator source using the previously defined setup\r
+ * function.\r
+ * \snippet qs_clock_source.c config_dfll_main\r
+ *\r
+ * -# Enable the configured DFLL oscillator source.\r
+ * \snippet qs_clock_source.c enable_dfll_main\r
+ *\r
+ * -# Switch the system clock source to the DFLL, by reconfiguring the main\r
+ * clock generator.\r
+ * \snippet qs_clock_source.c set_sys_clk_src\r
+ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Generic Clock Driver Quick Start\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_gclk_basic_use_case Quick Start Guide for SYSTEM CLOCK - GCLK Configuration\r
+ *\r
+ * In this use case, the GCLK module is configured for:\r
+ * \li One generator attached to the internal 8MHz RC oscillator clock source\r
+ * \li Generator output equal to input frequency divided by a factor of 128\r
+ * \li One channel (connected to the TC0 module) enabled with the enabled generator selected\r
+ *\r
+ * This use case configures a clock channel to output a clock for a peripheral\r
+ * within the device, by first setting up a clock generator from a master clock\r
+ * source, and then linking the generator to the desired channel. This clock\r
+ * can then be used to clock a module within the device.\r
+ *\r
+ * \section asfdoc_samd20_system_gclk_basic_use_case_setup Setup\r
+ *\r
+ * \subsection asfdoc_samd20_system_gclk_basic_use_case_setup_prereq Prerequisites\r
+ * There are no special setup requirements for this use-case.\r
+ *\r
+ * \subsection asfdoc_samd20_system_gclk_basic_use_case_setup_code Code\r
+ * Copy-paste the following setup code to your user application:\r
+ * \snippet qs_gclk_basic.c setup\r
+ *\r
+ * Add to user application initialization (typically the start of \c main()):\r
+ * \snippet qs_gclk_basic.c setup_init\r
+ *\r
+ * \subsection asfdoc_samd20_system_gclk_basic_use_case_setup_flow Workflow\r
+ * -# Create a GCLK generator configuration struct, which can be filled out to\r
+ * adjust the configuration of a single clock generator.\r
+ * \snippet qs_gclk_basic.c setup_1\r
+ * -# Initialize the generator configuration struct with the module's default\r
+ * values.\r
+ * \note This should always be performed before using the configuration\r
+ * struct to ensure that all values are initialized to known default\r
+ * settings.\r
+ *\r
+ * \snippet qs_gclk_basic.c setup_2\r
+ * -# Adjust the configuration struct to request that the master clock source\r
+ * channel 0 be used as the source of the generator, and set the generator\r
+ * output prescaler to divide the input clock by a factor of 128.\r
+ * \snippet qs_gclk_basic.c setup_3\r
+ * -# Configure the generator using the configuration structure.\r
+ * \note The existing configuration struct may be re-used, as long as any\r
+ * values that have been altered from the default settings are taken\r
+ * into account by the user application.\r
+ *\r
+ * \snippet qs_gclk_basic.c setup_4\r
+ * -# Enable the generator once it has been properly configured, to begin clock\r
+ * generation.\r
+ * \snippet qs_gclk_basic.c setup_5\r
+ *\r
+ * -# Create a GCLK channel configuration struct, which can be filled out to\r
+ * adjust the configuration of a single generic clock channel.\r
+ * \snippet qs_gclk_basic.c setup_6\r
+ * -# Initialize the channel configuration struct with the module's default\r
+ * values.\r
+ * \note This should always be performed before using the configuration\r
+ * struct to ensure that all values are initialized to known default\r
+ * settings.\r
+ *\r
+ * \snippet qs_gclk_basic.c setup_7\r
+ * -# Adjust the configuration struct to request that the previously configured\r
+ * and enabled clock generator be used as the clock source for the channel.\r
+ * \snippet qs_gclk_basic.c setup_8\r
+ * -# Configure the channel using the configuration structure.\r
+ * \note The existing configuration struct may be re-used, as long as any\r
+ * values that have been altered from the default settings are taken\r
+ * into account by the user application.\r
+ *\r
+ * \snippet qs_gclk_basic.c setup_9\r
+ * -# Enable the channel once it has been properly configured, to output the\r
+ * clock to the channel's peripheral module consumers.\r
+ * \snippet qs_gclk_basic.c setup_10\r
+ *\r
+ * \section asfdoc_samd20_system_gclk_basic_use_case_main Use Case\r
+ *\r
+ * \subsection asfdoc_samd20_system_gclk_basic_use_case_code Code\r
+ * Copy-paste the following code to your user application:\r
+ * \snippet qs_gclk_basic.c main\r
+ *\r
+ * \subsection asfdoc_samd20_system_gclk_basic_use_case_flow Workflow\r
+ * -# As the clock is generated asynchronously to the system core, no special\r
+ * extra application code is required.\r
+ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 External Interrupt Driver Quick Start\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_interrupt_critsec_use_case Quick Start Guide for SYSTEM INTERRUPT - Critical Section Use Case\r
+ *\r
+ * In this case we perform a critical piece of code, disabling all interrupts\r
+ * while a global shared flag is read. During the critical section, no interrupts\r
+ * may occur.\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_critsec_use_case_setup Setup\r
+ *\r
+ * \subsection asfdoc_samd20_system_interrupt_critsec_use_case_setup_prereq Prerequisites\r
+ * There are no special setup requirements for this use-case.\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_critsec_use_case_use_main Use Case\r
+ *\r
+ * \subsection asfdoc_samd20_system_interrupt_critsec_use_case_code Code\r
+ * Copy-paste the following code to your user application:\r
+ * \snippet qs_system_interrupt.c main_1\r
+ *\r
+ * \subsection asfdoc_samd20_system_interrupt_critsec_use_case_flow Workflow\r
+ * -# Enter a critical section to disable global interrupts.\r
+ * \note Critical sections <i>may</i> be nested if desired; if nested, global\r
+ * interrupts will only be re-enabled once the outer-most critical\r
+ * section has completed.\r
+ *\r
+ * \snippet qs_system_interrupt.c critical_section_start\r
+ *\r
+ * -# Check a global shared flag and perform a response. This code may be any\r
+ * critical code that requires exclusive access to all resources without the\r
+ * possibility of interruption.\r
+ * \snippet qs_system_interrupt.c do_critical_code\r
+ *\r
+ * -# Exit the critical section to re-enable global interrupts.\r
+ * \snippet qs_system_interrupt.c critical_section_end\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_interrupt_enablemodint_use_case Quick Start Guide for SYSTEM INTERRUPT - Enable Module Interrupt Use Case\r
+ *\r
+ * In this case we enable interrupt handling for a specific module, as well as\r
+ * enable interrupts globally for the device.\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_enablemodint_use_case_setup Setup\r
+ *\r
+ * \subsection asfdoc_samd20_system_interrupt_enablemodint_use_case_setup_prereq Prerequisites\r
+ * There are no special setup requirements for this use-case.\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_enablemodint_use_case_use_main Use Case\r
+ *\r
+ * \subsection asfdoc_samd20_system_interrupt_enablemodint_use_case_code Code\r
+ * Copy-paste the following code to your user application:\r
+ * \snippet qs_system_interrupt.c main_2\r
+ *\r
+ * \subsection asfdoc_samd20_system_interrupt_enablemodint_use_case_flow Workflow\r
+ * -# Enable interrupt handling for the device's RTC peripheral.\r
+ * \snippet qs_system_interrupt.c module_int_enable\r
+ *\r
+ * -# Enable global interrupts, so that any enabled and active interrupt sources\r
+ * can trigger their respective handler functions.\r
+ * \snippet qs_system_interrupt.c global_int_enable\r
+ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 System Interrupt Driver\r
+ *\r
+ * Copyright (C) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include "system_interrupt.h"\r
+\r
+/**\r
+ * \brief Check if a interrupt line is pending\r
+ *\r
+ * Checks if the requested interrupt vector is pending.\r
+ *\r
+ * \param[in] vector Interrupt vector number to check\r
+ *\r
+ * \returns A boolean identifying if the requested interrupt vector is pending.\r
+ *\r
+ * \retval true Specified interrupt vector is pending\r
+ * \retval false Specified interrupt vector is not pending\r
+ *\r
+ */\r
+bool system_interrupt_is_pending(\r
+ const enum system_interrupt_vector vector)\r
+{\r
+ bool result;\r
+\r
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {\r
+ result = ((NVIC->ISPR[0] & (1 << vector)) != 0);\r
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {\r
+ result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);\r
+ } else {\r
+ Assert(false);\r
+ result = false;\r
+ }\r
+\r
+ return result;\r
+}\r
+\r
+/**\r
+ * \brief Set a interrupt vector as pending\r
+ *\r
+ * Set the requested interrupt vector as pending (i.e issues a software\r
+ * interrupt request for the specified vector). The software handler will be\r
+ * handled (if enabled) in a priority order based on vector number and\r
+ * configured priority settings.\r
+ *\r
+ * \param[in] vector Interrupt vector number which is set as pending\r
+ *\r
+ * \returns Status code identifying if the vector was successfully set as\r
+ * pending.\r
+ *\r
+ * \retval STATUS_OK If no error was detected\r
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given\r
+ */\r
+enum status_code system_interrupt_set_pending(\r
+ const enum system_interrupt_vector vector)\r
+{\r
+ enum status_code status = STATUS_OK;\r
+\r
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {\r
+ NVIC->ISPR[0] = (1 << vector);\r
+ } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {\r
+ /* Note: Because NMI has highest priority it will be executed\r
+ * immediately after it has been set pending */\r
+ SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;\r
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {\r
+ SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;\r
+ } else {\r
+ /* The user want to set something unsupported as pending */\r
+ Assert(false);\r
+ status = STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Clear pending interrupt vector\r
+ *\r
+ * Clear a pending interrupt vector, so the software handler is not executed.\r
+ *\r
+ * \param[in] vector Interrupt vector number to clear\r
+ *\r
+ * \returns A status code identifying if the interrupt pending state was\r
+ * successfully cleared.\r
+ *\r
+ * \retval STATUS_OK If no error was detected\r
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given\r
+ */\r
+enum status_code system_interrupt_clear_pending(\r
+ const enum system_interrupt_vector vector)\r
+{\r
+ enum status_code status = STATUS_OK;\r
+\r
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {\r
+ NVIC->ICPR[0] = (1 << vector);\r
+ } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {\r
+ /* Note: Clearing of NMI pending interrupts does not make sense and is\r
+ * not supported by the device, as it has the highest priority and will\r
+ * always be executed at the moment it is set */\r
+ return STATUS_ERR_INVALID_ARG;\r
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {\r
+ SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;\r
+ } else {\r
+ Assert(false);\r
+ status = STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Set interrupt vector priority level\r
+ *\r
+ * Set the priority level of an external interrupt or exception.\r
+ *\r
+ * \param[in] vector Interrupt vector to change\r
+ * \param[in] priority_level New vector priority level to set\r
+ *\r
+ * \returns Status code indicating if the priority level of the interrupt was\r
+ * successfully set.\r
+ *\r
+ * \retval STATUS_OK If no error was detected\r
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given\r
+ */\r
+enum status_code system_interrupt_set_priority(\r
+ const enum system_interrupt_vector vector,\r
+ const enum system_interrupt_priority_level priority_level)\r
+{\r
+ enum status_code status = STATUS_OK;\r
+\r
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {\r
+ uint8_t register_num = vector / 4;\r
+ uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);\r
+\r
+ NVIC->IP[register_num] = (priority_level << priority_pos);\r
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {\r
+ SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);\r
+ } else {\r
+ Assert(false);\r
+ status = STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Get interrupt vector priority level\r
+ *\r
+ * Retrieves the priority level of the requested external interrupt or exception.\r
+ *\r
+ * \param[in] vector Interrupt vector of which the priority level will be read\r
+ *\r
+ * \return Currently configured interrupt priority level of the given interrupt\r
+ * vector.\r
+ */\r
+enum system_interrupt_priority_level system_interrupt_get_priority(\r
+ const enum system_interrupt_vector vector)\r
+{\r
+ uint8_t register_num = vector / 4;\r
+ uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);\r
+\r
+ enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;\r
+\r
+ if (vector >= 0) {\r
+ priority = (enum system_interrupt_priority_level)\r
+ ((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);\r
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {\r
+ priority = (enum system_interrupt_priority_level)\r
+ ((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);\r
+ }\r
+\r
+ return priority;\r
+}\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 System Interrupt Driver\r
+ *\r
+ * Copyright (C) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SYSTEM_INTERRUPT_H_INCLUDED\r
+#define SYSTEM_INTERRUPT_H_INCLUDED\r
+\r
+/**\r
+ * \defgroup asfdoc_samd20_system_interrupt_group SAM D20 System Interrupt Driver (SYSTEM INTERRUPT)\r
+ *\r
+ * This driver for SAM D20 devices provides an interface for the configuration\r
+ * and management of internal software and hardware interrupts/exceptions.\r
+ *\r
+ * The following peripherals are used by this module:\r
+ *\r
+ * - NVIC (Nested Vector Interrupt Controller)\r
+ *\r
+ * The outline of this documentation is as follows:\r
+ * - \ref asfdoc_samd20_system_interrupt_prerequisites\r
+ * - \ref asfdoc_samd20_system_interrupt_module_overview\r
+ * - \ref asfdoc_samd20_system_interrupt_special_considerations\r
+ * - \ref asfdoc_samd20_system_interrupt_extra_info\r
+ * - \ref asfdoc_samd20_system_interrupt_examples\r
+ * - \ref asfdoc_samd20_system_interrupt_api_overview\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_prerequisites Prerequisites\r
+ *\r
+ * There are no prerequisites for this module.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_module_overview Module Overview\r
+ *\r
+ * The Cortex M0+ core contains an interrupt an exception vector table, which\r
+ * can be used to configure the device's interrupt handlers; individual\r
+ * interrupts and exceptions can be enabled and disabled, as well as configured\r
+ * with a variable priority.\r
+ *\r
+ * This driver provides a set of wrappers around the core interrupt functions,\r
+ * to expose a simple API for the management of global and individual interrupts\r
+ * within the device.\r
+ *\r
+ * \subsection asfdoc_samd20_system_interrupt_module_overview_criticalsec Critical Sections\r
+ * In some applications it is important to ensure that no interrupts may be\r
+ * executed by the system whilst a critical portion of code is being run; for\r
+ * example, a buffer may be copied from one context to another - during which\r
+ * interrupts must be disabled to avoid corruption of the source buffer contents\r
+ * until the copy has completed. This driver provides a basic API to enter and\r
+ * exit nested critical sections, so that global interrupts can be kept disabled\r
+ * for as long as necessary to complete a critical application code section.\r
+ *\r
+ * \subsection asfdoc_samd20_system_interrupt_module_overview_softints Software Interrupts\r
+ * For some applications, it may be desirable to raise a module or core\r
+ * interrupt via software. For this reason, a set of APIs to set an interrupt or\r
+ * exception as pending are provided to the user application.\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_special_considerations Special Considerations\r
+ *\r
+ * Interrupts from peripherals in the SAM D20 devices are on a per-module basis;\r
+ * an interrupt raised from any source within a module will cause a single,\r
+ * module-common handler to execute. It is the user application or driver's\r
+ * responsibility to de-multiplex the module-common interrupt to determine the\r
+ * exact interrupt cause.\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_extra_info Extra Information\r
+ *\r
+ * For extra information see \ref asfdoc_samd20_system_interrupt_extra. This includes:\r
+ * - \ref asfdoc_samd20_system_interrupt_extra_acronyms\r
+ * - \ref asfdoc_samd20_system_interrupt_extra_dependencies\r
+ * - \ref asfdoc_samd20_system_interrupt_extra_errata\r
+ * - \ref asfdoc_samd20_system_interrupt_extra_history\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_examples Examples\r
+ *\r
+ * For a list of examples related to this driver, see\r
+ * \ref asfdoc_samd20_system_interrupt_exqsg.\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_api_overview API Overview\r
+ * @{\r
+ */\r
+\r
+#include <compiler.h>\r
+#include <core_cm0plus.h>\r
+\r
+#if !defined(__DOXYGEN__)\r
+/* Generates a interrupt vector table enum list entry for a given module type\r
+ and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */\r
+# define _MODULE_IRQn(n, module) \\r
+ SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,\r
+\r
+/* Generates interrupt vector table enum list entries for all instances of a\r
+ given module type on the selected device. */\r
+# define _SYSTEM_INTERRUPT_MODULES(name) \\r
+ MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)\r
+\r
+\r
+# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f\r
+# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000007\r
+\r
+# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0\r
+\r
+# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 29\r
+#endif\r
+\r
+/**\r
+ * \brief Table of possible system interrupt/exception vector numbers.\r
+ *\r
+ * Table of all possible interrupt and exception vector indexes within the\r
+ * device.\r
+ */\r
+enum system_interrupt_vector {\r
+ /** Interrupt vector index for a NMI interrupt. */\r
+ SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn,\r
+ /** Interrupt vector index for a Hard Fault memory access exception. */\r
+ SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn,\r
+ /** Interrupt vector index for a Supervisor Call exception. */\r
+ SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn,\r
+ /** Interrupt vector index for a Pending Supervisor interrupt. */\r
+ SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn,\r
+ /** Interrupt vector index for a System Tick interrupt. */\r
+ SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn,\r
+\r
+ /** Interrupt vector index for a Power Manager peripheral interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn,\r
+ /** Interrupt vector index for a System Control peripheral interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn,\r
+ /** Interrupt vector index for a Watch Dog peripheral interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn,\r
+ /** Interrupt vector index for a Real Time Clock peripheral interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn,\r
+ /** Interrupt vector index for an External Interrupt peripheral interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn,\r
+ /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn,\r
+ /** Interrupt vector index for an Event System interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn,\r
+#if defined(__DOXYGEN__)\r
+ /** Interrupt vector index for a SERCOM peripheral interrupt.\r
+ *\r
+ * Each specific device may contain several SERCOM peripherals; each module\r
+ * instance will have its own entry in the table, with the instance number\r
+ * substituted for "n" in the entry name (e.g.\r
+ * \c SYSTEM_INTERRUPT_MODULE_SERCOM0).\r
+ */\r
+ SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn,\r
+ /** Interrupt vector index for a Timer/Counter peripheral interrupt.\r
+ *\r
+ * Each specific device may contain several TC peripherals; each module\r
+ * instance will have its own entry in the table, with the instance number\r
+ * substituted for "n" in the entry name (e.g.\r
+ * \c SYSTEM_INTERRUPT_MODULE_TC0).\r
+ */\r
+ SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn,\r
+#else\r
+ _SYSTEM_INTERRUPT_MODULES(SERCOM)\r
+ _SYSTEM_INTERRUPT_MODULES(TC)\r
+#endif\r
+ /** Interrupt vector index for an Analog Comparator peripheral interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn,\r
+ /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn,\r
+ /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */\r
+ SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn,\r
+};\r
+\r
+/**\r
+ * \brief Table of possible system interrupt/exception vector priorities.\r
+ *\r
+ * Table of all possible interrupt and exception vector priorities within the\r
+ * device.\r
+ */\r
+enum system_interrupt_priority_level {\r
+ /** Priority level 0, the highest possible interrupt priority. */\r
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0,\r
+ /** Priority level 1. */\r
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1,\r
+ /** Priority level 2. */\r
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2,\r
+ /** Priority level 3, the lowest possible interrupt priority. */\r
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3,\r
+};\r
+\r
+/**\r
+ * \name Critical Section Management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Enters a critical section\r
+ *\r
+ * Disables global interrupts. To support nested critical sections, an internal\r
+ * count of the critical section nesting will be kept, so that global interrupts\r
+ * are only re-enabled upon leaving the outermost nested critical section.\r
+ *\r
+ */\r
+static inline void system_interrupt_enter_critical_section(void)\r
+{\r
+ cpu_irq_enter_critical();\r
+}\r
+\r
+/**\r
+ * \brief Leaves a critical section\r
+ *\r
+ * Enables global interrupts. To support nested critical sections, an internal\r
+ * count of the critical section nesting will be kept, so that global interrupts\r
+ * are only re-enabled upon leaving the outermost nested critical section.\r
+ *\r
+ */\r
+static inline void system_interrupt_leave_critical_section(void)\r
+{\r
+ cpu_irq_leave_critical();\r
+}\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \name Interrupt Enabling/Disabling\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Check if global interrupts are enabled\r
+ *\r
+ * Checks if global interrupts are currently enabled.\r
+ *\r
+ * \returns A boolean that identifies if the global interrupts are enabled or not.\r
+ *\r
+ * \retval true Global interrupts are currently enabled\r
+ * \retval false Global interrupts are currently disabled\r
+ *\r
+ */\r
+static inline bool system_interrupt_is_global_enabled(void)\r
+{\r
+ return cpu_irq_is_enabled();\r
+}\r
+\r
+/**\r
+ * \brief Enables global interrupts\r
+ *\r
+ * Enables global interrupts in the device to fire any enabled interrupt handlers.\r
+ */\r
+static inline void system_interrupt_enable_global(void)\r
+{\r
+ cpu_irq_enable();\r
+}\r
+\r
+/**\r
+ * \brief Disables global interrupts\r
+ *\r
+ * Disabled global interrupts in the device, preventing any enabled interrupt\r
+ * handlers from executing.\r
+ */\r
+static inline void system_interrupt_disable_global(void)\r
+{\r
+ cpu_irq_disable();\r
+}\r
+\r
+/**\r
+ * \brief Checks if an interrupt vector is enabled or not\r
+ *\r
+ * Checks if a specific interrupt vector is currently enabled.\r
+ *\r
+ * \param[in] vector Interrupt vector number to check\r
+ *\r
+ * \returns A variable identifying if the requested interrupt vector is enabled\r
+ *\r
+ * \retval true Specified interrupt vector is currently enabled\r
+ * \retval false Specified interrupt vector is currently disabled\r
+ *\r
+ */\r
+static inline bool system_interrupt_is_enabled(\r
+ const enum system_interrupt_vector vector)\r
+{\r
+ return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt vector\r
+ *\r
+ * Enables execution of the software handler for the requested interrupt vector.\r
+ *\r
+ * \param[in] vector Interrupt vector to enable\r
+ */\r
+static inline void system_interrupt_enable(\r
+ const enum system_interrupt_vector vector)\r
+{\r
+ NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));\r
+}\r
+\r
+/**\r
+ * \brief Disable interrupt vector\r
+ *\r
+ * Disables execution of the software handler for the requested interrupt vector.\r
+ *\r
+ * \param[in] vector Interrupt vector to disable\r
+ */\r
+static inline void system_interrupt_disable(\r
+ const enum system_interrupt_vector vector)\r
+{\r
+ NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));\r
+}\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \name Interrupt State Management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Get active interrupt (if any)\r
+ *\r
+ * Return the vector number for the current executing software handler, if any.\r
+ *\r
+ * \return Interrupt number that is currently executing.\r
+ */\r
+static inline enum system_interrupt_vector system_interrupt_get_active(void)\r
+{\r
+ uint32_t IPSR = __get_IPSR();\r
+\r
+ return (enum system_interrupt_vector)(IPSR & _SYSTEM_INTERRUPT_IPSR_MASK);\r
+}\r
+\r
+bool system_interrupt_is_pending(\r
+ const enum system_interrupt_vector vector);\r
+\r
+enum status_code system_interrupt_set_pending(\r
+ const enum system_interrupt_vector vector);\r
+\r
+enum status_code system_interrupt_clear_pending(\r
+ const enum system_interrupt_vector vector);\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \name Interrupt Priority Management\r
+ * @{\r
+ */\r
+\r
+enum status_code system_interrupt_set_priority(\r
+ const enum system_interrupt_vector vector,\r
+ const enum system_interrupt_priority_level priority_level);\r
+\r
+enum system_interrupt_priority_level system_interrupt_get_priority(\r
+ const enum system_interrupt_vector vector);\r
+\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_extra_acronyms Acronyms\r
+ * The table below presents the acronyms used in this module:\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Acronym</th>\r
+ * <th>Description</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>ISR</td>\r
+ * <td>Interrupt Service Routine</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_extra_dependencies Dependencies\r
+ * This driver has the following dependencies:\r
+ *\r
+ * - None\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_extra_errata Errata\r
+ * There are no errata related to this driver.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_interrupt_extra_history Module History\r
+ * An overview of the module history is presented in the table below, with\r
+ * details on the enhancements and fixes made to the module since its first\r
+ * release. The current version of this corresponds to the newest version in\r
+ * the table.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Changelog</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Initial Release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver\r
+ *\r
+ * This is a list of the available Quick Start guides (QSGs) and example\r
+ * applications for \ref asfdoc_samd20_system_interrupt_group. QSGs are simple examples with\r
+ * step-by-step instructions to configure and use this driver in a selection of\r
+ * use cases. Note that QSGs can be compiled as a standalone application or be\r
+ * added to the user application.\r
+ *\r
+ * - \subpage asfdoc_samd20_system_interrupt_critsec_use_case\r
+ * - \subpage asfdoc_samd20_system_interrupt_enablemodint_use_case\r
+ *\r
+ * \page asfdoc_samd20_system_interrupt_document_revision_history Document Revision History\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Doc. Rev.</td>\r
+ * <th>Date</td>\r
+ * <th>Comments</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>B</td>\r
+ * <td>06/2013</td>\r
+ * <td>Corrected documentation typos.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>A</td>\r
+ * <td>06/2013</td>\r
+ * <td>Initial release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Pin Multiplexer Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include <pinmux.h>\r
+\r
+/**\r
+ * \internal\r
+ * Writes out a given configuration of a Port pin configuration to the\r
+ * hardware module.\r
+ *\r
+ * \note If the pin direction is set as an output, the pull-up/pull-down input\r
+ * configuration setting is ignored.\r
+ *\r
+ * \param[in] port Base of the PORT module to configure.\r
+ * \param[in] pin_mask Mask of the port pin to configure.\r
+ * \param[in] config Configuration settings for the pin.\r
+ */\r
+static void _system_pinmux_config(\r
+ PortGroup *const port,\r
+ const uint32_t pin_mask,\r
+ const struct system_pinmux_config *const config)\r
+{\r
+ Assert(port);\r
+ Assert(config);\r
+\r
+ /* Track the configuration bits into a temporary variable before writing */\r
+ uint32_t pin_cfg = 0;\r
+\r
+ /* Enable the pin peripheral mux flag if non-GPIO selected (pin mux will\r
+ * be written later) and store the new mux mask */\r
+ if (config->mux_position != SYSTEM_PINMUX_GPIO) {\r
+ pin_cfg |= PORT_WRCONFIG_PMUXEN;\r
+ pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);\r
+ }\r
+\r
+ /* Check if the user has requested that the input buffer be enabled */\r
+ if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||\r
+ (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {\r
+ /* Enable input buffer flag */\r
+ pin_cfg |= PORT_WRCONFIG_INEN;\r
+\r
+ /* Enable pull-up/pull-down control flag if requested */\r
+ if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {\r
+ pin_cfg |= PORT_WRCONFIG_PULLEN;\r
+ }\r
+\r
+ /* Clear the port DIR bits to disable the output buffer */\r
+ port->DIRCLR.reg = pin_mask;\r
+ }\r
+\r
+ /* Check if the user has requested that the output buffer be enabled */\r
+ if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||\r
+ (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {\r
+ /* Cannot use a pullup if the output driver is enabled,\r
+ * if requested the input buffer can only sample the current\r
+ * output state */\r
+ pin_cfg &= ~PORT_WRCONFIG_PULLEN;\r
+\r
+ /* Set the port DIR bits to enable the output buffer */\r
+ port->DIRSET.reg = pin_mask;\r
+ }\r
+\r
+ /* The Write Configuration register (WRCONFIG) requires the\r
+ * pins to to grouped into two 16-bit half-words - split them out here */\r
+ uint32_t lower_pin_mask = (pin_mask & 0xFFFF);\r
+ uint32_t upper_pin_mask = (pin_mask >> 16);\r
+\r
+ /* Configure the lower 16-bits of the port to the desired configuration,\r
+ * including the pin peripheral multiplexer just in case it is enabled */\r
+ port->WRCONFIG.reg\r
+ = (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |\r
+ pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;\r
+\r
+ /* Configure the upper 16-bits of the port to the desired configuration,\r
+ * including the pin peripheral multiplexer just in case it is enabled */\r
+ port->WRCONFIG.reg\r
+ = (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |\r
+ pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |\r
+ PORT_WRCONFIG_HWSEL;\r
+\r
+ /* Set the pull-up state once the port pins are configured if one was\r
+ * requested and it does not violate the valid set of port\r
+ * configurations */\r
+ if (pin_cfg & PORT_WRCONFIG_PULLEN) {\r
+ /* Set the OUT register bits to enable the pullup if requested,\r
+ * clear to enable pull-down */\r
+ if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {\r
+ port->OUTSET.reg = pin_mask;\r
+ } else {\r
+ port->OUTCLR.reg = pin_mask;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Writes a Port pin configuration to the hardware module.\r
+ *\r
+ * Writes out a given configuration of a Port pin configuration to the hardware\r
+ * module.\r
+ *\r
+ * \note If the pin direction is set as an output, the pull-up/pull-down input\r
+ * configuration setting is ignored.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to configure.\r
+ * \param[in] config Configuration settings for the pin.\r
+ */\r
+void system_pinmux_pin_set_config(\r
+ const uint8_t gpio_pin,\r
+ const struct system_pinmux_config *const config)\r
+{\r
+ PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));\r
+\r
+ _system_pinmux_config(port, pin_mask, config);\r
+}\r
+\r
+/**\r
+ * \brief Writes a Port pin group configuration to the hardware module.\r
+ *\r
+ * Writes out a given configuration of a Port pin group configuration to the\r
+ * hardware module.\r
+ *\r
+ * \note If the pin direction is set as an output, the pull-up/pull-down input\r
+ * configuration setting is ignored.\r
+ *\r
+ * \param[in] port Base of the PORT module to configure.\r
+ * \param[in] mask Mask of the port pin(s) to configure.\r
+ * \param[in] config Configuration settings for the pin.\r
+ */\r
+void system_pinmux_group_set_config(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const struct system_pinmux_config *const config)\r
+{\r
+ Assert(port);\r
+\r
+ for (int i = 0; i < 32; i++) {\r
+ if (mask & (1UL << i)) {\r
+ _system_pinmux_config(port, (1UL << i), config);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures the input sampling mode for a group of pins.\r
+ *\r
+ * Configures the input sampling mode for a group of pins, to\r
+ * control when the physical I/O pin value is sampled and\r
+ * stored inside the microcontroller.\r
+ *\r
+ * \param[in] port Base of the PORT module to configure.\r
+ * \param[in] mask Mask of the port pin(s) to configure.\r
+ * \param[in] mode New pin sampling mode to configure.\r
+ */\r
+void system_pinmux_group_set_input_sample_mode(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const enum system_pinmux_pin_sample mode)\r
+{\r
+ Assert(port);\r
+\r
+ for (int i = 0; i < 32; i++) {\r
+ if (mask & (1UL << i)) {\r
+ uint32_t sample_quad_mask = (1UL << (i / 4));\r
+\r
+ if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {\r
+ port->CTRL.reg |= sample_quad_mask;\r
+ }\r
+ else {\r
+ port->CTRL.reg &= ~sample_quad_mask;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures the output driver strength mode for a group of pins.\r
+ *\r
+ * Configures the output drive strength for a group of pins, to\r
+ * control the amount of current the pad is able to sink/source.\r
+ *\r
+ * \param[in] port Base of the PORT module to configure.\r
+ * \param[in] mask Mask of the port pin(s) to configure.\r
+ * \param[in] mode New output driver strength mode to configure.\r
+ */\r
+void system_pinmux_group_set_output_strength(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const enum system_pinmux_pin_strength mode)\r
+{\r
+ Assert(port);\r
+\r
+ for (int i = 0; i < 32; i++) {\r
+ if (mask & (1UL << i)) {\r
+ if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {\r
+ port->PINCFG[i].reg |= PORT_PINCFG_DRVSTR;\r
+ }\r
+ else {\r
+ port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures the output slew rate mode for a group of pins.\r
+ *\r
+ * Configures the output slew rate mode for a group of pins, to\r
+ * control the speed at which the physical output pin can react to\r
+ * logical changes of the I/O pin value.\r
+ *\r
+ * \param[in] port Base of the PORT module to configure.\r
+ * \param[in] mask Mask of the port pin(s) to configure.\r
+ * \param[in] mode New pin slew rate mode to configure.\r
+ */\r
+void system_pinmux_group_set_output_slew_rate(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const enum system_pinmux_pin_slew_rate mode)\r
+{\r
+ Assert(port);\r
+\r
+ for (int i = 0; i < 32; i++) {\r
+ if (mask & (1UL << i)) {\r
+ if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {\r
+ port->PINCFG[i].reg |= PORT_PINCFG_SLEWLIM;\r
+ }\r
+ else {\r
+ port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures the output driver mode for a group of pins.\r
+ *\r
+ * Configures the output driver mode for a group of pins, to\r
+ * control the pad behavior.\r
+ *\r
+ * \param[in] port Base of the PORT module to configure.\r
+ * \param[in] mask Mask of the port pin(s) to configure.\r
+ * \param[in] mode New pad output driver mode to configure.\r
+ */\r
+void system_pinmux_group_set_output_drive(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const enum system_pinmux_pin_drive mode)\r
+{\r
+ Assert(port);\r
+\r
+ for (int i = 0; i < 32; i++) {\r
+ if (mask & (1UL << i)) {\r
+ if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {\r
+ port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;\r
+ }\r
+ else {\r
+ port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;\r
+ }\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Pin Multiplexer Driver\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef PINMUX_H_INCLUDED\r
+#define PINMUX_H_INCLUDED\r
+\r
+/**\r
+ * \defgroup asfdoc_samd20_system_pinmux_group SAM D20 System Pin Multiplexer Driver (SYSTEM PINMUX)\r
+ *\r
+ * This driver for SAM D20 devices provides an interface for the configuration\r
+ * and management of the device's physical I/O Pins, to alter the direction and\r
+ * input/drive characteristics as well as to configure the pin peripheral\r
+ * multiplexer selection.\r
+ *\r
+ * The following peripherals are used by this module:\r
+ *\r
+ * - PORT (Port I/O Management)\r
+ *\r
+ * Physically, the modules are interconnected within the device as shown in the\r
+ * following diagram:\r
+ *\r
+ * The outline of this documentation is as follows:\r
+ * - \ref asfdoc_samd20_system_pinmux_prerequisites\r
+ * - \ref asfdoc_samd20_system_pinmux_module_overview\r
+ * - \ref asfdoc_samd20_system_pinmux_special_considerations\r
+ * - \ref asfdoc_samd20_system_pinmux_extra_info\r
+ * - \ref asfdoc_samd20_system_pinmux_examples\r
+ * - \ref asfdoc_samd20_system_pinmux_api_overview\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_prerequisites Prerequisites\r
+ *\r
+ * There are no prerequisites for this module.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_module_overview Module Overview\r
+ *\r
+ * The SAM D20 devices contain a number of General Purpose I/O pins, used to\r
+ * interface the user application logic and internal hardware peripherals to\r
+ * an external system. The Pin Multiplexer (PINMUX) driver provides a method\r
+ * of configuring the individual pin peripheral multiplexers to select\r
+ * alternate pin functions,\r
+ *\r
+ * \subsection asfdoc_samd20_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins\r
+ * SAM D20 devices use two naming conventions for the I/O pins in the device; one\r
+ * physical, and one logical. Each physical pin on a device package is assigned\r
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a\r
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the\r
+ * former is used to map physical pins to their physical internal device module\r
+ * counterparts, for simplicity the design of this driver uses the logical GPIO\r
+ * numbers instead.\r
+ *\r
+ * \subsection asfdoc_samd20_system_pinmux_peripheral_muxing Peripheral Multiplexing\r
+ * SAM D20 devices contain a peripheral MUX, which is individually controllable\r
+ * for each I/O pin of the device. The peripheral MUX allows you to select the\r
+ * function of a physical package pin - whether it will be controlled as a user\r
+ * controllable GPIO pin, or whether it will be connected internally to one of\r
+ * several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is\r
+ * configured in GPIO mode, other peripherals connected to the same pin will be\r
+ * disabled.\r
+ *\r
+ * \subsection asfdoc_samd20_system_pinmux_pad_characteristics Special Pad Characteristics\r
+ * There are several special modes that can be selected on one or more I/O pins\r
+ * of the device, which alter the input and output characteristics of the pad:\r
+ *\r
+ * \subsubsection asfdoc_samd20_system_pinmux_drive_strength Drive Strength\r
+ * The Drive Strength configures the strength of the output driver on the\r
+ * pad. Normally, there is a fixed current limit that each I/O pin can safely\r
+ * drive, however some I/O pads offer a higher drive mode which increases this\r
+ * limit for that I/O pin at the expense of an increased power consumption.\r
+ *\r
+ * \subsubsection asfdoc_samd20_system_pinmux_slew_rate Slew Rate\r
+ * The Slew Rate configures the slew rate of the output driver, limiting the\r
+ * rate at which the pad output voltage can change with time.\r
+ *\r
+ * \subsubsection asfdoc_samd20_system_pinmux_input_sample_mode Input Sample Mode\r
+ * The Input Sample Mode configures the input sampler buffer of the pad. By\r
+ * default, the input buffer is only sampled "on-demand", i.e. when the user\r
+ * application attempts to read from the input buffer. This mode is the most\r
+ * power efficient, but increases the latency of the input sample by two clock\r
+ * cycles of the port clock. To reduce latency, the input sampler can instead\r
+ * be configured to always sample the input buffer on each port clock cycle, at\r
+ * the expense of an increased power consumption.\r
+ *\r
+ * \subsection asfdoc_samd20_system_pinmux_module_overview_physical Physical Connection\r
+ *\r
+ * \ref asfdoc_samd20_system_pinmux_intconnections "The diagram below" shows\r
+ * how this module is interconnected within the device:\r
+ *\r
+ * \anchor asfdoc_samd20_system_pinmux_intconnections\r
+ * \dot\r
+ * digraph overview {\r
+ * node [label="Port Pad" shape=square] pad;\r
+ *\r
+ * subgraph driver {\r
+ * node [label="Peripheral Mux" shape=trapezium] pinmux;\r
+ * node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;\r
+ * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;\r
+ * }\r
+ *\r
+ * pinmux -> gpio;\r
+ * pad -> pinmux;\r
+ * pinmux -> peripherals;\r
+ * }\r
+ * \enddot\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_special_considerations Special Considerations\r
+ *\r
+ * The SAM D20 port pin input sampling mode is set in groups of four physical\r
+ * pins; setting the sampling mode of any pin in a sub-group of four I/O pins\r
+ * will configure the sampling mode of the entire sub-group.\r
+ *\r
+ * High Drive Strength output driver mode is not available on all device pins -\r
+ * refer to your device specific datasheet.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_extra_info Extra Information\r
+ *\r
+ * For extra information see \ref asfdoc_samd20_system_pinmux_extra. This includes:\r
+ * - \ref asfdoc_samd20_system_pinmux_extra_acronyms\r
+ * - \ref asfdoc_samd20_system_pinmux_extra_dependencies\r
+ * - \ref asfdoc_samd20_system_pinmux_extra_errata\r
+ * - \ref asfdoc_samd20_system_pinmux_extra_history\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_examples Examples\r
+ *\r
+ * For a list of examples related to this driver, see\r
+ * \ref asfdoc_samd20_system_pinmux_exqsg.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_api_overview API Overview\r
+ * @{\r
+ */\r
+\r
+#include <compiler.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** Peripheral multiplexer index to select GPIO mode for a pin. */\r
+#define SYSTEM_PINMUX_GPIO (1 << 7)\r
+\r
+/**\r
+ * \brief Port pin direction configuration enum.\r
+ *\r
+ * Enum for the possible pin direction settings of the port pin configuration\r
+ * structure, to indicate the direction the pin should use.\r
+ */\r
+enum system_pinmux_pin_dir {\r
+ /** The pin's input buffer should be enabled, so that the pin state can\r
+ * be read. */\r
+ SYSTEM_PINMUX_PIN_DIR_INPUT,\r
+ /** The pin's output buffer should be enabled, so that the pin state can\r
+ * be set (but not read back). */\r
+ SYSTEM_PINMUX_PIN_DIR_OUTPUT,\r
+ /** The pin's output and input buffers should both be enabled, so that the\r
+ * pin state can be set and read back. */\r
+ SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,\r
+};\r
+\r
+/**\r
+ * \brief Port pin input pull configuration enum.\r
+ *\r
+ * Enum for the possible pin pull settings of the port pin configuration\r
+ * structure, to indicate the type of logic level pull the pin should use.\r
+ */\r
+enum system_pinmux_pin_pull {\r
+ /** No logical pull should be applied to the pin. */\r
+ SYSTEM_PINMUX_PIN_PULL_NONE,\r
+ /** Pin should be pulled up when idle. */\r
+ SYSTEM_PINMUX_PIN_PULL_UP,\r
+ /** Pin should be pulled down when idle. */\r
+ SYSTEM_PINMUX_PIN_PULL_DOWN,\r
+};\r
+\r
+/**\r
+ * \brief Port pin digital input sampling mode enum.\r
+ *\r
+ * Enum for the possible input sampling modes for the port pin configuration\r
+ * structure, to indicate the type of sampling a port pin should use.\r
+ */\r
+enum system_pinmux_pin_sample {\r
+ /** Pin input buffer should continuously sample the pin state. */\r
+ SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,\r
+ /** Pin input buffer should be enabled when the IN register is read. */\r
+ SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,\r
+};\r
+\r
+/**\r
+ * \brief Port pin drive output strength enum.\r
+ *\r
+ * Enum for the possible output drive strengths for the port pin\r
+ * configuration structure, to indicate the driver strength the pin should\r
+ * use.\r
+ */\r
+enum system_pinmux_pin_strength {\r
+ /** Normal output driver strength. */\r
+ SYSTEM_PINMUX_PIN_STRENGTH_NORMAL,\r
+ /** High current output driver strength. */\r
+ SYSTEM_PINMUX_PIN_STRENGTH_HIGH,\r
+};\r
+\r
+/**\r
+ * \brief Port pin output slew rate enum.\r
+ *\r
+ * Enum for the possible output drive slew rates for the port pin\r
+ * configuration structure, to indicate the driver slew rate the pin should\r
+ * use.\r
+ */\r
+enum system_pinmux_pin_slew_rate {\r
+ /** Normal pin output slew rate. */\r
+ SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL,\r
+ /** Enable slew rate limiter on the pin. */\r
+ SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED,\r
+};\r
+\r
+/**\r
+ * \brief Port pin output drive mode enum.\r
+ *\r
+ * Enum for the possible output drive modes for the port pin configuration\r
+ * structure, to indicate the output mode the pin should use.\r
+ */\r
+enum system_pinmux_pin_drive {\r
+ /** Use totem pole output drive mode. */\r
+ SYSTEM_PINMUX_PIN_DRIVE_TOTEM,\r
+ /** Use open drain output drive mode. */\r
+ SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN,\r
+};\r
+\r
+/**\r
+ * \brief Port pin configuration structure.\r
+ *\r
+ * Configuration structure for a port pin instance. This structure should be\r
+ * structure should be initialized by the\r
+ * \ref system_pinmux_get_config_defaults() function before being modified by\r
+ * the user application.\r
+ */\r
+struct system_pinmux_config {\r
+ /** MUX index of the peripheral that should control the pin, if peripheral\r
+ * control is desired. For GPIO use, this should be set to\r
+ * \ref SYSTEM_PINMUX_GPIO. */\r
+ uint8_t mux_position;\r
+\r
+ /** Port buffer input/output direction. */\r
+ enum system_pinmux_pin_dir direction;\r
+\r
+ /** Logic level pull of the input buffer. */\r
+ enum system_pinmux_pin_pull input_pull;\r
+};\r
+\r
+/** \name Configuration and initialization\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Initializes a Port pin configuration structure to defaults.\r
+ *\r
+ * Initializes a given Port pin configuration structure to a set of\r
+ * known default values. This function should be called on all new\r
+ * instances of these configuration structures before being modified by the\r
+ * user application.\r
+ *\r
+ * The default configuration is as follows:\r
+ * \li Non peripheral (i.e. GPIO) controlled\r
+ * \li Input mode with internal pull-up enabled\r
+ *\r
+ * \param[out] config Configuration structure to initialize to default values\r
+ */\r
+static inline void system_pinmux_get_config_defaults(\r
+ struct system_pinmux_config *const config)\r
+{\r
+ /* Sanity check arguments */\r
+ Assert(config);\r
+\r
+ /* Default configuration values */\r
+ config->mux_position = SYSTEM_PINMUX_GPIO;\r
+ config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;\r
+ config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP;\r
+}\r
+\r
+void system_pinmux_pin_set_config(\r
+ const uint8_t gpio_pin,\r
+ const struct system_pinmux_config *const config);\r
+\r
+void system_pinmux_group_set_config(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const struct system_pinmux_config *const config);\r
+\r
+/** @} */\r
+\r
+/** \name Special mode configuration (physical group orientated)\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.\r
+ *\r
+ * Retrieves the PORT module group instance associated with a given logical\r
+ * GPIO pin number.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to convert.\r
+ *\r
+ * \return Base address of the associated PORT module.\r
+ */\r
+static inline PortGroup* system_pinmux_get_group_from_gpio_pin(\r
+ const uint8_t gpio_pin)\r
+{\r
+ uint8_t port_index = (gpio_pin / 128);\r
+ uint8_t group_index = (gpio_pin / 32);\r
+\r
+ /* Array of available ports. */\r
+ Port *const ports[PORT_INST_NUM] = PORT_INSTS;\r
+\r
+ if (port_index < PORT_INST_NUM) {\r
+ return &(ports[port_index]->Group[group_index]);\r
+ } else {\r
+ Assert(false);\r
+ return NULL;\r
+ }\r
+}\r
+\r
+void system_pinmux_group_set_input_sample_mode(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const enum system_pinmux_pin_sample mode);\r
+\r
+void system_pinmux_group_set_output_strength(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const enum system_pinmux_pin_strength mode);\r
+\r
+void system_pinmux_group_set_output_slew_rate(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const enum system_pinmux_pin_slew_rate mode);\r
+\r
+void system_pinmux_group_set_output_drive(\r
+ PortGroup *const port,\r
+ const uint32_t mask,\r
+ const enum system_pinmux_pin_drive mode);\r
+\r
+/** @} */\r
+\r
+/** \name Special mode configuration (logical pin orientated)\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieves the currently selected MUX position of a logical pin.\r
+ *\r
+ * Retrieves the selected MUX peripheral on a given logical GPIO pin.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to configure.\r
+ *\r
+ * \return Currently selected peripheral index on the specified pin.\r
+ */\r
+static inline uint8_t system_pinmux_pin_get_mux_position(\r
+ const uint8_t gpio_pin)\r
+{\r
+ PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_index = (gpio_pin % 32);\r
+\r
+ if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {\r
+ return SYSTEM_PINMUX_GPIO;\r
+ }\r
+\r
+ uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;\r
+\r
+ if (pin_index & 1) {\r
+ return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;\r
+ }\r
+ else {\r
+ return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures the input sampling mode for a GPIO pin.\r
+ *\r
+ * Configures the input sampling mode for a GPIO input, to\r
+ * control when the physical I/O pin value is sampled and\r
+ * stored inside the microcontroller.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to configure.\r
+ * \param[in] mode New pin sampling mode to configure.\r
+ */\r
+static inline void system_pinmux_pin_set_input_sample_mode(\r
+ const uint8_t gpio_pin,\r
+ const enum system_pinmux_pin_sample mode)\r
+{\r
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t sample_quad_mask = (1UL << ((gpio_pin % 32) / 4));\r
+\r
+ if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {\r
+ port->CTRL.reg |= sample_quad_mask;\r
+ }\r
+ else {\r
+ port->CTRL.reg &= ~sample_quad_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures the output driver strength mode for a GPIO pin.\r
+ *\r
+ * Configures the output drive strength for a GPIO output, to\r
+ * control the amount of current the pad is able to sink/source.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to configure.\r
+ * \param[in] mode New output driver strength mode to configure.\r
+ */\r
+static inline void system_pinmux_pin_set_output_strength(\r
+ const uint8_t gpio_pin,\r
+ const enum system_pinmux_pin_strength mode)\r
+{\r
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_index = (gpio_pin % 32);\r
+\r
+ if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {\r
+ port->PINCFG[pin_index].reg |= PORT_PINCFG_DRVSTR;\r
+ }\r
+ else {\r
+ port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures the output slew rate mode for a GPIO pin.\r
+ *\r
+ * Configures the output slew rate mode for a GPIO output, to\r
+ * control the speed at which the physical output pin can react to\r
+ * logical changes of the I/O pin value.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to configure.\r
+ * \param[in] mode New pin slew rate mode to configure.\r
+ */\r
+static inline void system_pinmux_pin_set_output_slew_rate(\r
+ const uint8_t gpio_pin,\r
+ const enum system_pinmux_pin_slew_rate mode)\r
+{\r
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_index = (gpio_pin % 32);\r
+\r
+ if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {\r
+ port->PINCFG[pin_index].reg |= PORT_PINCFG_SLEWLIM;\r
+ }\r
+ else {\r
+ port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures the output driver mode for a GPIO pin.\r
+ *\r
+ * Configures the output driver mode for a GPIO output, to\r
+ * control the pad behavior.\r
+ *\r
+ * \param[in] gpio_pin Index of the GPIO pin to configure.\r
+ * \param[in] mode New pad output driver mode to configure.\r
+ */\r
+static inline void system_pinmux_pin_set_output_drive(\r
+ const uint8_t gpio_pin,\r
+ const enum system_pinmux_pin_drive mode)\r
+{\r
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);\r
+ uint32_t pin_index = (gpio_pin % 32);\r
+\r
+ if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {\r
+ port->PINCFG[pin_index].reg |= PORT_PINCFG_ODRAIN;\r
+ }\r
+ else {\r
+ port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN;\r
+ }\r
+}\r
+\r
+/** @} */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_extra_acronyms Acronyms\r
+ * The table below presents the acronyms used in this module:\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Acronym</th>\r
+ * <th>Description</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>GPIO</td>\r
+ * <td>General Purpose Input/Output</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>MUX</td>\r
+ * <td>Multiplexer</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_extra_dependencies Dependencies\r
+ * This driver has the following dependencies:\r
+ *\r
+ * - None\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_extra_errata Errata\r
+ * There are no errata related to this driver.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_extra_history Module History\r
+ * An overview of the module history is presented in the table below, with\r
+ * details on the enhancements and fixes made to the module since its first\r
+ * release. The current version of this corresponds to the newest version in\r
+ * the table.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Changelog</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Added missing NULL pointer asserts to the PORT driver functions.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Initial Release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver\r
+ *\r
+ * This is a list of the available Quick Start guides (QSGs) and example\r
+ * applications for \ref asfdoc_samd20_system_pinmux_group. QSGs are simple\r
+ * examples with step-by-step instructions to configure and use this driver in a\r
+ * selection of use cases. Note that QSGs can be compiled as a standalone\r
+ * application or be added to the user application.\r
+ *\r
+ * - \subpage asfdoc_samd20_system_pinmux_basic_use_case\r
+ *\r
+ * \page asfdoc_samd20_system_pinmux_document_revision_history Document Revision History\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Doc. Rev.</td>\r
+ * <th>Date</td>\r
+ * <th>Comments</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>B</td>\r
+ * <td>06/2013</td>\r
+ * <td>Corrected documentation typos.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>A</td>\r
+ * <td>06/2013</td>\r
+ * <td>Initial release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 PINMUX Driver Quick Start\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic\r
+ *\r
+ * In this use case, the PINMUX module is configured for:\r
+ * \li One pin in input mode, with pull-up enabled, connected to the GPIO\r
+ * module\r
+ * \li Sampling mode of the pin changed to sample on demand\r
+ *\r
+ * This use case sets up the PINMUX to configure a physical I/O pin set as\r
+ * an input with pull-up. and changes the sampling mode of the pin to reduce\r
+ * power by only sampling the physical pin state when the user application\r
+ * attempts to read it.\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_basic_use_case_setup Setup\r
+ *\r
+ * \subsection asfdoc_samd20_system_pinmux_basic_use_case_setup_prereq Prerequisites\r
+ * There are no special setup requirements for this use-case.\r
+ *\r
+ * \section asfdoc_samd20_system_pinmux_basic_use_case_use_main Use Case\r
+ *\r
+ * \subsection asfdoc_samd20_system_pinmux_basic_use_case_code Code\r
+ * Copy-paste the following code to your user application:\r
+ * \snippet qs_pinmux_basic.c main\r
+ *\r
+ * \subsection asfdoc_samd20_system_pinmux_basic_use_case_flow Workflow\r
+ * -# Create a PINMUX module pin configuration struct, which can be filled out\r
+ * to adjust the configuration of a single port pin.\r
+ * \snippet qs_pinmux_basic.c pinmux_config\r
+ * -# Initialize the pin configuration struct with the module's default values.\r
+ * \note This should always be performed before using the configuration\r
+ * struct to ensure that all values are initialized to known default\r
+ * settings.\r
+ *\r
+ * \snippet qs_pinmux_basic.c pinmux_config_defaults\r
+ * -# Adjust the configuration struct to request an input pin with pullup\r
+ * connected to the GPIO peripheral.\r
+ * \snippet qs_pinmux_basic.c pinmux_update_config_values\r
+ * -# Configure GPIO10 with the initialized pin configuration struct, to enable\r
+ * the input sampler on the pin.\r
+ * \snippet qs_pinmux_basic.c pinmux_set_config\r
+ * -# Adjust the configuration of the pin to enable on-demand sampling mode.\r
+ * \snippet qs_pinmux_basic.c pinmux_change_input_sampling\r
+ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 System related functionality\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <system.h>\r
+\r
+/**\r
+ * \internal\r
+ * Dummy initialization function, used as a weak alias target for the various\r
+ * init functions called by \ref system_init().\r
+ */\r
+void _system_dummy_init(void);\r
+void _system_dummy_init(void)\r
+{\r
+ return;\r
+}\r
+\r
+#if !defined(__DOXYGEN__)\r
+# if defined(__GNUC__)\r
+void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));\r
+void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));\r
+# elif defined(__ICCARM__)\r
+void system_clock_init(void);\r
+void system_board_init(void);\r
+# pragma weak system_clock_init=_system_dummy_init\r
+# pragma weak system_board_init=_system_dummy_init\r
+# endif\r
+#endif\r
+\r
+\r
+/**\r
+ * Handler for the CPU Hard Fault interrupt, fired if an illegal access was\r
+ * attempted to a memory address.\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ while (1) {\r
+ /* Infinite loop if CPU exception is detected */\r
+ Assert(false);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Initialize system\r
+ *\r
+ * This function will call the various initialization functions within the\r
+ * system namespace. If a given optional system module is not available, the\r
+ * associated call will effectively be a NOP (No Operation).\r
+ *\r
+ * Currently the following initialization functions are supported:\r
+ * - System clock initialization (via the SYSTEM CLOCK sub-module)\r
+ * - Board hardware initialization (via the Board module)\r
+ */\r
+void system_init(void)\r
+{\r
+ /* Configure GCLK and clock sources according to conf_clocks.h */\r
+ system_clock_init();\r
+\r
+ /* Initialize board hardware */\r
+ system_board_init();\r
+}\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 System related functionality\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SYSTEM_H_INCLUDED\r
+#define SYSTEM_H_INCLUDED\r
+\r
+#include <compiler.h>\r
+#include <clock.h>\r
+#include <gclk.h>\r
+#include <pinmux.h>\r
+\r
+/**\r
+ * \defgroup asfdoc_samd20_system_group SAM D20 System Driver (SYSTEM)\r
+ *\r
+ * This driver for SAM D20 devices provides an interface for the configuration\r
+ * and management of the device's system relation functionality, necessary for\r
+ * the basic device operation. This is not limited to a single peripheral, but\r
+ * extends across multiple hardware peripherals,\r
+ *\r
+ * The following peripherals are used by this module:\r
+ *\r
+ * - SYSCTRL (System Control)\r
+ * - PM (Power Manager)\r
+ *\r
+ * The outline of this documentation is as follows:\r
+ * - \ref asfdoc_samd20_system_prerequisites\r
+ * - \ref asfdoc_samd20_system_module_overview\r
+ * - \ref asfdoc_samd20_system_special_considerations\r
+ * - \ref asfdoc_samd20_system_extra_info\r
+ * - \ref asfdoc_samd20_system_examples\r
+ * - \ref asfdoc_samd20_system_api_overview\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_prerequisites Prerequisites\r
+ *\r
+ * There are no prerequisites for this module.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_module_overview Module Overview\r
+ *\r
+ * The System driver provides a collection of interfaces between the user\r
+ * application logic, and the core device functionality (such as clocks, reset\r
+ * cause determination, etc.) that is required for all applications. It contains\r
+ * a number of sub-modules that control one specific aspect of the device:\r
+ *\r
+ * - System Core (this module)\r
+ * - \ref asfdoc_samd20_system_clock_group "System Clock Control" (sub-module)\r
+ * - \ref asfdoc_samd20_system_interrupt_group "System Interrupt Control" (sub-module)\r
+ * - \ref asfdoc_samd20_system_pinmux_group "System Pin Multiplexer Control" (sub-module)\r
+ *\r
+ *\r
+ * \subsection asfdoc_samd20_system_module_overview_vref Voltage References\r
+ * The various analog modules within the SAM D20 devices (such as AC, ADC and\r
+ * DAC) require a voltage reference to be configured to act as a reference point\r
+ * for comparisons and conversions.\r
+ *\r
+ * The SAM D20 devices contain multiple references, including an internal\r
+ * temperature sensor, and a fixed band-gap voltage source. When enabled, the\r
+ * associated voltage reference can be selected within the desired peripheral\r
+ * where applicable.\r
+ *\r
+ * \subsection asfdoc_samd20_system_module_overview_reset_cause System Reset Cause\r
+ * In some application there may be a need to execute a different program\r
+ * flow based on how the device was reset. For example, if the cause of reset\r
+ * was the Watchdog timer (WDT), this might indicate an error in the application\r
+ * and a form of error handling or error logging might be needed.\r
+ *\r
+ * For this reason, an API is provided to retrieve the cause of the last system\r
+ * reset, so that appropriate action can be taken.\r
+ *\r
+ * \subsection asfdoc_samd20_system_module_overview_sleep_mode Sleep Modes\r
+ * The SAM D20 devices have several sleep modes, where the sleep mode controls\r
+ * which clock systems on the device will remain enabled or disabled when the\r
+ * device enters a low power sleep mode.\r
+ * \ref asfdoc_samd20_system_module_sleep_mode_table "The table below" lists the\r
+ * clock settings of the different sleep modes.\r
+ *\r
+ * \anchor asfdoc_samd20_system_module_sleep_mode_table\r
+ * <table>\r
+ * <caption>SAM D20 Device Sleep Modes</caption>\r
+ * <tr>\r
+ * <th>Sleep mode</th>\r
+ * <th>CPU clock</th>\r
+ * <th>AHB clock</th>\r
+ * <th>APB clocks</th>\r
+ * <th>Clock sources</th>\r
+ * <th>System clock</th>\r
+ * <th>32KHz</th>\r
+ * <th>Reg mode</th>\r
+ * <th>RAM mode</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>IDLE 0</td>\r
+ * <td>Stop</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Normal</td>\r
+ * <td>Normal</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>IDLE 1</td>\r
+ * <td>Stop</td>\r
+ * <td>Stop</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Normal</td>\r
+ * <td>Normal</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>IDLE 2</td>\r
+ * <td>Stop</td>\r
+ * <td>Stop</td>\r
+ * <td>Stop</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Run</td>\r
+ * <td>Normal</td>\r
+ * <td>Normal</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>STANDBY</td>\r
+ * <td>Stop</td>\r
+ * <td>Stop</td>\r
+ * <td>Stop</td>\r
+ * <td>Stop</td>\r
+ * <td>Stop</td>\r
+ * <td>Stop</td>\r
+ * <td>Low Power</td>\r
+ * <td>Source/Drain biasing</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * To enter device sleep, one of the available sleep modes must be set, and the\r
+ * function to enter sleep called. The device will automatically wake up in\r
+ * response to an interrupt being generated or other device event.\r
+ *\r
+ * Some peripheral clocks will remain enabled during sleep, depending on their\r
+ * configuration; if desired, modules can remain clocked during sleep to allow\r
+ * them to continue to operate while other parts of the system are powered down\r
+ * to save power.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_special_considerations Special Considerations\r
+ *\r
+ * Most of the functions in this driver have device specific restrictions and\r
+ * caveats; refer to your device datasheet.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_extra_info Extra Information\r
+ *\r
+ * For extra information see \ref asfdoc_samd20_system_extra. This includes:\r
+ * - \ref asfdoc_samd20_system_extra_acronyms\r
+ * - \ref asfdoc_samd20_system_extra_dependencies\r
+ * - \ref asfdoc_samd20_system_extra_errata\r
+ * - \ref asfdoc_samd20_system_extra_history\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_examples Examples\r
+ *\r
+ * For SYSTEM module related examples, please refer to the sub-modules listed in\r
+ * the \ref asfdoc_samd20_system_module_overview "system module overview".\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_api_overview API Overview\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Voltage references within the device.\r
+ *\r
+ * List of available voltage references (VREF) that may be used within the\r
+ * device.\r
+ */\r
+enum system_voltage_reference {\r
+ /** Temperature sensor voltage reference. */\r
+ SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,\r
+ /** Bandgap voltage reference. */\r
+ SYSTEM_VOLTAGE_REFERENCE_BANDGAP,\r
+};\r
+\r
+/**\r
+ * \brief Device sleep modes.\r
+ *\r
+ * List of available sleep modes in the device. A table of clocks available in\r
+ * different sleep modes can be found in \ref asfdoc_samd20_system_module_overview_sleep_mode.\r
+ */\r
+enum system_sleepmode {\r
+ /** IDLE 0 sleep mode. */\r
+ SYSTEM_SLEEPMODE_IDLE_0,\r
+ /** IDLE 1 sleep mode. */\r
+ SYSTEM_SLEEPMODE_IDLE_1,\r
+ /** IDLE 2 sleep mode. */\r
+ SYSTEM_SLEEPMODE_IDLE_2,\r
+ /** Standby sleep mode. */\r
+ SYSTEM_SLEEPMODE_STANDBY,\r
+};\r
+\r
+/**\r
+ * \brief Reset causes of the system.\r
+ *\r
+ * List of possible reset causes of the system.\r
+ */\r
+enum system_reset_cause {\r
+ /** The system was last reset by a software reset. */\r
+ SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST,\r
+ /** The system was last reset by the watchdog timer. */\r
+ SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT,\r
+ /** The system was last reset because the external reset line was pulled low. */\r
+ SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,\r
+ /** The system was last reset by the BOD33. */\r
+ SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33,\r
+ /** The system was last reset by the BOD12. */\r
+ SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12,\r
+ /** The system was last reset by the POR (Power on reset). */\r
+ SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR,\r
+};\r
+\r
+/**\r
+ * \name System identification\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Retrieve the device identification signature\r
+ *\r
+ * Retrieves the signature of the current device.\r
+ *\r
+ * \return Device ID signature as a 32-bit integer.\r
+ */\r
+static inline uint32_t system_get_device_id(void)\r
+{\r
+ return DSU->DID.reg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * \name Voltage references\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Enable the selected voltage reference\r
+ *\r
+ * Enables the selected voltage reference source, making the voltage reference\r
+ * available on a pin as well as an input source to the analog peripherals.\r
+ *\r
+ * \param[in] vref Voltage reference to enable\r
+ */\r
+static inline void system_voltage_reference_enable(\r
+ const enum system_voltage_reference vref)\r
+{\r
+ switch (vref) {\r
+ case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:\r
+ SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;\r
+ break;\r
+\r
+ case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:\r
+ SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable the selected voltage reference\r
+ *\r
+ * Disables the selected voltage reference source.\r
+ *\r
+ * \param[in] vref Voltage reference to disable\r
+ */\r
+static inline void system_voltage_reference_disable(\r
+ const enum system_voltage_reference vref)\r
+{\r
+ switch (vref) {\r
+ case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:\r
+ SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;\r
+ break;\r
+\r
+ case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:\r
+ SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * \name Device sleep\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Set the sleep mode of the device\r
+ *\r
+ * Sets the sleep mode of the device; the configured sleep mode will be entered\r
+ * upon the next call of the \ref system_sleep() function.\r
+ *\r
+ * For an overview of which systems are disabled in sleep for the different\r
+ * sleep modes, see \ref asfdoc_samd20_system_module_overview_sleep_mode.\r
+ *\r
+ * \param[in] sleep_mode Sleep mode to configure for the next sleep operation\r
+ *\r
+ * \retval STATUS_OK Operation completed successfully\r
+ * \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not\r
+ * available\r
+ */\r
+static inline enum status_code system_set_sleepmode(\r
+ const enum system_sleepmode sleep_mode)\r
+{\r
+ switch (sleep_mode) {\r
+ case SYSTEM_SLEEPMODE_IDLE_0:\r
+ case SYSTEM_SLEEPMODE_IDLE_1:\r
+ case SYSTEM_SLEEPMODE_IDLE_2:\r
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;\r
+ PM->SLEEP.reg = sleep_mode;\r
+ break;\r
+\r
+ case SYSTEM_SLEEPMODE_STANDBY:\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ break;\r
+\r
+ default:\r
+ return STATUS_ERR_INVALID_ARG;\r
+ }\r
+\r
+ return STATUS_OK;\r
+}\r
+\r
+/**\r
+ * \brief Put the system to sleep waiting for interrupt\r
+ *\r
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure\r
+ * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)\r
+ * instruction to place the device into the sleep mode specified by\r
+ * \ref system_set_sleepmode until woken by an interrupt.\r
+ */\r
+static inline void system_sleep(void)\r
+{\r
+ __DSB();\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \name Reset control\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Reset the MCU\r
+ *\r
+ * Resets the MCU and all associated peripherals and registers, except RTC, all 32kHz sources,\r
+ * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).\r
+ *\r
+ */\r
+static inline void system_reset(void)\r
+{\r
+ NVIC_SystemReset();\r
+}\r
+\r
+/**\r
+ * \brief Return the reset cause\r
+ *\r
+ * Retrieves the cause of the last system reset.\r
+ *\r
+ * \return An enum value indicating the cause of the last system reset.\r
+ */\r
+static inline enum system_reset_cause system_get_reset_cause(void)\r
+{\r
+ return (enum system_reset_cause)PM->RCAUSE.reg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * \name System initialization\r
+ * @{\r
+ */\r
+\r
+void system_init(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * \page asfdoc_samd20_system_extra Extra Information for SYSTEM Driver\r
+ *\r
+ * \section asfdoc_samd20_system_extra_acronyms Acronyms\r
+ * Below is a table listing the acronyms used in this module, along with their\r
+ * intended meanings.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Acronym</th>\r
+ * <th>Definition</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>PM</td>\r
+ * <td>Power Manager</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>SYSCTRL</td>\r
+ * <td>System control interface</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_extra_dependencies Dependencies\r
+ * This driver has the following dependencies:\r
+ *\r
+ * - None\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_extra_errata Errata\r
+ * There are no errata related to this driver.\r
+ *\r
+ *\r
+ * \section asfdoc_samd20_system_extra_history Module History\r
+ * An overview of the module history is presented in the table below, with\r
+ * details on the enhancements and fixes made to the module since its first\r
+ * release. The current version of this corresponds to the newest version in\r
+ * the table.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Changelog</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Added new \c system_get_device_id() function to retrieved the device\r
+ * ID.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Initial Release</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ * \page asfdoc_samd20_system_document_revision_history Document Revision History\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th>Doc. Rev.</td>\r
+ * <th>Date</td>\r
+ * <th>Comments</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>B</td>\r
+ * <td>06/2013</td>\r
+ * <td>Corrected documentation typos.</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>A</td>\r
+ * <td>06/2013</td>\r
+ * <td>Initial release</td>\r
+ * </tr>\r
+ * </table>\r
+ */\r
+\r
+#endif /* SYSTEM_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for AC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_AC_COMPONENT_\r
+#define _SAMD20_AC_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR AC */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_AC Analog Comparators */\r
+/*@{*/\r
+\r
+#define REV_AC 0x110\r
+\r
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run during Standby */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A Register */\r
+#define AC_CTRLA_RESETVALUE 0x00 /**< \brief (AC_CTRLA reset_value) Control A Register */\r
+\r
+#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */\r
+#define AC_CTRLA_SWRST (0x1u << AC_CTRLA_SWRST_Pos)\r
+#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */\r
+#define AC_CTRLA_ENABLE (0x1u << AC_CTRLA_ENABLE_Pos)\r
+#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run during Standby */\r
+#define AC_CTRLA_RUNSTDBY_Msk (0x1u << AC_CTRLA_RUNSTDBY_Pos)\r
+#define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))\r
+#define AC_CTRLA_MASK 0x07u /**< \brief (AC_CTRLA) MASK Register */\r
+\r
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */\r
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */\r
+ uint8_t START2:1; /*!< bit: 2 Comparator 2 Start Comparison */\r
+ uint8_t START3:1; /*!< bit: 3 Comparator 3 Start Comparison */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_CTRLB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B Register */\r
+#define AC_CTRLB_RESETVALUE 0x00 /**< \brief (AC_CTRLB reset_value) Control B Register */\r
+\r
+#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */\r
+#define AC_CTRLB_START0 (0x1u << AC_CTRLB_START0_Pos)\r
+#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */\r
+#define AC_CTRLB_START1 (0x1u << AC_CTRLB_START1_Pos)\r
+#define AC_CTRLB_START2_Pos 2 /**< \brief (AC_CTRLB) Comparator 2 Start Comparison */\r
+#define AC_CTRLB_START2 (0x1u << AC_CTRLB_START2_Pos)\r
+#define AC_CTRLB_START3_Pos 3 /**< \brief (AC_CTRLB) Comparator 3 Start Comparison */\r
+#define AC_CTRLB_START3 (0x1u << AC_CTRLB_START3_Pos)\r
+#define AC_CTRLB_MASK 0x0Fu /**< \brief (AC_CTRLB) MASK Register */\r
+\r
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */\r
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */\r
+ uint16_t COMPEO2:1; /*!< bit: 2 Comparator 2 Event Output Enable */\r
+ uint16_t COMPEO3:1; /*!< bit: 3 Comparator 3 Event Output Enable */\r
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */\r
+ uint16_t WINEO1:1; /*!< bit: 5 Window 1 Event Output Enable */\r
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */\r
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */\r
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */\r
+ uint16_t COMPEI2:1; /*!< bit: 10 Comparator 2 Event Input Enable */\r
+ uint16_t COMPEI3:1; /*!< bit: 11 Comparator 3 Event Input Enable */\r
+ uint16_t :4; /*!< bit: 12..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} AC_EVCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control Register */\r
+#define AC_EVCTRL_RESETVALUE 0x0000 /**< \brief (AC_EVCTRL reset_value) Event Control Register */\r
+\r
+#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */\r
+#define AC_EVCTRL_COMPEO0 (0x1u << AC_EVCTRL_COMPEO0_Pos)\r
+#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */\r
+#define AC_EVCTRL_COMPEO1 (0x1u << AC_EVCTRL_COMPEO1_Pos)\r
+#define AC_EVCTRL_COMPEO2_Pos 2 /**< \brief (AC_EVCTRL) Comparator 2 Event Output Enable */\r
+#define AC_EVCTRL_COMPEO2 (0x1u << AC_EVCTRL_COMPEO2_Pos)\r
+#define AC_EVCTRL_COMPEO3_Pos 3 /**< \brief (AC_EVCTRL) Comparator 3 Event Output Enable */\r
+#define AC_EVCTRL_COMPEO3 (0x1u << AC_EVCTRL_COMPEO3_Pos)\r
+#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */\r
+#define AC_EVCTRL_WINEO0 (0x1u << AC_EVCTRL_WINEO0_Pos)\r
+#define AC_EVCTRL_WINEO1_Pos 5 /**< \brief (AC_EVCTRL) Window 1 Event Output Enable */\r
+#define AC_EVCTRL_WINEO1 (0x1u << AC_EVCTRL_WINEO1_Pos)\r
+#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */\r
+#define AC_EVCTRL_COMPEI0 (0x1u << AC_EVCTRL_COMPEI0_Pos)\r
+#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */\r
+#define AC_EVCTRL_COMPEI1 (0x1u << AC_EVCTRL_COMPEI1_Pos)\r
+#define AC_EVCTRL_COMPEI2_Pos 10 /**< \brief (AC_EVCTRL) Comparator 2 Event Input Enable */\r
+#define AC_EVCTRL_COMPEI2 (0x1u << AC_EVCTRL_COMPEI2_Pos)\r
+#define AC_EVCTRL_COMPEI3_Pos 11 /**< \brief (AC_EVCTRL) Comparator 3 Event Input Enable */\r
+#define AC_EVCTRL_COMPEI3 (0x1u << AC_EVCTRL_COMPEI3_Pos)\r
+#define AC_EVCTRL_MASK 0x0F3Fu /**< \brief (AC_EVCTRL) MASK Register */\r
+\r
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Disable */\r
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Disable */\r
+ uint8_t COMP2:1; /*!< bit: 2 Comparator 2 Interrupt Disable */\r
+ uint8_t COMP3:1; /*!< bit: 3 Comparator 3 Interrupt Disable */\r
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Disable */\r
+ uint8_t WIN1:1; /*!< bit: 5 Window 1 Interrupt Disable */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define AC_INTENCLR_RESETVALUE 0x00 /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Disable */\r
+#define AC_INTENCLR_COMP0 (0x1u << AC_INTENCLR_COMP0_Pos)\r
+#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Disable */\r
+#define AC_INTENCLR_COMP1 (0x1u << AC_INTENCLR_COMP1_Pos)\r
+#define AC_INTENCLR_COMP2_Pos 2 /**< \brief (AC_INTENCLR) Comparator 2 Interrupt Disable */\r
+#define AC_INTENCLR_COMP2 (0x1u << AC_INTENCLR_COMP2_Pos)\r
+#define AC_INTENCLR_COMP3_Pos 3 /**< \brief (AC_INTENCLR) Comparator 3 Interrupt Disable */\r
+#define AC_INTENCLR_COMP3 (0x1u << AC_INTENCLR_COMP3_Pos)\r
+#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Disable */\r
+#define AC_INTENCLR_WIN0 (0x1u << AC_INTENCLR_WIN0_Pos)\r
+#define AC_INTENCLR_WIN1_Pos 5 /**< \brief (AC_INTENCLR) Window 1 Interrupt Disable */\r
+#define AC_INTENCLR_WIN1 (0x1u << AC_INTENCLR_WIN1_Pos)\r
+#define AC_INTENCLR_MASK 0x3Fu /**< \brief (AC_INTENCLR) MASK Register */\r
+\r
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */\r
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */\r
+ uint8_t COMP2:1; /*!< bit: 2 Comparator 2 Interrupt Enable */\r
+ uint8_t COMP3:1; /*!< bit: 3 Comparator 3 Interrupt Enable */\r
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */\r
+ uint8_t WIN1:1; /*!< bit: 5 Window 1 Interrupt Enable */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set Register */\r
+#define AC_INTENSET_RESETVALUE 0x00 /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */\r
+#define AC_INTENSET_COMP0 (0x1u << AC_INTENSET_COMP0_Pos)\r
+#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */\r
+#define AC_INTENSET_COMP1 (0x1u << AC_INTENSET_COMP1_Pos)\r
+#define AC_INTENSET_COMP2_Pos 2 /**< \brief (AC_INTENSET) Comparator 2 Interrupt Enable */\r
+#define AC_INTENSET_COMP2 (0x1u << AC_INTENSET_COMP2_Pos)\r
+#define AC_INTENSET_COMP3_Pos 3 /**< \brief (AC_INTENSET) Comparator 3 Interrupt Enable */\r
+#define AC_INTENSET_COMP3 (0x1u << AC_INTENSET_COMP3_Pos)\r
+#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */\r
+#define AC_INTENSET_WIN0 (0x1u << AC_INTENSET_WIN0_Pos)\r
+#define AC_INTENSET_WIN1_Pos 5 /**< \brief (AC_INTENSET) Window 1 Interrupt Enable */\r
+#define AC_INTENSET_WIN1 (0x1u << AC_INTENSET_WIN1_Pos)\r
+#define AC_INTENSET_MASK 0x3Fu /**< \brief (AC_INTENSET) MASK Register */\r
+\r
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Flag */\r
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Flag */\r
+ uint8_t COMP2:1; /*!< bit: 2 Comparator 2 Interrupt Flag */\r
+ uint8_t COMP3:1; /*!< bit: 3 Comparator 3 Interrupt Flag */\r
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Flag */\r
+ uint8_t WIN1:1; /*!< bit: 5 Window 1 Interrupt Flag */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define AC_INTFLAG_RESETVALUE 0x00 /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 Interrupt Flag */\r
+#define AC_INTFLAG_COMP0 (0x1u << AC_INTFLAG_COMP0_Pos)\r
+#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 Interrupt Flag */\r
+#define AC_INTFLAG_COMP1 (0x1u << AC_INTFLAG_COMP1_Pos)\r
+#define AC_INTFLAG_COMP2_Pos 2 /**< \brief (AC_INTFLAG) Comparator 2 Interrupt Flag */\r
+#define AC_INTFLAG_COMP2 (0x1u << AC_INTFLAG_COMP2_Pos)\r
+#define AC_INTFLAG_COMP3_Pos 3 /**< \brief (AC_INTFLAG) Comparator 3 Interrupt Flag */\r
+#define AC_INTFLAG_COMP3 (0x1u << AC_INTFLAG_COMP3_Pos)\r
+#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 Interrupt Flag */\r
+#define AC_INTFLAG_WIN0 (0x1u << AC_INTFLAG_WIN0_Pos)\r
+#define AC_INTFLAG_WIN1_Pos 5 /**< \brief (AC_INTFLAG) Window 1 Interrupt Flag */\r
+#define AC_INTFLAG_WIN1 (0x1u << AC_INTFLAG_WIN1_Pos)\r
+#define AC_INTFLAG_MASK 0x3Fu /**< \brief (AC_INTFLAG) MASK Register */\r
+\r
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */\r
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */\r
+ uint8_t STATE2:1; /*!< bit: 2 Comparator 2 Current State */\r
+ uint8_t STATE3:1; /*!< bit: 3 Comparator 3 Current State */\r
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */\r
+ uint8_t WSTATE1:2; /*!< bit: 6.. 7 Window 1 Current State */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_STATUSA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A Register */\r
+#define AC_STATUSA_RESETVALUE 0x00 /**< \brief (AC_STATUSA reset_value) Status A Register */\r
+\r
+#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */\r
+#define AC_STATUSA_STATE0 (0x1u << AC_STATUSA_STATE0_Pos)\r
+#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */\r
+#define AC_STATUSA_STATE1 (0x1u << AC_STATUSA_STATE1_Pos)\r
+#define AC_STATUSA_STATE2_Pos 2 /**< \brief (AC_STATUSA) Comparator 2 Current State */\r
+#define AC_STATUSA_STATE2 (0x1u << AC_STATUSA_STATE2_Pos)\r
+#define AC_STATUSA_STATE3_Pos 3 /**< \brief (AC_STATUSA) Comparator 3 Current State */\r
+#define AC_STATUSA_STATE3 (0x1u << AC_STATUSA_STATE3_Pos)\r
+#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */\r
+#define AC_STATUSA_WSTATE0_Msk (0x3u << AC_STATUSA_WSTATE0_Pos)\r
+#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))\r
+#define AC_STATUSA_WSTATE0_ABOVE (0x0u << 4) /**< \brief (AC_STATUSA) */\r
+#define AC_STATUSA_WSTATE0_INSIDE (0x1u << 4) /**< \brief (AC_STATUSA) */\r
+#define AC_STATUSA_WSTATE0_BELOW (0x2u << 4) /**< \brief (AC_STATUSA) */\r
+#define AC_STATUSA_WSTATE1_Pos 6 /**< \brief (AC_STATUSA) Window 1 Current State */\r
+#define AC_STATUSA_WSTATE1_Msk (0x3u << AC_STATUSA_WSTATE1_Pos)\r
+#define AC_STATUSA_WSTATE1(value) ((AC_STATUSA_WSTATE1_Msk & ((value) << AC_STATUSA_WSTATE1_Pos)))\r
+#define AC_STATUSA_WSTATE1_ABOVE (0x0u << 6) /**< \brief (AC_STATUSA) */\r
+#define AC_STATUSA_WSTATE1_INSIDE (0x1u << 6) /**< \brief (AC_STATUSA) */\r
+#define AC_STATUSA_WSTATE1_BELOW (0x2u << 6) /**< \brief (AC_STATUSA) */\r
+#define AC_STATUSA_MASK 0xFFu /**< \brief (AC_STATUSA) MASK Register */\r
+\r
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */\r
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */\r
+ uint8_t READY2:1; /*!< bit: 2 Comparator 2 Ready */\r
+ uint8_t READY3:1; /*!< bit: 3 Comparator 3 Ready */\r
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */\r
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_STATUSB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B Register */\r
+#define AC_STATUSB_RESETVALUE 0x00 /**< \brief (AC_STATUSB reset_value) Status B Register */\r
+\r
+#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */\r
+#define AC_STATUSB_READY0 (0x1u << AC_STATUSB_READY0_Pos)\r
+#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */\r
+#define AC_STATUSB_READY1 (0x1u << AC_STATUSB_READY1_Pos)\r
+#define AC_STATUSB_READY2_Pos 2 /**< \brief (AC_STATUSB) Comparator 2 Ready */\r
+#define AC_STATUSB_READY2 (0x1u << AC_STATUSB_READY2_Pos)\r
+#define AC_STATUSB_READY3_Pos 3 /**< \brief (AC_STATUSB) Comparator 3 Ready */\r
+#define AC_STATUSB_READY3 (0x1u << AC_STATUSB_READY3_Pos)\r
+#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */\r
+#define AC_STATUSB_SYNCBUSY (0x1u << AC_STATUSB_SYNCBUSY_Pos)\r
+#define AC_STATUSB_MASK 0x8Fu /**< \brief (AC_STATUSB) MASK Register */\r
+\r
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */\r
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */\r
+ uint8_t STATE2:1; /*!< bit: 2 Comparator 2 Current State */\r
+ uint8_t STATE3:1; /*!< bit: 3 Comparator 3 Current State */\r
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */\r
+ uint8_t WSTATE1:2; /*!< bit: 6.. 7 Window 1 Current State */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_STATUSC_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C Register */\r
+#define AC_STATUSC_RESETVALUE 0x00 /**< \brief (AC_STATUSC reset_value) Status C Register */\r
+\r
+#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */\r
+#define AC_STATUSC_STATE0 (0x1u << AC_STATUSC_STATE0_Pos)\r
+#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */\r
+#define AC_STATUSC_STATE1 (0x1u << AC_STATUSC_STATE1_Pos)\r
+#define AC_STATUSC_STATE2_Pos 2 /**< \brief (AC_STATUSC) Comparator 2 Current State */\r
+#define AC_STATUSC_STATE2 (0x1u << AC_STATUSC_STATE2_Pos)\r
+#define AC_STATUSC_STATE3_Pos 3 /**< \brief (AC_STATUSC) Comparator 3 Current State */\r
+#define AC_STATUSC_STATE3 (0x1u << AC_STATUSC_STATE3_Pos)\r
+#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */\r
+#define AC_STATUSC_WSTATE0_Msk (0x3u << AC_STATUSC_WSTATE0_Pos)\r
+#define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))\r
+#define AC_STATUSC_WSTATE0_ABOVE (0x0u << 4) /**< \brief (AC_STATUSC) */\r
+#define AC_STATUSC_WSTATE0_INSIDE (0x1u << 4) /**< \brief (AC_STATUSC) */\r
+#define AC_STATUSC_WSTATE0_BELOW (0x2u << 4) /**< \brief (AC_STATUSC) */\r
+#define AC_STATUSC_WSTATE1_Pos 6 /**< \brief (AC_STATUSC) Window 1 Current State */\r
+#define AC_STATUSC_WSTATE1_Msk (0x3u << AC_STATUSC_WSTATE1_Pos)\r
+#define AC_STATUSC_WSTATE1(value) ((AC_STATUSC_WSTATE1_Msk & ((value) << AC_STATUSC_WSTATE1_Pos)))\r
+#define AC_STATUSC_WSTATE1_ABOVE (0x0u << 6) /**< \brief (AC_STATUSC) */\r
+#define AC_STATUSC_WSTATE1_INSIDE (0x1u << 6) /**< \brief (AC_STATUSC) */\r
+#define AC_STATUSC_WSTATE1_BELOW (0x2u << 6) /**< \brief (AC_STATUSC) */\r
+#define AC_STATUSC_MASK 0xFFu /**< \brief (AC_STATUSC) MASK Register */\r
+\r
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */\r
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */\r
+ uint8_t :1; /*!< bit: 3 Reserved */\r
+ uint8_t WEN1:1; /*!< bit: 4 Window 1 Mode Enable */\r
+ uint8_t WINTSEL1:2; /*!< bit: 5.. 6 Window 1 Interrupt Selection */\r
+ uint8_t :1; /*!< bit: 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_WINCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control Register */\r
+#define AC_WINCTRL_RESETVALUE 0x00 /**< \brief (AC_WINCTRL reset_value) Window Control Register */\r
+\r
+#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */\r
+#define AC_WINCTRL_WEN0 (0x1u << AC_WINCTRL_WEN0_Pos)\r
+#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */\r
+#define AC_WINCTRL_WINTSEL0_Msk (0x3u << AC_WINCTRL_WINTSEL0_Pos)\r
+#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))\r
+#define AC_WINCTRL_WINTSEL0_ABOVE (0x0u << 1) /**< \brief (AC_WINCTRL) */\r
+#define AC_WINCTRL_WINTSEL0_INSIDE (0x1u << 1) /**< \brief (AC_WINCTRL) */\r
+#define AC_WINCTRL_WINTSEL0_BELOW (0x2u << 1) /**< \brief (AC_WINCTRL) */\r
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (0x3u << 1) /**< \brief (AC_WINCTRL) */\r
+#define AC_WINCTRL_WEN1_Pos 4 /**< \brief (AC_WINCTRL) Window 1 Mode Enable */\r
+#define AC_WINCTRL_WEN1 (0x1u << AC_WINCTRL_WEN1_Pos)\r
+#define AC_WINCTRL_WINTSEL1_Pos 5 /**< \brief (AC_WINCTRL) Window 1 Interrupt Selection */\r
+#define AC_WINCTRL_WINTSEL1_Msk (0x3u << AC_WINCTRL_WINTSEL1_Pos)\r
+#define AC_WINCTRL_WINTSEL1(value) ((AC_WINCTRL_WINTSEL1_Msk & ((value) << AC_WINCTRL_WINTSEL1_Pos)))\r
+#define AC_WINCTRL_WINTSEL1_ABOVE (0x0u << 5) /**< \brief (AC_WINCTRL) */\r
+#define AC_WINCTRL_WINTSEL1_INSIDE (0x1u << 5) /**< \brief (AC_WINCTRL) */\r
+#define AC_WINCTRL_WINTSEL1_BELOW (0x2u << 5) /**< \brief (AC_WINCTRL) */\r
+#define AC_WINCTRL_WINTSEL1_OUTSIDE (0x3u << 5) /**< \brief (AC_WINCTRL) */\r
+#define AC_WINCTRL_MASK 0x77u /**< \brief (AC_WINCTRL) MASK Register */\r
+\r
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */\r
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */\r
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */\r
+ uint32_t :1; /*!< bit: 4 Reserved */\r
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */\r
+ uint32_t :1; /*!< bit: 7 Reserved */\r
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */\r
+ uint32_t :1; /*!< bit: 11 Reserved */\r
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */\r
+ uint32_t :1; /*!< bit: 14 Reserved */\r
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */\r
+ uint32_t OUT:2; /*!< bit: 16..17 Output Mode */\r
+ uint32_t :1; /*!< bit: 18 Reserved */\r
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */\r
+ uint32_t :4; /*!< bit: 20..23 Reserved */\r
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */\r
+ uint32_t :5; /*!< bit: 27..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} AC_COMPCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control Register */\r
+#define AC_COMPCTRL_RESETVALUE 0x00000000 /**< \brief (AC_COMPCTRL reset_value) Comparator Control Register */\r
+\r
+#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */\r
+#define AC_COMPCTRL_ENABLE (0x1u << AC_COMPCTRL_ENABLE_Pos)\r
+#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */\r
+#define AC_COMPCTRL_SINGLE (0x1u << AC_COMPCTRL_SINGLE_Pos)\r
+#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */\r
+#define AC_COMPCTRL_SPEED_Msk (0x3u << AC_COMPCTRL_SPEED_Pos)\r
+#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))\r
+#define AC_COMPCTRL_SPEED_LOWPOWER (0x0u << 2) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_SPEED_FAST (0x1u << 2) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */\r
+#define AC_COMPCTRL_INTSEL_Msk (0x3u << AC_COMPCTRL_INTSEL_Pos)\r
+#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))\r
+#define AC_COMPCTRL_INTSEL_TOGGLE (0x0u << 5) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_INTSEL_RISING (0x1u << 5) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_INTSEL_FALLING (0x2u << 5) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_INTSEL_EOC (0x3u << 5) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */\r
+#define AC_COMPCTRL_MUXNEG_Msk (0x7u << AC_COMPCTRL_MUXNEG_Pos)\r
+#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))\r
+#define AC_COMPCTRL_MUXNEG_PIN0 (0x0u << 8) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXNEG_PIN1 (0x1u << 8) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXNEG_PIN2 (0x2u << 8) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXNEG_PIN3 (0x3u << 8) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXNEG_GND (0x4u << 8) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXNEG_VSCALE (0x5u << 8) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXNEG_BANDGAP (0x6u << 8) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXNEG_DAC (0x7u << 8) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */\r
+#define AC_COMPCTRL_MUXPOS_Msk (0x3u << AC_COMPCTRL_MUXPOS_Pos)\r
+#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))\r
+#define AC_COMPCTRL_MUXPOS_PIN0 (0x0u << 12) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXPOS_PIN1 (0x1u << 12) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXPOS_PIN2 (0x2u << 12) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MUXPOS_PIN3 (0x3u << 12) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */\r
+#define AC_COMPCTRL_SWAP (0x1u << AC_COMPCTRL_SWAP_Pos)\r
+#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output Mode */\r
+#define AC_COMPCTRL_OUT_Msk (0x3u << AC_COMPCTRL_OUT_Pos)\r
+#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))\r
+#define AC_COMPCTRL_OUT_OFF (0x0u << 16) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_OUT_ASYNC (0x1u << 16) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_OUT_SYNC (0x2u << 16) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */\r
+#define AC_COMPCTRL_HYST (0x1u << AC_COMPCTRL_HYST_Pos)\r
+#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */\r
+#define AC_COMPCTRL_FLEN_Msk (0x7u << AC_COMPCTRL_FLEN_Pos)\r
+#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))\r
+#define AC_COMPCTRL_FLEN_OFF (0x0u << 24) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_FLEN_MAJ3 (0x1u << 24) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_FLEN_MAJ5 (0x2u << 24) /**< \brief (AC_COMPCTRL) */\r
+#define AC_COMPCTRL_MASK 0x070BB76Fu /**< \brief (AC_COMPCTRL) MASK Register */\r
+\r
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} AC_SCALER_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler Register */\r
+#define AC_SCALER_RESETVALUE 0x00 /**< \brief (AC_SCALER reset_value) Scaler Register */\r
+\r
+#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */\r
+#define AC_SCALER_VALUE_Msk (0x3Fu << AC_SCALER_VALUE_Pos)\r
+#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))\r
+#define AC_SCALER_MASK 0x3Fu /**< \brief (AC_SCALER) MASK Register */\r
+\r
+/** \brief AC hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */\r
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */\r
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control Register */\r
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear Register */\r
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set Register */\r
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A Register */\r
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B Register */\r
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C Register */\r
+ RoReg8 Reserved2[0x1];\r
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control Register */\r
+ RoReg8 Reserved3[0x3];\r
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control Register [NUM_CMP] */\r
+ RoReg8 Reserved4[0x8];\r
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler Register [NUM_CMP] */\r
+} Ac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_AC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for ADC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_ADC_COMPONENT_\r
+#define _SAMD20_ADC_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR ADC */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_ADC Analog Digital Converter */\r
+/*@{*/\r
+\r
+#define REV_ADC 0x110\r
+\r
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run during Standby */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control Register A */\r
+#define ADC_CTRLA_RESETVALUE 0x00 /**< \brief (ADC_CTRLA reset_value) Control Register A */\r
+\r
+#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */\r
+#define ADC_CTRLA_SWRST (0x1u << ADC_CTRLA_SWRST_Pos)\r
+#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */\r
+#define ADC_CTRLA_ENABLE (0x1u << ADC_CTRLA_ENABLE_Pos)\r
+#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run during Standby */\r
+#define ADC_CTRLA_RUNSTDBY (0x1u << ADC_CTRLA_RUNSTDBY_Pos)\r
+#define ADC_CTRLA_MASK 0x07u /**< \brief (ADC_CTRLA) MASK Register */\r
+\r
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */\r
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */\r
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_REFCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control Register */\r
+#define ADC_REFCTRL_RESETVALUE 0x00 /**< \brief (ADC_REFCTRL reset_value) Reference Control Register */\r
+\r
+#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */\r
+#define ADC_REFCTRL_REFSEL_Msk (0xFu << ADC_REFCTRL_REFSEL_Pos)\r
+#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))\r
+#define ADC_REFCTRL_REFSEL_INT1V (0x0u << 0) /**< \brief (ADC_REFCTRL) */\r
+#define ADC_REFCTRL_REFSEL_INTVCC0 (0x1u << 0) /**< \brief (ADC_REFCTRL) */\r
+#define ADC_REFCTRL_REFSEL_INTVCC1 (0x2u << 0) /**< \brief (ADC_REFCTRL) */\r
+#define ADC_REFCTRL_REFSEL_AREFA (0x3u << 0) /**< \brief (ADC_REFCTRL) */\r
+#define ADC_REFCTRL_REFSEL_AREFB (0x4u << 0) /**< \brief (ADC_REFCTRL) */\r
+#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */\r
+#define ADC_REFCTRL_REFCOMP (0x1u << ADC_REFCTRL_REFCOMP_Pos)\r
+#define ADC_REFCTRL_MASK 0x8Fu /**< \brief (ADC_REFCTRL) MASK Register */\r
+\r
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */\r
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */\r
+ uint8_t :1; /*!< bit: 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_AVGCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control Register */\r
+#define ADC_AVGCTRL_RESETVALUE 0x00 /**< \brief (ADC_AVGCTRL reset_value) Average Control Register */\r
+\r
+#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */\r
+#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFu << ADC_AVGCTRL_SAMPLENUM_Pos)\r
+#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))\r
+#define ADC_AVGCTRL_SAMPLENUM_1 (0x0u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_2 (0x1u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_4 (0x2u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_8 (0x3u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_16 (0x4u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_32 (0x5u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_64 (0x6u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_128 (0x7u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_256 (0x8u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_512 (0x9u << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_SAMPLENUM_1024 (0xAu << 0) /**< \brief (ADC_AVGCTRL) */\r
+#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */\r
+#define ADC_AVGCTRL_ADJRES_Msk (0x7u << ADC_AVGCTRL_ADJRES_Pos)\r
+#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))\r
+#define ADC_AVGCTRL_MASK 0x7Fu /**< \brief (ADC_AVGCTRL) MASK Register */\r
+\r
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sample Time Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_SAMPCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sample Time Control Register */\r
+#define ADC_SAMPCTRL_RESETVALUE 0x00 /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control Register */\r
+\r
+#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */\r
+#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Fu << ADC_SAMPCTRL_SAMPLEN_Pos)\r
+#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))\r
+#define ADC_SAMPCTRL_MASK 0x3Fu /**< \brief (ADC_SAMPCTRL) MASK Register */\r
+\r
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */\r
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */\r
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */\r
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */\r
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */\r
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */\r
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */\r
+ uint16_t :5; /*!< bit: 11..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} ADC_CTRLB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control Register B */\r
+#define ADC_CTRLB_RESETVALUE 0x0000 /**< \brief (ADC_CTRLB reset_value) Control Register B */\r
+\r
+#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */\r
+#define ADC_CTRLB_DIFFMODE (0x1u << ADC_CTRLB_DIFFMODE_Pos)\r
+#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */\r
+#define ADC_CTRLB_LEFTADJ (0x1u << ADC_CTRLB_LEFTADJ_Pos)\r
+#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */\r
+#define ADC_CTRLB_FREERUN (0x1u << ADC_CTRLB_FREERUN_Pos)\r
+#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */\r
+#define ADC_CTRLB_CORREN (0x1u << ADC_CTRLB_CORREN_Pos)\r
+#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */\r
+#define ADC_CTRLB_RESSEL_Msk (0x3u << ADC_CTRLB_RESSEL_Pos)\r
+#define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))\r
+#define ADC_CTRLB_RESSEL_12BIT (0x0u << 4) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_RESSEL_16BIT (0x1u << 4) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_RESSEL_10BIT (0x2u << 4) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_RESSEL_8BIT (0x3u << 4) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */\r
+#define ADC_CTRLB_PRESCALER_Msk (0x7u << ADC_CTRLB_PRESCALER_Pos)\r
+#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))\r
+#define ADC_CTRLB_PRESCALER_DIV4 (0x0u << 8) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_PRESCALER_DIV8 (0x1u << 8) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_PRESCALER_DIV16 (0x2u << 8) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_PRESCALER_DIV32 (0x3u << 8) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_PRESCALER_DIV64 (0x4u << 8) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_PRESCALER_DIV128 (0x5u << 8) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_PRESCALER_DIV256 (0x6u << 8) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_PRESCALER_DIV512 (0x7u << 8) /**< \brief (ADC_CTRLB) */\r
+#define ADC_CTRLB_MASK 0x073Fu /**< \brief (ADC_CTRLB) MASK Register */\r
+\r
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_WINCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control Register */\r
+#define ADC_WINCTRL_RESETVALUE 0x00 /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control Register */\r
+\r
+#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */\r
+#define ADC_WINCTRL_WINMODE_Msk (0x7u << ADC_WINCTRL_WINMODE_Pos)\r
+#define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))\r
+#define ADC_WINCTRL_WINMODE_DISABLE (0x0u << 0) /**< \brief (ADC_WINCTRL) */\r
+#define ADC_WINCTRL_WINMODE_MODE1 (0x1u << 0) /**< \brief (ADC_WINCTRL) */\r
+#define ADC_WINCTRL_WINMODE_MODE2 (0x2u << 0) /**< \brief (ADC_WINCTRL) */\r
+#define ADC_WINCTRL_WINMODE_MODE3 (0x3u << 0) /**< \brief (ADC_WINCTRL) */\r
+#define ADC_WINCTRL_WINMODE_MODE4 (0x4u << 0) /**< \brief (ADC_WINCTRL) */\r
+#define ADC_WINCTRL_MASK 0x07u /**< \brief (ADC_WINCTRL) MASK Register */\r
+\r
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Control Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */\r
+ uint8_t START:1; /*!< bit: 1 Start ADC Conversion */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_SWTRIG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Control Register B */\r
+#define ADC_SWTRIG_RESETVALUE 0x00 /**< \brief (ADC_SWTRIG reset_value) Control Register B */\r
+\r
+#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */\r
+#define ADC_SWTRIG_FLUSH (0x1u << ADC_SWTRIG_FLUSH_Pos)\r
+#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */\r
+#define ADC_SWTRIG_START (0x1u << ADC_SWTRIG_START_Pos)\r
+#define ADC_SWTRIG_MASK 0x03u /**< \brief (ADC_SWTRIG) MASK Register */\r
+\r
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */\r
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */\r
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */\r
+ uint32_t :3; /*!< bit: 13..15 Reserved */\r
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */\r
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */\r
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Value */\r
+ uint32_t :4; /*!< bit: 28..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} ADC_INPUTCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control Register */\r
+#define ADC_INPUTCTRL_RESETVALUE 0x00000000 /**< \brief (ADC_INPUTCTRL reset_value) Input Control Register */\r
+\r
+#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */\r
+#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Fu << ADC_INPUTCTRL_MUXPOS_Pos)\r
+#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))\r
+#define ADC_INPUTCTRL_MUXPOS_PIN0 (0x0u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN1 (0x1u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN2 (0x2u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN3 (0x3u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN4 (0x4u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN5 (0x5u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN6 (0x6u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN7 (0x7u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN8 (0x8u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN9 (0x9u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN10 (0xAu << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN11 (0xBu << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN12 (0xCu << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN13 (0xDu << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN14 (0xEu << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN15 (0xFu << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN16 (0x10u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN17 (0x11u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN18 (0x12u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN19 (0x13u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN20 (0x14u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN21 (0x15u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN22 (0x16u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_PIN23 (0x17u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_TEMP (0x18u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (0x19u << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (0x1Au << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (0x1Bu << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXPOS_DAC (0x1Cu << 0) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */\r
+#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Fu << ADC_INPUTCTRL_MUXNEG_Pos)\r
+#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))\r
+#define ADC_INPUTCTRL_MUXNEG_PIN0 (0x0u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN1 (0x1u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN2 (0x2u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN3 (0x3u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN4 (0x4u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN5 (0x5u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN6 (0x6u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN7 (0x7u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN8 (0x8u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN9 (0x9u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN10 (0xAu << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN11 (0xBu << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN12 (0xCu << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN13 (0xDu << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN14 (0xEu << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN15 (0xFu << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN16 (0x10u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN17 (0x11u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN18 (0x12u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN19 (0x13u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN20 (0x14u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN21 (0x15u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN22 (0x16u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_PIN23 (0x17u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_GND (0x18u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MUXNEG_IOGND (0x19u << 8) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */\r
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFu << ADC_INPUTCTRL_INPUTSCAN_Pos)\r
+#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))\r
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */\r
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFu << ADC_INPUTCTRL_INPUTOFFSET_Pos)\r
+#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))\r
+#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Value */\r
+#define ADC_INPUTCTRL_GAIN_Msk (0xFu << ADC_INPUTCTRL_GAIN_Pos)\r
+#define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))\r
+#define ADC_INPUTCTRL_GAIN_1X (0x0u << 24) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_GAIN_2X (0x1u << 24) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_GAIN_4X (0x2u << 24) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_GAIN_8X (0x3u << 24) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_GAIN_16X (0x4u << 24) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_GAIN_DIV2 (0xFu << 24) /**< \brief (ADC_INPUTCTRL) */\r
+#define ADC_INPUTCTRL_MASK 0x0FFF1F1Fu /**< \brief (ADC_INPUTCTRL) MASK Register */\r
+\r
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */\r
+ uint8_t SYNCEI:1; /*!< bit: 1 Sync Event In */\r
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */\r
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */\r
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_EVCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control Register */\r
+#define ADC_EVCTRL_RESETVALUE 0x00 /**< \brief (ADC_EVCTRL reset_value) Event Control Register */\r
+\r
+#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */\r
+#define ADC_EVCTRL_STARTEI (0x1u << ADC_EVCTRL_STARTEI_Pos)\r
+#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Sync Event In */\r
+#define ADC_EVCTRL_SYNCEI (0x1u << ADC_EVCTRL_SYNCEI_Pos)\r
+#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */\r
+#define ADC_EVCTRL_RESRDYEO (0x1u << ADC_EVCTRL_RESRDYEO_Pos)\r
+#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */\r
+#define ADC_EVCTRL_WINMONEO (0x1u << ADC_EVCTRL_WINMONEO_Pos)\r
+#define ADC_EVCTRL_MASK 0x33u /**< \brief (ADC_EVCTRL) MASK Register */\r
+\r
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */\r
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */\r
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */\r
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronisation Ready Interrupt Disable */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define ADC_INTENCLR_RESETVALUE 0x00 /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */\r
+#define ADC_INTENCLR_RESRDY (0x1u << ADC_INTENCLR_RESRDY_Pos)\r
+#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */\r
+#define ADC_INTENCLR_OVERRUN (0x1u << ADC_INTENCLR_OVERRUN_Pos)\r
+#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */\r
+#define ADC_INTENCLR_WINMON (0x1u << ADC_INTENCLR_WINMON_Pos)\r
+#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronisation Ready Interrupt Disable */\r
+#define ADC_INTENCLR_SYNCRDY (0x1u << ADC_INTENCLR_SYNCRDY_Pos)\r
+#define ADC_INTENCLR_MASK 0x0Fu /**< \brief (ADC_INTENCLR) MASK Register */\r
+\r
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */\r
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */\r
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */\r
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronisation Ready Interrupt Enable */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set Register */\r
+#define ADC_INTENSET_RESETVALUE 0x00 /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */\r
+#define ADC_INTENSET_RESRDY (0x1u << ADC_INTENSET_RESRDY_Pos)\r
+#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */\r
+#define ADC_INTENSET_OVERRUN (0x1u << ADC_INTENSET_OVERRUN_Pos)\r
+#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */\r
+#define ADC_INTENSET_WINMON (0x1u << ADC_INTENSET_WINMON_Pos)\r
+#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronisation Ready Interrupt Enable */\r
+#define ADC_INTENSET_SYNCRDY (0x1u << ADC_INTENSET_SYNCRDY_Pos)\r
+#define ADC_INTENSET_MASK 0x0Fu /**< \brief (ADC_INTENSET) MASK Register */\r
+\r
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */\r
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */\r
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */\r
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronisation Ready Interrupt Flag */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define ADC_INTFLAG_RESETVALUE 0x00 /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */\r
+#define ADC_INTFLAG_RESRDY (0x1u << ADC_INTFLAG_RESRDY_Pos)\r
+#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */\r
+#define ADC_INTFLAG_OVERRUN (0x1u << ADC_INTFLAG_OVERRUN_Pos)\r
+#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */\r
+#define ADC_INTFLAG_WINMON (0x1u << ADC_INTFLAG_WINMON_Pos)\r
+#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronisation Ready Interrupt Flag */\r
+#define ADC_INTFLAG_SYNCRDY (0x1u << ADC_INTFLAG_SYNCRDY_Pos)\r
+#define ADC_INTFLAG_MASK 0x0Fu /**< \brief (ADC_INTFLAG) MASK Register */\r
+\r
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */\r
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronisation Busy Status */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status Register */\r
+#define ADC_STATUS_RESETVALUE 0x00 /**< \brief (ADC_STATUS reset_value) Status Register */\r
+\r
+#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronisation Busy Status */\r
+#define ADC_STATUS_SYNCBUSY (0x1u << ADC_STATUS_SYNCBUSY_Pos)\r
+#define ADC_STATUS_MASK 0x80u /**< \brief (ADC_STATUS) MASK Register */\r
+\r
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} ADC_RESULT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result Register */\r
+#define ADC_RESULT_RESETVALUE 0x0000 /**< \brief (ADC_RESULT reset_value) Result Register */\r
+\r
+#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */\r
+#define ADC_RESULT_RESULT_Msk (0xFFFFu << ADC_RESULT_RESULT_Pos)\r
+#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))\r
+#define ADC_RESULT_MASK 0xFFFFu /**< \brief (ADC_RESULT) MASK Register */\r
+\r
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} ADC_WINLT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold Register */\r
+#define ADC_WINLT_RESETVALUE 0x0000 /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold Register */\r
+\r
+#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */\r
+#define ADC_WINLT_WINLT_Msk (0xFFFFu << ADC_WINLT_WINLT_Pos)\r
+#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))\r
+#define ADC_WINLT_MASK 0xFFFFu /**< \brief (ADC_WINLT) MASK Register */\r
+\r
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} ADC_WINUT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold Register */\r
+#define ADC_WINUT_RESETVALUE 0x0000 /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold Register */\r
+\r
+#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */\r
+#define ADC_WINUT_WINUT_Msk (0xFFFFu << ADC_WINUT_WINUT_Pos)\r
+#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))\r
+#define ADC_WINUT_MASK 0xFFFFu /**< \brief (ADC_WINUT) MASK Register */\r
+\r
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */\r
+ uint16_t :4; /*!< bit: 12..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} ADC_GAINCORR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction Register */\r
+#define ADC_GAINCORR_RESETVALUE 0x0000 /**< \brief (ADC_GAINCORR reset_value) Gain Correction Register */\r
+\r
+#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */\r
+#define ADC_GAINCORR_GAINCORR_Msk (0xFFFu << ADC_GAINCORR_GAINCORR_Pos)\r
+#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))\r
+#define ADC_GAINCORR_MASK 0x0FFFu /**< \brief (ADC_GAINCORR) MASK Register */\r
+\r
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */\r
+ uint16_t :4; /*!< bit: 12..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} ADC_OFFSETCORR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction Register */\r
+#define ADC_OFFSETCORR_RESETVALUE 0x0000 /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction Register */\r
+\r
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */\r
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFu << ADC_OFFSETCORR_OFFSETCORR_Pos)\r
+#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))\r
+#define ADC_OFFSETCORR_MASK 0x0FFFu /**< \brief (ADC_OFFSETCORR) MASK Register */\r
+\r
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration */\r
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Configuration */\r
+ uint16_t :5; /*!< bit: 11..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} ADC_CALIB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration Register */\r
+#define ADC_CALIB_RESETVALUE 0x0000 /**< \brief (ADC_CALIB reset_value) Calibration Register */\r
+\r
+#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration */\r
+#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFu << ADC_CALIB_LINEARITY_CAL_Pos)\r
+#define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))\r
+#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Configuration */\r
+#define ADC_CALIB_BIAS_CAL_Msk (0x7u << ADC_CALIB_BIAS_CAL_Pos)\r
+#define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))\r
+#define ADC_CALIB_MASK 0x07FFu /**< \brief (ADC_CALIB) MASK Register */\r
+\r
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_DBGCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Register */\r
+#define ADC_DBGCTRL_RESETVALUE 0x00 /**< \brief (ADC_DBGCTRL reset_value) Debug Register */\r
+\r
+#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */\r
+#define ADC_DBGCTRL_DBGRUN (0x1u << ADC_DBGCTRL_DBGRUN_Pos)\r
+#define ADC_DBGCTRL_MASK 0x01u /**< \brief (ADC_DBGCTRL) MASK Register */\r
+\r
+/* -------- ADC_TEST : (ADC Offset: 0x2B) (R/W 8) Test Modes Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t TEST_EN:1; /*!< bit: 0 Enable Test Mode */\r
+ uint8_t REFPAD_EN:1; /*!< bit: 1 Connect Vrefp/n to aio33testp/n */\r
+ uint8_t REFINT_DIS:1; /*!< bit: 2 Disable Internal Reference */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_TEST_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_TEST_OFFSET 0x2B /**< \brief (ADC_TEST offset) Test Modes Register */\r
+#define ADC_TEST_RESETVALUE 0x00 /**< \brief (ADC_TEST reset_value) Test Modes Register */\r
+\r
+#define ADC_TEST_TEST_EN_Pos 0 /**< \brief (ADC_TEST) Enable Test Mode */\r
+#define ADC_TEST_TEST_EN (0x1u << ADC_TEST_TEST_EN_Pos)\r
+#define ADC_TEST_REFPAD_EN_Pos 1 /**< \brief (ADC_TEST) Connect Vrefp/n to aio33testp/n */\r
+#define ADC_TEST_REFPAD_EN (0x1u << ADC_TEST_REFPAD_EN_Pos)\r
+#define ADC_TEST_REFINT_DIS_Pos 2 /**< \brief (ADC_TEST) Disable Internal Reference */\r
+#define ADC_TEST_REFINT_DIS (0x1u << ADC_TEST_REFINT_DIS_Pos)\r
+#define ADC_TEST_MASK 0x07u /**< \brief (ADC_TEST) MASK Register */\r
+\r
+/* -------- ADC_TESTRESULT : (ADC Offset: 0x2C) (R/W 32) Test Result Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t TESTRESULT:24; /*!< bit: 0..23 Result Directly from ADC Hard Block */\r
+ uint32_t :8; /*!< bit: 24..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} ADC_TESTRESULT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_TESTRESULT_OFFSET 0x2C /**< \brief (ADC_TESTRESULT offset) Test Result Register */\r
+#define ADC_TESTRESULT_RESETVALUE 0x00000000 /**< \brief (ADC_TESTRESULT reset_value) Test Result Register */\r
+\r
+#define ADC_TESTRESULT_TESTRESULT_Pos 0 /**< \brief (ADC_TESTRESULT) Result Directly from ADC Hard Block */\r
+#define ADC_TESTRESULT_TESTRESULT_Msk (0xFFFFFFu << ADC_TESTRESULT_TESTRESULT_Pos)\r
+#define ADC_TESTRESULT_TESTRESULT(value) ((ADC_TESTRESULT_TESTRESULT_Msk & ((value) << ADC_TESTRESULT_TESTRESULT_Pos)))\r
+#define ADC_TESTRESULT_MASK 0x00FFFFFFu /**< \brief (ADC_TESTRESULT) MASK Register */\r
+\r
+/* -------- ADC_DCFG : (ADC Offset: 0x30) (R/W 8) Device Configuration -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CMPDELAY:1; /*!< bit: 0 Comparator Delay Control */\r
+ uint8_t BOOSTEN:1; /*!< bit: 1 Enable the SR Booster in the Op Amp */\r
+ uint8_t VCMPULSE:1; /*!< bit: 2 Enable VCM Pulse */\r
+ uint8_t BIAS_OPA:1; /*!< bit: 3 Select PTAT Biasing for OPA */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} ADC_DCFG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define ADC_DCFG_OFFSET 0x30 /**< \brief (ADC_DCFG offset) Device Configuration */\r
+#define ADC_DCFG_RESETVALUE 0x00 /**< \brief (ADC_DCFG reset_value) Device Configuration */\r
+\r
+#define ADC_DCFG_CMPDELAY_Pos 0 /**< \brief (ADC_DCFG) Comparator Delay Control */\r
+#define ADC_DCFG_CMPDELAY (0x1u << ADC_DCFG_CMPDELAY_Pos)\r
+#define ADC_DCFG_BOOSTEN_Pos 1 /**< \brief (ADC_DCFG) Enable the SR Booster in the Op Amp */\r
+#define ADC_DCFG_BOOSTEN (0x1u << ADC_DCFG_BOOSTEN_Pos)\r
+#define ADC_DCFG_VCMPULSE_Pos 2 /**< \brief (ADC_DCFG) Enable VCM Pulse */\r
+#define ADC_DCFG_VCMPULSE (0x1u << ADC_DCFG_VCMPULSE_Pos)\r
+#define ADC_DCFG_BIAS_OPA_Pos 3 /**< \brief (ADC_DCFG) Select PTAT Biasing for OPA */\r
+#define ADC_DCFG_BIAS_OPA (0x1u << ADC_DCFG_BIAS_OPA_Pos)\r
+#define ADC_DCFG_MASK 0x0Fu /**< \brief (ADC_DCFG) MASK Register */\r
+\r
+/** \brief ADC hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control Register A */\r
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control Register */\r
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control Register */\r
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sample Time Control Register */\r
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control Register B */\r
+ RoReg8 Reserved1[0x2];\r
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control Register */\r
+ RoReg8 Reserved2[0x3];\r
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Control Register B */\r
+ RoReg8 Reserved3[0x3];\r
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control Register */\r
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control Register */\r
+ RoReg8 Reserved4[0x1];\r
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear Register */\r
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set Register */\r
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear Register */\r
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status Register */\r
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result Register */\r
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold Register */\r
+ RoReg8 Reserved5[0x2];\r
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold Register */\r
+ RoReg8 Reserved6[0x2];\r
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction Register */\r
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction Register */\r
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration Register */\r
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Register */\r
+ __IO ADC_TEST_Type TEST; /**< \brief Offset: 0x2B (R/W 8) Test Modes Register */\r
+ __IO ADC_TESTRESULT_Type TESTRESULT; /**< \brief Offset: 0x2C (R/W 32) Test Result Register */\r
+ __IO ADC_DCFG_Type DCFG; /**< \brief Offset: 0x30 (R/W 8) Device Configuration */\r
+} Adc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_ADC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for DAC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_DAC_COMPONENT_\r
+#define _SAMD20_DAC_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR DAC */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_DAC Digital Analog Converter */\r
+/*@{*/\r
+\r
+#define REV_DAC 0x101\r
+\r
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run during Standby */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DAC_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control Register A */\r
+#define DAC_CTRLA_RESETVALUE 0x00 /**< \brief (DAC_CTRLA reset_value) Control Register A */\r
+\r
+#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */\r
+#define DAC_CTRLA_SWRST (0x1u << DAC_CTRLA_SWRST_Pos)\r
+#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */\r
+#define DAC_CTRLA_ENABLE (0x1u << DAC_CTRLA_ENABLE_Pos)\r
+#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run during Standby */\r
+#define DAC_CTRLA_RUNSTDBY (0x1u << DAC_CTRLA_RUNSTDBY_Pos)\r
+#define DAC_CTRLA_MASK 0x07u /**< \brief (DAC_CTRLA) MASK Register */\r
+\r
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t EOEN:1; /*!< bit: 0 Output Buffer Enable */\r
+ uint8_t IOEN:1; /*!< bit: 1 Internal DAC Output Channel Enabled for AC */\r
+ uint8_t LEFTADJ:1; /*!< bit: 2 Left-Adjusted Value */\r
+ uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */\r
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */\r
+ uint8_t REFSEL:2; /*!< bit: 6.. 7 Voltage Reference Select for DAC */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DAC_CTRLB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control Register B */\r
+#define DAC_CTRLB_RESETVALUE 0x00 /**< \brief (DAC_CTRLB reset_value) Control Register B */\r
+\r
+#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) Output Buffer Enable */\r
+#define DAC_CTRLB_EOEN (0x1u << DAC_CTRLB_EOEN_Pos)\r
+#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal DAC Output Channel Enabled for AC */\r
+#define DAC_CTRLB_IOEN (0x1u << DAC_CTRLB_IOEN_Pos)\r
+#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left-Adjusted Value */\r
+#define DAC_CTRLB_LEFTADJ (0x1u << DAC_CTRLB_LEFTADJ_Pos)\r
+#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */\r
+#define DAC_CTRLB_VPD (0x1u << DAC_CTRLB_VPD_Pos)\r
+#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Voltage Reference Select for DAC */\r
+#define DAC_CTRLB_REFSEL_Msk (0x3u << DAC_CTRLB_REFSEL_Pos)\r
+#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))\r
+#define DAC_CTRLB_MASK 0xCFu /**< \brief (DAC_CTRLB) MASK Register */\r
+\r
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */\r
+ uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DAC_EVCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control Register */\r
+#define DAC_EVCTRL_RESETVALUE 0x00 /**< \brief (DAC_EVCTRL reset_value) Event Control Register */\r
+\r
+#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */\r
+#define DAC_EVCTRL_STARTEI (0x1u << DAC_EVCTRL_STARTEI_Pos)\r
+#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */\r
+#define DAC_EVCTRL_EMPTYEO (0x1u << DAC_EVCTRL_EMPTYEO_Pos)\r
+#define DAC_EVCTRL_MASK 0x03u /**< \brief (DAC_EVCTRL) MASK Register */\r
+\r
+/* -------- DAC_TEST : (DAC Offset: 0x3) (R/W 8) Test Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t TESTEN:1; /*!< bit: 0 Test Enable */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DAC_TEST_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_TEST_OFFSET 0x3 /**< \brief (DAC_TEST offset) Test Register */\r
+#define DAC_TEST_RESETVALUE 0x00 /**< \brief (DAC_TEST reset_value) Test Register */\r
+\r
+#define DAC_TEST_TESTEN_Pos 0 /**< \brief (DAC_TEST) Test Enable */\r
+#define DAC_TEST_TESTEN (0x1u << DAC_TEST_TESTEN_Pos)\r
+#define DAC_TEST_MASK 0x01u /**< \brief (DAC_TEST) MASK Register */\r
+\r
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Disable */\r
+ uint8_t EMPTY:1; /*!< bit: 1 Empty Interrupt Disable */\r
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Disable */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DAC_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define DAC_INTENCLR_RESETVALUE 0x00 /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Disable */\r
+#define DAC_INTENCLR_UNDERRUN (0x1u << DAC_INTENCLR_UNDERRUN_Pos)\r
+#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Empty Interrupt Disable */\r
+#define DAC_INTENCLR_EMPTY (0x1u << DAC_INTENCLR_EMPTY_Pos)\r
+#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Disable */\r
+#define DAC_INTENCLR_SYNCRDY (0x1u << DAC_INTENCLR_SYNCRDY_Pos)\r
+#define DAC_INTENCLR_MASK 0x07u /**< \brief (DAC_INTENCLR) MASK Register */\r
+\r
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */\r
+ uint8_t EMPTY:1; /*!< bit: 1 Empty Interrupt Enable */\r
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DAC_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set Register */\r
+#define DAC_INTENSET_RESETVALUE 0x00 /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */\r
+#define DAC_INTENSET_UNDERRUN (0x1u << DAC_INTENSET_UNDERRUN_Pos)\r
+#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Empty Interrupt Enable */\r
+#define DAC_INTENSET_EMPTY (0x1u << DAC_INTENSET_EMPTY_Pos)\r
+#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */\r
+#define DAC_INTENSET_SYNCRDY (0x1u << DAC_INTENSET_SYNCRDY_Pos)\r
+#define DAC_INTENSET_MASK 0x07u /**< \brief (DAC_INTENSET) MASK Register */\r
+\r
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Flag */\r
+ uint8_t EMPTY:1; /*!< bit: 1 Empty Interrupt Flag */\r
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Flag */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DAC_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define DAC_INTFLAG_RESETVALUE 0x00 /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun Interrupt Flag */\r
+#define DAC_INTFLAG_UNDERRUN (0x1u << DAC_INTFLAG_UNDERRUN_Pos)\r
+#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Empty Interrupt Flag */\r
+#define DAC_INTFLAG_EMPTY (0x1u << DAC_INTFLAG_EMPTY_Pos)\r
+#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready Interrupt Flag */\r
+#define DAC_INTFLAG_SYNCRDY (0x1u << DAC_INTFLAG_SYNCRDY_Pos)\r
+#define DAC_INTFLAG_MASK 0x07u /**< \brief (DAC_INTFLAG) MASK Register */\r
+\r
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */\r
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DAC_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status Register */\r
+#define DAC_STATUS_RESETVALUE 0x00 /**< \brief (DAC_STATUS reset_value) Status Register */\r
+\r
+#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy */\r
+#define DAC_STATUS_SYNCBUSY (0x1u << DAC_STATUS_SYNCBUSY_Pos)\r
+#define DAC_STATUS_MASK 0x80u /**< \brief (DAC_STATUS) MASK Register */\r
+\r
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct { // LEFT_ADJUSTED mode\r
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */\r
+ uint16_t DATA:10; /*!< bit: 6..15 Data to be Converted */\r
+ } LEFT_ADJUSTED; /*!< Structure used for LEFT_ADJUSTED */\r
+ struct { // RIGHT_ADJUSTED mode\r
+ uint16_t DATA:10; /*!< bit: 0.. 9 Data to be converted */\r
+ uint16_t :6; /*!< bit: 10..15 Reserved */\r
+ } RIGHT_ADJUSTED; /*!< Structure used for RIGHT_ADJUSTED */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} DAC_DATA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data Register */\r
+#define DAC_DATA_RESETVALUE 0x0000 /**< \brief (DAC_DATA reset_value) Data Register */\r
+\r
+// LEFT_ADJUSTED mode\r
+#define DAC_DATA_LEFT_ADJUSTED_DATA_Pos 6 /**< \brief (DAC_DATA_LEFT_ADJUSTED) Data to be Converted */\r
+#define DAC_DATA_LEFT_ADJUSTED_DATA_Msk (0x3FFu << DAC_DATA_LEFT_ADJUSTED_DATA_Pos)\r
+#define DAC_DATA_LEFT_ADJUSTED_DATA(value) ((DAC_DATA_LEFT_ADJUSTED_DATA_Msk & ((value) << DAC_DATA_LEFT_ADJUSTED_DATA_Pos)))\r
+#define DAC_DATA_LEFT_ADJUSTED_MASK 0xFFC0u /**< \brief (DAC_DATA_LEFT_ADJUSTED) MASK Register */\r
+\r
+// RIGHT_ADJUSTED mode\r
+#define DAC_DATA_RIGHT_ADJUSTED_DATA_Pos 0 /**< \brief (DAC_DATA_RIGHT_ADJUSTED) Data to be converted */\r
+#define DAC_DATA_RIGHT_ADJUSTED_DATA_Msk (0x3FFu << DAC_DATA_RIGHT_ADJUSTED_DATA_Pos)\r
+#define DAC_DATA_RIGHT_ADJUSTED_DATA(value) ((DAC_DATA_RIGHT_ADJUSTED_DATA_Msk & ((value) << DAC_DATA_RIGHT_ADJUSTED_DATA_Pos)))\r
+#define DAC_DATA_RIGHT_ADJUSTED_MASK 0x03FFu /**< \brief (DAC_DATA_RIGHT_ADJUSTED) MASK Register */\r
+\r
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct { // LEFT_ADJUSTED mode\r
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */\r
+ uint16_t DATABUF:10; /*!< bit: 6..15 Data Buffer */\r
+ } LEFT_ADJUSTED; /*!< Structure used for LEFT_ADJUSTED */\r
+ struct { // RIGHT_ADJUSTED mode\r
+ uint16_t DATABUF:10; /*!< bit: 0.. 9 Data Buffer */\r
+ uint16_t :6; /*!< bit: 10..15 Reserved */\r
+ } RIGHT_ADJUSTED; /*!< Structure used for RIGHT_ADJUSTED */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} DAC_DATABUF_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer Register */\r
+#define DAC_DATABUF_RESETVALUE 0x0000 /**< \brief (DAC_DATABUF reset_value) Data Buffer Register */\r
+\r
+// LEFT_ADJUSTED mode\r
+#define DAC_DATABUF_LEFT_ADJUSTED_DATABUF_Pos 6 /**< \brief (DAC_DATABUF_LEFT_ADJUSTED) Data Buffer */\r
+#define DAC_DATABUF_LEFT_ADJUSTED_DATABUF_Msk (0x3FFu << DAC_DATABUF_LEFT_ADJUSTED_DATABUF_Pos)\r
+#define DAC_DATABUF_LEFT_ADJUSTED_DATABUF(value) ((DAC_DATABUF_LEFT_ADJUSTED_DATABUF_Msk & ((value) << DAC_DATABUF_LEFT_ADJUSTED_DATABUF_Pos)))\r
+#define DAC_DATABUF_LEFT_ADJUSTED_MASK 0xFFC0u /**< \brief (DAC_DATABUF_LEFT_ADJUSTED) MASK Register */\r
+\r
+// RIGHT_ADJUSTED mode\r
+#define DAC_DATABUF_RIGHT_ADJUSTED_DATABUF_Pos 0 /**< \brief (DAC_DATABUF_RIGHT_ADJUSTED) Data Buffer */\r
+#define DAC_DATABUF_RIGHT_ADJUSTED_DATABUF_Msk (0x3FFu << DAC_DATABUF_RIGHT_ADJUSTED_DATABUF_Pos)\r
+#define DAC_DATABUF_RIGHT_ADJUSTED_DATABUF(value) ((DAC_DATABUF_RIGHT_ADJUSTED_DATABUF_Msk & ((value) << DAC_DATABUF_RIGHT_ADJUSTED_DATABUF_Pos)))\r
+#define DAC_DATABUF_RIGHT_ADJUSTED_MASK 0x03FFu /**< \brief (DAC_DATABUF_RIGHT_ADJUSTED) MASK Register */\r
+\r
+/** \brief DAC hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control Register A */\r
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control Register B */\r
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control Register */\r
+ __IO DAC_TEST_Type TEST; /**< \brief Offset: 0x3 (R/W 8) Test Register */\r
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear Register */\r
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set Register */\r
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear Register */\r
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status Register */\r
+ __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data Register */\r
+ RoReg8 Reserved1[0x2];\r
+ __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer Register */\r
+} Dac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_DAC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for DSU\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_DSU_COMPONENT_\r
+#define _SAMD20_DSU_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR DSU */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_DSU Device Service Unit */\r
+/*@{*/\r
+\r
+#define REV_DSU 0x101\r
+\r
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint8_t :1; /*!< bit: 1 Reserved */\r
+ uint8_t CRC:1; /*!< bit: 2 Cyclic Redundancy Check */\r
+ uint8_t MBIST:1; /*!< bit: 3 Memory BIST */\r
+ uint8_t CE:1; /*!< bit: 4 Chip Erase */\r
+ uint8_t :1; /*!< bit: 5 Reserved */\r
+ uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */\r
+ uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DSU_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control Register */\r
+\r
+#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */\r
+#define DSU_CTRL_SWRST (0x1u << DSU_CTRL_SWRST_Pos)\r
+#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) Cyclic Redundancy Check */\r
+#define DSU_CTRL_CRC (0x1u << DSU_CTRL_CRC_Pos)\r
+#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory BIST */\r
+#define DSU_CTRL_MBIST (0x1u << DSU_CTRL_MBIST_Pos)\r
+#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */\r
+#define DSU_CTRL_CE (0x1u << DSU_CTRL_CE_Pos)\r
+#define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */\r
+#define DSU_CTRL_ARR (0x1u << DSU_CTRL_ARR_Pos)\r
+#define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */\r
+#define DSU_CTRL_SMSA (0x1u << DSU_CTRL_SMSA_Pos)\r
+#define DSU_CTRL_MASK 0xDDu /**< \brief (DSU_CTRL) MASK Register */\r
+\r
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DONE:1; /*!< bit: 0 Done */\r
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */\r
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */\r
+ uint8_t FAIL:1; /*!< bit: 3 Failure */\r
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */\r
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DSU_STATUSA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status Register A */\r
+\r
+#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */\r
+#define DSU_STATUSA_DONE (0x1u << DSU_STATUSA_DONE_Pos)\r
+#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */\r
+#define DSU_STATUSA_CRSTEXT (0x1u << DSU_STATUSA_CRSTEXT_Pos)\r
+#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */\r
+#define DSU_STATUSA_BERR (0x1u << DSU_STATUSA_BERR_Pos)\r
+#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */\r
+#define DSU_STATUSA_FAIL (0x1u << DSU_STATUSA_FAIL_Pos)\r
+#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */\r
+#define DSU_STATUSA_PERR (0x1u << DSU_STATUSA_PERR_Pos)\r
+#define DSU_STATUSA_MASK 0x1Fu /**< \brief (DSU_STATUSA) MASK Register */\r
+\r
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t PROT:1; /*!< bit: 0 Protected */\r
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */\r
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel Dirty */\r
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */\r
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} DSU_STATUSB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status Register B */\r
+#define DSU_STATUSB_RESETVALUE 0x00 /**< \brief (DSU_STATUSB reset_value) Status Register B */\r
+\r
+#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */\r
+#define DSU_STATUSB_PROT (0x1u << DSU_STATUSB_PROT_Pos)\r
+#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */\r
+#define DSU_STATUSB_DBGPRES (0x1u << DSU_STATUSB_DBGPRES_Pos)\r
+#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel Dirty */\r
+#define DSU_STATUSB_DCCD_Msk (0x3u << DSU_STATUSB_DCCD_Pos)\r
+#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))\r
+#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */\r
+#define DSU_STATUSB_HPE (0x1u << DSU_STATUSB_HPE_Pos)\r
+#define DSU_STATUSB_MASK 0x1Fu /**< \brief (DSU_STATUSB) MASK Register */\r
+\r
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */\r
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_ADDR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address Register */\r
+#define DSU_ADDR_RESETVALUE 0x00000000 /**< \brief (DSU_ADDR reset_value) Address Register */\r
+\r
+#define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */\r
+#define DSU_ADDR_AMOD_Msk (0x3u << DSU_ADDR_AMOD_Pos)\r
+#define DSU_ADDR_AMOD(value) ((DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos)))\r
+#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */\r
+#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFu << DSU_ADDR_ADDR_Pos)\r
+#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))\r
+#define DSU_ADDR_MASK 0xFFFFFFFFu /**< \brief (DSU_ADDR) MASK Register */\r
+\r
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */\r
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_LENGTH_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length Register */\r
+#define DSU_LENGTH_RESETVALUE 0x00000000 /**< \brief (DSU_LENGTH reset_value) Length Register */\r
+\r
+#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */\r
+#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFu << DSU_LENGTH_LENGTH_Pos)\r
+#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))\r
+#define DSU_LENGTH_MASK 0xFFFFFFFCu /**< \brief (DSU_LENGTH) MASK Register */\r
+\r
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t DATA:32; /*!< bit: 0..31 Data */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_DATA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data Register */\r
+\r
+#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */\r
+#define DSU_DATA_DATA_Msk (0xFFFFFFFFu << DSU_DATA_DATA_Pos)\r
+#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))\r
+#define DSU_DATA_MASK 0xFFFFFFFFu /**< \brief (DSU_DATA) MASK Register */\r
+\r
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t DATA:32; /*!< bit: 0..31 Data */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_DCC_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel Register */\r
+#define DSU_DCC_RESETVALUE 0x00000000 /**< \brief (DSU_DCC reset_value) Debug Communication Channel Register */\r
+\r
+#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */\r
+#define DSU_DCC_DATA_Msk (0xFFFFFFFFu << DSU_DCC_DATA_Pos)\r
+#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))\r
+#define DSU_DCC_MASK 0xFFFFFFFFu /**< \brief (DSU_DCC) MASK Register */\r
+\r
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */\r
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */\r
+ uint32_t DIE:4; /*!< bit: 12..15 Die Number */\r
+ uint32_t SUBFAMILY:8; /*!< bit: 16..23 Sub-Family */\r
+ uint32_t FAMILY:4; /*!< bit: 24..27 Family */\r
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_DID_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification Register */\r
+#define DSU_DID_RESETVALUE 0x00000000 /**< \brief (DSU_DID reset_value) Device Identification Register */\r
+\r
+#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */\r
+#define DSU_DID_DEVSEL_Msk (0xFFu << DSU_DID_DEVSEL_Pos)\r
+#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))\r
+#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */\r
+#define DSU_DID_REVISION_Msk (0xFu << DSU_DID_REVISION_Pos)\r
+#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))\r
+#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */\r
+#define DSU_DID_DIE_Msk (0xFu << DSU_DID_DIE_Pos)\r
+#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))\r
+#define DSU_DID_SUBFAMILY_Pos 16 /**< \brief (DSU_DID) Sub-Family */\r
+#define DSU_DID_SUBFAMILY_Msk (0xFFu << DSU_DID_SUBFAMILY_Pos)\r
+#define DSU_DID_SUBFAMILY(value) ((DSU_DID_SUBFAMILY_Msk & ((value) << DSU_DID_SUBFAMILY_Pos)))\r
+#define DSU_DID_FAMILY_Pos 24 /**< \brief (DSU_DID) Family */\r
+#define DSU_DID_FAMILY_Msk (0xFu << DSU_DID_FAMILY_Pos)\r
+#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))\r
+#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */\r
+#define DSU_DID_PROCESSOR_Msk (0xFu << DSU_DID_PROCESSOR_Pos)\r
+#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))\r
+#define DSU_DID_MASK 0xFFFFFFFFu /**< \brief (DSU_DID) MASK Register */\r
+\r
+/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_DCFG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration Register */\r
+#define DSU_DCFG_RESETVALUE 0x00000000 /**< \brief (DSU_DCFG reset_value) Device Configuration Register */\r
+\r
+#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */\r
+#define DSU_DCFG_DCFG_Msk (0xFFFFFFFFu << DSU_DCFG_DCFG_Pos)\r
+#define DSU_DCFG_DCFG(value) ((DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos)))\r
+#define DSU_DCFG_MASK 0xFFFFFFFFu /**< \brief (DSU_DCFG) MASK Register */\r
+\r
+/* -------- DSU_UPTM : (DSU Offset: 0x00F8) (R/W 32) UnProtected Test Mode Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t UPTM:32; /*!< bit: 0..31 Un-Protected Test Mode */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_UPTM_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_UPTM_OFFSET 0x00F8 /**< \brief (DSU_UPTM offset) UnProtected Test Mode Register */\r
+#define DSU_UPTM_RESETVALUE 0x00000000 /**< \brief (DSU_UPTM reset_value) UnProtected Test Mode Register */\r
+\r
+#define DSU_UPTM_UPTM_Pos 0 /**< \brief (DSU_UPTM) Un-Protected Test Mode */\r
+#define DSU_UPTM_UPTM_Msk (0xFFFFFFFFu << DSU_UPTM_UPTM_Pos)\r
+#define DSU_UPTM_UPTM(value) ((DSU_UPTM_UPTM_Msk & ((value) << DSU_UPTM_UPTM_Pos)))\r
+#define DSU_UPTM_MASK 0xFFFFFFFFu /**< \brief (DSU_UPTM) MASK Register */\r
+\r
+/* -------- DSU_TESTMODE : (DSU Offset: 0x00FC) (R/W 32) Test Mode Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t TESTMODE:32; /*!< bit: 0..31 Test Mode */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_TESTMODE_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_TESTMODE_OFFSET 0x00FC /**< \brief (DSU_TESTMODE offset) Test Mode Register */\r
+#define DSU_TESTMODE_RESETVALUE 0x00000000 /**< \brief (DSU_TESTMODE reset_value) Test Mode Register */\r
+\r
+#define DSU_TESTMODE_TESTMODE_Pos 0 /**< \brief (DSU_TESTMODE) Test Mode */\r
+#define DSU_TESTMODE_TESTMODE_Msk (0xFFFFFFFFu << DSU_TESTMODE_TESTMODE_Pos)\r
+#define DSU_TESTMODE_TESTMODE(value) ((DSU_TESTMODE_TESTMODE_Msk & ((value) << DSU_TESTMODE_TESTMODE_Pos)))\r
+#define DSU_TESTMODE_MASK 0xFFFFFFFFu /**< \brief (DSU_TESTMODE) MASK Register */\r
+\r
+/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */\r
+ uint32_t FMT:1; /*!< bit: 1 Format */\r
+ uint32_t :10; /*!< bit: 2..11 Reserved */\r
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_ENTRY_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) CoreSight ROM Table Entry Register */\r
+\r
+#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */\r
+#define DSU_ENTRY_EPRES (0x1u << DSU_ENTRY_EPRES_Pos)\r
+#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */\r
+#define DSU_ENTRY_FMT (0x1u << DSU_ENTRY_FMT_Pos)\r
+#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */\r
+#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFu << DSU_ENTRY_ADDOFF_Pos)\r
+#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))\r
+#define DSU_ENTRY_MASK 0xFFFFF003u /**< \brief (DSU_ENTRY) MASK Register */\r
+\r
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) CoreSight ROM Table End Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t END:32; /*!< bit: 0..31 End Marker */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_END_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) CoreSight ROM Table End Register */\r
+#define DSU_END_RESETVALUE 0x00000000 /**< \brief (DSU_END reset_value) CoreSight ROM Table End Register */\r
+\r
+#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */\r
+#define DSU_END_END_Msk (0xFFFFFFFFu << DSU_END_END_Pos)\r
+#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))\r
+#define DSU_END_MASK 0xFFFFFFFFu /**< \brief (DSU_END) MASK Register */\r
+\r
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) CoreSight ROM Table Memory Type Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */\r
+ uint32_t :31; /*!< bit: 1..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_MEMTYPE_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) CoreSight ROM Table Memory Type Register */\r
+\r
+#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */\r
+#define DSU_MEMTYPE_SMEMP (0x1u << DSU_MEMTYPE_SMEMP_Pos)\r
+#define DSU_MEMTYPE_MASK 0x00000001u /**< \brief (DSU_MEMTYPE) MASK Register */\r
+\r
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification Register 4 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */\r
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4kB Count */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_PID4_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification Register 4 */\r
+\r
+#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */\r
+#define DSU_PID4_JEPCC_Msk (0xFu << DSU_PID4_JEPCC_Pos)\r
+#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))\r
+#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4kB Count */\r
+#define DSU_PID4_FKBC_Msk (0xFu << DSU_PID4_FKBC_Pos)\r
+#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))\r
+#define DSU_PID4_MASK 0x000000FFu /**< \brief (DSU_PID4) MASK Register */\r
+\r
+/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification Register 5 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_PID5_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification Register 5 */\r
+#define DSU_PID5_MASK 0x00000000u /**< \brief (DSU_PID5) MASK Register */\r
+\r
+/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification Register 6 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_PID6_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification Register 6 */\r
+#define DSU_PID6_MASK 0x00000000u /**< \brief (DSU_PID6) MASK Register */\r
+\r
+/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification Register 7 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_PID7_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification Register 7 */\r
+#define DSU_PID7_MASK 0x00000000u /**< \brief (DSU_PID7) MASK Register */\r
+\r
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification Register 0 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_PID0_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification Register 0 */\r
+\r
+#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */\r
+#define DSU_PID0_PARTNBL_Msk (0xFFu << DSU_PID0_PARTNBL_Pos)\r
+#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))\r
+#define DSU_PID0_MASK 0x000000FFu /**< \brief (DSU_PID0) MASK Register */\r
+\r
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification Register 1 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */\r
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 JEP-106 Identity Code Low */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_PID1_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification Register 1 */\r
+\r
+#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */\r
+#define DSU_PID1_PARTNBH_Msk (0xFu << DSU_PID1_PARTNBH_Pos)\r
+#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))\r
+#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) JEP-106 Identity Code Low */\r
+#define DSU_PID1_JEPIDCL_Msk (0xFu << DSU_PID1_JEPIDCL_Pos)\r
+#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))\r
+#define DSU_PID1_MASK 0x000000FFu /**< \brief (DSU_PID1) MASK Register */\r
+\r
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification Register 2 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */\r
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is Used */\r
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_PID2_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification Register 2 */\r
+\r
+#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */\r
+#define DSU_PID2_JEPIDCH_Msk (0x7u << DSU_PID2_JEPIDCH_Pos)\r
+#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))\r
+#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is Used */\r
+#define DSU_PID2_JEPU (0x1u << DSU_PID2_JEPU_Pos)\r
+#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */\r
+#define DSU_PID2_REVISION_Msk (0xFu << DSU_PID2_REVISION_Pos)\r
+#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))\r
+#define DSU_PID2_MASK 0x000000FFu /**< \brief (DSU_PID2) MASK Register */\r
+\r
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification Register 3 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 Customer Mode */\r
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_PID3_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification Register 3 */\r
+\r
+#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) Customer Mode */\r
+#define DSU_PID3_CUSMOD_Msk (0xFu << DSU_PID3_CUSMOD_Pos)\r
+#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))\r
+#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */\r
+#define DSU_PID3_REVAND_Msk (0xFu << DSU_PID3_REVAND_Pos)\r
+#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))\r
+#define DSU_PID3_MASK 0x000000FFu /**< \brief (DSU_PID3) MASK Register */\r
+\r
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification Register 0 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_CID0_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification Register 0 */\r
+#define DSU_CID0_RESETVALUE 0x00000000 /**< \brief (DSU_CID0 reset_value) Component Identification Register 0 */\r
+\r
+#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */\r
+#define DSU_CID0_PREAMBLEB0_Msk (0xFFu << DSU_CID0_PREAMBLEB0_Pos)\r
+#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))\r
+#define DSU_CID0_MASK 0x000000FFu /**< \brief (DSU_CID0) MASK Register */\r
+\r
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification Register 1 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble Byte 1 */\r
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_CID1_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification Register 1 */\r
+#define DSU_CID1_RESETVALUE 0x00000000 /**< \brief (DSU_CID1 reset_value) Component Identification Register 1 */\r
+\r
+#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble Byte 1 */\r
+#define DSU_CID1_PREAMBLE_Msk (0xFu << DSU_CID1_PREAMBLE_Pos)\r
+#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))\r
+#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */\r
+#define DSU_CID1_CCLASS_Msk (0xFu << DSU_CID1_CCLASS_Pos)\r
+#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))\r
+#define DSU_CID1_MASK 0x000000FFu /**< \brief (DSU_CID1) MASK Register */\r
+\r
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification Register 2 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_CID2_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification Register 2 */\r
+#define DSU_CID2_RESETVALUE 0x00000000 /**< \brief (DSU_CID2 reset_value) Component Identification Register 2 */\r
+\r
+#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */\r
+#define DSU_CID2_PREAMBLEB2_Msk (0xFFu << DSU_CID2_PREAMBLEB2_Pos)\r
+#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))\r
+#define DSU_CID2_MASK 0x000000FFu /**< \brief (DSU_CID2) MASK Register */\r
+\r
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification Register 3 -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */\r
+ uint32_t :24; /*!< bit: 8..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} DSU_CID3_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification Register 3 */\r
+#define DSU_CID3_RESETVALUE 0x00000000 /**< \brief (DSU_CID3 reset_value) Component Identification Register 3 */\r
+\r
+#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */\r
+#define DSU_CID3_PREAMBLEB3_Msk (0xFFu << DSU_CID3_PREAMBLEB3_Pos)\r
+#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))\r
+#define DSU_CID3_MASK 0x000000FFu /**< \brief (DSU_CID3) MASK Register */\r
+\r
+/** \brief DSU hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control Register */\r
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status Register A */\r
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status Register B */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address Register */\r
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length Register */\r
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data Register */\r
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel Register */\r
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification Register */\r
+ RoReg8 Reserved2[0xD4];\r
+ __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration Register */\r
+ __IO DSU_UPTM_Type UPTM; /**< \brief Offset: 0x00F8 (R/W 32) UnProtected Test Mode Register */\r
+ __IO DSU_TESTMODE_Type TESTMODE; /**< \brief Offset: 0x00FC (R/W 32) Test Mode Register */\r
+ RoReg8 Reserved3[0xF00];\r
+ __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry Register */\r
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End Register */\r
+ RoReg8 Reserved4[0xFC0];\r
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type Register */\r
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification Register 4 */\r
+ __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification Register 5 */\r
+ __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification Register 6 */\r
+ __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification Register 7 */\r
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification Register 0 */\r
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification Register 1 */\r
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification Register 2 */\r
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification Register 3 */\r
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification Register 0 */\r
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification Register 1 */\r
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification Register 2 */\r
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification Register 3 */\r
+} Dsu;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_DSU_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for EIC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_EIC_COMPONENT_\r
+#define _SAMD20_EIC_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR EIC */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_EIC External Interrupt Controller */\r
+/*@{*/\r
+\r
+#define REV_EIC 0x101\r
+\r
+/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} EIC_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control Register */\r
+#define EIC_CTRL_RESETVALUE 0x00 /**< \brief (EIC_CTRL reset_value) Control Register */\r
+\r
+#define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */\r
+#define EIC_CTRL_SWRST (0x1u << EIC_CTRL_SWRST_Pos)\r
+#define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */\r
+#define EIC_CTRL_ENABLE (0x1u << EIC_CTRL_ENABLE_Pos)\r
+#define EIC_CTRL_MASK 0x03u /**< \brief (EIC_CTRL) MASK Register */\r
+\r
+/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */\r
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Sync Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} EIC_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status Register */\r
+#define EIC_STATUS_RESETVALUE 0x00 /**< \brief (EIC_STATUS reset_value) Status Register */\r
+\r
+#define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Sync Busy */\r
+#define EIC_STATUS_SYNCBUSY (0x1u << EIC_STATUS_SYNCBUSY_Pos)\r
+#define EIC_STATUS_MASK 0x80u /**< \brief (EIC_STATUS) MASK Register */\r
+\r
+/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) NMI Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 NMI Input Sense Configuration */\r
+ uint8_t NMIFILTEN:1; /*!< bit: 3 NMI Filter Enable */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} EIC_NMICTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) NMI Control Register */\r
+#define EIC_NMICTRL_RESETVALUE 0x00 /**< \brief (EIC_NMICTRL reset_value) NMI Control Register */\r
+\r
+#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) NMI Input Sense Configuration */\r
+#define EIC_NMICTRL_NMISENSE_Msk (0x7u << EIC_NMICTRL_NMISENSE_Pos)\r
+#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)))\r
+#define EIC_NMICTRL_NMISENSE_NONE (0x0u << 0) /**< \brief (EIC_NMICTRL) No detection */\r
+#define EIC_NMICTRL_NMISENSE_RISE (0x1u << 0) /**< \brief (EIC_NMICTRL) Rising edge detection */\r
+#define EIC_NMICTRL_NMISENSE_FALL (0x2u << 0) /**< \brief (EIC_NMICTRL) Falling edge detection */\r
+#define EIC_NMICTRL_NMISENSE_BOTH (0x3u << 0) /**< \brief (EIC_NMICTRL) Both edges detection */\r
+#define EIC_NMICTRL_NMISENSE_HIGH (0x4u << 0) /**< \brief (EIC_NMICTRL) High level detection */\r
+#define EIC_NMICTRL_NMISENSE_LOW (0x5u << 0) /**< \brief (EIC_NMICTRL) Low level detection */\r
+#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) NMI Filter Enable */\r
+#define EIC_NMICTRL_NMIFILTEN (0x1u << EIC_NMICTRL_NMIFILTEN_Pos)\r
+#define EIC_NMICTRL_MASK 0x0Fu /**< \brief (EIC_NMICTRL) MASK Register */\r
+\r
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) NMI Interrupt Flag Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t NMI:1; /*!< bit: 0 NMI Interrupt Flag */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} EIC_NMIFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) NMI Interrupt Flag Register */\r
+#define EIC_NMIFLAG_RESETVALUE 0x00 /**< \brief (EIC_NMIFLAG reset_value) NMI Interrupt Flag Register */\r
+\r
+#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) NMI Interrupt Flag */\r
+#define EIC_NMIFLAG_NMI (0x1u << EIC_NMIFLAG_NMI_Pos)\r
+#define EIC_NMIFLAG_MASK 0x01u /**< \brief (EIC_NMIFLAG) MASK Register */\r
+\r
+/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t EXTINTEO:32; /*!< bit: 0..31 External Interrupt Event Output Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EIC_EVCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control Register */\r
+#define EIC_EVCTRL_RESETVALUE 0x00000000 /**< \brief (EIC_EVCTRL reset_value) Event Control Register */\r
+\r
+#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */\r
+#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFFFFFu << EIC_EVCTRL_EXTINTEO_Pos)\r
+#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)))\r
+#define EIC_EVCTRL_MASK 0xFFFFFFFFu /**< \brief (EIC_EVCTRL) MASK Register */\r
+\r
+/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */\r
+ uint32_t :16; /*!< bit: 16..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EIC_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define EIC_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Disable */\r
+#define EIC_INTENCLR_EXTINT_Msk (0xFFFFu << EIC_INTENCLR_EXTINT_Pos)\r
+#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)))\r
+#define EIC_INTENCLR_MASK 0x0000FFFFu /**< \brief (EIC_INTENCLR) MASK Register */\r
+\r
+/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */\r
+ uint32_t :16; /*!< bit: 16..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EIC_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set Register */\r
+#define EIC_INTENSET_RESETVALUE 0x00000000 /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Disable */\r
+#define EIC_INTENSET_EXTINT_Msk (0xFFFFu << EIC_INTENSET_EXTINT_Pos)\r
+#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)))\r
+#define EIC_INTENSET_MASK 0x0000FFFFu /**< \brief (EIC_INTENSET) MASK Register */\r
+\r
+/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Flag */\r
+ uint32_t :16; /*!< bit: 16..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EIC_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define EIC_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt Flag */\r
+#define EIC_INTFLAG_EXTINT_Msk (0xFFFFu << EIC_INTFLAG_EXTINT_Pos)\r
+#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)))\r
+#define EIC_INTFLAG_MASK 0x0000FFFFu /**< \brief (EIC_INTFLAG) MASK Register */\r
+\r
+/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-up Enable Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt Wake-Up Enable */\r
+ uint32_t :16; /*!< bit: 16..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EIC_WAKEUP_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-up Enable Register */\r
+#define EIC_WAKEUP_RESETVALUE 0x00000000 /**< \brief (EIC_WAKEUP reset_value) Wake-up Enable Register */\r
+\r
+#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt Wake-Up Enable */\r
+#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFu << EIC_WAKEUP_WAKEUPEN_Pos)\r
+#define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)))\r
+#define EIC_WAKEUP_MASK 0x0000FFFFu /**< \brief (EIC_WAKEUP) MASK Register */\r
+\r
+/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Config Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */\r
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */\r
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */\r
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */\r
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */\r
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */\r
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */\r
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */\r
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */\r
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */\r
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */\r
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */\r
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */\r
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */\r
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */\r
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EIC_CONFIG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Config Register */\r
+#define EIC_CONFIG_RESETVALUE 0x00000000 /**< \brief (EIC_CONFIG reset_value) Config Register */\r
+\r
+#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */\r
+#define EIC_CONFIG_SENSE0_Msk (0x7u << EIC_CONFIG_SENSE0_Pos)\r
+#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)))\r
+#define EIC_CONFIG_SENSE0_NONE (0x0u << 0) /**< \brief (EIC_CONFIG) No detection */\r
+#define EIC_CONFIG_SENSE0_RISE (0x1u << 0) /**< \brief (EIC_CONFIG) Rising edge detection */\r
+#define EIC_CONFIG_SENSE0_FALL (0x2u << 0) /**< \brief (EIC_CONFIG) Falling edge detection */\r
+#define EIC_CONFIG_SENSE0_BOTH (0x3u << 0) /**< \brief (EIC_CONFIG) Both edges detection */\r
+#define EIC_CONFIG_SENSE0_HIGH (0x4u << 0) /**< \brief (EIC_CONFIG) High level detection */\r
+#define EIC_CONFIG_SENSE0_LOW (0x5u << 0) /**< \brief (EIC_CONFIG) Low level detection */\r
+#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */\r
+#define EIC_CONFIG_FILTEN0 (0x1u << EIC_CONFIG_FILTEN0_Pos)\r
+#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */\r
+#define EIC_CONFIG_SENSE1_Msk (0x7u << EIC_CONFIG_SENSE1_Pos)\r
+#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)))\r
+#define EIC_CONFIG_SENSE1_NONE (0x0u << 4) /**< \brief (EIC_CONFIG) No detection */\r
+#define EIC_CONFIG_SENSE1_RISE (0x1u << 4) /**< \brief (EIC_CONFIG) Rising edge detection */\r
+#define EIC_CONFIG_SENSE1_FALL (0x2u << 4) /**< \brief (EIC_CONFIG) Falling edge detection */\r
+#define EIC_CONFIG_SENSE1_BOTH (0x3u << 4) /**< \brief (EIC_CONFIG) Both edges detection */\r
+#define EIC_CONFIG_SENSE1_HIGH (0x4u << 4) /**< \brief (EIC_CONFIG) High level detection */\r
+#define EIC_CONFIG_SENSE1_LOW (0x5u << 4) /**< \brief (EIC_CONFIG) Low level detection */\r
+#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */\r
+#define EIC_CONFIG_FILTEN1 (0x1u << EIC_CONFIG_FILTEN1_Pos)\r
+#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */\r
+#define EIC_CONFIG_SENSE2_Msk (0x7u << EIC_CONFIG_SENSE2_Pos)\r
+#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)))\r
+#define EIC_CONFIG_SENSE2_NONE (0x0u << 8) /**< \brief (EIC_CONFIG) No detection */\r
+#define EIC_CONFIG_SENSE2_RISE (0x1u << 8) /**< \brief (EIC_CONFIG) Rising edge detection */\r
+#define EIC_CONFIG_SENSE2_FALL (0x2u << 8) /**< \brief (EIC_CONFIG) Falling edge detection */\r
+#define EIC_CONFIG_SENSE2_BOTH (0x3u << 8) /**< \brief (EIC_CONFIG) Both edges detection */\r
+#define EIC_CONFIG_SENSE2_HIGH (0x4u << 8) /**< \brief (EIC_CONFIG) High level detection */\r
+#define EIC_CONFIG_SENSE2_LOW (0x5u << 8) /**< \brief (EIC_CONFIG) Low level detection */\r
+#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */\r
+#define EIC_CONFIG_FILTEN2 (0x1u << EIC_CONFIG_FILTEN2_Pos)\r
+#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */\r
+#define EIC_CONFIG_SENSE3_Msk (0x7u << EIC_CONFIG_SENSE3_Pos)\r
+#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)))\r
+#define EIC_CONFIG_SENSE3_NONE (0x0u << 12) /**< \brief (EIC_CONFIG) No detection */\r
+#define EIC_CONFIG_SENSE3_RISE (0x1u << 12) /**< \brief (EIC_CONFIG) Rising edge detection */\r
+#define EIC_CONFIG_SENSE3_FALL (0x2u << 12) /**< \brief (EIC_CONFIG) Falling edge detection */\r
+#define EIC_CONFIG_SENSE3_BOTH (0x3u << 12) /**< \brief (EIC_CONFIG) Both edges detection */\r
+#define EIC_CONFIG_SENSE3_HIGH (0x4u << 12) /**< \brief (EIC_CONFIG) High level detection */\r
+#define EIC_CONFIG_SENSE3_LOW (0x5u << 12) /**< \brief (EIC_CONFIG) Low level detection */\r
+#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */\r
+#define EIC_CONFIG_FILTEN3 (0x1u << EIC_CONFIG_FILTEN3_Pos)\r
+#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */\r
+#define EIC_CONFIG_SENSE4_Msk (0x7u << EIC_CONFIG_SENSE4_Pos)\r
+#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)))\r
+#define EIC_CONFIG_SENSE4_NONE (0x0u << 16) /**< \brief (EIC_CONFIG) No detection */\r
+#define EIC_CONFIG_SENSE4_RISE (0x1u << 16) /**< \brief (EIC_CONFIG) Rising edge detection */\r
+#define EIC_CONFIG_SENSE4_FALL (0x2u << 16) /**< \brief (EIC_CONFIG) Falling edge detection */\r
+#define EIC_CONFIG_SENSE4_BOTH (0x3u << 16) /**< \brief (EIC_CONFIG) Both edges detection */\r
+#define EIC_CONFIG_SENSE4_HIGH (0x4u << 16) /**< \brief (EIC_CONFIG) High level detection */\r
+#define EIC_CONFIG_SENSE4_LOW (0x5u << 16) /**< \brief (EIC_CONFIG) Low level detection */\r
+#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */\r
+#define EIC_CONFIG_FILTEN4 (0x1u << EIC_CONFIG_FILTEN4_Pos)\r
+#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */\r
+#define EIC_CONFIG_SENSE5_Msk (0x7u << EIC_CONFIG_SENSE5_Pos)\r
+#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)))\r
+#define EIC_CONFIG_SENSE5_NONE (0x0u << 20) /**< \brief (EIC_CONFIG) No detection */\r
+#define EIC_CONFIG_SENSE5_RISE (0x1u << 20) /**< \brief (EIC_CONFIG) Rising edge detection */\r
+#define EIC_CONFIG_SENSE5_FALL (0x2u << 20) /**< \brief (EIC_CONFIG) Falling edge detection */\r
+#define EIC_CONFIG_SENSE5_BOTH (0x3u << 20) /**< \brief (EIC_CONFIG) Both edges detection */\r
+#define EIC_CONFIG_SENSE5_HIGH (0x4u << 20) /**< \brief (EIC_CONFIG) High level detection */\r
+#define EIC_CONFIG_SENSE5_LOW (0x5u << 20) /**< \brief (EIC_CONFIG) Low level detection */\r
+#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */\r
+#define EIC_CONFIG_FILTEN5 (0x1u << EIC_CONFIG_FILTEN5_Pos)\r
+#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */\r
+#define EIC_CONFIG_SENSE6_Msk (0x7u << EIC_CONFIG_SENSE6_Pos)\r
+#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)))\r
+#define EIC_CONFIG_SENSE6_NONE (0x0u << 24) /**< \brief (EIC_CONFIG) No detection */\r
+#define EIC_CONFIG_SENSE6_RISE (0x1u << 24) /**< \brief (EIC_CONFIG) Rising edge detection */\r
+#define EIC_CONFIG_SENSE6_FALL (0x2u << 24) /**< \brief (EIC_CONFIG) Falling edge detection */\r
+#define EIC_CONFIG_SENSE6_BOTH (0x3u << 24) /**< \brief (EIC_CONFIG) Both edges detection */\r
+#define EIC_CONFIG_SENSE6_HIGH (0x4u << 24) /**< \brief (EIC_CONFIG) High level detection */\r
+#define EIC_CONFIG_SENSE6_LOW (0x5u << 24) /**< \brief (EIC_CONFIG) Low level detection */\r
+#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */\r
+#define EIC_CONFIG_FILTEN6 (0x1u << EIC_CONFIG_FILTEN6_Pos)\r
+#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */\r
+#define EIC_CONFIG_SENSE7_Msk (0x7u << EIC_CONFIG_SENSE7_Pos)\r
+#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)))\r
+#define EIC_CONFIG_SENSE7_NONE (0x0u << 28) /**< \brief (EIC_CONFIG) No detection */\r
+#define EIC_CONFIG_SENSE7_RISE (0x1u << 28) /**< \brief (EIC_CONFIG) Rising edge detection */\r
+#define EIC_CONFIG_SENSE7_FALL (0x2u << 28) /**< \brief (EIC_CONFIG) Falling edge detection */\r
+#define EIC_CONFIG_SENSE7_BOTH (0x3u << 28) /**< \brief (EIC_CONFIG) Both edges detection */\r
+#define EIC_CONFIG_SENSE7_HIGH (0x4u << 28) /**< \brief (EIC_CONFIG) High level detection */\r
+#define EIC_CONFIG_SENSE7_LOW (0x5u << 28) /**< \brief (EIC_CONFIG) Low level detection */\r
+#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */\r
+#define EIC_CONFIG_FILTEN7 (0x1u << EIC_CONFIG_FILTEN7_Pos)\r
+#define EIC_CONFIG_MASK 0xFFFFFFFFu /**< \brief (EIC_CONFIG) MASK Register */\r
+\r
+/** \brief EIC hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control Register */\r
+ __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status Register */\r
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) NMI Control Register */\r
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) NMI Interrupt Flag Register */\r
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control Register */\r
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear Register */\r
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set Register */\r
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear Register */\r
+ __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-up Enable Register */\r
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Config Register [NUMBER_OF_CONFIG_REGS] */\r
+} Eic;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_EIC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for EVSYS\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_EVSYS_COMPONENT_\r
+#define _SAMD20_EVSYS_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR EVSYS */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_EVSYS Event System Interface */\r
+/*@{*/\r
+\r
+#define REV_EVSYS 0x100\r
+\r
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint8_t :3; /*!< bit: 1.. 3 Reserved */\r
+ uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Request */\r
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} EVSYS_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control Register */\r
+#define EVSYS_CTRL_RESETVALUE 0x00 /**< \brief (EVSYS_CTRL reset_value) Control Register */\r
+\r
+#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */\r
+#define EVSYS_CTRL_SWRST (0x1u << EVSYS_CTRL_SWRST_Pos)\r
+#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Request */\r
+#define EVSYS_CTRL_GCLKREQ (0x1u << EVSYS_CTRL_GCLKREQ_Pos)\r
+#define EVSYS_CTRL_MASK 0x11u /**< \brief (EVSYS_CTRL) MASK Register */\r
+\r
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t CHANNEL:8; /*!< bit: 0.. 7 Channel Selection */\r
+ uint32_t SWEVT:1; /*!< bit: 8 Software Event */\r
+ uint32_t :7; /*!< bit: 9..15 Reserved */\r
+ uint32_t EVGEN:8; /*!< bit: 16..23 Event Generator Selection */\r
+ uint32_t PATH:2; /*!< bit: 24..25 Path Selection */\r
+ uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Selection */\r
+ uint32_t :4; /*!< bit: 28..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EVSYS_CHANNEL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel Register */\r
+#define EVSYS_CHANNEL_RESETVALUE 0x00000000 /**< \brief (EVSYS_CHANNEL reset_value) Channel Register */\r
+\r
+#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */\r
+#define EVSYS_CHANNEL_CHANNEL_Msk (0xFFu << EVSYS_CHANNEL_CHANNEL_Pos)\r
+#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))\r
+#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */\r
+#define EVSYS_CHANNEL_SWEVT (0x1u << EVSYS_CHANNEL_SWEVT_Pos)\r
+#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */\r
+#define EVSYS_CHANNEL_EVGEN_Msk (0xFFu << EVSYS_CHANNEL_EVGEN_Pos)\r
+#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))\r
+#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */\r
+#define EVSYS_CHANNEL_PATH_Msk (0x3u << EVSYS_CHANNEL_PATH_Pos)\r
+#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))\r
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (0x0u << 24) /**< \brief (EVSYS_CHANNEL) Synchronous path */\r
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (0x1u << 24) /**< \brief (EVSYS_CHANNEL) Resynchronized path */\r
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (0x2u << 24) /**< \brief (EVSYS_CHANNEL) Asynchronous path */\r
+#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Selection */\r
+#define EVSYS_CHANNEL_EDGSEL_Msk (0x3u << EVSYS_CHANNEL_EDGSEL_Pos)\r
+#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))\r
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (0x0u << 26) /**< \brief (EVSYS_CHANNEL) No Event Output */\r
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (0x1u << 26) /**< \brief (EVSYS_CHANNEL) Event detection on the rising edge */\r
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (0x2u << 26) /**< \brief (EVSYS_CHANNEL) Event detection on the falling edge */\r
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGE (0x3u << 26) /**< \brief (EVSYS_CHANNEL) Event detection on both rising/falling edge */\r
+#define EVSYS_CHANNEL_MASK 0x0FFF01FFu /**< \brief (EVSYS_CHANNEL) MASK Register */\r
+\r
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Mux Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t USER:8; /*!< bit: 0.. 7 User Mux Selection */\r
+ uint16_t CHANNEL:8; /*!< bit: 8..15 Channel Event Selection */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} EVSYS_USER_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Mux Register */\r
+#define EVSYS_USER_RESETVALUE 0x0000 /**< \brief (EVSYS_USER reset_value) User Mux Register */\r
+\r
+#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Mux Selection */\r
+#define EVSYS_USER_USER_Msk (0xFFu << EVSYS_USER_USER_Pos)\r
+#define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))\r
+#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */\r
+#define EVSYS_USER_CHANNEL_Msk (0xFFu << EVSYS_USER_CHANNEL_Pos)\r
+#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))\r
+#define EVSYS_USER_MASK 0xFFFFu /**< \brief (EVSYS_USER) MASK Register */\r
+\r
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t USRRDY0:8; /*!< bit: 0.. 7 User Ready for Channels 0 to 7 (modulo 16) */\r
+ uint32_t CHBUSY0:8; /*!< bit: 8..15 Channels Busy 0 to 7 (modulo 16) */\r
+ uint32_t USRRDY1:8; /*!< bit: 16..23 User Ready for Channels 8 to 15 (modulo 16) */\r
+ uint32_t CHBUSY1:8; /*!< bit: 24..31 Channels Busy 8 to 15 (modulo 16) */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EVSYS_CHSTATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status Register */\r
+#define EVSYS_CHSTATUS_RESETVALUE 0x00000000 /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status Register */\r
+\r
+#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) User Ready for Channels 0 to 7 (modulo 16) */\r
+#define EVSYS_CHSTATUS_USRRDY0_Msk (0xFFu << EVSYS_CHSTATUS_USRRDY0_Pos)\r
+#define EVSYS_CHSTATUS_USRRDY0(value) ((EVSYS_CHSTATUS_USRRDY0_Msk & ((value) << EVSYS_CHSTATUS_USRRDY0_Pos)))\r
+#define EVSYS_CHSTATUS_USRRDY0_USRRDY0 (0x1u << 0) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 0 */\r
+#define EVSYS_CHSTATUS_USRRDY0_USRRDY1 (0x2u << 0) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 1 */\r
+#define EVSYS_CHSTATUS_USRRDY0_USRRDY2 (0x4u << 0) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 2 */\r
+#define EVSYS_CHSTATUS_USRRDY0_USRRDY3 (0x8u << 0) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 3 */\r
+#define EVSYS_CHSTATUS_USRRDY0_USRRDY4 (0x10u << 0) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 4 */\r
+#define EVSYS_CHSTATUS_USRRDY0_USRRDY5 (0x20u << 0) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 5 */\r
+#define EVSYS_CHSTATUS_USRRDY0_USRRDY6 (0x40u << 0) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 6 */\r
+#define EVSYS_CHSTATUS_USRRDY0_USRRDY7 (0x80u << 0) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 7 */\r
+#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channels Busy 0 to 7 (modulo 16) */\r
+#define EVSYS_CHSTATUS_CHBUSY0_Msk (0xFFu << EVSYS_CHSTATUS_CHBUSY0_Pos)\r
+#define EVSYS_CHSTATUS_CHBUSY0(value) ((EVSYS_CHSTATUS_CHBUSY0_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY0_Pos)))\r
+#define EVSYS_CHSTATUS_CHBUSY0_CHBUSY0 (0x1u << 8) /**< \brief (EVSYS_CHSTATUS) Channel 0 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY0_CHBUSY1 (0x2u << 8) /**< \brief (EVSYS_CHSTATUS) Channel 1 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY0_CHBUSY2 (0x4u << 8) /**< \brief (EVSYS_CHSTATUS) Channel 2 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY0_CHBUSY3 (0x8u << 8) /**< \brief (EVSYS_CHSTATUS) Channel 3 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY0_CHBUSY4 (0x10u << 8) /**< \brief (EVSYS_CHSTATUS) Channel 4 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY0_CHBUSY5 (0x20u << 8) /**< \brief (EVSYS_CHSTATUS) Channel 5 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY0_CHBUSY6 (0x40u << 8) /**< \brief (EVSYS_CHSTATUS) Channel 6 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY0_CHBUSY7 (0x80u << 8) /**< \brief (EVSYS_CHSTATUS) Channel 7 busy */\r
+#define EVSYS_CHSTATUS_USRRDY1_Pos 16 /**< \brief (EVSYS_CHSTATUS) User Ready for Channels 8 to 15 (modulo 16) */\r
+#define EVSYS_CHSTATUS_USRRDY1_Msk (0xFFu << EVSYS_CHSTATUS_USRRDY1_Pos)\r
+#define EVSYS_CHSTATUS_USRRDY1(value) ((EVSYS_CHSTATUS_USRRDY1_Msk & ((value) << EVSYS_CHSTATUS_USRRDY1_Pos)))\r
+#define EVSYS_CHSTATUS_USRRDY1_USRRDY8 (0x1u << 16) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 8 */\r
+#define EVSYS_CHSTATUS_USRRDY1_USRRDY9 (0x2u << 16) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 9 */\r
+#define EVSYS_CHSTATUS_USRRDY1_USRRDY10 (0x4u << 16) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 10 */\r
+#define EVSYS_CHSTATUS_USRRDY1_USRRDY11 (0x8u << 16) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 11 */\r
+#define EVSYS_CHSTATUS_USRRDY1_USRRDY12 (0x10u << 16) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 12 */\r
+#define EVSYS_CHSTATUS_USRRDY1_USRRDY13 (0x20u << 16) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 13 */\r
+#define EVSYS_CHSTATUS_USRRDY1_USRRDY14 (0x40u << 16) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 14 */\r
+#define EVSYS_CHSTATUS_USRRDY1_USRRDY15 (0x80u << 16) /**< \brief (EVSYS_CHSTATUS) User ready for Channel 15 */\r
+#define EVSYS_CHSTATUS_CHBUSY1_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channels Busy 8 to 15 (modulo 16) */\r
+#define EVSYS_CHSTATUS_CHBUSY1_Msk (0xFFu << EVSYS_CHSTATUS_CHBUSY1_Pos)\r
+#define EVSYS_CHSTATUS_CHBUSY1(value) ((EVSYS_CHSTATUS_CHBUSY1_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY1_Pos)))\r
+#define EVSYS_CHSTATUS_CHBUSY1_CHBUSY8 (0x1u << 24) /**< \brief (EVSYS_CHSTATUS) Channel 8 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY1_CHBUSY9 (0x2u << 24) /**< \brief (EVSYS_CHSTATUS) Channel 9 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY1_CHBUSY10 (0x4u << 24) /**< \brief (EVSYS_CHSTATUS) Channel 10 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY1_CHBUSY11 (0x8u << 24) /**< \brief (EVSYS_CHSTATUS) Channel 11 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY1_CHBUSY12 (0x10u << 24) /**< \brief (EVSYS_CHSTATUS) Channel 12 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY1_CHBUSY13 (0x20u << 24) /**< \brief (EVSYS_CHSTATUS) Channel 13 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY1_CHBUSY14 (0x40u << 24) /**< \brief (EVSYS_CHSTATUS) Channel 14 busy */\r
+#define EVSYS_CHSTATUS_CHBUSY1_CHBUSY15 (0x80u << 24) /**< \brief (EVSYS_CHSTATUS) Channel 15 busy */\r
+#define EVSYS_CHSTATUS_MASK 0xFFFFFFFFu /**< \brief (EVSYS_CHSTATUS) MASK Register */\r
+\r
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t OVR0:8; /*!< bit: 0.. 7 Overrun Interrupt Disable for Channels 0 to 7 (modulo 16) */\r
+ uint32_t EVD0:8; /*!< bit: 8..15 Event Detection Interrupt Disable for Channels 0 to 7 (modulo 16) */\r
+ uint32_t OVR1:8; /*!< bit: 16..23 Overrun Interrupt Disable for Channels 8 to 15 (modulo 16) */\r
+ uint32_t EVD1:8; /*!< bit: 24..31 Event Detection Interrupt Disable for Channels 8 to 15 (modulo 16) */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EVSYS_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define EVSYS_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Overrun Interrupt Disable for Channels 0 to 7 (modulo 16) */\r
+#define EVSYS_INTENCLR_OVR0_Msk (0xFFu << EVSYS_INTENCLR_OVR0_Pos)\r
+#define EVSYS_INTENCLR_OVR0(value) ((EVSYS_INTENCLR_OVR0_Msk & ((value) << EVSYS_INTENCLR_OVR0_Pos)))\r
+#define EVSYS_INTENCLR_OVR0_OVR0 (0x1u << 0) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 0 */\r
+#define EVSYS_INTENCLR_OVR0_OVR1 (0x2u << 0) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 1 */\r
+#define EVSYS_INTENCLR_OVR0_OVR2 (0x4u << 0) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 2 */\r
+#define EVSYS_INTENCLR_OVR0_OVR3 (0x8u << 0) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 3 */\r
+#define EVSYS_INTENCLR_OVR0_OVR4 (0x10u << 0) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 4 */\r
+#define EVSYS_INTENCLR_OVR0_OVR5 (0x20u << 0) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 5 */\r
+#define EVSYS_INTENCLR_OVR0_OVR6 (0x40u << 0) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 6 */\r
+#define EVSYS_INTENCLR_OVR0_OVR7 (0x80u << 0) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 7 */\r
+#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Event Detection Interrupt Disable for Channels 0 to 7 (modulo 16) */\r
+#define EVSYS_INTENCLR_EVD0_Msk (0xFFu << EVSYS_INTENCLR_EVD0_Pos)\r
+#define EVSYS_INTENCLR_EVD0(value) ((EVSYS_INTENCLR_EVD0_Msk & ((value) << EVSYS_INTENCLR_EVD0_Pos)))\r
+#define EVSYS_INTENCLR_EVD0_EVD0 (0x1u << 8) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 0 */\r
+#define EVSYS_INTENCLR_EVD0_EVD1 (0x2u << 8) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 1 */\r
+#define EVSYS_INTENCLR_EVD0_EVD2 (0x4u << 8) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 2 */\r
+#define EVSYS_INTENCLR_EVD0_EVD3 (0x8u << 8) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 3 */\r
+#define EVSYS_INTENCLR_EVD0_EVD4 (0x10u << 8) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 4 */\r
+#define EVSYS_INTENCLR_EVD0_EVD5 (0x20u << 8) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 5 */\r
+#define EVSYS_INTENCLR_EVD0_EVD6 (0x40u << 8) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 6 */\r
+#define EVSYS_INTENCLR_EVD0_EVD7 (0x80u << 8) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 7 */\r
+#define EVSYS_INTENCLR_OVR1_Pos 16 /**< \brief (EVSYS_INTENCLR) Overrun Interrupt Disable for Channels 8 to 15 (modulo 16) */\r
+#define EVSYS_INTENCLR_OVR1_Msk (0xFFu << EVSYS_INTENCLR_OVR1_Pos)\r
+#define EVSYS_INTENCLR_OVR1(value) ((EVSYS_INTENCLR_OVR1_Msk & ((value) << EVSYS_INTENCLR_OVR1_Pos)))\r
+#define EVSYS_INTENCLR_OVR1_OVR8 (0x1u << 16) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 8 */\r
+#define EVSYS_INTENCLR_OVR1_OVR9 (0x2u << 16) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 9 */\r
+#define EVSYS_INTENCLR_OVR1_OVR10 (0x4u << 16) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 10 */\r
+#define EVSYS_INTENCLR_OVR1_OVR11 (0x8u << 16) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 11 */\r
+#define EVSYS_INTENCLR_OVR1_OVR12 (0x10u << 16) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 12 */\r
+#define EVSYS_INTENCLR_OVR1_OVR13 (0x20u << 16) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 13 */\r
+#define EVSYS_INTENCLR_OVR1_OVR14 (0x40u << 16) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 14 */\r
+#define EVSYS_INTENCLR_OVR1_OVR15 (0x80u << 16) /**< \brief (EVSYS_INTENCLR) Overrun detected on Channel 15 */\r
+#define EVSYS_INTENCLR_EVD1_Pos 24 /**< \brief (EVSYS_INTENCLR) Event Detection Interrupt Disable for Channels 8 to 15 (modulo 16) */\r
+#define EVSYS_INTENCLR_EVD1_Msk (0xFFu << EVSYS_INTENCLR_EVD1_Pos)\r
+#define EVSYS_INTENCLR_EVD1(value) ((EVSYS_INTENCLR_EVD1_Msk & ((value) << EVSYS_INTENCLR_EVD1_Pos)))\r
+#define EVSYS_INTENCLR_EVD1_EVD8 (0x1u << 24) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 8 */\r
+#define EVSYS_INTENCLR_EVD1_EVD9 (0x2u << 24) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 9 */\r
+#define EVSYS_INTENCLR_EVD1_EVD10 (0x4u << 24) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 10 */\r
+#define EVSYS_INTENCLR_EVD1_EVD11 (0x8u << 24) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 11 */\r
+#define EVSYS_INTENCLR_EVD1_EVD12 (0x10u << 24) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 12 */\r
+#define EVSYS_INTENCLR_EVD1_EVD13 (0x20u << 24) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 13 */\r
+#define EVSYS_INTENCLR_EVD1_EVD14 (0x40u << 24) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 14 */\r
+#define EVSYS_INTENCLR_EVD1_EVD15 (0x80u << 24) /**< \brief (EVSYS_INTENCLR) Event detected on Channel 15 */\r
+#define EVSYS_INTENCLR_MASK 0xFFFFFFFFu /**< \brief (EVSYS_INTENCLR) MASK Register */\r
+\r
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t OVR0:8; /*!< bit: 0.. 7 Overrun Interrupt Enable for Channels 0 to 7 (modulo 16) */\r
+ uint32_t EVD0:8; /*!< bit: 8..15 Event Detection Interrupt Enable for Channels 0 to 7 (modulo 16) */\r
+ uint32_t OVR1:8; /*!< bit: 16..23 Overrun Interrupt Enable for Channels 8 to 15 (modulo 16) */\r
+ uint32_t EVD1:8; /*!< bit: 24..31 Event Detection Interrupt Enable for Channels 8 to 15 (modulo 16) */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EVSYS_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set Register */\r
+#define EVSYS_INTENSET_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Overrun Interrupt Enable for Channels 0 to 7 (modulo 16) */\r
+#define EVSYS_INTENSET_OVR0_Msk (0xFFu << EVSYS_INTENSET_OVR0_Pos)\r
+#define EVSYS_INTENSET_OVR0(value) ((EVSYS_INTENSET_OVR0_Msk & ((value) << EVSYS_INTENSET_OVR0_Pos)))\r
+#define EVSYS_INTENSET_OVR0_OVR0 (0x1u << 0) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 0 */\r
+#define EVSYS_INTENSET_OVR0_OVR1 (0x2u << 0) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 1 */\r
+#define EVSYS_INTENSET_OVR0_OVR2 (0x4u << 0) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 2 */\r
+#define EVSYS_INTENSET_OVR0_OVR3 (0x8u << 0) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 3 */\r
+#define EVSYS_INTENSET_OVR0_OVR4 (0x10u << 0) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 4 */\r
+#define EVSYS_INTENSET_OVR0_OVR5 (0x20u << 0) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 5 */\r
+#define EVSYS_INTENSET_OVR0_OVR6 (0x40u << 0) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 6 */\r
+#define EVSYS_INTENSET_OVR0_OVR7 (0x80u << 0) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 7 */\r
+#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Event Detection Interrupt Enable for Channels 0 to 7 (modulo 16) */\r
+#define EVSYS_INTENSET_EVD0_Msk (0xFFu << EVSYS_INTENSET_EVD0_Pos)\r
+#define EVSYS_INTENSET_EVD0(value) ((EVSYS_INTENSET_EVD0_Msk & ((value) << EVSYS_INTENSET_EVD0_Pos)))\r
+#define EVSYS_INTENSET_EVD0_EVD0 (0x1u << 8) /**< \brief (EVSYS_INTENSET) Event detected on Channel 0 */\r
+#define EVSYS_INTENSET_EVD0_EVD1 (0x2u << 8) /**< \brief (EVSYS_INTENSET) Event detected on Channel 1 */\r
+#define EVSYS_INTENSET_EVD0_EVD2 (0x4u << 8) /**< \brief (EVSYS_INTENSET) Event detected on Channel 2 */\r
+#define EVSYS_INTENSET_EVD0_EVD3 (0x8u << 8) /**< \brief (EVSYS_INTENSET) Event detected on Channel 3 */\r
+#define EVSYS_INTENSET_EVD0_EVD4 (0x10u << 8) /**< \brief (EVSYS_INTENSET) Event detected on Channel 4 */\r
+#define EVSYS_INTENSET_EVD0_EVD5 (0x20u << 8) /**< \brief (EVSYS_INTENSET) Event detected on Channel 5 */\r
+#define EVSYS_INTENSET_EVD0_EVD6 (0x40u << 8) /**< \brief (EVSYS_INTENSET) Event detected on Channel 6 */\r
+#define EVSYS_INTENSET_EVD0_EVD7 (0x80u << 8) /**< \brief (EVSYS_INTENSET) Event detected on Channel 7 */\r
+#define EVSYS_INTENSET_OVR1_Pos 16 /**< \brief (EVSYS_INTENSET) Overrun Interrupt Enable for Channels 8 to 15 (modulo 16) */\r
+#define EVSYS_INTENSET_OVR1_Msk (0xFFu << EVSYS_INTENSET_OVR1_Pos)\r
+#define EVSYS_INTENSET_OVR1(value) ((EVSYS_INTENSET_OVR1_Msk & ((value) << EVSYS_INTENSET_OVR1_Pos)))\r
+#define EVSYS_INTENSET_OVR1_OVR8 (0x1u << 16) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 8 */\r
+#define EVSYS_INTENSET_OVR1_OVR9 (0x2u << 16) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 9 */\r
+#define EVSYS_INTENSET_OVR1_OVR10 (0x4u << 16) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 10 */\r
+#define EVSYS_INTENSET_OVR1_OVR11 (0x8u << 16) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 11 */\r
+#define EVSYS_INTENSET_OVR1_OVR12 (0x10u << 16) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 12 */\r
+#define EVSYS_INTENSET_OVR1_OVR13 (0x20u << 16) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 13 */\r
+#define EVSYS_INTENSET_OVR1_OVR14 (0x40u << 16) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 14 */\r
+#define EVSYS_INTENSET_OVR1_OVR15 (0x80u << 16) /**< \brief (EVSYS_INTENSET) Overrun detected on Channel 15 */\r
+#define EVSYS_INTENSET_EVD1_Pos 24 /**< \brief (EVSYS_INTENSET) Event Detection Interrupt Enable for Channels 8 to 15 (modulo 16) */\r
+#define EVSYS_INTENSET_EVD1_Msk (0xFFu << EVSYS_INTENSET_EVD1_Pos)\r
+#define EVSYS_INTENSET_EVD1(value) ((EVSYS_INTENSET_EVD1_Msk & ((value) << EVSYS_INTENSET_EVD1_Pos)))\r
+#define EVSYS_INTENSET_EVD1_EVD8 (0x1u << 24) /**< \brief (EVSYS_INTENSET) Event detected on Channel 8 */\r
+#define EVSYS_INTENSET_EVD1_EVD9 (0x2u << 24) /**< \brief (EVSYS_INTENSET) Event detected on Channel 9 */\r
+#define EVSYS_INTENSET_EVD1_EVD10 (0x4u << 24) /**< \brief (EVSYS_INTENSET) Event detected on Channel 10 */\r
+#define EVSYS_INTENSET_EVD1_EVD11 (0x8u << 24) /**< \brief (EVSYS_INTENSET) Event detected on Channel 11 */\r
+#define EVSYS_INTENSET_EVD1_EVD12 (0x10u << 24) /**< \brief (EVSYS_INTENSET) Event detected on Channel 12 */\r
+#define EVSYS_INTENSET_EVD1_EVD13 (0x20u << 24) /**< \brief (EVSYS_INTENSET) Event detected on Channel 13 */\r
+#define EVSYS_INTENSET_EVD1_EVD14 (0x40u << 24) /**< \brief (EVSYS_INTENSET) Event detected on Channel 14 */\r
+#define EVSYS_INTENSET_EVD1_EVD15 (0x80u << 24) /**< \brief (EVSYS_INTENSET) Event detected on Channel 15 */\r
+#define EVSYS_INTENSET_MASK 0xFFFFFFFFu /**< \brief (EVSYS_INTENSET) MASK Register */\r
+\r
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t OVR0:8; /*!< bit: 0.. 7 Overrun Interrupt Flag for Channels 0 to 7 (modulo 16) */\r
+ uint32_t EVD0:8; /*!< bit: 8..15 Event Detection Interrupt Flag for Channels 0 to 7 (modulo 16) */\r
+ uint32_t OVR1:8; /*!< bit: 16..23 Overrun Interrupt Flag for Channels 8 to 15 (modulo 16) */\r
+ uint32_t EVD1:8; /*!< bit: 24..31 Event Detection Interrupt Flag for Channels 8 to 15 (modulo 16) */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} EVSYS_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define EVSYS_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Overrun Interrupt Flag for Channels 0 to 7 (modulo 16) */\r
+#define EVSYS_INTFLAG_OVR0_Msk (0xFFu << EVSYS_INTFLAG_OVR0_Pos)\r
+#define EVSYS_INTFLAG_OVR0(value) ((EVSYS_INTFLAG_OVR0_Msk & ((value) << EVSYS_INTFLAG_OVR0_Pos)))\r
+#define EVSYS_INTFLAG_OVR0_OVR0 (0x1u << 0) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 0 */\r
+#define EVSYS_INTFLAG_OVR0_OVR1 (0x2u << 0) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 1 */\r
+#define EVSYS_INTFLAG_OVR0_OVR2 (0x4u << 0) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 2 */\r
+#define EVSYS_INTFLAG_OVR0_OVR3 (0x8u << 0) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 3 */\r
+#define EVSYS_INTFLAG_OVR0_OVR4 (0x10u << 0) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 4 */\r
+#define EVSYS_INTFLAG_OVR0_OVR5 (0x20u << 0) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 5 */\r
+#define EVSYS_INTFLAG_OVR0_OVR6 (0x40u << 0) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 6 */\r
+#define EVSYS_INTFLAG_OVR0_OVR7 (0x80u << 0) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 7 */\r
+#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Event Detection Interrupt Flag for Channels 0 to 7 (modulo 16) */\r
+#define EVSYS_INTFLAG_EVD0_Msk (0xFFu << EVSYS_INTFLAG_EVD0_Pos)\r
+#define EVSYS_INTFLAG_EVD0(value) ((EVSYS_INTFLAG_EVD0_Msk & ((value) << EVSYS_INTFLAG_EVD0_Pos)))\r
+#define EVSYS_INTFLAG_EVD0_EVD0 (0x1u << 8) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 0 */\r
+#define EVSYS_INTFLAG_EVD0_EVD1 (0x2u << 8) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 1 */\r
+#define EVSYS_INTFLAG_EVD0_EVD2 (0x4u << 8) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 2 */\r
+#define EVSYS_INTFLAG_EVD0_EVD3 (0x8u << 8) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 3 */\r
+#define EVSYS_INTFLAG_EVD0_EVD4 (0x10u << 8) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 4 */\r
+#define EVSYS_INTFLAG_EVD0_EVD5 (0x20u << 8) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 5 */\r
+#define EVSYS_INTFLAG_EVD0_EVD6 (0x40u << 8) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 6 */\r
+#define EVSYS_INTFLAG_EVD0_EVD7 (0x80u << 8) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 7 */\r
+#define EVSYS_INTFLAG_OVR1_Pos 16 /**< \brief (EVSYS_INTFLAG) Overrun Interrupt Flag for Channels 8 to 15 (modulo 16) */\r
+#define EVSYS_INTFLAG_OVR1_Msk (0xFFu << EVSYS_INTFLAG_OVR1_Pos)\r
+#define EVSYS_INTFLAG_OVR1(value) ((EVSYS_INTFLAG_OVR1_Msk & ((value) << EVSYS_INTFLAG_OVR1_Pos)))\r
+#define EVSYS_INTFLAG_OVR1_OVR8 (0x1u << 16) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 8 */\r
+#define EVSYS_INTFLAG_OVR1_OVR9 (0x2u << 16) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 9 */\r
+#define EVSYS_INTFLAG_OVR1_OVR10 (0x4u << 16) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 10 */\r
+#define EVSYS_INTFLAG_OVR1_OVR11 (0x8u << 16) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 11 */\r
+#define EVSYS_INTFLAG_OVR1_OVR12 (0x10u << 16) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 12 */\r
+#define EVSYS_INTFLAG_OVR1_OVR13 (0x20u << 16) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 13 */\r
+#define EVSYS_INTFLAG_OVR1_OVR14 (0x40u << 16) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 14 */\r
+#define EVSYS_INTFLAG_OVR1_OVR15 (0x80u << 16) /**< \brief (EVSYS_INTFLAG) Overrun detected on Channel 15 */\r
+#define EVSYS_INTFLAG_EVD1_Pos 24 /**< \brief (EVSYS_INTFLAG) Event Detection Interrupt Flag for Channels 8 to 15 (modulo 16) */\r
+#define EVSYS_INTFLAG_EVD1_Msk (0xFFu << EVSYS_INTFLAG_EVD1_Pos)\r
+#define EVSYS_INTFLAG_EVD1(value) ((EVSYS_INTFLAG_EVD1_Msk & ((value) << EVSYS_INTFLAG_EVD1_Pos)))\r
+#define EVSYS_INTFLAG_EVD1_EVD8 (0x1u << 24) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 8 */\r
+#define EVSYS_INTFLAG_EVD1_EVD9 (0x2u << 24) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 9 */\r
+#define EVSYS_INTFLAG_EVD1_EVD10 (0x4u << 24) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 10 */\r
+#define EVSYS_INTFLAG_EVD1_EVD11 (0x8u << 24) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 11 */\r
+#define EVSYS_INTFLAG_EVD1_EVD12 (0x10u << 24) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 12 */\r
+#define EVSYS_INTFLAG_EVD1_EVD13 (0x20u << 24) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 13 */\r
+#define EVSYS_INTFLAG_EVD1_EVD14 (0x40u << 24) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 14 */\r
+#define EVSYS_INTFLAG_EVD1_EVD15 (0x80u << 24) /**< \brief (EVSYS_INTFLAG) Event detected on Channel 15 */\r
+#define EVSYS_INTFLAG_MASK 0xFFFFFFFFu /**< \brief (EVSYS_INTFLAG) MASK Register */\r
+\r
+/** \brief EVSYS hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control Register */\r
+ RoReg8 Reserved1[0x3];\r
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel Register */\r
+ __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Mux Register */\r
+ RoReg8 Reserved2[0x2];\r
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status Register */\r
+ __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear Register */\r
+ __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set Register */\r
+ __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear Register */\r
+} Evsys;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_EVSYS_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for GCLK\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_GCLK_COMPONENT_\r
+#define _SAMD20_GCLK_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR GCLK */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_GCLK Generic Clock Generator */\r
+/*@{*/\r
+\r
+#define REV_GCLK 0x200\r
+\r
+/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} GCLK_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control Register */\r
+#define GCLK_CTRL_RESETVALUE 0x00 /**< \brief (GCLK_CTRL reset_value) Control Register */\r
+\r
+#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */\r
+#define GCLK_CTRL_SWRST (0x1u << GCLK_CTRL_SWRST_Pos)\r
+#define GCLK_CTRL_MASK 0x01u /**< \brief (GCLK_CTRL) MASK Register */\r
+\r
+/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */\r
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} GCLK_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status Register */\r
+#define GCLK_STATUS_RESETVALUE 0x00 /**< \brief (GCLK_STATUS reset_value) Status Register */\r
+\r
+#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy */\r
+#define GCLK_STATUS_SYNCBUSY (0x1u << GCLK_STATUS_SYNCBUSY_Pos)\r
+#define GCLK_STATUS_MASK 0x80u /**< \brief (GCLK_STATUS) MASK Register */\r
+\r
+/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection */\r
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */\r
+ uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator Select */\r
+ uint16_t :2; /*!< bit: 12..13 Reserved */\r
+ uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */\r
+ uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} GCLK_CLKCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control Register */\r
+#define GCLK_CLKCTRL_RESETVALUE 0x0000 /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control Register */\r
+\r
+#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection */\r
+#define GCLK_CLKCTRL_ID_Msk (0x3Fu << GCLK_CLKCTRL_ID_Pos)\r
+#define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))\r
+#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator Select */\r
+#define GCLK_CLKCTRL_GEN_Msk (0xFu << GCLK_CLKCTRL_GEN_Pos)\r
+#define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))\r
+#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */\r
+#define GCLK_CLKCTRL_CLKEN (0x1u << GCLK_CLKCTRL_CLKEN_Pos)\r
+#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */\r
+#define GCLK_CLKCTRL_WRTLOCK (0x1u << GCLK_CLKCTRL_WRTLOCK_Pos)\r
+#define GCLK_CLKCTRL_MASK 0xCF3Fu /**< \brief (GCLK_CLKCTRL) MASK Register */\r
+\r
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */\r
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */\r
+ uint32_t SRC:5; /*!< bit: 8..12 Clock Source Select */\r
+ uint32_t :3; /*!< bit: 13..15 Reserved */\r
+ uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */\r
+ uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */\r
+ uint32_t OOV:1; /*!< bit: 18 Output Off Value */\r
+ uint32_t OE:1; /*!< bit: 19 Output Enable */\r
+ uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 21 Run during Standby */\r
+ uint32_t :10; /*!< bit: 22..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} GCLK_GENCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control Register */\r
+#define GCLK_GENCTRL_RESETVALUE 0x00000000 /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control Register */\r
+\r
+#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */\r
+#define GCLK_GENCTRL_ID_Msk (0xFu << GCLK_GENCTRL_ID_Pos)\r
+#define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))\r
+#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Clock Source Select */\r
+#define GCLK_GENCTRL_SRC_Msk (0x1Fu << GCLK_GENCTRL_SRC_Pos)\r
+#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))\r
+#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */\r
+#define GCLK_GENCTRL_GENEN (0x1u << GCLK_GENCTRL_GENEN_Pos)\r
+#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */\r
+#define GCLK_GENCTRL_IDC (0x1u << GCLK_GENCTRL_IDC_Pos)\r
+#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */\r
+#define GCLK_GENCTRL_OOV (0x1u << GCLK_GENCTRL_OOV_Pos)\r
+#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */\r
+#define GCLK_GENCTRL_OE (0x1u << GCLK_GENCTRL_OE_Pos)\r
+#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */\r
+#define GCLK_GENCTRL_DIVSEL (0x1u << GCLK_GENCTRL_DIVSEL_Pos)\r
+#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run during Standby */\r
+#define GCLK_GENCTRL_RUNSTDBY (0x1u << GCLK_GENCTRL_RUNSTDBY_Pos)\r
+#define GCLK_GENCTRL_MASK 0x003F1F0Fu /**< \brief (GCLK_GENCTRL) MASK Register */\r
+\r
+/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */\r
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */\r
+ uint32_t DIV:16; /*!< bit: 8..23 Division Factor */\r
+ uint32_t :8; /*!< bit: 24..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} GCLK_GENDIV_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division Register */\r
+#define GCLK_GENDIV_RESETVALUE 0x00000000 /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division Register */\r
+\r
+#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */\r
+#define GCLK_GENDIV_ID_Msk (0xFu << GCLK_GENDIV_ID_Pos)\r
+#define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))\r
+#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */\r
+#define GCLK_GENDIV_DIV_Msk (0xFFFFu << GCLK_GENDIV_DIV_Pos)\r
+#define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))\r
+#define GCLK_GENDIV_MASK 0x00FFFF0Fu /**< \brief (GCLK_GENDIV) MASK Register */\r
+\r
+/** \brief GCLK hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control Register */\r
+ __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status Register */\r
+ __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control Register */\r
+ __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control Register */\r
+ __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division Register */\r
+} Gclk;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_GCLK_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for NVMCTRL\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_NVMCTRL_COMPONENT_\r
+#define _SAMD20_NVMCTRL_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR NVMCTRL */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_NVMCTRL Non-Volatile Memory Controller */\r
+/*@{*/\r
+\r
+#define REV_NVMCTRL 0x102\r
+\r
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) NVM Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */\r
+ uint16_t :1; /*!< bit: 7 Reserved */\r
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} NVMCTRL_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) NVM Control Register A */\r
+#define NVMCTRL_CTRLA_RESETVALUE 0x0000 /**< \brief (NVMCTRL_CTRLA reset_value) NVM Control Register A */\r
+\r
+#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */\r
+#define NVMCTRL_CTRLA_CMD_Msk (0x7Fu << NVMCTRL_CTRLA_CMD_Pos)\r
+#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)))\r
+#define NVMCTRL_CTRLA_CMD_ER (0x2u << 0) /**< \brief (NVMCTRL_CTRLA) Erase Row */\r
+#define NVMCTRL_CTRLA_CMD_WP (0x4u << 0) /**< \brief (NVMCTRL_CTRLA) Write Page */\r
+#define NVMCTRL_CTRLA_CMD_EAR (0x5u << 0) /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row */\r
+#define NVMCTRL_CTRLA_CMD_WAP (0x6u << 0) /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Row */\r
+#define NVMCTRL_CTRLA_CMD_SF (0xAu << 0) /**< \brief (NVMCTRL_CTRLA) Security Flow Command */\r
+#define NVMCTRL_CTRLA_CMD_WL (0xFu << 0) /**< \brief (NVMCTRL_CTRLA) Write lockbits */\r
+#define NVMCTRL_CTRLA_CMD_LR (0x40u << 0) /**< \brief (NVMCTRL_CTRLA) Lock Region */\r
+#define NVMCTRL_CTRLA_CMD_UR (0x41u << 0) /**< \brief (NVMCTRL_CTRLA) Unlock Region */\r
+#define NVMCTRL_CTRLA_CMD_SPRM (0x42u << 0) /**< \brief (NVMCTRL_CTRLA) Set Power Reduction Mode */\r
+#define NVMCTRL_CTRLA_CMD_CPRM (0x43u << 0) /**< \brief (NVMCTRL_CTRLA) Clear Power Reduction Mode */\r
+#define NVMCTRL_CTRLA_CMD_PBC (0x44u << 0) /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear */\r
+#define NVMCTRL_CTRLA_CMD_SSB (0x45u << 0) /**< \brief (NVMCTRL_CTRLA) Set Security Bit */\r
+#define NVMCTRL_CTRLA_CMD_SMR (0x54u << 0) /**< \brief (NVMCTRL_CTRLA) State Machine Reset */\r
+#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */\r
+#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFu << NVMCTRL_CTRLA_CMDEX_Pos)\r
+#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)))\r
+#define NVMCTRL_CTRLA_CMDEX_KEY (0xA5u << 8) /**< \brief (NVMCTRL_CTRLA) Execution Key */\r
+#define NVMCTRL_CTRLA_MASK 0xFF7Fu /**< \brief (NVMCTRL_CTRLA) MASK Register */\r
+\r
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) NVM Control Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :1; /*!< bit: 0 Reserved */\r
+ uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */\r
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */\r
+ uint32_t MANW:1; /*!< bit: 7 Manual Write */\r
+ uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */\r
+ uint32_t :6; /*!< bit: 10..15 Reserved */\r
+ uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */\r
+ uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */\r
+ uint32_t :13; /*!< bit: 19..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} NVMCTRL_CTRLB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) NVM Control Register B */\r
+#define NVMCTRL_CTRLB_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_CTRLB reset_value) NVM Control Register B */\r
+\r
+#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */\r
+#define NVMCTRL_CTRLB_RWS_Msk (0xFu << NVMCTRL_CTRLB_RWS_Pos)\r
+#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)))\r
+#define NVMCTRL_CTRLB_RWS_SINGLE (0x0u << 1) /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */\r
+#define NVMCTRL_CTRLB_RWS_HALF (0x1u << 1) /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */\r
+#define NVMCTRL_CTRLB_RWS_DUAL (0x2u << 1) /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */\r
+#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */\r
+#define NVMCTRL_CTRLB_MANW (0x1u << NVMCTRL_CTRLB_MANW_Pos)\r
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */\r
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3u << NVMCTRL_CTRLB_SLEEPPRM_Pos)\r
+#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)))\r
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (0x0u << 8) /**< \brief (NVMCTRL_CTRLB) Wake on first access. */\r
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (0x1u << 8) /**< \brief (NVMCTRL_CTRLB) Wake on sleep exit. */\r
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (0x3u << 8) /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */\r
+#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */\r
+#define NVMCTRL_CTRLB_READMODE_Msk (0x3u << NVMCTRL_CTRLB_READMODE_Pos)\r
+#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)))\r
+#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */\r
+#define NVMCTRL_CTRLB_CACHEDIS (0x1u << NVMCTRL_CTRLB_CACHEDIS_Pos)\r
+#define NVMCTRL_CTRLB_MASK 0x0007039Eu /**< \brief (NVMCTRL_CTRLB) MASK Register */\r
+\r
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) Parameter Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */\r
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */\r
+ uint32_t :13; /*!< bit: 19..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} NVMCTRL_PARAM_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) Parameter Register */\r
+#define NVMCTRL_PARAM_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_PARAM reset_value) Parameter Register */\r
+\r
+#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */\r
+#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFu << NVMCTRL_PARAM_NVMP_Pos)\r
+#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)))\r
+#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */\r
+#define NVMCTRL_PARAM_PSZ_Msk (0x7u << NVMCTRL_PARAM_PSZ_Pos)\r
+#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)))\r
+#define NVMCTRL_PARAM_MASK 0x0007FFFFu /**< \brief (NVMCTRL_PARAM) MASK Register */\r
+\r
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Disable */\r
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Disable */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} NVMCTRL_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Disable */\r
+#define NVMCTRL_INTENCLR_READY (0x1u << NVMCTRL_INTENCLR_READY_Pos)\r
+#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Disable */\r
+#define NVMCTRL_INTENCLR_ERROR (0x1u << NVMCTRL_INTENCLR_ERROR_Pos)\r
+#define NVMCTRL_INTENCLR_MASK 0x03u /**< \brief (NVMCTRL_INTENCLR) MASK Register */\r
+\r
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */\r
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} NVMCTRL_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set Register */\r
+#define NVMCTRL_INTENSET_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */\r
+#define NVMCTRL_INTENSET_READY (0x1u << NVMCTRL_INTENSET_READY_Pos)\r
+#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */\r
+#define NVMCTRL_INTENSET_ERROR (0x1u << NVMCTRL_INTENSET_ERROR_Pos)\r
+#define NVMCTRL_INTENSET_MASK 0x03u /**< \brief (NVMCTRL_INTENSET) MASK Register */\r
+\r
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Flag */\r
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Flag */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} NVMCTRL_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define NVMCTRL_INTFLAG_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready Interrupt Flag */\r
+#define NVMCTRL_INTFLAG_READY (0x1u << NVMCTRL_INTFLAG_READY_Pos)\r
+#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error Interrupt Flag */\r
+#define NVMCTRL_INTFLAG_ERROR (0x1u << NVMCTRL_INTFLAG_ERROR_Pos)\r
+#define NVMCTRL_INTFLAG_MASK 0x03u /**< \brief (NVMCTRL_INTFLAG) MASK Register */\r
+\r
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */\r
+ uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */\r
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */\r
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */\r
+ uint16_t NVME:1; /*!< bit: 4 NVM Error */\r
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */\r
+ uint16_t SB:1; /*!< bit: 8 Security Bit Status */\r
+ uint16_t :7; /*!< bit: 9..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} NVMCTRL_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status Register */\r
+#define NVMCTRL_STATUS_RESETVALUE 0x0000 /**< \brief (NVMCTRL_STATUS reset_value) Status Register */\r
+\r
+#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */\r
+#define NVMCTRL_STATUS_PRM (0x1u << NVMCTRL_STATUS_PRM_Pos)\r
+#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */\r
+#define NVMCTRL_STATUS_LOAD (0x1u << NVMCTRL_STATUS_LOAD_Pos)\r
+#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */\r
+#define NVMCTRL_STATUS_PROGE (0x1u << NVMCTRL_STATUS_PROGE_Pos)\r
+#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */\r
+#define NVMCTRL_STATUS_LOCKE (0x1u << NVMCTRL_STATUS_LOCKE_Pos)\r
+#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */\r
+#define NVMCTRL_STATUS_NVME (0x1u << NVMCTRL_STATUS_NVME_Pos)\r
+#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */\r
+#define NVMCTRL_STATUS_SB (0x1u << NVMCTRL_STATUS_SB_Pos)\r
+#define NVMCTRL_STATUS_MASK 0x011Fu /**< \brief (NVMCTRL_STATUS) MASK Register */\r
+\r
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */\r
+ uint32_t :10; /*!< bit: 22..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} NVMCTRL_ADDR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address Register */\r
+#define NVMCTRL_ADDR_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_ADDR reset_value) Address Register */\r
+\r
+#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */\r
+#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFu << NVMCTRL_ADDR_ADDR_Pos)\r
+#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)))\r
+#define NVMCTRL_ADDR_MASK 0x003FFFFFu /**< \brief (NVMCTRL_ADDR) MASK Register */\r
+\r
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} NVMCTRL_LOCK_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Register */\r
+#define NVMCTRL_LOCK_RESETVALUE 0x0000 /**< \brief (NVMCTRL_LOCK reset_value) Lock Register */\r
+\r
+#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */\r
+#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFu << NVMCTRL_LOCK_LOCK_Pos)\r
+#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)))\r
+#define NVMCTRL_LOCK_MASK 0xFFFFu /**< \brief (NVMCTRL_LOCK) MASK Register */\r
+\r
+/** \brief NVMCTRL hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) NVM Control Register A */\r
+ RoReg8 Reserved1[0x2];\r
+ __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) NVM Control Register B */\r
+ __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) Parameter Register */\r
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear Register */\r
+ RoReg8 Reserved2[0x3];\r
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set Register */\r
+ RoReg8 Reserved3[0x3];\r
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved4[0x3];\r
+ __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status Register */\r
+ RoReg8 Reserved5[0x2];\r
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address Register */\r
+ __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Register */\r
+} Nvmctrl;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */\r
+/* ************************************************************************** */\r
+/** \addtogroup fuses_api Peripheral Software API */\r
+/*@{*/\r
+\r
+\r
+#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)\r
+#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */\r
+#define ADC_FUSES_BIASCAL_Msk (0x7u << ADC_FUSES_BIASCAL_Pos)\r
+#define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)))\r
+\r
+#define ADC_FUSES_BIAS_OPA_ADDR (NVMCTRL_OTP2 + 4)\r
+#define ADC_FUSES_BIAS_OPA_Pos 19 /**< \brief (NVMCTRL_OTP2) ADC OPA Bias */\r
+#define ADC_FUSES_BIAS_OPA_Msk (0x1u << ADC_FUSES_BIAS_OPA_Pos)\r
+\r
+#define ADC_FUSES_BOOSTEN_ADDR (NVMCTRL_OTP2 + 4)\r
+#define ADC_FUSES_BOOSTEN_Pos 17 /**< \brief (NVMCTRL_OTP2) ADC Boost Enable */\r
+#define ADC_FUSES_BOOSTEN_Msk (0x1u << ADC_FUSES_BOOSTEN_Pos)\r
+\r
+#define ADC_FUSES_CMPDELAY_ADDR (NVMCTRL_OTP2 + 4)\r
+#define ADC_FUSES_CMPDELAY_Pos 16 /**< \brief (NVMCTRL_OTP2) ADC Comparator Delay */\r
+#define ADC_FUSES_CMPDELAY_Msk (0x1u << ADC_FUSES_CMPDELAY_Pos)\r
+\r
+#define ADC_FUSES_DCFG_ADDR (NVMCTRL_OTP2 + 4)\r
+#define ADC_FUSES_DCFG_Pos 16 /**< \brief (NVMCTRL_OTP2) ADC Device Configuration */\r
+#define ADC_FUSES_DCFG_Msk (0xFu << ADC_FUSES_DCFG_Pos)\r
+#define ADC_FUSES_DCFG(value) ((ADC_FUSES_DCFG_Msk & ((value) << ADC_FUSES_DCFG_Pos)))\r
+\r
+#define ADC_FUSES_GAINCORR_ADDR NVMCTRL_OTP4\r
+#define ADC_FUSES_GAINCORR_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Gain Correction */\r
+#define ADC_FUSES_GAINCORR_Msk (0xFFFu << ADC_FUSES_GAINCORR_Pos)\r
+#define ADC_FUSES_GAINCORR(value) ((ADC_FUSES_GAINCORR_Msk & ((value) << ADC_FUSES_GAINCORR_Pos)))\r
+\r
+#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4\r
+#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */\r
+#define ADC_FUSES_LINEARITY_0_Msk (0x1Fu << ADC_FUSES_LINEARITY_0_Pos)\r
+#define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)))\r
+\r
+#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)\r
+#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */\r
+#define ADC_FUSES_LINEARITY_1_Msk (0x7u << ADC_FUSES_LINEARITY_1_Pos)\r
+#define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)))\r
+\r
+#define ADC_FUSES_OFFSETCORR_ADDR NVMCTRL_OTP4\r
+#define ADC_FUSES_OFFSETCORR_Pos 15 /**< \brief (NVMCTRL_OTP4) ADC Offset Correction */\r
+#define ADC_FUSES_OFFSETCORR_Msk (0xFFFu << ADC_FUSES_OFFSETCORR_Pos)\r
+#define ADC_FUSES_OFFSETCORR(value) ((ADC_FUSES_OFFSETCORR_Msk & ((value) << ADC_FUSES_OFFSETCORR_Pos)))\r
+\r
+#define ADC_FUSES_VCMPULSE_ADDR (NVMCTRL_OTP2 + 4)\r
+#define ADC_FUSES_VCMPULSE_Pos 18 /**< \brief (NVMCTRL_OTP2) ADC VCM Pulse */\r
+#define ADC_FUSES_VCMPULSE_Msk (0x1u << ADC_FUSES_VCMPULSE_Pos)\r
+\r
+#define DSU_FUSES_DCFG0_ADDR NVMCTRL_OTP2\r
+#define DSU_FUSES_DCFG0_Pos 0 /**< \brief (NVMCTRL_OTP2) Device Configuration 0 */\r
+#define DSU_FUSES_DCFG0_Msk (0xFFFFFFFFu << DSU_FUSES_DCFG0_Pos)\r
+#define DSU_FUSES_DCFG0(value) ((DSU_FUSES_DCFG0_Msk & ((value) << DSU_FUSES_DCFG0_Pos)))\r
+\r
+#define DSU_FUSES_DCFG1_ADDR (NVMCTRL_OTP2 + 4)\r
+#define DSU_FUSES_DCFG1_Pos 0 /**< \brief (NVMCTRL_OTP2) Device Configuration 1 */\r
+#define DSU_FUSES_DCFG1_Msk (0xFFFFFFFFu << DSU_FUSES_DCFG1_Pos)\r
+#define DSU_FUSES_DCFG1(value) ((DSU_FUSES_DCFG1_Msk & ((value) << DSU_FUSES_DCFG1_Pos)))\r
+\r
+#define DSU_FUSES_DEV_FAMILY_CFG_0_ADDR NVMCTRL_OTP2\r
+#define DSU_FUSES_DEV_FAMILY_CFG_0_Pos 5 /**< \brief (NVMCTRL_OTP2) Device Family Configuration bits 26:0 */\r
+#define DSU_FUSES_DEV_FAMILY_CFG_0_Msk (0x7FFFFFFu << DSU_FUSES_DEV_FAMILY_CFG_0_Pos)\r
+#define DSU_FUSES_DEV_FAMILY_CFG_0(value) ((DSU_FUSES_DEV_FAMILY_CFG_0_Msk & ((value) << DSU_FUSES_DEV_FAMILY_CFG_0_Pos)))\r
+\r
+#define DSU_FUSES_DEV_FAMILY_CFG_1_ADDR (NVMCTRL_OTP2 + 4)\r
+#define DSU_FUSES_DEV_FAMILY_CFG_1_Pos 0 /**< \brief (NVMCTRL_OTP2) Device Family Configuration bits 42:27 */\r
+#define DSU_FUSES_DEV_FAMILY_CFG_1_Msk (0xFFFFu << DSU_FUSES_DEV_FAMILY_CFG_1_Pos)\r
+#define DSU_FUSES_DEV_FAMILY_CFG_1(value) ((DSU_FUSES_DEV_FAMILY_CFG_1_Msk & ((value) << DSU_FUSES_DEV_FAMILY_CFG_1_Pos)))\r
+\r
+#define DSU_FUSES_DID_DEVSEL_ADDR NVMCTRL_OTP2\r
+#define DSU_FUSES_DID_DEVSEL_Pos 0 /**< \brief (NVMCTRL_OTP2) Device Number */\r
+#define DSU_FUSES_DID_DEVSEL_Msk (0x1Fu << DSU_FUSES_DID_DEVSEL_Pos)\r
+#define DSU_FUSES_DID_DEVSEL(value) ((DSU_FUSES_DID_DEVSEL_Msk & ((value) << DSU_FUSES_DID_DEVSEL_Pos)))\r
+\r
+#define DSU_FUSES_RAM_BIAS_ADDR (NVMCTRL_OTP2 + 4)\r
+#define DSU_FUSES_RAM_BIAS_Pos 20 /**< \brief (NVMCTRL_OTP2) RAM Bias */\r
+#define DSU_FUSES_RAM_BIAS_Msk (0x3u << DSU_FUSES_RAM_BIAS_Pos)\r
+#define DSU_FUSES_RAM_BIAS(value) ((DSU_FUSES_RAM_BIAS_Msk & ((value) << DSU_FUSES_RAM_BIAS_Pos)))\r
+\r
+#define DSU_FUSES_RAM_READ_MARGIN_ADDR (NVMCTRL_OTP2 + 4)\r
+#define DSU_FUSES_RAM_READ_MARGIN_Pos 22 /**< \brief (NVMCTRL_OTP2) RAM Read Margin */\r
+#define DSU_FUSES_RAM_READ_MARGIN_Msk (0xFu << DSU_FUSES_RAM_READ_MARGIN_Pos)\r
+#define DSU_FUSES_RAM_READ_MARGIN(value) ((DSU_FUSES_RAM_READ_MARGIN_Msk & ((value) << DSU_FUSES_RAM_READ_MARGIN_Pos)))\r
+\r
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER\r
+#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */\r
+#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7u << NVMCTRL_FUSES_BOOTPROT_Pos)\r
+#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)))\r
+\r
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER\r
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */\r
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7u << NVMCTRL_FUSES_EEPROM_SIZE_Pos)\r
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)))\r
+\r
+#define NVMCTRL_FUSES_LOCKFIELD_ADDR NVMCTRL_LOCKBIT\r
+#define NVMCTRL_FUSES_LOCKFIELD_Pos 0 /**< \brief (NVMCTRL_LOCKBIT) LOCK Region */\r
+#define NVMCTRL_FUSES_LOCKFIELD_Msk (0xFFu << NVMCTRL_FUSES_LOCKFIELD_Pos)\r
+#define NVMCTRL_FUSES_LOCKFIELD(value) ((NVMCTRL_FUSES_LOCKFIELD_Msk & ((value) << NVMCTRL_FUSES_LOCKFIELD_Pos)))\r
+\r
+#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1\r
+#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */\r
+#define NVMCTRL_FUSES_NVMP_Msk (0xFFFFu << NVMCTRL_FUSES_NVMP_Pos)\r
+#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)))\r
+\r
+#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1\r
+#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */\r
+#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFu << NVMCTRL_FUSES_NVM_LOCK_Pos)\r
+#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)))\r
+\r
+#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1\r
+#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */\r
+#define NVMCTRL_FUSES_PSZ_Msk (0xFu << NVMCTRL_FUSES_PSZ_Pos)\r
+#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)))\r
+\r
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)\r
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */\r
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFu << NVMCTRL_FUSES_REGION_LOCKS_Pos)\r
+#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)))\r
+\r
+#define SYSCTRL_FUSES_OSC32KCAL_ADDR (NVMCTRL_OTP4 + 4)\r
+#define SYSCTRL_FUSES_OSC32KCAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */\r
+#define SYSCTRL_FUSES_OSC32KCAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32KCAL_Pos)\r
+#define SYSCTRL_FUSES_OSC32KCAL(value) ((SYSCTRL_FUSES_OSC32KCAL_Msk & ((value) << SYSCTRL_FUSES_OSC32KCAL_Pos)))\r
+\r
+#define SYSCTRL_FUSES_BOD12USERLEVEL_ADDR NVMCTRL_USER\r
+#define SYSCTRL_FUSES_BOD12USERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BOD12 User Level */\r
+#define SYSCTRL_FUSES_BOD12USERLEVEL_Msk (0x1Fu << SYSCTRL_FUSES_BOD12USERLEVEL_Pos)\r
+#define SYSCTRL_FUSES_BOD12USERLEVEL(value) ((SYSCTRL_FUSES_BOD12USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD12USERLEVEL_Pos)))\r
+\r
+#define SYSCTRL_FUSES_BOD12_ACTION_ADDR NVMCTRL_USER\r
+#define SYSCTRL_FUSES_BOD12_ACTION_Pos 23 /**< \brief (NVMCTRL_USER) BOD12 Action */\r
+#define SYSCTRL_FUSES_BOD12_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD12_ACTION_Pos)\r
+#define SYSCTRL_FUSES_BOD12_ACTION(value) ((SYSCTRL_FUSES_BOD12_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD12_ACTION_Pos)))\r
+\r
+#define SYSCTRL_FUSES_BOD12_EN_ADDR NVMCTRL_USER\r
+#define SYSCTRL_FUSES_BOD12_EN_Pos 22 /**< \brief (NVMCTRL_USER) BOD12 Enable */\r
+#define SYSCTRL_FUSES_BOD12_EN_Msk (0x1u << SYSCTRL_FUSES_BOD12_EN_Pos)\r
+\r
+#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER\r
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */\r
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)\r
+#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))\r
+\r
+#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER\r
+#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */\r
+#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)\r
+#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))\r
+\r
+#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER\r
+#define SYSCTRL_FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */\r
+#define SYSCTRL_FUSES_BOD33_EN_Msk (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)\r
+\r
+#define SYSCTRL_FUSES_ULPVREG_ADDR NVMCTRL_OTP4\r
+#define SYSCTRL_FUSES_ULPVREG_Pos 0 /**< \brief (NVMCTRL_OTP4) ULP Regulator Fallback Mode */\r
+#define SYSCTRL_FUSES_ULPVREG_Msk (0x7u << SYSCTRL_FUSES_ULPVREG_Pos)\r
+#define SYSCTRL_FUSES_ULPVREG(value) ((SYSCTRL_FUSES_ULPVREG_Msk & ((value) << SYSCTRL_FUSES_ULPVREG_Pos)))\r
+\r
+#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER\r
+#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */\r
+#define WDT_FUSES_ALWAYSON_Msk (0x1u << WDT_FUSES_ALWAYSON_Pos)\r
+\r
+#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER\r
+#define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */\r
+#define WDT_FUSES_ENABLE_Msk (0x1u << WDT_FUSES_ENABLE_Pos)\r
+\r
+#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)\r
+#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */\r
+#define WDT_FUSES_EWOFFSET_Msk (0xFu << WDT_FUSES_EWOFFSET_Pos)\r
+#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)))\r
+\r
+#define WDT_FUSES_PER_ADDR NVMCTRL_USER\r
+#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */\r
+#define WDT_FUSES_PER_Msk (0xFu << WDT_FUSES_PER_Pos)\r
+#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)))\r
+\r
+#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)\r
+#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */\r
+#define WDT_FUSES_WEN_Msk (0x1u << WDT_FUSES_WEN_Pos)\r
+\r
+#define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER\r
+#define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */\r
+#define WDT_FUSES_WINDOW_0_Msk (0x1u << WDT_FUSES_WINDOW_0_Pos)\r
+\r
+#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)\r
+#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */\r
+#define WDT_FUSES_WINDOW_1_Msk (0x7u << WDT_FUSES_WINDOW_1_Pos)\r
+#define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)))\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_NVMCTRL_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for PAC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_PAC_COMPONENT_\r
+#define _SAMD20_PAC_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR PAC */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_PAC Peripheral Access Controller */\r
+/*@{*/\r
+\r
+#define REV_PAC 0x101\r
+\r
+/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :1; /*!< bit: 0 Reserved */\r
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PAC_WPCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear Register */\r
+#define PAC_WPCLR_RESETVALUE 0x00000000 /**< \brief (PAC_WPCLR reset_value) Write Protection Clear Register */\r
+\r
+#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */\r
+#define PAC_WPCLR_WP_Msk (0x7FFFFFFFu << PAC_WPCLR_WP_Pos)\r
+#define PAC_WPCLR_WP(value) ((PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)))\r
+#define PAC_WPCLR_MASK 0xFFFFFFFEu /**< \brief (PAC_WPCLR) MASK Register */\r
+\r
+/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :1; /*!< bit: 0 Reserved */\r
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PAC_WPSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set Register */\r
+#define PAC_WPSET_RESETVALUE 0x00000000 /**< \brief (PAC_WPSET reset_value) Write Protection Set Register */\r
+\r
+#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */\r
+#define PAC_WPSET_WP_Msk (0x7FFFFFFFu << PAC_WPSET_WP_Pos)\r
+#define PAC_WPSET_WP(value) ((PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)))\r
+#define PAC_WPSET_MASK 0xFFFFFFFEu /**< \brief (PAC_WPSET) MASK Register */\r
+\r
+/** \brief PAC hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear Register */\r
+ __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set Register */\r
+} Pac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_PAC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for PM\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_PM_COMPONENT_\r
+#define _SAMD20_PM_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR PM */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_PM Power Manager */\r
+/*@{*/\r
+\r
+#define REV_PM 0x200\r
+\r
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */\r
+ uint8_t CFDEN:1; /*!< bit: 2 Clock Failure Detector Enable */\r
+ uint8_t :1; /*!< bit: 3 Reserved */\r
+ uint8_t BKUPCLK:1; /*!< bit: 4 Backup Clock Select */\r
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control Register */\r
+#define PM_CTRL_RESETVALUE 0x00 /**< \brief (PM_CTRL reset_value) Control Register */\r
+\r
+#define PM_CTRL_CFDEN_Pos 2 /**< \brief (PM_CTRL) Clock Failure Detector Enable */\r
+#define PM_CTRL_CFDEN (0x1u << PM_CTRL_CFDEN_Pos)\r
+#define PM_CTRL_BKUPCLK_Pos 4 /**< \brief (PM_CTRL) Backup Clock Select */\r
+#define PM_CTRL_BKUPCLK (0x1u << PM_CTRL_BKUPCLK_Pos)\r
+#define PM_CTRL_MASK 0x14u /**< \brief (PM_CTRL) MASK Register */\r
+\r
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Level */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_SLEEP_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Register */\r
+#define PM_SLEEP_RESETVALUE 0x00 /**< \brief (PM_SLEEP reset_value) Sleep Register */\r
+\r
+#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Level */\r
+#define PM_SLEEP_IDLE_Msk (0x3u << PM_SLEEP_IDLE_Pos)\r
+#define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))\r
+#define PM_SLEEP_MASK 0x03u /**< \brief (PM_SLEEP) MASK Register */\r
+\r
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Clock Select */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_CPUSEL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */\r
+#define PM_CPUSEL_RESETVALUE 0x00 /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */\r
+\r
+#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Clock Select */\r
+#define PM_CPUSEL_CPUDIV_Msk (0x7u << PM_CPUSEL_CPUDIV_Pos)\r
+#define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))\r
+#define PM_CPUSEL_MASK 0x07u /**< \brief (PM_CPUSEL) MASK Register */\r
+\r
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Clock Select */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_APBASEL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */\r
+#define PM_APBASEL_RESETVALUE 0x00 /**< \brief (PM_APBASEL reset_value) APBA Clock Select */\r
+\r
+#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Clock Select */\r
+#define PM_APBASEL_APBADIV_Msk (0x7u << PM_APBASEL_APBADIV_Pos)\r
+#define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))\r
+#define PM_APBASEL_MASK 0x07u /**< \brief (PM_APBASEL) MASK Register */\r
+\r
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t APBBDIV:3; /*!< bit: 0.. 2 PB Clock Select */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_APBBSEL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */\r
+#define PM_APBBSEL_RESETVALUE 0x00 /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */\r
+\r
+#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) PB Clock Select */\r
+#define PM_APBBSEL_APBBDIV_Msk (0x7u << PM_APBBSEL_APBBDIV_Pos)\r
+#define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))\r
+#define PM_APBBSEL_MASK 0x07u /**< \brief (PM_APBBSEL) MASK Register */\r
+\r
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Clock Select */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_APBCSEL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */\r
+#define PM_APBCSEL_RESETVALUE 0x00 /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */\r
+\r
+#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Clock Select */\r
+#define PM_APBCSEL_APBCDIV_Msk (0x7u << PM_APBCSEL_APBCDIV_Pos)\r
+#define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))\r
+#define PM_APBCSEL_MASK 0x07u /**< \brief (PM_APBCSEL) MASK Register */\r
+\r
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t HPB0:1; /*!< bit: 0 HPB0 AHB Clock Mask */\r
+ uint32_t HPB1:1; /*!< bit: 1 HPB1 AHB Clock Mask */\r
+ uint32_t HPB2:1; /*!< bit: 2 HPB2 AHB Clock Mask */\r
+ uint32_t DSU:1; /*!< bit: 3 DSU AHB Clock Mask */\r
+ uint32_t NVMCTRL:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */\r
+ uint32_t :27; /*!< bit: 5..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PM_AHBMASK_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */\r
+#define PM_AHBMASK_RESETVALUE 0x0000001F /**< \brief (PM_AHBMASK reset_value) AHB Mask */\r
+\r
+#define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */\r
+#define PM_AHBMASK_HPB0 (0x1u << PM_AHBMASK_HPB0_Pos)\r
+#define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */\r
+#define PM_AHBMASK_HPB1 (0x1u << PM_AHBMASK_HPB1_Pos)\r
+#define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */\r
+#define PM_AHBMASK_HPB2 (0x1u << PM_AHBMASK_HPB2_Pos)\r
+#define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */\r
+#define PM_AHBMASK_DSU (0x1u << PM_AHBMASK_DSU_Pos)\r
+#define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */\r
+#define PM_AHBMASK_NVMCTRL (0x1u << PM_AHBMASK_NVMCTRL_Pos)\r
+#define PM_AHBMASK_MASK 0x0000001Fu /**< \brief (PM_AHBMASK) MASK Register */\r
+\r
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PAC0:1; /*!< bit: 0 PAC0 APB Clock Mask */\r
+ uint32_t PM:1; /*!< bit: 1 PM APB Clock Mask */\r
+ uint32_t SYSCTRL:1; /*!< bit: 2 SYSCTRL APB Clock Mask */\r
+ uint32_t GCLK:1; /*!< bit: 3 GCLK APB Clock Mask */\r
+ uint32_t WDT:1; /*!< bit: 4 WDT APB Clock Mask */\r
+ uint32_t RTC:1; /*!< bit: 5 RTC APB Clock Mask */\r
+ uint32_t EIC:1; /*!< bit: 6 EIC APB Clock Mask */\r
+ uint32_t :25; /*!< bit: 7..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PM_APBAMASK_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */\r
+#define PM_APBAMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBAMASK reset_value) APBA Mask */\r
+\r
+#define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Mask */\r
+#define PM_APBAMASK_PAC0 (0x1u << PM_APBAMASK_PAC0_Pos)\r
+#define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Mask */\r
+#define PM_APBAMASK_PM (0x1u << PM_APBAMASK_PM_Pos)\r
+#define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Mask */\r
+#define PM_APBAMASK_SYSCTRL (0x1u << PM_APBAMASK_SYSCTRL_Pos)\r
+#define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Mask */\r
+#define PM_APBAMASK_GCLK (0x1u << PM_APBAMASK_GCLK_Pos)\r
+#define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Mask */\r
+#define PM_APBAMASK_WDT (0x1u << PM_APBAMASK_WDT_Pos)\r
+#define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Mask */\r
+#define PM_APBAMASK_RTC (0x1u << PM_APBAMASK_RTC_Pos)\r
+#define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Mask */\r
+#define PM_APBAMASK_EIC (0x1u << PM_APBAMASK_EIC_Pos)\r
+#define PM_APBAMASK_MASK 0x0000007Fu /**< \brief (PM_APBAMASK) MASK Register */\r
+\r
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PAC1:1; /*!< bit: 0 PAC1 APB Clock Mask */\r
+ uint32_t DSU:1; /*!< bit: 1 DSU APB Clock Mask */\r
+ uint32_t NVMCTRL:1; /*!< bit: 2 NVMCTRL APB Clock Mask */\r
+ uint32_t PORT:1; /*!< bit: 3 PORT APB Clock Mask */\r
+ uint32_t :28; /*!< bit: 4..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PM_APBBMASK_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */\r
+#define PM_APBBMASK_RESETVALUE 0x0000001F /**< \brief (PM_APBBMASK reset_value) APBB Mask */\r
+\r
+#define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Mask */\r
+#define PM_APBBMASK_PAC1 (0x1u << PM_APBBMASK_PAC1_Pos)\r
+#define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Mask */\r
+#define PM_APBBMASK_DSU (0x1u << PM_APBBMASK_DSU_Pos)\r
+#define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Mask */\r
+#define PM_APBBMASK_NVMCTRL (0x1u << PM_APBBMASK_NVMCTRL_Pos)\r
+#define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Mask */\r
+#define PM_APBBMASK_PORT (0x1u << PM_APBBMASK_PORT_Pos)\r
+#define PM_APBBMASK_MASK 0x0000000Fu /**< \brief (PM_APBBMASK) MASK Register */\r
+\r
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PAC2:1; /*!< bit: 0 PAC2 APB Clock Mask */\r
+ uint32_t EVSYS:1; /*!< bit: 1 EVSYS APB Clock Mask */\r
+ uint32_t SERCOM0:1; /*!< bit: 2 SERCOM0 APB Clock Mask */\r
+ uint32_t SERCOM1:1; /*!< bit: 3 SERCOM1 APB Clock Mask */\r
+ uint32_t SERCOM2:1; /*!< bit: 4 SERCOM2 APB Clock Mask */\r
+ uint32_t SERCOM3:1; /*!< bit: 5 SERCOM3 APB Clock Mask */\r
+ uint32_t SERCOM4:1; /*!< bit: 6 SERCOM4 APB Clock Mask */\r
+ uint32_t SERCOM5:1; /*!< bit: 7 SERCOM5 APB Clock Mask */\r
+ uint32_t TC0:1; /*!< bit: 8 TC0 APB Clock Mask */\r
+ uint32_t TC1:1; /*!< bit: 9 TC1 APB Clock Mask */\r
+ uint32_t TC2:1; /*!< bit: 10 TC2 APB Clock Mask */\r
+ uint32_t TC3:1; /*!< bit: 11 TC3 APB Clock Mask */\r
+ uint32_t TC4:1; /*!< bit: 12 TC4 APB Clock Mask */\r
+ uint32_t TC5:1; /*!< bit: 13 TC5 APB Clock Mask */\r
+ uint32_t TC6:1; /*!< bit: 14 TC6 APB Clock Mask */\r
+ uint32_t TC7:1; /*!< bit: 15 TC7 APB Clock Mask */\r
+ uint32_t ADC:1; /*!< bit: 16 ADC APB Clock Mask */\r
+ uint32_t AC:1; /*!< bit: 17 AC APB Clock Mask */\r
+ uint32_t DAC:1; /*!< bit: 18 DAC APB Clock Mask */\r
+ uint32_t :13; /*!< bit: 19..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PM_APBCMASK_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */\r
+#define PM_APBCMASK_RESETVALUE 0x00010000 /**< \brief (PM_APBCMASK reset_value) APBC Mask */\r
+\r
+#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Mask */\r
+#define PM_APBCMASK_PAC2 (0x1u << PM_APBCMASK_PAC2_Pos)\r
+#define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Mask */\r
+#define PM_APBCMASK_EVSYS (0x1u << PM_APBCMASK_EVSYS_Pos)\r
+#define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Mask */\r
+#define PM_APBCMASK_SERCOM0 (0x1u << PM_APBCMASK_SERCOM0_Pos)\r
+#define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Mask */\r
+#define PM_APBCMASK_SERCOM1 (0x1u << PM_APBCMASK_SERCOM1_Pos)\r
+#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Mask */\r
+#define PM_APBCMASK_SERCOM2 (0x1u << PM_APBCMASK_SERCOM2_Pos)\r
+#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Mask */\r
+#define PM_APBCMASK_SERCOM3 (0x1u << PM_APBCMASK_SERCOM3_Pos)\r
+#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Mask */\r
+#define PM_APBCMASK_SERCOM4 (0x1u << PM_APBCMASK_SERCOM4_Pos)\r
+#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Mask */\r
+#define PM_APBCMASK_SERCOM5 (0x1u << PM_APBCMASK_SERCOM5_Pos)\r
+#define PM_APBCMASK_TC0_Pos 8 /**< \brief (PM_APBCMASK) TC0 APB Clock Mask */\r
+#define PM_APBCMASK_TC0 (0x1u << PM_APBCMASK_TC0_Pos)\r
+#define PM_APBCMASK_TC1_Pos 9 /**< \brief (PM_APBCMASK) TC1 APB Clock Mask */\r
+#define PM_APBCMASK_TC1 (0x1u << PM_APBCMASK_TC1_Pos)\r
+#define PM_APBCMASK_TC2_Pos 10 /**< \brief (PM_APBCMASK) TC2 APB Clock Mask */\r
+#define PM_APBCMASK_TC2 (0x1u << PM_APBCMASK_TC2_Pos)\r
+#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Mask */\r
+#define PM_APBCMASK_TC3 (0x1u << PM_APBCMASK_TC3_Pos)\r
+#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Mask */\r
+#define PM_APBCMASK_TC4 (0x1u << PM_APBCMASK_TC4_Pos)\r
+#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Mask */\r
+#define PM_APBCMASK_TC5 (0x1u << PM_APBCMASK_TC5_Pos)\r
+#define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Mask */\r
+#define PM_APBCMASK_TC6 (0x1u << PM_APBCMASK_TC6_Pos)\r
+#define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Mask */\r
+#define PM_APBCMASK_TC7 (0x1u << PM_APBCMASK_TC7_Pos)\r
+#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Mask */\r
+#define PM_APBCMASK_ADC (0x1u << PM_APBCMASK_ADC_Pos)\r
+#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Mask */\r
+#define PM_APBCMASK_AC (0x1u << PM_APBCMASK_AC_Pos)\r
+#define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Mask */\r
+#define PM_APBCMASK_DAC (0x1u << PM_APBCMASK_DAC_Pos)\r
+#define PM_APBCMASK_MASK 0x0007FFFFu /**< \brief (PM_APBCMASK) MASK Register */\r
+\r
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable Clear */\r
+ uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector Enable Clear */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define PM_INTENCLR_RESETVALUE 0x00 /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable Clear */\r
+#define PM_INTENCLR_CKRDY (0x1u << PM_INTENCLR_CKRDY_Pos)\r
+#define PM_INTENCLR_CFD_Pos 1 /**< \brief (PM_INTENCLR) Clock Failure Detector Enable Clear */\r
+#define PM_INTENCLR_CFD (0x1u << PM_INTENCLR_CFD_Pos)\r
+#define PM_INTENCLR_MASK 0x03u /**< \brief (PM_INTENCLR) MASK Register */\r
+\r
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable Set */\r
+ uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector Enable Set */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set Register */\r
+#define PM_INTENSET_RESETVALUE 0x00 /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable Set */\r
+#define PM_INTENSET_CKRDY (0x1u << PM_INTENSET_CKRDY_Pos)\r
+#define PM_INTENSET_CFD_Pos 1 /**< \brief (PM_INTENSET) Clock Failure Detector Enable Set */\r
+#define PM_INTENSET_CFD (0x1u << PM_INTENSET_CFD_Pos)\r
+#define PM_INTENSET_MASK 0x03u /**< \brief (PM_INTENSET) MASK Register */\r
+\r
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt */\r
+ uint8_t CFD:1; /*!< bit: 1 Clock Failure Detectore Interrupt */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define PM_INTFLAG_RESETVALUE 0x00 /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready Interrupt */\r
+#define PM_INTFLAG_CKRDY (0x1u << PM_INTFLAG_CKRDY_Pos)\r
+#define PM_INTFLAG_CFD_Pos 1 /**< \brief (PM_INTFLAG) Clock Failure Detectore Interrupt */\r
+#define PM_INTFLAG_CFD (0x1u << PM_INTFLAG_CFD_Pos)\r
+#define PM_INTFLAG_MASK 0x03u /**< \brief (PM_INTFLAG) MASK Register */\r
+\r
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t POR:1; /*!< bit: 0 Power-on Reset */\r
+ uint8_t BOD12:1; /*!< bit: 1 Brown-out 1.2V Reset */\r
+ uint8_t BOD33:1; /*!< bit: 2 Brown-out 3.3V Reset */\r
+ uint8_t :1; /*!< bit: 3 Reserved */\r
+ uint8_t EXT:1; /*!< bit: 4 External Reset Pin */\r
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */\r
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */\r
+ uint8_t :1; /*!< bit: 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PM_RCAUSE_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause Register */\r
+#define PM_RCAUSE_RESETVALUE 0x01 /**< \brief (PM_RCAUSE reset_value) Reset Cause Register */\r
+\r
+#define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power-on Reset */\r
+#define PM_RCAUSE_POR (0x1u << PM_RCAUSE_POR_Pos)\r
+#define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown-out 1.2V Reset */\r
+#define PM_RCAUSE_BOD12 (0x1u << PM_RCAUSE_BOD12_Pos)\r
+#define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown-out 3.3V Reset */\r
+#define PM_RCAUSE_BOD33 (0x1u << PM_RCAUSE_BOD33_Pos)\r
+#define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset Pin */\r
+#define PM_RCAUSE_EXT (0x1u << PM_RCAUSE_EXT_Pos)\r
+#define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */\r
+#define PM_RCAUSE_WDT (0x1u << PM_RCAUSE_WDT_Pos)\r
+#define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */\r
+#define PM_RCAUSE_SYST (0x1u << PM_RCAUSE_SYST_Pos)\r
+#define PM_RCAUSE_MASK 0x77u /**< \brief (PM_RCAUSE) MASK Register */\r
+\r
+/** \brief PM hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control Register */\r
+ __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Register */\r
+ RoReg8 Reserved1[0x6];\r
+ __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */\r
+ __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */\r
+ __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */\r
+ __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */\r
+ RoReg8 Reserved2[0x8];\r
+ __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */\r
+ __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */\r
+ __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */\r
+ __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */\r
+ RoReg8 Reserved3[0x10];\r
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear Register */\r
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set Register */\r
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved4[0x1];\r
+ __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause Register */\r
+} Pm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_PM_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for PORT\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_PORT_COMPONENT_\r
+#define _SAMD20_PORT_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR PORT */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_PORT Port Module */\r
+/*@{*/\r
+\r
+#define REV_PORT 0x100\r
+\r
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_DIR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction Register */\r
+#define PORT_DIR_RESETVALUE 0x00000000 /**< \brief (PORT_DIR reset_value) Data Direction Register */\r
+\r
+#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */\r
+#define PORT_DIR_DIR_Msk (0xFFFFFFFFu << PORT_DIR_DIR_Pos)\r
+#define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))\r
+#define PORT_DIR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIR) MASK Register */\r
+\r
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_DIRCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear Register */\r
+#define PORT_DIRCLR_RESETVALUE 0x00000000 /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear Register */\r
+\r
+#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */\r
+#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFu << PORT_DIRCLR_DIRCLR_Pos)\r
+#define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))\r
+#define PORT_DIRCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRCLR) MASK Register */\r
+\r
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_DIRSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set Register */\r
+#define PORT_DIRSET_RESETVALUE 0x00000000 /**< \brief (PORT_DIRSET reset_value) Data Direction Set Register */\r
+\r
+#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */\r
+#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFu << PORT_DIRSET_DIRSET_Pos)\r
+#define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))\r
+#define PORT_DIRSET_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRSET) MASK Register */\r
+\r
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_DIRTGL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle Register */\r
+#define PORT_DIRTGL_RESETVALUE 0x00000000 /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle Register */\r
+\r
+#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */\r
+#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFu << PORT_DIRTGL_DIRTGL_Pos)\r
+#define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))\r
+#define PORT_DIRTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRTGL) MASK Register */\r
+\r
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_OUT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value Register */\r
+#define PORT_OUT_RESETVALUE 0x00000000 /**< \brief (PORT_OUT reset_value) Data Output Value Register */\r
+\r
+#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */\r
+#define PORT_OUT_OUT_Msk (0xFFFFFFFFu << PORT_OUT_OUT_Pos)\r
+#define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))\r
+#define PORT_OUT_MASK 0xFFFFFFFFu /**< \brief (PORT_OUT) MASK Register */\r
+\r
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_OUTCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear Register */\r
+#define PORT_OUTCLR_RESETVALUE 0x00000000 /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear Register */\r
+\r
+#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */\r
+#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFu << PORT_OUTCLR_OUTCLR_Pos)\r
+#define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))\r
+#define PORT_OUTCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTCLR) MASK Register */\r
+\r
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_OUTSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set Register */\r
+#define PORT_OUTSET_RESETVALUE 0x00000000 /**< \brief (PORT_OUTSET reset_value) Data Output Value Set Register */\r
+\r
+#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */\r
+#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFu << PORT_OUTSET_OUTSET_Pos)\r
+#define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))\r
+#define PORT_OUTSET_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTSET) MASK Register */\r
+\r
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_OUTTGL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle Register */\r
+#define PORT_OUTTGL_RESETVALUE 0x00000000 /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle Register */\r
+\r
+#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */\r
+#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFu << PORT_OUTTGL_OUTTGL_Pos)\r
+#define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))\r
+#define PORT_OUTTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTTGL) MASK Register */\r
+\r
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_IN_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value Register */\r
+#define PORT_IN_RESETVALUE 0x00000000 /**< \brief (PORT_IN reset_value) Data Input Value Register */\r
+\r
+#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */\r
+#define PORT_IN_IN_Msk (0xFFFFFFFFu << PORT_IN_IN_Pos)\r
+#define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))\r
+#define PORT_IN_MASK 0xFFFFFFFFu /**< \brief (PORT_IN) MASK Register */\r
+\r
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control Register */\r
+#define PORT_CTRL_RESETVALUE 0x00000000 /**< \brief (PORT_CTRL reset_value) Control Register */\r
+\r
+#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */\r
+#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFu << PORT_CTRL_SAMPLING_Pos)\r
+#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))\r
+#define PORT_CTRL_MASK 0xFFFFFFFFu /**< \brief (PORT_CTRL) MASK Register */\r
+\r
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */\r
+ uint32_t PMUXEN:1; /*!< bit: 16 Select Peripheral Multiplexer */\r
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */\r
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */\r
+ uint32_t ODRAIN:1; /*!< bit: 19 Open Drain Output */\r
+ uint32_t SLEWLIM:1; /*!< bit: 20 Output Driver Slew Rate Limit Enable */\r
+ uint32_t :1; /*!< bit: 21 Reserved */\r
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */\r
+ uint32_t :1; /*!< bit: 23 Reserved */\r
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing Template */\r
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX Registers */\r
+ uint32_t :1; /*!< bit: 29 Reserved */\r
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG Registers */\r
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} PORT_WRCONFIG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration Register */\r
+#define PORT_WRCONFIG_RESETVALUE 0x00000000 /**< \brief (PORT_WRCONFIG reset_value) Write Configuration Register */\r
+\r
+#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */\r
+#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFu << PORT_WRCONFIG_PINMASK_Pos)\r
+#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))\r
+#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Select Peripheral Multiplexer */\r
+#define PORT_WRCONFIG_PMUXEN (0x1u << PORT_WRCONFIG_PMUXEN_Pos)\r
+#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */\r
+#define PORT_WRCONFIG_INEN (0x1u << PORT_WRCONFIG_INEN_Pos)\r
+#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */\r
+#define PORT_WRCONFIG_PULLEN (0x1u << PORT_WRCONFIG_PULLEN_Pos)\r
+#define PORT_WRCONFIG_ODRAIN_Pos 19 /**< \brief (PORT_WRCONFIG) Open Drain Output */\r
+#define PORT_WRCONFIG_ODRAIN (0x1u << PORT_WRCONFIG_ODRAIN_Pos)\r
+#define PORT_WRCONFIG_SLEWLIM_Pos 20 /**< \brief (PORT_WRCONFIG) Output Driver Slew Rate Limit Enable */\r
+#define PORT_WRCONFIG_SLEWLIM (0x1u << PORT_WRCONFIG_SLEWLIM_Pos)\r
+#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */\r
+#define PORT_WRCONFIG_DRVSTR (0x1u << PORT_WRCONFIG_DRVSTR_Pos)\r
+#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing Template */\r
+#define PORT_WRCONFIG_PMUX_Msk (0xFu << PORT_WRCONFIG_PMUX_Pos)\r
+#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))\r
+#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX Registers */\r
+#define PORT_WRCONFIG_WRPMUX (0x1u << PORT_WRCONFIG_WRPMUX_Pos)\r
+#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG Registers */\r
+#define PORT_WRCONFIG_WRPINCFG (0x1u << PORT_WRCONFIG_WRPINCFG_Pos)\r
+#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */\r
+#define PORT_WRCONFIG_HWSEL (0x1u << PORT_WRCONFIG_HWSEL_Pos)\r
+#define PORT_WRCONFIG_MASK 0xDF5FFFFFu /**< \brief (PORT_WRCONFIG) MASK Register */\r
+\r
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */\r
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PORT_PMUX_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing Register */\r
+#define PORT_PMUX_RESETVALUE 0x00 /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing Register */\r
+\r
+#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */\r
+#define PORT_PMUX_PMUXE_Msk (0xFu << PORT_PMUX_PMUXE_Pos)\r
+#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))\r
+#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */\r
+#define PORT_PMUX_PMUXO_Msk (0xFu << PORT_PMUX_PMUXO_Pos)\r
+#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))\r
+#define PORT_PMUX_MASK 0xFFu /**< \brief (PORT_PMUX) MASK Register */\r
+\r
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t PMUXEN:1; /*!< bit: 0 Select Peripheral Multiplexer */\r
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */\r
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */\r
+ uint8_t ODRAIN:1; /*!< bit: 3 Open Drain Output */\r
+ uint8_t SLEWLIM:1; /*!< bit: 4 Output Driver Slew Rate Limit Enable */\r
+ uint8_t :1; /*!< bit: 5 Reserved */\r
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */\r
+ uint8_t :1; /*!< bit: 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} PORT_PINCFG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration Register */\r
+#define PORT_PINCFG_RESETVALUE 0x00 /**< \brief (PORT_PINCFG reset_value) Pin Configuration Register */\r
+\r
+#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Select Peripheral Multiplexer */\r
+#define PORT_PINCFG_PMUXEN (0x1u << PORT_PINCFG_PMUXEN_Pos)\r
+#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */\r
+#define PORT_PINCFG_INEN (0x1u << PORT_PINCFG_INEN_Pos)\r
+#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */\r
+#define PORT_PINCFG_PULLEN (0x1u << PORT_PINCFG_PULLEN_Pos)\r
+#define PORT_PINCFG_ODRAIN_Pos 3 /**< \brief (PORT_PINCFG) Open Drain Output */\r
+#define PORT_PINCFG_ODRAIN (0x1u << PORT_PINCFG_ODRAIN_Pos)\r
+#define PORT_PINCFG_SLEWLIM_Pos 4 /**< \brief (PORT_PINCFG) Output Driver Slew Rate Limit Enable */\r
+#define PORT_PINCFG_SLEWLIM (0x1u << PORT_PINCFG_SLEWLIM_Pos)\r
+#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */\r
+#define PORT_PINCFG_DRVSTR (0x1u << PORT_PINCFG_DRVSTR_Pos)\r
+#define PORT_PINCFG_MASK 0x5Fu /**< \brief (PORT_PINCFG) MASK Register */\r
+\r
+/** \brief PortGroup hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction Register */\r
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear Register */\r
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set Register */\r
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle Register */\r
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value Register */\r
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear Register */\r
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set Register */\r
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle Register */\r
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value Register */\r
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control Register */\r
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration Register */\r
+ RoReg8 Reserved1[0x4];\r
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing Register */\r
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration Register */\r
+ RoReg8 Reserved2[0x20];\r
+} PortGroup;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief PORT hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */\r
+} Port;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_PORT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for RTC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_RTC_COMPONENT_\r
+#define _SAMD20_RTC_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR RTC */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_RTC Real-Time Counter */\r
+/*@{*/\r
+\r
+#define REV_RTC 0x101\r
+\r
+/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint16_t MODE:2; /*!< bit: 2.. 3 Mode */\r
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */\r
+ uint16_t MATCHCLR:1; /*!< bit: 7 Match Clears Counter */\r
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */\r
+ uint16_t :4; /*!< bit: 12..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE0_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control Register */\r
+#define RTC_MODE0_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control Register */\r
+\r
+#define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */\r
+#define RTC_MODE0_CTRL_SWRST (0x1u << RTC_MODE0_CTRL_SWRST_Pos)\r
+#define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */\r
+#define RTC_MODE0_CTRL_ENABLE (0x1u << RTC_MODE0_CTRL_ENABLE_Pos)\r
+#define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Mode */\r
+#define RTC_MODE0_CTRL_MODE_Msk (0x3u << RTC_MODE0_CTRL_MODE_Pos)\r
+#define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)))\r
+#define RTC_MODE0_CTRL_MODE_COUNT32 (0x0u << 2) /**< \brief (RTC_MODE0_CTRL) Mode 0 */\r
+#define RTC_MODE0_CTRL_MODE_COUNT16 (0x1u << 2) /**< \brief (RTC_MODE0_CTRL) Mode 1 */\r
+#define RTC_MODE0_CTRL_MODE_CLOCK (0x2u << 2) /**< \brief (RTC_MODE0_CTRL) Mode 2 */\r
+#define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Match Clears Counter */\r
+#define RTC_MODE0_CTRL_MATCHCLR (0x1u << RTC_MODE0_CTRL_MATCHCLR_Pos)\r
+#define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */\r
+#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFu << RTC_MODE0_CTRL_PRESCALER_Pos)\r
+#define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)))\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV1 (0x0u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV2 (0x1u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV4 (0x2u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV8 (0x3u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV16 (0x4u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV32 (0x5u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV64 (0x6u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV128 (0x7u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV256 (0x8u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV512 (0x9u << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (0xAu << 8) /**< \brief (RTC_MODE0_CTRL) */\r
+#define RTC_MODE0_CTRL_MASK 0x0F8Fu /**< \brief (RTC_MODE0_CTRL) MASK Register */\r
+\r
+/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint16_t MODE:2; /*!< bit: 2.. 3 Mode */\r
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */\r
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */\r
+ uint16_t :4; /*!< bit: 12..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE1_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control Register */\r
+#define RTC_MODE1_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control Register */\r
+\r
+#define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */\r
+#define RTC_MODE1_CTRL_SWRST (0x1u << RTC_MODE1_CTRL_SWRST_Pos)\r
+#define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */\r
+#define RTC_MODE1_CTRL_ENABLE (0x1u << RTC_MODE1_CTRL_ENABLE_Pos)\r
+#define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Mode */\r
+#define RTC_MODE1_CTRL_MODE_Msk (0x3u << RTC_MODE1_CTRL_MODE_Pos)\r
+#define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)))\r
+#define RTC_MODE1_CTRL_MODE_COUNT32 (0x0u << 2) /**< \brief (RTC_MODE1_CTRL) Mode 0 */\r
+#define RTC_MODE1_CTRL_MODE_COUNT16 (0x1u << 2) /**< \brief (RTC_MODE1_CTRL) Mode 1 */\r
+#define RTC_MODE1_CTRL_MODE_CLOCK (0x2u << 2) /**< \brief (RTC_MODE1_CTRL) Mode 2 */\r
+#define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */\r
+#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFu << RTC_MODE1_CTRL_PRESCALER_Pos)\r
+#define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)))\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV1 (0x0u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV2 (0x1u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV4 (0x2u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV8 (0x3u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV16 (0x4u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV32 (0x5u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV64 (0x6u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV128 (0x7u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV256 (0x8u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV512 (0x9u << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (0xAu << 8) /**< \brief (RTC_MODE1_CTRL) */\r
+#define RTC_MODE1_CTRL_MASK 0x0F0Fu /**< \brief (RTC_MODE1_CTRL) MASK Register */\r
+\r
+/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint16_t MODE:2; /*!< bit: 2.. 3 Mode */\r
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */\r
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */\r
+ uint16_t MATCHCLR:1; /*!< bit: 7 Match Clears Counter */\r
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */\r
+ uint16_t :4; /*!< bit: 12..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE2_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control Register */\r
+#define RTC_MODE2_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control Register */\r
+\r
+#define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */\r
+#define RTC_MODE2_CTRL_SWRST (0x1u << RTC_MODE2_CTRL_SWRST_Pos)\r
+#define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */\r
+#define RTC_MODE2_CTRL_ENABLE (0x1u << RTC_MODE2_CTRL_ENABLE_Pos)\r
+#define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Mode */\r
+#define RTC_MODE2_CTRL_MODE_Msk (0x3u << RTC_MODE2_CTRL_MODE_Pos)\r
+#define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)))\r
+#define RTC_MODE2_CTRL_MODE_COUNT32 (0x0u << 2) /**< \brief (RTC_MODE2_CTRL) Mode 0 */\r
+#define RTC_MODE2_CTRL_MODE_COUNT16 (0x1u << 2) /**< \brief (RTC_MODE2_CTRL) Mode 1 */\r
+#define RTC_MODE2_CTRL_MODE_CLOCK (0x2u << 2) /**< \brief (RTC_MODE2_CTRL) Mode 2 */\r
+#define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */\r
+#define RTC_MODE2_CTRL_CLKREP (0x1u << RTC_MODE2_CTRL_CLKREP_Pos)\r
+#define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Match Clears Counter */\r
+#define RTC_MODE2_CTRL_MATCHCLR (0x1u << RTC_MODE2_CTRL_MATCHCLR_Pos)\r
+#define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */\r
+#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFu << RTC_MODE2_CTRL_PRESCALER_Pos)\r
+#define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)))\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV1 (0x0u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV2 (0x1u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV4 (0x2u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV8 (0x3u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV16 (0x4u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV32 (0x5u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV64 (0x6u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV128 (0x7u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV256 (0x8u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV512 (0x9u << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (0xAu << 8) /**< \brief (RTC_MODE2_CTRL) */\r
+#define RTC_MODE2_CTRL_MASK 0x0FCFu /**< \brief (RTC_MODE2_CTRL) MASK Register */\r
+\r
+/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t ADDR:6; /*!< bit: 0.. 5 Read Address */\r
+ uint16_t :8; /*!< bit: 6..13 Reserved */\r
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */\r
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_READREQ_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request Register */\r
+#define RTC_READREQ_RESETVALUE 0x0010 /**< \brief (RTC_READREQ reset_value) Read Request Register */\r
+\r
+#define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Read Address */\r
+#define RTC_READREQ_ADDR_Msk (0x3Fu << RTC_READREQ_ADDR_Pos)\r
+#define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)))\r
+#define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */\r
+#define RTC_READREQ_RCONT (0x1u << RTC_READREQ_RCONT_Pos)\r
+#define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */\r
+#define RTC_READREQ_RREQ (0x1u << RTC_READREQ_RREQ_Pos)\r
+#define RTC_READREQ_MASK 0xC03Fu /**< \brief (RTC_READREQ) MASK Register */\r
+\r
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval Event Output Enables */\r
+ uint16_t CMPEO:1; /*!< bit: 8 Compare Event Output Enables */\r
+ uint16_t :6; /*!< bit: 9..14 Reserved */\r
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE0_EVCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control Register */\r
+#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control Register */\r
+\r
+#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval Event Output Enables */\r
+#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE0_EVCTRL_PEREO_Pos)\r
+#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)))\r
+#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare Event Output Enables */\r
+#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1u << RTC_MODE0_EVCTRL_CMPEO_Pos)\r
+#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)))\r
+#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */\r
+#define RTC_MODE0_EVCTRL_OVFEO (0x1u << RTC_MODE0_EVCTRL_OVFEO_Pos)\r
+#define RTC_MODE0_EVCTRL_MASK 0x81FFu /**< \brief (RTC_MODE0_EVCTRL) MASK Register */\r
+\r
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval Event Output Enables */\r
+ uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare Event Output Enables */\r
+ uint16_t :5; /*!< bit: 10..14 Reserved */\r
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE1_EVCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control Register */\r
+#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control Register */\r
+\r
+#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval Event Output Enables */\r
+#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE1_EVCTRL_PEREO_Pos)\r
+#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)))\r
+#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare Event Output Enables */\r
+#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3u << RTC_MODE1_EVCTRL_CMPEO_Pos)\r
+#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)))\r
+#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */\r
+#define RTC_MODE1_EVCTRL_OVFEO (0x1u << RTC_MODE1_EVCTRL_OVFEO_Pos)\r
+#define RTC_MODE1_EVCTRL_MASK 0x83FFu /**< \brief (RTC_MODE1_EVCTRL) MASK Register */\r
+\r
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval Event Output Enables */\r
+ uint16_t ALARMEO:1; /*!< bit: 8 Alarm 0Event Output Enables */\r
+ uint16_t :6; /*!< bit: 9..14 Reserved */\r
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE2_EVCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control Register */\r
+#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control Register */\r
+\r
+#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval Event Output Enables */\r
+#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE2_EVCTRL_PEREO_Pos)\r
+#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)))\r
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0Event Output Enables */\r
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1u << RTC_MODE2_EVCTRL_ALARMEO_Pos)\r
+#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)))\r
+#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */\r
+#define RTC_MODE2_EVCTRL_OVFEO (0x1u << RTC_MODE2_EVCTRL_OVFEO_Pos)\r
+#define RTC_MODE2_EVCTRL_MASK 0x81FFu /**< \brief (RTC_MODE2_EVCTRL) MASK Register */\r
+\r
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CMP:1; /*!< bit: 0 Comparator Interrupt Disables */\r
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Disable */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Disable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE0_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear Register */\r
+#define RTC_MODE0_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear Register */\r
+\r
+#define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Comparator Interrupt Disables */\r
+#define RTC_MODE0_INTENCLR_CMP_Msk (0x1u << RTC_MODE0_INTENCLR_CMP_Pos)\r
+#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)))\r
+#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Disable */\r
+#define RTC_MODE0_INTENCLR_SYNCRDY (0x1u << RTC_MODE0_INTENCLR_SYNCRDY_Pos)\r
+#define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Disable */\r
+#define RTC_MODE0_INTENCLR_OVF (0x1u << RTC_MODE0_INTENCLR_OVF_Pos)\r
+#define RTC_MODE0_INTENCLR_MASK 0xC1u /**< \brief (RTC_MODE0_INTENCLR) MASK Register */\r
+\r
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CMP:2; /*!< bit: 0.. 1 Comparator Interrupt Disables */\r
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Disable */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Disable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE1_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear Register */\r
+#define RTC_MODE1_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear Register */\r
+\r
+#define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Comparator Interrupt Disables */\r
+#define RTC_MODE1_INTENCLR_CMP_Msk (0x3u << RTC_MODE1_INTENCLR_CMP_Pos)\r
+#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)))\r
+#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Disable */\r
+#define RTC_MODE1_INTENCLR_SYNCRDY (0x1u << RTC_MODE1_INTENCLR_SYNCRDY_Pos)\r
+#define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Disable */\r
+#define RTC_MODE1_INTENCLR_OVF (0x1u << RTC_MODE1_INTENCLR_OVF_Pos)\r
+#define RTC_MODE1_INTENCLR_MASK 0xC3u /**< \brief (RTC_MODE1_INTENCLR) MASK Register */\r
+\r
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t ALARM:1; /*!< bit: 0 Alarm Interrupt Disables */\r
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Disable */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Disable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE2_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear Register */\r
+#define RTC_MODE2_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear Register */\r
+\r
+#define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm Interrupt Disables */\r
+#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1u << RTC_MODE2_INTENCLR_ALARM_Pos)\r
+#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)))\r
+#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Disable */\r
+#define RTC_MODE2_INTENCLR_SYNCRDY (0x1u << RTC_MODE2_INTENCLR_SYNCRDY_Pos)\r
+#define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Disable */\r
+#define RTC_MODE2_INTENCLR_OVF (0x1u << RTC_MODE2_INTENCLR_OVF_Pos)\r
+#define RTC_MODE2_INTENCLR_MASK 0xC1u /**< \brief (RTC_MODE2_INTENCLR) MASK Register */\r
+\r
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CMP:1; /*!< bit: 0 Comparator Interrupt Enables */\r
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE0_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set Register */\r
+#define RTC_MODE0_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set Register */\r
+\r
+#define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Comparator Interrupt Enables */\r
+#define RTC_MODE0_INTENSET_CMP_Msk (0x1u << RTC_MODE0_INTENSET_CMP_Pos)\r
+#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)))\r
+#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */\r
+#define RTC_MODE0_INTENSET_SYNCRDY (0x1u << RTC_MODE0_INTENSET_SYNCRDY_Pos)\r
+#define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */\r
+#define RTC_MODE0_INTENSET_OVF (0x1u << RTC_MODE0_INTENSET_OVF_Pos)\r
+#define RTC_MODE0_INTENSET_MASK 0xC1u /**< \brief (RTC_MODE0_INTENSET) MASK Register */\r
+\r
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CMP:2; /*!< bit: 0.. 1 Comparator Interrupt Enables */\r
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE1_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set Register */\r
+#define RTC_MODE1_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set Register */\r
+\r
+#define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Comparator Interrupt Enables */\r
+#define RTC_MODE1_INTENSET_CMP_Msk (0x3u << RTC_MODE1_INTENSET_CMP_Pos)\r
+#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)))\r
+#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */\r
+#define RTC_MODE1_INTENSET_SYNCRDY (0x1u << RTC_MODE1_INTENSET_SYNCRDY_Pos)\r
+#define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */\r
+#define RTC_MODE1_INTENSET_OVF (0x1u << RTC_MODE1_INTENSET_OVF_Pos)\r
+#define RTC_MODE1_INTENSET_MASK 0xC3u /**< \brief (RTC_MODE1_INTENSET) MASK Register */\r
+\r
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t ALARM:1; /*!< bit: 0 Alarm Interrupt Enables */\r
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE2_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set Register */\r
+#define RTC_MODE2_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set Register */\r
+\r
+#define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm Interrupt Enables */\r
+#define RTC_MODE2_INTENSET_ALARM_Msk (0x1u << RTC_MODE2_INTENSET_ALARM_Pos)\r
+#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)))\r
+#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */\r
+#define RTC_MODE2_INTENSET_SYNCRDY (0x1u << RTC_MODE2_INTENSET_SYNCRDY_Pos)\r
+#define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */\r
+#define RTC_MODE2_INTENSET_OVF (0x1u << RTC_MODE2_INTENSET_OVF_Pos)\r
+#define RTC_MODE2_INTENSET_MASK 0xC1u /**< \brief (RTC_MODE2_INTENSET) MASK Register */\r
+\r
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CMP:1; /*!< bit: 0 Comparator Interrupt Flags */\r
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Flag */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Flag */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE0_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear Register */\r
+#define RTC_MODE0_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear Register */\r
+\r
+#define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Comparator Interrupt Flags */\r
+#define RTC_MODE0_INTFLAG_CMP_Msk (0x1u << RTC_MODE0_INTFLAG_CMP_Pos)\r
+#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)))\r
+#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready Interrupt Flag */\r
+#define RTC_MODE0_INTFLAG_SYNCRDY (0x1u << RTC_MODE0_INTFLAG_SYNCRDY_Pos)\r
+#define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow Interrupt Flag */\r
+#define RTC_MODE0_INTFLAG_OVF (0x1u << RTC_MODE0_INTFLAG_OVF_Pos)\r
+#define RTC_MODE0_INTFLAG_MASK 0xC1u /**< \brief (RTC_MODE0_INTFLAG) MASK Register */\r
+\r
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CMP:2; /*!< bit: 0.. 1 Comparator Interrupt Flags */\r
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Flag */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Flag */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE1_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear Register */\r
+#define RTC_MODE1_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear Register */\r
+\r
+#define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Comparator Interrupt Flags */\r
+#define RTC_MODE1_INTFLAG_CMP_Msk (0x3u << RTC_MODE1_INTFLAG_CMP_Pos)\r
+#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)))\r
+#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready Interrupt Flag */\r
+#define RTC_MODE1_INTFLAG_SYNCRDY (0x1u << RTC_MODE1_INTFLAG_SYNCRDY_Pos)\r
+#define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow Interrupt Flag */\r
+#define RTC_MODE1_INTFLAG_OVF (0x1u << RTC_MODE1_INTFLAG_OVF_Pos)\r
+#define RTC_MODE1_INTFLAG_MASK 0xC3u /**< \brief (RTC_MODE1_INTFLAG) MASK Register */\r
+\r
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t ALARM:1; /*!< bit: 0 Alarm Interrupt Flags */\r
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Flag */\r
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Flag */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE2_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear Register */\r
+#define RTC_MODE2_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear Register */\r
+\r
+#define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm Interrupt Flags */\r
+#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1u << RTC_MODE2_INTFLAG_ALARM_Pos)\r
+#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)))\r
+#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready Interrupt Flag */\r
+#define RTC_MODE2_INTFLAG_SYNCRDY (0x1u << RTC_MODE2_INTFLAG_SYNCRDY_Pos)\r
+#define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow Interrupt Flag */\r
+#define RTC_MODE2_INTFLAG_OVF (0x1u << RTC_MODE2_INTFLAG_OVF_Pos)\r
+#define RTC_MODE2_INTFLAG_MASK 0xC1u /**< \brief (RTC_MODE2_INTFLAG) MASK Register */\r
+\r
+/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */\r
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status Register */\r
+#define RTC_STATUS_RESETVALUE 0x00 /**< \brief (RTC_STATUS reset_value) Status Register */\r
+\r
+#define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy Status */\r
+#define RTC_STATUS_SYNCBUSY (0x1u << RTC_STATUS_SYNCBUSY_Pos)\r
+#define RTC_STATUS_MASK 0x80u /**< \brief (RTC_STATUS) MASK Register */\r
+\r
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_DBGCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Register */\r
+#define RTC_DBGCTRL_RESETVALUE 0x00 /**< \brief (RTC_DBGCTRL reset_value) Debug Register */\r
+\r
+#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */\r
+#define RTC_DBGCTRL_DBGRUN (0x1u << RTC_DBGCTRL_DBGRUN_Pos)\r
+#define RTC_DBGCTRL_MASK 0x01u /**< \brief (RTC_DBGCTRL) MASK Register */\r
+\r
+/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */\r
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_FREQCORR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction Register */\r
+#define RTC_FREQCORR_RESETVALUE 0x00 /**< \brief (RTC_FREQCORR reset_value) Frequency Correction Register */\r
+\r
+#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */\r
+#define RTC_FREQCORR_VALUE_Msk (0x7Fu << RTC_FREQCORR_VALUE_Pos)\r
+#define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)))\r
+#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */\r
+#define RTC_FREQCORR_SIGN (0x1u << RTC_FREQCORR_SIGN_Pos)\r
+#define RTC_FREQCORR_MASK 0xFFu /**< \brief (RTC_FREQCORR) MASK Register */\r
+\r
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Count Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} RTC_MODE0_COUNT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Count Register */\r
+#define RTC_MODE0_COUNT_RESETVALUE 0x00000000 /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Count Register */\r
+\r
+#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */\r
+#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFu << RTC_MODE0_COUNT_COUNT_Pos)\r
+#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)))\r
+#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE0_COUNT) MASK Register */\r
+\r
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Count Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE1_COUNT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Count Register */\r
+#define RTC_MODE1_COUNT_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Count Register */\r
+\r
+#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */\r
+#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFu << RTC_MODE1_COUNT_COUNT_Pos)\r
+#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)))\r
+#define RTC_MODE1_COUNT_MASK 0xFFFFu /**< \brief (RTC_MODE1_COUNT) MASK Register */\r
+\r
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Current Second */\r
+ uint32_t MINUTE:6; /*!< bit: 6..11 Current Minute */\r
+ uint32_t HOUR:5; /*!< bit: 12..16 Current Hour */\r
+ uint32_t DAY:5; /*!< bit: 17..21 Current Day */\r
+ uint32_t MONTH:4; /*!< bit: 22..25 Current Month */\r
+ uint32_t YEAR:6; /*!< bit: 26..31 Current Year */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} RTC_MODE2_CLOCK_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Register */\r
+#define RTC_MODE2_CLOCK_RESETVALUE 0x00000000 /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Register */\r
+\r
+#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Current Second */\r
+#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Fu << RTC_MODE2_CLOCK_SECOND_Pos)\r
+#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)))\r
+#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Current Minute */\r
+#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Fu << RTC_MODE2_CLOCK_MINUTE_Pos)\r
+#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)))\r
+#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Current Hour */\r
+#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Fu << RTC_MODE2_CLOCK_HOUR_Pos)\r
+#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)))\r
+#define RTC_MODE2_CLOCK_HOUR_PM (0x10u << 12) /**< \brief (RTC_MODE2_CLOCK) */\r
+#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Current Day */\r
+#define RTC_MODE2_CLOCK_DAY_Msk (0x1Fu << RTC_MODE2_CLOCK_DAY_Pos)\r
+#define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)))\r
+#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Current Month */\r
+#define RTC_MODE2_CLOCK_MONTH_Msk (0xFu << RTC_MODE2_CLOCK_MONTH_Pos)\r
+#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)))\r
+#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Current Year */\r
+#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Fu << RTC_MODE2_CLOCK_YEAR_Pos)\r
+#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)))\r
+#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE2_CLOCK) MASK Register */\r
+\r
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Period Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE1_PER_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Period Register */\r
+#define RTC_MODE1_PER_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_PER reset_value) MODE1 Period Register */\r
+\r
+#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */\r
+#define RTC_MODE1_PER_PER_Msk (0xFFFFu << RTC_MODE1_PER_PER_Pos)\r
+#define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)))\r
+#define RTC_MODE1_PER_MASK 0xFFFFu /**< \brief (RTC_MODE1_PER) MASK Register */\r
+\r
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} RTC_MODE0_COMP_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare Register */\r
+#define RTC_MODE0_COMP_RESETVALUE 0x00000000 /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare Register */\r
+\r
+#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */\r
+#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFu << RTC_MODE0_COMP_COMP_Pos)\r
+#define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)))\r
+#define RTC_MODE0_COMP_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE0_COMP) MASK Register */\r
+\r
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} RTC_MODE1_COMP_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare Register */\r
+#define RTC_MODE1_COMP_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare Register */\r
+\r
+#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */\r
+#define RTC_MODE1_COMP_COMP_Msk (0xFFFFu << RTC_MODE1_COMP_COMP_Pos)\r
+#define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)))\r
+#define RTC_MODE1_COMP_MASK 0xFFFFu /**< \brief (RTC_MODE1_COMP) MASK Register */\r
+\r
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Alarm Second */\r
+ uint32_t MINUTE:6; /*!< bit: 6..11 Alarm Minute */\r
+ uint32_t HOUR:5; /*!< bit: 12..16 Alarm Hour */\r
+ uint32_t DAY:5; /*!< bit: 17..21 Alarm Day */\r
+ uint32_t MONTH:4; /*!< bit: 22..25 Alarm Month */\r
+ uint32_t YEAR:6; /*!< bit: 26..31 Alarm Year */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} RTC_MODE2_ALARM_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm Register */\r
+#define RTC_MODE2_ALARM_RESETVALUE 0x00000000 /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm Register */\r
+\r
+#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Alarm Second */\r
+#define RTC_MODE2_ALARM_SECOND_Msk (0x3Fu << RTC_MODE2_ALARM_SECOND_Pos)\r
+#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)))\r
+#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Alarm Minute */\r
+#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Fu << RTC_MODE2_ALARM_MINUTE_Pos)\r
+#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)))\r
+#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Alarm Hour */\r
+#define RTC_MODE2_ALARM_HOUR_Msk (0x1Fu << RTC_MODE2_ALARM_HOUR_Pos)\r
+#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)))\r
+#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Alarm Day */\r
+#define RTC_MODE2_ALARM_DAY_Msk (0x1Fu << RTC_MODE2_ALARM_DAY_Pos)\r
+#define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)))\r
+#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Alarm Month */\r
+#define RTC_MODE2_ALARM_MONTH_Msk (0xFu << RTC_MODE2_ALARM_MONTH_Pos)\r
+#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)))\r
+#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Alarm Year */\r
+#define RTC_MODE2_ALARM_YEAR_Msk (0x3Fu << RTC_MODE2_ALARM_YEAR_Pos)\r
+#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)))\r
+#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE2_ALARM) MASK Register */\r
+\r
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm Mask Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} RTC_MODE2_MASK_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm Mask Register */\r
+#define RTC_MODE2_MASK_RESETVALUE 0x00 /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm Mask Register */\r
+\r
+#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */\r
+#define RTC_MODE2_MASK_SEL_Msk (0x7u << RTC_MODE2_MASK_SEL_Pos)\r
+#define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)))\r
+#define RTC_MODE2_MASK_SEL_OFF (0x0u << 0) /**< \brief (RTC_MODE2_MASK) */\r
+#define RTC_MODE2_MASK_SEL_SS (0x1u << 0) /**< \brief (RTC_MODE2_MASK) */\r
+#define RTC_MODE2_MASK_SEL_MMSS (0x2u << 0) /**< \brief (RTC_MODE2_MASK) */\r
+#define RTC_MODE2_MASK_SEL_HHMMSS (0x3u << 0) /**< \brief (RTC_MODE2_MASK) */\r
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (0x4u << 0) /**< \brief (RTC_MODE2_MASK) */\r
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (0x5u << 0) /**< \brief (RTC_MODE2_MASK) */\r
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (0x6u << 0) /**< \brief (RTC_MODE2_MASK) */\r
+#define RTC_MODE2_MASK_MASK 0x07u /**< \brief (RTC_MODE2_MASK) MASK Register */\r
+\r
+/** \brief RtcMode2Alarm hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm Register */\r
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm Mask Register */\r
+ RoReg8 Reserved1[0x3];\r
+} RtcMode2Alarm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief RTC_MODE0 hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */\r
+ __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control Register */\r
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request Register */\r
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control Register */\r
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear Register */\r
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set Register */\r
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status Register */\r
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Register */\r
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction Register */\r
+ RoReg8 Reserved2[0x3];\r
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Count Register */\r
+ RoReg8 Reserved3[0x4];\r
+ __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare Register [NUM_OF_COMP32] */\r
+} RtcMode0;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief RTC_MODE1 hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */\r
+ __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control Register */\r
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request Register */\r
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control Register */\r
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear Register */\r
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set Register */\r
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status Register */\r
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Register */\r
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction Register */\r
+ RoReg8 Reserved2[0x3];\r
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Count Register */\r
+ RoReg8 Reserved3[0x2];\r
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Period Register */\r
+ RoReg8 Reserved4[0x2];\r
+ __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare Register [NUM_OF_COMP16] */\r
+} RtcMode1;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief RTC_MODE2 hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* Clock/Calendar with Alarm */\r
+ __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control Register */\r
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request Register */\r
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control Register */\r
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear Register */\r
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set Register */\r
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status Register */\r
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Register */\r
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction Register */\r
+ RoReg8 Reserved2[0x3];\r
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Register */\r
+ RoReg8 Reserved3[0x4];\r
+ RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [NUM_OF_ALARMS] */\r
+} RtcMode2;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */\r
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */\r
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */\r
+} Rtc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_RTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for SERCOM\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SERCOM_COMPONENT_\r
+#define _SAMD20_SERCOM_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR SERCOM */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_SERCOM Serial Communication Interface */\r
+/*@{*/\r
+\r
+#define REV_SERCOM 0x101\r
+\r
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */\r
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */\r
+ uint32_t :8; /*!< bit: 8..15 Reserved */\r
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */\r
+ uint32_t :3; /*!< bit: 17..19 Reserved */\r
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */\r
+ uint32_t :6; /*!< bit: 22..27 Reserved */\r
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Bus Timeout */\r
+ uint32_t LOWTOUT:1; /*!< bit: 30 SCL Low Timeout */\r
+ uint32_t :1; /*!< bit: 31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control Register A */\r
+#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control Register A */\r
+\r
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */\r
+#define SERCOM_I2CM_CTRLA_SWRST (0x1u << SERCOM_I2CM_CTRLA_SWRST_Pos)\r
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */\r
+#define SERCOM_I2CM_CTRLA_ENABLE (0x1u << SERCOM_I2CM_CTRLA_ENABLE_Pos)\r
+#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */\r
+#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7u << SERCOM_I2CM_CTRLA_MODE_Pos)\r
+#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))\r
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (0x0u << 2) /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */\r
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (0x1u << 2) /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */\r
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (0x2u << 2) /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */\r
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (0x3u << 2) /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */\r
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (0x4u << 2) /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */\r
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (0x5u << 2) /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */\r
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run during Standby */\r
+#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1u << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)\r
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */\r
+#define SERCOM_I2CM_CTRLA_PINOUT (0x1u << SERCOM_I2CM_CTRLA_PINOUT_Pos)\r
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */\r
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3u << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)\r
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))\r
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Bus Timeout */\r
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3u << SERCOM_I2CM_CTRLA_INACTOUT_Pos)\r
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))\r
+#define SERCOM_I2CM_CTRLA_LOWTOUT_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout */\r
+#define SERCOM_I2CM_CTRLA_LOWTOUT (0x1u << SERCOM_I2CM_CTRLA_LOWTOUT_Pos)\r
+#define SERCOM_I2CM_CTRLA_MASK 0x7031009Fu /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */\r
+\r
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */\r
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */\r
+ uint32_t :8; /*!< bit: 8..15 Reserved */\r
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */\r
+ uint32_t :3; /*!< bit: 17..19 Reserved */\r
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */\r
+ uint32_t :8; /*!< bit: 22..29 Reserved */\r
+ uint32_t LOWTOUT:1; /*!< bit: 30 SCL Low Timeout */\r
+ uint32_t :1; /*!< bit: 31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CS_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control Register A */\r
+#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control Register A */\r
+\r
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */\r
+#define SERCOM_I2CS_CTRLA_SWRST (0x1u << SERCOM_I2CS_CTRLA_SWRST_Pos)\r
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */\r
+#define SERCOM_I2CS_CTRLA_ENABLE (0x1u << SERCOM_I2CS_CTRLA_ENABLE_Pos)\r
+#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */\r
+#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7u << SERCOM_I2CS_CTRLA_MODE_Pos)\r
+#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))\r
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (0x0u << 2) /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */\r
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (0x1u << 2) /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */\r
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (0x2u << 2) /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */\r
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (0x3u << 2) /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */\r
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (0x4u << 2) /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */\r
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (0x5u << 2) /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */\r
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */\r
+#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1u << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)\r
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */\r
+#define SERCOM_I2CS_CTRLA_PINOUT (0x1u << SERCOM_I2CS_CTRLA_PINOUT_Pos)\r
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */\r
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3u << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)\r
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))\r
+#define SERCOM_I2CS_CTRLA_LOWTOUT_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout */\r
+#define SERCOM_I2CS_CTRLA_LOWTOUT (0x1u << SERCOM_I2CS_CTRLA_LOWTOUT_Pos)\r
+#define SERCOM_I2CS_CTRLA_MASK 0x4031009Fu /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */\r
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */\r
+ uint32_t :8; /*!< bit: 8..15 Reserved */\r
+ uint32_t DOPO:1; /*!< bit: 16 Data Out Pinout */\r
+ uint32_t :3; /*!< bit: 17..19 Reserved */\r
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */\r
+ uint32_t :2; /*!< bit: 22..23 Reserved */\r
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */\r
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */\r
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */\r
+ uint32_t DORD:1; /*!< bit: 30 Data Order */\r
+ uint32_t :1; /*!< bit: 31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control Register A */\r
+#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control Register A */\r
+\r
+#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */\r
+#define SERCOM_SPI_CTRLA_SWRST (0x1u << SERCOM_SPI_CTRLA_SWRST_Pos)\r
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */\r
+#define SERCOM_SPI_CTRLA_ENABLE (0x1u << SERCOM_SPI_CTRLA_ENABLE_Pos)\r
+#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */\r
+#define SERCOM_SPI_CTRLA_MODE_Msk (0x7u << SERCOM_SPI_CTRLA_MODE_Pos)\r
+#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))\r
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (0x0u << 2) /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */\r
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (0x1u << 2) /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */\r
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (0x2u << 2) /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */\r
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (0x3u << 2) /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */\r
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (0x4u << 2) /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */\r
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (0x5u << 2) /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */\r
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */\r
+#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1u << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)\r
+#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */\r
+#define SERCOM_SPI_CTRLA_DOPO (0x1u << SERCOM_SPI_CTRLA_DOPO_Pos)\r
+#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */\r
+#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3u << SERCOM_SPI_CTRLA_DIPO_Pos)\r
+#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))\r
+#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */\r
+#define SERCOM_SPI_CTRLA_FORM_Msk (0xFu << SERCOM_SPI_CTRLA_FORM_Pos)\r
+#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))\r
+#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */\r
+#define SERCOM_SPI_CTRLA_CPHA (0x1u << SERCOM_SPI_CTRLA_CPHA_Pos)\r
+#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */\r
+#define SERCOM_SPI_CTRLA_CPOL (0x1u << SERCOM_SPI_CTRLA_CPOL_Pos)\r
+#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */\r
+#define SERCOM_SPI_CTRLA_DORD (0x1u << SERCOM_SPI_CTRLA_DORD_Pos)\r
+#define SERCOM_SPI_CTRLA_MASK 0x7F31009Fu /**< \brief (SERCOM_SPI_CTRLA) MASK Register */\r
+\r
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */\r
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */\r
+ uint32_t :8; /*!< bit: 8..15 Reserved */\r
+ uint32_t TXPO:1; /*!< bit: 16 Transmit Data Pinout */\r
+ uint32_t :3; /*!< bit: 17..19 Reserved */\r
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */\r
+ uint32_t :2; /*!< bit: 22..23 Reserved */\r
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */\r
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */\r
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */\r
+ uint32_t DORD:1; /*!< bit: 30 Data Order */\r
+ uint32_t :1; /*!< bit: 31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control Register A */\r
+#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control Register A */\r
+\r
+#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */\r
+#define SERCOM_USART_CTRLA_SWRST (0x1u << SERCOM_USART_CTRLA_SWRST_Pos)\r
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */\r
+#define SERCOM_USART_CTRLA_ENABLE (0x1u << SERCOM_USART_CTRLA_ENABLE_Pos)\r
+#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */\r
+#define SERCOM_USART_CTRLA_MODE_Msk (0x7u << SERCOM_USART_CTRLA_MODE_Pos)\r
+#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))\r
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (0x0u << 2) /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */\r
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (0x1u << 2) /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */\r
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (0x2u << 2) /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */\r
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (0x3u << 2) /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */\r
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (0x4u << 2) /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */\r
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (0x5u << 2) /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */\r
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */\r
+#define SERCOM_USART_CTRLA_RUNSTDBY (0x1u << SERCOM_USART_CTRLA_RUNSTDBY_Pos)\r
+#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */\r
+#define SERCOM_USART_CTRLA_TXPO (0x1u << SERCOM_USART_CTRLA_TXPO_Pos)\r
+#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */\r
+#define SERCOM_USART_CTRLA_RXPO_Msk (0x3u << SERCOM_USART_CTRLA_RXPO_Pos)\r
+#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))\r
+#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */\r
+#define SERCOM_USART_CTRLA_FORM_Msk (0xFu << SERCOM_USART_CTRLA_FORM_Pos)\r
+#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))\r
+#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */\r
+#define SERCOM_USART_CTRLA_CMODE (0x1u << SERCOM_USART_CTRLA_CMODE_Pos)\r
+#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */\r
+#define SERCOM_USART_CTRLA_CPOL (0x1u << SERCOM_USART_CTRLA_CPOL_Pos)\r
+#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */\r
+#define SERCOM_USART_CTRLA_DORD (0x1u << SERCOM_USART_CTRLA_DORD_Pos)\r
+#define SERCOM_USART_CTRLA_MASK 0x7F31009Fu /**< \brief (SERCOM_USART_CTRLA) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */\r
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */\r
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */\r
+ uint32_t :6; /*!< bit: 10..15 Reserved */\r
+ uint32_t CMD:2; /*!< bit: 16..17 Command */\r
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */\r
+ uint32_t :13; /*!< bit: 19..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_CTRLB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control Register B */\r
+#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control Register B */\r
+\r
+#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */\r
+#define SERCOM_I2CM_CTRLB_SMEN (0x1u << SERCOM_I2CM_CTRLB_SMEN_Pos)\r
+#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */\r
+#define SERCOM_I2CM_CTRLB_QCEN (0x1u << SERCOM_I2CM_CTRLB_QCEN_Pos)\r
+#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */\r
+#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3u << SERCOM_I2CM_CTRLB_CMD_Pos)\r
+#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))\r
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */\r
+#define SERCOM_I2CM_CTRLB_ACKACT (0x1u << SERCOM_I2CM_CTRLB_ACKACT_Pos)\r
+#define SERCOM_I2CM_CTRLB_MASK 0x00070300u /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */\r
+\r
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */\r
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */\r
+ uint32_t :5; /*!< bit: 9..13 Reserved */\r
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */\r
+ uint32_t CMD:2; /*!< bit: 16..17 Command */\r
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */\r
+ uint32_t :13; /*!< bit: 19..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CS_CTRLB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control Register B */\r
+#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control Register B */\r
+\r
+#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */\r
+#define SERCOM_I2CS_CTRLB_SMEN (0x1u << SERCOM_I2CS_CTRLB_SMEN_Pos)\r
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */\r
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3u << SERCOM_I2CS_CTRLB_AMODE_Pos)\r
+#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))\r
+#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */\r
+#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3u << SERCOM_I2CS_CTRLB_CMD_Pos)\r
+#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))\r
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */\r
+#define SERCOM_I2CS_CTRLB_ACKACT (0x1u << SERCOM_I2CS_CTRLB_ACKACT_Pos)\r
+#define SERCOM_I2CS_CTRLB_MASK 0x0007C100u /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */\r
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */\r
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */\r
+ uint32_t :7; /*!< bit: 7..13 Reserved */\r
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */\r
+ uint32_t :1; /*!< bit: 16 Reserved */\r
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */\r
+ uint32_t :14; /*!< bit: 18..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_CTRLB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control Register B */\r
+#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control Register B */\r
+\r
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */\r
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7u << SERCOM_SPI_CTRLB_CHSIZE_Pos)\r
+#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))\r
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */\r
+#define SERCOM_SPI_CTRLB_PLOADEN (0x1u << SERCOM_SPI_CTRLB_PLOADEN_Pos)\r
+#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */\r
+#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3u << SERCOM_SPI_CTRLB_AMODE_Pos)\r
+#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))\r
+#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */\r
+#define SERCOM_SPI_CTRLB_RXEN (0x1u << SERCOM_SPI_CTRLB_RXEN_Pos)\r
+#define SERCOM_SPI_CTRLB_MASK 0x0002C047u /**< \brief (SERCOM_SPI_CTRLB) MASK Register */\r
+\r
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control Register B -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */\r
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */\r
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */\r
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */\r
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */\r
+ uint32_t :3; /*!< bit: 10..12 Reserved */\r
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */\r
+ uint32_t :2; /*!< bit: 14..15 Reserved */\r
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */\r
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */\r
+ uint32_t :14; /*!< bit: 18..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_CTRLB_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control Register B */\r
+#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control Register B */\r
+\r
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */\r
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7u << SERCOM_USART_CTRLB_CHSIZE_Pos)\r
+#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))\r
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */\r
+#define SERCOM_USART_CTRLB_SBMODE (0x1u << SERCOM_USART_CTRLB_SBMODE_Pos)\r
+#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */\r
+#define SERCOM_USART_CTRLB_SFDE (0x1u << SERCOM_USART_CTRLB_SFDE_Pos)\r
+#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */\r
+#define SERCOM_USART_CTRLB_PMODE (0x1u << SERCOM_USART_CTRLB_PMODE_Pos)\r
+#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */\r
+#define SERCOM_USART_CTRLB_TXEN (0x1u << SERCOM_USART_CTRLB_TXEN_Pos)\r
+#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */\r
+#define SERCOM_USART_CTRLB_RXEN (0x1u << SERCOM_USART_CTRLB_RXEN_Pos)\r
+#define SERCOM_USART_CTRLB_MASK 0x00032247u /**< \brief (SERCOM_USART_CTRLB) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) I2CM I2CM Debug Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_DBGCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Register */\r
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Register */\r
+\r
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */\r
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1u << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)\r
+#define SERCOM_I2CM_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) SPI SPI Debug Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_DBGCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Register */\r
+#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Register */\r
+\r
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */\r
+#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1u << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)\r
+#define SERCOM_SPI_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */\r
+\r
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) USART USART Debug Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_DBGCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Register */\r
+#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Register */\r
+\r
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */\r
+#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1u << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)\r
+#define SERCOM_USART_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0A) (R/W 16) I2CM I2CM Baud Rate Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */\r
+ uint16_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_BAUD_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_BAUD_OFFSET 0x0A /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate Register */\r
+#define SERCOM_I2CM_BAUD_RESETVALUE 0x0000 /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate Register */\r
+\r
+#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */\r
+#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFu << SERCOM_I2CM_BAUD_BAUD_Pos)\r
+#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))\r
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */\r
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFu << SERCOM_I2CM_BAUD_BAUDLOW_Pos)\r
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))\r
+#define SERCOM_I2CM_BAUD_MASK 0xFFFFu /**< \brief (SERCOM_I2CM_BAUD) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0A) (R/W 8) SPI SPI Baud Rate Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_BAUD_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_BAUD_OFFSET 0x0A /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate Register */\r
+#define SERCOM_SPI_BAUD_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate Register */\r
+\r
+#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */\r
+#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFu << SERCOM_SPI_BAUD_BAUD_Pos)\r
+#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))\r
+#define SERCOM_SPI_BAUD_MASK 0xFFu /**< \brief (SERCOM_SPI_BAUD) MASK Register */\r
+\r
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0A) (R/W 16) USART USART Baud Rate Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_BAUD_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_BAUD_OFFSET 0x0A /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate Register */\r
+#define SERCOM_USART_BAUD_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate Register */\r
+\r
+#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */\r
+#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFu << SERCOM_USART_BAUD_BAUD_Pos)\r
+#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))\r
+#define SERCOM_USART_BAUD_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) I2CM I2CM Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t MB:1; /*!< bit: 0 Write Interrupt Disable */\r
+ uint8_t SB:1; /*!< bit: 1 Read Interrupt Disable */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear Register */\r
+#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear Register */\r
+\r
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Write Interrupt Disable */\r
+#define SERCOM_I2CM_INTENCLR_MB (0x1u << SERCOM_I2CM_INTENCLR_MB_Pos)\r
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Read Interrupt Disable */\r
+#define SERCOM_I2CM_INTENCLR_SB (0x1u << SERCOM_I2CM_INTENCLR_SB_Pos)\r
+#define SERCOM_I2CM_INTENCLR_MASK 0x03u /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */\r
+\r
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) I2CS I2CS Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t PREC:1; /*!< bit: 0 Stop Interrupt Disable */\r
+ uint8_t AMATCH:1; /*!< bit: 1 Address Interrupt Disable */\r
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CS_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear Register */\r
+#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear Register */\r
+\r
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Interrupt Disable */\r
+#define SERCOM_I2CS_INTENCLR_PREC (0x1u << SERCOM_I2CS_INTENCLR_PREC_Pos)\r
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Interrupt Disable */\r
+#define SERCOM_I2CS_INTENCLR_AMATCH (0x1u << SERCOM_I2CS_INTENCLR_AMATCH_Pos)\r
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */\r
+#define SERCOM_I2CS_INTENCLR_DRDY (0x1u << SERCOM_I2CS_INTENCLR_DRDY_Pos)\r
+#define SERCOM_I2CS_INTENCLR_MASK 0x07u /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */\r
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */\r
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear Register */\r
+#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear Register */\r
+\r
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */\r
+#define SERCOM_SPI_INTENCLR_DRE (0x1u << SERCOM_SPI_INTENCLR_DRE_Pos)\r
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */\r
+#define SERCOM_SPI_INTENCLR_TXC (0x1u << SERCOM_SPI_INTENCLR_TXC_Pos)\r
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */\r
+#define SERCOM_SPI_INTENCLR_RXC (0x1u << SERCOM_SPI_INTENCLR_RXC_Pos)\r
+#define SERCOM_SPI_INTENCLR_MASK 0x07u /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */\r
+\r
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) USART USART Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */\r
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */\r
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */\r
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear Register */\r
+#define SERCOM_USART_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear Register */\r
+\r
+#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */\r
+#define SERCOM_USART_INTENCLR_DRE (0x1u << SERCOM_USART_INTENCLR_DRE_Pos)\r
+#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */\r
+#define SERCOM_USART_INTENCLR_TXC (0x1u << SERCOM_USART_INTENCLR_TXC_Pos)\r
+#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */\r
+#define SERCOM_USART_INTENCLR_RXC (0x1u << SERCOM_USART_INTENCLR_RXC_Pos)\r
+#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */\r
+#define SERCOM_USART_INTENCLR_RXS (0x1u << SERCOM_USART_INTENCLR_RXS_Pos)\r
+#define SERCOM_USART_INTENCLR_MASK 0x0Fu /**< \brief (SERCOM_USART_INTENCLR) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) I2CM I2CM Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t MB:1; /*!< bit: 0 Write Interrupt Enable */\r
+ uint8_t SB:1; /*!< bit: 1 Read Interrupt Enable */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set Register */\r
+#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set Register */\r
+\r
+#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Write Interrupt Enable */\r
+#define SERCOM_I2CM_INTENSET_MB (0x1u << SERCOM_I2CM_INTENSET_MB_Pos)\r
+#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Read Interrupt Enable */\r
+#define SERCOM_I2CM_INTENSET_SB (0x1u << SERCOM_I2CM_INTENSET_SB_Pos)\r
+#define SERCOM_I2CM_INTENSET_MASK 0x03u /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */\r
+\r
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) I2CS I2CS Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t PREC:1; /*!< bit: 0 Stop Interrupt Enable */\r
+ uint8_t AMATCH:1; /*!< bit: 1 Address Interrupt Enable */\r
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CS_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CS_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set Register */\r
+#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set Register */\r
+\r
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Interrupt Enable */\r
+#define SERCOM_I2CS_INTENSET_PREC (0x1u << SERCOM_I2CS_INTENSET_PREC_Pos)\r
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Interrupt Enable */\r
+#define SERCOM_I2CS_INTENSET_AMATCH (0x1u << SERCOM_I2CS_INTENSET_AMATCH_Pos)\r
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */\r
+#define SERCOM_I2CS_INTENSET_DRDY (0x1u << SERCOM_I2CS_INTENSET_DRDY_Pos)\r
+#define SERCOM_I2CS_INTENSET_MASK 0x07u /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) SPI SPI Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */\r
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */\r
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set Register */\r
+#define SERCOM_SPI_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set Register */\r
+\r
+#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */\r
+#define SERCOM_SPI_INTENSET_DRE (0x1u << SERCOM_SPI_INTENSET_DRE_Pos)\r
+#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */\r
+#define SERCOM_SPI_INTENSET_TXC (0x1u << SERCOM_SPI_INTENSET_TXC_Pos)\r
+#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */\r
+#define SERCOM_SPI_INTENSET_RXC (0x1u << SERCOM_SPI_INTENSET_RXC_Pos)\r
+#define SERCOM_SPI_INTENSET_MASK 0x07u /**< \brief (SERCOM_SPI_INTENSET) MASK Register */\r
+\r
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) USART USART Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */\r
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */\r
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */\r
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set Register */\r
+#define SERCOM_USART_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set Register */\r
+\r
+#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */\r
+#define SERCOM_USART_INTENSET_DRE (0x1u << SERCOM_USART_INTENSET_DRE_Pos)\r
+#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */\r
+#define SERCOM_USART_INTENSET_TXC (0x1u << SERCOM_USART_INTENSET_TXC_Pos)\r
+#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */\r
+#define SERCOM_USART_INTENSET_RXC (0x1u << SERCOM_USART_INTENSET_RXC_Pos)\r
+#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */\r
+#define SERCOM_USART_INTENSET_RXS (0x1u << SERCOM_USART_INTENSET_RXS_Pos)\r
+#define SERCOM_USART_INTENSET_MASK 0x0Fu /**< \brief (SERCOM_USART_INTENSET) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t MB:1; /*!< bit: 0 Write Interrupt */\r
+ uint8_t SB:1; /*!< bit: 1 Read Interrupt */\r
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear Register */\r
+#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear Register */\r
+\r
+#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Write Interrupt */\r
+#define SERCOM_I2CM_INTFLAG_MB (0x1u << SERCOM_I2CM_INTFLAG_MB_Pos)\r
+#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Read Interrupt */\r
+#define SERCOM_I2CM_INTFLAG_SB (0x1u << SERCOM_I2CM_INTFLAG_SB_Pos)\r
+#define SERCOM_I2CM_INTFLAG_MASK 0x03u /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */\r
+\r
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t PREC:1; /*!< bit: 0 Stop Interrupt */\r
+ uint8_t AMATCH:1; /*!< bit: 1 Address Interrupt */\r
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CS_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CS_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear Register */\r
+#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear Register */\r
+\r
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Interrupt */\r
+#define SERCOM_I2CS_INTFLAG_PREC (0x1u << SERCOM_I2CS_INTFLAG_PREC_Pos)\r
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Interrupt */\r
+#define SERCOM_I2CS_INTFLAG_AMATCH (0x1u << SERCOM_I2CS_INTFLAG_AMATCH_Pos)\r
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */\r
+#define SERCOM_I2CS_INTFLAG_DRDY (0x1u << SERCOM_I2CS_INTFLAG_DRDY_Pos)\r
+#define SERCOM_I2CS_INTFLAG_MASK 0x07u /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) SPI SPI Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */\r
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */\r
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */\r
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear Register */\r
+#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear Register */\r
+\r
+#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */\r
+#define SERCOM_SPI_INTFLAG_DRE (0x1u << SERCOM_SPI_INTFLAG_DRE_Pos)\r
+#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */\r
+#define SERCOM_SPI_INTFLAG_TXC (0x1u << SERCOM_SPI_INTFLAG_TXC_Pos)\r
+#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */\r
+#define SERCOM_SPI_INTFLAG_RXC (0x1u << SERCOM_SPI_INTFLAG_RXC_Pos)\r
+#define SERCOM_SPI_INTFLAG_MASK 0x07u /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */\r
+\r
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) USART USART Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */\r
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */\r
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */\r
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear Register */\r
+#define SERCOM_USART_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear Register */\r
+\r
+#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */\r
+#define SERCOM_USART_INTFLAG_DRE (0x1u << SERCOM_USART_INTFLAG_DRE_Pos)\r
+#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */\r
+#define SERCOM_USART_INTFLAG_TXC (0x1u << SERCOM_USART_INTFLAG_TXC_Pos)\r
+#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */\r
+#define SERCOM_USART_INTFLAG_RXC (0x1u << SERCOM_USART_INTFLAG_RXC_Pos)\r
+#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */\r
+#define SERCOM_USART_INTFLAG_RXS (0x1u << SERCOM_USART_INTFLAG_RXS_Pos)\r
+#define SERCOM_USART_INTFLAG_MASK 0x0Fu /**< \brief (SERCOM_USART_INTFLAG) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x10) (R/W 16) I2CM I2CM Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */\r
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */\r
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */\r
+ uint16_t :1; /*!< bit: 3 Reserved */\r
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */\r
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */\r
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */\r
+ uint16_t :7; /*!< bit: 8..14 Reserved */\r
+ uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_STATUS_OFFSET 0x10 /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status Register */\r
+#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status Register */\r
+\r
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */\r
+#define SERCOM_I2CM_STATUS_BUSERR (0x1u << SERCOM_I2CM_STATUS_BUSERR_Pos)\r
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */\r
+#define SERCOM_I2CM_STATUS_ARBLOST (0x1u << SERCOM_I2CM_STATUS_ARBLOST_Pos)\r
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */\r
+#define SERCOM_I2CM_STATUS_RXNACK (0x1u << SERCOM_I2CM_STATUS_RXNACK_Pos)\r
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */\r
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3u << SERCOM_I2CM_STATUS_BUSSTATE_Pos)\r
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))\r
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */\r
+#define SERCOM_I2CM_STATUS_LOWTOUT (0x1u << SERCOM_I2CM_STATUS_LOWTOUT_Pos)\r
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */\r
+#define SERCOM_I2CM_STATUS_CLKHOLD (0x1u << SERCOM_I2CM_STATUS_CLKHOLD_Pos)\r
+#define SERCOM_I2CM_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_I2CM_STATUS) Synchronization Busy */\r
+#define SERCOM_I2CM_STATUS_SYNCBUSY (0x1u << SERCOM_I2CM_STATUS_SYNCBUSY_Pos)\r
+#define SERCOM_I2CM_STATUS_MASK 0x80F7u /**< \brief (SERCOM_I2CM_STATUS) MASK Register */\r
+\r
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x10) (R/W 16) I2CS I2CS Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */\r
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */\r
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */\r
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */\r
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */\r
+ uint16_t :1; /*!< bit: 5 Reserved */\r
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */\r
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */\r
+ uint16_t :7; /*!< bit: 8..14 Reserved */\r
+ uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CS_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CS_STATUS_OFFSET 0x10 /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status Register */\r
+#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status Register */\r
+\r
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */\r
+#define SERCOM_I2CS_STATUS_BUSERR (0x1u << SERCOM_I2CS_STATUS_BUSERR_Pos)\r
+#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */\r
+#define SERCOM_I2CS_STATUS_COLL (0x1u << SERCOM_I2CS_STATUS_COLL_Pos)\r
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */\r
+#define SERCOM_I2CS_STATUS_RXNACK (0x1u << SERCOM_I2CS_STATUS_RXNACK_Pos)\r
+#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */\r
+#define SERCOM_I2CS_STATUS_DIR (0x1u << SERCOM_I2CS_STATUS_DIR_Pos)\r
+#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */\r
+#define SERCOM_I2CS_STATUS_SR (0x1u << SERCOM_I2CS_STATUS_SR_Pos)\r
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */\r
+#define SERCOM_I2CS_STATUS_LOWTOUT (0x1u << SERCOM_I2CS_STATUS_LOWTOUT_Pos)\r
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */\r
+#define SERCOM_I2CS_STATUS_CLKHOLD (0x1u << SERCOM_I2CS_STATUS_CLKHOLD_Pos)\r
+#define SERCOM_I2CS_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_I2CS_STATUS) Synchronization Busy */\r
+#define SERCOM_I2CS_STATUS_SYNCBUSY (0x1u << SERCOM_I2CS_STATUS_SYNCBUSY_Pos)\r
+#define SERCOM_I2CS_STATUS_MASK 0x80DFu /**< \brief (SERCOM_I2CS_STATUS) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x10) (R/W 16) SPI SPI Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */\r
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */\r
+ uint16_t :12; /*!< bit: 3..14 Reserved */\r
+ uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_STATUS_OFFSET 0x10 /**< \brief (SERCOM_SPI_STATUS offset) SPI Status Register */\r
+#define SERCOM_SPI_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status Register */\r
+\r
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */\r
+#define SERCOM_SPI_STATUS_BUFOVF (0x1u << SERCOM_SPI_STATUS_BUFOVF_Pos)\r
+#define SERCOM_SPI_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_SPI_STATUS) Synchronization Busy */\r
+#define SERCOM_SPI_STATUS_SYNCBUSY (0x1u << SERCOM_SPI_STATUS_SYNCBUSY_Pos)\r
+#define SERCOM_SPI_STATUS_MASK 0x8004u /**< \brief (SERCOM_SPI_STATUS) MASK Register */\r
+\r
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x10) (R/W 16) USART USART Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */\r
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */\r
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */\r
+ uint16_t :12; /*!< bit: 3..14 Reserved */\r
+ uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_STATUS_OFFSET 0x10 /**< \brief (SERCOM_USART_STATUS offset) USART Status Register */\r
+#define SERCOM_USART_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_STATUS reset_value) USART Status Register */\r
+\r
+#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */\r
+#define SERCOM_USART_STATUS_PERR (0x1u << SERCOM_USART_STATUS_PERR_Pos)\r
+#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */\r
+#define SERCOM_USART_STATUS_FERR (0x1u << SERCOM_USART_STATUS_FERR_Pos)\r
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */\r
+#define SERCOM_USART_STATUS_BUFOVF (0x1u << SERCOM_USART_STATUS_BUFOVF_Pos)\r
+#define SERCOM_USART_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_USART_STATUS) Synchronization Busy */\r
+#define SERCOM_USART_STATUS_SYNCBUSY (0x1u << SERCOM_USART_STATUS_SYNCBUSY_Pos)\r
+#define SERCOM_USART_STATUS_MASK 0x8007u /**< \brief (SERCOM_USART_STATUS) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Address Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t ADDR:8; /*!< bit: 0.. 7 Address Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_ADDR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_ADDR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address Register */\r
+#define SERCOM_I2CM_ADDR_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address Register */\r
+\r
+#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */\r
+#define SERCOM_I2CM_ADDR_ADDR_Msk (0xFFu << SERCOM_I2CM_ADDR_ADDR_Pos)\r
+#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))\r
+#define SERCOM_I2CM_ADDR_MASK 0xFFu /**< \brief (SERCOM_I2CM_ADDR) MASK Register */\r
+\r
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x14) (R/W 32) I2CS I2CS Address Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */\r
+ uint32_t ADDR:7; /*!< bit: 1.. 7 Address Value */\r
+ uint32_t :9; /*!< bit: 8..16 Reserved */\r
+ uint32_t ADDRMASK:7; /*!< bit: 17..23 Address Mask */\r
+ uint32_t :8; /*!< bit: 24..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CS_ADDR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CS_ADDR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address Register */\r
+#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address Register */\r
+\r
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */\r
+#define SERCOM_I2CS_ADDR_GENCEN (0x1u << SERCOM_I2CS_ADDR_GENCEN_Pos)\r
+#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */\r
+#define SERCOM_I2CS_ADDR_ADDR_Msk (0x7Fu << SERCOM_I2CS_ADDR_ADDR_Pos)\r
+#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))\r
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */\r
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x7Fu << SERCOM_I2CS_ADDR_ADDRMASK_Pos)\r
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))\r
+#define SERCOM_I2CS_ADDR_MASK 0x00FE00FFu /**< \brief (SERCOM_I2CS_ADDR) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x14) (R/W 32) SPI SPI Address Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */\r
+ uint32_t :8; /*!< bit: 8..15 Reserved */\r
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */\r
+ uint32_t :8; /*!< bit: 24..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_ADDR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_ADDR_OFFSET 0x14 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address Register */\r
+#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address Register */\r
+\r
+#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */\r
+#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFu << SERCOM_SPI_ADDR_ADDR_Pos)\r
+#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))\r
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */\r
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFu << SERCOM_SPI_ADDR_ADDRMASK_Pos)\r
+#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))\r
+#define SERCOM_SPI_ADDR_MASK 0x00FF00FFu /**< \brief (SERCOM_SPI_ADDR) MASK Register */\r
+\r
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Data Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CM_DATA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CM_DATA_OFFSET 0x18 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data Register */\r
+#define SERCOM_I2CM_DATA_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data Register */\r
+\r
+#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */\r
+#define SERCOM_I2CM_DATA_DATA_Msk (0xFFu << SERCOM_I2CM_DATA_DATA_Pos)\r
+#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))\r
+#define SERCOM_I2CM_DATA_MASK 0xFFu /**< \brief (SERCOM_I2CM_DATA) MASK Register */\r
+\r
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Data Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SERCOM_I2CS_DATA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_I2CS_DATA_OFFSET 0x18 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data Register */\r
+#define SERCOM_I2CS_DATA_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data Register */\r
+\r
+#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */\r
+#define SERCOM_I2CS_DATA_DATA_Msk (0xFFu << SERCOM_I2CS_DATA_DATA_Pos)\r
+#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))\r
+#define SERCOM_I2CS_DATA_MASK 0xFFu /**< \brief (SERCOM_I2CS_DATA) MASK Register */\r
+\r
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x18) (R/W 16) SPI SPI Data Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */\r
+ uint16_t :7; /*!< bit: 9..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SERCOM_SPI_DATA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_SPI_DATA_OFFSET 0x18 /**< \brief (SERCOM_SPI_DATA offset) SPI Data Register */\r
+#define SERCOM_SPI_DATA_RESETVALUE 0x0000 /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data Register */\r
+\r
+#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */\r
+#define SERCOM_SPI_DATA_DATA_Msk (0x1FFu << SERCOM_SPI_DATA_DATA_Pos)\r
+#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))\r
+#define SERCOM_SPI_DATA_MASK 0x01FFu /**< \brief (SERCOM_SPI_DATA) MASK Register */\r
+\r
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x18) (R/W 16) USART USART Data Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */\r
+ uint16_t :7; /*!< bit: 9..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SERCOM_USART_DATA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SERCOM_USART_DATA_OFFSET 0x18 /**< \brief (SERCOM_USART_DATA offset) USART Data Register */\r
+#define SERCOM_USART_DATA_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_DATA reset_value) USART Data Register */\r
+\r
+#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */\r
+#define SERCOM_USART_DATA_DATA_Msk (0x1FFu << SERCOM_USART_DATA_DATA_Pos)\r
+#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))\r
+#define SERCOM_USART_DATA_MASK 0x01FFu /**< \brief (SERCOM_USART_DATA) MASK Register */\r
+\r
+/** \brief SERCOM_I2CM hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* I2C Master Mode */\r
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control Register A */\r
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control Register B */\r
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) I2CM Debug Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 16) I2CM Baud Rate Register */\r
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) I2CM Interrupt Enable Clear Register */\r
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) I2CM Interrupt Enable Set Register */\r
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) I2CM Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved2[0x1];\r
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) I2CM Status Register */\r
+ RoReg8 Reserved3[0x2];\r
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 8) I2CM Address Register */\r
+ RoReg8 Reserved4[0x3];\r
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 8) I2CM Data Register */\r
+} SercomI2cm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief SERCOM_I2CS hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* I2C Slave Mode */\r
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control Register A */\r
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control Register B */\r
+ RoReg8 Reserved1[0x4];\r
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) I2CS Interrupt Enable Clear Register */\r
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) I2CS Interrupt Enable Set Register */\r
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) I2CS Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved2[0x1];\r
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) I2CS Status Register */\r
+ RoReg8 Reserved3[0x2];\r
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) I2CS Address Register */\r
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 8) I2CS Data Register */\r
+} SercomI2cs;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief SERCOM_SPI hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* SPI Mode */\r
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control Register A */\r
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control Register B */\r
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) SPI Debug Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 8) SPI Baud Rate Register */\r
+ RoReg8 Reserved2[0x1];\r
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) SPI Interrupt Enable Clear Register */\r
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) SPI Interrupt Enable Set Register */\r
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) SPI Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved3[0x1];\r
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) SPI Status Register */\r
+ RoReg8 Reserved4[0x2];\r
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) SPI Address Register */\r
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 16) SPI Data Register */\r
+} SercomSpi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief SERCOM_USART hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* USART Mode */\r
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control Register A */\r
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control Register B */\r
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) USART Debug Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 16) USART Baud Rate Register */\r
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) USART Interrupt Enable Clear Register */\r
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) USART Interrupt Enable Set Register */\r
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) USART Interrupt Flag Status and Clear Register */\r
+ RoReg8 Reserved2[0x1];\r
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) USART Status Register */\r
+ RoReg8 Reserved3[0x6];\r
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 16) USART Data Register */\r
+} SercomUsart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */\r
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */\r
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */\r
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */\r
+} Sercom;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_SERCOM_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for SYSCTRL\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SYSCTRL_COMPONENT_\r
+#define _SAMD20_SYSCTRL_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR SYSCTRL */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_SYSCTRL System Control */\r
+/*@{*/\r
+\r
+#define REV_SYSCTRL 0x200\r
+\r
+/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */\r
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */\r
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */\r
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */\r
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */\r
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */\r
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */\r
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */\r
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */\r
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */\r
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */\r
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */\r
+ uint32_t BOD12RDY:1; /*!< bit: 12 BOD12 Ready */\r
+ uint32_t BOD12DET:1; /*!< bit: 13 BOD12 Detection */\r
+ uint32_t B12SRDY:1; /*!< bit: 14 BOD12 Synchronization Ready */\r
+ uint32_t :17; /*!< bit: 15..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready */\r
+#define SYSCTRL_INTENCLR_XOSCRDY (0x1u << SYSCTRL_INTENCLR_XOSCRDY_Pos)\r
+#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready */\r
+#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1u << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)\r
+#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready */\r
+#define SYSCTRL_INTENCLR_OSC32KRDY (0x1u << SYSCTRL_INTENCLR_OSC32KRDY_Pos)\r
+#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready */\r
+#define SYSCTRL_INTENCLR_OSC8MRDY (0x1u << SYSCTRL_INTENCLR_OSC8MRDY_Pos)\r
+#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready */\r
+#define SYSCTRL_INTENCLR_DFLLRDY (0x1u << SYSCTRL_INTENCLR_DFLLRDY_Pos)\r
+#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds */\r
+#define SYSCTRL_INTENCLR_DFLLOOB (0x1u << SYSCTRL_INTENCLR_DFLLOOB_Pos)\r
+#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine */\r
+#define SYSCTRL_INTENCLR_DFLLLCKF (0x1u << SYSCTRL_INTENCLR_DFLLLCKF_Pos)\r
+#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse */\r
+#define SYSCTRL_INTENCLR_DFLLLCKC (0x1u << SYSCTRL_INTENCLR_DFLLLCKC_Pos)\r
+#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped */\r
+#define SYSCTRL_INTENCLR_DFLLRCS (0x1u << SYSCTRL_INTENCLR_DFLLRCS_Pos)\r
+#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready */\r
+#define SYSCTRL_INTENCLR_BOD33RDY (0x1u << SYSCTRL_INTENCLR_BOD33RDY_Pos)\r
+#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection */\r
+#define SYSCTRL_INTENCLR_BOD33DET (0x1u << SYSCTRL_INTENCLR_BOD33DET_Pos)\r
+#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready */\r
+#define SYSCTRL_INTENCLR_B33SRDY (0x1u << SYSCTRL_INTENCLR_B33SRDY_Pos)\r
+#define SYSCTRL_INTENCLR_BOD12RDY_Pos 12 /**< \brief (SYSCTRL_INTENCLR) BOD12 Ready */\r
+#define SYSCTRL_INTENCLR_BOD12RDY (0x1u << SYSCTRL_INTENCLR_BOD12RDY_Pos)\r
+#define SYSCTRL_INTENCLR_BOD12DET_Pos 13 /**< \brief (SYSCTRL_INTENCLR) BOD12 Detection */\r
+#define SYSCTRL_INTENCLR_BOD12DET (0x1u << SYSCTRL_INTENCLR_BOD12DET_Pos)\r
+#define SYSCTRL_INTENCLR_B12SRDY_Pos 14 /**< \brief (SYSCTRL_INTENCLR) BOD12 Synchronization Ready */\r
+#define SYSCTRL_INTENCLR_B12SRDY (0x1u << SYSCTRL_INTENCLR_B12SRDY_Pos)\r
+#define SYSCTRL_INTENCLR_MASK 0x00007FFFu /**< \brief (SYSCTRL_INTENCLR) MASK Register */\r
+\r
+/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */\r
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */\r
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */\r
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */\r
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */\r
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */\r
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */\r
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */\r
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */\r
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */\r
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */\r
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */\r
+ uint32_t BOD12RDY:1; /*!< bit: 12 BOD12 Ready */\r
+ uint32_t BOD12DET:1; /*!< bit: 13 BOD12 Detection */\r
+ uint32_t B12SRDY:1; /*!< bit: 14 BOD12 Synchronization Ready */\r
+ uint32_t :17; /*!< bit: 15..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set Register */\r
+#define SYSCTRL_INTENSET_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready */\r
+#define SYSCTRL_INTENSET_XOSCRDY (0x1u << SYSCTRL_INTENSET_XOSCRDY_Pos)\r
+#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready */\r
+#define SYSCTRL_INTENSET_XOSC32KRDY (0x1u << SYSCTRL_INTENSET_XOSC32KRDY_Pos)\r
+#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready */\r
+#define SYSCTRL_INTENSET_OSC32KRDY (0x1u << SYSCTRL_INTENSET_OSC32KRDY_Pos)\r
+#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready */\r
+#define SYSCTRL_INTENSET_OSC8MRDY (0x1u << SYSCTRL_INTENSET_OSC8MRDY_Pos)\r
+#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready */\r
+#define SYSCTRL_INTENSET_DFLLRDY (0x1u << SYSCTRL_INTENSET_DFLLRDY_Pos)\r
+#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds */\r
+#define SYSCTRL_INTENSET_DFLLOOB (0x1u << SYSCTRL_INTENSET_DFLLOOB_Pos)\r
+#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine */\r
+#define SYSCTRL_INTENSET_DFLLLCKF (0x1u << SYSCTRL_INTENSET_DFLLLCKF_Pos)\r
+#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse */\r
+#define SYSCTRL_INTENSET_DFLLLCKC (0x1u << SYSCTRL_INTENSET_DFLLLCKC_Pos)\r
+#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped */\r
+#define SYSCTRL_INTENSET_DFLLRCS (0x1u << SYSCTRL_INTENSET_DFLLRCS_Pos)\r
+#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready */\r
+#define SYSCTRL_INTENSET_BOD33RDY (0x1u << SYSCTRL_INTENSET_BOD33RDY_Pos)\r
+#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection */\r
+#define SYSCTRL_INTENSET_BOD33DET (0x1u << SYSCTRL_INTENSET_BOD33DET_Pos)\r
+#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready */\r
+#define SYSCTRL_INTENSET_B33SRDY (0x1u << SYSCTRL_INTENSET_B33SRDY_Pos)\r
+#define SYSCTRL_INTENSET_BOD12RDY_Pos 12 /**< \brief (SYSCTRL_INTENSET) BOD12 Ready */\r
+#define SYSCTRL_INTENSET_BOD12RDY (0x1u << SYSCTRL_INTENSET_BOD12RDY_Pos)\r
+#define SYSCTRL_INTENSET_BOD12DET_Pos 13 /**< \brief (SYSCTRL_INTENSET) BOD12 Detection */\r
+#define SYSCTRL_INTENSET_BOD12DET (0x1u << SYSCTRL_INTENSET_BOD12DET_Pos)\r
+#define SYSCTRL_INTENSET_B12SRDY_Pos 14 /**< \brief (SYSCTRL_INTENSET) BOD12 Synchronization Ready */\r
+#define SYSCTRL_INTENSET_B12SRDY (0x1u << SYSCTRL_INTENSET_B12SRDY_Pos)\r
+#define SYSCTRL_INTENSET_MASK 0x00007FFFu /**< \brief (SYSCTRL_INTENSET) MASK Register */\r
+\r
+/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */\r
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */\r
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */\r
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */\r
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */\r
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */\r
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */\r
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */\r
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */\r
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */\r
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */\r
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */\r
+ uint32_t BOD12RDY:1; /*!< bit: 12 BOD12 Ready */\r
+ uint32_t BOD12DET:1; /*!< bit: 13 BOD12 Detection */\r
+ uint32_t B12SRDY:1; /*!< bit: 14 BOD12 Synchronization Ready */\r
+ uint32_t :17; /*!< bit: 15..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */\r
+#define SYSCTRL_INTFLAG_XOSCRDY (0x1u << SYSCTRL_INTFLAG_XOSCRDY_Pos)\r
+#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */\r
+#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1u << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)\r
+#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */\r
+#define SYSCTRL_INTFLAG_OSC32KRDY (0x1u << SYSCTRL_INTFLAG_OSC32KRDY_Pos)\r
+#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */\r
+#define SYSCTRL_INTFLAG_OSC8MRDY (0x1u << SYSCTRL_INTFLAG_OSC8MRDY_Pos)\r
+#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */\r
+#define SYSCTRL_INTFLAG_DFLLRDY (0x1u << SYSCTRL_INTFLAG_DFLLRDY_Pos)\r
+#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */\r
+#define SYSCTRL_INTFLAG_DFLLOOB (0x1u << SYSCTRL_INTFLAG_DFLLOOB_Pos)\r
+#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */\r
+#define SYSCTRL_INTFLAG_DFLLLCKF (0x1u << SYSCTRL_INTFLAG_DFLLLCKF_Pos)\r
+#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */\r
+#define SYSCTRL_INTFLAG_DFLLLCKC (0x1u << SYSCTRL_INTFLAG_DFLLLCKC_Pos)\r
+#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */\r
+#define SYSCTRL_INTFLAG_DFLLRCS (0x1u << SYSCTRL_INTFLAG_DFLLRCS_Pos)\r
+#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */\r
+#define SYSCTRL_INTFLAG_BOD33RDY (0x1u << SYSCTRL_INTFLAG_BOD33RDY_Pos)\r
+#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */\r
+#define SYSCTRL_INTFLAG_BOD33DET (0x1u << SYSCTRL_INTFLAG_BOD33DET_Pos)\r
+#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */\r
+#define SYSCTRL_INTFLAG_B33SRDY (0x1u << SYSCTRL_INTFLAG_B33SRDY_Pos)\r
+#define SYSCTRL_INTFLAG_BOD12RDY_Pos 12 /**< \brief (SYSCTRL_INTFLAG) BOD12 Ready */\r
+#define SYSCTRL_INTFLAG_BOD12RDY (0x1u << SYSCTRL_INTFLAG_BOD12RDY_Pos)\r
+#define SYSCTRL_INTFLAG_BOD12DET_Pos 13 /**< \brief (SYSCTRL_INTFLAG) BOD12 Detection */\r
+#define SYSCTRL_INTFLAG_BOD12DET (0x1u << SYSCTRL_INTFLAG_BOD12DET_Pos)\r
+#define SYSCTRL_INTFLAG_B12SRDY_Pos 14 /**< \brief (SYSCTRL_INTFLAG) BOD12 Synchronization Ready */\r
+#define SYSCTRL_INTFLAG_B12SRDY (0x1u << SYSCTRL_INTFLAG_B12SRDY_Pos)\r
+#define SYSCTRL_INTFLAG_MASK 0x00007FFFu /**< \brief (SYSCTRL_INTFLAG) MASK Register */\r
+\r
+/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */\r
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */\r
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */\r
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */\r
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */\r
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */\r
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */\r
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */\r
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */\r
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */\r
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */\r
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */\r
+ uint32_t BOD12RDY:1; /*!< bit: 12 BOD12 Ready */\r
+ uint32_t BOD12DET:1; /*!< bit: 13 BOD12 Detection */\r
+ uint32_t B12SRDY:1; /*!< bit: 14 BOD12 Synchronization Ready */\r
+ uint32_t :17; /*!< bit: 15..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_PCLKSR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status Register */\r
+#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status Register */\r
+\r
+#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */\r
+#define SYSCTRL_PCLKSR_XOSCRDY (0x1u << SYSCTRL_PCLKSR_XOSCRDY_Pos)\r
+#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */\r
+#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1u << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)\r
+#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */\r
+#define SYSCTRL_PCLKSR_OSC32KRDY (0x1u << SYSCTRL_PCLKSR_OSC32KRDY_Pos)\r
+#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */\r
+#define SYSCTRL_PCLKSR_OSC8MRDY (0x1u << SYSCTRL_PCLKSR_OSC8MRDY_Pos)\r
+#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */\r
+#define SYSCTRL_PCLKSR_DFLLRDY (0x1u << SYSCTRL_PCLKSR_DFLLRDY_Pos)\r
+#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */\r
+#define SYSCTRL_PCLKSR_DFLLOOB (0x1u << SYSCTRL_PCLKSR_DFLLOOB_Pos)\r
+#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */\r
+#define SYSCTRL_PCLKSR_DFLLLCKF (0x1u << SYSCTRL_PCLKSR_DFLLLCKF_Pos)\r
+#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */\r
+#define SYSCTRL_PCLKSR_DFLLLCKC (0x1u << SYSCTRL_PCLKSR_DFLLLCKC_Pos)\r
+#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */\r
+#define SYSCTRL_PCLKSR_DFLLRCS (0x1u << SYSCTRL_PCLKSR_DFLLRCS_Pos)\r
+#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */\r
+#define SYSCTRL_PCLKSR_BOD33RDY (0x1u << SYSCTRL_PCLKSR_BOD33RDY_Pos)\r
+#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */\r
+#define SYSCTRL_PCLKSR_BOD33DET (0x1u << SYSCTRL_PCLKSR_BOD33DET_Pos)\r
+#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */\r
+#define SYSCTRL_PCLKSR_B33SRDY (0x1u << SYSCTRL_PCLKSR_B33SRDY_Pos)\r
+#define SYSCTRL_PCLKSR_BOD12RDY_Pos 12 /**< \brief (SYSCTRL_PCLKSR) BOD12 Ready */\r
+#define SYSCTRL_PCLKSR_BOD12RDY (0x1u << SYSCTRL_PCLKSR_BOD12RDY_Pos)\r
+#define SYSCTRL_PCLKSR_BOD12DET_Pos 13 /**< \brief (SYSCTRL_PCLKSR) BOD12 Detection */\r
+#define SYSCTRL_PCLKSR_BOD12DET (0x1u << SYSCTRL_PCLKSR_BOD12DET_Pos)\r
+#define SYSCTRL_PCLKSR_B12SRDY_Pos 14 /**< \brief (SYSCTRL_PCLKSR) BOD12 Synchronization Ready */\r
+#define SYSCTRL_PCLKSR_B12SRDY (0x1u << SYSCTRL_PCLKSR_B12SRDY_Pos)\r
+#define SYSCTRL_PCLKSR_MASK 0x00007FFFu /**< \brief (SYSCTRL_PCLKSR) MASK Register */\r
+\r
+/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) XOSC Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t :1; /*!< bit: 0 Reserved */\r
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */\r
+ uint16_t :3; /*!< bit: 3.. 5 Reserved */\r
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */\r
+ uint16_t ONDEMAND:1; /*!< bit: 7 Enable on Demand */\r
+ uint16_t GAIN:3; /*!< bit: 8..10 Gain Value */\r
+ uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */\r
+ uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SYSCTRL_XOSC_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) XOSC Control Register */\r
+#define SYSCTRL_XOSC_RESETVALUE 0x0080 /**< \brief (SYSCTRL_XOSC reset_value) XOSC Control Register */\r
+\r
+#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Enable */\r
+#define SYSCTRL_XOSC_ENABLE (0x1u << SYSCTRL_XOSC_ENABLE_Pos)\r
+#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */\r
+#define SYSCTRL_XOSC_XTALEN (0x1u << SYSCTRL_XOSC_XTALEN_Pos)\r
+#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run during Standby */\r
+#define SYSCTRL_XOSC_RUNSTDBY (0x1u << SYSCTRL_XOSC_RUNSTDBY_Pos)\r
+#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) Enable on Demand */\r
+#define SYSCTRL_XOSC_ONDEMAND (0x1u << SYSCTRL_XOSC_ONDEMAND_Pos)\r
+#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Gain Value */\r
+#define SYSCTRL_XOSC_GAIN_Msk (0x7u << SYSCTRL_XOSC_GAIN_Pos)\r
+#define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))\r
+#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */\r
+#define SYSCTRL_XOSC_AMPGC (0x1u << SYSCTRL_XOSC_AMPGC_Pos)\r
+#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */\r
+#define SYSCTRL_XOSC_STARTUP_Msk (0xFu << SYSCTRL_XOSC_STARTUP_Pos)\r
+#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))\r
+#define SYSCTRL_XOSC_MASK 0xFFC6u /**< \brief (SYSCTRL_XOSC) MASK Register */\r
+\r
+/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) XOSC32K Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t :1; /*!< bit: 0 Reserved */\r
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */\r
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */\r
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */\r
+ uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */\r
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */\r
+ uint16_t ONDEMAND:1; /*!< bit: 7 Enable on Demand */\r
+ uint16_t STARTUP:3; /*!< bit: 8..10 Start-Up Time */\r
+ uint16_t :1; /*!< bit: 11 Reserved */\r
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */\r
+ uint16_t :3; /*!< bit: 13..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SYSCTRL_XOSC32K_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) XOSC32K Control Register */\r
+#define SYSCTRL_XOSC32K_RESETVALUE 0x0080 /**< \brief (SYSCTRL_XOSC32K reset_value) XOSC32K Control Register */\r
+\r
+#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Enable */\r
+#define SYSCTRL_XOSC32K_ENABLE (0x1u << SYSCTRL_XOSC32K_ENABLE_Pos)\r
+#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */\r
+#define SYSCTRL_XOSC32K_XTALEN (0x1u << SYSCTRL_XOSC32K_XTALEN_Pos)\r
+#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */\r
+#define SYSCTRL_XOSC32K_EN32K (0x1u << SYSCTRL_XOSC32K_EN32K_Pos)\r
+#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */\r
+#define SYSCTRL_XOSC32K_EN1K (0x1u << SYSCTRL_XOSC32K_EN1K_Pos)\r
+#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */\r
+#define SYSCTRL_XOSC32K_AAMPEN (0x1u << SYSCTRL_XOSC32K_AAMPEN_Pos)\r
+#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run during Standby */\r
+#define SYSCTRL_XOSC32K_RUNSTDBY (0x1u << SYSCTRL_XOSC32K_RUNSTDBY_Pos)\r
+#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) Enable on Demand */\r
+#define SYSCTRL_XOSC32K_ONDEMAND (0x1u << SYSCTRL_XOSC32K_ONDEMAND_Pos)\r
+#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Start-Up Time */\r
+#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7u << SYSCTRL_XOSC32K_STARTUP_Pos)\r
+#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))\r
+#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */\r
+#define SYSCTRL_XOSC32K_WRTLOCK (0x1u << SYSCTRL_XOSC32K_WRTLOCK_Pos)\r
+#define SYSCTRL_XOSC32K_MASK 0x17FEu /**< \brief (SYSCTRL_XOSC32K) MASK Register */\r
+\r
+/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) OSC32K Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :1; /*!< bit: 0 Reserved */\r
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */\r
+ uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */\r
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */\r
+ uint32_t ONDEMAND:1; /*!< bit: 7 Enable on Demand */\r
+ uint32_t STARTUP:3; /*!< bit: 8..10 Start-Up Time */\r
+ uint32_t :1; /*!< bit: 11 Reserved */\r
+ uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */\r
+ uint32_t :3; /*!< bit: 13..15 Reserved */\r
+ uint32_t CALIB:7; /*!< bit: 16..22 Calibration Value */\r
+ uint32_t :9; /*!< bit: 23..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_OSC32K_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) OSC32K Control Register */\r
+#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080 /**< \brief (SYSCTRL_OSC32K reset_value) OSC32K Control Register */\r
+\r
+#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Enable */\r
+#define SYSCTRL_OSC32K_ENABLE (0x1u << SYSCTRL_OSC32K_ENABLE_Pos)\r
+#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */\r
+#define SYSCTRL_OSC32K_EN32K (0x1u << SYSCTRL_OSC32K_EN32K_Pos)\r
+#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */\r
+#define SYSCTRL_OSC32K_EN1K (0x1u << SYSCTRL_OSC32K_EN1K_Pos)\r
+#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run during Standby */\r
+#define SYSCTRL_OSC32K_RUNSTDBY (0x1u << SYSCTRL_OSC32K_RUNSTDBY_Pos)\r
+#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) Enable on Demand */\r
+#define SYSCTRL_OSC32K_ONDEMAND (0x1u << SYSCTRL_OSC32K_ONDEMAND_Pos)\r
+#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Start-Up Time */\r
+#define SYSCTRL_OSC32K_STARTUP_Msk (0x7u << SYSCTRL_OSC32K_STARTUP_Pos)\r
+#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))\r
+#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */\r
+#define SYSCTRL_OSC32K_WRTLOCK (0x1u << SYSCTRL_OSC32K_WRTLOCK_Pos)\r
+#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Calibration Value */\r
+#define SYSCTRL_OSC32K_CALIB_Msk (0x7Fu << SYSCTRL_OSC32K_CALIB_Pos)\r
+#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))\r
+#define SYSCTRL_OSC32K_MASK 0x007F17CEu /**< \brief (SYSCTRL_OSC32K) MASK Register */\r
+\r
+/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) OSCULP32K Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CALIB:5; /*!< bit: 0.. 4 Calibration Value */\r
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */\r
+ uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SYSCTRL_OSCULP32K_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) OSCULP32K Control Register */\r
+#define SYSCTRL_OSCULP32K_RESETVALUE 0x0F /**< \brief (SYSCTRL_OSCULP32K reset_value) OSCULP32K Control Register */\r
+\r
+#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Calibration Value */\r
+#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Fu << SYSCTRL_OSCULP32K_CALIB_Pos)\r
+#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))\r
+#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */\r
+#define SYSCTRL_OSCULP32K_WRTLOCK (0x1u << SYSCTRL_OSCULP32K_WRTLOCK_Pos)\r
+#define SYSCTRL_OSCULP32K_MASK 0x9Fu /**< \brief (SYSCTRL_OSCULP32K) MASK Register */\r
+\r
+/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) OSC8M Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :1; /*!< bit: 0 Reserved */\r
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */\r
+ uint32_t ONDEMAND:1; /*!< bit: 7 Enable on Demand */\r
+ uint32_t PRESC:2; /*!< bit: 8.. 9 Prescaler Select */\r
+ uint32_t :6; /*!< bit: 10..15 Reserved */\r
+ uint32_t CALIB:12; /*!< bit: 16..27 Calibration Value */\r
+ uint32_t :2; /*!< bit: 28..29 Reserved */\r
+ uint32_t FRANGE:2; /*!< bit: 30..31 Frequency Range */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_OSC8M_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) OSC8M Control Register A */\r
+#define SYSCTRL_OSC8M_RESETVALUE 0x00000080 /**< \brief (SYSCTRL_OSC8M reset_value) OSC8M Control Register A */\r
+\r
+#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Enable */\r
+#define SYSCTRL_OSC8M_ENABLE (0x1u << SYSCTRL_OSC8M_ENABLE_Pos)\r
+#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run during Standby */\r
+#define SYSCTRL_OSC8M_RUNSTDBY (0x1u << SYSCTRL_OSC8M_RUNSTDBY_Pos)\r
+#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) Enable on Demand */\r
+#define SYSCTRL_OSC8M_ONDEMAND (0x1u << SYSCTRL_OSC8M_ONDEMAND_Pos)\r
+#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Prescaler Select */\r
+#define SYSCTRL_OSC8M_PRESC_Msk (0x3u << SYSCTRL_OSC8M_PRESC_Pos)\r
+#define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))\r
+#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Calibration Value */\r
+#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFu << SYSCTRL_OSC8M_CALIB_Pos)\r
+#define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))\r
+#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Frequency Range */\r
+#define SYSCTRL_OSC8M_FRANGE_Msk (0x3u << SYSCTRL_OSC8M_FRANGE_Pos)\r
+#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))\r
+#define SYSCTRL_OSC8M_MASK 0xCFFF03C2u /**< \brief (SYSCTRL_OSC8M) MASK Register */\r
+\r
+/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL Config Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t :1; /*!< bit: 0 Reserved */\r
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint16_t MODE:1; /*!< bit: 2 Mode Selection */\r
+ uint16_t STABLE:1; /*!< bit: 3 Stable Frequency */\r
+ uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */\r
+ uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */\r
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */\r
+ uint16_t ONDEMAND:1; /*!< bit: 7 Enable on Demand */\r
+ uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */\r
+ uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */\r
+ uint16_t :6; /*!< bit: 10..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SYSCTRL_DFLLCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL Config Register */\r
+#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080 /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL Config Register */\r
+\r
+#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) Enable */\r
+#define SYSCTRL_DFLLCTRL_ENABLE (0x1u << SYSCTRL_DFLLCTRL_ENABLE_Pos)\r
+#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Mode Selection */\r
+#define SYSCTRL_DFLLCTRL_MODE (0x1u << SYSCTRL_DFLLCTRL_MODE_Pos)\r
+#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable Frequency */\r
+#define SYSCTRL_DFLLCTRL_STABLE (0x1u << SYSCTRL_DFLLCTRL_STABLE_Pos)\r
+#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */\r
+#define SYSCTRL_DFLLCTRL_LLAW (0x1u << SYSCTRL_DFLLCTRL_LLAW_Pos)\r
+#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */\r
+#define SYSCTRL_DFLLCTRL_USBCRM (0x1u << SYSCTRL_DFLLCTRL_USBCRM_Pos)\r
+#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run during Standby */\r
+#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1u << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)\r
+#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) Enable on Demand */\r
+#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1u << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)\r
+#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */\r
+#define SYSCTRL_DFLLCTRL_CCDIS (0x1u << SYSCTRL_DFLLCTRL_CCDIS_Pos)\r
+#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */\r
+#define SYSCTRL_DFLLCTRL_QLDIS (0x1u << SYSCTRL_DFLLCTRL_QLDIS_Pos)\r
+#define SYSCTRL_DFLLCTRL_MASK 0x03FEu /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */\r
+\r
+/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL Calibration Value Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t FINE:8; /*!< bit: 0.. 7 Fine Calibration Value */\r
+ uint32_t COARSE:5; /*!< bit: 8..12 Coarse Calibration Value */\r
+ uint32_t :3; /*!< bit: 13..15 Reserved */\r
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_DFLLVAL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL Calibration Value Register */\r
+#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL Calibration Value Register */\r
+\r
+#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Calibration Value */\r
+#define SYSCTRL_DFLLVAL_FINE_Msk (0xFFu << SYSCTRL_DFLLVAL_FINE_Pos)\r
+#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))\r
+#define SYSCTRL_DFLLVAL_COARSE_Pos 8 /**< \brief (SYSCTRL_DFLLVAL) Coarse Calibration Value */\r
+#define SYSCTRL_DFLLVAL_COARSE_Msk (0x1Fu << SYSCTRL_DFLLVAL_COARSE_Pos)\r
+#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))\r
+#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */\r
+#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFu << SYSCTRL_DFLLVAL_DIFF_Pos)\r
+#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))\r
+#define SYSCTRL_DFLLVAL_MASK 0xFFFF1FFFu /**< \brief (SYSCTRL_DFLLVAL) MASK Register */\r
+\r
+/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL Multiplier Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t MUL:16; /*!< bit: 0..15 Multiplication Value */\r
+ uint32_t FSTEP:8; /*!< bit: 16..23 Maximum Fine Step Size */\r
+ uint32_t CSTEP:5; /*!< bit: 24..28 Maximum Coarse Step Size */\r
+ uint32_t :3; /*!< bit: 29..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_DFLLMUL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL Multiplier Register */\r
+#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL Multiplier Register */\r
+\r
+#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) Multiplication Value */\r
+#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFu << SYSCTRL_DFLLMUL_MUL_Pos)\r
+#define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))\r
+#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Maximum Fine Step Size */\r
+#define SYSCTRL_DFLLMUL_FSTEP_Msk (0xFFu << SYSCTRL_DFLLMUL_FSTEP_Pos)\r
+#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))\r
+#define SYSCTRL_DFLLMUL_CSTEP_Pos 24 /**< \brief (SYSCTRL_DFLLMUL) Maximum Coarse Step Size */\r
+#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x1Fu << SYSCTRL_DFLLMUL_CSTEP_Pos)\r
+#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))\r
+#define SYSCTRL_DFLLMUL_MASK 0x1FFFFFFFu /**< \brief (SYSCTRL_DFLLMUL) MASK Register */\r
+\r
+/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL Synchronization Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */\r
+ uint8_t READREQ:1; /*!< bit: 7 Read Request Synchronization */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} SYSCTRL_DFLLSYNC_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL Synchronization Register */\r
+#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00 /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL Synchronization Register */\r
+\r
+#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request Synchronization */\r
+#define SYSCTRL_DFLLSYNC_READREQ (0x1u << SYSCTRL_DFLLSYNC_READREQ_Pos)\r
+#define SYSCTRL_DFLLSYNC_MASK 0x80u /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */\r
+\r
+/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) BOD33 Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :1; /*!< bit: 0 Reserved */\r
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */\r
+ uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */\r
+ uint32_t :1; /*!< bit: 5 Reserved */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */\r
+ uint32_t :1; /*!< bit: 7 Reserved */\r
+ uint32_t MODE:1; /*!< bit: 8 Operation Modes */\r
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */\r
+ uint32_t :2; /*!< bit: 10..11 Reserved */\r
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */\r
+ uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */\r
+ uint32_t :10; /*!< bit: 22..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_BOD33_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) BOD33 Control Register */\r
+\r
+#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */\r
+#define SYSCTRL_BOD33_ENABLE (0x1u << SYSCTRL_BOD33_ENABLE_Pos)\r
+#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis Enable */\r
+#define SYSCTRL_BOD33_HYST (0x1u << SYSCTRL_BOD33_HYST_Pos)\r
+#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) Action when Threshold Crossed */\r
+#define SYSCTRL_BOD33_ACTION_Msk (0x3u << SYSCTRL_BOD33_ACTION_Pos)\r
+#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))\r
+#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run during Standby */\r
+#define SYSCTRL_BOD33_RUNSTDBY (0x1u << SYSCTRL_BOD33_RUNSTDBY_Pos)\r
+#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Modes */\r
+#define SYSCTRL_BOD33_MODE (0x1u << SYSCTRL_BOD33_MODE_Pos)\r
+#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */\r
+#define SYSCTRL_BOD33_CEN (0x1u << SYSCTRL_BOD33_CEN_Pos)\r
+#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */\r
+#define SYSCTRL_BOD33_PSEL_Msk (0xFu << SYSCTRL_BOD33_PSEL_Pos)\r
+#define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))\r
+#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) Threshold Level */\r
+#define SYSCTRL_BOD33_LEVEL_Msk (0x3Fu << SYSCTRL_BOD33_LEVEL_Pos)\r
+#define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))\r
+#define SYSCTRL_BOD33_MASK 0x003FF35Eu /**< \brief (SYSCTRL_BOD33) MASK Register */\r
+\r
+/* -------- SYSCTRL_BOD12 : (SYSCTRL Offset: 0x38) (R/W 32) BOD12 Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :1; /*!< bit: 0 Reserved */\r
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */\r
+ uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */\r
+ uint32_t :1; /*!< bit: 5 Reserved */\r
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */\r
+ uint32_t :1; /*!< bit: 7 Reserved */\r
+ uint32_t MODE:1; /*!< bit: 8 Operation Modes */\r
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */\r
+ uint32_t :2; /*!< bit: 10..11 Reserved */\r
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */\r
+ uint32_t LEVEL:5; /*!< bit: 16..20 Threshold Level */\r
+ uint32_t :11; /*!< bit: 21..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_BOD12_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_BOD12_OFFSET 0x38 /**< \brief (SYSCTRL_BOD12 offset) BOD12 Control Register */\r
+\r
+#define SYSCTRL_BOD12_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD12) Enable */\r
+#define SYSCTRL_BOD12_ENABLE (0x1u << SYSCTRL_BOD12_ENABLE_Pos)\r
+#define SYSCTRL_BOD12_HYST_Pos 2 /**< \brief (SYSCTRL_BOD12) Hysteresis Enable */\r
+#define SYSCTRL_BOD12_HYST (0x1u << SYSCTRL_BOD12_HYST_Pos)\r
+#define SYSCTRL_BOD12_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD12) Action when Threshold Crossed */\r
+#define SYSCTRL_BOD12_ACTION_Msk (0x3u << SYSCTRL_BOD12_ACTION_Pos)\r
+#define SYSCTRL_BOD12_ACTION(value) ((SYSCTRL_BOD12_ACTION_Msk & ((value) << SYSCTRL_BOD12_ACTION_Pos)))\r
+#define SYSCTRL_BOD12_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD12) Run during Standby */\r
+#define SYSCTRL_BOD12_RUNSTDBY (0x1u << SYSCTRL_BOD12_RUNSTDBY_Pos)\r
+#define SYSCTRL_BOD12_MODE_Pos 8 /**< \brief (SYSCTRL_BOD12) Operation Modes */\r
+#define SYSCTRL_BOD12_MODE (0x1u << SYSCTRL_BOD12_MODE_Pos)\r
+#define SYSCTRL_BOD12_CEN_Pos 9 /**< \brief (SYSCTRL_BOD12) Clock Enable */\r
+#define SYSCTRL_BOD12_CEN (0x1u << SYSCTRL_BOD12_CEN_Pos)\r
+#define SYSCTRL_BOD12_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD12) Prescaler Select */\r
+#define SYSCTRL_BOD12_PSEL_Msk (0xFu << SYSCTRL_BOD12_PSEL_Pos)\r
+#define SYSCTRL_BOD12_PSEL(value) ((SYSCTRL_BOD12_PSEL_Msk & ((value) << SYSCTRL_BOD12_PSEL_Pos)))\r
+#define SYSCTRL_BOD12_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD12) Threshold Level */\r
+#define SYSCTRL_BOD12_LEVEL_Msk (0x1Fu << SYSCTRL_BOD12_LEVEL_Pos)\r
+#define SYSCTRL_BOD12_LEVEL(value) ((SYSCTRL_BOD12_LEVEL_Msk & ((value) << SYSCTRL_BOD12_LEVEL_Pos)))\r
+#define SYSCTRL_BOD12_MASK 0x001FF35Eu /**< \brief (SYSCTRL_BOD12) MASK Register */\r
+\r
+/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) VREG Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t :1; /*!< bit: 0 Reserved */\r
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */\r
+ uint16_t VDDMON:2; /*!< bit: 4.. 5 Enable reset on core supply failure */\r
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */\r
+ uint16_t :1; /*!< bit: 7 Reserved */\r
+ uint16_t LEVEL:3; /*!< bit: 8..10 Output Voltage Level */\r
+ uint16_t :1; /*!< bit: 11 Reserved */\r
+ uint16_t CALIB:3; /*!< bit: 12..14 Calibration Value */\r
+ uint16_t :1; /*!< bit: 15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} SYSCTRL_VREG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) VREG Control Register */\r
+#define SYSCTRL_VREG_RESETVALUE 0x0000 /**< \brief (SYSCTRL_VREG reset_value) VREG Control Register */\r
+\r
+#define SYSCTRL_VREG_ENABLE_Pos 1 /**< \brief (SYSCTRL_VREG) Enable */\r
+#define SYSCTRL_VREG_ENABLE (0x1u << SYSCTRL_VREG_ENABLE_Pos)\r
+#define SYSCTRL_VREG_VDDMON_Pos 4 /**< \brief (SYSCTRL_VREG) Enable reset on core supply failure */\r
+#define SYSCTRL_VREG_VDDMON_Msk (0x3u << SYSCTRL_VREG_VDDMON_Pos)\r
+#define SYSCTRL_VREG_VDDMON(value) ((SYSCTRL_VREG_VDDMON_Msk & ((value) << SYSCTRL_VREG_VDDMON_Pos)))\r
+#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run during Standby */\r
+#define SYSCTRL_VREG_RUNSTDBY (0x1u << SYSCTRL_VREG_RUNSTDBY_Pos)\r
+#define SYSCTRL_VREG_LEVEL_Pos 8 /**< \brief (SYSCTRL_VREG) Output Voltage Level */\r
+#define SYSCTRL_VREG_LEVEL_Msk (0x7u << SYSCTRL_VREG_LEVEL_Pos)\r
+#define SYSCTRL_VREG_LEVEL(value) ((SYSCTRL_VREG_LEVEL_Msk & ((value) << SYSCTRL_VREG_LEVEL_Pos)))\r
+#define SYSCTRL_VREG_CALIB_Pos 12 /**< \brief (SYSCTRL_VREG) Calibration Value */\r
+#define SYSCTRL_VREG_CALIB_Msk (0x7u << SYSCTRL_VREG_CALIB_Pos)\r
+#define SYSCTRL_VREG_CALIB(value) ((SYSCTRL_VREG_CALIB_Msk & ((value) << SYSCTRL_VREG_CALIB_Pos)))\r
+#define SYSCTRL_VREG_MASK 0x7772u /**< \brief (SYSCTRL_VREG) MASK Register */\r
+\r
+/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) VREF Control Register A -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t :1; /*!< bit: 0 Reserved */\r
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */\r
+ uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */\r
+ uint32_t :13; /*!< bit: 3..15 Reserved */\r
+ uint32_t CALIB:11; /*!< bit: 16..26 Voltage Reference Calibration Value */\r
+ uint32_t :5; /*!< bit: 27..31 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} SYSCTRL_VREF_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) VREF Control Register A */\r
+#define SYSCTRL_VREF_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_VREF reset_value) VREF Control Register A */\r
+\r
+#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Output Enable */\r
+#define SYSCTRL_VREF_TSEN (0x1u << SYSCTRL_VREF_TSEN_Pos)\r
+#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */\r
+#define SYSCTRL_VREF_BGOUTEN (0x1u << SYSCTRL_VREF_BGOUTEN_Pos)\r
+#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Voltage Reference Calibration Value */\r
+#define SYSCTRL_VREF_CALIB_Msk (0x7FFu << SYSCTRL_VREF_CALIB_Pos)\r
+#define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))\r
+#define SYSCTRL_VREF_MASK 0x07FF0006u /**< \brief (SYSCTRL_VREF) MASK Register */\r
+\r
+/** \brief SYSCTRL hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear Register */\r
+ __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set Register */\r
+ __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear Register */\r
+ __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status Register */\r
+ __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) XOSC Control Register */\r
+ RoReg8 Reserved1[0x2];\r
+ __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) XOSC32K Control Register */\r
+ RoReg8 Reserved2[0x2];\r
+ __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) OSC32K Control Register */\r
+ __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) OSCULP32K Control Register */\r
+ RoReg8 Reserved3[0x3];\r
+ __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) OSC8M Control Register A */\r
+ __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL Config Register */\r
+ RoReg8 Reserved4[0x2];\r
+ __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL Calibration Value Register */\r
+ __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL Multiplier Register */\r
+ __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL Synchronization Register */\r
+ RoReg8 Reserved5[0x3];\r
+ __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) BOD33 Control Register */\r
+ __IO SYSCTRL_BOD12_Type BOD12; /**< \brief Offset: 0x38 (R/W 32) BOD12 Control Register */\r
+ __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) VREG Control Register */\r
+ RoReg8 Reserved6[0x2];\r
+ __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) VREF Control Register A */\r
+} Sysctrl;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_SYSCTRL_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for TC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC_COMPONENT_\r
+#define _SAMD20_TC_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR TC */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_TC Basic Timer Counter */\r
+/*@{*/\r
+\r
+#define REV_TC 0x110\r
+\r
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */\r
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint16_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */\r
+ uint16_t :1; /*!< bit: 4 Reserved */\r
+ uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */\r
+ uint16_t :1; /*!< bit: 7 Reserved */\r
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */\r
+ uint16_t RUNSTDBY:1; /*!< bit: 11 Run during Standby */\r
+ uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */\r
+ uint16_t :2; /*!< bit: 14..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} TC_CTRLA_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A Register */\r
+#define TC_CTRLA_RESETVALUE 0x0000 /**< \brief (TC_CTRLA reset_value) Control A Register */\r
+\r
+#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */\r
+#define TC_CTRLA_SWRST (0x1u << TC_CTRLA_SWRST_Pos)\r
+#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */\r
+#define TC_CTRLA_ENABLE (0x1u << TC_CTRLA_ENABLE_Pos)\r
+#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */\r
+#define TC_CTRLA_MODE_Msk (0x3u << TC_CTRLA_MODE_Pos)\r
+#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))\r
+#define TC_CTRLA_MODE_COUNT16 (0x0u << 2) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_MODE_COUNT8 (0x1u << 2) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_MODE_COUNT32 (0x2u << 2) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */\r
+#define TC_CTRLA_WAVEGEN_Msk (0x3u << TC_CTRLA_WAVEGEN_Pos)\r
+#define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))\r
+#define TC_CTRLA_WAVEGEN_NFRQ (0x0u << 5) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_WAVEGEN_MFRQ (0x1u << 5) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_WAVEGEN_NPWM (0x2u << 5) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_WAVEGEN_MPWM (0x3u << 5) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */\r
+#define TC_CTRLA_PRESCALER_Msk (0x7u << TC_CTRLA_PRESCALER_Pos)\r
+#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))\r
+#define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run during Standby */\r
+#define TC_CTRLA_RUNSTDBY (0x1u << TC_CTRLA_RUNSTDBY_Pos)\r
+#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */\r
+#define TC_CTRLA_PRESCSYNC_Msk (0x3u << TC_CTRLA_PRESCSYNC_Pos)\r
+#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))\r
+#define TC_CTRLA_PRESCSYNC_GCLK (0x0u << 12) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_PRESCSYNC_PRESC (0x1u << 12) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_PRESCSYNC_RESYNC (0x2u << 12) /**< \brief (TC_CTRLA) */\r
+#define TC_CTRLA_MASK 0x3F6Fu /**< \brief (TC_CTRLA) MASK Register */\r
+\r
+/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t ADDR:5; /*!< bit: 0.. 4 Address */\r
+ uint16_t :9; /*!< bit: 5..13 Reserved */\r
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */\r
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} TC_READREQ_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request Register */\r
+#define TC_READREQ_RESETVALUE 0x0000 /**< \brief (TC_READREQ reset_value) Read Request Register */\r
+\r
+#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */\r
+#define TC_READREQ_ADDR_Msk (0x1Fu << TC_READREQ_ADDR_Pos)\r
+#define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))\r
+#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */\r
+#define TC_READREQ_RCONT (0x1u << TC_READREQ_RCONT_Pos)\r
+#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */\r
+#define TC_READREQ_RREQ (0x1u << TC_READREQ_RREQ_Pos)\r
+#define TC_READREQ_MASK 0xC01Fu /**< \brief (TC_READREQ) MASK Register */\r
+\r
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */\r
+ uint8_t :1; /*!< bit: 1 Reserved */\r
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */\r
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */\r
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_CTRLBCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear Register */\r
+#define TC_CTRLBCLR_RESETVALUE 0x02 /**< \brief (TC_CTRLBCLR reset_value) Control B Clear Register */\r
+\r
+#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */\r
+#define TC_CTRLBCLR_DIR (0x1u << TC_CTRLBCLR_DIR_Pos)\r
+#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */\r
+#define TC_CTRLBCLR_ONESHOT (0x1u << TC_CTRLBCLR_ONESHOT_Pos)\r
+#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */\r
+#define TC_CTRLBCLR_CMD_Msk (0x3u << TC_CTRLBCLR_CMD_Pos)\r
+#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))\r
+#define TC_CTRLBCLR_CMD_NONE (0x0u << 6) /**< \brief (TC_CTRLBCLR) */\r
+#define TC_CTRLBCLR_CMD_RETRIGGER (0x1u << 6) /**< \brief (TC_CTRLBCLR) */\r
+#define TC_CTRLBCLR_CMD_STOP (0x2u << 6) /**< \brief (TC_CTRLBCLR) */\r
+#define TC_CTRLBCLR_MASK 0xC5u /**< \brief (TC_CTRLBCLR) MASK Register */\r
+\r
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */\r
+ uint8_t :1; /*!< bit: 1 Reserved */\r
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */\r
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */\r
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_CTRLBSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set Register */\r
+#define TC_CTRLBSET_RESETVALUE 0x00 /**< \brief (TC_CTRLBSET reset_value) Control B Set Register */\r
+\r
+#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */\r
+#define TC_CTRLBSET_DIR (0x1u << TC_CTRLBSET_DIR_Pos)\r
+#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */\r
+#define TC_CTRLBSET_ONESHOT (0x1u << TC_CTRLBSET_ONESHOT_Pos)\r
+#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */\r
+#define TC_CTRLBSET_CMD_Msk (0x3u << TC_CTRLBSET_CMD_Pos)\r
+#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))\r
+#define TC_CTRLBSET_CMD_NONE (0x0u << 6) /**< \brief (TC_CTRLBSET) */\r
+#define TC_CTRLBSET_CMD_RETRIGGER (0x1u << 6) /**< \brief (TC_CTRLBSET) */\r
+#define TC_CTRLBSET_CMD_STOP (0x2u << 6) /**< \brief (TC_CTRLBSET) */\r
+#define TC_CTRLBSET_MASK 0xC5u /**< \brief (TC_CTRLBSET) MASK Register */\r
+\r
+/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable */\r
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */\r
+ uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel Enable */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_CTRLC_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C Register */\r
+#define TC_CTRLC_RESETVALUE 0x00 /**< \brief (TC_CTRLC reset_value) Control C Register */\r
+\r
+#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform Invert Enable */\r
+#define TC_CTRLC_INVEN_Msk (0x3u << TC_CTRLC_INVEN_Pos)\r
+#define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))\r
+#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel Enable */\r
+#define TC_CTRLC_CPTEN_Msk (0x3u << TC_CTRLC_CPTEN_Pos)\r
+#define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))\r
+#define TC_CTRLC_MASK 0x33u /**< \brief (TC_CTRLC) MASK Register */\r
+\r
+/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_DBGCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Register */\r
+#define TC_DBGCTRL_RESETVALUE 0x00 /**< \brief (TC_DBGCTRL reset_value) Debug Register */\r
+\r
+#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */\r
+#define TC_DBGCTRL_DBGRUN (0x1u << TC_DBGCTRL_DBGRUN_Pos)\r
+#define TC_DBGCTRL_MASK 0x01u /**< \brief (TC_DBGCTRL) MASK Register */\r
+\r
+/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */\r
+ uint16_t :1; /*!< bit: 3 Reserved */\r
+ uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */\r
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */\r
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */\r
+ uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */\r
+ uint16_t :3; /*!< bit: 9..11 Reserved */\r
+ uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable */\r
+ uint16_t :2; /*!< bit: 14..15 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} TC_EVCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control Register */\r
+#define TC_EVCTRL_RESETVALUE 0x0000 /**< \brief (TC_EVCTRL reset_value) Event Control Register */\r
+\r
+#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */\r
+#define TC_EVCTRL_EVACT_Msk (0x7u << TC_EVCTRL_EVACT_Pos)\r
+#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))\r
+#define TC_EVCTRL_EVACT_OFF (0x0u << 0) /**< \brief (TC_EVCTRL) */\r
+#define TC_EVCTRL_EVACT_RETRIGGER (0x1u << 0) /**< \brief (TC_EVCTRL) */\r
+#define TC_EVCTRL_EVACT_COUNT (0x2u << 0) /**< \brief (TC_EVCTRL) */\r
+#define TC_EVCTRL_EVACT_START (0x3u << 0) /**< \brief (TC_EVCTRL) */\r
+#define TC_EVCTRL_EVACT_PPW (0x5u << 0) /**< \brief (TC_EVCTRL) */\r
+#define TC_EVCTRL_EVACT_PWP (0x6u << 0) /**< \brief (TC_EVCTRL) */\r
+#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */\r
+#define TC_EVCTRL_TCINV (0x1u << TC_EVCTRL_TCINV_Pos)\r
+#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */\r
+#define TC_EVCTRL_TCEI (0x1u << TC_EVCTRL_TCEI_Pos)\r
+#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */\r
+#define TC_EVCTRL_OVFEO (0x1u << TC_EVCTRL_OVFEO_Pos)\r
+#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable */\r
+#define TC_EVCTRL_MCEO_Msk (0x3u << TC_EVCTRL_MCEO_Pos)\r
+#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))\r
+#define TC_EVCTRL_MASK 0x3137u /**< \brief (TC_EVCTRL) MASK Register */\r
+\r
+/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */\r
+ uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */\r
+ uint8_t :1; /*!< bit: 2 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 3 READY Interrupt Disable */\r
+ uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define TC_INTENCLR_RESETVALUE 0x00 /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */\r
+#define TC_INTENCLR_OVF (0x1u << TC_INTENCLR_OVF_Pos)\r
+#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */\r
+#define TC_INTENCLR_ERR (0x1u << TC_INTENCLR_ERR_Pos)\r
+#define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) READY Interrupt Disable */\r
+#define TC_INTENCLR_SYNCRDY (0x1u << TC_INTENCLR_SYNCRDY_Pos)\r
+#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable */\r
+#define TC_INTENCLR_MC_Msk (0x3u << TC_INTENCLR_MC_Pos)\r
+#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))\r
+#define TC_INTENCLR_MASK 0x3Bu /**< \brief (TC_INTENCLR) MASK Register */\r
+\r
+/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */\r
+ uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */\r
+ uint8_t :1; /*!< bit: 2 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 3 READY Interrupt Enable */\r
+ uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set Register */\r
+#define TC_INTENSET_RESETVALUE 0x00 /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */\r
+#define TC_INTENSET_OVF (0x1u << TC_INTENSET_OVF_Pos)\r
+#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */\r
+#define TC_INTENSET_ERR (0x1u << TC_INTENSET_ERR_Pos)\r
+#define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) READY Interrupt Enable */\r
+#define TC_INTENSET_SYNCRDY (0x1u << TC_INTENSET_SYNCRDY_Pos)\r
+#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable */\r
+#define TC_INTENSET_MC_Msk (0x3u << TC_INTENSET_MC_Pos)\r
+#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))\r
+#define TC_INTENSET_MASK 0x3Bu /**< \brief (TC_INTENSET) MASK Register */\r
+\r
+/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */\r
+ uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */\r
+ uint8_t :1; /*!< bit: 2 Reserved */\r
+ uint8_t SYNCRDY:1; /*!< bit: 3 READY Interrupt Flag */\r
+ uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag */\r
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define TC_INTFLAG_RESETVALUE 0x00 /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */\r
+#define TC_INTFLAG_OVF (0x1u << TC_INTFLAG_OVF_Pos)\r
+#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */\r
+#define TC_INTFLAG_ERR (0x1u << TC_INTFLAG_ERR_Pos)\r
+#define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) READY Interrupt Flag */\r
+#define TC_INTFLAG_SYNCRDY (0x1u << TC_INTFLAG_SYNCRDY_Pos)\r
+#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag */\r
+#define TC_INTFLAG_MC_Msk (0x3u << TC_INTFLAG_MC_Pos)\r
+#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))\r
+#define TC_INTFLAG_MASK 0x3Bu /**< \brief (TC_INTFLAG) MASK Register */\r
+\r
+/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :3; /*!< bit: 0.. 2 Reserved */\r
+ uint8_t STOP:1; /*!< bit: 3 Stop Status Flag */\r
+ uint8_t SLAVE:1; /*!< bit: 4 Slave Status Flag */\r
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */\r
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status Register */\r
+#define TC_STATUS_RESETVALUE 0x08 /**< \brief (TC_STATUS reset_value) Status Register */\r
+\r
+#define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop Status Flag */\r
+#define TC_STATUS_STOP (0x1u << TC_STATUS_STOP_Pos)\r
+#define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave Status Flag */\r
+#define TC_STATUS_SLAVE (0x1u << TC_STATUS_SLAVE_Pos)\r
+#define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy Status */\r
+#define TC_STATUS_SYNCBUSY (0x1u << TC_STATUS_SYNCBUSY_Pos)\r
+#define TC_STATUS_MASK 0x98u /**< \brief (TC_STATUS) MASK Register */\r
+\r
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Count Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_COUNT8_COUNT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count Register */\r
+#define TC_COUNT8_COUNT_RESETVALUE 0x00 /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count Register */\r
+\r
+#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */\r
+#define TC_COUNT8_COUNT_COUNT_Msk (0xFFu << TC_COUNT8_COUNT_COUNT_Pos)\r
+#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))\r
+#define TC_COUNT8_COUNT_MASK 0xFFu /**< \brief (TC_COUNT8_COUNT) MASK Register */\r
+\r
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Count Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} TC_COUNT16_COUNT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count Register */\r
+#define TC_COUNT16_COUNT_RESETVALUE 0x0000 /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count Register */\r
+\r
+#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */\r
+#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFu << TC_COUNT16_COUNT_COUNT_Pos)\r
+#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))\r
+#define TC_COUNT16_COUNT_MASK 0xFFFFu /**< \brief (TC_COUNT16_COUNT) MASK Register */\r
+\r
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Count Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} TC_COUNT32_COUNT_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count Register */\r
+#define TC_COUNT32_COUNT_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count Register */\r
+\r
+#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */\r
+#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFu << TC_COUNT32_COUNT_COUNT_Pos)\r
+#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))\r
+#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_COUNT) MASK Register */\r
+\r
+/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_COUNT8_PER_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Register */\r
+#define TC_COUNT8_PER_RESETVALUE 0xFF /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Register */\r
+\r
+#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */\r
+#define TC_COUNT8_PER_PER_Msk (0xFFu << TC_COUNT8_PER_PER_Pos)\r
+#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))\r
+#define TC_COUNT8_PER_MASK 0xFFu /**< \brief (TC_COUNT8_PER) MASK Register */\r
+\r
+/* -------- TC_COUNT32_PER : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Period Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t PER:32; /*!< bit: 0..31 Period Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} TC_COUNT32_PER_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_COUNT32_PER_OFFSET 0x14 /**< \brief (TC_COUNT32_PER offset) COUNT32 Period Register */\r
+#define TC_COUNT32_PER_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_PER reset_value) COUNT32 Period Register */\r
+\r
+#define TC_COUNT32_PER_PER_Pos 0 /**< \brief (TC_COUNT32_PER) Period Value */\r
+#define TC_COUNT32_PER_PER_Msk (0xFFFFFFFFu << TC_COUNT32_PER_PER_Pos)\r
+#define TC_COUNT32_PER_PER(value) ((TC_COUNT32_PER_PER_Msk & ((value) << TC_COUNT32_PER_PER_Pos)))\r
+#define TC_COUNT32_PER_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_PER) MASK Register */\r
+\r
+/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare and Capture Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} TC_COUNT8_CC_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture Register */\r
+#define TC_COUNT8_CC_RESETVALUE 0x00 /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture Register */\r
+\r
+#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */\r
+#define TC_COUNT8_CC_CC_Msk (0xFFu << TC_COUNT8_CC_CC_Pos)\r
+#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))\r
+#define TC_COUNT8_CC_MASK 0xFFu /**< \brief (TC_COUNT8_CC) MASK Register */\r
+\r
+/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare and Capture Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint16_t reg; /*!< Type used for register access */\r
+} TC_COUNT16_CC_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture Register */\r
+#define TC_COUNT16_CC_RESETVALUE 0x0000 /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture Register */\r
+\r
+#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */\r
+#define TC_COUNT16_CC_CC_Msk (0xFFFFu << TC_COUNT16_CC_CC_Pos)\r
+#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))\r
+#define TC_COUNT16_CC_MASK 0xFFFFu /**< \brief (TC_COUNT16_CC) MASK Register */\r
+\r
+/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare and Capture Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint32_t reg; /*!< Type used for register access */\r
+} TC_COUNT32_CC_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture Register */\r
+#define TC_COUNT32_CC_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture Register */\r
+\r
+#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */\r
+#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFu << TC_COUNT32_CC_CC_Pos)\r
+#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))\r
+#define TC_COUNT32_CC_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_CC) MASK Register */\r
+\r
+/** \brief TC_COUNT8 hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* 8-bit Counter Mode */\r
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A Register */\r
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request Register */\r
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear Register */\r
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set Register */\r
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Register */\r
+ RoReg8 Reserved2[0x1];\r
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control Register */\r
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear Register */\r
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set Register */\r
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear Register */\r
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status Register */\r
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Count Register */\r
+ RoReg8 Reserved3[0x3];\r
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Register */\r
+ RoReg8 Reserved4[0x3];\r
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare and Capture Register [CC8_NUM] */\r
+} TcCount8;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief TC_COUNT16 hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* 16-bit Counter Mode */\r
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A Register */\r
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request Register */\r
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear Register */\r
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set Register */\r
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Register */\r
+ RoReg8 Reserved2[0x1];\r
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control Register */\r
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear Register */\r
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set Register */\r
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear Register */\r
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status Register */\r
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Count Register */\r
+ RoReg8 Reserved3[0x6];\r
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare and Capture Register [CC16_NUM] */\r
+} TcCount16;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/** \brief TC_COUNT32 hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct { /* 32-bit Counter Mode */\r
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A Register */\r
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request Register */\r
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear Register */\r
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set Register */\r
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Register */\r
+ RoReg8 Reserved2[0x1];\r
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control Register */\r
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear Register */\r
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set Register */\r
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear Register */\r
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status Register */\r
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Count Register */\r
+ __IO TC_COUNT32_PER_Type PER; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Period Register */\r
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare and Capture Register [CC32_NUM] */\r
+} TcCount32;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */\r
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */\r
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */\r
+} Tc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_TC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Component description for WDT\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_WDT_COMPONENT_\r
+#define _SAMD20_WDT_COMPONENT_\r
+\r
+/* ========================================================================== */\r
+/** SOFTWARE API DEFINITION FOR WDT */\r
+/* ========================================================================== */\r
+/** \addtogroup SAMD20_WDT Watchdog Timer */\r
+/*@{*/\r
+\r
+#define REV_WDT 0x200\r
+\r
+/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :1; /*!< bit: 0 Reserved */\r
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */\r
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */\r
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */\r
+ uint8_t ALWAYSON:1; /*!< bit: 7 Watchdog Timer Always-On Enable */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} WDT_CTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control Register */\r
+#define WDT_CTRL_RESETVALUE 0x00 /**< \brief (WDT_CTRL reset_value) Control Register */\r
+\r
+#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */\r
+#define WDT_CTRL_ENABLE (0x1u << WDT_CTRL_ENABLE_Pos)\r
+#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */\r
+#define WDT_CTRL_WEN (0x1u << WDT_CTRL_WEN_Pos)\r
+#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Watchdog Timer Always-On Enable */\r
+#define WDT_CTRL_ALWAYSON (0x1u << WDT_CTRL_ALWAYSON_Pos)\r
+#define WDT_CTRL_MASK 0x86u /**< \brief (WDT_CTRL) MASK Register */\r
+\r
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t PER:4; /*!< bit: 0.. 3 Timeout Period */\r
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Watchdow Timer Window Timeout Period */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} WDT_CONFIG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration Register */\r
+#define WDT_CONFIG_RESETVALUE 0xBB /**< \brief (WDT_CONFIG reset_value) Configuration Register */\r
+\r
+#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Timeout Period */\r
+#define WDT_CONFIG_PER_Msk (0xFu << WDT_CONFIG_PER_Pos)\r
+#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))\r
+#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Watchdow Timer Window Timeout Period */\r
+#define WDT_CONFIG_WINDOW_Msk (0xFu << WDT_CONFIG_WINDOW_Pos)\r
+#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))\r
+#define WDT_CONFIG_MASK 0xFFu /**< \brief (WDT_CONFIG) MASK Register */\r
+\r
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Control Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */\r
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} WDT_EWCTRL_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Control Register */\r
+#define WDT_EWCTRL_RESETVALUE 0x0B /**< \brief (WDT_EWCTRL reset_value) Early Warning Control Register */\r
+\r
+#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */\r
+#define WDT_EWCTRL_EWOFFSET_Msk (0xFu << WDT_EWCTRL_EWOFFSET_Pos)\r
+#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))\r
+#define WDT_EWCTRL_MASK 0x0Fu /**< \brief (WDT_EWCTRL) MASK Register */\r
+\r
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Disable */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} WDT_INTENCLR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear Register */\r
+#define WDT_INTENCLR_RESETVALUE 0x00 /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear Register */\r
+\r
+#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Disable */\r
+#define WDT_INTENCLR_EW (0x1u << WDT_INTENCLR_EW_Pos)\r
+#define WDT_INTENCLR_MASK 0x01u /**< \brief (WDT_INTENCLR) MASK Register */\r
+\r
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} WDT_INTENSET_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set Register */\r
+#define WDT_INTENSET_RESETVALUE 0x00 /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set Register */\r
+\r
+#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */\r
+#define WDT_INTENSET_EW (0x1u << WDT_INTENSET_EW_Pos)\r
+#define WDT_INTENSET_MASK 0x01u /**< \brief (WDT_INTENSET) MASK Register */\r
+\r
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Flag */\r
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} WDT_INTFLAG_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear Register */\r
+#define WDT_INTFLAG_RESETVALUE 0x00 /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear Register */\r
+\r
+#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning Interrupt Flag */\r
+#define WDT_INTFLAG_EW (0x1u << WDT_INTFLAG_EW_Pos)\r
+#define WDT_INTFLAG_MASK 0x01u /**< \brief (WDT_INTFLAG) MASK Register */\r
+\r
+/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */\r
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} WDT_STATUS_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status Register */\r
+#define WDT_STATUS_RESETVALUE 0x00 /**< \brief (WDT_STATUS reset_value) Status Register */\r
+\r
+#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */\r
+#define WDT_STATUS_SYNCBUSY (0x1u << WDT_STATUS_SYNCBUSY_Pos)\r
+#define WDT_STATUS_MASK 0x80u /**< \brief (WDT_STATUS) MASK Register */\r
+\r
+/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear Register -------- */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef union {\r
+ struct {\r
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Timer Clears Command Register */\r
+ } bit; /*!< Structure used for bit access */\r
+ uint8_t reg; /*!< Type used for register access */\r
+} WDT_CLEAR_Type;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear Register */\r
+#define WDT_CLEAR_RESETVALUE 0x00 /**< \brief (WDT_CLEAR reset_value) Clear Register */\r
+\r
+#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Timer Clears Command Register */\r
+#define WDT_CLEAR_CLEAR_Msk (0xFFu << WDT_CLEAR_CLEAR_Pos)\r
+#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))\r
+#define WDT_CLEAR_CLEAR_KEY (0xA5u << 0) /**< \brief (WDT_CLEAR) Clear Key */\r
+#define WDT_CLEAR_MASK 0xFFu /**< \brief (WDT_CLEAR) MASK Register */\r
+\r
+/** \brief WDT hardware registers */\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+typedef struct {\r
+ __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control Register */\r
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration Register */\r
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Control Register */\r
+ RoReg8 Reserved1[0x1];\r
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear Register */\r
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set Register */\r
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear Register */\r
+ __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status Register */\r
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear Register */\r
+} Wdt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMD20_WDT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for AC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_AC_INSTANCE_\r
+#define _SAMD20_AC_INSTANCE_\r
+\r
+/* ========== Register definition for AC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A Register */\r
+#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B Register */\r
+#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control Register */\r
+#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear Register */\r
+#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set Register */\r
+#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear Register */\r
+#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A Register */\r
+#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B Register */\r
+#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C Register */\r
+#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control Register */\r
+#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control Register 0 */\r
+#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control Register 1 */\r
+#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler Register 0 */\r
+#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler Register 1 */\r
+#else\r
+#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A Register */\r
+#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B Register */\r
+#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control Register */\r
+#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear Register */\r
+#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set Register */\r
+#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear Register */\r
+#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A Register */\r
+#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B Register */\r
+#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C Register */\r
+#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control Register */\r
+#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control Register 0 */\r
+#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control Register 1 */\r
+#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler Register 0 */\r
+#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for AC peripheral ========== */\r
+#define AC_GCLK_ID_ANA 25\r
+#define AC_GCLK_ID_DIG 24\r
+#define AC_NUM_CMP 2\r
+#define AC_PAIRS 1\r
+\r
+#endif /* _SAMD20_AC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for ADC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_ADC_INSTANCE_\r
+#define _SAMD20_ADC_INSTANCE_\r
+\r
+/* ========== Register definition for ADC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control Register A */\r
+#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control Register */\r
+#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control Register */\r
+#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sample Time Control Register */\r
+#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control Register B */\r
+#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control Register */\r
+#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Control Register B */\r
+#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control Register */\r
+#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control Register */\r
+#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear Register */\r
+#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set Register */\r
+#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear Register */\r
+#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status Register */\r
+#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result Register */\r
+#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold Register */\r
+#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold Register */\r
+#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction Register */\r
+#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction Register */\r
+#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration Register */\r
+#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Register */\r
+#define REG_ADC_TEST (0x4200402BU) /**< \brief (ADC) Test Modes Register */\r
+#define REG_ADC_TESTRESULT (0x4200402CU) /**< \brief (ADC) Test Result Register */\r
+#define REG_ADC_DCFG (0x42004030U) /**< \brief (ADC) Device Configuration */\r
+#else\r
+#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control Register A */\r
+#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control Register */\r
+#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control Register */\r
+#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sample Time Control Register */\r
+#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control Register B */\r
+#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control Register */\r
+#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Control Register B */\r
+#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control Register */\r
+#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control Register */\r
+#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear Register */\r
+#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set Register */\r
+#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear Register */\r
+#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status Register */\r
+#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result Register */\r
+#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold Register */\r
+#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold Register */\r
+#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction Register */\r
+#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction Register */\r
+#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration Register */\r
+#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Register */\r
+#define REG_ADC_TEST (*(RwReg8 *)0x4200402BU) /**< \brief (ADC) Test Modes Register */\r
+#define REG_ADC_TESTRESULT (*(RwReg *)0x4200402CU) /**< \brief (ADC) Test Result Register */\r
+#define REG_ADC_DCFG (*(RwReg8 *)0x42004030U) /**< \brief (ADC) Device Configuration */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for ADC peripheral ========== */\r
+#define ADC_EXTCHANNEL_MSB 19\r
+#define ADC_GCLK_ID 23\r
+#define ADC_RESULT_MSB 15\r
+\r
+#endif /* _SAMD20_ADC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for DAC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_DAC_INSTANCE_\r
+#define _SAMD20_DAC_INSTANCE_\r
+\r
+/* ========== Register definition for DAC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control Register A */\r
+#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control Register B */\r
+#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control Register */\r
+#define REG_DAC_TEST (0x42004803U) /**< \brief (DAC) Test Register */\r
+#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear Register */\r
+#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set Register */\r
+#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear Register */\r
+#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status Register */\r
+#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data Register */\r
+#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer Register */\r
+#else\r
+#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control Register A */\r
+#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control Register B */\r
+#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control Register */\r
+#define REG_DAC_TEST (*(RwReg8 *)0x42004803U) /**< \brief (DAC) Test Register */\r
+#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear Register */\r
+#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set Register */\r
+#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear Register */\r
+#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status Register */\r
+#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data Register */\r
+#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for DAC peripheral ========== */\r
+#define DAC_GCLK_ID 26\r
+\r
+#endif /* _SAMD20_DAC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for DSU\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_DSU_INSTANCE_\r
+#define _SAMD20_DSU_INSTANCE_\r
+\r
+/* ========== Register definition for DSU peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control Register */\r
+#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status Register A */\r
+#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status Register B */\r
+#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address Register */\r
+#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length Register */\r
+#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data Register */\r
+#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel Register 0 */\r
+#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel Register 1 */\r
+#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification Register */\r
+#define REG_DSU_DCFG0 (0x410020F0U) /**< \brief (DSU) Device Configuration Register 0 */\r
+#define REG_DSU_DCFG1 (0x410020F4U) /**< \brief (DSU) Device Configuration Register 1 */\r
+#define REG_DSU_UPTM (0x410020F8U) /**< \brief (DSU) UnProtected Test Mode Register */\r
+#define REG_DSU_TESTMODE (0x410020FCU) /**< \brief (DSU) Test Mode Register */\r
+#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) CoreSight ROM Table Entry Register 0 */\r
+#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) CoreSight ROM Table Entry Register 1 */\r
+#define REG_DSU_END (0x41003008U) /**< \brief (DSU) CoreSight ROM Table End Register */\r
+#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) CoreSight ROM Table Memory Type Register */\r
+#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification Register 4 */\r
+#define REG_DSU_PID5 (0x41003FD4U) /**< \brief (DSU) Peripheral Identification Register 5 */\r
+#define REG_DSU_PID6 (0x41003FD8U) /**< \brief (DSU) Peripheral Identification Register 6 */\r
+#define REG_DSU_PID7 (0x41003FDCU) /**< \brief (DSU) Peripheral Identification Register 7 */\r
+#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification Register 0 */\r
+#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification Register 1 */\r
+#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification Register 2 */\r
+#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification Register 3 */\r
+#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification Register 0 */\r
+#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification Register 1 */\r
+#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification Register 2 */\r
+#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification Register 3 */\r
+#else\r
+#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control Register */\r
+#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status Register A */\r
+#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status Register B */\r
+#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address Register */\r
+#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length Register */\r
+#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data Register */\r
+#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel Register 0 */\r
+#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel Register 1 */\r
+#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification Register */\r
+#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0U) /**< \brief (DSU) Device Configuration Register 0 */\r
+#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4U) /**< \brief (DSU) Device Configuration Register 1 */\r
+#define REG_DSU_UPTM (*(RwReg *)0x410020F8U) /**< \brief (DSU) UnProtected Test Mode Register */\r
+#define REG_DSU_TESTMODE (*(RwReg *)0x410020FCU) /**< \brief (DSU) Test Mode Register */\r
+#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) CoreSight ROM Table Entry Register 0 */\r
+#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) CoreSight ROM Table Entry Register 1 */\r
+#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) CoreSight ROM Table End Register */\r
+#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) CoreSight ROM Table Memory Type Register */\r
+#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification Register 4 */\r
+#define REG_DSU_PID5 (*(RoReg *)0x41003FD4U) /**< \brief (DSU) Peripheral Identification Register 5 */\r
+#define REG_DSU_PID6 (*(RoReg *)0x41003FD8U) /**< \brief (DSU) Peripheral Identification Register 6 */\r
+#define REG_DSU_PID7 (*(RoReg *)0x41003FDCU) /**< \brief (DSU) Peripheral Identification Register 7 */\r
+#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification Register 0 */\r
+#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification Register 1 */\r
+#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification Register 2 */\r
+#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification Register 3 */\r
+#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification Register 0 */\r
+#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification Register 1 */\r
+#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification Register 2 */\r
+#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification Register 3 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for DSU peripheral ========== */\r
+#define DSU_CLK_HSB_ID 3\r
+\r
+#endif /* _SAMD20_DSU_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for EIC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_EIC_INSTANCE_\r
+#define _SAMD20_EIC_INSTANCE_\r
+\r
+/* ========== Register definition for EIC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control Register */\r
+#define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status Register */\r
+#define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) NMI Control Register */\r
+#define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) NMI Interrupt Flag Register */\r
+#define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control Register */\r
+#define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear Register */\r
+#define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set Register */\r
+#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear Register */\r
+#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-up Enable Register */\r
+#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Config Register 0 */\r
+#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Config Register 1 */\r
+#else\r
+#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control Register */\r
+#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status Register */\r
+#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) NMI Control Register */\r
+#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) NMI Interrupt Flag Register */\r
+#define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control Register */\r
+#define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear Register */\r
+#define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set Register */\r
+#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear Register */\r
+#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-up Enable Register */\r
+#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Config Register 0 */\r
+#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Config Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for EIC peripheral ========== */\r
+#define EIC_GCLK_ID 3\r
+#define EIC_NMI_NO_DETECT_ALLOWED 0\r
+#define EIC_NUMBER_OF_CONFIG_REGS 2\r
+#define EIC_NUMBER_OF_INTERRUPTS 16\r
+\r
+#endif /* _SAMD20_EIC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for EVSYS\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_EVSYS_INSTANCE_\r
+#define _SAMD20_EVSYS_INSTANCE_\r
+\r
+/* ========== Register definition for EVSYS peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_EVSYS_CTRL (0x42000400U) /**< \brief (EVSYS) Control Register */\r
+#define REG_EVSYS_CHANNEL (0x42000404U) /**< \brief (EVSYS) Channel Register */\r
+#define REG_EVSYS_USER (0x42000408U) /**< \brief (EVSYS) User Mux Register */\r
+#define REG_EVSYS_CHSTATUS (0x4200040CU) /**< \brief (EVSYS) Channel Status Register */\r
+#define REG_EVSYS_INTENCLR (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear Register */\r
+#define REG_EVSYS_INTENSET (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set Register */\r
+#define REG_EVSYS_INTFLAG (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear Register */\r
+#else\r
+#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control Register */\r
+#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404U) /**< \brief (EVSYS) Channel Register */\r
+#define REG_EVSYS_USER (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Mux Register */\r
+#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CU) /**< \brief (EVSYS) Channel Status Register */\r
+#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear Register */\r
+#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set Register */\r
+#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for EVSYS peripheral ========== */\r
+#define EVSYS_CHANNELS 8\r
+#define EVSYS_CHANNELS_MSB 7\r
+#define EVSYS_EXT_EVT_MSB 0\r
+#define EVSYS_GCLK_ID_0 4\r
+#define EVSYS_GCLK_ID_1 5\r
+#define EVSYS_GCLK_ID_2 6\r
+#define EVSYS_GCLK_ID_3 7\r
+#define EVSYS_GCLK_ID_4 8\r
+#define EVSYS_GCLK_ID_5 9\r
+#define EVSYS_GCLK_ID_6 10\r
+#define EVSYS_GCLK_ID_7 11\r
+#define EVSYS_GCLK_ID_LSB 4\r
+#define EVSYS_GCLK_ID_MSB 11\r
+#define EVSYS_GCLK_ID_SIZE 8\r
+#define EVSYS_GENERATORS 49\r
+#define EVSYS_USERS 14\r
+\r
+// GENERATORS\r
+#define EVSYS_ID_GEN_RTC_CMP_0 1\r
+#define EVSYS_ID_GEN_RTC_CMP_1 2\r
+#define EVSYS_ID_GEN_RTC_OVF 3\r
+#define EVSYS_ID_GEN_RTC_PER_0 4\r
+#define EVSYS_ID_GEN_RTC_PER_1 5\r
+#define EVSYS_ID_GEN_RTC_PER_2 6\r
+#define EVSYS_ID_GEN_RTC_PER_3 7\r
+#define EVSYS_ID_GEN_RTC_PER_4 8\r
+#define EVSYS_ID_GEN_RTC_PER_5 9\r
+#define EVSYS_ID_GEN_RTC_PER_6 10\r
+#define EVSYS_ID_GEN_RTC_PER_7 11\r
+#define EVSYS_ID_GEN_EIC_EXTINT_0 12\r
+#define EVSYS_ID_GEN_EIC_EXTINT_1 13\r
+#define EVSYS_ID_GEN_EIC_EXTINT_2 14\r
+#define EVSYS_ID_GEN_EIC_EXTINT_3 15\r
+#define EVSYS_ID_GEN_EIC_EXTINT_4 16\r
+#define EVSYS_ID_GEN_EIC_EXTINT_5 17\r
+#define EVSYS_ID_GEN_EIC_EXTINT_6 18\r
+#define EVSYS_ID_GEN_EIC_EXTINT_7 19\r
+#define EVSYS_ID_GEN_EIC_EXTINT_8 20\r
+#define EVSYS_ID_GEN_EIC_EXTINT_9 21\r
+#define EVSYS_ID_GEN_EIC_EXTINT_10 22\r
+#define EVSYS_ID_GEN_EIC_EXTINT_11 23\r
+#define EVSYS_ID_GEN_EIC_EXTINT_12 24\r
+#define EVSYS_ID_GEN_EIC_EXTINT_13 25\r
+#define EVSYS_ID_GEN_EIC_EXTINT_14 26\r
+#define EVSYS_ID_GEN_EIC_EXTINT_15 27\r
+#define EVSYS_ID_GEN_TC0_OVF 28\r
+#define EVSYS_ID_GEN_TC0_MCX_0 29\r
+#define EVSYS_ID_GEN_TC0_MCX_1 30\r
+#define EVSYS_ID_GEN_TC1_OVF 31\r
+#define EVSYS_ID_GEN_TC1_MCX_0 32\r
+#define EVSYS_ID_GEN_TC1_MCX_1 33\r
+#define EVSYS_ID_GEN_TC2_OVF 34\r
+#define EVSYS_ID_GEN_TC2_MCX_0 35\r
+#define EVSYS_ID_GEN_TC2_MCX_1 36\r
+#define EVSYS_ID_GEN_TC3_OVF 37\r
+#define EVSYS_ID_GEN_TC3_MCX_0 38\r
+#define EVSYS_ID_GEN_TC3_MCX_1 39\r
+#define EVSYS_ID_GEN_TC4_OVF 40\r
+#define EVSYS_ID_GEN_TC4_MCX_0 41\r
+#define EVSYS_ID_GEN_TC4_MCX_1 42\r
+#define EVSYS_ID_GEN_TC5_OVF 43\r
+#define EVSYS_ID_GEN_TC5_MCX_0 44\r
+#define EVSYS_ID_GEN_TC5_MCX_1 45\r
+#define EVSYS_ID_GEN_TC6_OVF 46\r
+#define EVSYS_ID_GEN_TC6_MCX_0 47\r
+#define EVSYS_ID_GEN_TC6_MCX_1 48\r
+#define EVSYS_ID_GEN_TC7_OVF 49\r
+#define EVSYS_ID_GEN_TC7_MCX_0 50\r
+#define EVSYS_ID_GEN_TC7_MCX_1 51\r
+#define EVSYS_ID_GEN_ADC_RESRDY 52\r
+#define EVSYS_ID_GEN_ADC_WINMON 53\r
+#define EVSYS_ID_GEN_AC_COMP_0 54\r
+#define EVSYS_ID_GEN_AC_COMP_1 55\r
+#define EVSYS_ID_GEN_AC_WIN 56\r
+#define EVSYS_ID_GEN_DAC_EMPTY 57\r
+#define EVSYS_ID_GEN_PTC_EOC 58\r
+#define EVSYS_ID_GEN_PTC_WCOMP 59\r
+\r
+// USERS\r
+#define EVSYS_ID_USER_TC0_EVU 0\r
+#define EVSYS_ID_USER_TC1_EVU 1\r
+#define EVSYS_ID_USER_TC2_EVU 2\r
+#define EVSYS_ID_USER_TC3_EVU 3\r
+#define EVSYS_ID_USER_TC4_EVU 4\r
+#define EVSYS_ID_USER_TC5_EVU 5\r
+#define EVSYS_ID_USER_TC6_EVU 6\r
+#define EVSYS_ID_USER_TC7_EVU 7\r
+#define EVSYS_ID_USER_ADC_START 8\r
+#define EVSYS_ID_USER_ADC_SYNC 9\r
+#define EVSYS_ID_USER_AC_SOC_0 10\r
+#define EVSYS_ID_USER_AC_SOC_1 11\r
+#define EVSYS_ID_USER_DAC_START 12\r
+#define EVSYS_ID_USER_PTC_STCONV 13\r
+\r
+#endif /* _SAMD20_EVSYS_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for GCLK\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_GCLK_INSTANCE_\r
+#define _SAMD20_GCLK_INSTANCE_\r
+\r
+/* ========== Register definition for GCLK peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control Register */\r
+#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status Register */\r
+#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control Register */\r
+#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control Register */\r
+#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division Register */\r
+#else\r
+#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control Register */\r
+#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status Register */\r
+#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control Register */\r
+#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control Register */\r
+#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for GCLK peripheral ========== */\r
+#define GCLK_GEN_NUM_MSB 7\r
+#define GCLK_GEN_SOURCE_NUM_MSB 7\r
+#define GCLK_MAX_DIV_BITS 16\r
+#define GCLK_NUM 28\r
+#define GCLK_SOURCE_DFLL48M 7\r
+#define GCLK_SOURCE_GCLKGEN1 2\r
+#define GCLK_SOURCE_GCLKIN 1\r
+#define GCLK_SOURCE_OSCULP32K 3\r
+#define GCLK_SOURCE_OSC8M 6\r
+#define GCLK_SOURCE_OSC32K 4\r
+#define GCLK_SOURCE_XOSC 0\r
+#define GCLK_SOURCE_XOSC32K 5\r
+\r
+#endif /* _SAMD20_GCLK_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for NVMCTRL\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_NVMCTRL_INSTANCE_\r
+#define _SAMD20_NVMCTRL_INSTANCE_\r
+\r
+/* ========== Register definition for NVMCTRL peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) NVM Control Register A */\r
+#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) NVM Control Register B */\r
+#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) Parameter Register */\r
+#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear Register */\r
+#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set Register */\r
+#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear Register */\r
+#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status Register */\r
+#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address Register */\r
+#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Register */\r
+#else\r
+#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) NVM Control Register A */\r
+#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) NVM Control Register B */\r
+#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) Parameter Register */\r
+#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear Register */\r
+#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set Register */\r
+#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear Register */\r
+#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status Register */\r
+#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address Register */\r
+#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for NVMCTRL peripheral ========== */\r
+#define NVMCTRL_AUX0_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00004000)\r
+#define NVMCTRL_AUX1_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00006000)\r
+#define NVMCTRL_AUX2_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00008000)\r
+#define NVMCTRL_AUX3_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x0000A000)\r
+#define NVMCTRL_CLK_AHB_ID 4\r
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF\r
+#define NVMCTRL_FLASH_SIZE (NVMCTRL_PAGES*NVMCTRL_PAGE_SIZE)\r
+#define NVMCTRL_FUSES_SECURE_NVM \r
+#define NVMCTRL_FUSES_SECURE_RAM \r
+#define NVMCTRL_FUSES_SECURE_STATE \r
+#define NVMCTRL_LOCKBIT_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00002000)\r
+#define NVMCTRL_PAGES 4096\r
+#define NVMCTRL_PAGE_HW (NVMCTRL_PAGE_SIZE/2)\r
+#define NVMCTRL_PAGE_SIZE (1<<NVMCTRL_PSZ_BITS)\r
+#define NVMCTRL_PAGE_W (NVMCTRL_PAGE_SIZE/4)\r
+#define NVMCTRL_PMSB 3\r
+#define NVMCTRL_PSZ_BITS 6\r
+#define NVMCTRL_ROW_PAGES (NVMCTRL_ROW_SIZE/NVMCTRL_PAGE_SIZE)\r
+#define NVMCTRL_ROW_SIZE (NVMCTRL_PAGE_SIZE*4)\r
+#define NVMCTRL_USER_PAGE_ADDRESS (FLASH_ADDR + NVMCTRL_USER_PAGE_OFFSET)\r
+#define NVMCTRL_USER_PAGE_OFFSET 0x00800000\r
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF\r
+\r
+#endif /* _SAMD20_NVMCTRL_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for PAC0\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_PAC0_INSTANCE_\r
+#define _SAMD20_PAC0_INSTANCE_\r
+\r
+/* ========== Register definition for PAC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear Register */\r
+#define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set Register */\r
+#else\r
+#define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear Register */\r
+#define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for PAC0 peripheral ========== */\r
+#define PAC0_WPROT_DEFAULT_VAL 0x00000000\r
+\r
+#endif /* _SAMD20_PAC0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for PAC1\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_PAC1_INSTANCE_\r
+#define _SAMD20_PAC1_INSTANCE_\r
+\r
+/* ========== Register definition for PAC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear Register */\r
+#define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set Register */\r
+#else\r
+#define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear Register */\r
+#define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for PAC1 peripheral ========== */\r
+#define PAC1_WPROT_DEFAULT_VAL 0x00000002\r
+\r
+#endif /* _SAMD20_PAC1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for PAC2\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_PAC2_INSTANCE_\r
+#define _SAMD20_PAC2_INSTANCE_\r
+\r
+/* ========== Register definition for PAC2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear Register */\r
+#define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set Register */\r
+#else\r
+#define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear Register */\r
+#define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for PAC2 peripheral ========== */\r
+#define PAC2_WPROT_DEFAULT_VAL 0x00100000\r
+\r
+#endif /* _SAMD20_PAC2_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for PM\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_PM_INSTANCE_\r
+#define _SAMD20_PM_INSTANCE_\r
+\r
+/* ========== Register definition for PM peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control Register */\r
+#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Register */\r
+#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */\r
+#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */\r
+#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */\r
+#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */\r
+#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */\r
+#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */\r
+#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */\r
+#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */\r
+#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear Register */\r
+#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set Register */\r
+#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear Register */\r
+#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause Register */\r
+#else\r
+#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control Register */\r
+#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Register */\r
+#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */\r
+#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */\r
+#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */\r
+#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */\r
+#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */\r
+#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */\r
+#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */\r
+#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */\r
+#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear Register */\r
+#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set Register */\r
+#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear Register */\r
+#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for PM peripheral ========== */\r
+#define PM_CTRL_MCSEL_DFLL48M 3\r
+#define PM_CTRL_MCSEL_GCLK 0\r
+#define PM_CTRL_MCSEL_OSC8M 1\r
+#define PM_CTRL_MCSEL_XOSC 2\r
+#define PM_PM_CLK_APB_NUM 2\r
+\r
+#endif /* _SAMD20_PM_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for PORT\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_PORT_INSTANCE_\r
+#define _SAMD20_PORT_INSTANCE_\r
+\r
+/* ========== Register definition for PORT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction Register 0 */\r
+#define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear Register 0 */\r
+#define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set Register 0 */\r
+#define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle Register 0 */\r
+#define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value Register 0 */\r
+#define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear Register 0 */\r
+#define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set Register 0 */\r
+#define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle Register 0 */\r
+#define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value Register 0 */\r
+#define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control Register 0 */\r
+#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration Register 0 */\r
+#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing Register 0 */\r
+#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration Register 0 */\r
+#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction Register 1 */\r
+#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear Register 1 */\r
+#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set Register 1 */\r
+#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle Register 1 */\r
+#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value Register 1 */\r
+#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear Register 1 */\r
+#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set Register 1 */\r
+#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle Register 1 */\r
+#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value Register 1 */\r
+#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control Register 1 */\r
+#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration Register 1 */\r
+#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing Register 1 */\r
+#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration Register 1 */\r
+#else\r
+#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction Register 0 */\r
+#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear Register 0 */\r
+#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set Register 0 */\r
+#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle Register 0 */\r
+#define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value Register 0 */\r
+#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear Register 0 */\r
+#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set Register 0 */\r
+#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle Register 0 */\r
+#define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value Register 0 */\r
+#define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control Register 0 */\r
+#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration Register 0 */\r
+#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing Register 0 */\r
+#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration Register 0 */\r
+#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction Register 1 */\r
+#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear Register 1 */\r
+#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set Register 1 */\r
+#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle Register 1 */\r
+#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value Register 1 */\r
+#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear Register 1 */\r
+#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set Register 1 */\r
+#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle Register 1 */\r
+#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value Register 1 */\r
+#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control Register 1 */\r
+#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration Register 1 */\r
+#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing Register 1 */\r
+#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for PORT peripheral ========== */\r
+#define PORT_BITS 64\r
+#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }\r
+#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_DRVSTR_IMPLEMENTED { 0x00000000, 0x00000000 }\r
+#define PORT_GROUPS 2\r
+#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }\r
+#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000 }\r
+#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }\r
+#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }\r
+#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }\r
+#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000 }\r
+#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F }\r
+#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000 }\r
+#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F }\r
+#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000 }\r
+#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000 }\r
+#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }\r
+#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }\r
+#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000 }\r
+#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000 }\r
+\r
+#endif /* _SAMD20_PORT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for RTC\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_RTC_INSTANCE_\r
+#define _SAMD20_RTC_INSTANCE_\r
+\r
+/* ========== Register definition for RTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control Register */\r
+#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control Register */\r
+#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control Register */\r
+#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request Register */\r
+#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control Register */\r
+#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control Register */\r
+#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control Register */\r
+#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear Register */\r
+#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear Register */\r
+#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear Register */\r
+#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set Register */\r
+#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set Register */\r
+#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set Register */\r
+#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear Register */\r
+#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear Register */\r
+#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear Register */\r
+#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Register */\r
+#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction Register */\r
+#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Count Register */\r
+#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Count Register */\r
+#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Register */\r
+#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Period Register */\r
+#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare Register 0 */\r
+#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare Register 0 */\r
+#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare Register 1 */\r
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm Register 0 */\r
+#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm Mask Register 0 */\r
+#else\r
+#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control Register */\r
+#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control Register */\r
+#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control Register */\r
+#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request Register */\r
+#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control Register */\r
+#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control Register */\r
+#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control Register */\r
+#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear Register */\r
+#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear Register */\r
+#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear Register */\r
+#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set Register */\r
+#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set Register */\r
+#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set Register */\r
+#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear Register */\r
+#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear Register */\r
+#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear Register */\r
+#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Register */\r
+#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction Register */\r
+#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Count Register */\r
+#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Count Register */\r
+#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Register */\r
+#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Period Register */\r
+#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare Register 0 */\r
+#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare Register 0 */\r
+#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare Register 1 */\r
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm Register 0 */\r
+#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm Mask Register 0 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for RTC peripheral ========== */\r
+#define RTC_GCLK_ID 2\r
+#define RTC_NUM_OF_ALARMS 1\r
+#define RTC_NUM_OF_COMP16 2\r
+#define RTC_NUM_OF_COMP32 1\r
+\r
+#endif /* _SAMD20_RTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for SERCOM0\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SERCOM0_INSTANCE_\r
+#define _SAMD20_SERCOM0_INSTANCE_\r
+\r
+/* ========== Register definition for SERCOM0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control Register A */\r
+#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control Register A */\r
+#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control Register A */\r
+#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control Register A */\r
+#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control Register B */\r
+#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control Register B */\r
+#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control Register B */\r
+#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control Register B */\r
+#define REG_SERCOM0_I2CM_DBGCTRL (0x42000808U) /**< \brief (SERCOM0) I2CM Debug Register */\r
+#define REG_SERCOM0_SPI_DBGCTRL (0x42000808U) /**< \brief (SERCOM0) SPI Debug Register */\r
+#define REG_SERCOM0_USART_DBGCTRL (0x42000808U) /**< \brief (SERCOM0) USART Debug Register */\r
+#define REG_SERCOM0_I2CM_BAUD (0x4200080AU) /**< \brief (SERCOM0) I2CM Baud Rate Register */\r
+#define REG_SERCOM0_SPI_BAUD (0x4200080AU) /**< \brief (SERCOM0) SPI Baud Rate Register */\r
+#define REG_SERCOM0_USART_BAUD (0x4200080AU) /**< \brief (SERCOM0) USART Baud Rate Register */\r
+#define REG_SERCOM0_I2CM_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM0_I2CS_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM0_SPI_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM0_USART_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM0_I2CM_INTENSET (0x4200080DU) /**< \brief (SERCOM0) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM0_I2CS_INTENSET (0x4200080DU) /**< \brief (SERCOM0) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM0_SPI_INTENSET (0x4200080DU) /**< \brief (SERCOM0) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM0_USART_INTENSET (0x4200080DU) /**< \brief (SERCOM0) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM0_I2CM_INTFLAG (0x4200080EU) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM0_I2CS_INTFLAG (0x4200080EU) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM0_SPI_INTFLAG (0x4200080EU) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM0_USART_INTFLAG (0x4200080EU) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM0_I2CM_STATUS (0x42000810U) /**< \brief (SERCOM0) I2CM Status Register */\r
+#define REG_SERCOM0_I2CS_STATUS (0x42000810U) /**< \brief (SERCOM0) I2CS Status Register */\r
+#define REG_SERCOM0_SPI_STATUS (0x42000810U) /**< \brief (SERCOM0) SPI Status Register */\r
+#define REG_SERCOM0_USART_STATUS (0x42000810U) /**< \brief (SERCOM0) USART Status Register */\r
+#define REG_SERCOM0_I2CM_ADDR (0x42000814U) /**< \brief (SERCOM0) I2CM Address Register */\r
+#define REG_SERCOM0_I2CS_ADDR (0x42000814U) /**< \brief (SERCOM0) I2CS Address Register */\r
+#define REG_SERCOM0_SPI_ADDR (0x42000814U) /**< \brief (SERCOM0) SPI Address Register */\r
+#define REG_SERCOM0_I2CM_DATA (0x42000818U) /**< \brief (SERCOM0) I2CM Data Register */\r
+#define REG_SERCOM0_I2CS_DATA (0x42000818U) /**< \brief (SERCOM0) I2CS Data Register */\r
+#define REG_SERCOM0_SPI_DATA (0x42000818U) /**< \brief (SERCOM0) SPI Data Register */\r
+#define REG_SERCOM0_USART_DATA (0x42000818U) /**< \brief (SERCOM0) USART Data Register */\r
+#else\r
+#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control Register A */\r
+#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control Register A */\r
+#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control Register A */\r
+#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control Register A */\r
+#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control Register B */\r
+#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control Register B */\r
+#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control Register B */\r
+#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control Register B */\r
+#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) I2CM Debug Register */\r
+#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) SPI Debug Register */\r
+#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) USART Debug Register */\r
+#define REG_SERCOM0_I2CM_BAUD (*(RwReg16*)0x4200080AU) /**< \brief (SERCOM0) I2CM Baud Rate Register */\r
+#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080AU) /**< \brief (SERCOM0) SPI Baud Rate Register */\r
+#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080AU) /**< \brief (SERCOM0) USART Baud Rate Register */\r
+#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) I2CM Status Register */\r
+#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) I2CS Status Register */\r
+#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) SPI Status Register */\r
+#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) USART Status Register */\r
+#define REG_SERCOM0_I2CM_ADDR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Address Register */\r
+#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000814U) /**< \brief (SERCOM0) I2CS Address Register */\r
+#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000814U) /**< \brief (SERCOM0) SPI Address Register */\r
+#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Data Register */\r
+#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Data Register */\r
+#define REG_SERCOM0_SPI_DATA (*(RwReg16*)0x42000818U) /**< \brief (SERCOM0) SPI Data Register */\r
+#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000818U) /**< \brief (SERCOM0) USART Data Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for SERCOM0 peripheral ========== */\r
+#define SERCOM0_GCLK_ID_CORE 13\r
+#define SERCOM0_GCLK_ID_SLOW 12\r
+#define SERCOM0_INT_MSB 3\r
+#define SERCOM0_PMSB 3\r
+\r
+#endif /* _SAMD20_SERCOM0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for SERCOM1\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SERCOM1_INSTANCE_\r
+#define _SAMD20_SERCOM1_INSTANCE_\r
+\r
+/* ========== Register definition for SERCOM1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control Register A */\r
+#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control Register A */\r
+#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control Register A */\r
+#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control Register A */\r
+#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control Register B */\r
+#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control Register B */\r
+#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control Register B */\r
+#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control Register B */\r
+#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C08U) /**< \brief (SERCOM1) I2CM Debug Register */\r
+#define REG_SERCOM1_SPI_DBGCTRL (0x42000C08U) /**< \brief (SERCOM1) SPI Debug Register */\r
+#define REG_SERCOM1_USART_DBGCTRL (0x42000C08U) /**< \brief (SERCOM1) USART Debug Register */\r
+#define REG_SERCOM1_I2CM_BAUD (0x42000C0AU) /**< \brief (SERCOM1) I2CM Baud Rate Register */\r
+#define REG_SERCOM1_SPI_BAUD (0x42000C0AU) /**< \brief (SERCOM1) SPI Baud Rate Register */\r
+#define REG_SERCOM1_USART_BAUD (0x42000C0AU) /**< \brief (SERCOM1) USART Baud Rate Register */\r
+#define REG_SERCOM1_I2CM_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM1_I2CS_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM1_SPI_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM1_USART_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM1_I2CM_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM1_I2CS_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM1_SPI_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM1_USART_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM1_I2CM_INTFLAG (0x42000C0EU) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM1_I2CS_INTFLAG (0x42000C0EU) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM1_SPI_INTFLAG (0x42000C0EU) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM1_USART_INTFLAG (0x42000C0EU) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM1_I2CM_STATUS (0x42000C10U) /**< \brief (SERCOM1) I2CM Status Register */\r
+#define REG_SERCOM1_I2CS_STATUS (0x42000C10U) /**< \brief (SERCOM1) I2CS Status Register */\r
+#define REG_SERCOM1_SPI_STATUS (0x42000C10U) /**< \brief (SERCOM1) SPI Status Register */\r
+#define REG_SERCOM1_USART_STATUS (0x42000C10U) /**< \brief (SERCOM1) USART Status Register */\r
+#define REG_SERCOM1_I2CM_ADDR (0x42000C14U) /**< \brief (SERCOM1) I2CM Address Register */\r
+#define REG_SERCOM1_I2CS_ADDR (0x42000C14U) /**< \brief (SERCOM1) I2CS Address Register */\r
+#define REG_SERCOM1_SPI_ADDR (0x42000C14U) /**< \brief (SERCOM1) SPI Address Register */\r
+#define REG_SERCOM1_I2CM_DATA (0x42000C18U) /**< \brief (SERCOM1) I2CM Data Register */\r
+#define REG_SERCOM1_I2CS_DATA (0x42000C18U) /**< \brief (SERCOM1) I2CS Data Register */\r
+#define REG_SERCOM1_SPI_DATA (0x42000C18U) /**< \brief (SERCOM1) SPI Data Register */\r
+#define REG_SERCOM1_USART_DATA (0x42000C18U) /**< \brief (SERCOM1) USART Data Register */\r
+#else\r
+#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control Register A */\r
+#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control Register A */\r
+#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control Register A */\r
+#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control Register A */\r
+#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control Register B */\r
+#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control Register B */\r
+#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control Register B */\r
+#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control Register B */\r
+#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) I2CM Debug Register */\r
+#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) SPI Debug Register */\r
+#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) USART Debug Register */\r
+#define REG_SERCOM1_I2CM_BAUD (*(RwReg16*)0x42000C0AU) /**< \brief (SERCOM1) I2CM Baud Rate Register */\r
+#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0AU) /**< \brief (SERCOM1) SPI Baud Rate Register */\r
+#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0AU) /**< \brief (SERCOM1) USART Baud Rate Register */\r
+#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) I2CM Status Register */\r
+#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) I2CS Status Register */\r
+#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) SPI Status Register */\r
+#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) USART Status Register */\r
+#define REG_SERCOM1_I2CM_ADDR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Address Register */\r
+#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C14U) /**< \brief (SERCOM1) I2CS Address Register */\r
+#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C14U) /**< \brief (SERCOM1) SPI Address Register */\r
+#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Data Register */\r
+#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Data Register */\r
+#define REG_SERCOM1_SPI_DATA (*(RwReg16*)0x42000C18U) /**< \brief (SERCOM1) SPI Data Register */\r
+#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C18U) /**< \brief (SERCOM1) USART Data Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for SERCOM1 peripheral ========== */\r
+#define SERCOM1_GCLK_ID_CORE 14\r
+#define SERCOM1_GCLK_ID_SLOW 12\r
+#define SERCOM1_INT_MSB 3\r
+#define SERCOM1_PMSB 3\r
+\r
+#endif /* _SAMD20_SERCOM1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for SERCOM2\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SERCOM2_INSTANCE_\r
+#define _SAMD20_SERCOM2_INSTANCE_\r
+\r
+/* ========== Register definition for SERCOM2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control Register A */\r
+#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control Register A */\r
+#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control Register A */\r
+#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control Register A */\r
+#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control Register B */\r
+#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control Register B */\r
+#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control Register B */\r
+#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control Register B */\r
+#define REG_SERCOM2_I2CM_DBGCTRL (0x42001008U) /**< \brief (SERCOM2) I2CM Debug Register */\r
+#define REG_SERCOM2_SPI_DBGCTRL (0x42001008U) /**< \brief (SERCOM2) SPI Debug Register */\r
+#define REG_SERCOM2_USART_DBGCTRL (0x42001008U) /**< \brief (SERCOM2) USART Debug Register */\r
+#define REG_SERCOM2_I2CM_BAUD (0x4200100AU) /**< \brief (SERCOM2) I2CM Baud Rate Register */\r
+#define REG_SERCOM2_SPI_BAUD (0x4200100AU) /**< \brief (SERCOM2) SPI Baud Rate Register */\r
+#define REG_SERCOM2_USART_BAUD (0x4200100AU) /**< \brief (SERCOM2) USART Baud Rate Register */\r
+#define REG_SERCOM2_I2CM_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM2_I2CS_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM2_SPI_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM2_USART_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM2_I2CM_INTENSET (0x4200100DU) /**< \brief (SERCOM2) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM2_I2CS_INTENSET (0x4200100DU) /**< \brief (SERCOM2) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM2_SPI_INTENSET (0x4200100DU) /**< \brief (SERCOM2) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM2_USART_INTENSET (0x4200100DU) /**< \brief (SERCOM2) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM2_I2CM_INTFLAG (0x4200100EU) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM2_I2CS_INTFLAG (0x4200100EU) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM2_SPI_INTFLAG (0x4200100EU) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM2_USART_INTFLAG (0x4200100EU) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM2_I2CM_STATUS (0x42001010U) /**< \brief (SERCOM2) I2CM Status Register */\r
+#define REG_SERCOM2_I2CS_STATUS (0x42001010U) /**< \brief (SERCOM2) I2CS Status Register */\r
+#define REG_SERCOM2_SPI_STATUS (0x42001010U) /**< \brief (SERCOM2) SPI Status Register */\r
+#define REG_SERCOM2_USART_STATUS (0x42001010U) /**< \brief (SERCOM2) USART Status Register */\r
+#define REG_SERCOM2_I2CM_ADDR (0x42001014U) /**< \brief (SERCOM2) I2CM Address Register */\r
+#define REG_SERCOM2_I2CS_ADDR (0x42001014U) /**< \brief (SERCOM2) I2CS Address Register */\r
+#define REG_SERCOM2_SPI_ADDR (0x42001014U) /**< \brief (SERCOM2) SPI Address Register */\r
+#define REG_SERCOM2_I2CM_DATA (0x42001018U) /**< \brief (SERCOM2) I2CM Data Register */\r
+#define REG_SERCOM2_I2CS_DATA (0x42001018U) /**< \brief (SERCOM2) I2CS Data Register */\r
+#define REG_SERCOM2_SPI_DATA (0x42001018U) /**< \brief (SERCOM2) SPI Data Register */\r
+#define REG_SERCOM2_USART_DATA (0x42001018U) /**< \brief (SERCOM2) USART Data Register */\r
+#else\r
+#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control Register A */\r
+#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control Register A */\r
+#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control Register A */\r
+#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control Register A */\r
+#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control Register B */\r
+#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control Register B */\r
+#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control Register B */\r
+#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control Register B */\r
+#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) I2CM Debug Register */\r
+#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) SPI Debug Register */\r
+#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) USART Debug Register */\r
+#define REG_SERCOM2_I2CM_BAUD (*(RwReg16*)0x4200100AU) /**< \brief (SERCOM2) I2CM Baud Rate Register */\r
+#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100AU) /**< \brief (SERCOM2) SPI Baud Rate Register */\r
+#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100AU) /**< \brief (SERCOM2) USART Baud Rate Register */\r
+#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) I2CM Status Register */\r
+#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) I2CS Status Register */\r
+#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) SPI Status Register */\r
+#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) USART Status Register */\r
+#define REG_SERCOM2_I2CM_ADDR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Address Register */\r
+#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001014U) /**< \brief (SERCOM2) I2CS Address Register */\r
+#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001014U) /**< \brief (SERCOM2) SPI Address Register */\r
+#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Data Register */\r
+#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Data Register */\r
+#define REG_SERCOM2_SPI_DATA (*(RwReg16*)0x42001018U) /**< \brief (SERCOM2) SPI Data Register */\r
+#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001018U) /**< \brief (SERCOM2) USART Data Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for SERCOM2 peripheral ========== */\r
+#define SERCOM2_GCLK_ID_CORE 15\r
+#define SERCOM2_GCLK_ID_SLOW 12\r
+#define SERCOM2_INT_MSB 3\r
+#define SERCOM2_PMSB 3\r
+\r
+#endif /* _SAMD20_SERCOM2_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for SERCOM3\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SERCOM3_INSTANCE_\r
+#define _SAMD20_SERCOM3_INSTANCE_\r
+\r
+/* ========== Register definition for SERCOM3 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control Register A */\r
+#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control Register A */\r
+#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control Register A */\r
+#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control Register A */\r
+#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control Register B */\r
+#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control Register B */\r
+#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control Register B */\r
+#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control Register B */\r
+#define REG_SERCOM3_I2CM_DBGCTRL (0x42001408U) /**< \brief (SERCOM3) I2CM Debug Register */\r
+#define REG_SERCOM3_SPI_DBGCTRL (0x42001408U) /**< \brief (SERCOM3) SPI Debug Register */\r
+#define REG_SERCOM3_USART_DBGCTRL (0x42001408U) /**< \brief (SERCOM3) USART Debug Register */\r
+#define REG_SERCOM3_I2CM_BAUD (0x4200140AU) /**< \brief (SERCOM3) I2CM Baud Rate Register */\r
+#define REG_SERCOM3_SPI_BAUD (0x4200140AU) /**< \brief (SERCOM3) SPI Baud Rate Register */\r
+#define REG_SERCOM3_USART_BAUD (0x4200140AU) /**< \brief (SERCOM3) USART Baud Rate Register */\r
+#define REG_SERCOM3_I2CM_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM3_I2CS_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM3_SPI_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM3_USART_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM3_I2CM_INTENSET (0x4200140DU) /**< \brief (SERCOM3) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM3_I2CS_INTENSET (0x4200140DU) /**< \brief (SERCOM3) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM3_SPI_INTENSET (0x4200140DU) /**< \brief (SERCOM3) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM3_USART_INTENSET (0x4200140DU) /**< \brief (SERCOM3) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM3_I2CM_INTFLAG (0x4200140EU) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM3_I2CS_INTFLAG (0x4200140EU) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM3_SPI_INTFLAG (0x4200140EU) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM3_USART_INTFLAG (0x4200140EU) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM3_I2CM_STATUS (0x42001410U) /**< \brief (SERCOM3) I2CM Status Register */\r
+#define REG_SERCOM3_I2CS_STATUS (0x42001410U) /**< \brief (SERCOM3) I2CS Status Register */\r
+#define REG_SERCOM3_SPI_STATUS (0x42001410U) /**< \brief (SERCOM3) SPI Status Register */\r
+#define REG_SERCOM3_USART_STATUS (0x42001410U) /**< \brief (SERCOM3) USART Status Register */\r
+#define REG_SERCOM3_I2CM_ADDR (0x42001414U) /**< \brief (SERCOM3) I2CM Address Register */\r
+#define REG_SERCOM3_I2CS_ADDR (0x42001414U) /**< \brief (SERCOM3) I2CS Address Register */\r
+#define REG_SERCOM3_SPI_ADDR (0x42001414U) /**< \brief (SERCOM3) SPI Address Register */\r
+#define REG_SERCOM3_I2CM_DATA (0x42001418U) /**< \brief (SERCOM3) I2CM Data Register */\r
+#define REG_SERCOM3_I2CS_DATA (0x42001418U) /**< \brief (SERCOM3) I2CS Data Register */\r
+#define REG_SERCOM3_SPI_DATA (0x42001418U) /**< \brief (SERCOM3) SPI Data Register */\r
+#define REG_SERCOM3_USART_DATA (0x42001418U) /**< \brief (SERCOM3) USART Data Register */\r
+#else\r
+#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control Register A */\r
+#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control Register A */\r
+#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control Register A */\r
+#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control Register A */\r
+#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control Register B */\r
+#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control Register B */\r
+#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control Register B */\r
+#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control Register B */\r
+#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) I2CM Debug Register */\r
+#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) SPI Debug Register */\r
+#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) USART Debug Register */\r
+#define REG_SERCOM3_I2CM_BAUD (*(RwReg16*)0x4200140AU) /**< \brief (SERCOM3) I2CM Baud Rate Register */\r
+#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140AU) /**< \brief (SERCOM3) SPI Baud Rate Register */\r
+#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140AU) /**< \brief (SERCOM3) USART Baud Rate Register */\r
+#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) I2CM Status Register */\r
+#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) I2CS Status Register */\r
+#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) SPI Status Register */\r
+#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) USART Status Register */\r
+#define REG_SERCOM3_I2CM_ADDR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Address Register */\r
+#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001414U) /**< \brief (SERCOM3) I2CS Address Register */\r
+#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001414U) /**< \brief (SERCOM3) SPI Address Register */\r
+#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Data Register */\r
+#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Data Register */\r
+#define REG_SERCOM3_SPI_DATA (*(RwReg16*)0x42001418U) /**< \brief (SERCOM3) SPI Data Register */\r
+#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001418U) /**< \brief (SERCOM3) USART Data Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for SERCOM3 peripheral ========== */\r
+#define SERCOM3_GCLK_ID_CORE 16\r
+#define SERCOM3_GCLK_ID_SLOW 12\r
+#define SERCOM3_INT_MSB 3\r
+#define SERCOM3_PMSB 3\r
+\r
+#endif /* _SAMD20_SERCOM3_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for SERCOM4\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SERCOM4_INSTANCE_\r
+#define _SAMD20_SERCOM4_INSTANCE_\r
+\r
+/* ========== Register definition for SERCOM4 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control Register A */\r
+#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control Register A */\r
+#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control Register A */\r
+#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control Register A */\r
+#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control Register B */\r
+#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control Register B */\r
+#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control Register B */\r
+#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control Register B */\r
+#define REG_SERCOM4_I2CM_DBGCTRL (0x42001808U) /**< \brief (SERCOM4) I2CM Debug Register */\r
+#define REG_SERCOM4_SPI_DBGCTRL (0x42001808U) /**< \brief (SERCOM4) SPI Debug Register */\r
+#define REG_SERCOM4_USART_DBGCTRL (0x42001808U) /**< \brief (SERCOM4) USART Debug Register */\r
+#define REG_SERCOM4_I2CM_BAUD (0x4200180AU) /**< \brief (SERCOM4) I2CM Baud Rate Register */\r
+#define REG_SERCOM4_SPI_BAUD (0x4200180AU) /**< \brief (SERCOM4) SPI Baud Rate Register */\r
+#define REG_SERCOM4_USART_BAUD (0x4200180AU) /**< \brief (SERCOM4) USART Baud Rate Register */\r
+#define REG_SERCOM4_I2CM_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM4_I2CS_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM4_SPI_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM4_USART_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM4_I2CM_INTENSET (0x4200180DU) /**< \brief (SERCOM4) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM4_I2CS_INTENSET (0x4200180DU) /**< \brief (SERCOM4) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM4_SPI_INTENSET (0x4200180DU) /**< \brief (SERCOM4) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM4_USART_INTENSET (0x4200180DU) /**< \brief (SERCOM4) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM4_I2CM_INTFLAG (0x4200180EU) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM4_I2CS_INTFLAG (0x4200180EU) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM4_SPI_INTFLAG (0x4200180EU) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM4_USART_INTFLAG (0x4200180EU) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM4_I2CM_STATUS (0x42001810U) /**< \brief (SERCOM4) I2CM Status Register */\r
+#define REG_SERCOM4_I2CS_STATUS (0x42001810U) /**< \brief (SERCOM4) I2CS Status Register */\r
+#define REG_SERCOM4_SPI_STATUS (0x42001810U) /**< \brief (SERCOM4) SPI Status Register */\r
+#define REG_SERCOM4_USART_STATUS (0x42001810U) /**< \brief (SERCOM4) USART Status Register */\r
+#define REG_SERCOM4_I2CM_ADDR (0x42001814U) /**< \brief (SERCOM4) I2CM Address Register */\r
+#define REG_SERCOM4_I2CS_ADDR (0x42001814U) /**< \brief (SERCOM4) I2CS Address Register */\r
+#define REG_SERCOM4_SPI_ADDR (0x42001814U) /**< \brief (SERCOM4) SPI Address Register */\r
+#define REG_SERCOM4_I2CM_DATA (0x42001818U) /**< \brief (SERCOM4) I2CM Data Register */\r
+#define REG_SERCOM4_I2CS_DATA (0x42001818U) /**< \brief (SERCOM4) I2CS Data Register */\r
+#define REG_SERCOM4_SPI_DATA (0x42001818U) /**< \brief (SERCOM4) SPI Data Register */\r
+#define REG_SERCOM4_USART_DATA (0x42001818U) /**< \brief (SERCOM4) USART Data Register */\r
+#else\r
+#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control Register A */\r
+#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control Register A */\r
+#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control Register A */\r
+#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control Register A */\r
+#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control Register B */\r
+#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control Register B */\r
+#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control Register B */\r
+#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control Register B */\r
+#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) I2CM Debug Register */\r
+#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) SPI Debug Register */\r
+#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) USART Debug Register */\r
+#define REG_SERCOM4_I2CM_BAUD (*(RwReg16*)0x4200180AU) /**< \brief (SERCOM4) I2CM Baud Rate Register */\r
+#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180AU) /**< \brief (SERCOM4) SPI Baud Rate Register */\r
+#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180AU) /**< \brief (SERCOM4) USART Baud Rate Register */\r
+#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) I2CM Status Register */\r
+#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) I2CS Status Register */\r
+#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) SPI Status Register */\r
+#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) USART Status Register */\r
+#define REG_SERCOM4_I2CM_ADDR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Address Register */\r
+#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001814U) /**< \brief (SERCOM4) I2CS Address Register */\r
+#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001814U) /**< \brief (SERCOM4) SPI Address Register */\r
+#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Data Register */\r
+#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Data Register */\r
+#define REG_SERCOM4_SPI_DATA (*(RwReg16*)0x42001818U) /**< \brief (SERCOM4) SPI Data Register */\r
+#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001818U) /**< \brief (SERCOM4) USART Data Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for SERCOM4 peripheral ========== */\r
+#define SERCOM4_GCLK_ID_CORE 17\r
+#define SERCOM4_GCLK_ID_SLOW 12\r
+#define SERCOM4_INT_MSB 3\r
+#define SERCOM4_PMSB 3\r
+\r
+#endif /* _SAMD20_SERCOM4_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for SERCOM5\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SERCOM5_INSTANCE_\r
+#define _SAMD20_SERCOM5_INSTANCE_\r
+\r
+/* ========== Register definition for SERCOM5 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control Register A */\r
+#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control Register A */\r
+#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control Register A */\r
+#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control Register A */\r
+#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control Register B */\r
+#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control Register B */\r
+#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control Register B */\r
+#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control Register B */\r
+#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) I2CM Debug Register */\r
+#define REG_SERCOM5_SPI_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) SPI Debug Register */\r
+#define REG_SERCOM5_USART_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) USART Debug Register */\r
+#define REG_SERCOM5_I2CM_BAUD (0x42001C0AU) /**< \brief (SERCOM5) I2CM Baud Rate Register */\r
+#define REG_SERCOM5_SPI_BAUD (0x42001C0AU) /**< \brief (SERCOM5) SPI Baud Rate Register */\r
+#define REG_SERCOM5_USART_BAUD (0x42001C0AU) /**< \brief (SERCOM5) USART Baud Rate Register */\r
+#define REG_SERCOM5_I2CM_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM5_I2CS_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM5_SPI_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM5_USART_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM5_I2CM_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM5_I2CS_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM5_SPI_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM5_USART_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM5_I2CM_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM5_I2CS_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM5_SPI_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM5_USART_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM5_I2CM_STATUS (0x42001C10U) /**< \brief (SERCOM5) I2CM Status Register */\r
+#define REG_SERCOM5_I2CS_STATUS (0x42001C10U) /**< \brief (SERCOM5) I2CS Status Register */\r
+#define REG_SERCOM5_SPI_STATUS (0x42001C10U) /**< \brief (SERCOM5) SPI Status Register */\r
+#define REG_SERCOM5_USART_STATUS (0x42001C10U) /**< \brief (SERCOM5) USART Status Register */\r
+#define REG_SERCOM5_I2CM_ADDR (0x42001C14U) /**< \brief (SERCOM5) I2CM Address Register */\r
+#define REG_SERCOM5_I2CS_ADDR (0x42001C14U) /**< \brief (SERCOM5) I2CS Address Register */\r
+#define REG_SERCOM5_SPI_ADDR (0x42001C14U) /**< \brief (SERCOM5) SPI Address Register */\r
+#define REG_SERCOM5_I2CM_DATA (0x42001C18U) /**< \brief (SERCOM5) I2CM Data Register */\r
+#define REG_SERCOM5_I2CS_DATA (0x42001C18U) /**< \brief (SERCOM5) I2CS Data Register */\r
+#define REG_SERCOM5_SPI_DATA (0x42001C18U) /**< \brief (SERCOM5) SPI Data Register */\r
+#define REG_SERCOM5_USART_DATA (0x42001C18U) /**< \brief (SERCOM5) USART Data Register */\r
+#else\r
+#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control Register A */\r
+#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control Register A */\r
+#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control Register A */\r
+#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control Register A */\r
+#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control Register B */\r
+#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control Register B */\r
+#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control Register B */\r
+#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control Register B */\r
+#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) I2CM Debug Register */\r
+#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) SPI Debug Register */\r
+#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) USART Debug Register */\r
+#define REG_SERCOM5_I2CM_BAUD (*(RwReg16*)0x42001C0AU) /**< \brief (SERCOM5) I2CM Baud Rate Register */\r
+#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0AU) /**< \brief (SERCOM5) SPI Baud Rate Register */\r
+#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0AU) /**< \brief (SERCOM5) USART Baud Rate Register */\r
+#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear Register */\r
+#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear Register */\r
+#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Interrupt Enable Clear Register */\r
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) USART Interrupt Enable Clear Register */\r
+#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) I2CM Interrupt Enable Set Register */\r
+#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) I2CS Interrupt Enable Set Register */\r
+#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) SPI Interrupt Enable Set Register */\r
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) USART Interrupt Enable Set Register */\r
+#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear Register */\r
+#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) I2CM Status Register */\r
+#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) I2CS Status Register */\r
+#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) SPI Status Register */\r
+#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) USART Status Register */\r
+#define REG_SERCOM5_I2CM_ADDR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Address Register */\r
+#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C14U) /**< \brief (SERCOM5) I2CS Address Register */\r
+#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C14U) /**< \brief (SERCOM5) SPI Address Register */\r
+#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Data Register */\r
+#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Data Register */\r
+#define REG_SERCOM5_SPI_DATA (*(RwReg16*)0x42001C18U) /**< \brief (SERCOM5) SPI Data Register */\r
+#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C18U) /**< \brief (SERCOM5) USART Data Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for SERCOM5 peripheral ========== */\r
+#define SERCOM5_GCLK_ID_CORE 18\r
+#define SERCOM5_GCLK_ID_SLOW 12\r
+#define SERCOM5_INT_MSB 3\r
+#define SERCOM5_PMSB 3\r
+\r
+#endif /* _SAMD20_SERCOM5_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for SYSCTRL\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_SYSCTRL_INSTANCE_\r
+#define _SAMD20_SYSCTRL_INSTANCE_\r
+\r
+/* ========== Register definition for SYSCTRL peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear Register */\r
+#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set Register */\r
+#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear Register */\r
+#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status Register */\r
+#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) XOSC Control Register */\r
+#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control Register */\r
+#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) OSC32K Control Register */\r
+#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control Register */\r
+#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) OSC8M Control Register A */\r
+#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL Config Register */\r
+#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value Register */\r
+#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier Register */\r
+#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization Register */\r
+#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) BOD33 Control Register */\r
+#define REG_SYSCTRL_BOD12 (0x40000838U) /**< \brief (SYSCTRL) BOD12 Control Register */\r
+#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) VREG Control Register */\r
+#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) VREF Control Register A */\r
+#else\r
+#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear Register */\r
+#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set Register */\r
+#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear Register */\r
+#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status Register */\r
+#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) XOSC Control Register */\r
+#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control Register */\r
+#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) OSC32K Control Register */\r
+#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control Register */\r
+#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) OSC8M Control Register A */\r
+#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL Config Register */\r
+#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value Register */\r
+#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier Register */\r
+#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization Register */\r
+#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) BOD33 Control Register */\r
+#define REG_SYSCTRL_BOD12 (*(RwReg *)0x40000838U) /**< \brief (SYSCTRL) BOD12 Control Register */\r
+#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) VREG Control Register */\r
+#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) VREF Control Register A */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for SYSCTRL peripheral ========== */\r
+#define SYSCTRL_BGAP_CALIB_MSB 11\r
+#define SYSCTRL_BOD12_CALIB_MSB 4\r
+#define SYSCTRL_BOD33_CALIB_MSB 5\r
+#define SYSCTRL_DFLL48M_COARSE_MSB 4\r
+#define SYSCTRL_DFLL48M_FINE_MSB 7\r
+#define SYSCTRL_DFLL48M_TESTEN_MSB 1\r
+#define SYSCTRL_GCLK_ID_DFLL48 0\r
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6\r
+#define SYSCTRL_POR33_ENTEST_MSB 1\r
+#define SYSCTRL_ULPVREF_DIVLEV_MSB 3\r
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1\r
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2\r
+#define SYSCTRL_VREF_CONTROL_MSB 48\r
+#define SYSCTRL_VREF_STATUS_MSB 7\r
+#define SYSCTRL_VREG_LEVEL_MSB 2\r
+#define SYSCTRL_BOD12_VERSION 0x110\r
+#define SYSCTRL_BOD33_VERSION 0x110\r
+#define SYSCTRL_DFLL48M_VERSION 0x200\r
+#define SYSCTRL_GCLK_VERSION 0x200\r
+#define SYSCTRL_OSCULP32K_VERSION 0x110\r
+#define SYSCTRL_OSC8M_VERSION 0x110\r
+#define SYSCTRL_OSC32K_VERSION 0x110\r
+#define SYSCTRL_VREF_VERSION 0x200\r
+#define SYSCTRL_VREG_VERSION 0x200\r
+#define SYSCTRL_XOSC_VERSION 0x110\r
+#define SYSCTRL_XOSC32K_VERSION 0x110\r
+\r
+#endif /* _SAMD20_SYSCTRL_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for TC0\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC0_INSTANCE_\r
+#define _SAMD20_TC0_INSTANCE_\r
+\r
+/* ========== Register definition for TC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC0_CTRLA (0x42002000U) /**< \brief (TC0) Control A Register */\r
+#define REG_TC0_READREQ (0x42002002U) /**< \brief (TC0) Read Request Register */\r
+#define REG_TC0_CTRLBCLR (0x42002004U) /**< \brief (TC0) Control B Clear Register */\r
+#define REG_TC0_CTRLBSET (0x42002005U) /**< \brief (TC0) Control B Set Register */\r
+#define REG_TC0_CTRLC (0x42002006U) /**< \brief (TC0) Control C Register */\r
+#define REG_TC0_DBGCTRL (0x42002008U) /**< \brief (TC0) Debug Register */\r
+#define REG_TC0_EVCTRL (0x4200200AU) /**< \brief (TC0) Event Control Register */\r
+#define REG_TC0_INTENCLR (0x4200200CU) /**< \brief (TC0) Interrupt Enable Clear Register */\r
+#define REG_TC0_INTENSET (0x4200200DU) /**< \brief (TC0) Interrupt Enable Set Register */\r
+#define REG_TC0_INTFLAG (0x4200200EU) /**< \brief (TC0) Interrupt Flag Status and Clear Register */\r
+#define REG_TC0_STATUS (0x4200200FU) /**< \brief (TC0) Status Register */\r
+#define REG_TC0_COUNT8_COUNT (0x42002010U) /**< \brief (TC0) COUNT8 Count Register */\r
+#define REG_TC0_COUNT16_COUNT (0x42002010U) /**< \brief (TC0) COUNT16 Count Register */\r
+#define REG_TC0_COUNT32_COUNT (0x42002010U) /**< \brief (TC0) COUNT32 Count Register */\r
+#define REG_TC0_COUNT8_PER (0x42002014U) /**< \brief (TC0) COUNT8 Period Register */\r
+#define REG_TC0_COUNT32_PER (0x42002014U) /**< \brief (TC0) COUNT32 Period Register */\r
+#define REG_TC0_COUNT8_CC0 (0x42002018U) /**< \brief (TC0) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC0_COUNT8_CC1 (0x42002019U) /**< \brief (TC0) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC0_COUNT16_CC0 (0x42002018U) /**< \brief (TC0) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC0_COUNT16_CC1 (0x4200201AU) /**< \brief (TC0) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC0_COUNT32_CC0 (0x42002018U) /**< \brief (TC0) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC0_COUNT32_CC1 (0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture Register 1 */\r
+#else\r
+#define REG_TC0_CTRLA (*(RwReg16*)0x42002000U) /**< \brief (TC0) Control A Register */\r
+#define REG_TC0_READREQ (*(RwReg16*)0x42002002U) /**< \brief (TC0) Read Request Register */\r
+#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TC0) Control B Clear Register */\r
+#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TC0) Control B Set Register */\r
+#define REG_TC0_CTRLC (*(RwReg8 *)0x42002006U) /**< \brief (TC0) Control C Register */\r
+#define REG_TC0_DBGCTRL (*(RwReg8 *)0x42002008U) /**< \brief (TC0) Debug Register */\r
+#define REG_TC0_EVCTRL (*(RwReg16*)0x4200200AU) /**< \brief (TC0) Event Control Register */\r
+#define REG_TC0_INTENCLR (*(RwReg8 *)0x4200200CU) /**< \brief (TC0) Interrupt Enable Clear Register */\r
+#define REG_TC0_INTENSET (*(RwReg8 *)0x4200200DU) /**< \brief (TC0) Interrupt Enable Set Register */\r
+#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200EU) /**< \brief (TC0) Interrupt Flag Status and Clear Register */\r
+#define REG_TC0_STATUS (*(RoReg8 *)0x4200200FU) /**< \brief (TC0) Status Register */\r
+#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002010U) /**< \brief (TC0) COUNT8 Count Register */\r
+#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002010U) /**< \brief (TC0) COUNT16 Count Register */\r
+#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002010U) /**< \brief (TC0) COUNT32 Count Register */\r
+#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x42002014U) /**< \brief (TC0) COUNT8 Period Register */\r
+#define REG_TC0_COUNT32_PER (*(RwReg *)0x42002014U) /**< \brief (TC0) COUNT32 Period Register */\r
+#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x42002018U) /**< \brief (TC0) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x42002019U) /**< \brief (TC0) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x42002018U) /**< \brief (TC0) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201AU) /**< \brief (TC0) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x42002018U) /**< \brief (TC0) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for TC0 peripheral ========== */\r
+#define TC0_CC8_NUM 2\r
+#define TC0_CC16_NUM 2\r
+#define TC0_CC32_NUM 2\r
+#define TC0_DITHERING_EXT 0\r
+#define TC0_GCLK_ID 19\r
+#define TC0_OW_NUM 2\r
+#define TC0_PERIOD_EXT 0\r
+#define TC0_SHADOW_EXT 0\r
+\r
+#endif /* _SAMD20_TC0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for TC1\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC1_INSTANCE_\r
+#define _SAMD20_TC1_INSTANCE_\r
+\r
+/* ========== Register definition for TC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC1_CTRLA (0x42002400U) /**< \brief (TC1) Control A Register */\r
+#define REG_TC1_READREQ (0x42002402U) /**< \brief (TC1) Read Request Register */\r
+#define REG_TC1_CTRLBCLR (0x42002404U) /**< \brief (TC1) Control B Clear Register */\r
+#define REG_TC1_CTRLBSET (0x42002405U) /**< \brief (TC1) Control B Set Register */\r
+#define REG_TC1_CTRLC (0x42002406U) /**< \brief (TC1) Control C Register */\r
+#define REG_TC1_DBGCTRL (0x42002408U) /**< \brief (TC1) Debug Register */\r
+#define REG_TC1_EVCTRL (0x4200240AU) /**< \brief (TC1) Event Control Register */\r
+#define REG_TC1_INTENCLR (0x4200240CU) /**< \brief (TC1) Interrupt Enable Clear Register */\r
+#define REG_TC1_INTENSET (0x4200240DU) /**< \brief (TC1) Interrupt Enable Set Register */\r
+#define REG_TC1_INTFLAG (0x4200240EU) /**< \brief (TC1) Interrupt Flag Status and Clear Register */\r
+#define REG_TC1_STATUS (0x4200240FU) /**< \brief (TC1) Status Register */\r
+#define REG_TC1_COUNT8_COUNT (0x42002410U) /**< \brief (TC1) COUNT8 Count Register */\r
+#define REG_TC1_COUNT16_COUNT (0x42002410U) /**< \brief (TC1) COUNT16 Count Register */\r
+#define REG_TC1_COUNT32_COUNT (0x42002410U) /**< \brief (TC1) COUNT32 Count Register */\r
+#define REG_TC1_COUNT8_PER (0x42002414U) /**< \brief (TC1) COUNT8 Period Register */\r
+#define REG_TC1_COUNT32_PER (0x42002414U) /**< \brief (TC1) COUNT32 Period Register */\r
+#define REG_TC1_COUNT8_CC0 (0x42002418U) /**< \brief (TC1) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC1_COUNT8_CC1 (0x42002419U) /**< \brief (TC1) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC1_COUNT16_CC0 (0x42002418U) /**< \brief (TC1) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC1_COUNT16_CC1 (0x4200241AU) /**< \brief (TC1) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC1_COUNT32_CC0 (0x42002418U) /**< \brief (TC1) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC1_COUNT32_CC1 (0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture Register 1 */\r
+#else\r
+#define REG_TC1_CTRLA (*(RwReg16*)0x42002400U) /**< \brief (TC1) Control A Register */\r
+#define REG_TC1_READREQ (*(RwReg16*)0x42002402U) /**< \brief (TC1) Read Request Register */\r
+#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TC1) Control B Clear Register */\r
+#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TC1) Control B Set Register */\r
+#define REG_TC1_CTRLC (*(RwReg8 *)0x42002406U) /**< \brief (TC1) Control C Register */\r
+#define REG_TC1_DBGCTRL (*(RwReg8 *)0x42002408U) /**< \brief (TC1) Debug Register */\r
+#define REG_TC1_EVCTRL (*(RwReg16*)0x4200240AU) /**< \brief (TC1) Event Control Register */\r
+#define REG_TC1_INTENCLR (*(RwReg8 *)0x4200240CU) /**< \brief (TC1) Interrupt Enable Clear Register */\r
+#define REG_TC1_INTENSET (*(RwReg8 *)0x4200240DU) /**< \brief (TC1) Interrupt Enable Set Register */\r
+#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240EU) /**< \brief (TC1) Interrupt Flag Status and Clear Register */\r
+#define REG_TC1_STATUS (*(RoReg8 *)0x4200240FU) /**< \brief (TC1) Status Register */\r
+#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002410U) /**< \brief (TC1) COUNT8 Count Register */\r
+#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002410U) /**< \brief (TC1) COUNT16 Count Register */\r
+#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002410U) /**< \brief (TC1) COUNT32 Count Register */\r
+#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x42002414U) /**< \brief (TC1) COUNT8 Period Register */\r
+#define REG_TC1_COUNT32_PER (*(RwReg *)0x42002414U) /**< \brief (TC1) COUNT32 Period Register */\r
+#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x42002418U) /**< \brief (TC1) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x42002419U) /**< \brief (TC1) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x42002418U) /**< \brief (TC1) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241AU) /**< \brief (TC1) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x42002418U) /**< \brief (TC1) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for TC1 peripheral ========== */\r
+#define TC1_CC8_NUM 2\r
+#define TC1_CC16_NUM 2\r
+#define TC1_CC32_NUM 2\r
+#define TC1_DITHERING_EXT 0\r
+#define TC1_GCLK_ID 19\r
+#define TC1_OW_NUM 2\r
+#define TC1_PERIOD_EXT 0\r
+#define TC1_SHADOW_EXT 0\r
+\r
+#endif /* _SAMD20_TC1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for TC2\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC2_INSTANCE_\r
+#define _SAMD20_TC2_INSTANCE_\r
+\r
+/* ========== Register definition for TC2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC2_CTRLA (0x42002800U) /**< \brief (TC2) Control A Register */\r
+#define REG_TC2_READREQ (0x42002802U) /**< \brief (TC2) Read Request Register */\r
+#define REG_TC2_CTRLBCLR (0x42002804U) /**< \brief (TC2) Control B Clear Register */\r
+#define REG_TC2_CTRLBSET (0x42002805U) /**< \brief (TC2) Control B Set Register */\r
+#define REG_TC2_CTRLC (0x42002806U) /**< \brief (TC2) Control C Register */\r
+#define REG_TC2_DBGCTRL (0x42002808U) /**< \brief (TC2) Debug Register */\r
+#define REG_TC2_EVCTRL (0x4200280AU) /**< \brief (TC2) Event Control Register */\r
+#define REG_TC2_INTENCLR (0x4200280CU) /**< \brief (TC2) Interrupt Enable Clear Register */\r
+#define REG_TC2_INTENSET (0x4200280DU) /**< \brief (TC2) Interrupt Enable Set Register */\r
+#define REG_TC2_INTFLAG (0x4200280EU) /**< \brief (TC2) Interrupt Flag Status and Clear Register */\r
+#define REG_TC2_STATUS (0x4200280FU) /**< \brief (TC2) Status Register */\r
+#define REG_TC2_COUNT8_COUNT (0x42002810U) /**< \brief (TC2) COUNT8 Count Register */\r
+#define REG_TC2_COUNT16_COUNT (0x42002810U) /**< \brief (TC2) COUNT16 Count Register */\r
+#define REG_TC2_COUNT32_COUNT (0x42002810U) /**< \brief (TC2) COUNT32 Count Register */\r
+#define REG_TC2_COUNT8_PER (0x42002814U) /**< \brief (TC2) COUNT8 Period Register */\r
+#define REG_TC2_COUNT32_PER (0x42002814U) /**< \brief (TC2) COUNT32 Period Register */\r
+#define REG_TC2_COUNT8_CC0 (0x42002818U) /**< \brief (TC2) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC2_COUNT8_CC1 (0x42002819U) /**< \brief (TC2) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC2_COUNT16_CC0 (0x42002818U) /**< \brief (TC2) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC2_COUNT16_CC1 (0x4200281AU) /**< \brief (TC2) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC2_COUNT32_CC0 (0x42002818U) /**< \brief (TC2) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC2_COUNT32_CC1 (0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture Register 1 */\r
+#else\r
+#define REG_TC2_CTRLA (*(RwReg16*)0x42002800U) /**< \brief (TC2) Control A Register */\r
+#define REG_TC2_READREQ (*(RwReg16*)0x42002802U) /**< \brief (TC2) Read Request Register */\r
+#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TC2) Control B Clear Register */\r
+#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TC2) Control B Set Register */\r
+#define REG_TC2_CTRLC (*(RwReg8 *)0x42002806U) /**< \brief (TC2) Control C Register */\r
+#define REG_TC2_DBGCTRL (*(RwReg8 *)0x42002808U) /**< \brief (TC2) Debug Register */\r
+#define REG_TC2_EVCTRL (*(RwReg16*)0x4200280AU) /**< \brief (TC2) Event Control Register */\r
+#define REG_TC2_INTENCLR (*(RwReg8 *)0x4200280CU) /**< \brief (TC2) Interrupt Enable Clear Register */\r
+#define REG_TC2_INTENSET (*(RwReg8 *)0x4200280DU) /**< \brief (TC2) Interrupt Enable Set Register */\r
+#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280EU) /**< \brief (TC2) Interrupt Flag Status and Clear Register */\r
+#define REG_TC2_STATUS (*(RoReg8 *)0x4200280FU) /**< \brief (TC2) Status Register */\r
+#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002810U) /**< \brief (TC2) COUNT8 Count Register */\r
+#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002810U) /**< \brief (TC2) COUNT16 Count Register */\r
+#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002810U) /**< \brief (TC2) COUNT32 Count Register */\r
+#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x42002814U) /**< \brief (TC2) COUNT8 Period Register */\r
+#define REG_TC2_COUNT32_PER (*(RwReg *)0x42002814U) /**< \brief (TC2) COUNT32 Period Register */\r
+#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x42002818U) /**< \brief (TC2) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x42002819U) /**< \brief (TC2) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x42002818U) /**< \brief (TC2) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281AU) /**< \brief (TC2) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x42002818U) /**< \brief (TC2) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for TC2 peripheral ========== */\r
+#define TC2_CC8_NUM 2\r
+#define TC2_CC16_NUM 2\r
+#define TC2_CC32_NUM 2\r
+#define TC2_DITHERING_EXT 0\r
+#define TC2_GCLK_ID 20\r
+#define TC2_OW_NUM 2\r
+#define TC2_PERIOD_EXT 0\r
+#define TC2_SHADOW_EXT 0\r
+\r
+#endif /* _SAMD20_TC2_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for TC3\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC3_INSTANCE_\r
+#define _SAMD20_TC3_INSTANCE_\r
+\r
+/* ========== Register definition for TC3 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A Register */\r
+#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request Register */\r
+#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear Register */\r
+#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set Register */\r
+#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C Register */\r
+#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Register */\r
+#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control Register */\r
+#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear Register */\r
+#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set Register */\r
+#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear Register */\r
+#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status Register */\r
+#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Count Register */\r
+#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Count Register */\r
+#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Count Register */\r
+#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Register */\r
+#define REG_TC3_COUNT32_PER (0x42002C14U) /**< \brief (TC3) COUNT32 Period Register */\r
+#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture Register 1 */\r
+#else\r
+#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A Register */\r
+#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request Register */\r
+#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear Register */\r
+#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set Register */\r
+#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C Register */\r
+#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Register */\r
+#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control Register */\r
+#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear Register */\r
+#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set Register */\r
+#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear Register */\r
+#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status Register */\r
+#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Count Register */\r
+#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Count Register */\r
+#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Count Register */\r
+#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Register */\r
+#define REG_TC3_COUNT32_PER (*(RwReg *)0x42002C14U) /**< \brief (TC3) COUNT32 Period Register */\r
+#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for TC3 peripheral ========== */\r
+#define TC3_CC8_NUM 2\r
+#define TC3_CC16_NUM 2\r
+#define TC3_CC32_NUM 2\r
+#define TC3_DITHERING_EXT 0\r
+#define TC3_GCLK_ID 20\r
+#define TC3_OW_NUM 2\r
+#define TC3_PERIOD_EXT 0\r
+#define TC3_SHADOW_EXT 0\r
+\r
+#endif /* _SAMD20_TC3_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for TC4\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC4_INSTANCE_\r
+#define _SAMD20_TC4_INSTANCE_\r
+\r
+/* ========== Register definition for TC4 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A Register */\r
+#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request Register */\r
+#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear Register */\r
+#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set Register */\r
+#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C Register */\r
+#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Register */\r
+#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control Register */\r
+#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear Register */\r
+#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set Register */\r
+#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear Register */\r
+#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status Register */\r
+#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Count Register */\r
+#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Count Register */\r
+#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Count Register */\r
+#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Register */\r
+#define REG_TC4_COUNT32_PER (0x42003014U) /**< \brief (TC4) COUNT32 Period Register */\r
+#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare and Capture Register 1 */\r
+#else\r
+#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A Register */\r
+#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request Register */\r
+#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear Register */\r
+#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set Register */\r
+#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C Register */\r
+#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Register */\r
+#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control Register */\r
+#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear Register */\r
+#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set Register */\r
+#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear Register */\r
+#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status Register */\r
+#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Count Register */\r
+#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Count Register */\r
+#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Count Register */\r
+#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Register */\r
+#define REG_TC4_COUNT32_PER (*(RwReg *)0x42003014U) /**< \brief (TC4) COUNT32 Period Register */\r
+#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare and Capture Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for TC4 peripheral ========== */\r
+#define TC4_CC8_NUM 2\r
+#define TC4_CC16_NUM 2\r
+#define TC4_CC32_NUM 2\r
+#define TC4_DITHERING_EXT 0\r
+#define TC4_GCLK_ID 21\r
+#define TC4_OW_NUM 2\r
+#define TC4_PERIOD_EXT 0\r
+#define TC4_SHADOW_EXT 0\r
+\r
+#endif /* _SAMD20_TC4_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for TC5\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC5_INSTANCE_\r
+#define _SAMD20_TC5_INSTANCE_\r
+\r
+/* ========== Register definition for TC5 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A Register */\r
+#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request Register */\r
+#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear Register */\r
+#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set Register */\r
+#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C Register */\r
+#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Register */\r
+#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control Register */\r
+#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear Register */\r
+#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set Register */\r
+#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear Register */\r
+#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status Register */\r
+#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Count Register */\r
+#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Count Register */\r
+#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Count Register */\r
+#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Register */\r
+#define REG_TC5_COUNT32_PER (0x42003414U) /**< \brief (TC5) COUNT32 Period Register */\r
+#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare and Capture Register 1 */\r
+#else\r
+#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A Register */\r
+#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request Register */\r
+#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear Register */\r
+#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set Register */\r
+#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C Register */\r
+#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Register */\r
+#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control Register */\r
+#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear Register */\r
+#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set Register */\r
+#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear Register */\r
+#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status Register */\r
+#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Count Register */\r
+#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Count Register */\r
+#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Count Register */\r
+#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Register */\r
+#define REG_TC5_COUNT32_PER (*(RwReg *)0x42003414U) /**< \brief (TC5) COUNT32 Period Register */\r
+#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare and Capture Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for TC5 peripheral ========== */\r
+#define TC5_CC8_NUM 2\r
+#define TC5_CC16_NUM 2\r
+#define TC5_CC32_NUM 2\r
+#define TC5_DITHERING_EXT 0\r
+#define TC5_GCLK_ID 21\r
+#define TC5_OW_NUM 2\r
+#define TC5_PERIOD_EXT 0\r
+#define TC5_SHADOW_EXT 0\r
+\r
+#endif /* _SAMD20_TC5_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for TC6\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC6_INSTANCE_\r
+#define _SAMD20_TC6_INSTANCE_\r
+\r
+/* ========== Register definition for TC6 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A Register */\r
+#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request Register */\r
+#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear Register */\r
+#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set Register */\r
+#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C Register */\r
+#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Register */\r
+#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control Register */\r
+#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear Register */\r
+#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set Register */\r
+#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear Register */\r
+#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status Register */\r
+#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Count Register */\r
+#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Count Register */\r
+#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Count Register */\r
+#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Register */\r
+#define REG_TC6_COUNT32_PER (0x42003814U) /**< \brief (TC6) COUNT32 Period Register */\r
+#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare and Capture Register 1 */\r
+#else\r
+#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A Register */\r
+#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request Register */\r
+#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear Register */\r
+#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set Register */\r
+#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C Register */\r
+#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Register */\r
+#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control Register */\r
+#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear Register */\r
+#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set Register */\r
+#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear Register */\r
+#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status Register */\r
+#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Count Register */\r
+#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Count Register */\r
+#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Count Register */\r
+#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Register */\r
+#define REG_TC6_COUNT32_PER (*(RwReg *)0x42003814U) /**< \brief (TC6) COUNT32 Period Register */\r
+#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare and Capture Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for TC6 peripheral ========== */\r
+#define TC6_CC8_NUM 2\r
+#define TC6_CC16_NUM 2\r
+#define TC6_CC32_NUM 2\r
+#define TC6_DITHERING_EXT 0\r
+#define TC6_GCLK_ID 22\r
+#define TC6_OW_NUM 2\r
+#define TC6_PERIOD_EXT 0\r
+#define TC6_SHADOW_EXT 0\r
+\r
+#endif /* _SAMD20_TC6_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for TC7\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_TC7_INSTANCE_\r
+#define _SAMD20_TC7_INSTANCE_\r
+\r
+/* ========== Register definition for TC7 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC7_CTRLA (0x42003C00U) /**< \brief (TC7) Control A Register */\r
+#define REG_TC7_READREQ (0x42003C02U) /**< \brief (TC7) Read Request Register */\r
+#define REG_TC7_CTRLBCLR (0x42003C04U) /**< \brief (TC7) Control B Clear Register */\r
+#define REG_TC7_CTRLBSET (0x42003C05U) /**< \brief (TC7) Control B Set Register */\r
+#define REG_TC7_CTRLC (0x42003C06U) /**< \brief (TC7) Control C Register */\r
+#define REG_TC7_DBGCTRL (0x42003C08U) /**< \brief (TC7) Debug Register */\r
+#define REG_TC7_EVCTRL (0x42003C0AU) /**< \brief (TC7) Event Control Register */\r
+#define REG_TC7_INTENCLR (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear Register */\r
+#define REG_TC7_INTENSET (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set Register */\r
+#define REG_TC7_INTFLAG (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear Register */\r
+#define REG_TC7_STATUS (0x42003C0FU) /**< \brief (TC7) Status Register */\r
+#define REG_TC7_COUNT8_COUNT (0x42003C10U) /**< \brief (TC7) COUNT8 Count Register */\r
+#define REG_TC7_COUNT16_COUNT (0x42003C10U) /**< \brief (TC7) COUNT16 Count Register */\r
+#define REG_TC7_COUNT32_COUNT (0x42003C10U) /**< \brief (TC7) COUNT32 Count Register */\r
+#define REG_TC7_COUNT8_PER (0x42003C14U) /**< \brief (TC7) COUNT8 Period Register */\r
+#define REG_TC7_COUNT32_PER (0x42003C14U) /**< \brief (TC7) COUNT32 Period Register */\r
+#define REG_TC7_COUNT8_CC0 (0x42003C18U) /**< \brief (TC7) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC7_COUNT8_CC1 (0x42003C19U) /**< \brief (TC7) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC7_COUNT16_CC0 (0x42003C18U) /**< \brief (TC7) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC7_COUNT16_CC1 (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC7_COUNT32_CC0 (0x42003C18U) /**< \brief (TC7) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC7_COUNT32_CC1 (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare and Capture Register 1 */\r
+#else\r
+#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A Register */\r
+#define REG_TC7_READREQ (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request Register */\r
+#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear Register */\r
+#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set Register */\r
+#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C Register */\r
+#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Register */\r
+#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control Register */\r
+#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear Register */\r
+#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set Register */\r
+#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear Register */\r
+#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status Register */\r
+#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Count Register */\r
+#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Count Register */\r
+#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10U) /**< \brief (TC7) COUNT32 Count Register */\r
+#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Register */\r
+#define REG_TC7_COUNT32_PER (*(RwReg *)0x42003C14U) /**< \brief (TC7) COUNT32 Period Register */\r
+#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare and Capture Register 0 */\r
+#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare and Capture Register 1 */\r
+#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare and Capture Register 0 */\r
+#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare and Capture Register 1 */\r
+#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare and Capture Register 0 */\r
+#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare and Capture Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for TC7 peripheral ========== */\r
+#define TC7_CC8_NUM 2\r
+#define TC7_CC16_NUM 2\r
+#define TC7_CC32_NUM 2\r
+#define TC7_DITHERING_EXT 0\r
+#define TC7_GCLK_ID 22\r
+#define TC7_OW_NUM 2\r
+#define TC7_PERIOD_EXT 0\r
+#define TC7_SHADOW_EXT 0\r
+\r
+#endif /* _SAMD20_TC7_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Instance description for WDT\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_WDT_INSTANCE_\r
+#define _SAMD20_WDT_INSTANCE_\r
+\r
+/* ========== Register definition for WDT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration Register */\r
+#define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Control Register */\r
+#define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear Register */\r
+#define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set Register */\r
+#define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear Register */\r
+#define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status Register */\r
+#define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear Register */\r
+#else\r
+#define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration Register */\r
+#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Control Register */\r
+#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear Register */\r
+#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set Register */\r
+#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear Register */\r
+#define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status Register */\r
+#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* ========== Instance parameters for WDT peripheral ========== */\r
+#define WDT_GCLK_ID 1\r
+\r
+#endif /* _SAMD20_WDT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20E14\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E14_PIO_\r
+#define _SAMD20E14_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20E14_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20E15\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E15_PIO_\r
+#define _SAMD20E15_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20E15_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20E16\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E16_PIO_\r
+#define _SAMD20E16_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20E16_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20E17\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E17_PIO_\r
+#define _SAMD20E17_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20E17_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20E18\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E18_PIO_\r
+#define _SAMD20E18_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20E18_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20G14\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G14_PIO_\r
+#define _SAMD20G14_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20G14_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20G15\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G15_PIO_\r
+#define _SAMD20G15_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20G15_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20G16\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G16_PIO_\r
+#define _SAMD20G16_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20G16_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20G17\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G17_PIO_\r
+#define _SAMD20G17_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20G17_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20G18\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G18_PIO_\r
+#define _SAMD20G18_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20G18_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20J14\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J14_PIO_\r
+#define _SAMD20J14_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */\r
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */\r
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */\r
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */\r
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */\r
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */\r
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */\r
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */\r
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */\r
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */\r
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */\r
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */\r
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */\r
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */\r
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */\r
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */\r
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */\r
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */\r
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */\r
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */\r
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */\r
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */\r
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */\r
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */\r
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */\r
+#define MUX_PB14H_GCLK_IO0 7\r
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)\r
+#define PORT_PB14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */\r
+#define MUX_PB15H_GCLK_IO1 7\r
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)\r
+#define PORT_PB15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */\r
+#define MUX_PB16H_GCLK_IO2 7\r
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)\r
+#define PORT_PB16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */\r
+#define MUX_PB17H_GCLK_IO3 7\r
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)\r
+#define PORT_PB17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */\r
+#define MUX_PB12H_GCLK_IO6 7\r
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)\r
+#define PORT_PB12H_GCLK_IO6 (1u << 12)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */\r
+#define MUX_PB13H_GCLK_IO7 7\r
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)\r
+#define PORT_PB13H_GCLK_IO7 (1u << 13)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */\r
+#define MUX_PB00A_EIC_EXTINT0 0\r
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)\r
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */\r
+#define MUX_PB16A_EIC_EXTINT0 0\r
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)\r
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */\r
+#define MUX_PB01A_EIC_EXTINT1 0\r
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)\r
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */\r
+#define MUX_PB17A_EIC_EXTINT1 0\r
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)\r
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */\r
+#define MUX_PB04A_EIC_EXTINT4 0\r
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)\r
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */\r
+#define MUX_PB05A_EIC_EXTINT5 0\r
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)\r
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */\r
+#define MUX_PB06A_EIC_EXTINT6 0\r
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)\r
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */\r
+#define MUX_PB07A_EIC_EXTINT7 0\r
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)\r
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */\r
+#define MUX_PB12A_EIC_EXTINT12 0\r
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)\r
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */\r
+#define MUX_PB13A_EIC_EXTINT13 0\r
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)\r
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */\r
+#define MUX_PB14A_EIC_EXTINT14 0\r
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)\r
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */\r
+#define MUX_PB30A_EIC_EXTINT14 0\r
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)\r
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */\r
+#define MUX_PB15A_EIC_EXTINT15 0\r
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)\r
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */\r
+#define MUX_PB31A_EIC_EXTINT15 0\r
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)\r
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */\r
+#define MUX_PB12C_SERCOM4_PAD0 2\r
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)\r
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */\r
+#define MUX_PB13C_SERCOM4_PAD1 2\r
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)\r
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */\r
+#define MUX_PB14C_SERCOM4_PAD2 2\r
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)\r
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */\r
+#define MUX_PB15C_SERCOM4_PAD3 2\r
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)\r
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */\r
+#define MUX_PB30D_SERCOM5_PAD0 3\r
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)\r
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)\r
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */\r
+#define MUX_PB16C_SERCOM5_PAD0 2\r
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)\r
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */\r
+#define MUX_PB31D_SERCOM5_PAD1 3\r
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)\r
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)\r
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */\r
+#define MUX_PB17C_SERCOM5_PAD1 2\r
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)\r
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */\r
+#define MUX_PB00D_SERCOM5_PAD2 3\r
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)\r
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */\r
+#define MUX_PB01D_SERCOM5_PAD3 3\r
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)\r
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PB30F_TC0_WO0 62 /**< \brief TC0 signal: WO0 on PB30 mux F */\r
+#define MUX_PB30F_TC0_WO0 5\r
+#define PINMUX_PB30F_TC0_WO0 ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)\r
+#define PORT_PB30F_TC0_WO0 (1u << 30)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PB31F_TC0_WO1 63 /**< \brief TC0 signal: WO1 on PB31 mux F */\r
+#define MUX_PB31F_TC0_WO1 5\r
+#define PINMUX_PB31F_TC0_WO1 ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)\r
+#define PORT_PB31F_TC0_WO1 (1u << 31)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */\r
+#define MUX_PB12E_TC4_WO0 4\r
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)\r
+#define PORT_PB12E_TC4_WO0 (1u << 12)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */\r
+#define MUX_PB13E_TC4_WO1 4\r
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)\r
+#define PORT_PB13E_TC4_WO1 (1u << 13)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */\r
+#define MUX_PB14E_TC5_WO0 4\r
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)\r
+#define PORT_PB14E_TC5_WO0 (1u << 14)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */\r
+#define MUX_PB15E_TC5_WO1 4\r
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)\r
+#define PORT_PB15E_TC5_WO1 (1u << 15)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */\r
+#define MUX_PB16E_TC6_WO0 4\r
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)\r
+#define PORT_PB16E_TC6_WO0 (1u << 16)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */\r
+#define MUX_PB17E_TC6_WO1 4\r
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)\r
+#define PORT_PB17E_TC6_WO1 (1u << 17)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB00F_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux F */\r
+#define MUX_PB00F_TC7_WO0 5\r
+#define PINMUX_PB00F_TC7_WO0 ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)\r
+#define PORT_PB00F_TC7_WO0 (1u << 0)\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB01F_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux F */\r
+#define MUX_PB01F_TC7_WO1 5\r
+#define PINMUX_PB01F_TC7_WO1 ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)\r
+#define PORT_PB01F_TC7_WO1 (1u << 1)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */\r
+#define MUX_PB00B_ADC_AIN8 1\r
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)\r
+#define PORT_PB00B_ADC_AIN8 (1u << 0)\r
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */\r
+#define MUX_PB01B_ADC_AIN9 1\r
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)\r
+#define PORT_PB01B_ADC_AIN9 (1u << 1)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */\r
+#define MUX_PB04B_ADC_AIN12 1\r
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)\r
+#define PORT_PB04B_ADC_AIN12 (1u << 4)\r
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */\r
+#define MUX_PB05B_ADC_AIN13 1\r
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)\r
+#define PORT_PB05B_ADC_AIN13 (1u << 5)\r
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */\r
+#define MUX_PB06B_ADC_AIN14 1\r
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)\r
+#define PORT_PB06B_ADC_AIN14 (1u << 6)\r
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */\r
+#define MUX_PB07B_ADC_AIN15 1\r
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)\r
+#define PORT_PB07B_ADC_AIN15 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20J14_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20J15\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J15_PIO_\r
+#define _SAMD20J15_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */\r
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */\r
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */\r
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */\r
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */\r
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */\r
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */\r
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */\r
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */\r
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */\r
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */\r
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */\r
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */\r
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */\r
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */\r
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */\r
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */\r
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */\r
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */\r
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */\r
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */\r
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */\r
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */\r
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */\r
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */\r
+#define MUX_PB14H_GCLK_IO0 7\r
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)\r
+#define PORT_PB14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */\r
+#define MUX_PB15H_GCLK_IO1 7\r
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)\r
+#define PORT_PB15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */\r
+#define MUX_PB16H_GCLK_IO2 7\r
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)\r
+#define PORT_PB16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */\r
+#define MUX_PB17H_GCLK_IO3 7\r
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)\r
+#define PORT_PB17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */\r
+#define MUX_PB12H_GCLK_IO6 7\r
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)\r
+#define PORT_PB12H_GCLK_IO6 (1u << 12)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */\r
+#define MUX_PB13H_GCLK_IO7 7\r
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)\r
+#define PORT_PB13H_GCLK_IO7 (1u << 13)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */\r
+#define MUX_PB00A_EIC_EXTINT0 0\r
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)\r
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */\r
+#define MUX_PB16A_EIC_EXTINT0 0\r
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)\r
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */\r
+#define MUX_PB01A_EIC_EXTINT1 0\r
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)\r
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */\r
+#define MUX_PB17A_EIC_EXTINT1 0\r
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)\r
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */\r
+#define MUX_PB04A_EIC_EXTINT4 0\r
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)\r
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */\r
+#define MUX_PB05A_EIC_EXTINT5 0\r
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)\r
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */\r
+#define MUX_PB06A_EIC_EXTINT6 0\r
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)\r
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */\r
+#define MUX_PB07A_EIC_EXTINT7 0\r
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)\r
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */\r
+#define MUX_PB12A_EIC_EXTINT12 0\r
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)\r
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */\r
+#define MUX_PB13A_EIC_EXTINT13 0\r
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)\r
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */\r
+#define MUX_PB14A_EIC_EXTINT14 0\r
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)\r
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */\r
+#define MUX_PB30A_EIC_EXTINT14 0\r
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)\r
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */\r
+#define MUX_PB15A_EIC_EXTINT15 0\r
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)\r
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */\r
+#define MUX_PB31A_EIC_EXTINT15 0\r
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)\r
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */\r
+#define MUX_PB12C_SERCOM4_PAD0 2\r
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)\r
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */\r
+#define MUX_PB13C_SERCOM4_PAD1 2\r
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)\r
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */\r
+#define MUX_PB14C_SERCOM4_PAD2 2\r
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)\r
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */\r
+#define MUX_PB15C_SERCOM4_PAD3 2\r
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)\r
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */\r
+#define MUX_PB30D_SERCOM5_PAD0 3\r
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)\r
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)\r
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */\r
+#define MUX_PB16C_SERCOM5_PAD0 2\r
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)\r
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */\r
+#define MUX_PB31D_SERCOM5_PAD1 3\r
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)\r
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)\r
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */\r
+#define MUX_PB17C_SERCOM5_PAD1 2\r
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)\r
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */\r
+#define MUX_PB00D_SERCOM5_PAD2 3\r
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)\r
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */\r
+#define MUX_PB01D_SERCOM5_PAD3 3\r
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)\r
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PB30F_TC0_WO0 62 /**< \brief TC0 signal: WO0 on PB30 mux F */\r
+#define MUX_PB30F_TC0_WO0 5\r
+#define PINMUX_PB30F_TC0_WO0 ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)\r
+#define PORT_PB30F_TC0_WO0 (1u << 30)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PB31F_TC0_WO1 63 /**< \brief TC0 signal: WO1 on PB31 mux F */\r
+#define MUX_PB31F_TC0_WO1 5\r
+#define PINMUX_PB31F_TC0_WO1 ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)\r
+#define PORT_PB31F_TC0_WO1 (1u << 31)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */\r
+#define MUX_PB12E_TC4_WO0 4\r
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)\r
+#define PORT_PB12E_TC4_WO0 (1u << 12)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */\r
+#define MUX_PB13E_TC4_WO1 4\r
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)\r
+#define PORT_PB13E_TC4_WO1 (1u << 13)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */\r
+#define MUX_PB14E_TC5_WO0 4\r
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)\r
+#define PORT_PB14E_TC5_WO0 (1u << 14)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */\r
+#define MUX_PB15E_TC5_WO1 4\r
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)\r
+#define PORT_PB15E_TC5_WO1 (1u << 15)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */\r
+#define MUX_PB16E_TC6_WO0 4\r
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)\r
+#define PORT_PB16E_TC6_WO0 (1u << 16)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */\r
+#define MUX_PB17E_TC6_WO1 4\r
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)\r
+#define PORT_PB17E_TC6_WO1 (1u << 17)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB00F_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux F */\r
+#define MUX_PB00F_TC7_WO0 5\r
+#define PINMUX_PB00F_TC7_WO0 ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)\r
+#define PORT_PB00F_TC7_WO0 (1u << 0)\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB01F_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux F */\r
+#define MUX_PB01F_TC7_WO1 5\r
+#define PINMUX_PB01F_TC7_WO1 ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)\r
+#define PORT_PB01F_TC7_WO1 (1u << 1)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */\r
+#define MUX_PB00B_ADC_AIN8 1\r
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)\r
+#define PORT_PB00B_ADC_AIN8 (1u << 0)\r
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */\r
+#define MUX_PB01B_ADC_AIN9 1\r
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)\r
+#define PORT_PB01B_ADC_AIN9 (1u << 1)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */\r
+#define MUX_PB04B_ADC_AIN12 1\r
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)\r
+#define PORT_PB04B_ADC_AIN12 (1u << 4)\r
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */\r
+#define MUX_PB05B_ADC_AIN13 1\r
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)\r
+#define PORT_PB05B_ADC_AIN13 (1u << 5)\r
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */\r
+#define MUX_PB06B_ADC_AIN14 1\r
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)\r
+#define PORT_PB06B_ADC_AIN14 (1u << 6)\r
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */\r
+#define MUX_PB07B_ADC_AIN15 1\r
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)\r
+#define PORT_PB07B_ADC_AIN15 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20J15_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20J16\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J16_PIO_\r
+#define _SAMD20J16_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */\r
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */\r
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */\r
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */\r
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */\r
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */\r
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */\r
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */\r
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */\r
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */\r
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */\r
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */\r
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */\r
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */\r
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */\r
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */\r
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */\r
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */\r
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */\r
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */\r
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */\r
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */\r
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */\r
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */\r
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */\r
+#define MUX_PB14H_GCLK_IO0 7\r
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)\r
+#define PORT_PB14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */\r
+#define MUX_PB15H_GCLK_IO1 7\r
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)\r
+#define PORT_PB15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */\r
+#define MUX_PB16H_GCLK_IO2 7\r
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)\r
+#define PORT_PB16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */\r
+#define MUX_PB17H_GCLK_IO3 7\r
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)\r
+#define PORT_PB17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */\r
+#define MUX_PB12H_GCLK_IO6 7\r
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)\r
+#define PORT_PB12H_GCLK_IO6 (1u << 12)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */\r
+#define MUX_PB13H_GCLK_IO7 7\r
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)\r
+#define PORT_PB13H_GCLK_IO7 (1u << 13)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */\r
+#define MUX_PB00A_EIC_EXTINT0 0\r
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)\r
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */\r
+#define MUX_PB16A_EIC_EXTINT0 0\r
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)\r
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */\r
+#define MUX_PB01A_EIC_EXTINT1 0\r
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)\r
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */\r
+#define MUX_PB17A_EIC_EXTINT1 0\r
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)\r
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */\r
+#define MUX_PB04A_EIC_EXTINT4 0\r
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)\r
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */\r
+#define MUX_PB05A_EIC_EXTINT5 0\r
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)\r
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */\r
+#define MUX_PB06A_EIC_EXTINT6 0\r
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)\r
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */\r
+#define MUX_PB07A_EIC_EXTINT7 0\r
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)\r
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */\r
+#define MUX_PB12A_EIC_EXTINT12 0\r
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)\r
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */\r
+#define MUX_PB13A_EIC_EXTINT13 0\r
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)\r
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */\r
+#define MUX_PB14A_EIC_EXTINT14 0\r
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)\r
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */\r
+#define MUX_PB30A_EIC_EXTINT14 0\r
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)\r
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */\r
+#define MUX_PB15A_EIC_EXTINT15 0\r
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)\r
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */\r
+#define MUX_PB31A_EIC_EXTINT15 0\r
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)\r
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */\r
+#define MUX_PB12C_SERCOM4_PAD0 2\r
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)\r
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */\r
+#define MUX_PB13C_SERCOM4_PAD1 2\r
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)\r
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */\r
+#define MUX_PB14C_SERCOM4_PAD2 2\r
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)\r
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */\r
+#define MUX_PB15C_SERCOM4_PAD3 2\r
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)\r
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */\r
+#define MUX_PB30D_SERCOM5_PAD0 3\r
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)\r
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)\r
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */\r
+#define MUX_PB16C_SERCOM5_PAD0 2\r
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)\r
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */\r
+#define MUX_PB31D_SERCOM5_PAD1 3\r
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)\r
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)\r
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */\r
+#define MUX_PB17C_SERCOM5_PAD1 2\r
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)\r
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */\r
+#define MUX_PB00D_SERCOM5_PAD2 3\r
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)\r
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */\r
+#define MUX_PB01D_SERCOM5_PAD3 3\r
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)\r
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PB30F_TC0_WO0 62 /**< \brief TC0 signal: WO0 on PB30 mux F */\r
+#define MUX_PB30F_TC0_WO0 5\r
+#define PINMUX_PB30F_TC0_WO0 ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)\r
+#define PORT_PB30F_TC0_WO0 (1u << 30)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PB31F_TC0_WO1 63 /**< \brief TC0 signal: WO1 on PB31 mux F */\r
+#define MUX_PB31F_TC0_WO1 5\r
+#define PINMUX_PB31F_TC0_WO1 ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)\r
+#define PORT_PB31F_TC0_WO1 (1u << 31)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */\r
+#define MUX_PB12E_TC4_WO0 4\r
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)\r
+#define PORT_PB12E_TC4_WO0 (1u << 12)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */\r
+#define MUX_PB13E_TC4_WO1 4\r
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)\r
+#define PORT_PB13E_TC4_WO1 (1u << 13)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */\r
+#define MUX_PB14E_TC5_WO0 4\r
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)\r
+#define PORT_PB14E_TC5_WO0 (1u << 14)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */\r
+#define MUX_PB15E_TC5_WO1 4\r
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)\r
+#define PORT_PB15E_TC5_WO1 (1u << 15)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */\r
+#define MUX_PB16E_TC6_WO0 4\r
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)\r
+#define PORT_PB16E_TC6_WO0 (1u << 16)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */\r
+#define MUX_PB17E_TC6_WO1 4\r
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)\r
+#define PORT_PB17E_TC6_WO1 (1u << 17)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB00F_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux F */\r
+#define MUX_PB00F_TC7_WO0 5\r
+#define PINMUX_PB00F_TC7_WO0 ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)\r
+#define PORT_PB00F_TC7_WO0 (1u << 0)\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB01F_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux F */\r
+#define MUX_PB01F_TC7_WO1 5\r
+#define PINMUX_PB01F_TC7_WO1 ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)\r
+#define PORT_PB01F_TC7_WO1 (1u << 1)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */\r
+#define MUX_PB00B_ADC_AIN8 1\r
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)\r
+#define PORT_PB00B_ADC_AIN8 (1u << 0)\r
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */\r
+#define MUX_PB01B_ADC_AIN9 1\r
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)\r
+#define PORT_PB01B_ADC_AIN9 (1u << 1)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */\r
+#define MUX_PB04B_ADC_AIN12 1\r
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)\r
+#define PORT_PB04B_ADC_AIN12 (1u << 4)\r
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */\r
+#define MUX_PB05B_ADC_AIN13 1\r
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)\r
+#define PORT_PB05B_ADC_AIN13 (1u << 5)\r
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */\r
+#define MUX_PB06B_ADC_AIN14 1\r
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)\r
+#define PORT_PB06B_ADC_AIN14 (1u << 6)\r
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */\r
+#define MUX_PB07B_ADC_AIN15 1\r
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)\r
+#define PORT_PB07B_ADC_AIN15 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20J16_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20J17\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J17_PIO_\r
+#define _SAMD20J17_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */\r
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */\r
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */\r
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */\r
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */\r
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */\r
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */\r
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */\r
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */\r
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */\r
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */\r
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */\r
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */\r
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */\r
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */\r
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */\r
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */\r
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */\r
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */\r
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */\r
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */\r
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */\r
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */\r
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */\r
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */\r
+#define MUX_PB14H_GCLK_IO0 7\r
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)\r
+#define PORT_PB14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */\r
+#define MUX_PB15H_GCLK_IO1 7\r
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)\r
+#define PORT_PB15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */\r
+#define MUX_PB16H_GCLK_IO2 7\r
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)\r
+#define PORT_PB16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */\r
+#define MUX_PB17H_GCLK_IO3 7\r
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)\r
+#define PORT_PB17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */\r
+#define MUX_PB12H_GCLK_IO6 7\r
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)\r
+#define PORT_PB12H_GCLK_IO6 (1u << 12)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */\r
+#define MUX_PB13H_GCLK_IO7 7\r
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)\r
+#define PORT_PB13H_GCLK_IO7 (1u << 13)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */\r
+#define MUX_PB00A_EIC_EXTINT0 0\r
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)\r
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */\r
+#define MUX_PB16A_EIC_EXTINT0 0\r
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)\r
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */\r
+#define MUX_PB01A_EIC_EXTINT1 0\r
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)\r
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */\r
+#define MUX_PB17A_EIC_EXTINT1 0\r
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)\r
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */\r
+#define MUX_PB04A_EIC_EXTINT4 0\r
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)\r
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */\r
+#define MUX_PB05A_EIC_EXTINT5 0\r
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)\r
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */\r
+#define MUX_PB06A_EIC_EXTINT6 0\r
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)\r
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */\r
+#define MUX_PB07A_EIC_EXTINT7 0\r
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)\r
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */\r
+#define MUX_PB12A_EIC_EXTINT12 0\r
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)\r
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */\r
+#define MUX_PB13A_EIC_EXTINT13 0\r
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)\r
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */\r
+#define MUX_PB14A_EIC_EXTINT14 0\r
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)\r
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */\r
+#define MUX_PB30A_EIC_EXTINT14 0\r
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)\r
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */\r
+#define MUX_PB15A_EIC_EXTINT15 0\r
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)\r
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */\r
+#define MUX_PB31A_EIC_EXTINT15 0\r
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)\r
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */\r
+#define MUX_PB12C_SERCOM4_PAD0 2\r
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)\r
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */\r
+#define MUX_PB13C_SERCOM4_PAD1 2\r
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)\r
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */\r
+#define MUX_PB14C_SERCOM4_PAD2 2\r
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)\r
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */\r
+#define MUX_PB15C_SERCOM4_PAD3 2\r
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)\r
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */\r
+#define MUX_PB30D_SERCOM5_PAD0 3\r
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)\r
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)\r
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */\r
+#define MUX_PB16C_SERCOM5_PAD0 2\r
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)\r
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */\r
+#define MUX_PB31D_SERCOM5_PAD1 3\r
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)\r
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)\r
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */\r
+#define MUX_PB17C_SERCOM5_PAD1 2\r
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)\r
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */\r
+#define MUX_PB00D_SERCOM5_PAD2 3\r
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)\r
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */\r
+#define MUX_PB01D_SERCOM5_PAD3 3\r
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)\r
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PB30F_TC0_WO0 62 /**< \brief TC0 signal: WO0 on PB30 mux F */\r
+#define MUX_PB30F_TC0_WO0 5\r
+#define PINMUX_PB30F_TC0_WO0 ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)\r
+#define PORT_PB30F_TC0_WO0 (1u << 30)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PB31F_TC0_WO1 63 /**< \brief TC0 signal: WO1 on PB31 mux F */\r
+#define MUX_PB31F_TC0_WO1 5\r
+#define PINMUX_PB31F_TC0_WO1 ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)\r
+#define PORT_PB31F_TC0_WO1 (1u << 31)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */\r
+#define MUX_PB12E_TC4_WO0 4\r
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)\r
+#define PORT_PB12E_TC4_WO0 (1u << 12)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */\r
+#define MUX_PB13E_TC4_WO1 4\r
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)\r
+#define PORT_PB13E_TC4_WO1 (1u << 13)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */\r
+#define MUX_PB14E_TC5_WO0 4\r
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)\r
+#define PORT_PB14E_TC5_WO0 (1u << 14)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */\r
+#define MUX_PB15E_TC5_WO1 4\r
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)\r
+#define PORT_PB15E_TC5_WO1 (1u << 15)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */\r
+#define MUX_PB16E_TC6_WO0 4\r
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)\r
+#define PORT_PB16E_TC6_WO0 (1u << 16)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */\r
+#define MUX_PB17E_TC6_WO1 4\r
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)\r
+#define PORT_PB17E_TC6_WO1 (1u << 17)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB00F_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux F */\r
+#define MUX_PB00F_TC7_WO0 5\r
+#define PINMUX_PB00F_TC7_WO0 ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)\r
+#define PORT_PB00F_TC7_WO0 (1u << 0)\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB01F_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux F */\r
+#define MUX_PB01F_TC7_WO1 5\r
+#define PINMUX_PB01F_TC7_WO1 ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)\r
+#define PORT_PB01F_TC7_WO1 (1u << 1)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */\r
+#define MUX_PB00B_ADC_AIN8 1\r
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)\r
+#define PORT_PB00B_ADC_AIN8 (1u << 0)\r
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */\r
+#define MUX_PB01B_ADC_AIN9 1\r
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)\r
+#define PORT_PB01B_ADC_AIN9 (1u << 1)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */\r
+#define MUX_PB04B_ADC_AIN12 1\r
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)\r
+#define PORT_PB04B_ADC_AIN12 (1u << 4)\r
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */\r
+#define MUX_PB05B_ADC_AIN13 1\r
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)\r
+#define PORT_PB05B_ADC_AIN13 (1u << 5)\r
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */\r
+#define MUX_PB06B_ADC_AIN14 1\r
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)\r
+#define PORT_PB06B_ADC_AIN14 (1u << 6)\r
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */\r
+#define MUX_PB07B_ADC_AIN15 1\r
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)\r
+#define PORT_PB07B_ADC_AIN15 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20J17_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Peripheral I/O description for SAMD20J18\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J18_PIO_\r
+#define _SAMD20J18_PIO_\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */\r
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */\r
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */\r
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */\r
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */\r
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */\r
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */\r
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */\r
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */\r
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */\r
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */\r
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */\r
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */\r
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */\r
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */\r
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */\r
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */\r
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */\r
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */\r
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */\r
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */\r
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */\r
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */\r
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */\r
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */\r
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */\r
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */\r
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */\r
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */\r
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */\r
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */\r
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */\r
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */\r
+/* ========== PORT definition for CORE peripheral ========== */\r
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */\r
+#define MUX_PA30G_CORE_SWCLK 6\r
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)\r
+#define PORT_PA30G_CORE_SWCLK (1u << 30)\r
+/* ========== PORT definition for GCLK peripheral ========== */\r
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */\r
+#define MUX_PB14H_GCLK_IO0 7\r
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)\r
+#define PORT_PB14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */\r
+#define MUX_PB22H_GCLK_IO0 7\r
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)\r
+#define PORT_PB22H_GCLK_IO0 (1u << 22)\r
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */\r
+#define MUX_PA14H_GCLK_IO0 7\r
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)\r
+#define PORT_PA14H_GCLK_IO0 (1u << 14)\r
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */\r
+#define MUX_PA27H_GCLK_IO0 7\r
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)\r
+#define PORT_PA27H_GCLK_IO0 (1u << 27)\r
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */\r
+#define MUX_PA28H_GCLK_IO0 7\r
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)\r
+#define PORT_PA28H_GCLK_IO0 (1u << 28)\r
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */\r
+#define MUX_PA30H_GCLK_IO0 7\r
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)\r
+#define PORT_PA30H_GCLK_IO0 (1u << 30)\r
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */\r
+#define MUX_PB15H_GCLK_IO1 7\r
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)\r
+#define PORT_PB15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */\r
+#define MUX_PB23H_GCLK_IO1 7\r
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)\r
+#define PORT_PB23H_GCLK_IO1 (1u << 23)\r
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */\r
+#define MUX_PA15H_GCLK_IO1 7\r
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)\r
+#define PORT_PA15H_GCLK_IO1 (1u << 15)\r
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */\r
+#define MUX_PB16H_GCLK_IO2 7\r
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)\r
+#define PORT_PB16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */\r
+#define MUX_PA16H_GCLK_IO2 7\r
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)\r
+#define PORT_PA16H_GCLK_IO2 (1u << 16)\r
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */\r
+#define MUX_PA17H_GCLK_IO3 7\r
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)\r
+#define PORT_PA17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */\r
+#define MUX_PB17H_GCLK_IO3 7\r
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)\r
+#define PORT_PB17H_GCLK_IO3 (1u << 17)\r
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */\r
+#define MUX_PA10H_GCLK_IO4 7\r
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)\r
+#define PORT_PA10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */\r
+#define MUX_PA20H_GCLK_IO4 7\r
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)\r
+#define PORT_PA20H_GCLK_IO4 (1u << 20)\r
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */\r
+#define MUX_PB10H_GCLK_IO4 7\r
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)\r
+#define PORT_PB10H_GCLK_IO4 (1u << 10)\r
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */\r
+#define MUX_PA11H_GCLK_IO5 7\r
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)\r
+#define PORT_PA11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */\r
+#define MUX_PA21H_GCLK_IO5 7\r
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)\r
+#define PORT_PA21H_GCLK_IO5 (1u << 21)\r
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */\r
+#define MUX_PB11H_GCLK_IO5 7\r
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)\r
+#define PORT_PB11H_GCLK_IO5 (1u << 11)\r
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */\r
+#define MUX_PA22H_GCLK_IO6 7\r
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)\r
+#define PORT_PA22H_GCLK_IO6 (1u << 22)\r
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */\r
+#define MUX_PB12H_GCLK_IO6 7\r
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)\r
+#define PORT_PB12H_GCLK_IO6 (1u << 12)\r
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */\r
+#define MUX_PA23H_GCLK_IO7 7\r
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)\r
+#define PORT_PA23H_GCLK_IO7 (1u << 23)\r
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */\r
+#define MUX_PB13H_GCLK_IO7 7\r
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)\r
+#define PORT_PB13H_GCLK_IO7 (1u << 13)\r
+/* ========== PORT definition for EIC peripheral ========== */\r
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */\r
+#define MUX_PA16A_EIC_EXTINT0 0\r
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)\r
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */\r
+#define MUX_PB00A_EIC_EXTINT0 0\r
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)\r
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */\r
+#define MUX_PB16A_EIC_EXTINT0 0\r
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)\r
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)\r
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */\r
+#define MUX_PA00A_EIC_EXTINT0 0\r
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)\r
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)\r
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */\r
+#define MUX_PA17A_EIC_EXTINT1 0\r
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)\r
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */\r
+#define MUX_PB01A_EIC_EXTINT1 0\r
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)\r
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */\r
+#define MUX_PB17A_EIC_EXTINT1 0\r
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)\r
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)\r
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */\r
+#define MUX_PA01A_EIC_EXTINT1 0\r
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)\r
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)\r
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */\r
+#define MUX_PA02A_EIC_EXTINT2 0\r
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)\r
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */\r
+#define MUX_PA18A_EIC_EXTINT2 0\r
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)\r
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)\r
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */\r
+#define MUX_PB02A_EIC_EXTINT2 0\r
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)\r
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)\r
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */\r
+#define MUX_PA03A_EIC_EXTINT3 0\r
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)\r
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */\r
+#define MUX_PA19A_EIC_EXTINT3 0\r
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)\r
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)\r
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */\r
+#define MUX_PB03A_EIC_EXTINT3 0\r
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)\r
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)\r
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */\r
+#define MUX_PA04A_EIC_EXTINT4 0\r
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)\r
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */\r
+#define MUX_PA20A_EIC_EXTINT4 0\r
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)\r
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)\r
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */\r
+#define MUX_PB04A_EIC_EXTINT4 0\r
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)\r
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)\r
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */\r
+#define MUX_PA05A_EIC_EXTINT5 0\r
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)\r
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */\r
+#define MUX_PA21A_EIC_EXTINT5 0\r
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)\r
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)\r
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */\r
+#define MUX_PB05A_EIC_EXTINT5 0\r
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)\r
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)\r
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */\r
+#define MUX_PA06A_EIC_EXTINT6 0\r
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)\r
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */\r
+#define MUX_PA22A_EIC_EXTINT6 0\r
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)\r
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */\r
+#define MUX_PB06A_EIC_EXTINT6 0\r
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)\r
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)\r
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */\r
+#define MUX_PB22A_EIC_EXTINT6 0\r
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)\r
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)\r
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */\r
+#define MUX_PA07A_EIC_EXTINT7 0\r
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)\r
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */\r
+#define MUX_PA23A_EIC_EXTINT7 0\r
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)\r
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */\r
+#define MUX_PB07A_EIC_EXTINT7 0\r
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)\r
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)\r
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */\r
+#define MUX_PB23A_EIC_EXTINT7 0\r
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)\r
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)\r
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */\r
+#define MUX_PA28A_EIC_EXTINT8 0\r
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)\r
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)\r
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */\r
+#define MUX_PB08A_EIC_EXTINT8 0\r
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)\r
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)\r
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */\r
+#define MUX_PA09A_EIC_EXTINT9 0\r
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)\r
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */\r
+#define MUX_PB09A_EIC_EXTINT9 0\r
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)\r
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)\r
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */\r
+#define MUX_PA10A_EIC_EXTINT10 0\r
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)\r
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */\r
+#define MUX_PA30A_EIC_EXTINT10 0\r
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)\r
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)\r
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */\r
+#define MUX_PB10A_EIC_EXTINT10 0\r
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)\r
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)\r
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */\r
+#define MUX_PA11A_EIC_EXTINT11 0\r
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)\r
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */\r
+#define MUX_PA31A_EIC_EXTINT11 0\r
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)\r
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)\r
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */\r
+#define MUX_PB11A_EIC_EXTINT11 0\r
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)\r
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)\r
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */\r
+#define MUX_PA12A_EIC_EXTINT12 0\r
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)\r
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */\r
+#define MUX_PA24A_EIC_EXTINT12 0\r
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)\r
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)\r
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */\r
+#define MUX_PB12A_EIC_EXTINT12 0\r
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)\r
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)\r
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */\r
+#define MUX_PA13A_EIC_EXTINT13 0\r
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)\r
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */\r
+#define MUX_PA25A_EIC_EXTINT13 0\r
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)\r
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)\r
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */\r
+#define MUX_PB13A_EIC_EXTINT13 0\r
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)\r
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)\r
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */\r
+#define MUX_PB14A_EIC_EXTINT14 0\r
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)\r
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */\r
+#define MUX_PB30A_EIC_EXTINT14 0\r
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)\r
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)\r
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */\r
+#define MUX_PA14A_EIC_EXTINT14 0\r
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)\r
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)\r
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */\r
+#define MUX_PA27A_EIC_EXTINT15 0\r
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)\r
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)\r
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */\r
+#define MUX_PB15A_EIC_EXTINT15 0\r
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)\r
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */\r
+#define MUX_PB31A_EIC_EXTINT15 0\r
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)\r
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)\r
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */\r
+#define MUX_PA15A_EIC_EXTINT15 0\r
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)\r
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)\r
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */\r
+#define MUX_PA08A_EIC_NMI 0\r
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)\r
+#define PORT_PA08A_EIC_NMI (1u << 8)\r
+/* ========== PORT definition for SERCOM0 peripheral ========== */\r
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */\r
+#define MUX_PA04D_SERCOM0_PAD0 3\r
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)\r
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)\r
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */\r
+#define MUX_PA08C_SERCOM0_PAD0 2\r
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)\r
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)\r
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */\r
+#define MUX_PA05D_SERCOM0_PAD1 3\r
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)\r
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)\r
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */\r
+#define MUX_PA09C_SERCOM0_PAD1 2\r
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)\r
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)\r
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */\r
+#define MUX_PA06D_SERCOM0_PAD2 3\r
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)\r
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)\r
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */\r
+#define MUX_PA10C_SERCOM0_PAD2 2\r
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)\r
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)\r
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */\r
+#define MUX_PA07D_SERCOM0_PAD3 3\r
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)\r
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)\r
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */\r
+#define MUX_PA11C_SERCOM0_PAD3 2\r
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)\r
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)\r
+/* ========== PORT definition for SERCOM1 peripheral ========== */\r
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */\r
+#define MUX_PA16C_SERCOM1_PAD0 2\r
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)\r
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)\r
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */\r
+#define MUX_PA00D_SERCOM1_PAD0 3\r
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)\r
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)\r
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */\r
+#define MUX_PA17C_SERCOM1_PAD1 2\r
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)\r
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)\r
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */\r
+#define MUX_PA01D_SERCOM1_PAD1 3\r
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)\r
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)\r
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */\r
+#define MUX_PA30D_SERCOM1_PAD2 3\r
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)\r
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)\r
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */\r
+#define MUX_PA18C_SERCOM1_PAD2 2\r
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)\r
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)\r
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */\r
+#define MUX_PA31D_SERCOM1_PAD3 3\r
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)\r
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)\r
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */\r
+#define MUX_PA19C_SERCOM1_PAD3 2\r
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)\r
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)\r
+/* ========== PORT definition for SERCOM2 peripheral ========== */\r
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */\r
+#define MUX_PA08D_SERCOM2_PAD0 3\r
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)\r
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)\r
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */\r
+#define MUX_PA12C_SERCOM2_PAD0 2\r
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)\r
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)\r
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */\r
+#define MUX_PA09D_SERCOM2_PAD1 3\r
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)\r
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)\r
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */\r
+#define MUX_PA13C_SERCOM2_PAD1 2\r
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)\r
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)\r
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */\r
+#define MUX_PA10D_SERCOM2_PAD2 3\r
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)\r
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)\r
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */\r
+#define MUX_PA14C_SERCOM2_PAD2 2\r
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)\r
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)\r
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */\r
+#define MUX_PA11D_SERCOM2_PAD3 3\r
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)\r
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)\r
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */\r
+#define MUX_PA15C_SERCOM2_PAD3 2\r
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)\r
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM3 peripheral ========== */\r
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */\r
+#define MUX_PA16D_SERCOM3_PAD0 3\r
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)\r
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)\r
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */\r
+#define MUX_PA22C_SERCOM3_PAD0 2\r
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)\r
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)\r
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */\r
+#define MUX_PA17D_SERCOM3_PAD1 3\r
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)\r
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)\r
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */\r
+#define MUX_PA23C_SERCOM3_PAD1 2\r
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)\r
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)\r
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */\r
+#define MUX_PA18D_SERCOM3_PAD2 3\r
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)\r
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)\r
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */\r
+#define MUX_PA20D_SERCOM3_PAD2 3\r
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)\r
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)\r
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */\r
+#define MUX_PA24C_SERCOM3_PAD2 2\r
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)\r
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)\r
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */\r
+#define MUX_PA19D_SERCOM3_PAD3 3\r
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)\r
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)\r
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */\r
+#define MUX_PA21D_SERCOM3_PAD3 3\r
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)\r
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)\r
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */\r
+#define MUX_PA25C_SERCOM3_PAD3 2\r
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)\r
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)\r
+/* ========== PORT definition for SERCOM4 peripheral ========== */\r
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */\r
+#define MUX_PA12D_SERCOM4_PAD0 3\r
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)\r
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */\r
+#define MUX_PB08D_SERCOM4_PAD0 3\r
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)\r
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)\r
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */\r
+#define MUX_PB12C_SERCOM4_PAD0 2\r
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)\r
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)\r
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */\r
+#define MUX_PA13D_SERCOM4_PAD1 3\r
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)\r
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */\r
+#define MUX_PB09D_SERCOM4_PAD1 3\r
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)\r
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)\r
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */\r
+#define MUX_PB13C_SERCOM4_PAD1 2\r
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)\r
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)\r
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */\r
+#define MUX_PA14D_SERCOM4_PAD2 3\r
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)\r
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */\r
+#define MUX_PB10D_SERCOM4_PAD2 3\r
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)\r
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)\r
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */\r
+#define MUX_PB14C_SERCOM4_PAD2 2\r
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)\r
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)\r
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */\r
+#define MUX_PA15D_SERCOM4_PAD3 3\r
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)\r
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)\r
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */\r
+#define MUX_PB11D_SERCOM4_PAD3 3\r
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)\r
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)\r
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */\r
+#define MUX_PB15C_SERCOM4_PAD3 2\r
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)\r
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)\r
+/* ========== PORT definition for SERCOM5 peripheral ========== */\r
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */\r
+#define MUX_PA22D_SERCOM5_PAD0 3\r
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)\r
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)\r
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */\r
+#define MUX_PB02D_SERCOM5_PAD0 3\r
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)\r
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)\r
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */\r
+#define MUX_PB30D_SERCOM5_PAD0 3\r
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)\r
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)\r
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */\r
+#define MUX_PB16C_SERCOM5_PAD0 2\r
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)\r
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)\r
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */\r
+#define MUX_PA23D_SERCOM5_PAD1 3\r
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)\r
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)\r
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */\r
+#define MUX_PB03D_SERCOM5_PAD1 3\r
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)\r
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)\r
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */\r
+#define MUX_PB31D_SERCOM5_PAD1 3\r
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)\r
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)\r
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */\r
+#define MUX_PB17C_SERCOM5_PAD1 2\r
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)\r
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)\r
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */\r
+#define MUX_PA24D_SERCOM5_PAD2 3\r
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)\r
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)\r
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */\r
+#define MUX_PB00D_SERCOM5_PAD2 3\r
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)\r
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)\r
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */\r
+#define MUX_PB22D_SERCOM5_PAD2 3\r
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)\r
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)\r
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */\r
+#define MUX_PA20C_SERCOM5_PAD2 2\r
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)\r
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)\r
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */\r
+#define MUX_PA25D_SERCOM5_PAD3 3\r
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)\r
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)\r
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */\r
+#define MUX_PB01D_SERCOM5_PAD3 3\r
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)\r
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)\r
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */\r
+#define MUX_PB23D_SERCOM5_PAD3 3\r
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)\r
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)\r
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */\r
+#define MUX_PA21C_SERCOM5_PAD3 2\r
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)\r
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)\r
+/* ========== PORT definition for TC0 peripheral ========== */\r
+#define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */\r
+#define MUX_PA04F_TC0_WO0 5\r
+#define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)\r
+#define PORT_PA04F_TC0_WO0 (1u << 4)\r
+#define PIN_PB30F_TC0_WO0 62 /**< \brief TC0 signal: WO0 on PB30 mux F */\r
+#define MUX_PB30F_TC0_WO0 5\r
+#define PINMUX_PB30F_TC0_WO0 ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0)\r
+#define PORT_PB30F_TC0_WO0 (1u << 30)\r
+#define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */\r
+#define MUX_PA08E_TC0_WO0 4\r
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)\r
+#define PORT_PA08E_TC0_WO0 (1u << 8)\r
+#define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */\r
+#define MUX_PA05F_TC0_WO1 5\r
+#define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)\r
+#define PORT_PA05F_TC0_WO1 (1u << 5)\r
+#define PIN_PB31F_TC0_WO1 63 /**< \brief TC0 signal: WO1 on PB31 mux F */\r
+#define MUX_PB31F_TC0_WO1 5\r
+#define PINMUX_PB31F_TC0_WO1 ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1)\r
+#define PORT_PB31F_TC0_WO1 (1u << 31)\r
+#define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */\r
+#define MUX_PA09E_TC0_WO1 4\r
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)\r
+#define PORT_PA09E_TC0_WO1 (1u << 9)\r
+/* ========== PORT definition for TC1 peripheral ========== */\r
+#define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */\r
+#define MUX_PA06F_TC1_WO0 5\r
+#define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)\r
+#define PORT_PA06F_TC1_WO0 (1u << 6)\r
+#define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */\r
+#define MUX_PA30F_TC1_WO0 5\r
+#define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)\r
+#define PORT_PA30F_TC1_WO0 (1u << 30)\r
+#define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */\r
+#define MUX_PA10E_TC1_WO0 4\r
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)\r
+#define PORT_PA10E_TC1_WO0 (1u << 10)\r
+#define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */\r
+#define MUX_PA07F_TC1_WO1 5\r
+#define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)\r
+#define PORT_PA07F_TC1_WO1 (1u << 7)\r
+#define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */\r
+#define MUX_PA31F_TC1_WO1 5\r
+#define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)\r
+#define PORT_PA31F_TC1_WO1 (1u << 31)\r
+#define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */\r
+#define MUX_PA11E_TC1_WO1 4\r
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)\r
+#define PORT_PA11E_TC1_WO1 (1u << 11)\r
+/* ========== PORT definition for TC2 peripheral ========== */\r
+#define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */\r
+#define MUX_PA16F_TC2_WO0 5\r
+#define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)\r
+#define PORT_PA16F_TC2_WO0 (1u << 16)\r
+#define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */\r
+#define MUX_PA12E_TC2_WO0 4\r
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)\r
+#define PORT_PA12E_TC2_WO0 (1u << 12)\r
+#define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */\r
+#define MUX_PA00F_TC2_WO0 5\r
+#define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)\r
+#define PORT_PA00F_TC2_WO0 (1u << 0)\r
+#define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */\r
+#define MUX_PA17F_TC2_WO1 5\r
+#define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)\r
+#define PORT_PA17F_TC2_WO1 (1u << 17)\r
+#define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */\r
+#define MUX_PA13E_TC2_WO1 4\r
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)\r
+#define PORT_PA13E_TC2_WO1 (1u << 13)\r
+#define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */\r
+#define MUX_PA01F_TC2_WO1 5\r
+#define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)\r
+#define PORT_PA01F_TC2_WO1 (1u << 1)\r
+/* ========== PORT definition for TC3 peripheral ========== */\r
+#define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */\r
+#define MUX_PA18F_TC3_WO0 5\r
+#define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)\r
+#define PORT_PA18F_TC3_WO0 (1u << 18)\r
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */\r
+#define MUX_PA14E_TC3_WO0 4\r
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)\r
+#define PORT_PA14E_TC3_WO0 (1u << 14)\r
+#define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */\r
+#define MUX_PA19F_TC3_WO1 5\r
+#define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)\r
+#define PORT_PA19F_TC3_WO1 (1u << 19)\r
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */\r
+#define MUX_PA15E_TC3_WO1 4\r
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)\r
+#define PORT_PA15E_TC3_WO1 (1u << 15)\r
+/* ========== PORT definition for TC4 peripheral ========== */\r
+#define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */\r
+#define MUX_PA22F_TC4_WO0 5\r
+#define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)\r
+#define PORT_PA22F_TC4_WO0 (1u << 22)\r
+#define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */\r
+#define MUX_PB08F_TC4_WO0 5\r
+#define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)\r
+#define PORT_PB08F_TC4_WO0 (1u << 8)\r
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */\r
+#define MUX_PB12E_TC4_WO0 4\r
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)\r
+#define PORT_PB12E_TC4_WO0 (1u << 12)\r
+#define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */\r
+#define MUX_PA23F_TC4_WO1 5\r
+#define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)\r
+#define PORT_PA23F_TC4_WO1 (1u << 23)\r
+#define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */\r
+#define MUX_PB09F_TC4_WO1 5\r
+#define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)\r
+#define PORT_PB09F_TC4_WO1 (1u << 9)\r
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */\r
+#define MUX_PB13E_TC4_WO1 4\r
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)\r
+#define PORT_PB13E_TC4_WO1 (1u << 13)\r
+/* ========== PORT definition for TC5 peripheral ========== */\r
+#define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */\r
+#define MUX_PA24F_TC5_WO0 5\r
+#define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)\r
+#define PORT_PA24F_TC5_WO0 (1u << 24)\r
+#define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */\r
+#define MUX_PB10F_TC5_WO0 5\r
+#define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)\r
+#define PORT_PB10F_TC5_WO0 (1u << 10)\r
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */\r
+#define MUX_PB14E_TC5_WO0 4\r
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)\r
+#define PORT_PB14E_TC5_WO0 (1u << 14)\r
+#define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */\r
+#define MUX_PA25F_TC5_WO1 5\r
+#define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)\r
+#define PORT_PA25F_TC5_WO1 (1u << 25)\r
+#define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */\r
+#define MUX_PB11F_TC5_WO1 5\r
+#define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)\r
+#define PORT_PB11F_TC5_WO1 (1u << 11)\r
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */\r
+#define MUX_PB15E_TC5_WO1 4\r
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)\r
+#define PORT_PB15E_TC5_WO1 (1u << 15)\r
+/* ========== PORT definition for TC6 peripheral ========== */\r
+#define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */\r
+#define MUX_PB02F_TC6_WO0 5\r
+#define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)\r
+#define PORT_PB02F_TC6_WO0 (1u << 2)\r
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */\r
+#define MUX_PB16E_TC6_WO0 4\r
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)\r
+#define PORT_PB16E_TC6_WO0 (1u << 16)\r
+#define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */\r
+#define MUX_PB03F_TC6_WO1 5\r
+#define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)\r
+#define PORT_PB03F_TC6_WO1 (1u << 3)\r
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */\r
+#define MUX_PB17E_TC6_WO1 4\r
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)\r
+#define PORT_PB17E_TC6_WO1 (1u << 17)\r
+/* ========== PORT definition for TC7 peripheral ========== */\r
+#define PIN_PB00F_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux F */\r
+#define MUX_PB00F_TC7_WO0 5\r
+#define PINMUX_PB00F_TC7_WO0 ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0)\r
+#define PORT_PB00F_TC7_WO0 (1u << 0)\r
+#define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */\r
+#define MUX_PB22F_TC7_WO0 5\r
+#define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)\r
+#define PORT_PB22F_TC7_WO0 (1u << 22)\r
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */\r
+#define MUX_PA20E_TC7_WO0 4\r
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)\r
+#define PORT_PA20E_TC7_WO0 (1u << 20)\r
+#define PIN_PB01F_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux F */\r
+#define MUX_PB01F_TC7_WO1 5\r
+#define PINMUX_PB01F_TC7_WO1 ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1)\r
+#define PORT_PB01F_TC7_WO1 (1u << 1)\r
+#define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */\r
+#define MUX_PB23F_TC7_WO1 5\r
+#define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)\r
+#define PORT_PB23F_TC7_WO1 (1u << 23)\r
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */\r
+#define MUX_PA21E_TC7_WO1 4\r
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)\r
+#define PORT_PA21E_TC7_WO1 (1u << 21)\r
+/* ========== PORT definition for ADC peripheral ========== */\r
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */\r
+#define MUX_PA02B_ADC_AIN0 1\r
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)\r
+#define PORT_PA02B_ADC_AIN0 (1u << 2)\r
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */\r
+#define MUX_PA03B_ADC_AIN1 1\r
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)\r
+#define PORT_PA03B_ADC_AIN1 (1u << 3)\r
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */\r
+#define MUX_PB08B_ADC_AIN2 1\r
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)\r
+#define PORT_PB08B_ADC_AIN2 (1u << 8)\r
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */\r
+#define MUX_PB09B_ADC_AIN3 1\r
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)\r
+#define PORT_PB09B_ADC_AIN3 (1u << 9)\r
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */\r
+#define MUX_PA04B_ADC_AIN4 1\r
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)\r
+#define PORT_PA04B_ADC_AIN4 (1u << 4)\r
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */\r
+#define MUX_PA05B_ADC_AIN5 1\r
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)\r
+#define PORT_PA05B_ADC_AIN5 (1u << 5)\r
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */\r
+#define MUX_PA06B_ADC_AIN6 1\r
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)\r
+#define PORT_PA06B_ADC_AIN6 (1u << 6)\r
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */\r
+#define MUX_PA07B_ADC_AIN7 1\r
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)\r
+#define PORT_PA07B_ADC_AIN7 (1u << 7)\r
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */\r
+#define MUX_PB00B_ADC_AIN8 1\r
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)\r
+#define PORT_PB00B_ADC_AIN8 (1u << 0)\r
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */\r
+#define MUX_PB01B_ADC_AIN9 1\r
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)\r
+#define PORT_PB01B_ADC_AIN9 (1u << 1)\r
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */\r
+#define MUX_PB02B_ADC_AIN10 1\r
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)\r
+#define PORT_PB02B_ADC_AIN10 (1u << 2)\r
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */\r
+#define MUX_PB03B_ADC_AIN11 1\r
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)\r
+#define PORT_PB03B_ADC_AIN11 (1u << 3)\r
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */\r
+#define MUX_PB04B_ADC_AIN12 1\r
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)\r
+#define PORT_PB04B_ADC_AIN12 (1u << 4)\r
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */\r
+#define MUX_PB05B_ADC_AIN13 1\r
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)\r
+#define PORT_PB05B_ADC_AIN13 (1u << 5)\r
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */\r
+#define MUX_PB06B_ADC_AIN14 1\r
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)\r
+#define PORT_PB06B_ADC_AIN14 (1u << 6)\r
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */\r
+#define MUX_PB07B_ADC_AIN15 1\r
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)\r
+#define PORT_PB07B_ADC_AIN15 (1u << 7)\r
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */\r
+#define MUX_PA08B_ADC_AIN16 1\r
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)\r
+#define PORT_PA08B_ADC_AIN16 (1u << 8)\r
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */\r
+#define MUX_PA09B_ADC_AIN17 1\r
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)\r
+#define PORT_PA09B_ADC_AIN17 (1u << 9)\r
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */\r
+#define MUX_PA10B_ADC_AIN18 1\r
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)\r
+#define PORT_PA10B_ADC_AIN18 (1u << 10)\r
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */\r
+#define MUX_PA11B_ADC_AIN19 1\r
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)\r
+#define PORT_PA11B_ADC_AIN19 (1u << 11)\r
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */\r
+#define MUX_PA04B_ADC_VREFP 1\r
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)\r
+#define PORT_PA04B_ADC_VREFP (1u << 4)\r
+/* ========== PORT definition for AC peripheral ========== */\r
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */\r
+#define MUX_PA04B_AC_AIN0 1\r
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)\r
+#define PORT_PA04B_AC_AIN0 (1u << 4)\r
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */\r
+#define MUX_PA05B_AC_AIN1 1\r
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)\r
+#define PORT_PA05B_AC_AIN1 (1u << 5)\r
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */\r
+#define MUX_PA06B_AC_AIN2 1\r
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)\r
+#define PORT_PA06B_AC_AIN2 (1u << 6)\r
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */\r
+#define MUX_PA07B_AC_AIN3 1\r
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)\r
+#define PORT_PA07B_AC_AIN3 (1u << 7)\r
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */\r
+#define MUX_PA12H_AC_CMP0 7\r
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)\r
+#define PORT_PA12H_AC_CMP0 (1u << 12)\r
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */\r
+#define MUX_PA18H_AC_CMP0 7\r
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)\r
+#define PORT_PA18H_AC_CMP0 (1u << 18)\r
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */\r
+#define MUX_PA13H_AC_CMP1 7\r
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)\r
+#define PORT_PA13H_AC_CMP1 (1u << 13)\r
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */\r
+#define MUX_PA19H_AC_CMP1 7\r
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)\r
+#define PORT_PA19H_AC_CMP1 (1u << 19)\r
+/* ========== PORT definition for DAC peripheral ========== */\r
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */\r
+#define MUX_PA02B_DAC_VOUT 1\r
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)\r
+#define PORT_PA02B_DAC_VOUT (1u << 2)\r
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */\r
+#define MUX_PA03B_DAC_VREFP 1\r
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)\r
+#define PORT_PA03B_DAC_VREFP (1u << 3)\r
+\r
+#endif /* _SAMD20J18_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Top header file for SAM D20\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20_\r
+#define _SAMD20_\r
+\r
+/**\r
+ * \defgroup SAMD20_definitions SAM D20 Device Definitions\r
+ * \brief SAM D20 CMSIS Definitions.\r
+ */\r
+\r
+#if defined(__SAMD20E14__) || defined(__ATSAMD20E14__)\r
+ #include "samd20e14.h"\r
+#elif defined(__SAMD20E15__) || defined(__ATSAMD20E15__)\r
+ #include "samd20e15.h"\r
+#elif defined(__SAMD20E16__) || defined(__ATSAMD20E16__)\r
+ #include "samd20e16.h"\r
+#elif defined(__SAMD20E17__) || defined(__ATSAMD20E17__)\r
+ #include "samd20e17.h"\r
+#elif defined(__SAMD20E18__) || defined(__ATSAMD20E18__)\r
+ #include "samd20e18.h"\r
+#elif defined(__SAMD20G14__) || defined(__ATSAMD20G14__)\r
+ #include "samd20g14.h"\r
+#elif defined(__SAMD20G15__) || defined(__ATSAMD20G15__)\r
+ #include "samd20g15.h"\r
+#elif defined(__SAMD20G16__) || defined(__ATSAMD20G16__)\r
+ #include "samd20g16.h"\r
+#elif defined(__SAMD20G17__) || defined(__ATSAMD20G17__)\r
+ #include "samd20g17.h"\r
+#elif defined(__SAMD20G18__) || defined(__ATSAMD20G18__)\r
+ #include "samd20g18.h"\r
+#elif defined(__SAMD20J14__) || defined(__ATSAMD20J14__)\r
+ #include "samd20j14.h"\r
+#elif defined(__SAMD20J15__) || defined(__ATSAMD20J15__)\r
+ #include "samd20j15.h"\r
+#elif defined(__SAMD20J16__) || defined(__ATSAMD20J16__)\r
+ #include "samd20j16.h"\r
+#elif defined(__SAMD20J17__) || defined(__ATSAMD20J17__)\r
+ #include "samd20j17.h"\r
+#elif defined(__SAMD20J18__) || defined(__ATSAMD20J18__)\r
+ #include "samd20j18.h"\r
+#else\r
+ #error Library does not support the specified device.\r
+#endif\r
+\r
+#endif /* _SAMD20_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20E14\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E14_\r
+#define _SAMD20E14_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20E14_definitions SAMD20E14 definitions\r
+ * This file defines all structures and symbols for SAMD20E14:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20E14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E14_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20E14-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20E14 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20E14 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20E14 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20E14 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20E14 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20E14 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20E14 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20E14 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20E14 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20E14 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20E14 Serial Communication Interface 3 (SERCOM3) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20E14 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20E14 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20E14 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20E14 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20E14 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20E14 Basic Timer Counter 5 (TC5) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20E14 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20E14 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20E14 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnReserved11;\r
+ void* pfnReserved12;\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnReserved19;\r
+ void* pfnReserved20;\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E14_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20E14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E14_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20E14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E14_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20E14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E14_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20E14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E14_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20e14.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20E14 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x4000 /* 16 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 256\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x800 /* 2 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20E14 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20E14_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20E15\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E15_\r
+#define _SAMD20E15_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20E15_definitions SAMD20E15 definitions\r
+ * This file defines all structures and symbols for SAMD20E15:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20E15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E15_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20E15-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20E15 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20E15 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20E15 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20E15 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20E15 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20E15 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20E15 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20E15 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20E15 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20E15 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20E15 Serial Communication Interface 3 (SERCOM3) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20E15 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20E15 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20E15 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20E15 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20E15 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20E15 Basic Timer Counter 5 (TC5) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20E15 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20E15 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20E15 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnReserved11;\r
+ void* pfnReserved12;\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnReserved19;\r
+ void* pfnReserved20;\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E15_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20E15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E15_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20E15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E15_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20E15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E15_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20E15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E15_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20e15.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20E15 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x8000 /* 32 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 512\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x1000 /* 4 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20E15 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20E15_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20E16\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E16_\r
+#define _SAMD20E16_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20E16_definitions SAMD20E16 definitions\r
+ * This file defines all structures and symbols for SAMD20E16:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20E16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E16_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20E16-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20E16 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20E16 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20E16 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20E16 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20E16 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20E16 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20E16 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20E16 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20E16 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20E16 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20E16 Serial Communication Interface 3 (SERCOM3) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20E16 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20E16 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20E16 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20E16 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20E16 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20E16 Basic Timer Counter 5 (TC5) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20E16 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20E16 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20E16 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnReserved11;\r
+ void* pfnReserved12;\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnReserved19;\r
+ void* pfnReserved20;\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E16_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20E16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E16_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20E16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E16_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20E16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E16_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20E16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E16_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20e16.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20E16 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x10000 /* 64 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 1024\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x2000 /* 8 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20E16 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20E16_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20E17\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E17_\r
+#define _SAMD20E17_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20E17_definitions SAMD20E17 definitions\r
+ * This file defines all structures and symbols for SAMD20E17:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20E17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E17_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20E17-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20E17 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20E17 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20E17 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20E17 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20E17 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20E17 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20E17 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20E17 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20E17 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20E17 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20E17 Serial Communication Interface 3 (SERCOM3) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20E17 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20E17 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20E17 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20E17 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20E17 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20E17 Basic Timer Counter 5 (TC5) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20E17 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20E17 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20E17 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnReserved11;\r
+ void* pfnReserved12;\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnReserved19;\r
+ void* pfnReserved20;\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E17_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20E17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E17_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20E17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E17_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20E17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E17_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20E17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E17_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20e17.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20E17 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x20000 /* 128 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 2048\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x4000 /* 16 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20E17 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20E17_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20E18\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20E18_\r
+#define _SAMD20E18_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20E18_definitions SAMD20E18 definitions\r
+ * This file defines all structures and symbols for SAMD20E18:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20E18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E18_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20E18-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20E18 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20E18 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20E18 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20E18 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20E18 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20E18 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20E18 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20E18 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20E18 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20E18 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20E18 Serial Communication Interface 3 (SERCOM3) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20E18 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20E18 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20E18 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20E18 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20E18 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20E18 Basic Timer Counter 5 (TC5) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20E18 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20E18 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20E18 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnReserved11;\r
+ void* pfnReserved12;\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnReserved19;\r
+ void* pfnReserved20;\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E18_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20E18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E18_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20E18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E18_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20E18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E18_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20E18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20E18_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20e18.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20E18 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x40000 /* 256 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 4096\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20E18 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20E18_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20G14\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G14_\r
+#define _SAMD20G14_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20G14_definitions SAMD20G14 definitions\r
+ * This file defines all structures and symbols for SAMD20G14:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20G14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G14_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20G14-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20G14 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20G14 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20G14 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20G14 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20G14 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20G14 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20G14 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20G14 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20G14 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20G14 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20G14 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20G14 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20G14 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20G14 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20G14 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20G14 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20G14 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20G14 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20G14 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20G14 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20G14 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20G14 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20G14 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20G14 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G14_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20G14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G14_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20G14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G14_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20G14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G14_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20G14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G14_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20g14.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20G14 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x4000 /* 16 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 256\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x800 /* 2 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20G14 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20G14_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20G15\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G15_\r
+#define _SAMD20G15_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20G15_definitions SAMD20G15 definitions\r
+ * This file defines all structures and symbols for SAMD20G15:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20G15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G15_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20G15-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20G15 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20G15 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20G15 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20G15 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20G15 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20G15 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20G15 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20G15 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20G15 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20G15 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20G15 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20G15 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20G15 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20G15 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20G15 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20G15 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20G15 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20G15 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20G15 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20G15 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20G15 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20G15 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20G15 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20G15 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G15_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20G15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G15_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20G15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G15_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20G15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G15_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20G15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G15_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20g15.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20G15 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x8000 /* 32 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 512\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x1000 /* 4 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20G15 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20G15_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20G16\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G16_\r
+#define _SAMD20G16_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20G16_definitions SAMD20G16 definitions\r
+ * This file defines all structures and symbols for SAMD20G16:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20G16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G16_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20G16-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20G16 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20G16 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20G16 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20G16 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20G16 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20G16 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20G16 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20G16 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20G16 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20G16 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20G16 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20G16 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20G16 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20G16 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20G16 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20G16 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20G16 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20G16 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20G16 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20G16 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20G16 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20G16 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20G16 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20G16 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G16_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20G16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G16_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20G16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G16_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20G16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G16_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20G16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G16_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20g16.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20G16 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x10000 /* 64 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 1024\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x2000 /* 8 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20G16 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20G16_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20G17\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G17_\r
+#define _SAMD20G17_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20G17_definitions SAMD20G17 definitions\r
+ * This file defines all structures and symbols for SAMD20G17:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20G17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G17_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20G17-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20G17 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20G17 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20G17 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20G17 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20G17 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20G17 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20G17 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20G17 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20G17 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20G17 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20G17 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20G17 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20G17 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20G17 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20G17 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20G17 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20G17 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20G17 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20G17 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20G17 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20G17 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20G17 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20G17 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20G17 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G17_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20G17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G17_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20G17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G17_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20G17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G17_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20G17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G17_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20g17.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20G17 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x20000 /* 128 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 2048\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x4000 /* 16 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20G17 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20G17_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20G18\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20G18_\r
+#define _SAMD20G18_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20G18_definitions SAMD20G18 definitions\r
+ * This file defines all structures and symbols for SAMD20G18:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20G18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G18_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20G18-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20G18 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20G18 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20G18 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20G18 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20G18 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20G18 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20G18 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20G18 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20G18 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20G18 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20G18 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20G18 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20G18 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20G18 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20G18 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20G18 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20G18 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20G18 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20G18 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20G18 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20G18 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20G18 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20G18 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20G18 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20G18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G18_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20G18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G18_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20G18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G18_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20G18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G18_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20G18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20G18_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20g18.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20G18 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x40000 /* 256 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 4096\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20G18 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20G18_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20J14\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J14_\r
+#define _SAMD20J14_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20J14_definitions SAMD20J14 definitions\r
+ * This file defines all structures and symbols for SAMD20J14:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20J14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J14_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20J14-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20J14 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20J14 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20J14 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20J14 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20J14 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20J14 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20J14 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20J14 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20J14 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20J14 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20J14 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20J14 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20J14 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20J14 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20J14 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20J14 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20J14 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20J14 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20J14 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20J14 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20J14 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20J14 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20J14 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20J14 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J14_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20J14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J14_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20J14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J14_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20J14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J14_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20J14 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J14_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20j14.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20J14 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x4000 /* 16 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 256\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x800 /* 2 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20J14 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20J14_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20J15\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J15_\r
+#define _SAMD20J15_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20J15_definitions SAMD20J15 definitions\r
+ * This file defines all structures and symbols for SAMD20J15:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20J15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J15_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20J15-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20J15 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20J15 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20J15 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20J15 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20J15 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20J15 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20J15 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20J15 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20J15 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20J15 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20J15 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20J15 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20J15 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20J15 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20J15 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20J15 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20J15 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20J15 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20J15 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20J15 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20J15 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20J15 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20J15 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20J15 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J15_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20J15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J15_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20J15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J15_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20J15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J15_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20J15 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J15_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20j15.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20J15 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x8000 /* 32 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 512\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x1000 /* 4 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20J15 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20J15_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20J16\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J16_\r
+#define _SAMD20J16_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20J16_definitions SAMD20J16 definitions\r
+ * This file defines all structures and symbols for SAMD20J16:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20J16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J16_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20J16-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20J16 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20J16 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20J16 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20J16 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20J16 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20J16 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20J16 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20J16 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20J16 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20J16 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20J16 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20J16 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20J16 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20J16 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20J16 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20J16 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20J16 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20J16 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20J16 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20J16 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20J16 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20J16 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20J16 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20J16 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J16_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20J16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J16_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20J16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J16_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20J16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J16_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20J16 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J16_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20j16.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20J16 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x10000 /* 64 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 1024\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x2000 /* 8 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20J16 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20J16_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20J17\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J17_\r
+#define _SAMD20J17_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20J17_definitions SAMD20J17 definitions\r
+ * This file defines all structures and symbols for SAMD20J17:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20J17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J17_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20J17-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20J17 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20J17 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20J17 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20J17 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20J17 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20J17 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20J17 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20J17 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20J17 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20J17 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20J17 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20J17 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20J17 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20J17 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20J17 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20J17 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20J17 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20J17 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20J17 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20J17 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20J17 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20J17 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20J17 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20J17 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J17_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20J17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J17_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20J17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J17_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20J17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J17_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20J17 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J17_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20j17.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20J17 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x20000 /* 128 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 2048\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x4000 /* 16 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20J17 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20J17_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Header file for SAMD20J18\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAMD20J18_\r
+#define _SAMD20J18_\r
+\r
+/**\r
+ * \ingroup SAMD20_definitions\r
+ * \addtogroup SAMD20J18_definitions SAMD20J18 definitions\r
+ * This file defines all structures and symbols for SAMD20J18:\r
+ * - registers and bitfields\r
+ * - peripheral base address\r
+ * - peripheral ID\r
+ * - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/** CMSIS DEFINITIONS FOR SAMD20J18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J18_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */\r
+ /****** SAMD20J18-specific Interrupt Numbers ***********************/\r
+ PM_IRQn = 0, /**< 0 SAMD20J18 Power Manager (PM) */\r
+ SYSCTRL_IRQn = 1, /**< 1 SAMD20J18 System Control (SYSCTRL) */\r
+ WDT_IRQn = 2, /**< 2 SAMD20J18 Watchdog Timer (WDT) */\r
+ RTC_IRQn = 3, /**< 3 SAMD20J18 Real-Time Counter (RTC) */\r
+ EIC_IRQn = 4, /**< 4 SAMD20J18 External Interrupt Controller (EIC) */\r
+ NVMCTRL_IRQn = 5, /**< 5 SAMD20J18 Non-Volatile Memory Controller (NVMCTRL) */\r
+ EVSYS_IRQn = 6, /**< 6 SAMD20J18 Event System Interface (EVSYS) */\r
+ SERCOM0_IRQn = 7, /**< 7 SAMD20J18 Serial Communication Interface 0 (SERCOM0) */\r
+ SERCOM1_IRQn = 8, /**< 8 SAMD20J18 Serial Communication Interface 1 (SERCOM1) */\r
+ SERCOM2_IRQn = 9, /**< 9 SAMD20J18 Serial Communication Interface 2 (SERCOM2) */\r
+ SERCOM3_IRQn = 10, /**< 10 SAMD20J18 Serial Communication Interface 3 (SERCOM3) */\r
+ SERCOM4_IRQn = 11, /**< 11 SAMD20J18 Serial Communication Interface 4 (SERCOM4) */\r
+ SERCOM5_IRQn = 12, /**< 12 SAMD20J18 Serial Communication Interface 5 (SERCOM5) */\r
+ TC0_IRQn = 13, /**< 13 SAMD20J18 Basic Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 14, /**< 14 SAMD20J18 Basic Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 15, /**< 15 SAMD20J18 Basic Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 16, /**< 16 SAMD20J18 Basic Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 17, /**< 17 SAMD20J18 Basic Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 18, /**< 18 SAMD20J18 Basic Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 19, /**< 19 SAMD20J18 Basic Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 20, /**< 20 SAMD20J18 Basic Timer Counter 7 (TC7) */\r
+ ADC_IRQn = 21, /**< 21 SAMD20J18 Analog Digital Converter (ADC) */\r
+ AC_IRQn = 22, /**< 22 SAMD20J18 Analog Comparators (AC) */\r
+ DAC_IRQn = 23, /**< 23 SAMD20J18 Digital Analog Converter (DAC) */\r
+\r
+ PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnReservedM12;\r
+ void* pfnReservedM11;\r
+ void* pfnReservedM10;\r
+ void* pfnReservedM9;\r
+ void* pfnReservedM8;\r
+ void* pfnReservedM7;\r
+ void* pfnReservedM6;\r
+ void* pfnSVC_Handler;\r
+ void* pfnReservedM4;\r
+ void* pfnReservedM3;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnPM_Handler; /* 0 Power Manager */\r
+ void* pfnSYSCTRL_Handler; /* 1 System Control */\r
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */\r
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */\r
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */\r
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */\r
+ void* pfnEVSYS_Handler; /* 6 Event System Interface */\r
+ void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */\r
+ void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */\r
+ void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */\r
+ void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */\r
+ void* pfnSERCOM4_Handler; /* 11 Serial Communication Interface 4 */\r
+ void* pfnSERCOM5_Handler; /* 12 Serial Communication Interface 5 */\r
+ void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 19 Basic Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 20 Basic Timer Counter 7 */\r
+ void* pfnADC_Handler; /* 21 Analog Digital Converter */\r
+ void* pfnAC_Handler; /* 22 Analog Comparators */\r
+ void* pfnDAC_Handler; /* 23 Digital Analog Converter */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M0+ processor handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void );\r
+void SYSCTRL_Handler ( void );\r
+void WDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void EIC_Handler ( void );\r
+void NVMCTRL_Handler ( void );\r
+void EVSYS_Handler ( void );\r
+void SERCOM0_Handler ( void );\r
+void SERCOM1_Handler ( void );\r
+void SERCOM2_Handler ( void );\r
+void SERCOM3_Handler ( void );\r
+void SERCOM4_Handler ( void );\r
+void SERCOM5_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void ADC_Handler ( void );\r
+void AC_Handler ( void );\r
+void DAC_Handler ( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals\r
+ */\r
+\r
+#define LITTLE_ENDIAN 1 \r
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */\r
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm0plus.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_samd20.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20J18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J18_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_ac.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_dac.h"\r
+#include "component/component_dsu.h"\r
+#include "component/component_eic.h"\r
+#include "component/component_evsys.h"\r
+#include "component/component_gclk.h"\r
+#include "component/component_nvmctrl.h"\r
+#include "component/component_pac.h"\r
+#include "component/component_pm.h"\r
+#include "component/component_port.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_sercom.h"\r
+#include "component/component_sysctrl.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD20J18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J18_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_ac.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dac.h"\r
+#include "instance/instance_dsu.h"\r
+#include "instance/instance_eic.h"\r
+#include "instance/instance_evsys.h"\r
+#include "instance/instance_gclk.h"\r
+#include "instance/instance_nvmctrl.h"\r
+#include "instance/instance_pac0.h"\r
+#include "instance/instance_pac1.h"\r
+#include "instance/instance_pac2.h"\r
+#include "instance/instance_pm.h"\r
+#include "instance/instance_port.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_sercom0.h"\r
+#include "instance/instance_sercom1.h"\r
+#include "instance/instance_sercom2.h"\r
+#include "instance/instance_sercom3.h"\r
+#include "instance/instance_sercom4.h"\r
+#include "instance/instance_sercom5.h"\r
+#include "instance/instance_sysctrl.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_tc4.h"\r
+#include "instance/instance_tc5.h"\r
+#include "instance/instance_tc6.h"\r
+#include "instance/instance_tc7.h"\r
+#include "instance/instance_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAMD20J18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J18_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+// Peripheral instances on HPB0 bridge\r
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */\r
+#define ID_PM 1 /**< \brief Power Manager (PM) */\r
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */\r
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */\r
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */\r
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */\r
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */\r
+\r
+// Peripheral instances on HPB1 bridge\r
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */\r
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */\r
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */\r
+#define ID_PORT 35 /**< \brief Port Module (PORT) */\r
+\r
+// Peripheral instances on HPB2 bridge\r
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */\r
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */\r
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */\r
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */\r
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */\r
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */\r
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */\r
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */\r
+#define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */\r
+#define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */\r
+#define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */\r
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */\r
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */\r
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */\r
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */\r
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */\r
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */\r
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */\r
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */\r
+\r
+#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAMD20J18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J18_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)\r
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#else\r
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */\r
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */\r
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */\r
+\r
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */\r
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */\r
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */\r
+\r
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */\r
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */\r
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */\r
+\r
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */\r
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */\r
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */\r
+\r
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */\r
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */\r
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */\r
+\r
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */\r
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */\r
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */\r
+\r
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */\r
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */\r
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */\r
+\r
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */\r
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */\r
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */\r
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */\r
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */\r
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */\r
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */\r
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */\r
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */\r
+\r
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */\r
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */\r
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */\r
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */\r
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */\r
+\r
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */\r
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */\r
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */\r
+\r
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */\r
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */\r
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */\r
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */\r
+\r
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */\r
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */\r
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */\r
+\r
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */\r
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */\r
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */\r
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */\r
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */\r
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */\r
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */\r
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */\r
+\r
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */\r
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */\r
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */\r
+\r
+#define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */\r
+#define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */\r
+#define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */\r
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */\r
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */\r
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */\r
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */\r
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */\r
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */\r
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */\r
+\r
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */\r
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */\r
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */\r
+\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PORT DEFINITIONS FOR SAMD20J18 */\r
+/* ************************************************************************** */\r
+/** \defgroup SAMD20J18_port PORT Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samd20j18.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAMD20J18 */\r
+/* ************************************************************************** */\r
+\r
+#define FLASH_SIZE 0x40000 /* 256 kB */\r
+#define FLASH_PAGE_SIZE 64\r
+#define FLASH_NB_OF_PAGES 4096\r
+#define FLASH_USER_PAGE_SIZE 64\r
+#define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */\r
+\r
+/* ************************************************************************** */\r
+/** ELECTRICAL DEFINITIONS FOR SAMD20J18 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAMD20J18_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief GCC start-up implementation for the SAM D20\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "samd20.h"\r
+\r
+/* Initialize segments */\r
+extern uint32_t _sfixed;\r
+extern uint32_t _efixed;\r
+extern uint32_t _etext;\r
+extern uint32_t _srelocate;\r
+extern uint32_t _erelocate;\r
+extern uint32_t _szero;\r
+extern uint32_t _ezero;\r
+extern uint32_t _sstack;\r
+extern uint32_t _estack;\r
+\r
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */\r
+int main(void);\r
+/** \endcond */\r
+\r
+void __libc_init_array(void);\r
+\r
+/* Default empty handler */\r
+void Dummy_Handler(void);\r
+\r
+/* Cortex-M0+ core handlers */\r
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+\r
+/* Peripherals handlers */\r
+void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+\r
+/* Exception Table */\r
+__attribute__ ((section(".vectors")))\r
+const DeviceVectors exception_table = {\r
+\r
+ /* Configure Initial Stack Pointer, using linker-generated symbols */\r
+ (void*) (&_estack),\r
+\r
+ (void*) Reset_Handler,\r
+ (void*) NMI_Handler,\r
+ (void*) HardFault_Handler,\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) SVC_Handler,\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) PendSV_Handler,\r
+ (void*) SysTick_Handler,\r
+\r
+ /* Configurable interrupts */\r
+ (void*) PM_Handler, /* 0 Power Manager */\r
+ (void*) SYSCTRL_Handler, /* 1 System Control */\r
+ (void*) WDT_Handler, /* 2 Watchdog Timer */\r
+ (void*) RTC_Handler, /* 3 Real-Time Counter */\r
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */\r
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */\r
+ (void*) EVSYS_Handler, /* 6 Event System Interface */\r
+ (void*) SERCOM0_Handler, /* 7 Serial Communication Interface 0 */\r
+ (void*) SERCOM1_Handler, /* 8 Serial Communication Interface 1 */\r
+ (void*) SERCOM2_Handler, /* 9 Serial Communication Interface 2 */\r
+ (void*) SERCOM3_Handler, /* 10 Serial Communication Interface 3 */\r
+ (void*) SERCOM4_Handler, /* 11 Serial Communication Interface 4 */\r
+ (void*) SERCOM5_Handler, /* 12 Serial Communication Interface 5 */\r
+ (void*) TC0_Handler, /* 13 Basic Timer Counter 0 */\r
+ (void*) TC1_Handler, /* 14 Basic Timer Counter 1 */\r
+ (void*) TC2_Handler, /* 15 Basic Timer Counter 2 */\r
+ (void*) TC3_Handler, /* 16 Basic Timer Counter 3 */\r
+ (void*) TC4_Handler, /* 17 Basic Timer Counter 4 */\r
+ (void*) TC5_Handler, /* 18 Basic Timer Counter 5 */\r
+ (void*) TC6_Handler, /* 19 Basic Timer Counter 6 */\r
+ (void*) TC7_Handler, /* 20 Basic Timer Counter 7 */\r
+ (void*) ADC_Handler, /* 21 Analog Digital Converter */\r
+ (void*) AC_Handler, /* 22 Analog Comparators */\r
+ (void*) DAC_Handler /* 23 Digital Analog Converter */\r
+};\r
+\r
+/**\r
+ * \brief This is the code that gets called on processor reset.\r
+ * To initialize the device, and call the main() routine.\r
+ */\r
+void Reset_Handler(void)\r
+{\r
+ uint32_t *pSrc, *pDest;\r
+\r
+ /* Initialize the relocate segment */\r
+ pSrc = &_etext;\r
+ pDest = &_srelocate;\r
+\r
+ if (pSrc != pDest) {\r
+ for (; pDest < &_erelocate;) {\r
+ *pDest++ = *pSrc++;\r
+ }\r
+ }\r
+\r
+ /* Clear the zero segment */\r
+ for (pDest = &_szero; pDest < &_ezero;) {\r
+ *pDest++ = 0;\r
+ }\r
+\r
+ /* Set the vector table base address */\r
+ pSrc = (uint32_t *) & _sfixed;\r
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);\r
+\r
+ /* Initialize the C library */\r
+ __libc_init_array();\r
+\r
+ /* Branch to main function */\r
+ main();\r
+\r
+ /* Infinite loop */\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for unused IRQs.\r
+ */\r
+void Dummy_Handler(void)\r
+{\r
+ while (1) {\r
+ }\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Low-level initialization functions called upon chip startup.\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "samd20.h"\r
+\r
+/**\r
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides\r
+ * the source for the main clock at chip startup.\r
+ */\r
+#define __SYSTEM_CLOCK (8000000)\r
+\r
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemCoreClock variable.\r
+ */\r
+void SystemInit(void)\r
+{\r
+ // Keep the default device state after reset\r
+ SystemCoreClock = __SYSTEM_CLOCK;\r
+ return;\r
+}\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @brief Updates the SystemCoreClock with current core Clock\r
+ * retrieved from cpu registers.\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ // Not implemented\r
+ SystemCoreClock = __SYSTEM_CLOCK;\r
+ return;\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Low-level initialization functions called upon chip startup\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SYSTEM_SAMD20_H_INCLUDED_\r
+#define _SYSTEM_SAMD20_H_INCLUDED_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+void SystemInit(void);\r
+void SystemCoreClockUpdate(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* SYSTEM_SAMD20_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Commonly used includes, types and macros.\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_COMPILER_H_INCLUDED\r
+#define UTILS_COMPILER_H_INCLUDED\r
+\r
+/**\r
+ * \defgroup group_sam0_utils Compiler abstraction layer and code utilities\r
+ *\r
+ * Compiler abstraction layer and code utilities for AT91SAMD20.\r
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if (defined __ICCARM__)\r
+# include <intrinsics.h>\r
+#endif\r
+\r
+#include <stddef.h>\r
+#include <parts.h>\r
+#include <status_codes.h>\r
+#include <preprocessor.h>\r
+#include <io.h>\r
+\r
+#ifndef __ASSEMBLY__\r
+\r
+#include <stdio.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+\r
+/**\r
+ * \def UNUSED\r
+ * \brief Marking \a v as a unused parameter or value.\r
+ */\r
+#define UNUSED(v) (void)(v)\r
+\r
+/**\r
+ * \def barrier\r
+ * \brief Memory barrier\r
+ */\r
+#ifdef __GNUC__\r
+# define barrier() asm volatile("" ::: "memory")\r
+#else\r
+# define barrier() asm ("")\r
+#endif\r
+\r
+/**\r
+ * \brief Emit the compiler pragma \a arg.\r
+ *\r
+ * \param[in] arg The pragma directive as it would appear after \e \#pragma\r
+ * (i.e. not stringified).\r
+ */\r
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)\r
+\r
+/**\r
+ * \def COMPILER_PACK_SET(alignment)\r
+ * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.\r
+ */\r
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))\r
+\r
+/**\r
+ * \def COMPILER_PACK_RESET()\r
+ * \brief Set default alignment for subsequent struct and union definitions.\r
+ */\r
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())\r
+\r
+\r
+/**\r
+ * \brief Set aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))\r
+#elif (defined __ICCARM__)\r
+# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)\r
+#endif\r
+\r
+/**\r
+ * \brief Set word-aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || defined(__CC_ARM)\r
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))\r
+#elif (defined __ICCARM__)\r
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)\r
+#endif\r
+\r
+/**\r
+ * \def __always_inline\r
+ * \brief The function should always be inlined.\r
+ *\r
+ * This annotation instructs the compiler to ignore its inlining\r
+ * heuristics and inline the function no matter how big it thinks it\r
+ * becomes.\r
+ */\r
+#if defined(__CC_ARM)\r
+# define __always_inline __forceinline\r
+#elif (defined __GNUC__)\r
+# define __always_inline __attribute__((__always_inline__))\r
+#elif (defined __ICCARM__)\r
+# define __always_inline _Pragma("inline=forced")\r
+#endif\r
+\r
+/**\r
+ * \def __no_inline\r
+ * \brief The function should never be inlined\r
+ *\r
+ * This annotation instructs the compiler to ignore its inlining\r
+ * heuristics and not inline the function no matter how small it thinks it\r
+ * becomes.\r
+ */\r
+#if defined(__CC_ARM)\r
+# define __no_inline __attribute__((noinline))\r
+#elif (defined __GNUC__)\r
+# define __no_inline __attribute__((noinline))\r
+#elif (defined __ICCARM__)\r
+# define __no_inline _Pragma("inline=never")\r
+#endif\r
+\r
+\r
+/** \brief This macro is used to test fatal errors.\r
+ *\r
+ * The macro tests if the expression is false. If it is, a fatal error is\r
+ * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO\r
+ * is defined, a unit test version of the macro is used, to allow execution\r
+ * of further tests after a false expression.\r
+ *\r
+ * \param[in] expr Expression to evaluate and supposed to be nonzero.\r
+ */\r
+#if defined(_ASSERT_ENABLE_)\r
+# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)\r
+# include "unit_test/suite.h"\r
+# else\r
+# undef TEST_SUITE_DEFINE_ASSERT_MACRO\r
+# define Assert(expr) \\r
+ {\\r
+ if (!(expr)) asm("BKPT #0");\\r
+ }\r
+# endif\r
+#else\r
+# define Assert(expr) ((void) 0)\r
+#endif\r
+\r
+/* Define WEAK attribute */\r
+#if defined ( __CC_ARM )\r
+# define WEAK __attribute__ ((weak))\r
+#elif defined ( __ICCARM__ )\r
+# define WEAK __weak\r
+#elif defined ( __GNUC__ )\r
+# define WEAK __attribute__ ((weak))\r
+#endif\r
+\r
+/* Define NO_INIT attribute */\r
+#if defined ( __CC_ARM )\r
+# define NO_INIT __attribute__((zero_init))\r
+#elif defined ( __ICCARM__ )\r
+# define NO_INIT __no_init\r
+#elif defined ( __GNUC__ )\r
+# define NO_INIT __attribute__((section(".no_init")))\r
+#endif\r
+\r
+#include "interrupt.h"\r
+\r
+/** \name Usual Types\r
+ * @{ */\r
+#ifndef __cplusplus\r
+# if !defined(__bool_true_false_are_defined)\r
+typedef unsigned char bool;\r
+# endif\r
+#endif\r
+typedef uint16_t le16_t;\r
+typedef uint16_t be16_t;\r
+typedef uint32_t le32_t;\r
+typedef uint32_t be32_t;\r
+typedef uint32_t iram_size_t;\r
+/** @} */\r
+\r
+/** \name Aliasing Aggregate Types\r
+ * @{ */\r
+\r
+/** 16-bit union. */\r
+typedef union\r
+{\r
+ int16_t s16;\r
+ uint16_t u16;\r
+ int8_t int8_t[2];\r
+ uint8_t uint8_t[2];\r
+} Union16;\r
+\r
+/** 32-bit union. */\r
+typedef union\r
+{\r
+ int32_t s32;\r
+ uint32_t u32;\r
+ int16_t s16[2];\r
+ uint16_t u16[2];\r
+ int8_t int8_t[4];\r
+ uint8_t uint8_t[4];\r
+} Union32;\r
+\r
+/** 64-bit union. */\r
+typedef union\r
+{\r
+ int64_t s64;\r
+ uint64_t u64;\r
+ int32_t s32[2];\r
+ uint32_t u32[2];\r
+ int16_t s16[4];\r
+ uint16_t u16[4];\r
+ int8_t int8_t[8];\r
+ uint8_t uint8_t[8];\r
+} Union64;\r
+\r
+/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */\r
+typedef union\r
+{\r
+ int64_t *s64ptr;\r
+ uint64_t *u64ptr;\r
+ int32_t *s32ptr;\r
+ uint32_t *u32ptr;\r
+ int16_t *s16ptr;\r
+ uint16_t *u16ptr;\r
+ int8_t *s8ptr;\r
+ uint8_t *u8ptr;\r
+} UnionPtr;\r
+\r
+/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */\r
+typedef union\r
+{\r
+ volatile int64_t *s64ptr;\r
+ volatile uint64_t *u64ptr;\r
+ volatile int32_t *s32ptr;\r
+ volatile uint32_t *u32ptr;\r
+ volatile int16_t *s16ptr;\r
+ volatile uint16_t *u16ptr;\r
+ volatile int8_t *s8ptr;\r
+ volatile uint8_t *u8ptr;\r
+} UnionVPtr;\r
+\r
+/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */\r
+typedef union\r
+{\r
+ const int64_t *s64ptr;\r
+ const uint64_t *u64ptr;\r
+ const int32_t *s32ptr;\r
+ const uint32_t *u32ptr;\r
+ const int16_t *s16ptr;\r
+ const uint16_t *u16ptr;\r
+ const int8_t *s8ptr;\r
+ const uint8_t *u8ptr;\r
+} UnionCPtr;\r
+\r
+/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */\r
+typedef union\r
+{\r
+ const volatile int64_t *s64ptr;\r
+ const volatile uint64_t *u64ptr;\r
+ const volatile int32_t *s32ptr;\r
+ const volatile uint32_t *u32ptr;\r
+ const volatile int16_t *s16ptr;\r
+ const volatile uint16_t *u16ptr;\r
+ const volatile int8_t *s8ptr;\r
+ const volatile uint8_t *u8ptr;\r
+} UnionCVPtr;\r
+\r
+/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */\r
+typedef struct\r
+{\r
+ int64_t *s64ptr;\r
+ uint64_t *u64ptr;\r
+ int32_t *s32ptr;\r
+ uint32_t *u32ptr;\r
+ int16_t *s16ptr;\r
+ uint16_t *u16ptr;\r
+ int8_t *s8ptr;\r
+ uint8_t *u8ptr;\r
+} StructPtr;\r
+\r
+/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */\r
+typedef struct\r
+{\r
+ volatile int64_t *s64ptr;\r
+ volatile uint64_t *u64ptr;\r
+ volatile int32_t *s32ptr;\r
+ volatile uint32_t *u32ptr;\r
+ volatile int16_t *s16ptr;\r
+ volatile uint16_t *u16ptr;\r
+ volatile int8_t *s8ptr;\r
+ volatile uint8_t *u8ptr;\r
+} StructVPtr;\r
+\r
+/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */\r
+typedef struct\r
+{\r
+ const int64_t *s64ptr;\r
+ const uint64_t *u64ptr;\r
+ const int32_t *s32ptr;\r
+ const uint32_t *u32ptr;\r
+ const int16_t *s16ptr;\r
+ const uint16_t *u16ptr;\r
+ const int8_t *s8ptr;\r
+ const uint8_t *u8ptr;\r
+} StructCPtr;\r
+\r
+/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */\r
+typedef struct\r
+{\r
+ const volatile int64_t *s64ptr;\r
+ const volatile uint64_t *u64ptr;\r
+ const volatile int32_t *s32ptr;\r
+ const volatile uint32_t *u32ptr;\r
+ const volatile int16_t *s16ptr;\r
+ const volatile uint16_t *u16ptr;\r
+ const volatile int8_t *s8ptr;\r
+ const volatile uint8_t *u8ptr;\r
+} StructCVPtr;\r
+\r
+/** @} */\r
+\r
+#endif /* #ifndef __ASSEMBLY__ */\r
+\r
+/** \name Usual Constants\r
+ * @{ */\r
+#define DISABLE 0\r
+#define ENABLE 1\r
+\r
+#ifndef __cplusplus\r
+# if !defined(__bool_true_false_are_defined)\r
+# define false 0\r
+# define true 1\r
+# endif\r
+#endif\r
+/** @} */\r
+\r
+#ifndef __ASSEMBLY__\r
+\r
+/** \name Optimization Control\r
+ * @{ */\r
+\r
+/**\r
+ * \def likely(exp)\r
+ * \brief The expression \a exp is likely to be true\r
+ */\r
+#if !defined(likely) || defined(__DOXYGEN__)\r
+# define likely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def unlikely(exp)\r
+ * \brief The expression \a exp is unlikely to be true\r
+ */\r
+#if !defined(unlikely) || defined(__DOXYGEN__)\r
+# define unlikely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def is_constant(exp)\r
+ * \brief Determine if an expression evaluates to a constant value.\r
+ *\r
+ * \param[in] exp Any expression\r
+ *\r
+ * \return true if \a exp is constant, false otherwise.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define is_constant(exp) __builtin_constant_p(exp)\r
+#else\r
+# define is_constant(exp) (0)\r
+#endif\r
+\r
+/** @} */\r
+\r
+/** \name Bit-Field Handling\r
+ * @{ */\r
+\r
+/*! \brief Reads the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param[in] value Value to read bits from.\r
+ * \param[in] mask Bit-mask indicating bits to read.\r
+ *\r
+ * \return Read bits.\r
+ */\r
+#define Rd_bits( value, mask) ((value) & (mask))\r
+\r
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param[in] lvalue C lvalue to write bits to.\r
+ * \param[in] mask Bit-mask indicating bits to write.\r
+ * \param[in] bits Bits to write.\r
+ *\r
+ * \return Resulting value with written bits.\r
+ */\r
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\\r
+ ((bits ) & (mask)))\r
+\r
+/*! \brief Tests the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param[in] value Value of which to test bits.\r
+ * \param[in] mask Bit-mask indicating bits to test.\r
+ *\r
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.\r
+ */\r
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)\r
+\r
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param[in] lvalue C lvalue of which to clear bits.\r
+ * \param[in] mask Bit-mask indicating bits to clear.\r
+ *\r
+ * \return Resulting value with cleared bits.\r
+ */\r
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))\r
+\r
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param[in] lvalue C lvalue of which to set bits.\r
+ * \param[in] mask Bit-mask indicating bits to set.\r
+ *\r
+ * \return Resulting value with set bits.\r
+ */\r
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))\r
+\r
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param[in] lvalue C lvalue of which to toggle bits.\r
+ * \param[in] mask Bit-mask indicating bits to toggle.\r
+ *\r
+ * \return Resulting value with toggled bits.\r
+ */\r
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))\r
+\r
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.\r
+ *\r
+ * \param[in] value Value to read a bit-field from.\r
+ * \param[in] mask Bit-mask indicating the bit-field to read.\r
+ *\r
+ * \return Read bit-field.\r
+ */\r
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))\r
+\r
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param[in] lvalue C lvalue to write a bit-field to.\r
+ * \param[in] mask Bit-mask indicating the bit-field to write.\r
+ * \param[in] bitfield Bit-field to write.\r
+ *\r
+ * \return Resulting value with written bit-field.\r
+ */\r
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask)))\r
+\r
+/** @} */\r
+\r
+\r
+/** \name Zero-Bit Counting\r
+ *\r
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when\r
+ * applied to constant expressions (values known at compile time), so they are\r
+ * more optimized than the use of the corresponding assembly instructions and\r
+ * they can be used as constant expressions e.g. to initialize objects having\r
+ * static storage duration, and like the corresponding assembly instructions\r
+ * when applied to non-constant expressions (values unknown at compile time), so\r
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz\r
+ * ensure a possible and optimized behavior for both constant and non-constant\r
+ * expressions.\r
+ *\r
+ * @{ */\r
+\r
+/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param[in] u Value of which to count the leading zero bits.\r
+ *\r
+ * \return The count of leading zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define clz(u) __builtin_clz(u)\r
+#elif (defined __ICCARM__)\r
+# define clz(u) __CLZ(u)\r
+#else\r
+# define clz(u) (((u) == 0) ? 32 : \\r
+ ((u) & (1ul << 31)) ? 0 : \\r
+ ((u) & (1ul << 30)) ? 1 : \\r
+ ((u) & (1ul << 29)) ? 2 : \\r
+ ((u) & (1ul << 28)) ? 3 : \\r
+ ((u) & (1ul << 27)) ? 4 : \\r
+ ((u) & (1ul << 26)) ? 5 : \\r
+ ((u) & (1ul << 25)) ? 6 : \\r
+ ((u) & (1ul << 24)) ? 7 : \\r
+ ((u) & (1ul << 23)) ? 8 : \\r
+ ((u) & (1ul << 22)) ? 9 : \\r
+ ((u) & (1ul << 21)) ? 10 : \\r
+ ((u) & (1ul << 20)) ? 11 : \\r
+ ((u) & (1ul << 19)) ? 12 : \\r
+ ((u) & (1ul << 18)) ? 13 : \\r
+ ((u) & (1ul << 17)) ? 14 : \\r
+ ((u) & (1ul << 16)) ? 15 : \\r
+ ((u) & (1ul << 15)) ? 16 : \\r
+ ((u) & (1ul << 14)) ? 17 : \\r
+ ((u) & (1ul << 13)) ? 18 : \\r
+ ((u) & (1ul << 12)) ? 19 : \\r
+ ((u) & (1ul << 11)) ? 20 : \\r
+ ((u) & (1ul << 10)) ? 21 : \\r
+ ((u) & (1ul << 9)) ? 22 : \\r
+ ((u) & (1ul << 8)) ? 23 : \\r
+ ((u) & (1ul << 7)) ? 24 : \\r
+ ((u) & (1ul << 6)) ? 25 : \\r
+ ((u) & (1ul << 5)) ? 26 : \\r
+ ((u) & (1ul << 4)) ? 27 : \\r
+ ((u) & (1ul << 3)) ? 28 : \\r
+ ((u) & (1ul << 2)) ? 29 : \\r
+ ((u) & (1ul << 1)) ? 30 : \\r
+ 31)\r
+#endif\r
+\r
+/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param[in] u Value of which to count the trailing zero bits.\r
+ *\r
+ * \return The count of trailing zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define ctz(u) __builtin_ctz(u)\r
+#else\r
+# define ctz(u) ((u) & (1ul << 0) ? 0 : \\r
+ (u) & (1ul << 1) ? 1 : \\r
+ (u) & (1ul << 2) ? 2 : \\r
+ (u) & (1ul << 3) ? 3 : \\r
+ (u) & (1ul << 4) ? 4 : \\r
+ (u) & (1ul << 5) ? 5 : \\r
+ (u) & (1ul << 6) ? 6 : \\r
+ (u) & (1ul << 7) ? 7 : \\r
+ (u) & (1ul << 8) ? 8 : \\r
+ (u) & (1ul << 9) ? 9 : \\r
+ (u) & (1ul << 10) ? 10 : \\r
+ (u) & (1ul << 11) ? 11 : \\r
+ (u) & (1ul << 12) ? 12 : \\r
+ (u) & (1ul << 13) ? 13 : \\r
+ (u) & (1ul << 14) ? 14 : \\r
+ (u) & (1ul << 15) ? 15 : \\r
+ (u) & (1ul << 16) ? 16 : \\r
+ (u) & (1ul << 17) ? 17 : \\r
+ (u) & (1ul << 18) ? 18 : \\r
+ (u) & (1ul << 19) ? 19 : \\r
+ (u) & (1ul << 20) ? 20 : \\r
+ (u) & (1ul << 21) ? 21 : \\r
+ (u) & (1ul << 22) ? 22 : \\r
+ (u) & (1ul << 23) ? 23 : \\r
+ (u) & (1ul << 24) ? 24 : \\r
+ (u) & (1ul << 25) ? 25 : \\r
+ (u) & (1ul << 26) ? 26 : \\r
+ (u) & (1ul << 27) ? 27 : \\r
+ (u) & (1ul << 28) ? 28 : \\r
+ (u) & (1ul << 29) ? 29 : \\r
+ (u) & (1ul << 30) ? 30 : \\r
+ (u) & (1ul << 31) ? 31 : \\r
+ 32)\r
+#endif\r
+\r
+/** @} */\r
+\r
+\r
+/** \name Bit Reversing\r
+ * @{ */\r
+\r
+/** \brief Reverses the bits of \a u8.\r
+ *\r
+ * \param[in] u8 U8 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u8 with reversed bits.\r
+ */\r
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))\r
+\r
+/** \brief Reverses the bits of \a u16.\r
+ *\r
+ * \param[in] u16 U16 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u16 with reversed bits.\r
+ */\r
+#define bit_reverse16(u16) ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16))\r
+\r
+/** \brief Reverses the bits of \a u32.\r
+ *\r
+ * \param[in] u32 U32 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u32 with reversed bits.\r
+ */\r
+#define bit_reverse32(u32) __RBIT(u32)\r
+\r
+/** \brief Reverses the bits of \a u64.\r
+ *\r
+ * \param[in] u64 U64 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u64 with reversed bits.\r
+ */\r
+#define bit_reverse64(u64) ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) |\\r
+ ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32)))\r
+\r
+/** @} */\r
+\r
+\r
+/** \name Alignment\r
+ * @{ */\r
+\r
+/** \brief Tests alignment of the number \a val with the \a n boundary.\r
+ *\r
+ * \param[in] val Input value.\r
+ * \param[in] n Boundary.\r
+ *\r
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.\r
+ */\r
+#define Test_align(val, n) (!Tst_bits( val, (n) - 1 ) )\r
+\r
+/** \brief Gets alignment of the number \a val with respect to the \a n boundary.\r
+ *\r
+ * \param[in] val Input value.\r
+ * \param[in] n Boundary.\r
+ *\r
+ * \return Alignment of the number \a val with respect to the \a n boundary.\r
+ */\r
+#define Get_align(val, n) ( Rd_bits( val, (n) - 1 ) )\r
+\r
+/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.\r
+ *\r
+ * \param[in] lval Input/output lvalue.\r
+ * \param[in] n Boundary.\r
+ * \param[in] alg Alignment.\r
+ *\r
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.\r
+ */\r
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )\r
+\r
+/** \brief Aligns the number \a val with the upper \a n boundary.\r
+ *\r
+ * \param[in] val Input value.\r
+ * \param[in] n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.\r
+ */\r
+#define Align_up( val, n) (((val) + ((n) - 1)) & ~((n) - 1))\r
+\r
+/** \brief Aligns the number \a val with the lower \a n boundary.\r
+ *\r
+ * \param[in] val Input value.\r
+ * \param[in] n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.\r
+ */\r
+#define Align_down(val, n) ( (val) & ~((n) - 1))\r
+\r
+/** @} */\r
+\r
+\r
+/** \name Mathematics\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC does not\r
+ * provide built-in functions to access the assembly instructions abs, min and\r
+ * max and it does not produce them by itself in most cases, so two sets of\r
+ * macros are defined here:\r
+ * - Abs, Min and Max to apply to constant expressions (values known at\r
+ * compile time);\r
+ * - abs, min and max to apply to non-constant expressions (values unknown at\r
+ * compile time), abs is found in stdlib.h.\r
+ *\r
+ * @{ */\r
+\r
+/** \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param[in] a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))\r
+\r
+/** \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param[in] a Input value.\r
+ * \param[in] b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Min(a, b) (((a) < (b)) ? (a) : (b))\r
+\r
+/** \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param[in] a Input value.\r
+ * \param[in] b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Max(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+/** \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param[in] a Input value.\r
+ * \param[in] b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define min(a, b) Min(a, b)\r
+\r
+/** \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param[in] a Input value.\r
+ * \param[in] b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define max(a, b) Max(a, b)\r
+\r
+/** @} */\r
+\r
+\r
+/** \brief Calls the routine at address \a addr.\r
+ *\r
+ * It generates a long call opcode.\r
+ *\r
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if\r
+ * it is invoked from the CPU supervisor mode.\r
+ *\r
+ * \param[in] addr Address of the routine to call.\r
+ *\r
+ * \note It may be used as a long jump opcode in some special cases.\r
+ */\r
+#define Long_call(addr) ((*(void (*)(void))(addr))())\r
+\r
+\r
+/** \name MCU Endianism Handling\r
+ * ARM is MCU little endian.\r
+ *\r
+ * @{ */\r
+#define BE16(x) Swap16(x)\r
+#define LE16(x) (x)\r
+\r
+#define le16_to_cpu(x) (x)\r
+#define cpu_to_le16(x) (x)\r
+#define LE16_TO_CPU(x) (x)\r
+#define CPU_TO_LE16(x) (x)\r
+\r
+#define be16_to_cpu(x) Swap16(x)\r
+#define cpu_to_be16(x) Swap16(x)\r
+#define BE16_TO_CPU(x) Swap16(x)\r
+#define CPU_TO_BE16(x) Swap16(x)\r
+\r
+#define le32_to_cpu(x) (x)\r
+#define cpu_to_le32(x) (x)\r
+#define LE32_TO_CPU(x) (x)\r
+#define CPU_TO_LE32(x) (x)\r
+\r
+#define be32_to_cpu(x) swap32(x)\r
+#define cpu_to_be32(x) swap32(x)\r
+#define BE32_TO_CPU(x) swap32(x)\r
+#define CPU_TO_BE32(x) swap32(x)\r
+/** @} */\r
+\r
+\r
+/** \name Endianism Conversion\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC's\r
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when\r
+ * applied to constant expressions, so two sets of macros are defined here:\r
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known\r
+ * at compile time);\r
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values\r
+ * unknown at compile time).\r
+ *\r
+ * @{ */\r
+\r
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param[in] u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) |\\r
+ ((uint16_t)(u16) << 8)))\r
+\r
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param[in] u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) |\\r
+ ((uint32_t)Swap16((uint32_t)(u32)) << 16)))\r
+\r
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param[in] u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) |\\r
+ ((uint64_t)Swap32((uint64_t)(u64)) << 32)))\r
+\r
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param[in] u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define swap16(u16) Swap16(u16)\r
+\r
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param[in] u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32)))\r
+#else\r
+# define swap32(u32) Swap32(u32)\r
+#endif\r
+\r
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param[in] u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64)))\r
+#else\r
+# define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) |\\r
+ ((uint64_t)swap32((uint64_t)(u64)) << 32)))\r
+#endif\r
+\r
+/** @} */\r
+\r
+\r
+/** \name Target Abstraction\r
+ *\r
+ * @{ */\r
+\r
+#define _GLOBEXT_ extern /**< extern storage-class specifier. */\r
+#define _CONST_TYPE_ const /**< const type qualifier. */\r
+#define _MEM_TYPE_SLOW_ /**< Slow memory type. */\r
+#define _MEM_TYPE_MEDFAST_ /**< Fairly fast memory type. */\r
+#define _MEM_TYPE_FAST_ /**< Fast memory type. */\r
+\r
+#define memcmp_ram2ram memcmp /**< Target-specific memcmp of RAM to RAM. */\r
+#define memcmp_code2ram memcmp /**< Target-specific memcmp of RAM to NVRAM. */\r
+#define memcpy_ram2ram memcpy /**< Target-specific memcpy from RAM to RAM. */\r
+#define memcpy_code2ram memcpy /**< Target-specific memcpy from NVRAM to RAM. */\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using\r
+ * integer arithmetic.\r
+ *\r
+ * \param[in] a An integer\r
+ * \param[in] b Another integer\r
+ *\r
+ * \return (\a a / \a b) rounded up to the nearest integer.\r
+ */\r
+#define div_ceil(a, b) (((a) + (b) - 1) / (b))\r
+\r
+#endif /* #ifndef __ASSEMBLY__ */\r
+#ifdef __ICCARM__\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Port of some keywords from GCC to IAR Embedded Workbench.\r
+ */\r
+//! @{\r
+#define __asm__ asm\r
+#define __inline__ inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+/**\r
+ * \def unused\r
+ * \brief Marking \a v as a unused parameter or value.\r
+ */\r
+#define unused(v) do { (void)(v); } while(0)\r
+\r
+/* Define RAMFUNC attribute */\r
+#if defined ( __CC_ARM ) /* Keil uVision 4 */\r
+# define RAMFUNC __attribute__ ((section(".ramfunc")))\r
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\r
+# define RAMFUNC __ramfunc\r
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */\r
+# define RAMFUNC __attribute__ ((section(".ramfunc")))\r
+#endif\r
+\r
+/* Define OPTIMIZE_HIGH attribute */\r
+#if defined ( __CC_ARM ) /* Keil uVision 4 */\r
+# define OPTIMIZE_HIGH _Pragma("O3")\r
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\r
+# define OPTIMIZE_HIGH _Pragma("optimize=high")\r
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */\r
+# define OPTIMIZE_HIGH __attribute__((optimize(s)))\r
+#endif\r
+#define PASS 0\r
+#define FAIL 1\r
+#define LOW 0\r
+#define HIGH 1\r
+\r
+typedef int8_t S8 ; //!< 8-bit signed integer.\r
+typedef uint8_t U8 ; //!< 8-bit unsigned integer.\r
+typedef int16_t S16; //!< 16-bit signed integer.\r
+typedef uint16_t U16; //!< 16-bit unsigned integer.\r
+typedef int32_t S32; //!< 32-bit signed integer.\r
+typedef uint32_t U32; //!< 32-bit unsigned integer.\r
+typedef int64_t S64; //!< 64-bit signed integer.\r
+typedef uint64_t U64; //!< 64-bit unsigned integer.\r
+typedef float F32; //!< 32-bit floating-point number.\r
+typedef double F64; //!< 64-bit floating-point number.\r
+\r
+#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.\r
+#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.\r
+\r
+#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.\r
+#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.\r
+#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.\r
+#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.\r
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+\r
+#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.\r
+#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.\r
+#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.\r
+#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.\r
+#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.\r
+#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.\r
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.\r
+#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.\r
+#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.\r
+#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.\r
+#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.\r
+#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.\r
+#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.\r
+#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.\r
+#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.\r
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.\r
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.\r
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.\r
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.\r
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.\r
+\r
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
+#if defined(__ICCARM__)\r
+#define SHORTENUM __packed\r
+#elif defined(__GNUC__)\r
+#define SHORTENUM __attribute__((packed))\r
+#endif\r
+\r
+/* No operation */\r
+#if defined(__ICCARM__)\r
+#define nop() __no_operation()\r
+#elif defined(__GNUC__)\r
+#define nop() (__NOP())\r
+#endif\r
+\r
+#define FLASH_DECLARE(x) const x\r
+#define FLASH_EXTERN(x) extern const x\r
+#define PGM_READ_BYTE(x) *(x)\r
+#define PGM_READ_WORD(x) *(x)\r
+#define MEMCPY_ENDIAN memcpy\r
+#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))\r
+\r
+/* Converting of values from CPU endian to little endian. */\r
+#define CPU_ENDIAN_TO_LE16(x) (x)\r
+#define CPU_ENDIAN_TO_LE32(x) (x)\r
+#define CPU_ENDIAN_TO_LE64(x) (x)\r
+\r
+/* Converting of values from little endian to CPU endian. */\r
+#define LE16_TO_CPU_ENDIAN(x) (x)\r
+#define LE32_TO_CPU_ENDIAN(x) (x)\r
+#define LE64_TO_CPU_ENDIAN(x) (x)\r
+\r
+/* Converting of constants from little endian to CPU endian. */\r
+#define CLE16_TO_CPU_ENDIAN(x) (x)\r
+#define CLE32_TO_CPU_ENDIAN(x) (x)\r
+#define CLE64_TO_CPU_ENDIAN(x) (x)\r
+\r
+/* Converting of constants from CPU endian to little endian. */\r
+#define CCPU_ENDIAN_TO_LE16(x) (x)\r
+#define CCPU_ENDIAN_TO_LE32(x) (x)\r
+#define CCPU_ENDIAN_TO_LE64(x) (x)\r
+\r
+#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src))\r
+#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src))\r
+\r
+/**\r
+ * @brief Converts a 64-Bit value into a 8 Byte array\r
+ *\r
+ * @param[in] value 64-Bit value\r
+ * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value\r
+ * @ingroup apiPalApi\r
+ */\r
+static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)\r
+{\r
+ uint8_t index = 0;\r
+\r
+ while (index < 8)\r
+ {\r
+ data[index++] = value & 0xFF;\r
+ value = value >> 8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Converts a 16-Bit value into a 2 Byte array\r
+ *\r
+ * @param[in] value 16-Bit value\r
+ * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value\r
+ * @ingroup apiPalApi\r
+ */\r
+static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)\r
+{\r
+ data[0] = value & 0xFF;\r
+ data[1] = (value >> 8) & 0xFF;\r
+}\r
+\r
+/* Converts a 16-Bit value into a 2 Byte array */\r
+static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)\r
+{\r
+ data[0] = value & 0xFF;\r
+ data[1] = (value >> 8) & 0xFF;\r
+}\r
+\r
+/* Converts a 16-Bit value into a 2 Byte array */\r
+static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)\r
+{\r
+ data[0] = value & 0xFF;\r
+ data[1] = (value >> 8) & 0xFF;\r
+}\r
+\r
+/*\r
+ * @brief Converts a 2 Byte array into a 16-Bit value\r
+ *\r
+ * @param data Specifies the pointer to the 2 Byte array\r
+ *\r
+ * @return 16-Bit value\r
+ * @ingroup apiPalApi\r
+ */\r
+static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)\r
+{\r
+ return (data[0] | ((uint16_t)data[1] << 8));\r
+}\r
+\r
+/**\r
+ * @brief Converts a 8 Byte array into a 64-Bit value\r
+ *\r
+ * @param data Specifies the pointer to the 8 Byte array\r
+ *\r
+ * @return 64-Bit value\r
+ * @ingroup apiPalApi\r
+ */\r
+static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)\r
+{\r
+ union\r
+ {\r
+ uint64_t u64;\r
+ uint8_t u8[8];\r
+ } long_addr;\r
+\r
+ uint8_t index;\r
+\r
+ for (index = 0; index < 8; index++)\r
+ {\r
+ long_addr.u8[index] = *data++;\r
+ }\r
+\r
+ return long_addr.u64;\r
+}\r
+\r
+/** @} */\r
+\r
+#endif /* UTILS_COMPILER_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Arch file for SAM0.\r
+ *\r
+ * This file defines common SAM0 series.\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM_IO_\r
+#define _SAM_IO_\r
+\r
+#include <stddef.h>\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+\r
+/* SAM D20 family */\r
+#if (SAMD20)\r
+# include "samd20.h"\r
+#endif\r
+\r
+#endif /* _SAM_IO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Linker script for running in internal FLASH on the SAMD20J18\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+SEARCH_DIR(.)\r
+\r
+/* Memory Spaces Definitions */\r
+MEMORY\r
+{\r
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000\r
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\r
+}\r
+\r
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */\r
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000;\r
+\r
+/* Section Definitions */\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+ _sfixed = .;\r
+ KEEP(*(.vectors .vectors.*))\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *(.glue_7t) *(.glue_7)\r
+ *(.rodata .rodata* .gnu.linkonce.r.*)\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+\r
+ /* Support C constructors, and C destructors in both user code\r
+ and the C library. This also provides support for C++ code. */\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+\r
+ . = ALIGN(4);\r
+ _efixed = .; /* End of text section */\r
+ } > rom\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > rom\r
+ PROVIDE_HIDDEN (__exidx_end = .);\r
+\r
+ . = ALIGN(4);\r
+ _etext = .;\r
+\r
+ .relocate : AT (_etext)\r
+ {\r
+ . = ALIGN(4);\r
+ _srelocate = .;\r
+ *(.ramfunc .ramfunc.*);\r
+ *(.data .data.*);\r
+ . = ALIGN(4);\r
+ _erelocate = .;\r
+ } > ram\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+ .bss (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ _sbss = . ;\r
+ _szero = .;\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = . ;\r
+ _ezero = .;\r
+ } > ram\r
+\r
+ /* stack section */\r
+ .stack (NOLOAD):\r
+ {\r
+ . = ALIGN(8);\r
+ _sstack = .;\r
+ . = . + STACK_SIZE;\r
+ . = ALIGN(8);\r
+ _estack = .;\r
+ } > ram\r
+\r
+ . = ALIGN(4);\r
+ _end = . ;\r
+}\r
--- /dev/null
+# List of available make goals:\r
+#\r
+# all Default target, builds the project\r
+# clean Clean up the project\r
+# rebuild Rebuild the project\r
+# debug_flash Builds the project and debug in flash\r
+# debug_sram Builds the project and debug in sram\r
+#\r
+# doc Build the documentation\r
+# cleandoc Clean up the documentation\r
+# rebuilddoc Rebuild the documentation\r
+#\r
+# \file\r
+#\r
+# Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved.\r
+#\r
+# \asf_license_start\r
+#\r
+# \page License\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# 1. Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the following disclaimer.\r
+#\r
+# 2. Redistributions in binary form must reproduce the above copyright notice,\r
+# this list of conditions and the following disclaimer in the documentation\r
+# and/or other materials provided with the distribution.\r
+#\r
+# 3. The name of Atmel may not be used to endorse or promote products derived\r
+# from this software without specific prior written permission.\r
+#\r
+# 4. This software may only be redistributed and used in connection with an\r
+# Atmel microcontroller product.\r
+#\r
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+# POSSIBILITY OF SUCH DAMAGE.\r
+#\r
+# \asf_license_stop\r
+#\r
+\r
+# Include the config.mk file from the current working path, e.g., where the\r
+# user called make.\r
+include config.mk\r
+\r
+# Tool to use to generate documentation from the source code\r
+DOCGEN ?= doxygen\r
+\r
+# Look for source files relative to the top-level source directory\r
+VPATH := $(PRJ_PATH)\r
+\r
+# Output target file\r
+project_type := $(PROJECT_TYPE)\r
+\r
+# Output target file\r
+ifeq ($(project_type),flash)\r
+target := $(TARGET_FLASH)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)\r
+else\r
+target := $(TARGET_SRAM)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)\r
+endif\r
+\r
+# Output project name (target name minus suffix)\r
+project := $(basename $(target))\r
+\r
+# Output target file (typically ELF or static library)\r
+ifeq ($(suffix $(target)),.a)\r
+target_type := lib\r
+else\r
+ifeq ($(suffix $(target)),.elf)\r
+target_type := elf\r
+else\r
+$(error "Target type $(target_type) is not supported")\r
+endif\r
+endif\r
+\r
+# Allow override of operating system detection. The user can add OS=Linux or\r
+# OS=Windows on the command line to explicit set the host OS.\r
+#\r
+# This allows to work around broken uname utility on certain systems.\r
+ifdef OS\r
+ ifeq ($(strip $(OS)), Linux)\r
+ os_type := Linux\r
+ endif\r
+ ifeq ($(strip $(OS)), Windows)\r
+ os_type := windows32_64\r
+ endif\r
+endif\r
+\r
+os_type ?= $(strip $(shell uname))\r
+\r
+ifeq ($(os_type),windows32)\r
+os := Windows\r
+else\r
+ifeq ($(os_type),windows64)\r
+os := Windows\r
+else\r
+ifeq ($(os_type),windows32_64)\r
+os ?= Windows\r
+else\r
+ifeq ($(os_type),)\r
+os := Windows\r
+else\r
+# Default to Linux style operating system. Both Cygwin and mingw are fully\r
+# compatible (for this Makefile) with Linux.\r
+os := Linux\r
+endif\r
+endif\r
+endif\r
+endif\r
+\r
+# Output documentation directory and configuration file.\r
+docdir := ../doxygen/html\r
+doccfg := ../doxygen/doxyfile.doxygen\r
+\r
+CROSS ?= arm-none-eabi-\r
+AR := $(CROSS)ar\r
+AS := $(CROSS)as\r
+CC := $(CROSS)gcc\r
+CPP := $(CROSS)gcc -E\r
+CXX := $(CROSS)g++\r
+LD := $(CROSS)g++\r
+NM := $(CROSS)nm\r
+OBJCOPY := $(CROSS)objcopy\r
+OBJDUMP := $(CROSS)objdump\r
+SIZE := $(CROSS)size\r
+GDB := $(CROSS)gdb\r
+\r
+RM := rm\r
+ifeq ($(os),Windows)\r
+RMDIR := rmdir /S /Q\r
+else\r
+RMDIR := rmdir -p --ignore-fail-on-non-empty\r
+endif\r
+\r
+# On Windows, we need to override the shell to force the use of cmd.exe\r
+ifeq ($(os),Windows)\r
+SHELL := cmd\r
+endif\r
+\r
+# Strings for beautifying output\r
+MSG_CLEAN_FILES = "RM *.o *.d"\r
+MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))"\r
+MSG_CLEAN_DOC = "RMDIR $(docdir)"\r
+MSG_MKDIR = "MKDIR $(dir $@)"\r
+\r
+MSG_INFO = "INFO "\r
+\r
+MSG_ARCHIVING = "AR $@"\r
+MSG_ASSEMBLING = "AS $@"\r
+MSG_BINARY_IMAGE = "OBJCOPY $@"\r
+MSG_COMPILING = "CC $@"\r
+MSG_COMPILING_CXX = "CXX $@"\r
+MSG_EXTENDED_LISTING = "OBJDUMP $@"\r
+MSG_IHEX_IMAGE = "OBJCOPY $@"\r
+MSG_LINKING = "LN $@"\r
+MSG_PREPROCESSING = "CPP $@"\r
+MSG_SIZE = "SIZE $@"\r
+MSG_SYMBOL_TABLE = "NM $@"\r
+\r
+MSG_GENERATING_DOC = "DOXYGEN $(docdir)"\r
+\r
+# Don't use make's built-in rules and variables\r
+MAKEFLAGS += -rR\r
+\r
+# Don't print 'Entering directory ...'\r
+MAKEFLAGS += --no-print-directory\r
+\r
+# Function for reversing the order of a list\r
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))\r
+\r
+# Hide command output by default, but allow the user to override this\r
+# by adding V=1 on the command line.\r
+#\r
+# This is inspired by the Kbuild system used by the Linux kernel.\r
+ifdef V\r
+ ifeq ("$(origin V)", "command line")\r
+ VERBOSE = $(V)\r
+ endif\r
+endif\r
+ifndef VERBOSE\r
+ VERBOSE = 0\r
+endif\r
+\r
+ifeq ($(VERBOSE), 1)\r
+ Q =\r
+else\r
+ Q = @\r
+endif\r
+\r
+arflags-gnu-y := $(ARFLAGS)\r
+asflags-gnu-y := $(ASFLAGS)\r
+cflags-gnu-y := $(CFLAGS)\r
+cxxflags-gnu-y := $(CXXFLAGS)\r
+cppflags-gnu-y := $(CPPFLAGS)\r
+cpuflags-gnu-y :=\r
+dbgflags-gnu-y := $(DBGFLAGS)\r
+libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB))\r
+ldflags-gnu-y := $(LDFLAGS)\r
+flashflags-gnu-y :=\r
+clean-files :=\r
+clean-dirs :=\r
+\r
+clean-files += $(wildcard $(target) $(project).map)\r
+clean-files += $(wildcard $(project).hex $(project).bin)\r
+clean-files += $(wildcard $(project).lss $(project).sym)\r
+clean-files += $(wildcard $(build))\r
+\r
+# Use pipes instead of temporary files for communication between processes\r
+cflags-gnu-y += -pipe\r
+asflags-gnu-y += -pipe\r
+ldflags-gnu-y += -pipe\r
+\r
+# Archiver flags.\r
+arflags-gnu-y += rcs\r
+\r
+# Always enable warnings. And be very careful about implicit\r
+# declarations.\r
+cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes\r
+cflags-gnu-y += -Werror-implicit-function-declaration\r
+cxxflags-gnu-y += -Wall\r
+# IAR doesn't allow arithmetic on void pointers, so warn about that.\r
+cflags-gnu-y += -Wpointer-arith\r
+cxxflags-gnu-y += -Wpointer-arith\r
+\r
+# Preprocessor flags.\r
+cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))\r
+asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')\r
+\r
+# CPU specific flags.\r
+cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__\r
+\r
+# Dependency file flags.\r
+depflags = -MD -MP -MQ $@\r
+\r
+# Debug specific flags.\r
+ifdef BUILD_DEBUG_LEVEL\r
+dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL)\r
+else\r
+dbgflags-gnu-y += -g3\r
+endif\r
+\r
+# Optimization specific flags.\r
+ifdef BUILD_OPTIMIZATION\r
+optflags-gnu-y = -O$(BUILD_OPTIMIZATION)\r
+else\r
+optflags-gnu-y = $(OPTIMIZATION)\r
+endif\r
+\r
+# Always preprocess assembler files.\r
+asflags-gnu-y += -x assembler-with-cpp\r
+# Compile C files using the GNU99 standard.\r
+cflags-gnu-y += -std=gnu99\r
+# Compile C++ files using the GNU++98 standard.\r
+cxxflags-gnu-y += -std=gnu++98\r
+\r
+# Don't use strict aliasing (very common in embedded applications).\r
+cflags-gnu-y += -fno-strict-aliasing\r
+cxxflags-gnu-y += -fno-strict-aliasing\r
+\r
+# Separate each function and data into its own separate section to allow\r
+# garbage collection of unused sections.\r
+cflags-gnu-y += -ffunction-sections -fdata-sections\r
+cxxflags-gnu-y += -ffunction-sections -fdata-sections\r
+\r
+# Various cflags.\r
+cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int\r
+cflags-gnu-y += -Wmain -Wparentheses\r
+cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused\r
+cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef\r
+cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings\r
+cflags-gnu-y += -Wsign-compare -Waggregate-return\r
+cflags-gnu-y += -Wmissing-declarations\r
+cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations\r
+cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long\r
+cflags-gnu-y += -Wunreachable-code\r
+cflags-gnu-y += -Wcast-align\r
+cflags-gnu-y += --param max-inline-insns-single=500\r
+\r
+# To reduce application size use only integer printf function.\r
+cflags-gnu-y += -Dprintf=iprintf\r
+\r
+# Garbage collect unreferred sections when linking.\r
+ldflags-gnu-y += -Wl,--gc-sections\r
+\r
+# Use the linker script if provided by the project.\r
+ifneq ($(strip $(linker_script)),)\r
+ldflags-gnu-y += -Wl,-T $(linker_script)\r
+endif\r
+\r
+# Output a link map file and a cross reference table\r
+ldflags-gnu-y += -Wl,-Map=$(project).map,--cref\r
+\r
+# Add library search paths relative to the top level directory.\r
+ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))\r
+\r
+a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__\r
+c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)\r
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)\r
+l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)\r
+ar_flags = $(arflags-gnu-y)\r
+\r
+# Source files list and part informations must already be included before\r
+# running this makefile\r
+\r
+# If a custom build directory is specified, use it -- force trailing / in directory name.\r
+ifdef BUILD_DIR\r
+ build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)\r
+else\r
+ build-dir =\r
+endif\r
+\r
+# Create object files list from source files list.\r
+obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))\r
+# Create dependency files list from source files list.\r
+dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))\r
+\r
+clean-files += $(wildcard $(obj-y))\r
+clean-files += $(dep-files)\r
+\r
+clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))\r
+\r
+# Default target.\r
+.PHONY: all\r
+ifeq ($(project_type),all)\r
+all:\r
+ $(MAKE) all PROJECT_TYPE=flash\r
+ $(MAKE) all PROJECT_TYPE=sram\r
+else\r
+ifeq ($(target_type),lib)\r
+all: $(target) $(project).lss $(project).sym\r
+else\r
+ifeq ($(target_type),elf)\r
+all: $(target) $(project).lss $(project).sym $(project).hex $(project).bin\r
+endif\r
+endif\r
+endif\r
+\r
+# Clean up the project.\r
+.PHONY: clean\r
+clean:\r
+ @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))\r
+ $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)\r
+ @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))\r
+# Remove created directories, and make sure we only remove existing\r
+# directories, since recursive rmdir might help us a bit on the way.\r
+ifeq ($(os),Windows)\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ $(RMDIR) $(strip $(subst /,\,$(clean-dirs))))\r
+else\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ for directory in $(strip $(clean-dirs)); do \\r
+ if [ -d "$$directory" ]; then \\r
+ $(RMDIR) $$directory; \\r
+ fi \\r
+ done \\r
+ )\r
+endif\r
+\r
+# Rebuild the project.\r
+.PHONY: rebuild\r
+rebuild: clean all\r
+\r
+# Debug the project in flash.\r
+.PHONY: debug_flash\r
+debug_flash: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)\r
+\r
+# Debug the project in sram.\r
+.PHONY: debug_sram\r
+debug_sram: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)\r
+\r
+.PHONY: objfiles\r
+objfiles: $(obj-y)\r
+\r
+# Create object files from C source files.\r
+$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk\r
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))\r
+else\r
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING)\r
+ $(Q)$(CC) $(c_flags) -c $< -o $@\r
+\r
+# Create object files from C++ source files.\r
+$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk\r
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))\r
+else\r
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING_CXX)\r
+ $(Q)$(CXX) $(cxx_flags) -c $< -o $@\r
+\r
+# Preprocess and assemble: create object files from assembler source files.\r
+$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk\r
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))\r
+else\r
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_ASSEMBLING)\r
+ $(Q)$(CC) $(a_flags) -c $< -o $@\r
+\r
+# Include all dependency files to add depedency to all header files in use.\r
+include $(dep-files)\r
+\r
+ifeq ($(target_type),lib)\r
+# Archive object files into an archive\r
+$(target): $(MAKEFILE_PATH) config.mk $(obj-y)\r
+ @echo $(MSG_ARCHIVING)\r
+ $(Q)$(AR) $(ar_flags) $@ $(obj-y)\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Bxt $@\r
+else\r
+ifeq ($(target_type),elf)\r
+# Link the object files into an ELF file. Also make sure the target is rebuilt\r
+# if the common Makefile.sam.in or project config.mk is changed.\r
+$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y)\r
+ @echo $(MSG_LINKING)\r
+ $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Ax $@\r
+ $(Q)$(SIZE) -Bx $@\r
+endif\r
+endif\r
+\r
+# Create extended function listing from target output file.\r
+%.lss: $(target)\r
+ @echo $(MSG_EXTENDED_LISTING)\r
+ $(Q)$(OBJDUMP) -h -S $< > $@\r
+\r
+# Create symbol table from target output file.\r
+%.sym: $(target)\r
+ @echo $(MSG_SYMBOL_TABLE)\r
+ $(Q)$(NM) -n $< > $@\r
+\r
+# Create Intel HEX image from ELF output file.\r
+%.hex: $(target)\r
+ @echo $(MSG_IHEX_IMAGE)\r
+ $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@\r
+\r
+# Create binary image from ELF output file.\r
+%.bin: $(target)\r
+ @echo $(MSG_BINARY_IMAGE)\r
+ $(Q)$(OBJCOPY) -O binary $< $@\r
+\r
+# Provide information about the detected host operating system.\r
+.SECONDARY: info-os\r
+info-os:\r
+ @echo $(MSG_INFO)$(os) build host detected\r
+\r
+# Build Doxygen generated documentation.\r
+.PHONY: doc\r
+doc:\r
+ @echo $(MSG_GENERATING_DOC)\r
+ $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))\r
+\r
+# Clean Doxygen generated documentation.\r
+.PHONY: cleandoc\r
+cleandoc:\r
+ @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))\r
+ $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))\r
+\r
+# Rebuild the Doxygen generated documentation.\r
+.PHONY: rebuilddoc\r
+rebuilddoc: cleandoc doc\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor macro repeating utils.\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _MREPEAT_H_\r
+#define _MREPEAT_H_\r
+\r
+/**\r
+ * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat\r
+ *\r
+ * \ingroup group_sam0_utils\r
+ *\r
+ * @{\r
+ */\r
+\r
+#include "preprocessor.h"\r
+\r
+/** Maximal number of repetitions supported by MREPEAT. */\r
+#define MREPEAT_LIMIT 256\r
+\r
+/** \brief Macro repeat.\r
+ *\r
+ * This macro represents a horizontal repetition construct.\r
+ *\r
+ * \param[in] count The number of repetitious calls to macro. Valid values\r
+ * range from 0 to MREPEAT_LIMIT.\r
+ * \param[in] macro A binary operation of the form macro(n, data). This macro\r
+ * is expanded by MREPEAT with the current repetition number\r
+ * and the auxiliary data argument.\r
+ * \param[in] data Auxiliary data passed to macro.\r
+ *\r
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>\r
+ */\r
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data)\r
+\r
+#define MREPEAT0( macro, data)\r
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)\r
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)\r
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)\r
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)\r
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)\r
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)\r
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)\r
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)\r
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)\r
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)\r
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)\r
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)\r
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)\r
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)\r
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)\r
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)\r
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)\r
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)\r
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)\r
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)\r
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)\r
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)\r
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)\r
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)\r
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)\r
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)\r
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)\r
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)\r
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)\r
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)\r
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)\r
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)\r
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)\r
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)\r
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)\r
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)\r
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)\r
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)\r
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)\r
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)\r
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)\r
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)\r
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)\r
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)\r
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)\r
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)\r
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)\r
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)\r
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)\r
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)\r
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)\r
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)\r
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)\r
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)\r
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)\r
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)\r
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)\r
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)\r
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)\r
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)\r
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)\r
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)\r
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)\r
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)\r
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)\r
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)\r
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)\r
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)\r
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)\r
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)\r
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)\r
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)\r
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)\r
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)\r
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)\r
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)\r
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)\r
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)\r
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)\r
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)\r
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)\r
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)\r
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)\r
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)\r
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)\r
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)\r
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)\r
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)\r
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)\r
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)\r
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)\r
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)\r
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)\r
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)\r
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)\r
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)\r
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)\r
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)\r
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)\r
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)\r
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)\r
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)\r
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)\r
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)\r
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)\r
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)\r
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)\r
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)\r
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)\r
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)\r
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)\r
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)\r
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)\r
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)\r
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)\r
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)\r
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)\r
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)\r
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)\r
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)\r
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)\r
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)\r
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)\r
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)\r
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)\r
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)\r
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)\r
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)\r
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)\r
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)\r
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)\r
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)\r
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)\r
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)\r
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)\r
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)\r
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)\r
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)\r
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)\r
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)\r
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)\r
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)\r
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)\r
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)\r
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)\r
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)\r
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)\r
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)\r
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)\r
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)\r
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)\r
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)\r
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)\r
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)\r
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)\r
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)\r
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)\r
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)\r
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)\r
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)\r
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)\r
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)\r
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)\r
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)\r
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)\r
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)\r
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)\r
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)\r
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)\r
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)\r
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)\r
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)\r
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)\r
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)\r
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)\r
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)\r
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)\r
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)\r
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)\r
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)\r
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)\r
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)\r
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)\r
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)\r
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)\r
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)\r
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)\r
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)\r
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)\r
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)\r
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)\r
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)\r
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)\r
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)\r
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)\r
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)\r
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)\r
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)\r
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)\r
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)\r
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)\r
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)\r
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)\r
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)\r
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)\r
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)\r
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)\r
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)\r
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)\r
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)\r
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)\r
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)\r
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)\r
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)\r
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)\r
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)\r
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)\r
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)\r
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)\r
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)\r
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)\r
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)\r
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)\r
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)\r
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)\r
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)\r
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)\r
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)\r
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)\r
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)\r
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)\r
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)\r
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)\r
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)\r
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)\r
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)\r
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)\r
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)\r
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)\r
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)\r
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)\r
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)\r
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)\r
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)\r
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)\r
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)\r
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)\r
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)\r
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)\r
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)\r
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)\r
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)\r
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)\r
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)\r
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)\r
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)\r
+\r
+/** @} */\r
+\r
+#endif /* _MREPEAT_H_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor utils.\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _PREPROCESSOR_H_\r
+#define _PREPROCESSOR_H_\r
+\r
+#include "tpaste.h"\r
+#include "stringz.h"\r
+#include "mrepeat.h"\r
+\r
+#endif // _PREPROCESSOR_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor stringizing utils.\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _STRINGZ_H_\r
+#define _STRINGZ_H_\r
+\r
+/**\r
+ * \defgroup group_sam0_utils_stringz Preprocessor - Stringize\r
+ *\r
+ * \ingroup group_sam0_utils\r
+ *\r
+ * @{\r
+ */\r
+\r
+/** \brief Stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the token passed as an argument if the\r
+ * token is \#defined.\r
+ *\r
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to\r
+ * writing "A0".\r
+ */\r
+#define STRINGZ(x) #x\r
+\r
+/** \brief Absolute stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the token is \#defined.\r
+ *\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is\r
+ * equivalent to writing "A0".\r
+ */\r
+#define ASTRINGZ(x) STRINGZ(x)\r
+\r
+/** @} */\r
+\r
+#endif // _STRINGZ_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor token pasting utils.\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _TPASTE_H_\r
+#define _TPASTE_H_\r
+\r
+/**\r
+ * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste\r
+ *\r
+ * \ingroup group_sam0_utils\r
+ *\r
+ * @{\r
+ */\r
+\r
+/** \name Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.\r
+ *\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is\r
+ * equivalent to writing U32.\r
+ *\r
+ * @{ */\r
+#define TPASTE2( a, b) a##b\r
+#define TPASTE3( a, b, c) a##b##c\r
+#define TPASTE4( a, b, c, d) a##b##c##d\r
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e\r
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f\r
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g\r
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h\r
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i\r
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j\r
+/** @} */\r
+\r
+/** \name Absolute Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the tokens are \#defined.\r
+ *\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined\r
+ * as 32 is equivalent to writing U32.\r
+ *\r
+ * @{ */\r
+#define ATPASTE2( a, b) TPASTE2( a, b)\r
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)\r
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)\r
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)\r
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)\r
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)\r
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)\r
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)\r
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+#endif // _TPASTE_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Status code definitions.\r
+ *\r
+ * This file defines various status codes returned by functions,\r
+ * indicating success or failure as well as what kind of failure.\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef STATUS_CODES_H_INCLUDED\r
+#define STATUS_CODES_H_INCLUDED\r
+\r
+#include <stdint.h>\r
+\r
+/**\r
+ * \defgroup group_sam0_utils_status_codes Status Codes\r
+ *\r
+ * \ingroup group_sam0_utils\r
+ *\r
+ * @{\r
+ */\r
+\r
+/** Mask to retrieve the error category of a status code. */\r
+#define STATUS_CATEGORY_MASK 0xF0\r
+\r
+/** Mask to retrieve the error code within the category of a status code. */\r
+#define STATUS_ERROR_MASK 0x0F\r
+\r
+/** Status code error categories. */\r
+enum status_categories {\r
+ STATUS_CATEGORY_OK = 0x00,\r
+ STATUS_CATEGORY_COMMON = 0x10,\r
+ STATUS_CATEGORY_ANALOG = 0x30,\r
+ STATUS_CATEGORY_COM = 0x40,\r
+ STATUS_CATEGORY_IO = 0x50,\r
+};\r
+\r
+/**\r
+ * Status code that may be returned by shell commands and protocol\r
+ * implementations.\r
+ *\r
+ * \note Any change to these status codes and the corresponding\r
+ * message strings is strictly forbidden. New codes can be added,\r
+ * however, but make sure that any message string tables are updated\r
+ * at the same time.\r
+ */\r
+enum status_code {\r
+ STATUS_OK = STATUS_CATEGORY_OK | 0x00,\r
+ STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01,\r
+ STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02,\r
+ STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04,\r
+ STATUS_BUSY = STATUS_CATEGORY_OK | 0x05,\r
+\r
+ STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00,\r
+ STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01,\r
+ STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02,\r
+ STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03,\r
+ STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05,\r
+ STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06,\r
+ STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07,\r
+ STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08,\r
+ STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A,\r
+ STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B,\r
+ STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c,\r
+ STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d,\r
+ STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e,\r
+ STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f,\r
+\r
+ STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,\r
+ STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,\r
+\r
+ STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00,\r
+ STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01,\r
+ STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02,\r
+\r
+ STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00,\r
+};\r
+\r
+/** @} */\r
+\r
+#endif /* STATUS_CODES_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Syscalls for SAM0 (GCC).\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <stdio.h>\r
+#include <stdarg.h>\r
+#include <sys/types.h>\r
+#include <sys/stat.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#undef errno\r
+extern int errno;\r
+extern int _end;\r
+\r
+extern caddr_t _sbrk(int incr);\r
+extern int link(char *old, char *new);\r
+extern int _close(int file);\r
+extern int _fstat(int file, struct stat *st);\r
+extern int _isatty(int file);\r
+extern int _lseek(int file, int ptr, int dir);\r
+extern void _exit(int status);\r
+extern void _kill(int pid, int sig);\r
+extern int _getpid(void);\r
+\r
+extern caddr_t _sbrk(int incr)\r
+{\r
+ static unsigned char *heap = NULL;\r
+ unsigned char *prev_heap;\r
+\r
+ if (heap == NULL) {\r
+ heap = (unsigned char *)&_end;\r
+ }\r
+ prev_heap = heap;\r
+\r
+ heap += incr;\r
+\r
+ return (caddr_t) prev_heap;\r
+}\r
+\r
+extern int link(char *old, char *new)\r
+{\r
+ return -1;\r
+}\r
+\r
+extern int _close(int file)\r
+{\r
+ return -1;\r
+}\r
+\r
+extern int _fstat(int file, struct stat *st)\r
+{\r
+ st->st_mode = S_IFCHR;\r
+\r
+ return 0;\r
+}\r
+\r
+extern int _isatty(int file)\r
+{\r
+ return 1;\r
+}\r
+\r
+extern int _lseek(int file, int ptr, int dir)\r
+{\r
+ return 0;\r
+}\r
+\r
+extern void _exit(int status)\r
+{\r
+ printf("Exiting with status %d.\n", status);\r
+\r
+ for (;;);\r
+}\r
+\r
+extern void _kill(int pid, int sig)\r
+{\r
+ return;\r
+}\r
+\r
+extern int _getpid(void)\r
+{\r
+ return -1;\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * $Date: 15. July 2011\r
+ * $Revision: V1.0.10\r
+ *\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_math.h\r
+ *\r
+ * Description: Public header file for CMSIS DSP Library\r
+ *\r
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\r
+ *\r
+ * Version 1.0.10 2011/7/15\r
+ * Big Endian support added and Merged M0 and M3/M4 Source code.\r
+ *\r
+ * Version 1.0.3 2010/11/29\r
+ * Re-organized the CMSIS folders and updated documentation.\r
+ *\r
+ * Version 1.0.2 2010/11/11\r
+ * Documentation updated.\r
+ *\r
+ * Version 1.0.1 2010/10/05\r
+ * Production release and review comments incorporated.\r
+ *\r
+ * Version 1.0.0 2010/09/20\r
+ * Production release and review comments incorporated.\r
+ * -------------------------------------------------------------------- */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * <b>Introduction</b>\r
+ *\r
+ * This user manual describes the CMSIS DSP software library,\r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of modules each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transforms\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values.\r
+ *\r
+ * <b>Processor Support</b>\r
+ *\r
+ * The library is completely written in C and is fully CMSIS compliant.\r
+ * High performance is achieved through maximum use of Cortex-M4 intrinsics.\r
+ *\r
+ * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,\r
+ * with the DSP intrinsics being emulated through software.\r
+ *\r
+ *\r
+ * <b>Toolchain Support</b>\r
+ *\r
+ * The library has been developed and tested with MDK-ARM version 4.21.\r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * <b>Using the Library</b>\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)\r
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
+ * public header file <code>arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or\r
+ * ARM_MATH_CM0 depending on the target processor in the application.\r
+ *\r
+ * <b>Examples</b>\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * <b>Building the Library</b>\r
+ *\r
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
+ * - arm_cortexM0b_math.uvproj\r
+ * - arm_cortexM0l_math.uvproj\r
+ * - arm_cortexM3b_math.uvproj\r
+ * - arm_cortexM3l_math.uvproj\r
+ * - arm_cortexM4b_math.uvproj\r
+ * - arm_cortexM4l_math.uvproj\r
+ * - arm_cortexM4bf_math.uvproj\r
+ * - arm_cortexM4lf_math.uvproj\r
+ *\r
+ * Each library project have differant pre-processor macros.\r
+ *\r
+ * <b>ARM_MATH_CMx:</b>\r
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.\r
+ *\r
+ * <b>ARM_MATH_BIG_ENDIAN:</b>\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * <b>ARM_MATH_MATRIX_CHECK:</b>\r
+ * Define macro for checking on the input and output sizes of matrices\r
+ *\r
+ * <b>ARM_MATH_ROUNDING:</b>\r
+ * Define macro for rounding on support functions\r
+ *\r
+ * <b>__FPU_PRESENT:</b>\r
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\r
+ *\r
+ *\r
+ * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.\r
+ *\r
+ * <b>Copyright Notice</b>\r
+ *\r
+ * Copyright (C) 2010 ARM Limited. All rights reserved.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the \#define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
+\r
+#if defined (ARM_MATH_CM4)\r
+ #include "core_cm4.h"\r
+#elif defined (ARM_MATH_CM3)\r
+ #include "core_cm3.h"\r
+#elif defined (ARM_MATH_CM0)\r
+ #include "core_cm0.h"\r
+#else\r
+#include "ARMCM4.h"\r
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."\r
+#endif\r
+\r
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
+#include "string.h"\r
+ #include "math.h"\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#define PI 3.14159265358979f\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define TABLE_SIZE 256\r
+#define TABLE_SPACING_Q31 0x800000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+ /**\r
+ * @brief definition to read/write two 16 bit values.\r
+ */\r
+#define __SIMD32(addr) (*(int32_t **) & (addr))\r
+\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ __STATIC_INLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ __STATIC_INLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ __STATIC_INLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ __STATIC_INLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+\r
+ __STATIC_INLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y)));\r
+ }\r
+\r
+\r
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )\r
+#define __CLZ __clz\r
+#endif\r
+\r
+#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )\r
+/* No need to redefine __CLZ */\r
+#endif\r
+\r
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )\r
+\r
+ __STATIC_INLINE uint32_t __CLZ(q31_t data);\r
+\r
+\r
+ __STATIC_INLINE uint32_t __CLZ(q31_t data)\r
+ {\r
+ uint32_t count = 0;\r
+ uint32_t mask = 0x80000000;\r
+\r
+ while((data & mask) == 0)\r
+ {\r
+ count += 1u;\r
+ mask = mask >> 1u;\r
+ }\r
+\r
+ return(count);\r
+\r
+ }\r
+\r
+#endif\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.\r
+ */\r
+\r
+ __STATIC_INLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ q31_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out, tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 1;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 1;\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t) (in >> 24u);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0u; i < 2u; i++)\r
+ {\r
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);\r
+ tempVal = 0x7FFFFFFF - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);\r
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.\r
+ */\r
+ __STATIC_INLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ q15_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out = 0, tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 17;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 17;\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = in >> 8;\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0; i < 2; i++)\r
+ {\r
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFF - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinisic function for only M0 processors\r
+ */\r
+#if defined(ARM_MATH_CM0)\r
+\r
+ __STATIC_INLINE q31_t __SSAT(\r
+ q31_t x,\r
+ uint32_t y)\r
+ {\r
+ int32_t posMax, negMin;\r
+ uint32_t i;\r
+\r
+ posMax = 1;\r
+ for (i = 0; i < (y - 1); i++)\r
+ {\r
+ posMax = posMax * 2;\r
+ }\r
+\r
+ if(x > 0)\r
+ {\r
+ posMax = (posMax - 1);\r
+\r
+ if(x > posMax)\r
+ {\r
+ x = posMax;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ negMin = -posMax;\r
+\r
+ if(x < negMin)\r
+ {\r
+ x = negMin;\r
+ }\r
+ }\r
+ return (x);\r
+\r
+\r
+ }\r
+\r
+#endif /* end of ARM_MATH_CM0 */\r
+\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinsic function for M3 and M0 processors\r
+ */\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QADD8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q7_t r, s, t, u;\r
+\r
+ r = (char) x;\r
+ s = (char) y;\r
+\r
+ r = __SSAT((q31_t) (r + s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);\r
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);\r
+\r
+ sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |\r
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QSUB8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s, t, u;\r
+\r
+ r = (char) x;\r
+ s = (char) y;\r
+\r
+ r = __SSAT((r - s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;\r
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;\r
+\r
+ sum =\r
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = __SSAT(r + s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SHADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) + (s >> 1));\r
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = __SSAT(r - s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SHSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t diff;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) - (s >> 1));\r
+ s = (((x >> 17) - (y >> 17)) << 16);\r
+\r
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return diff;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QASX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHASX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SHASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) - (y >> 17));\r
+ s = (((x >> 17) + (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SHSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) + (y >> 17));\r
+ s = (((x >> 17) - (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMUSDX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t)(((short) x * (short) (y >> 16)) -\r
+ ((short) (x >> 16) * (short) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMUADX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t)(((short) x * (short) (y >> 16)) +\r
+ ((short) (x >> 16) * (short) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QADD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x + y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QSUB(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x - y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMLAD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r
+ ((short) x * (short) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMLADX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y)) +\r
+ ((short) x * (short) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMLSDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum - ((short) (x >> 16) * (short) (y)) +\r
+ ((short) x * (short) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q63_t __SMLALD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r
+ ((short) x * (short) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q63_t __SMLALDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) y)) +\r
+ ((short) x * (short) (y >> 16));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMUAD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMUSD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (-((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+\r
+\r
+\r
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ * @return none\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>numTaps</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+\r
+\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q31;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @param[in] *pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t *pData);\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t *pData);\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t *pData);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ #ifdef ARM_MATH_CM0\r
+ q15_t A1;\r
+ q15_t A2;\r
+ #else\r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+ #endif\r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] *S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @return none\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the q15 PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues; /**< nValues */\r
+ float32_t x1; /**< x1 */\r
+ float32_t xSpacing; /**< xSpacing */\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+\r
+\r
+ /*----------------------------------------------------------------------\r
+ * Internal functions prototypes FFT function\r
+ ----------------------------------------------------------------------*/\r
+\r
+ /**\r
+ * @brief Core function for the floating-point CFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to the twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_f32(\r
+ float32_t * pSrc,\r
+ uint16_t fftLen,\r
+ float32_t * pCoef,\r
+ uint16_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the floating-point CIFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @param[in] onebyfftLen value of 1/fftLen.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_inverse_f32(\r
+ float32_t * pSrc,\r
+ uint16_t fftLen,\r
+ float32_t * pCoef,\r
+ uint16_t twidCoefModifier,\r
+ float32_t onebyfftLen);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftSize length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.\r
+ * @param[in] *pBitRevTab points to the bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_f32(\r
+ float32_t *pSrc,\r
+ uint16_t fftSize,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Core function for the Q31 CFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_q31(\r
+ q31_t *pSrc,\r
+ uint32_t fftLen,\r
+ q31_t *pCoef,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the Q31 CIFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_inverse_q31(\r
+ q31_t * pSrc,\r
+ uint32_t fftLen,\r
+ q31_t * pCoef,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r
+ * @param[in] *pBitRevTab points to bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_q31(\r
+ q31_t * pSrc,\r
+ uint32_t fftLen,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Core function for the Q15 CFFT butterfly process.\r
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_q15(\r
+ q15_t *pSrc16,\r
+ uint32_t fftLen,\r
+ q15_t *pCoef16,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the Q15 CIFFT butterfly process.\r
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_inverse_q15(\r
+ q15_t *pSrc16,\r
+ uint32_t fftLen,\r
+ q15_t *pCoef16,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r
+ * @param[in] *pBitRevTab points to bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_q15(\r
+ q15_t * pSrc,\r
+ uint32_t fftLen,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 RFFT/RIFFT.\r
+ * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 RFFT/RIFFT.\r
+ * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.\r
+ * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point RFFT/RIFFT.\r
+ * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.\r
+ * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_f32(\r
+ float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q7(\r
+ q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q15(\r
+ q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q31(\r
+ q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q7(\r
+ q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q15(\r
+ q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q31(\r
+ q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_f32(\r
+ float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q7(\r
+ q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q15(\r
+ q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q31(\r
+ q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+/**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR decimator.\r
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR decimator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the filter data structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t *pkCoeffs,\r
+ float32_t *pvCoeffs,\r
+ float32_t *pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t *pkCoeffs,\r
+ q31_t *pvCoeffs,\r
+ q31_t *pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t *pkCoeffs,\r
+ q15_t *pvCoeffs,\r
+ q15_t *pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+\r
+ } arm_lms_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t *pCoeffs,\r
+ q31_t *pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t *pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /*\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees\r
+ * @param[out] *pSinVal points to the processed sine output.\r
+ * @param[out] *pCosVal points to the processed cos output.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t *pSinVal,\r
+ float32_t *pCcosVal);\r
+\r
+ /*\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees\r
+ * @param[out] *pSinVal points to the processed sine output.\r
+ * @param[out] *pCosVal points to the processed cosine output.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t *pSinVal,\r
+ q31_t *pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ *\r
+ * \par\r
+ * \image html PID.gif "Proportional Integral Derivative Controller"\r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs.\r
+ * The proportional value determines the reaction to the current error,\r
+ * the integral value determines the reaction based on the sum of recent errors,\r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure\r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
+ * A separate instance structure must be defined for each PID Controller.\r
+ * There are separate instance structure declarations for each of the 3 supported data types.\r
+ *\r
+ * \par Reset Functions\r
+ * There is also an associated reset function for each data type which clears the state array.\r
+ *\r
+ * \par Initialization Functions\r
+ * There is also an associated initialization function for each data type.\r
+ * The initialization function performs the following operations:\r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer.\r
+ *\r
+ * \par\r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
+ *\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 64-bit accumulator.\r
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
+ * Thus, if the accumulator result overflows it wraps around rather than clip.\r
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
+ */\r
+\r
+ __STATIC_INLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31u);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using a 64-bit internal accumulator.\r
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+\r
+ __STATIC_INLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+ /* Implementation of PID controller */\r
+\r
+ #ifdef ARM_MATH_CM0\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0 )* in ;\r
+\r
+ #else\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD(S->A0, in);\r
+\r
+ #endif\r
+\r
+ #ifdef ARM_MATH_CM0\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0] ;\r
+ acc += (q31_t) S->A2 * S->state[1] ;\r
+\r
+ #else\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);\r
+\r
+ #endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] *src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Clarke transform for Q31 version\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q31(\r
+ q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Inverse Clarke transform for Q31 version\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q15(\r
+ q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
+ * from the stationary to the moving reference frame and control the spatial relationship between\r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+\r
+ __STATIC_INLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Park transform for Q31 version\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_float(\r
+ q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Park transform for Q31 version\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_float(\r
+ q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par\r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ *\r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
+ * if x is below input range and returns last value of table if x is above range.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+\r
+ __STATIC_INLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (x - S->x1) / xSpacing;\r
+\r
+ if(i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if(i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues-1];\r
+ }\r
+ else\r
+ {\r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i +1) * xSpacing;\r
+\r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+\r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));\r
+\r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ __STATIC_INLINE q31_t arm_linear_interp_q31(q31_t *pYData,\r
+ q31_t x, uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20);\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+\r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+\r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+\r
+ /* Convert y to 1.31 format */\r
+ return (y << 1u);\r
+\r
+ }\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ __STATIC_INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u);\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+\r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+\r
+ /* convert y to 1.15 format */\r
+ return (y >> 20);\r
+ }\r
+\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u);\r
+\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+\r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+\r
+ /* convert y to 1.7(q7) format */\r
+ return (y >> 20u);\r
+\r
+ }\r
+\r
+ }\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types.\r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point square root function.\r
+ * @param[in] in input value.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+\r
+ __STATIC_INLINE arm_status arm_sqrt_f32(\r
+ float32_t in, float32_t *pOut)\r
+ {\r
+ if(in > 0)\r
+ {\r
+\r
+// #if __FPU_USED\r
+ #if (__FPU_USED == 1) && defined ( __CC_ARM )\r
+ *pOut = __sqrtf(in);\r
+ #elif (__FPU_USED == 1) && defined ( __TMS_740 )\r
+ *pOut = __builtin_sqrtf(in);\r
+ #else\r
+ *pOut = sqrtf(in);\r
+ #endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q31(\r
+ q31_t in, q31_t *pOut);\r
+\r
+ /**\r
+ * @brief Q15 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q15(\r
+ q15_t in, q15_t *pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ __STATIC_INLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (int32_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ __STATIC_INLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q15_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ __STATIC_INLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q7_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mean_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q15(\r
+ q15_t * pSrcCmplx,\r
+ q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q31(\r
+ q31_t * pSrcCmplx,\r
+ q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_f32(\r
+ float32_t * pSrcCmplx,\r
+ float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+ void arm_min_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none.\r
+ */\r
+ void arm_float_to_q31(\r
+ float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none\r
+ */\r
+ void arm_float_to_q15(\r
+ float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none\r
+ */\r
+ void arm_float_to_q7(\r
+ float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q15(\r
+ q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q7(\r
+ q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_float(\r
+ q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q31(\r
+ q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q7(\r
+ q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components.\r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex-1) * S->numCols ;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex-1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ __STATIC_INLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20u);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20u);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return (acc << 2u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ __STATIC_INLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return (acc >> 36);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ __STATIC_INLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return (acc >> 40);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0plus.h\r
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
+ * @version V3.01\r
+ * @date 22. March 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM0PLUS_H_GENERIC\r
+#define __CORE_CM0PLUS_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex-M0+\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0P definitions */\r
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM0PLUS_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
+#define __CORE_CM0PLUS_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0PLUS_REV\r
+ #define __CM0PLUS_REV 0x0000\r
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex-M0+ */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if (__VTOR_PRESENT == 1)\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if (__VTOR_PRESENT == 1)\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0+ Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */\r
+ else {\r
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V3.00\r
+ * @date 19. January 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+ \r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V3.00\r
+ * @date 07. February 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+\r
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );\r
+ return(op1);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+* -------------------------------------------------------------------\r
+* Copyright (C) 2011 ARM Limited. All rights reserved. \r
+* \r
+* Date: 11 October 2011 \r
+* Revision: V3.00 \r
+* \r
+* Project: Cortex Microcontroller Software Interface Standard (CMSIS)\r
+* Title: Release Note for CMSIS\r
+*\r
+* -------------------------------------------------------------------\r
+\r
+\r
+NOTE - Open the index.html file to access CMSIS documentation\r
+\r
+\r
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all \r
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects \r
+and reduces time-to-market for new embedded applications.\r
+\r
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").\r
+Any user of the software package is bound to the terms and conditions of the end user license agreement.\r
+\r
+\r
+You will find the following sub-directories:\r
+\r
+Documentation - Contains CMSIS documentation.\r
+ \r
+DSP_Lib - MDK project files, Examples and source files etc.. to build the \r
+ CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.\r
+\r
+Include - CMSIS Core Support and CMSIS DSP Include Files.\r
+\r
+Lib - CMSIS DSP Libraries.\r
+\r
+RTOS - CMSIS RTOS API template header file.\r
+\r
+SVD - CMSIS SVD Schema files and Conversion Utility.\r
--- /dev/null
+END USER LICENCE AGREEMENT FOR THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE\r
+STANDARD (CMSIS) SPECIFICATION AND SOFTWARE\r
+\r
+THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A\r
+SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE\r
+CMSIS SPECIFICATION, EXAMPLE CODE, DSP LIBRARY SPECIFICATION AND DSP LIBRARY\r
+IMPLEMENTATION AS SUCH TERMS ARE DEFINED BELOW (COLLECTIVELY, THE "ARM\r
+DELIVERABLES"). ARM IS ONLY WILLING TO LICENSE THE ARM DELIVERABLES TO YOU ON CONDITION\r
+THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING\r
+OR OTHERWISE USING OR COPYING THE ARM DELIVERABLES YOU INDICATE THAT YOU AGREE TO\r
+BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS\r
+LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE THE ARM DELIVERABLES AND YOU MAY NOT\r
+INSTALL, USE OR COPY THE ARM DELIVERABLES.\r
+\r
+"CMSIS Specification" means any documentation and C programming language files defining the application\r
+programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface\r
+Standard (CMSIS) as well as the System View Description (SVD) documentation and associated XML schema\r
+file. Notwithstanding the foregoing, "CMSIS Specification" shall not include (i) the implementation of other\r
+published specifications referenced in the CMSIS Specification; (ii) any enabling technologies that may be\r
+necessary to make or use any product or portion thereof that complies with the CMSIS Specification, but are not\r
+themselves expressly set forth in the CMSIS Specification (e.g. compiler front ends, code generators, back ends,\r
+libraries or other compiler, assembler or linker technologies; validation or debug software or hardware;\r
+applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii)\r
+maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of\r
+integrated circuit designs.\r
+\r
+"DSP Library Implementation" means any C programming language source code implementing the functionality\r
+of the digital signal processor (DSP) algorithms and the application programming interface as defined in the DSP\r
+Library Specification. The DSP Library Implementation makes use of CMSIS application programming interface\r
+and therefore is targeted at Cortex-M class processors.\r
+\r
+"DSP Library Specification" means the DSP library documentation and C programming language file defining the\r
+application programming interface of the DSP Library Implementation. Notwithstanding the foregoing, "DSP\r
+Library Specification" shall not include (i) the implementation of other published specifications referenced in the\r
+DSP Library Specification; (ii) any enabling technologies that may be necessary to make or use any product or\r
+portion thereof that complies with the DSP Library Specification, but are not themselves expressly set forth in the\r
+DSP Library Specification (e.g. compiler front ends, code generators, back ends, libraries or other compiler,\r
+assembler or linker technologies; validation or debug software or hardware; applications, operating system or\r
+driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of\r
+integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.\r
+\r
+"Example Code" means any files in C, C++ or ARM assembly programming languages, associated project and\r
+configuration files that demonstrate the usage of the CMSIS Specification, the DSP Library Specification and the\r
+DSP Library Implementation, for microprocessors or device specific software applications that are for use with\r
+microprocessors.\r
+\r
+1. LICENCE GRANTS.\r
+\r
+1.1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, nontransferable\r
+licence, to;\r
+\r
+(i) use and copy the CMSIS Specification for the purpose of developing, having developed, manufacturing,\r
+having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the\r
+CMSIS Specification, provided that you preserve any copyright notices which are included with, or in, the CMSIS\r
+Specification and provided that you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(ii) use, copy, and modify (solely to the extent necessary to incorporate the whole or any part of the DSP Library\r
+Specification into your documentation), the DSP Library Specification, for the purpose of developing, having\r
+developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing\r
+products that comply with the DSP Library Specification, and distribute and have distributed any documentation\r
+created by or for you that has been derived from the DSP Library Specification with such products, provided that\r
+you preserve any copyright notices which are included with, or in, the DSP Library Specification and provided that\r
+you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(iii) use, copy, modify and sublicense the Example Code solely for the purpose of developing, having developed,\r
+manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that\r
+comply with either or both the CMSIS Specification and the DSP Library Specification, provided that you preserve\r
+any copyright notices which are included with, or in, the Example Code and that you do not use ARM's name,\r
+logo or trademarks to market such products;\r
+\r
+(iv) use, copy and modify (provided that the logical functionality and the application programming interface of the\r
+DSP Library Implementation are maintained) the DSP Library Implementation, solely for the purposes of\r
+developing; (a) software applications for use with microprocessors manufactured or simulated under licence from\r
+ARM ("Software Applications"); and (b) tools that are designed to develop software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM ("Tools"); and\r
+\r
+(v) subject to clause 1.1(vi) below; (a) distribute and sublicense the use of the DSP Library Implementation\r
+(including any modified forms thereof created under Clause 1.1(iv) above) in binary or source format, solely as\r
+incorporated into Software Library Applications and Tools to third parties; and (b) sublicense to such third parties\r
+the right to use and copy the Tools for the purposes of developing and distribute software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM.\r
+\r
+(vi) CONDITIONS ON REDISTRIBUTION: If you choose to redistribute the whole or any part of the DSP Library\r
+Implementation as incorporated into Software Library Applications or Tools, you agree to; (a) ensure that the\r
+DSP Library Implementation is licensed for use only as part of Software Library Applications and Tools and only\r
+for use with microprocessors manufactured or simulated under licence from ARM; (b) not to use ARM's name,\r
+logo or trademarks to market Software Applications and Tools; and (c) include valid copyright notices on\r
+Software Applications and Tools, and preserve any copyright notices which are included with, or in, the DSP\r
+Library Implementation.\r
+\r
+2. RESTRICTIONS ON USE OF THE ARM DELIVERABLES.\r
+\r
+PERMITTED USERS: The ARM Deliverables shall be used only by you (either a single individual, or single legal\r
+entity) your employees, or by your on-site bona fide sub-contractors for whose acts and omissions you hereby\r
+agree to be responsible to ARM for to the same extent as you are for your employees, and provided always that\r
+such sub-contractors; (i) are contractually obligated to use the ARM Deliverables only for your benefit, and (ii)\r
+agree to assign all their work product and any rights they create therein in the supply of such work to you.\r
+COPYRIGHT AND RESERVATION OF RIGHTS: The ARM Deliverables are owned by ARM or its licensors and\r
+are protected by copyright and other intellectual property laws and international treaties. The ARM Deliverables\r
+are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the ARM\r
+Deliverables or any intellectual property therein. In no event shall the licences granted herein be construed as\r
+granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except\r
+the ARM Deliverables.\r
+\r
+3. SUPPORT.\r
+\r
+ARM is not obligated to support the ARM Deliverables but may do so entirely at ARM's discretion.\r
+\r
+4. NO WARRANTY\r
+\r
+YOU AGREE THAT THE ARM DELIVERABLES ARE LICENSED "AS IS", AND THAT ARM EXPRESSLY\r
+DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS,\r
+IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NONINFRINGEMENT,\r
+SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. THE ARM\r
+DELIVERABLES MAY CONTAIN ERRORS. ARM RESERVES THE RIGHT TO INCORPORATE\r
+MODIFICATIONS TO THE ARM DELIVERABLES IN LATER REVISIONS OF THEM, AND TO MAKE\r
+IMPROVEMENTS OR CHANGES IN THE ARM DELIVERABLES AT ANY TIME.\r
+\r
+5. LIMITATION OF LIABILITY.\r
+\r
+THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN\r
+CONTRACT, TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS\r
+LICENCE SHALL NOT EXCEED THE GREATER OF (I) THE TOTAL OF SUMS PAID BY YOU TO ARM (IF\r
+ANY) FOR THIS LICENCE AND (II) US$10.00. THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN\r
+THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.\r
+\r
+6. U.S. GOVERNMENT END USERS.\r
+US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this\r
+commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.\r
+\r
+7. TERM AND TERMINATION.\r
+\r
+7.1 This Licence shall remain in force until terminated in accordance with the terms of Clause 7.2 or Clause 7.3\r
+below.\r
+\r
+7.2 Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this\r
+Licence then ARM may terminate this Licence immediately upon giving written notice to you. You may terminate\r
+this Licence at any time.\r
+\r
+7.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you\r
+asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the ARM\r
+Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate)\r
+patent is Necessary to implement the CMSIS Specification or DSP Library Specification. In this Licence; (i)\r
+"affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via\r
+voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert"\r
+means to allege infringement in legal or administrative proceedings, or proceedings before any other competent\r
+trade, arbitral or international authority; (iii) "Necessary" means with respect to any claims of any patent, those\r
+claims which, without the appropriate permission of the patent owner, will be infringed when implementing the\r
+CMSIS Specification or DSP Library Specification because no alternative, commercially reasonable, noninfringing\r
+way of implementing the CMSIS Specification or DSP Library Specification is known.\r
+\r
+7.4 Upon termination of this Licence, you shall stop using the ARM Deliverables and destroy all copies of the\r
+ARM Deliverables in your possession. The provisions of clauses 5, 6, 7, and 8 shall survive termination of this\r
+Licence.\r
+\r
+8. GENERAL.\r
+\r
+This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by\r
+you and ARM, this is the only agreement between you and ARM relating to the ARM Deliverables and it may only\r
+be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence\r
+may not be modified by purchase orders, advertising or other representation by any person. If any clause or\r
+sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this\r
+Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless\r
+waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of\r
+this Licence in the future. This Licence may not be assigned without the prior written consent of ARM.\r
+\r
+ARM contract reference LEC-PRE-00489\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Autogenerated API include file for the Atmel Software Framework (ASF)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ASF_H\r
+#define ASF_H\r
+\r
+/*\r
+ * This file includes all API header files for the selected drivers from ASF.\r
+ * Note: There might be duplicate includes required by more than one driver.\r
+ *\r
+ * The file is automatically generated and will be re-written when\r
+ * running the ASF driver selector tool. Any changes will be discarded.\r
+ */\r
+\r
+// From module: Common SAM D20 compiler driver\r
+#include <compiler.h>\r
+#include <status_codes.h>\r
+\r
+// From module: Generic board support\r
+#include <board.h>\r
+\r
+// From module: Interrupt management - SAM implementation\r
+#include <interrupt.h>\r
+\r
+// From module: PORT - GPIO Pin Control\r
+#include <port.h>\r
+\r
+// From module: Part identification macros\r
+#include <parts.h>\r
+\r
+// From module: SERCOM\r
+#include <sercom.h>\r
+#include <sercom_interrupt.h>\r
+\r
+// From module: SERCOM USART - Serial Communications (Callback APIs)\r
+#include <usart.h>\r
+#include <usart_interrupt.h>\r
+\r
+// From module: SYSTEM - Clock Management\r
+#include <clock.h>\r
+#include <gclk.h>\r
+\r
+// From module: SYSTEM - Core System Driver\r
+#include <system.h>\r
+\r
+// From module: SYSTEM - I/O Pin Multiplexer\r
+#include <pinmux.h>\r
+\r
+// From module: SYSTEM - Interrupt Driver\r
+#include <system_interrupt.h>\r
+\r
+// From module: USART - Serial interface- SAM implementation for devices with only USART\r
+#include <serial.h>\r
+\r
+#endif // ASF_H\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+extern uint32_t SystemCoreClock;\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 500 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 11000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 5 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configUSE_QUEUE_SETS 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( 80 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_eTaskGetState 1\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names - or at least those used in the unmodified vector table. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* The size of the global output buffer that is available for use when there\r
+are multiple command interpreters running at once (for example, one on a UART\r
+and one on TCP/IP). This is done to prevent an output buffer being defined by\r
+each implementation - which would waste RAM. In this case, there is only one\r
+command interpreter running. */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAMD20 Xplained PRO board configuration.\r
+ *\r
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_BOARD_H_INCLUDED\r
+#define CONF_BOARD_H_INCLUDED\r
+\r
+#endif /* CONF_BOARD_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM D20 Clock configuration\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include <clock.h>\r
+\r
+#ifndef CONF_CLOCKS_H_INCLUDED\r
+# define CONF_CLOCKS_H_INCLUDED\r
+\r
+/* System clock bus configuration */\r
+# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT true\r
+# define CONF_CLOCK_FLASH_WAIT_STATES 0\r
+# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1\r
+# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1\r
+# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1\r
+\r
+\r
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */\r
+# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1\r
+# define CONF_CLOCK_OSC8M_ON_DEMAND true\r
+# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false\r
+\r
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */\r
+# define CONF_CLOCK_XOSC_ENABLE false\r
+# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL\r
+# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL\r
+# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768\r
+# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true\r
+# define CONF_CLOCK_XOSC_ON_DEMAND true\r
+# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false\r
+\r
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */\r
+# define CONF_CLOCK_XOSC32K_ENABLE false\r
+# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL\r
+# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536\r
+# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL true\r
+# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false\r
+# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true\r
+# define CONF_CLOCK_XOSC32K_ON_DEMAND true\r
+# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false\r
+\r
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */\r
+# define CONF_CLOCK_OSC32K_ENABLE false\r
+# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_128\r
+# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true\r
+# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true\r
+# define CONF_CLOCK_OSC32K_ON_DEMAND true\r
+# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false\r
+\r
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */\r
+# define CONF_CLOCK_DFLL_ENABLE false\r
+# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN\r
+# define CONF_CLOCK_DFLL_ON_DEMAND false\r
+# define CONF_CLOCK_DFLL_RUN_IN_STANDBY false\r
+\r
+/* DFLL open loop mode configuration */\r
+# define CONF_CLOCK_DFLL_COARSE_VALUE (0x1f / 4)\r
+# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4)\r
+\r
+/* DFLL closed loop mode configuration */\r
+# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1\r
+# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR 6\r
+# define CONF_CLOCK_DFLL_QUICK_LOCK true\r
+# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true\r
+# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true\r
+# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true\r
+# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4)\r
+# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4)\r
+\r
+\r
+/* Set this to true to configure the GCLK when running clocks_init. If set to\r
+ * false, none of the GCLK generators will be configured in clocks_init(). */\r
+# define CONF_CLOCK_CONFIGURE_GCLK true\r
+\r
+/* Configure GCLK generator 0 (Main Clock) */\r
+# define CONF_CLOCK_GCLK_0_ENABLE true\r
+# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false\r
+# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M\r
+# define CONF_CLOCK_GCLK_0_PRESCALER 1\r
+# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false\r
+\r
+/* Configure GCLK generator 1 */\r
+# define CONF_CLOCK_GCLK_1_ENABLE false\r
+# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false\r
+# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M\r
+# define CONF_CLOCK_GCLK_1_PRESCALER 1\r
+# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false\r
+\r
+/* Configure GCLK generator 2 (RTC) */\r
+# define CONF_CLOCK_GCLK_2_ENABLE false\r
+# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false\r
+# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K\r
+# define CONF_CLOCK_GCLK_2_PRESCALER 32\r
+# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false\r
+\r
+/* Configure GCLK generator 3 */\r
+# define CONF_CLOCK_GCLK_3_ENABLE false\r
+# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false\r
+# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M\r
+# define CONF_CLOCK_GCLK_3_PRESCALER 1\r
+# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false\r
+\r
+/* Configure GCLK generator 4 */\r
+# define CONF_CLOCK_GCLK_4_ENABLE false\r
+# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false\r
+# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M\r
+# define CONF_CLOCK_GCLK_4_PRESCALER 1\r
+# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false\r
+\r
+/* Configure GCLK generator 5 */\r
+# define CONF_CLOCK_GCLK_5_ENABLE false\r
+# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false\r
+# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M\r
+# define CONF_CLOCK_GCLK_5_PRESCALER 1\r
+# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false\r
+\r
+/* Configure GCLK generator 6 */\r
+# define CONF_CLOCK_GCLK_6_ENABLE false\r
+# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false\r
+# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M\r
+# define CONF_CLOCK_GCLK_6_PRESCALER 1\r
+# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false\r
+\r
+/* Configure GCLK generator 7 */\r
+# define CONF_CLOCK_GCLK_7_ENABLE false\r
+# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false\r
+# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M\r
+# define CONF_CLOCK_GCLK_7_PRESCALER 1\r
+# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false\r
+\r
+#endif /* CONF_CLOCKS_H_INCLUDED */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Library includes. */\r
+#include <asf.h>\r
+\r
+void usart_read_callback(const struct usart_module *const usart_module);\r
+void usart_write_callback(const struct usart_module *const usart_module);\r
+static void prvSetupHardware( void );\r
+void configure_usart(void);\r
+void configure_usart_callbacks(void);\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+struct usart_module usart_instance;\r
+#define MAX_RX_BUFFER_LENGTH 5\r
+volatile uint8_t rx_buffer[MAX_RX_BUFFER_LENGTH];\r
+#define NUM 1024\r
+char cChars[ NUM ] = { 0 };\r
+\r
+void usart_read_callback(const struct usart_module *const usart_module)\r
+{\r
+ usart_write_buffer_job(&usart_instance, (uint8_t *)rx_buffer, MAX_RX_BUFFER_LENGTH);\r
+}\r
+\r
+void usart_write_callback(const struct usart_module *const usart_module)\r
+{\r
+ port_pin_toggle_output_level(LED_0_PIN);\r
+}\r
+\r
+void configure_usart(void)\r
+{\r
+ struct usart_config config_usart;\r
+ usart_get_config_defaults(&config_usart);\r
+ config_usart.baudrate = 115200;\r
+ config_usart.mux_setting = EDBG_CDC_SERCOM_MUX_SETTING;\r
+ config_usart.pinmux_pad0 = EDBG_CDC_SERCOM_PINMUX_PAD0;\r
+ config_usart.pinmux_pad1 = EDBG_CDC_SERCOM_PINMUX_PAD1;\r
+ config_usart.pinmux_pad2 = EDBG_CDC_SERCOM_PINMUX_PAD2;\r
+ config_usart.pinmux_pad3 = EDBG_CDC_SERCOM_PINMUX_PAD3;\r
+ while (usart_init(&usart_instance,\r
+ EDBG_CDC_MODULE, &config_usart) != STATUS_OK) {\r
+ }\r
+ usart_enable(&usart_instance);\r
+}\r
+\r
+void configure_usart_callbacks(void)\r
+{\r
+ usart_register_callback(&usart_instance,\r
+ usart_write_callback, USART_CALLBACK_BUFFER_TRANSMITTED);\r
+ usart_register_callback(&usart_instance,\r
+ usart_read_callback, USART_CALLBACK_BUFFER_RECEIVED);\r
+ usart_enable_callback(&usart_instance, USART_CALLBACK_BUFFER_TRANSMITTED);\r
+ usart_enable_callback(&usart_instance, USART_CALLBACK_BUFFER_RECEIVED);\r
+}\r
+\r
+\r
+\r
+\r
+int main (void)\r
+{\r
+ prvSetupHardware();\r
+\r
+ configure_usart();\r
+ configure_usart_callbacks();\r
+ system_interrupt_enable_global();\r
+\r
+ uint8_t string[] = "Hello World!\r\n";\r
+ usart_write_buffer_job(&usart_instance, string, sizeof(string));\r
+\r
+\r
+\r
+ while (true) {\r
+ usart_read_buffer_job(&usart_instance,\r
+ (uint8_t *)rx_buffer, MAX_RX_BUFFER_LENGTH);\r
+ }\r
+\r
+ while (1) {\r
+ if (port_pin_get_input_level(BUTTON_0_PIN) == BUTTON_0_ACTIVE) {\r
+ port_pin_set_output_level(LED_0_PIN, LED_0_ACTIVE);\r
+ } else {\r
+ port_pin_set_output_level(LED_0_PIN, !LED_0_ACTIVE);\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ system_init();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+\r
projects / freertos / commitdiff