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git.sur5r.net Git - freertos/log
rtel [Tue, 16 Sep 2014 12:24:14 +0000 (12:24 +0000)]
SAM4L tickless implementation: Bug fix and update the demo project to exercise the fix.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2305
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rtel [Fri, 12 Sep 2014 11:32:47 +0000 (11:32 +0000)]
Demo project only:
Add the new IntSem test/demo code into the MSVC demo project.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2304
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rtel [Thu, 11 Sep 2014 12:06:27 +0000 (12:06 +0000)]
Demo tasks only, with the aim of improving test coverage:
+ Split out the code that uses a mutex from an interrupt from GenQTest.c and add to new common demo task IntSemTest.c.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2303
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rtel [Tue, 2 Sep 2014 22:39:54 +0000 (22:39 +0000)]
Update version number to 8.1.2 after moving the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into individual port layers so it does not affect ports that do not support the definition.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2301
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rtel [Tue, 2 Sep 2014 16:06:57 +0000 (16:06 +0000)]
Demo code only:
Add the IntQ standard test to the SAM4S project.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2300
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rtel [Sat, 30 Aug 2014 20:18:18 +0000 (20:18 +0000)]
Correct potential compiler warning when configUSE_MUTEXES is set to 0.
Add comments.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2297
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rtel [Fri, 29 Aug 2014 19:14:23 +0000 (19:14 +0000)]
Update version number to 8.1.1 for patch release that re-enables mutexes to be given from an interrupt.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2295
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rtel [Fri, 29 Aug 2014 13:53:58 +0000 (13:53 +0000)]
Core kernel code:
- Re-introduce the ability to give a mutex from an ISR.
Common demo code:
- Add additional tests into the GenQTest files for priority inheritance and using a mutex from an ISR.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2294
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rtel [Tue, 26 Aug 2014 16:53:40 +0000 (16:53 +0000)]
Lower the minimum stack size used by the ATSAMA5 demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2292
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rtel [Tue, 26 Aug 2014 16:23:09 +0000 (16:23 +0000)]
Minor edits prior to tagging V8.1.0.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2291
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rtel [Sat, 16 Aug 2014 20:19:40 +0000 (20:19 +0000)]
***IMMINENT RELEASE NOTICE***
Update version numbers ready for FreeRTOS V8.1.0 release in about 10 days.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2290
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rtel [Sat, 16 Aug 2014 15:43:43 +0000 (15:43 +0000)]
Remove some irrelevant CyaSSL files.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2289
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rtel [Sat, 16 Aug 2014 14:29:39 +0000 (14:29 +0000)]
Demo application related:
+ Update the RZ IAR project so it targets the RZ RSK rather than custom hardware.
+ Update the RZ ARM/DS-5 project so it targets the RZ RSK rather than custom hardware.
+ Updated RX64M demos to use the new iodefine.h naming.
Cortex-A9 port related:
+ Update IAR, ARM and GCC Cortex-A9 port layers to include a 'task exit error' function which is called if a task attempts to incorrectly exit its implementing function.
+ Moved the instruction which switches into system mode out of the restore context macro, as it is only needed when starting the first task.
Core kernel files related:
+ Ensure there are no references to the mutexes held count when mutexes are excluded from the build.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2288
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rtel [Mon, 4 Aug 2014 07:57:18 +0000 (07:57 +0000)]
General maintenance - changing comments and correcting spellings only.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2287
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rtel [Mon, 4 Aug 2014 07:53:20 +0000 (07:53 +0000)]
Common demo tasks:
- Add additional tests to GenQTest.c to test the updated priority inheritance mechanism.
- Slightly increase some delays in recmutex.c to prevent it reporting false errors in high load test cases.
SAMA5D3 Xplained IAR demo:
- Remove space being allocated for stacks that are not used.
- Remove explicit enabling of interrupts in ISR handers as this is now done from the central ISR callback before the individual handers are invoked.
- Reduce both the allocated heap size and the stack allocated to each task.
- Enable I cache.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2286
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rtel [Sun, 3 Aug 2014 19:15:30 +0000 (19:15 +0000)]
Cortex-A5 IAR port:
- Removed SAMA5 specifics from the port layer, and instead call a generic ISR callback as per Cortex-A9 ports.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2285
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rtel [Sun, 3 Aug 2014 18:37:58 +0000 (18:37 +0000)]
Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2284
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rtel [Tue, 29 Jul 2014 21:31:04 +0000 (21:31 +0000)]
Continue working on the GIC-less Cortex-A5 port for IAR:
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2283
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rtel [Tue, 29 Jul 2014 21:28:22 +0000 (21:28 +0000)]
Carry on working on SAMA5D3 demo:
- Add full interrupt nesting tests.
- Add additional critical section/context switching tests.
- Set interrupt priorities so everything can run at once without any software watchdog errors.
- Re-enable interrupts in each IRQ handler.
- Add in run-time stats.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2282
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rtel [Wed, 23 Jul 2014 21:07:03 +0000 (21:07 +0000)]
SAMA5D3 demo: Add CDC driver code and use CDC to create a simple command console.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2281
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rtel [Fri, 18 Jul 2014 18:54:25 +0000 (18:54 +0000)]
Update CyaSSL to latest version.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2280
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rtel [Mon, 14 Jul 2014 14:01:07 +0000 (14:01 +0000)]
Re-test Zynq demo now it is using the latest tools.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2279
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rtel [Mon, 14 Jul 2014 13:00:18 +0000 (13:00 +0000)]
Add back Zynq demo - this time using SDK V14.2.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2278
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rtel [Mon, 14 Jul 2014 11:46:34 +0000 (11:46 +0000)]
Remove Zynq demo project ready to recreate the project using the 14.2 version of Xilinx's SDK.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2277
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rtel [Sat, 12 Jul 2014 20:40:33 +0000 (20:40 +0000)]
Add 'full' demo to the SAMA5 Xplained demo - but so far without interrupt nesting tests or CLI.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2276
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rtel [Sat, 12 Jul 2014 20:39:22 +0000 (20:39 +0000)]
Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specify the number of registers in the FPU unit.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2275
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rtel [Sat, 12 Jul 2014 19:25:18 +0000 (19:25 +0000)]
SAMA5D3 Xplained demo blinky running.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2274
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rtel [Sat, 12 Jul 2014 19:21:04 +0000 (19:21 +0000)]
Add new port layer for Cortex-A devices without the means to mask interrupt priorities.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2273
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rtel [Wed, 9 Jul 2014 21:19:01 +0000 (21:19 +0000)]
Start of SAMA5D3 XPlained demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2272
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rtel [Fri, 4 Jul 2014 13:17:21 +0000 (13:17 +0000)]
Make the parameters to vPortDefineHeapRegions() const.
Add additional asserts to the Keil CM3 and CM4F ports (other CM3/4 ports already updated).
Add the additional yield necessitated by the mutex held count to the case when configUSE_QUEUE_SETS is 0.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2271
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rtel [Thu, 3 Jul 2014 16:49:29 +0000 (16:49 +0000)]
Update the MSVC simulator demo to demonstrate heap_5 allocator and pdTICKS_TO_MS macro being used.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2270
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rtel [Thu, 3 Jul 2014 14:44:37 +0000 (14:44 +0000)]
Simply some of the alignment calculations in heap_4.c to match those used in heap_5.c.
Remove some apparently obsolete code from xTaskPriorityDisinherit() (a task cannot be both blocked and giving bac a mutex at the same time].
Update the new "mutex held count" increment and decrement functions to allow mutexes to be created before the scheduler is started.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2269
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rtel [Wed, 2 Jul 2014 10:20:35 +0000 (10:20 +0000)]
Check in the portable.h version required to use heap_5.c.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2268
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rtel [Wed, 2 Jul 2014 10:19:49 +0000 (10:19 +0000)]
Check in the new memory allocator that allows the heap to span multiple blocks.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2267
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rtel [Fri, 20 Jun 2014 20:15:20 +0000 (20:15 +0000)]
Update FreeRTOS+ components and demos to use typedef names introduced in FreeRTOS V8.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2266
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rtel [Mon, 16 Jun 2014 13:07:01 +0000 (13:07 +0000)]
Update timer demo in PIC32MZ demo to remove multiple extern definition created by adding in the macro that checks non ISR safe functions are not called from ISRs.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2265
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rtel [Mon, 16 Jun 2014 12:55:50 +0000 (12:55 +0000)]
Implementation of mutex held counting in tasks.c - needs optimisation before release.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2264
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rtel [Mon, 16 Jun 2014 12:51:35 +0000 (12:51 +0000)]
Default the definition of portASSERT_IF_IN_ISR() to nothing if it is not defined.
Helper updates to allow a count of the number of mutexes held to be added.
Updates to the CCS Cortex-R4 implementation necessitated by a change in compiler semantics.
Update PIC32MX and MZ ports to assert if a non ISR safe function is called from an ISR.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2263
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rtel [Sun, 15 Jun 2014 09:24:08 +0000 (09:24 +0000)]
Add code to assert() if non ISR safe API function is called from ISR in Tasking CM4F ports - plus fix bug where the max syscall interrupt priority was used incorrectly in the Tasking CM4F port.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2262
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rtel [Sat, 14 Jun 2014 13:56:25 +0000 (13:56 +0000)]
Add code to assert() if non ISR safe API function is called from ISR in IAR and GCC CM3 and CM4F ports - Keil and tasking to follow.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2261
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rtel [Fri, 13 Jun 2014 14:08:28 +0000 (14:08 +0000)]
Simplify the assert that checks if a non-ISR safe function is called from an ISR in the GCC Cortex-A9 port.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2260
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rtel [Fri, 13 Jun 2014 14:06:43 +0000 (14:06 +0000)]
Add additional comments to the Zynq lwIP demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2259
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rtel [Thu, 12 Jun 2014 16:28:56 +0000 (16:28 +0000)]
Added portASSERT_IF_IN_INTERRUPT() macro to the GCC Cortex A9 port layer.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2258
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rtel [Thu, 12 Jun 2014 16:27:35 +0000 (16:27 +0000)]
Zynq demo: Fix Xilinx network driver by deferring the function that allocated memory from the interrupt into a task. Add DHCP option.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2257
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rtel [Tue, 10 Jun 2014 16:29:32 +0000 (16:29 +0000)]
Remove some of the lwip asserts to allow use with 64-bit alignment.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2256
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rtel [Tue, 10 Jun 2014 16:25:46 +0000 (16:25 +0000)]
Switch to using the private watchdog as the run time stats timer in the Zynq demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2255
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rtel [Mon, 9 Jun 2014 20:20:23 +0000 (20:20 +0000)]
Reorganise Zynq project after spitting lwIP example into a separate configuration.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2254
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rtel [Mon, 9 Jun 2014 19:35:08 +0000 (19:35 +0000)]
Move the Zynq's lwIP example from the Full demo into its own configuration as having the lwIP tasks at a high priority made the self checking test tasks report failures, while having the lwIP tasks at a low priority slugged the throughput.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2253
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rtel [Mon, 9 Jun 2014 12:43:18 +0000 (12:43 +0000)]
Update lwIP byte alignment to make Zynq pings more reliable.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2252
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rtel [Thu, 5 Jun 2014 12:44:38 +0000 (12:44 +0000)]
Update RL78 GCC demo application after testing with fixed compiler.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2251
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rtel [Thu, 5 Jun 2014 12:42:49 +0000 (12:42 +0000)]
Check in RL78 GCC port layer now it has been verified with the fixed compiler.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2250
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rtel [Wed, 4 Jun 2014 09:19:16 +0000 (09:19 +0000)]
Complete RX64M GCC demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2249
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rtel [Wed, 4 Jun 2014 09:17:14 +0000 (09:17 +0000)]
Reverse order of projdefs.h and FreeRTOSConfig.h includes in FreeRTOS.h to allow addition of pdMS_TO_TICKS() macro.
Update RXv2 GCC port to match RXv2 Renesas port.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2248
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rtel [Thu, 29 May 2014 13:56:16 +0000 (13:56 +0000)]
Add -nomessage command line option to RX64M demo to suppress warning about the yield function being defined when it is not called directly.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2247
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rtel [Thu, 29 May 2014 13:54:15 +0000 (13:54 +0000)]
Ensure demo app files are using FreeRTOS V8 names - a few were missed previously.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2246
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rtel [Thu, 29 May 2014 13:39:48 +0000 (13:39 +0000)]
A few additional casts to keep the Renesas RX compiler happy.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2245
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rtel [Fri, 23 May 2014 16:38:18 +0000 (16:38 +0000)]
Add lwIP driver into Zynq demo - not yet fully functional.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2244
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rtel [Fri, 23 May 2014 16:36:49 +0000 (16:36 +0000)]
Add brackets in lwIP assert statement to prevent compiler warnings.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2243
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rtel [Mon, 19 May 2014 13:14:02 +0000 (13:14 +0000)]
Add some missing volatiles to __asm statements in the CA9 GCC port.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2242
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rtel [Thu, 24 Apr 2014 14:26:36 +0000 (14:26 +0000)]
Update version number ready for release.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2240
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rtel [Thu, 24 Apr 2014 12:29:40 +0000 (12:29 +0000)]
Add xQueueGetMutexHolder() to MPU functions.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2239
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rtel [Wed, 23 Apr 2014 15:23:54 +0000 (15:23 +0000)]
Event Groups: Convert the 'clear bits from ISR' function into a pended function to fix reentrancy issue.
Event Groups: Ensure the 'wait bits' and 'sync' functions don't return values that still contain some internal control bits.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2238
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rtel [Wed, 23 Apr 2014 14:34:49 +0000 (14:34 +0000)]
Update demos that use FreeRTOS+FAT SL to have correct version numbers after the update of FreeRTOS+FAT SL itself.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2237
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rtel [Wed, 23 Apr 2014 13:59:56 +0000 (13:59 +0000)]
Update IAR XMC4200 project to fix link error that resulted from updating the IAR version to 7.x.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2236
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rtel [Wed, 23 Apr 2014 13:28:21 +0000 (13:28 +0000)]
Update FreeRTOS+FAT SL to version 1.0.1.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2235
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rtel [Wed, 9 Apr 2014 09:07:19 +0000 (09:07 +0000)]
Ensure xNewLib_reent is reclaimed when a task is deleted.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2234
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rtel [Mon, 31 Mar 2014 02:12:17 +0000 (02:12 +0000)]
Add test and correct code for the unusual case of a task using an event group to synchronise only with itself.
Add critical sections around call to prvResetNextTaskUnblockTime() that can occur from within a task.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2233
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rtel [Fri, 28 Mar 2014 14:41:15 +0000 (14:41 +0000)]
Add the pcTimerGetTimerName() API function.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2232
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rtel [Fri, 28 Mar 2014 13:05:29 +0000 (13:05 +0000)]
Add interrupt nesting test code into RX64M demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2231
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rtel [Fri, 28 Mar 2014 11:47:40 +0000 (11:47 +0000)]
Add RSK definition and LED flash tasks into RX64M demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2230
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rtel [Tue, 25 Mar 2014 17:12:31 +0000 (17:12 +0000)]
Update Cortex-A port layers to ensure the ICCRPR and ICCPMR registers are always accessed as 32-bit values.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2229
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rtel [Thu, 20 Mar 2014 12:04:49 +0000 (12:04 +0000)]
Started to create RX64M GCC project - building but not yet converted to new core.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2228
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rtel [Wed, 19 Mar 2014 16:45:53 +0000 (16:45 +0000)]
Delete old RL78 launch configurations.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2227
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rtel [Wed, 19 Mar 2014 16:44:58 +0000 (16:44 +0000)]
Add RL78/L1C configuration into e2studio demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2226
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rtel [Wed, 19 Mar 2014 13:29:11 +0000 (13:29 +0000)]
RL78/L1C configuration added to the IAR RL78 demo projects.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2225
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rtel [Fri, 7 Mar 2014 17:13:05 +0000 (17:13 +0000)]
Working but incomplete RXv2 demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2224
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rtel [Fri, 7 Mar 2014 17:12:06 +0000 (17:12 +0000)]
First pass at RXv2 port layer.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2223
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rtel [Thu, 6 Mar 2014 12:46:16 +0000 (12:46 +0000)]
RXv1 tests running before updating to RXv2.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2222
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rtel [Mon, 3 Mar 2014 16:39:41 +0000 (16:39 +0000)]
Start to create an RX64M demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2221
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rtel [Sun, 23 Feb 2014 20:01:07 +0000 (20:01 +0000)]
Cast away a few unused return types to ensure lint/compilers don't generate warnings when the warning level is high.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2220
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rtel [Wed, 19 Feb 2014 13:08:34 +0000 (13:08 +0000)]
Add extra #error message as a configuration sanity check.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2218
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rtel [Wed, 19 Feb 2014 11:58:52 +0000 (11:58 +0000)]
Minor updates to ensure all kernel aware debuggers are happy with V8.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2217
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rtel [Tue, 18 Feb 2014 14:01:57 +0000 (14:01 +0000)]
Update version number to V8.0.0 (without the release candidate number).
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2216
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rtel [Tue, 18 Feb 2014 10:10:32 +0000 (10:10 +0000)]
Add logic to determine the tick timer source and vector installation into the PIC32MZ port assembly file to allow more efficient interrupt entry.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2215
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rtel [Tue, 18 Feb 2014 10:08:33 +0000 (10:08 +0000)]
Add event group code to the PIC32MZ demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2214
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rtel [Mon, 17 Feb 2014 19:41:29 +0000 (19:41 +0000)]
Linting.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2213
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rtel [Mon, 17 Feb 2014 19:32:20 +0000 (19:32 +0000)]
Add #define INCLUDE_eTaskGetState 1 to the demos that use the int queue test.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2212
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rtel [Mon, 17 Feb 2014 15:11:16 +0000 (15:11 +0000)]
Update final demos that use the trace recorder code to use the new version.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2211
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rtel [Mon, 17 Feb 2014 14:18:00 +0000 (14:18 +0000)]
Update LPC1830 example to use the latest trace recorder code.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2210
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rtel [Mon, 17 Feb 2014 12:56:05 +0000 (12:56 +0000)]
Remove test of trace functions from the Win32/GCC build as it messes up the trace recorder.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2209
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rtel [Mon, 17 Feb 2014 12:48:18 +0000 (12:48 +0000)]
Remove test of trace functions from the Win32 build as it messes up the trace recorder.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2208
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rtel [Mon, 17 Feb 2014 12:45:56 +0000 (12:45 +0000)]
Update trace recorder to include heap tracing and new v8 features.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2207
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rtel [Sun, 16 Feb 2014 22:03:39 +0000 (22:03 +0000)]
Add event groups demo to SAM4E demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2206
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rtel [Sun, 16 Feb 2014 21:47:07 +0000 (21:47 +0000)]
Add event group tests to IAR LM3S demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2205
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rtel [Fri, 14 Feb 2014 11:07:25 +0000 (11:07 +0000)]
Make xEventGroupSetBitsFromISR() a function when configUSE_TRACE_FACILITY is enabled to allow the inclusion of a trace macro.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2204
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rtel [Tue, 11 Feb 2014 15:15:36 +0000 (15:15 +0000)]
Follow instructions on http://blogs.msdn.com/b/vsproject/archive/2009/07/21/enable-c-project-system-logging.aspx to manually prevent MSVC from incorrectly reporting the MSVC demo project as being out of date.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2203
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rtel [Tue, 11 Feb 2014 12:04:59 +0000 (12:04 +0000)]
Update the demo directory to use the version 8 type naming conventions.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2202
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rtel [Tue, 11 Feb 2014 11:38:33 +0000 (11:38 +0000)]
Replace xTaskIsTaskSuspended() call with eTaskGetState() call in IntQueue.c as the former is now a private function.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2201
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rtel [Tue, 11 Feb 2014 11:37:42 +0000 (11:37 +0000)]
Add a small amount of randomisation into the Zynq demo.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2200
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rtel [Tue, 11 Feb 2014 09:24:33 +0000 (09:24 +0000)]
Add event groups demo to Zynq demo.
Add C implementations of some standard library functions to the Zynq demo to prevent the GCC libraries (which use floating point registers as scratch registers) being linked in.
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2199
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